2 * This software is released into the public domain.
3 * See UNLICENSE file in top level directory.
10 #define VDP_DATA_PORT 0xC00000
11 #define VDP_CTRL_PORT 0xC00004
12 #define VDP_HV_COUNTER 0xC00008
14 #define TILE_MEM_END 0xB000
17 #define TILE_FONT_BASE (TILE_MEM_END - FONT_LEN * 32)
19 /* note: using ED menu's layout here.. */
20 #define WPLANE (TILE_MEM_END + 0x0000)
21 #define HSCRL (TILE_MEM_END + 0x0800)
22 #define SLIST (TILE_MEM_END + 0x0C00)
23 #define APLANE (TILE_MEM_END + 0x1000)
24 #define BPLANE (TILE_MEM_END + 0x3000)
26 #define write16_z80le(a, d) \
27 ((volatile u8 *)(a))[0] = (u8)(d), \
28 ((volatile u8 *)(a))[1] = ((d) >> 8)
30 static inline u16 read16_z80le(const void *a_)
32 volatile const u8 *a = (volatile const u8 *)a_;
33 return a[0] | ((u16)a[1] << 8);
36 #define CTL_WRITE_VRAM(adr) \
37 (((0x4000 | ((adr) & 0x3FFF)) << 16) | ((adr) >> 14) | 0x00)
38 #define CTL_WRITE_VSRAM(adr) \
39 (((0x4000 | ((adr) & 0x3FFF)) << 16) | ((adr) >> 14) | 0x10)
40 #define CTL_WRITE_CRAM(adr) \
41 (((0xC000 | ((adr) & 0x3FFF)) << 16) | ((adr) >> 14) | 0x00)
42 #define CTL_READ_VRAM(adr) \
43 (((0x0000 | ((adr) & 0x3FFF)) << 16) | ((adr) >> 14) | 0x00)
44 #define CTL_READ_VSRAM(adr) \
45 (((0x0000 | ((adr) & 0x3FFF)) << 16) | ((adr) >> 14) | 0x10)
46 #define CTL_READ_CRAM(adr) \
47 (((0x0000 | ((adr) & 0x3FFF)) << 16) | ((adr) >> 14) | 0x20)
49 #define CTL_WRITE_DMA 0x80
51 #define VDP_setReg(r, v) \
52 write16(VDP_CTRL_PORT, 0x8000 | ((r) << 8) | ((v) & 0xff))
57 VDP_NT_SCROLLA = 0x02,
59 VDP_NT_SCROLLB = 0x04,
74 #define VDP_MODE1_PS 0x04
75 #define VDP_MODE1_IE1 0x10 // h int
76 #define VDP_MODE2_MD 0x04
77 #define VDP_MODE2_PAL 0x08 // 30 col
78 #define VDP_MODE2_DMA 0x10
79 #define VDP_MODE2_IE0 0x20 // v int
80 #define VDP_MODE2_DISP 0x40
81 #define VDP_MODE2_128K 0x80
83 #define SR_PAL (1 << 0)
84 #define SR_DMA (1 << 1)
85 #define SR_HB (1 << 2)
86 #define SR_VB (1 << 3)
87 #define SR_ODD (1 << 4)
89 #define SR_SOVR (1 << 6)
91 #define SR_FULL (1 << 8)
92 #define SR_EMPT (1 << 9)
95 #define LEFT_BORDER 1 /* lame TV */
101 extern const u32 font_base[];
102 extern const u8 z80_test[];
103 extern const u8 z80_test_end[];
107 static noinline void VDP_drawTextML(const char *str, u16 plane_base,
110 const u8 *src = (const u8 *)str;
111 u16 basetile = text_pal << 13;
112 int max_len = 40 - LEFT_BORDER;
118 for (len = 0; str[len] && len < max_len; len++)
120 if (len > (PLANE_W - x))
123 addr = plane_base + ((x + (PLANE_W * y)) << 1);
124 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(addr));
127 write16(VDP_DATA_PORT,
128 basetile | ((*src++) - 32 + TILE_FONT_BASE / 32));
132 static int printf_ypos;
134 static void printf_line(int x, const char *buf)
139 VDP_drawTextML(buf, APLANE, x, printf_ypos++ & (PLANE_H - 1));
141 if (printf_ypos >= CSCREEN_H) {
142 /* clear next line */
144 addr += (PLANE_W * (printf_ypos & (PLANE_H - 1))) << 1;
145 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(addr));
146 for (i = 0; i < 40 / 2; i++)
147 write32(VDP_DATA_PORT, 0);
150 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0));
151 write16(VDP_DATA_PORT, (printf_ypos - CSCREEN_H + 1) * 8);
155 #define PRINTF_LEN 40
157 static int printf_xpos;
159 static noinline int printf(const char *fmt, ...)
161 static const char hexchars[] = "0123456789abcdef";
162 char c, buf[PRINTF_LEN + 11 + 1];
171 for (d = 0; *fmt; ) {
182 printf_line(printf_xpos, buf);
198 while ('1' <= *fmt && *fmt <= '9') {
199 fwidth = fwidth * 10 + *fmt - '0';
209 ival = va_arg(ap, int);
214 for (i = 1000000000; i >= 10; i /= 10)
217 for (; i >= 10; i /= 10) {
218 buf[d++] = '0' + ival / i;
221 buf[d++] = '0' + ival;
224 uval = va_arg(ap, int);
225 while (fwidth > 1 && uval < (1 << (fwidth - 1) * 4)) {
226 buf[d++] = prefix0 ? '0' : ' ';
229 for (j = 1; j < 8 && uval >= (1 << j * 4); j++)
231 for (j--; j >= 0; j--)
232 buf[d++] = hexchars[(uval >> j * 4) & 0x0f];
235 s = va_arg(ap, char *);
236 while (*s && d < PRINTF_LEN)
240 // don't handle, for now
251 VDP_drawTextML(buf, APLANE, printf_xpos,
252 printf_ypos & (PLANE_H - 1));
259 static const char *exc_names[] = {
264 "Illegal Instruction",
268 "Privilege Violation", /* 8 8 */
270 "Line 1010 Emulator",
271 "Line 1111 Emulator",
275 "Uninitialized Interrupt",
284 "Spurious Interrupt", /* 18 24 */
297 u16 ecxnum; // from handler
309 } bae _packed; // bus/address error frame
313 void exception(const struct exc_frame *f)
318 while (read16(VDP_CTRL_PORT) & 2)
320 VDP_setReg(VDP_MODE1, VDP_MODE1_PS);
321 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DISP);
323 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0));
324 write16(VDP_DATA_PORT,
325 printf_ypos >= CSCREEN_H ?
326 (printf_ypos - CSCREEN_H + 1) * 8 : 0);
328 printf("exception %i ", f->ecxnum);
329 if (f->ecxnum < ARRAY_SIZE(exc_names) && exc_names[f->ecxnum] != NULL)
330 printf("(%s)", exc_names[f->ecxnum]);
332 printf(" (%s)", (f->bae.fc & 0x10) ? "r" : "w");
336 printf(" PC: %08x SR: %04x \n", f->bae.pc, f->bae.sr);
337 printf("addr: %08x IR: %04x FC: %02x \n",
338 f->bae.addr, f->bae.ir, f->bae.fc);
342 printf(" PC: %08x SR: %04x \n", f->g.pc, f->g.sr);
345 for (i = 0; i < 8; i++)
346 printf(" D%d: %08x A%d: %08x \n", i, f->dr[i], i, f->ar[i]);
348 sp = (u32 *)(f->ar[7] + sp_add);
349 printf(" %08x %08x %08x %08x\n", sp[0], sp[1], sp[2], sp[3]);
350 printf(" %08x %08x %08x %08x\n", sp[4], sp[5], sp[6], sp[7]);
355 static void setup_default_palette(void)
357 write32(VDP_CTRL_PORT, CTL_WRITE_CRAM(0));
358 write32(VDP_DATA_PORT, 0);
359 write32(VDP_CTRL_PORT, CTL_WRITE_CRAM(15 * 2)); // font normal
360 write16(VDP_DATA_PORT, 0xeee);
361 write32(VDP_CTRL_PORT, CTL_WRITE_CRAM(31 * 2)); // green
362 write16(VDP_DATA_PORT, 0x0e0);
363 write32(VDP_CTRL_PORT, CTL_WRITE_CRAM(47 * 2)); // red
364 write16(VDP_DATA_PORT, 0x00e);
367 static void do_setup_dma(const void *src_, u16 words)
370 // VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA);
371 VDP_setReg(VDP_DMA_LEN0, words);
372 VDP_setReg(VDP_DMA_LEN1, words >> 8);
373 VDP_setReg(VDP_DMA_SRC0, src >> 1);
374 VDP_setReg(VDP_DMA_SRC1, src >> 9);
375 VDP_setReg(VDP_DMA_SRC2, src >> 17);
376 // write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(addr) | CTL_WRITE_DMA);
379 static void vdp_wait_for_fifo_empty(void)
381 while (!(read16(VDP_CTRL_PORT) & 0x200))
382 /* fifo not empty */;
385 static void vdp_wait_for_dma_idle(void)
387 while (read16(VDP_CTRL_PORT) & 2)
391 static void vdp_wait_for_line_0(void)
393 // in PAL vcounter reports 0 twice in a frame,
394 // so wait for vblank to clear first
395 while (!(read16(VDP_CTRL_PORT) & 8))
397 while (read16(VDP_CTRL_PORT) & 8)
399 while (read8(VDP_HV_COUNTER) != 0)
403 static void t_dma_zero_wrap_early(void)
405 const u32 *src = (const u32 *)0x3c0000;
406 u32 *ram = (u32 *)0xff0000;
408 do_setup_dma(src + 4, 2);
409 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0) | CTL_WRITE_DMA);
410 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0) | CTL_WRITE_DMA);
412 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0));
413 ram[0] = read32(VDP_DATA_PORT);
414 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0xfffc));
415 ram[1] = read32(VDP_DATA_PORT);
418 static void t_dma_zero_fill_early(void)
420 u32 *ram = (u32 *)0xff0000;
422 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0));
423 write32(VDP_DATA_PORT, 0);
424 write32(VDP_DATA_PORT, 0);
425 write32(VDP_DATA_PORT, 0);
426 write32(VDP_DATA_PORT, 0);
428 VDP_setReg(VDP_AUTOINC, 1);
429 VDP_setReg(VDP_DMA_SRC2, 0x80);
430 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(1) | CTL_WRITE_DMA);
431 write16(VDP_DATA_PORT, 0x1122);
432 ram[2] = read16(VDP_CTRL_PORT);
433 vdp_wait_for_dma_idle();
435 VDP_setReg(VDP_AUTOINC, 2);
436 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0));
437 ram[3] = read32(VDP_DATA_PORT);
440 #define expect(ok_, v0_, v1_) \
441 if ((v0_) != (v1_)) { \
442 printf("%s: %08x %08x\n", #v0_, v0_, v1_); \
446 #define expect_range(ok_, v0_, vmin_, vmax_) \
447 if ((v0_) < (vmin_) || (v0_) > (vmax_)) { \
448 printf("%s: %02x /%02x-%02x\n", #v0_, v0_, vmin_, vmax_); \
452 #define expect_bits(ok_, v0_, val_, mask_) \
453 if (((v0_) & (mask_)) != (val_)) { \
454 printf("%s: %04x & %04x != %04x\n", #v0_, v0_, mask_, val_); \
458 static int t_dma_zero_wrap(void)
460 const u32 *src = (const u32 *)0x3c0000;
461 const u32 *ram = (const u32 *)0xff0000;
464 expect(ok, ram[0], src[5 + 0x10000/4]);
465 expect(ok, ram[1], src[4]);
469 static int t_dma_zero_fill(void)
471 const u32 *ram = (const u32 *)0xff0000;
476 expect(ok, ram[3], 0x11111111);
480 static int t_dma_ram_wrap(void)
482 u32 *ram = (u32 *)0xff0000;
486 saved = read32(&ram[0x10000/4 - 1]);
487 ram[0x10000/4 - 1] = 0x01020304;
489 do_setup_dma(&ram[0x10000/4 - 1], 4);
491 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100) | CTL_WRITE_DMA);
494 write32(&ram[0x10000/4 - 1], saved);
496 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100));
497 v0 = read32(VDP_DATA_PORT);
498 v1 = read32(VDP_DATA_PORT);
500 expect(ok, v0, 0x01020304);
501 expect(ok, v1, 0x05060708);
505 // test no src reprogram, only len0
506 static int t_dma_multi(void)
508 const u32 *src = (const u32 *)0x3c0000;
512 do_setup_dma(src, 2);
513 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100) | CTL_WRITE_DMA);
514 VDP_setReg(VDP_DMA_LEN0, 2);
515 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x104) | CTL_WRITE_DMA);
517 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100));
518 v0 = read32(VDP_DATA_PORT);
519 v1 = read32(VDP_DATA_PORT);
521 expect(ok, v0, src[0]);
522 expect(ok, v1, src[1]);
526 static int t_dma_cram_wrap(void)
528 u32 *ram = (u32 *)0xff0000;
532 write32(VDP_CTRL_PORT, CTL_WRITE_CRAM(0));
533 write32(VDP_DATA_PORT, 0);
538 do_setup_dma(ram, 4);
539 write32(VDP_CTRL_PORT, CTL_WRITE_CRAM(0x7c | 0xff81) | CTL_WRITE_DMA);
541 write32(VDP_CTRL_PORT, CTL_READ_CRAM(0x7c));
542 v0 = read32(VDP_DATA_PORT) & 0x0eee0eee;
543 write32(VDP_CTRL_PORT, CTL_READ_CRAM(0));
544 v1 = read32(VDP_DATA_PORT) & 0x0eee0eee;
546 setup_default_palette();
548 expect(ok, v0, ram[0]);
549 expect(ok, v1, ram[1]);
553 static int t_dma_vsram_wrap(void)
555 u32 *ram32 = (u32 *)0xff0000;
556 u16 *ram16 = (u16 *)0xff0000;
561 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0));
562 write32(VDP_DATA_PORT, 0);
564 for (i = 0; i < 0x48/2; i++)
567 do_setup_dma(ram16, 0x48/2);
568 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0x3c | 0xff81) | CTL_WRITE_DMA);
570 write32(VDP_CTRL_PORT, CTL_READ_VSRAM(0x3c));
571 v0 = read32(VDP_DATA_PORT) & 0x03ff03ff;
572 write32(VDP_CTRL_PORT, CTL_READ_VSRAM(0));
573 v1 = read32(VDP_DATA_PORT) & 0x03ff03ff;
575 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0));
576 write32(VDP_DATA_PORT, 0);
578 expect(ok, v0, ram32[0]);
579 expect(ok, v1, ram32[0x48/4 - 1]);
583 static int t_dma_and_data(void)
585 const u32 *src = (const u32 *)0x3c0000;
589 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
590 write32(VDP_DATA_PORT, 0);
592 do_setup_dma(src, 2);
593 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0xfc) | CTL_WRITE_DMA);
594 write32(VDP_DATA_PORT, 0x5ec8a248);
596 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0xfc));
597 v0 = read32(VDP_DATA_PORT);
598 v1 = read32(VDP_DATA_PORT);
600 expect(ok, v0, src[0]);
601 expect(ok, v1, 0x5ec8a248);
605 static int t_dma_short_cmd(void)
607 const u32 *src = (const u32 *)0x3c0000;
611 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x3ff4));
612 write32(VDP_DATA_PORT, 0x10111213);
613 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0xfff0));
614 write32(VDP_DATA_PORT, 0x20212223);
615 write32(VDP_DATA_PORT, 0x30313233);
616 vdp_wait_for_fifo_empty();
618 do_setup_dma(src, 2);
619 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0xfff0) | CTL_WRITE_DMA);
620 write16(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x3ff4) >> 16);
621 write32(VDP_DATA_PORT, 0x40414243);
623 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x3ff4));
624 v0 = read32(VDP_DATA_PORT);
625 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0xfff0));
626 v1 = read32(VDP_DATA_PORT);
627 v2 = read32(VDP_DATA_PORT);
629 expect(ok, v0, 0x10111213);
630 expect(ok, v1, src[0]);
631 expect(ok, v2, 0x40414243);
635 static int t_dma_fill3_odd(void)
640 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
641 write32(VDP_DATA_PORT, 0);
642 write32(VDP_DATA_PORT, 0);
643 write32(VDP_DATA_PORT, 0);
644 vdp_wait_for_fifo_empty();
646 VDP_setReg(VDP_AUTOINC, 3);
647 VDP_setReg(VDP_DMA_LEN0, 3);
648 VDP_setReg(VDP_DMA_SRC2, 0x80);
649 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x101) | CTL_WRITE_DMA);
650 write16(VDP_DATA_PORT, 0x1122);
651 vdp_wait_for_dma_idle();
653 VDP_setReg(VDP_AUTOINC, 2);
654 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100));
655 v0 = read32(VDP_DATA_PORT);
656 v1 = read32(VDP_DATA_PORT);
657 v2 = read32(VDP_DATA_PORT);
659 expect(ok, v0, 0x22110000);
660 expect(ok, v1, 0x00111100);
661 expect(ok, v2, 0x00000011);
665 static int t_dma_fill3_even(void)
670 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
671 write32(VDP_DATA_PORT, 0);
672 write32(VDP_DATA_PORT, 0);
673 write32(VDP_DATA_PORT, 0);
674 vdp_wait_for_fifo_empty();
676 VDP_setReg(VDP_AUTOINC, 3);
677 VDP_setReg(VDP_DMA_LEN0, 3);
678 VDP_setReg(VDP_DMA_SRC2, 0x80);
679 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100) | CTL_WRITE_DMA);
680 write16(VDP_DATA_PORT, 0x1122);
681 vdp_wait_for_dma_idle();
683 VDP_setReg(VDP_AUTOINC, 2);
684 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100));
685 v0 = read32(VDP_DATA_PORT);
686 v1 = read32(VDP_DATA_PORT);
687 v2 = read32(VDP_DATA_PORT);
689 expect(ok, v0, 0x11221100);
690 expect(ok, v1, 0x00000011);
691 expect(ok, v2, 0x11000000);
695 static unused int t_dma_fill3_vsram(void)
700 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0));
701 write32(VDP_DATA_PORT, 0);
702 write32(VDP_DATA_PORT, 0);
703 write32(VDP_DATA_PORT, 0);
705 write16(VDP_DATA_PORT, 0x0111);
706 write16(VDP_DATA_PORT, 0x0222);
707 write16(VDP_DATA_PORT, 0x0333);
708 vdp_wait_for_fifo_empty();
710 VDP_setReg(VDP_AUTOINC, 3);
711 VDP_setReg(VDP_DMA_LEN0, 3);
712 VDP_setReg(VDP_DMA_SRC2, 0x80);
713 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(1) | CTL_WRITE_DMA);
714 write16(VDP_DATA_PORT, 0x0102);
715 vdp_wait_for_dma_idle();
717 VDP_setReg(VDP_AUTOINC, 2);
718 write32(VDP_CTRL_PORT, CTL_READ_VSRAM(0));
719 v0 = read32(VDP_DATA_PORT);
720 v1 = read32(VDP_DATA_PORT);
721 v2 = read32(VDP_DATA_PORT);
723 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0));
724 write32(VDP_DATA_PORT, 0);
726 expect(ok, v0, 0x01020000);
727 expect(ok, v1, 0x01110111);
728 expect(ok, v2, 0x00000111);
732 static int t_dma_fill_dis(void)
737 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
738 write32(VDP_DATA_PORT, 0);
739 write32(VDP_DATA_PORT, 0);
741 VDP_setReg(VDP_DMA_LEN0, 1);
742 VDP_setReg(VDP_DMA_SRC2, 0x80);
743 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100) | CTL_WRITE_DMA);
744 VDP_setReg(VDP_MODE2, VDP_MODE2_MD);
745 write16(VDP_DATA_PORT, 0x1122);
746 vdp_wait_for_dma_idle();
748 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
749 write16(VDP_DATA_PORT, 0x3344);
750 vdp_wait_for_dma_idle();
752 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100));
753 v0 = read32(VDP_DATA_PORT);
754 v1 = read32(VDP_DATA_PORT);
761 static int t_dma_fill_src(void)
763 const u32 *src = (const u32 *)0x3c0000;
767 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
768 write32(VDP_DATA_PORT, 0);
770 // do_setup_dma(src, 2); // hang, can't write src2 twice
771 VDP_setReg(VDP_DMA_LEN0, 2);
772 VDP_setReg(VDP_DMA_SRC0, (u32)src >> 1);
773 VDP_setReg(VDP_DMA_SRC1, (u32)src >> 9);
774 VDP_setReg(VDP_DMA_SRC2, 0x80);
775 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100) | CTL_WRITE_DMA);
776 write16(VDP_DATA_PORT, 0x1122);
777 vdp_wait_for_dma_idle();
779 VDP_setReg(VDP_DMA_LEN0, 2);
780 VDP_setReg(VDP_DMA_SRC2, (u32)src >> 17);
781 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x104) | CTL_WRITE_DMA);
783 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100));
784 v0 = read32(VDP_DATA_PORT);
785 v1 = read32(VDP_DATA_PORT);
787 expect(ok, v0, 0x11220011);
788 expect(ok, v1, src[1]);
792 // (((a & 2) >> 1) ^ 1) | ((a & $400) >> 9) | (a & $3FC) | ((a & $1F800) >> 1)
793 static int t_dma_128k(void)
795 u16 *ram = (u16 *)0xff0000;
803 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
804 write32(VDP_DATA_PORT, 0x01020304);
805 write32(VDP_DATA_PORT, 0x05060708);
806 vdp_wait_for_fifo_empty();
809 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_128K);
810 do_setup_dma(ram, 3);
811 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100) | CTL_WRITE_DMA);
812 vdp_wait_for_fifo_empty();
814 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
815 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100));
816 v0 = read32(VDP_DATA_PORT);
817 v1 = read32(VDP_DATA_PORT);
819 expect(ok, v0, 0x22110304);
820 expect(ok, v1, 0x05330708);
824 static int t_vdp_128k_b16(void)
829 VDP_setReg(VDP_AUTOINC, 0);
830 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x8100));
831 write32(VDP_DATA_PORT, 0x01020304);
832 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x10100));
833 write32(VDP_DATA_PORT, 0x05060708);
834 vdp_wait_for_fifo_empty();
836 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_128K);
837 write16(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100) >> 16); // note: upper cmd
838 write32(VDP_DATA_PORT, 0x11223344);
839 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x10102));
840 write32(VDP_DATA_PORT, 0x55667788);
841 vdp_wait_for_fifo_empty();
843 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
844 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x8100));
845 v0 = read16(VDP_DATA_PORT);
846 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x0100));
847 v1 = read16(VDP_DATA_PORT);
849 VDP_setReg(VDP_AUTOINC, 2);
851 expect(ok, v0, 0x8844);
852 expect(ok, v1, 0x0708);
856 static unused int t_vdp_128k_b16_inc(void)
861 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0));
862 write32(VDP_DATA_PORT, 0x01020304);
863 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x8000));
864 write32(VDP_DATA_PORT, 0x05060708);
865 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0xfffe));
866 write32(VDP_DATA_PORT, 0x090a0b0c);
867 vdp_wait_for_fifo_empty();
869 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_128K);
870 write16(VDP_CTRL_PORT, CTL_WRITE_VRAM(0) >> 16); // note: upper cmd
871 write16(VDP_DATA_PORT, 0x1122);
872 vdp_wait_for_fifo_empty();
874 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
875 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0));
876 v0 = read32(VDP_DATA_PORT);
877 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x8000));
878 v1 = read32(VDP_DATA_PORT);
879 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0));
880 write32(VDP_DATA_PORT, 0);
881 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x8000));
882 write32(VDP_DATA_PORT, 0);
884 expect(ok, v0, 0x0b0c0304); // XXX: no 22 anywhere?
885 expect(ok, v1, 0x05060708);
889 static int t_vdp_reg_cmd(void)
894 VDP_setReg(VDP_AUTOINC, 0);
895 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
896 write32(VDP_DATA_PORT, 0x01020304);
897 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
898 write32(VDP_DATA_PORT, 0x05060708);
900 VDP_setReg(VDP_AUTOINC, 2);
901 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x0100));
902 v0 = read16(VDP_DATA_PORT);
904 expect(ok, v0, 0x0304);
908 static int t_vdp_sr_vb(void)
913 while (read8(VDP_HV_COUNTER) != 242)
915 sr[0] = read16(VDP_CTRL_PORT);
916 VDP_setReg(VDP_MODE2, VDP_MODE2_MD);
917 sr[1] = read16(VDP_CTRL_PORT);
918 while (read8(VDP_HV_COUNTER) != 4)
920 sr[2] = read16(VDP_CTRL_PORT);
921 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
922 sr[3] = read16(VDP_CTRL_PORT);
924 expect_bits(ok, sr[0], SR_VB, SR_VB);
925 expect_bits(ok, sr[1], SR_VB, SR_VB);
926 expect_bits(ok, sr[2], SR_VB, SR_VB);
927 expect_bits(ok, sr[3], 0, SR_VB);
931 /* z80 tests assume busreq state */
932 static int t_z80mem_long_mirror(void)
934 u8 *zram = (u8 *)0xa00000;
937 write8(&zram[0x1100], 0x11);
938 write8(&zram[0x1101], 0x22);
939 write8(&zram[0x1102], 0x33);
940 write8(&zram[0x1103], 0x44);
942 write32(&zram[0x3100], 0x55667788);
945 expect(ok, zram[0x1100], 0x55);
946 expect(ok, zram[0x1101], 0x22);
947 expect(ok, zram[0x1102], 0x77);
948 expect(ok, zram[0x1103], 0x44);
952 static int t_z80mem_noreq_w(void)
954 u8 *zram = (u8 *)0xa00000;
957 write8(&zram[0x1100], 0x11);
959 write16(0xa11100, 0x000);
960 write8(&zram[0x1100], 0x22);
963 write16(0xa11100, 0x100);
964 while (read16(0xa11100) & 0x100)
967 expect(ok, zram[0x1100], 0x11);
971 #define Z80_CP_CYCLES(b) (118 + ((b) - 1) * 21 + 26 + 17)
973 static int t_z80mem_vdp_r(void)
975 u8 *zram = (u8 *)0xa00000;
978 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
979 write32(VDP_DATA_PORT, 0x11223344);
980 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100));
982 zram[0x1000] = 1; // cp
983 write16_z80le(&zram[0x1002], 0x7f00); // src
984 write16_z80le(&zram[0x1004], 0x1100); // dst
985 write16_z80le(&zram[0x1006], 2); // len
986 zram[0x1100] = zram[0x1101] = zram[0x1102] = 0x5a;
988 write16(0xa11100, 0x000);
989 burn10(Z80_CP_CYCLES(2) * 15 / 7 * 2 / 10);
991 write16(0xa11100, 0x100);
992 while (read16(0xa11100) & 0x100)
995 expect(ok, zram[0x1000], 0);
996 expect(ok, zram[0x1100], 0x11);
997 expect(ok, zram[0x1101], 0x44);
998 expect(ok, zram[0x1102], 0x5a);
1002 static unused int t_z80mem_vdp_w(void)
1004 u8 *zram = (u8 *)0xa00000;
1008 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
1009 write32(VDP_DATA_PORT, 0x11223344);
1010 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
1011 vdp_wait_for_fifo_empty();
1013 zram[0x1000] = 1; // cp
1014 write16_z80le(&zram[0x1002], 0x1100); // src
1015 write16_z80le(&zram[0x1004], 0x7f00); // dst
1016 write16_z80le(&zram[0x1006], 2); // len
1017 zram[0x1100] = 0x55;
1018 zram[0x1101] = 0x66;
1020 write16(0xa11100, 0x000);
1021 burn10(Z80_CP_CYCLES(2) * 15 / 7 * 2 / 10);
1023 write16(0xa11100, 0x100);
1024 while (read16(0xa11100) & 0x100)
1027 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100));
1028 v0 = read32(VDP_DATA_PORT);
1030 expect(ok, zram[0x1000], 0);
1031 expect(ok, v0, 0x55556666);
1035 static int t_tim_loop(void)
1040 vdp_wait_for_line_0();
1042 vcnt = read8(VDP_HV_COUNTER);
1045 //expect_range(ok, vcnt, 0x80, 0x80);
1046 expect(ok, vcnt, 223);
1050 #define Z80_RD_V_CYCLES(b) (132 + (b) * 38 + 50 + 17)
1053 static void z80_read_loop(u8 *zram, u16 src)
1055 const int pairs = 512 + 256;
1057 zram[0x1000] = 2; // read loop, save vcnt
1058 write16_z80le(&zram[0x1002], src); // src
1059 write16_z80le(&zram[0x1004], 0x1100); // vcnt dst
1060 write16_z80le(&zram[0x1006], pairs); // reads/2
1064 vdp_wait_for_line_0();
1065 write16(0xa11100, 0x000);
1066 burn10(Z80_RD_V_CYCLES(pairs) * 15 / 7 * 4 / 10);
1068 write16(0xa11100, 0x100);
1069 while (read16(0xa11100) & 0x100)
1073 static int t_tim_z80_ram(void)
1075 u8 *zram = (u8 *)0xa00000;
1078 z80_read_loop(zram, 0);
1080 expect(ok, zram[0x1000], 0);
1081 expect_range(ok, zram[0x1100], 0x80, 0x80);
1085 static int t_tim_z80_ym(void)
1087 u8 *zram = (u8 *)0xa00000;
1090 z80_read_loop(zram, 0x4000);
1092 expect(ok, zram[0x1000], 0);
1093 expect_range(ok, zram[0x1100], 0x80, 0x80);
1097 static int t_tim_z80_vdp(void)
1099 u8 *zram = (u8 *)0xa00000;
1102 z80_read_loop(zram, 0x7f08);
1104 expect(ok, zram[0x1000], 0);
1105 expect_range(ok, zram[0x1100], 0x91, 0x91);
1109 static int t_tim_z80_bank_rom(void)
1111 u8 *zram = (u8 *)0xa00000;
1114 for (i = 0; i < 17; i++)
1115 write8(0xa06000, 0); // bank 0
1117 z80_read_loop(zram, 0x8000);
1119 expect(ok, zram[0x1000], 0);
1120 expect_range(ok, zram[0x1100], 0x95, 0x96);
1124 /* borderline too slow */
1126 static void test_vcnt_vb(void)
1128 const u32 *srhv = (u32 *)0xc00006; // to read SR and HV counter
1129 u32 *ram = (u32 *)0xff0000;
1130 u16 vcnt, vcnt_expect = 0;
1134 vdp_wait_for_line_0();
1139 vcnt = val & 0xff00;
1140 if (vcnt == vcnt_expect)
1143 if (vcnt == 0 && !(sr & SR_VB)) // not VB
1144 break; // wrapped to start of frame
1146 vcnt_expect += 0x100;
1147 if (vcnt == vcnt_expect && !((sr ^ (old >> 16)) & SR_VB)) {
1151 // should have a vcnt jump here
1163 static int t_tim_vcnt(void)
1165 const u32 *ram32 = (u32 *)0xff0000;
1166 const u8 *ram = (u8 *)0xff0000;
1167 u8 pal = read8(0xa10001) & 0x40;
1168 u8 vc_jmp_b = pal ? 0x02 : 0xea;
1169 u8 vc_jmp_a = pal ? 0xca : 0xe5;
1170 u16 lines = pal ? 313 : 262;
1174 expect(ok, ram[0*4+2], 0); // line 0
1175 expect_bits(ok, ram[0*4+1], 0, SR_VB);
1176 expect(ok, ram[1*4+2], 223); // last no blank
1177 expect_bits(ok, ram[1*4+1], 0, SR_VB);
1178 expect(ok, ram[2*4+2], 224); // 1st blank
1179 expect_bits(ok, ram[2*4+1], SR_VB, SR_VB);
1180 expect(ok, ram[3*4+2], vc_jmp_b); // before jump
1181 expect_bits(ok, ram[3*4+1], SR_VB, SR_VB);
1182 expect(ok, ram[4*4+2], vc_jmp_a); // after jump
1183 expect_bits(ok, ram[4*4+1], SR_VB, SR_VB);
1184 expect(ok, ram[5*4+2], 0xfe); // before vb clear
1185 expect_bits(ok, ram[5*4+1], SR_VB, SR_VB);
1186 expect(ok, ram[6*4+2], 0xff); // after vb clear
1187 expect_bits(ok, ram[6*4+1], 0, SR_VB);
1188 expect(ok, ram[7*4+2], 0); // next line 0
1189 expect_bits(ok, ram[7*4+1], 0, SR_VB);
1190 expect(ok, ram32[8], lines - 1);
1194 static int t_tim_hblank_h40(void)
1196 const u8 *r = (u8 *)0xff0000;
1202 expect_bits(ok, r[2], SR_HB, SR_HB);
1203 expect_bits(ok, r[5], SR_HB, SR_HB);
1205 expect_bits(ok, r[7], SR_HB, SR_HB);
1207 expect_bits(ok, r[12], 0, SR_HB);
1211 static int t_tim_hblank_h32(void)
1213 const u8 *r = (u8 *)0xff0000;
1216 VDP_setReg(VDP_MODE4, 0x00);
1218 VDP_setReg(VDP_MODE4, 0x81);
1220 expect_bits(ok, r[0], 0, SR_HB);
1222 expect_bits(ok, r[4], SR_HB, SR_HB);
1223 expect_bits(ok, r[5], SR_HB, SR_HB);
1225 expect_bits(ok, r[8], SR_HB, SR_HB);
1227 expect_bits(ok, r[12], 0, SR_HB);
1231 static int t_tim_vdp_as_vram_w(void)
1236 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
1237 vdp_wait_for_line_0();
1238 write16_x16(VDP_DATA_PORT, 112*18 / 16, 0);
1239 vcnt = read8(VDP_HV_COUNTER);
1242 expect(ok, vcnt, 112*2-1);
1246 static int t_tim_vdp_as_cram_w(void)
1251 write32(VDP_CTRL_PORT, CTL_WRITE_CRAM(0));
1252 vdp_wait_for_line_0();
1253 write16_x16(VDP_DATA_PORT, 112*18 / 16, 0);
1254 vcnt = read8(VDP_HV_COUNTER);
1257 setup_default_palette();
1259 expect(ok, vcnt, 112);
1272 static int t_irq_hint(void)
1274 struct irq_test *it = (void *)0xfff000;
1277 // for more fun, disable the display
1278 VDP_setReg(VDP_MODE2, VDP_MODE2_MD);
1280 it->cnt = it->first.hv = it->last.hv = 0;
1281 memcpy_((void *)0xff0100, test_hint, test_hint_end - test_hint);
1283 while (read8(VDP_HV_COUNTER) != 100)
1285 while (read8(VDP_HV_COUNTER) != 229)
1287 // take the pending irq
1288 VDP_setReg(VDP_MODE1, VDP_MODE1_PS | VDP_MODE1_IE1);
1290 burn10(488 * 2 / 10);
1292 expect(ok, it->first.v, 229); // pending irq trigger
1293 expect(ok, it->cnt, 1);
1296 it->cnt = it->first.hv = it->last.hv = 0;
1298 while (read8(VDP_HV_COUNTER) != 4)
1300 while (read8(VDP_HV_COUNTER) != 228)
1303 expect(ok, it->cnt, 225);
1304 expect(ok, it->first.v, 0);
1305 expect(ok, it->last.v, 224);
1307 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
1309 // detect reload line
1310 it->cnt = it->first.hv = it->last.hv = 0;
1313 while (read16(VDP_CTRL_PORT) & 8)
1315 VDP_setReg(10, 255);
1316 while (read8(VDP_HV_COUNTER) != 228)
1319 expect(ok, it->cnt, 1);
1320 expect(ok, it->first.v, 17);
1321 expect(ok, it->last.v, 17);
1323 VDP_setReg(VDP_MODE1, VDP_MODE1_PS);
1328 static int t_irq_both_cpu_unmask(void)
1330 struct irq_test *ith = (void *)0xfff000;
1331 struct irq_test *itv = ith + 1;
1335 memset_(ith, 0, sizeof(*ith) * 2);
1336 memcpy_((void *)0xff0100, test_hint, test_hint_end - test_hint);
1337 memcpy_((void *)0xff0140, test_vint, test_vint_end - test_vint);
1339 while (read8(VDP_HV_COUNTER) != 100)
1341 while (read8(VDP_HV_COUNTER) != 226)
1344 VDP_setReg(VDP_MODE1, VDP_MODE1_PS | VDP_MODE1_IE1);
1345 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_IE0 | VDP_MODE2_DISP);
1346 /* go to active display line 100 */
1347 while (read8(VDP_HV_COUNTER) != 100)
1349 s0 = read16(VDP_CTRL_PORT);
1350 s1 = move_sr_and_read(0x2000, VDP_CTRL_PORT);
1352 VDP_setReg(VDP_MODE1, VDP_MODE1_PS);
1353 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
1355 expect(ok, itv->cnt, 1); // vint count
1356 expect(ok, itv->first.v, 100); // vint line
1357 expect(ok, ith->cnt, 1); // hint count
1358 expect(ok, ith->first.v, 100); // hint line
1359 expect_bits(ok, s0, SR_F, SR_F);
1360 expect_bits(ok, s1, 0, SR_F);
1364 static int t_irq_ack_v_h(void)
1366 struct irq_test *ith = (void *)0xfff000;
1367 struct irq_test *itv = ith + 1;
1371 memset_(ith, 0, sizeof(*ith) * 2);
1372 memcpy_((void *)0xff0100, test_hint, test_hint_end - test_hint);
1373 memcpy_((void *)0xff0140, test_vint, test_vint_end - test_vint);
1375 /* ensure hcnt reload */
1376 while (!(read16(VDP_CTRL_PORT) & 8))
1378 while (read16(VDP_CTRL_PORT) & 8)
1380 VDP_setReg(VDP_MODE1, VDP_MODE1_PS | VDP_MODE1_IE1);
1381 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_IE0);
1382 while (read8(VDP_HV_COUNTER) != 100)
1384 while (read8(VDP_HV_COUNTER) != 226)
1386 s0 = read16(VDP_CTRL_PORT);
1387 s1 = move_sr_and_read(0x2500, VDP_CTRL_PORT);
1389 s2 = move_sr_and_read(0x2000, VDP_CTRL_PORT);
1392 VDP_setReg(VDP_MODE1, VDP_MODE1_PS);
1393 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
1395 expect(ok, itv->cnt, 1); // vint count
1396 expect(ok, itv->first.v, 226); // vint line
1397 expect(ok, ith->cnt, 1); // hint count
1398 expect(ok, ith->first.v, 228); // hint line
1399 expect_bits(ok, s0, SR_F, SR_F);
1400 expect_bits(ok, s1, 0, SR_F);
1401 expect_bits(ok, s2, 0, SR_F);
1405 static int t_irq_ack_v_h_2(void)
1407 struct irq_test *ith = (void *)0xfff000;
1408 struct irq_test *itv = ith + 1;
1412 memset_(ith, 0, sizeof(*ith) * 2);
1413 memcpy_((void *)0xff0100, test_hint, test_hint_end - test_hint);
1414 memcpy_((void *)0xff0140, test_vint, test_vint_end - test_vint);
1416 while (read8(VDP_HV_COUNTER) != 100)
1418 while (read8(VDP_HV_COUNTER) != 226)
1420 s0 = read16(VDP_CTRL_PORT);
1422 s1 = read16(VDP_CTRL_PORT);
1423 VDP_setReg(VDP_MODE1, VDP_MODE1_PS);
1424 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
1426 expect(ok, itv->cnt, 2); // vint count
1427 expect(ok, itv->first.v, 226); // vint line
1428 expect(ok, ith->cnt, 1); // hint count
1429 expect(ok, ith->first.v, 227); // hint line
1430 expect_bits(ok, s0, SR_F, SR_F);
1431 expect_bits(ok, s1, 0, SR_F);
1435 static int t_irq_ack_h_v(void)
1437 u16 *ram = (u16 *)0xfff000;
1438 u8 *ram8 = (u8 *)0xfff000;
1442 ram[0] = ram[1] = ram[2] =
1443 ram[4] = ram[5] = ram[6] = 0;
1444 memcpy_((void *)0xff0100, test_hint, test_hint_end - test_hint);
1445 memcpy_((void *)0xff0140, test_vint, test_vint_end - test_vint);
1447 while (read8(VDP_HV_COUNTER) != 100)
1449 while (read8(VDP_HV_COUNTER) != 226)
1451 s0 = read16(VDP_CTRL_PORT);
1452 VDP_setReg(VDP_MODE1, VDP_MODE1_PS | VDP_MODE1_IE1);
1455 s1 = read16(VDP_CTRL_PORT);
1456 write_and_read1(VDP_CTRL_PORT, 0x8000 | (VDP_MODE2 << 8)
1457 | VDP_MODE2_MD | VDP_MODE2_IE0, s);
1459 VDP_setReg(VDP_MODE1, VDP_MODE1_PS);
1460 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
1462 expect(ok, ram[0], 1); // hint count
1463 expect(ok, ram8[2], 226); // hint line
1464 expect(ok, ram[4], 1); // vint count
1465 expect(ok, ram8[10], 228); // vint line
1466 expect_bits(ok, s0, SR_F, SR_F);
1467 expect_bits(ok, s1, SR_F, SR_F);
1468 expect_bits(ok, s[0], SR_F, SR_F);
1469 expect_bits(ok, s[1], SR_F, SR_F);
1470 expect_bits(ok, s[2], 0, SR_F);
1471 expect_bits(ok, s[3], 0, SR_F);
1475 static int t_irq_ack_h_v_2(void)
1477 u16 *ram = (u16 *)0xfff000;
1478 u8 *ram8 = (u8 *)0xfff000;
1482 ram[0] = ram[1] = ram[2] =
1483 ram[4] = ram[5] = ram[6] = 0;
1484 memcpy_((void *)0xff0100, test_hint, test_hint_end - test_hint);
1485 memcpy_((void *)0xff0140, test_vint, test_vint_end - test_vint);
1487 while (read8(VDP_HV_COUNTER) != 100)
1489 while (read8(VDP_HV_COUNTER) != 226)
1491 s0 = read16(VDP_CTRL_PORT);
1493 s1 = read16(VDP_CTRL_PORT);
1494 VDP_setReg(VDP_MODE1, VDP_MODE1_PS);
1495 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
1497 expect(ok, ram[0], 2); // hint count
1498 expect(ok, ram8[2], 226); // hint first line
1499 expect(ok, ram8[4], 226); // hint last line
1500 expect(ok, ram[4], 0); // vint count
1501 expect(ok, ram8[10], 0); // vint line
1502 expect_bits(ok, s0, SR_F, SR_F);
1503 expect_bits(ok, s1, 0, SR_F);
1507 static void t_irq_f_flag(void)
1509 memcpy_((void *)0xff0140, test_f_vint, test_f_vint_end - test_f_vint);
1510 memset_((void *)0xff0000, 0, 10);
1511 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_IE0 | VDP_MODE2_DISP);
1513 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
1516 static int t_irq_f_flag_h40(void)
1518 u8 f, *r = (u8 *)0xff0000;
1523 expect_bits(ok, r[0], 0, SR_F);
1524 expect_bits(ok, r[1], 0, SR_F);
1525 expect_bits(ok, r[2], 0, SR_F);
1526 // hits 1-3 times in range 3-9, usually ~5
1527 f = r[3] | r[4] | r[5] | r[6] | r[7];
1529 expect_bits(ok, r[10], 0, SR_F);
1530 expect_bits(ok, r[11], 0, SR_F);
1531 expect_bits(ok, f, SR_F, SR_F);
1535 static int t_irq_f_flag_h32(void)
1537 u8 f, *r = (u8 *)0xff0000;
1540 VDP_setReg(VDP_MODE4, 0x00);
1542 VDP_setReg(VDP_MODE4, 0x81);
1544 expect_bits(ok, r[0], 0, SR_F);
1545 expect_bits(ok, r[1], 0, SR_F);
1546 // hits 1-3 times in range 2-7, usually 3
1547 f = r[2] | r[3] | r[4] | r[5] | r[6] | r[7];
1549 expect_bits(ok, r[8], 0, SR_F);
1550 expect_bits(ok, r[9], 0, SR_F);
1551 expect_bits(ok, r[10], 0, SR_F);
1552 expect_bits(ok, r[11], 0, SR_F);
1553 expect_bits(ok, f, SR_F, SR_F);
1559 static int t_32x_init(void)
1561 void (*do_32x_enable)(void) = (void *)0xff0040;
1562 u32 M_OK = MKLONG('M','_','O','K');
1563 u32 S_OK = MKLONG('S','_','O','K');
1564 u32 *r = (u32 *)0xa15100;
1565 u16 *r16 = (u16 *)r;
1568 //v1070 = read32(0x1070);
1570 /* what does REN mean exactly?
1571 * Seems to be sometimes clear after reset */
1572 for (i = 0; i < 1000000; i++)
1573 if (read16(r16) & 0x80)
1575 expect(ok, r16[0x00/2], 0x82);
1576 expect(ok, r16[0x02/2], 0);
1577 expect(ok, r16[0x04/2], 0);
1578 expect(ok, r16[0x06/2], 0);
1579 expect(ok, r[0x14/4], 0);
1580 expect(ok, r[0x18/4], 0);
1581 expect(ok, r[0x1c/4], 0);
1582 write32(&r[0x20/4], 0); // master resp
1583 write32(&r[0x24/4], 0); // slave resp
1584 write32(&r[0x28/4], 0);
1585 write32(&r[0x2c/4], 0);
1587 // could just set RV, but BIOS reads ROM, so can't
1588 memcpy_(do_32x_enable, x32x_enable,
1589 x32x_enable_end - x32x_enable);
1592 expect(ok, r16[0x00/2], 0x83);
1593 expect(ok, r16[0x02/2], 0);
1594 expect(ok, r16[0x04/2], 0);
1595 expect(ok, r16[0x06/2], 1); // RV
1596 expect(ok, r[0x14/4], 0);
1597 expect(ok, r[0x18/4], 0);
1598 expect(ok, r[0x1c/4], 0);
1599 expect(ok, r[0x20/4], M_OK);
1600 while (!read16(&r16[0x24/2]))
1602 expect(ok, r[0x24/4], S_OK);
1603 write32(&r[0x20/4], 0);
1607 static void x32_cmd(enum x32x_cmd cmd, u32 a0, u32 a1, u16 is_slave)
1609 u16 v, *r = (u16 *)0xa15120;
1610 u16 cmd_s = cmd | (is_slave << 15);
1613 write32(&r[4/2], a0);
1614 write32(&r[8/2], a1);
1618 for (i = 0; i < 10000 && (v = read16(r)) == cmd_s; i++)
1621 printf("cmd clr: %x\n", v);
1623 printf("c, e: %02x %02x\n", r[0x0c/2], r[0x0e/2]);
1628 printf("cmd err: %x\n", v);
1633 static int t_32x_echo(void)
1635 u16 *r = (u16 *)0xa15120;
1638 x32_cmd(CMD_ECHO, 0x12340000, 0, 0);
1639 expect(ok, r[0x06/2], 0x1234);
1640 x32_cmd(CMD_ECHO, 0x23450000, 0, 1);
1641 expect(ok, r[0x06/2], 0xa345);
1645 static int t_32x_md_bios(void)
1647 void (*do_call_c0)(int a, int d) = (void *)0xff0040;
1648 u8 *rmb = (u8 *)0xff0000;
1652 memcpy_(do_call_c0, test_32x_b_c0,
1653 test_32x_b_c0_end - test_32x_b_c0);
1655 do_call_c0(0xff0000, 0x5a);
1657 expect(ok, rmb[0], 0x5a);
1658 expect(ok, rl[0x04/4], 0x880200);
1659 expect(ok, rl[0x10/4], 0x880212);
1660 expect(ok, rl[0x94/4], 0x8802d8);
1664 static int t_32x_md_rom(void)
1669 expect(ok, rl[0x004/4], 0x880200);
1670 expect(ok, rl[0x100/4], 0x53454741);
1671 expect(ok, rl[0x70/4], 0);
1672 write32(&rl[0x70/4], 0xa5123456);
1673 write32(&rl[0x78/4], ~0);
1675 expect(ok, rl[0x78/4], 0x8802ae);
1676 expect(ok, rl[0x70/4], 0xa5123456);
1677 //expect(ok, rl[0x1070/4], v1070);
1678 write32(&rl[0x70/4], 0);
1679 // with RV 0x880000/0x900000 hangs, can't test
1683 static int t_32x_md_fb(void)
1685 u8 *fbb = (u8 *)0x840000;
1686 u16 *fbw = (u16 *)fbb;
1687 u32 *fbl = (u32 *)fbb;
1688 u8 *fob = (u8 *)0x860000;
1689 u16 *fow = (u16 *)fob;
1690 u32 *fol = (u32 *)fob;
1693 fbl[0] = 0x12345678;
1694 fol[1] = 0x89abcdef;
1696 expect(ok, fbw[1], 0x5678);
1697 expect(ok, fow[2], 0x89ab);
1706 expect(ok, fol[0], 0x12340000);
1707 expect(ok, fbl[1], 0x89ab0201);
1711 static int t_32x_sh_fb(void)
1713 u32 *fbl = (u32 *)0x840000;
1716 fbl[0] = 0x12345678;
1717 fbl[1] = 0x89abcdef;
1719 write8(0xa15100, 0x80); // FM=1
1720 x32_cmd(CMD_WRITE8, 0x24000000, 0, 0);
1721 x32_cmd(CMD_WRITE8, 0x24020001, 0, 0);
1722 x32_cmd(CMD_WRITE16, 0x24000002, 0, 0);
1723 x32_cmd(CMD_WRITE16, 0x24020000, 0, 0);
1724 x32_cmd(CMD_WRITE32, 0x24020004, 0x5a0000a5, 1);
1725 write8(0xa15100, 0x00); // FM=0
1727 expect(ok, fbl[0], 0x12340000);
1728 expect(ok, fbl[1], 0x5aabcda5);
1732 static int t_32x_disable(void)
1734 void (*do_32x_disable)(void) = (void *)0xff0040;
1735 u32 *r = (u32 *)0xa15100;
1736 u16 *r16 = (u16 *)r;
1740 expect(ok, r16[0x00/2], 0x83);
1742 memcpy_(do_32x_disable, x32x_disable,
1743 x32x_disable_end - x32x_disable);
1746 expect(ok, r16[0x00/2], 0x82);
1747 expect(ok, r16[0x02/2], 0);
1748 expect(ok, r16[0x04/2], 0);
1749 expect(ok, r16[0x06/2], 1); // RV
1750 expect(ok, r[0x14/4], 0);
1751 expect(ok, r[0x18/4], 0);
1752 expect(ok, r[0x1c/4], 0);
1753 expect(ok, rl[0x04/4], 0x000800);
1755 write16(&r16[0x06/2], 0); // can just set without ADEN
1757 expect(ok, r16[0x06/2], 0); // RV
1766 static const struct {
1771 { T_MD, t_dma_zero_wrap, "dma zero len + wrap" },
1772 { T_MD, t_dma_zero_fill, "dma zero len + fill" },
1773 { T_MD, t_dma_ram_wrap, "dma ram wrap" },
1774 { T_MD, t_dma_multi, "dma multi" },
1775 { T_MD, t_dma_cram_wrap, "dma cram wrap" },
1776 { T_MD, t_dma_vsram_wrap, "dma vsram wrap" },
1777 { T_MD, t_dma_and_data, "dma and data" },
1778 { T_MD, t_dma_short_cmd, "dma short cmd" },
1779 { T_MD, t_dma_fill3_odd, "dma fill3 odd" },
1780 { T_MD, t_dma_fill3_even, "dma fill3 even" },
1781 { T_MD, t_dma_fill3_vsram, "dma fill3 vsram" },
1782 { T_MD, t_dma_fill_dis, "dma fill disabled" },
1783 { T_MD, t_dma_fill_src, "dma fill src incr" },
1784 { T_MD, t_dma_128k, "dma 128k mode" },
1785 { T_MD, t_vdp_128k_b16, "vdp 128k addr bit16" },
1786 // { t_vdp_128k_b16_inc, "vdp 128k bit16 inc" }, // mystery
1787 { T_MD, t_vdp_reg_cmd, "vdp reg w cmd reset" },
1788 { T_MD, t_vdp_sr_vb, "vdp status reg vb" },
1789 { T_MD, t_z80mem_long_mirror, "z80 ram long mirror" },
1790 { T_MD, t_z80mem_noreq_w, "z80 ram noreq write" },
1791 { T_MD, t_z80mem_vdp_r, "z80 vdp read" },
1792 // { t_z80mem_vdp_w, "z80 vdp write" }, // hang
1793 { T_MD, t_tim_loop, "time loop" },
1794 { T_MD, t_tim_z80_ram, "time z80 ram" },
1795 { T_MD, t_tim_z80_ym, "time z80 ym2612" },
1796 { T_MD, t_tim_z80_vdp, "time z80 vdp" },
1797 { T_MD, t_tim_z80_bank_rom, "time z80 bank rom" },
1798 { T_MD, t_tim_vcnt, "time V counter" },
1799 { T_MD, t_tim_hblank_h40, "time hblank h40" },
1800 { T_MD, t_tim_hblank_h32, "time hblank h32" },
1801 { T_MD, t_tim_vdp_as_vram_w, "time vdp vram w" },
1802 { T_MD, t_tim_vdp_as_cram_w, "time vdp cram w" },
1803 { T_MD, t_irq_hint, "irq4 / line" },
1804 { T_MD, t_irq_both_cpu_unmask, "irq both umask" },
1805 { T_MD, t_irq_ack_v_h, "irq ack v-h" },
1806 { T_MD, t_irq_ack_v_h_2, "irq ack v-h 2" },
1807 { T_MD, t_irq_ack_h_v, "irq ack h-v" },
1808 { T_MD, t_irq_ack_h_v_2, "irq ack h-v 2" },
1809 { T_MD, t_irq_f_flag_h40, "irq f flag h40" },
1810 { T_MD, t_irq_f_flag_h32, "irq f flag h32" },
1812 // the first one enables 32X, so must be kept
1813 // all tests assume RV=1 FM=0
1814 { T_32, t_32x_init, "32x init" },
1815 { T_32, t_32x_echo, "32x echo" },
1816 { T_32, t_32x_md_bios, "32x md bios" },
1817 { T_32, t_32x_md_rom, "32x md rom" },
1818 { T_32, t_32x_md_fb, "32x md fb" },
1819 { T_32, t_32x_sh_fb, "32x sh fb" },
1820 { T_32, t_32x_disable, "32x disable" }, // must be last 32x
1823 static void setup_z80(void)
1825 u8 *zram = (u8 *)0xa00000;
1829 write16(0xa11100, 0x100);
1830 write16(0xa11200, 0x100);
1832 while (read16(0xa11100) & 0x100)
1835 // load the default test program, clear it's data
1836 len = z80_test_end - z80_test;
1837 for (i = 0; i < len; i++)
1838 write8(&zram[i], z80_test[i]);
1839 for (i = 0x1000; i < 0x1007; i++)
1840 write8(&zram[i], 0);
1843 write16(0xa11200, 0x000);
1844 write16(0xa11100, 0x000);
1846 write16(0xa11200, 0x100);
1849 // take back the bus
1850 write16(0xa11100, 0x100);
1851 while (read16(0xa11100) & 0x100)
1855 static void wait_next_vsync(void)
1857 while (read16(VDP_CTRL_PORT) & 8)
1859 while (!(read16(VDP_CTRL_PORT) & 8))
1863 static unused int hexinc(char *c)
1888 write8(0xa10009, 0x40);
1891 while (read16(VDP_CTRL_PORT) & 2)
1894 VDP_setReg(VDP_MODE1, VDP_MODE1_PS);
1895 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA);
1896 VDP_setReg(VDP_MODE3, 0x00);
1897 VDP_setReg(VDP_MODE4, 0x81);
1898 VDP_setReg(VDP_NT_SCROLLA, APLANE >> 10);
1899 VDP_setReg(VDP_NT_SCROLLB, BPLANE >> 13);
1900 VDP_setReg(VDP_SAT_BASE, SLIST >> 9);
1901 VDP_setReg(VDP_HSCROLL, HSCRL >> 10);
1902 VDP_setReg(VDP_AUTOINC, 2);
1903 VDP_setReg(VDP_SCROLLSZ, 0x01);
1904 VDP_setReg(VDP_BACKDROP, 0);
1907 t_dma_zero_wrap_early();
1908 t_dma_zero_fill_early();
1911 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0));
1912 for (i = 0; i < 32 / 4; i++)
1913 write32(VDP_DATA_PORT, 0);
1915 /* clear name tables */
1916 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(APLANE));
1917 for (i = 0; i < PLANE_W * PLANE_H / 2; i++)
1918 write32(VDP_DATA_PORT, 0);
1920 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(BPLANE));
1921 for (i = 0; i < PLANE_W * PLANE_H / 2; i++)
1922 write32(VDP_DATA_PORT, 0);
1924 /* SAT, h. scroll */
1925 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(SLIST));
1926 write32(VDP_DATA_PORT, 0);
1928 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(HSCRL));
1929 write32(VDP_DATA_PORT, 0);
1931 /* scroll plane vscroll */
1932 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0));
1933 write32(VDP_DATA_PORT, 0);
1937 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(TILE_FONT_BASE));
1938 for (i = 0; i < FONT_LEN * 32 / 4; i++)
1939 write32(VDP_DATA_PORT, font_base[i]);
1942 setup_default_palette();
1944 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
1946 have_32x = read32(0xa130ec) == MKLONG('M','A','R','S');
1947 en_32x = have_32x && (read32(0xa15100) & 1);
1948 v8 = read8(0xa10001);
1949 printf("MD version: %02x %s %s %s%s\n", v8,
1950 (v8 & 0x80) ? "world" : "jap",
1951 (v8 & 0x40) ? "pal" : "ntsc",
1952 have_32x ? "32X" : "",
1955 for (i = 0; i < ARRAY_SIZE(g_tests); i++) {
1956 // print test number if we haven't scrolled away
1957 if (printf_ypos < CSCREEN_H) {
1958 int old_ypos = printf_ypos;
1960 printf("%02d/%02d", i, ARRAY_SIZE(g_tests));
1961 printf_ypos = old_ypos;
1964 if ((g_tests[i].type & T_32) && !have_32x) {
1968 ret = g_tests[i].test();
1971 printf("failed %d: %s\n", i, g_tests[i].name);
1979 printf("%d/%d passed, %d skipped.\n",
1980 passed, ARRAY_SIZE(g_tests), skipped);
1985 while (!(get_input() & BTNM_A))
1990 char c[3] = { '0', '0', '0' };
1991 short hscroll = 0, vscroll = 0;
1992 short hsz = 1, vsz = 0;
1995 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(APLANE));
1998 for (i = 0, c[0] = 'a'; i < 8 * 1024 / 2; i++) {
1999 write16(VDP_DATA_PORT, (u16)c[0] - 32 + TILE_FONT_BASE / 32);
2001 if (c[0] == 'z' + 1)
2005 for (i = 0; i < 8 * 1024 / 2 / 4; i++) {
2006 write16(VDP_DATA_PORT, (u16)'.' - 32 + TILE_FONT_BASE / 32);
2007 write16(VDP_DATA_PORT, (u16)c[2] - 32 + TILE_FONT_BASE / 32);
2008 write16(VDP_DATA_PORT, (u16)c[1] - 32 + TILE_FONT_BASE / 32);
2009 write16(VDP_DATA_PORT, (u16)c[0] - 32 + TILE_FONT_BASE / 32);
2015 while (get_input() & BTNM_A)
2020 int b = get_input();
2023 hscroll = 1, vscroll = -1;
2026 } while (get_input() & BTNM_C);
2029 if (b & (BTNM_L | BTNM_R | BTNM_C)) {
2030 hscroll += (b & BTNM_L) ? 1 : -1;
2031 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(HSCRL));
2032 write16(VDP_DATA_PORT, hscroll);
2034 if (b & (BTNM_U | BTNM_D | BTNM_C)) {
2035 vscroll += (b & BTNM_U) ? -1 : 1;
2036 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0));
2038 int end = (int)vscroll + 21;
2039 for (i = vscroll; i < end; i++)
2040 write32(VDP_DATA_PORT, i << 17);
2041 VDP_setReg(VDP_MODE3, 0x04);
2044 write16(VDP_DATA_PORT, vscroll);
2045 VDP_setReg(VDP_MODE3, 0x00);
2049 hsz = (hsz + 1) & 3;
2052 } while (get_input() & BTNM_A);
2055 vsz = (vsz + 1) & 3;
2058 } while (get_input() & BTNM_B);
2060 VDP_setReg(VDP_SCROLLSZ, (vsz << 4) | hsz);
2065 printf(" %d %d ", hsz, vsz);
2077 // vim:ts=4:sw=4:expandtab