1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * linkage_arm.s for PCSX *
3 * Copyright (C) 2009-2011 Ari64 *
4 * Copyright (C) 2010-2013 GraÅžvydas "notaz" Ignotas *
6 * This program is free software; you can redistribute it and/or modify *
7 * it under the terms of the GNU General Public License as published by *
8 * the Free Software Foundation; either version 2 of the License, or *
9 * (at your option) any later version. *
11 * This program is distributed in the hope that it will be useful, *
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
14 * GNU General Public License for more details. *
16 * You should have received a copy of the GNU General Public License *
17 * along with this program; if not, write to the *
18 * Free Software Foundation, Inc., *
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
20 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
22 #include "arm_features.h"
23 #include "linkage_offsets.h"
27 #define dynarec_local ESYM(dynarec_local)
28 #define add_link ESYM(add_link)
29 #define new_recompile_block ESYM(new_recompile_block)
30 #define get_addr ESYM(get_addr)
31 #define get_addr_ht ESYM(get_addr_ht)
32 #define clean_blocks ESYM(clean_blocks)
33 #define gen_interupt ESYM(gen_interupt)
34 #define psxException ESYM(psxException)
35 #define execI ESYM(execI)
36 #define invalidate_addr ESYM(invalidate_addr)
42 .type dynarec_local, %object
43 .size dynarec_local, LO_dynarec_local_size
45 .space LO_dynarec_local_size
47 #define DRC_VAR_(name, vname, size_) \
48 vname = dynarec_local + LO_##name; \
50 .type vname, %object; \
53 #define DRC_VAR(name, size_) \
54 DRC_VAR_(name, ESYM(name), size_)
56 DRC_VAR(next_interupt, 4)
57 DRC_VAR(cycle_count, 4)
58 DRC_VAR(last_count, 4)
59 DRC_VAR(pending_exception, 4)
63 DRC_VAR(psxRegs, LO_psxRegs_end - LO_psxRegs)
69 DRC_VAR(reg_cop0, 128)
70 DRC_VAR(reg_cop2d, 128)
71 DRC_VAR(reg_cop2c, 128)
75 @DRC_VAR(interrupt, 4)
76 @DRC_VAR(intCycle, 256)
82 DRC_VAR(zeromem_ptr, 4)
83 DRC_VAR(inv_code_start, 4)
84 DRC_VAR(inv_code_end, 4)
85 DRC_VAR(branch_target, 4)
86 @DRC_VAR(align0, 16) /* unused/alignment */
88 DRC_VAR(restore_candidate, 512)
101 .macro load_varadr reg var
102 #if defined(__ARM_ARCH_7A__) && !defined(__PIC__)
103 movw \reg, #:lower16:\var
104 movt \reg, #:upper16:\var
110 .macro mov_16 reg imm
111 #ifdef __ARM_ARCH_7A__
114 mov \reg, #(\imm & 0x00ff)
115 orr \reg, #(\imm & 0xff00)
119 .macro mov_24 reg imm
120 #ifdef __ARM_ARCH_7A__
121 movw \reg, #(\imm & 0xffff)
122 movt \reg, #(\imm >> 16)
124 mov \reg, #(\imm & 0x0000ff)
125 orr \reg, #(\imm & 0x00ff00)
126 orr \reg, #(\imm & 0xff0000)
130 .macro dyna_linker_main
131 /* r0 = virtual target address */
132 /* r1 = instruction to patch */
146 ldr r5, [r3, r2, lsl #2]
148 add r6, r1, r12, asr #6
163 moveq pc, r4 /* Stale i-cache */
165 b 1b /* jump_in may have dupes, continue search */
168 beq 3f /* r0 not in jump_in */
174 and r1, r7, #0xff000000
177 add r1, r1, r2, lsr #8
181 /* hash_table lookup */
184 eor r4, r0, r0, lsl #16
190 ldr r5, [r3, r2, lsl #2]
197 /* jump_dirty lookup */
207 /* hash_table insert */
221 FUNCTION(dyna_linker):
222 /* r0 = virtual target address */
223 /* r1 = instruction to patch */
228 bl new_recompile_block
236 .size dyna_linker, .-dyna_linker
238 FUNCTION(exec_pagefault):
239 /* r0 = instruction pointer */
240 /* r1 = fault address */
242 ldr r3, [fp, #LO_reg_cop0+48] /* Status */
244 ldr r4, [fp, #LO_reg_cop0+16] /* Context */
245 bic r6, r6, #0x0F800000
246 str r0, [fp, #LO_reg_cop0+56] /* EPC */
248 str r1, [fp, #LO_reg_cop0+32] /* BadVAddr */
250 str r3, [fp, #LO_reg_cop0+48] /* Status */
251 and r5, r6, r1, lsr #9
252 str r2, [fp, #LO_reg_cop0+52] /* Cause */
253 and r1, r1, r6, lsl #9
254 str r1, [fp, #LO_reg_cop0+40] /* EntryHi */
256 str r4, [fp, #LO_reg_cop0+16] /* Context */
260 .size exec_pagefault, .-exec_pagefault
262 /* Special dynamic linker for the case where a page fault
263 may occur in a branch delay slot */
264 FUNCTION(dyna_linker_ds):
265 /* r0 = virtual target address */
266 /* r1 = instruction to patch */
273 bl new_recompile_block
280 mov r2, #0x80000008 /* High bit set indicates pagefault in delay slot */
283 .size dyna_linker_ds, .-dyna_linker_ds
293 FUNCTION(jump_vaddr_r0):
294 eor r2, r0, r0, lsl #16
296 .size jump_vaddr_r0, .-jump_vaddr_r0
297 FUNCTION(jump_vaddr_r1):
298 eor r2, r1, r1, lsl #16
301 .size jump_vaddr_r1, .-jump_vaddr_r1
302 FUNCTION(jump_vaddr_r2):
304 eor r2, r2, r2, lsl #16
306 .size jump_vaddr_r2, .-jump_vaddr_r2
307 FUNCTION(jump_vaddr_r3):
308 eor r2, r3, r3, lsl #16
311 .size jump_vaddr_r3, .-jump_vaddr_r3
312 FUNCTION(jump_vaddr_r4):
313 eor r2, r4, r4, lsl #16
316 .size jump_vaddr_r4, .-jump_vaddr_r4
317 FUNCTION(jump_vaddr_r5):
318 eor r2, r5, r5, lsl #16
321 .size jump_vaddr_r5, .-jump_vaddr_r5
322 FUNCTION(jump_vaddr_r6):
323 eor r2, r6, r6, lsl #16
326 .size jump_vaddr_r6, .-jump_vaddr_r6
327 FUNCTION(jump_vaddr_r8):
328 eor r2, r8, r8, lsl #16
331 .size jump_vaddr_r8, .-jump_vaddr_r8
332 FUNCTION(jump_vaddr_r9):
333 eor r2, r9, r9, lsl #16
336 .size jump_vaddr_r9, .-jump_vaddr_r9
337 FUNCTION(jump_vaddr_r10):
338 eor r2, r10, r10, lsl #16
341 .size jump_vaddr_r10, .-jump_vaddr_r10
342 FUNCTION(jump_vaddr_r12):
343 eor r2, r12, r12, lsl #16
346 .size jump_vaddr_r12, .-jump_vaddr_r12
347 FUNCTION(jump_vaddr_r7):
348 eor r2, r7, r7, lsl #16
350 .size jump_vaddr_r7, .-jump_vaddr_r7
351 FUNCTION(jump_vaddr):
354 and r2, r3, r2, lsr #12
361 str r10, [fp, #LO_cycle_count]
363 ldr r10, [fp, #LO_cycle_count]
365 .size jump_vaddr, .-jump_vaddr
369 FUNCTION(verify_code_ds):
370 str r8, [fp, #LO_branch_target]
371 FUNCTION(verify_code_vm):
372 FUNCTION(verify_code):
400 ldr r8, [fp, #LO_branch_target]
405 .size verify_code, .-verify_code
406 .size verify_code_vm, .-verify_code_vm
409 FUNCTION(cc_interrupt):
410 ldr r0, [fp, #LO_last_count]
414 str r1, [fp, #LO_pending_exception]
415 and r2, r2, r10, lsr #17
416 add r3, fp, #LO_restore_candidate
417 str r10, [fp, #LO_cycle] /* PCSX cycles */
418 @@ str r10, [fp, #LO_reg_cop0+36] /* Count */
426 ldr r10, [fp, #LO_cycle]
427 ldr r0, [fp, #LO_next_interupt]
428 ldr r1, [fp, #LO_pending_exception]
429 ldr r2, [fp, #LO_stop]
430 str r0, [fp, #LO_last_count]
433 ldmnefd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, pc}
437 ldr r0, [fp, #LO_pcaddr]
441 /* Move 'dirty' blocks to the 'clean' list */
452 .size cc_interrupt, .-cc_interrupt
455 FUNCTION(do_interrupt):
456 ldr r0, [fp, #LO_pcaddr]
460 .size do_interrupt, .-do_interrupt
463 FUNCTION(fp_exception):
466 ldr r1, [fp, #LO_reg_cop0+48] /* Status */
468 str r0, [fp, #LO_reg_cop0+56] /* EPC */
471 str r1, [fp, #LO_reg_cop0+48] /* Status */
472 str r2, [fp, #LO_reg_cop0+52] /* Cause */
476 .size fp_exception, .-fp_exception
478 FUNCTION(fp_exception_ds):
479 mov r2, #0x90000000 /* Set high bit if delay slot */
481 .size fp_exception_ds, .-fp_exception_ds
484 FUNCTION(jump_syscall):
485 ldr r1, [fp, #LO_reg_cop0+48] /* Status */
487 str r0, [fp, #LO_reg_cop0+56] /* EPC */
490 str r1, [fp, #LO_reg_cop0+48] /* Status */
491 str r2, [fp, #LO_reg_cop0+52] /* Cause */
495 .size jump_syscall, .-jump_syscall
499 FUNCTION(jump_syscall_hle):
500 str r0, [fp, #LO_pcaddr] /* PC must be set to EPC for psxException */
501 ldr r2, [fp, #LO_last_count]
502 mov r1, #0 /* in delay slot */
504 mov r0, #0x20 /* cause */
505 str r2, [fp, #LO_cycle] /* PCSX cycle counter */
508 /* note: psxException might do recursive recompiler call from it's HLE code,
509 * so be ready for this */
511 ldr r1, [fp, #LO_next_interupt]
512 ldr r10, [fp, #LO_cycle]
513 ldr r0, [fp, #LO_pcaddr]
515 str r1, [fp, #LO_last_count]
518 .size jump_syscall_hle, .-jump_syscall_hle
521 FUNCTION(jump_hlecall):
522 ldr r2, [fp, #LO_last_count]
523 str r0, [fp, #LO_pcaddr]
526 str r2, [fp, #LO_cycle] /* PCSX cycle counter */
528 .size jump_hlecall, .-jump_hlecall
531 FUNCTION(jump_intcall):
532 ldr r2, [fp, #LO_last_count]
533 str r0, [fp, #LO_pcaddr]
536 str r2, [fp, #LO_cycle] /* PCSX cycle counter */
538 .size jump_hlecall, .-jump_hlecall
541 FUNCTION(new_dyna_leave):
542 ldr r0, [fp, #LO_last_count]
545 str r10, [fp, #LO_cycle]
546 ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, pc}
547 .size new_dyna_leave, .-new_dyna_leave
550 FUNCTION(invalidate_addr_r0):
551 stmia fp, {r0, r1, r2, r3, r12, lr}
552 b invalidate_addr_call
553 .size invalidate_addr_r0, .-invalidate_addr_r0
555 FUNCTION(invalidate_addr_r1):
556 stmia fp, {r0, r1, r2, r3, r12, lr}
558 b invalidate_addr_call
559 .size invalidate_addr_r1, .-invalidate_addr_r1
561 FUNCTION(invalidate_addr_r2):
562 stmia fp, {r0, r1, r2, r3, r12, lr}
564 b invalidate_addr_call
565 .size invalidate_addr_r2, .-invalidate_addr_r2
567 FUNCTION(invalidate_addr_r3):
568 stmia fp, {r0, r1, r2, r3, r12, lr}
570 b invalidate_addr_call
571 .size invalidate_addr_r3, .-invalidate_addr_r3
573 FUNCTION(invalidate_addr_r4):
574 stmia fp, {r0, r1, r2, r3, r12, lr}
576 b invalidate_addr_call
577 .size invalidate_addr_r4, .-invalidate_addr_r4
579 FUNCTION(invalidate_addr_r5):
580 stmia fp, {r0, r1, r2, r3, r12, lr}
582 b invalidate_addr_call
583 .size invalidate_addr_r5, .-invalidate_addr_r5
585 FUNCTION(invalidate_addr_r6):
586 stmia fp, {r0, r1, r2, r3, r12, lr}
588 b invalidate_addr_call
589 .size invalidate_addr_r6, .-invalidate_addr_r6
591 FUNCTION(invalidate_addr_r7):
592 stmia fp, {r0, r1, r2, r3, r12, lr}
594 b invalidate_addr_call
595 .size invalidate_addr_r7, .-invalidate_addr_r7
597 FUNCTION(invalidate_addr_r8):
598 stmia fp, {r0, r1, r2, r3, r12, lr}
600 b invalidate_addr_call
601 .size invalidate_addr_r8, .-invalidate_addr_r8
603 FUNCTION(invalidate_addr_r9):
604 stmia fp, {r0, r1, r2, r3, r12, lr}
606 b invalidate_addr_call
607 .size invalidate_addr_r9, .-invalidate_addr_r9
609 FUNCTION(invalidate_addr_r10):
610 stmia fp, {r0, r1, r2, r3, r12, lr}
612 b invalidate_addr_call
613 .size invalidate_addr_r10, .-invalidate_addr_r10
615 FUNCTION(invalidate_addr_r12):
616 stmia fp, {r0, r1, r2, r3, r12, lr}
618 .size invalidate_addr_r12, .-invalidate_addr_r12
620 invalidate_addr_call:
621 ldr r12, [fp, #LO_inv_code_start]
622 ldr lr, [fp, #LO_inv_code_end]
626 ldmia fp, {r0, r1, r2, r3, r12, pc}
627 .size invalidate_addr_call, .-invalidate_addr_call
630 FUNCTION(new_dyna_start):
631 /* ip is stored to conform EABI alignment */
632 stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, lr}
633 load_varadr fp, dynarec_local
634 ldr r0, [fp, #LO_pcaddr]
636 ldr r1, [fp, #LO_next_interupt]
637 ldr r10, [fp, #LO_cycle]
638 str r1, [fp, #LO_last_count]
641 .size new_dyna_start, .-new_dyna_start
643 /* --------------------------------------- */
647 .macro pcsx_read_mem readop tab_shift
648 /* r0 = address, r1 = handler_tab, r2 = cycles */
650 lsr r3, #(20+\tab_shift)
651 ldr r12, [fp, #LO_last_count]
652 ldr r1, [r1, r3, lsl #2]
659 \readop r0, [r1, r3, lsl #\tab_shift]
662 str r2, [fp, #LO_cycle]
666 FUNCTION(jump_handler_read8):
667 add r1, #0x1000/4*4 + 0x1000/2*4 @ shift to r8 part
668 pcsx_read_mem ldrccb, 0
670 FUNCTION(jump_handler_read16):
671 add r1, #0x1000/4*4 @ shift to r16 part
672 pcsx_read_mem ldrcch, 1
674 FUNCTION(jump_handler_read32):
675 pcsx_read_mem ldrcc, 2
678 .macro pcsx_write_mem wrtop tab_shift
679 /* r0 = address, r1 = data, r2 = cycles, r3 = handler_tab */
681 lsr r12, #(20+\tab_shift)
682 ldr r3, [r3, r12, lsl #2]
683 str r0, [fp, #LO_address] @ some handlers still need it..
685 mov r0, r2 @ cycle return in case of direct store
690 \wrtop r1, [r3, r12, lsl #\tab_shift]
693 ldr r12, [fp, #LO_last_count]
697 str r2, [fp, #LO_cycle]
700 ldr r0, [fp, #LO_next_interupt]
702 str r0, [fp, #LO_last_count]
707 FUNCTION(jump_handler_write8):
708 add r3, #0x1000/4*4 + 0x1000/2*4 @ shift to r8 part
709 pcsx_write_mem strccb, 0
711 FUNCTION(jump_handler_write16):
712 add r3, #0x1000/4*4 @ shift to r16 part
713 pcsx_write_mem strcch, 1
715 FUNCTION(jump_handler_write32):
716 pcsx_write_mem strcc, 2
718 FUNCTION(jump_handler_write_h):
719 /* r0 = address, r1 = data, r2 = cycles, r3 = handler */
720 ldr r12, [fp, #LO_last_count]
721 str r0, [fp, #LO_address] @ some handlers still need it..
725 str r2, [fp, #LO_cycle]
728 ldr r0, [fp, #LO_next_interupt]
730 str r0, [fp, #LO_last_count]
734 FUNCTION(jump_handle_swl):
735 /* r0 = address, r1 = data, r2 = cycles */
736 ldr r3, [fp, #LO_mem_wtab]
738 ldr r3, [r3, r12, lsl #2]
759 lsreq r12, r1, #24 @ 0
769 FUNCTION(jump_handle_swr):
770 /* r0 = address, r1 = data, r2 = cycles */
771 ldr r3, [fp, #LO_mem_wtab]
773 ldr r3, [r3, r12, lsl #2]
795 .macro rcntx_read_mode0 num
796 /* r0 = address, r2 = cycles */
797 ldr r3, [fp, #LO_rcnts+6*4+7*4*\num] @ cycleStart
804 FUNCTION(rcnt0_read_count_m0):
807 FUNCTION(rcnt1_read_count_m0):
810 FUNCTION(rcnt2_read_count_m0):
813 FUNCTION(rcnt0_read_count_m1):
814 /* r0 = address, r2 = cycles */
815 ldr r3, [fp, #LO_rcnts+6*4+7*4*0] @ cycleStart
818 mul r0, r1, r2 @ /= 5
822 FUNCTION(rcnt1_read_count_m1):
823 /* r0 = address, r2 = cycles */
824 ldr r3, [fp, #LO_rcnts+6*4+7*4*1]
827 umull r3, r0, r1, r2 @ ~ /= hsync_cycles, max ~0x1e6cdd
830 FUNCTION(rcnt2_read_count_m1):
831 /* r0 = address, r2 = cycles */
832 ldr r3, [fp, #LO_rcnts+6*4+7*4*2]
833 mov r0, r2, lsl #16-3
834 sub r0, r3, lsl #16-3
838 @ vim:filetype=armasm