1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
3 * Copyright (C) 2009-2011 Ari64 *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
22 #include <stdint.h> //include for uint64_t
25 #include "emu_if.h" //emulator interface
30 #include "assem_x86.h"
33 #include "assem_x64.h"
36 #include "assem_arm.h"
40 #define MAX_OUTPUT_BLOCK_SIZE 262144
41 #define CLOCK_DIVIDER 2
45 signed char regmap_entry[HOST_REGS];
46 signed char regmap[HOST_REGS];
55 uint64_t constmap[HOST_REGS];
63 struct ll_entry *next;
69 char insn[MAXBLOCK][10];
70 u_char itype[MAXBLOCK];
71 u_char opcode[MAXBLOCK];
72 u_char opcode2[MAXBLOCK];
80 u_char dep1[MAXBLOCK];
81 u_char dep2[MAXBLOCK];
85 char likely[MAXBLOCK];
88 uint64_t unneeded_reg[MAXBLOCK];
89 uint64_t unneeded_reg_upper[MAXBLOCK];
90 uint64_t branch_unneeded_reg[MAXBLOCK];
91 uint64_t branch_unneeded_reg_upper[MAXBLOCK];
92 uint64_t p32[MAXBLOCK];
93 uint64_t pr32[MAXBLOCK];
94 signed char regmap_pre[MAXBLOCK][HOST_REGS];
95 signed char regmap[MAXBLOCK][HOST_REGS];
96 signed char regmap_entry[MAXBLOCK][HOST_REGS];
97 uint64_t constmap[MAXBLOCK][HOST_REGS];
98 struct regstat regs[MAXBLOCK];
99 struct regstat branch_regs[MAXBLOCK];
100 signed char minimum_free_regs[MAXBLOCK];
101 u_int needed_reg[MAXBLOCK];
102 uint64_t requires_32bit[MAXBLOCK];
103 u_int wont_dirty[MAXBLOCK];
104 u_int will_dirty[MAXBLOCK];
107 u_int instr_addr[MAXBLOCK];
108 u_int link_addr[MAXBLOCK][3];
110 u_int stubs[MAXBLOCK*3][8];
112 u_int literals[1024][2];
117 struct ll_entry *jump_in[4096];
118 struct ll_entry *jump_out[4096];
119 struct ll_entry *jump_dirty[4096];
120 u_int hash_table[65536][4] __attribute__((aligned(16)));
121 char shadow[1048576] __attribute__((aligned(16)));
127 static const u_int using_tlb=0;
129 static u_int sp_in_mirror;
130 u_int stop_after_jal;
131 extern u_char restore_candidate[512];
132 extern int cycle_count;
134 /* registers that may be allocated */
136 #define HIREG 32 // hi
137 #define LOREG 33 // lo
138 #define FSREG 34 // FPU status (FCSR)
139 #define CSREG 35 // Coprocessor status
140 #define CCREG 36 // Cycle count
141 #define INVCP 37 // Pointer to invalid_code
142 #define MMREG 38 // Pointer to memory_map
143 #define ROREG 39 // ram offset (if rdram!=0x80000000)
145 #define FTEMP 40 // FPU temporary register
146 #define PTEMP 41 // Prefetch temporary register
147 #define TLREG 42 // TLB mapping offset
148 #define RHASH 43 // Return address hash
149 #define RHTBL 44 // Return address hash table address
150 #define RTEMP 45 // JR/JALR address register
152 #define AGEN1 46 // Address generation temporary register
153 #define AGEN2 47 // Address generation temporary register
154 #define MGEN1 48 // Maptable address generation temporary register
155 #define MGEN2 49 // Maptable address generation temporary register
156 #define BTREG 50 // Branch target temporary register
158 /* instruction types */
159 #define NOP 0 // No operation
160 #define LOAD 1 // Load
161 #define STORE 2 // Store
162 #define LOADLR 3 // Unaligned load
163 #define STORELR 4 // Unaligned store
164 #define MOV 5 // Move
165 #define ALU 6 // Arithmetic/logic
166 #define MULTDIV 7 // Multiply/divide
167 #define SHIFT 8 // Shift by register
168 #define SHIFTIMM 9// Shift by immediate
169 #define IMM16 10 // 16-bit immediate
170 #define RJUMP 11 // Unconditional jump to register
171 #define UJUMP 12 // Unconditional jump
172 #define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
173 #define SJUMP 14 // Conditional branch (regimm format)
174 #define COP0 15 // Coprocessor 0
175 #define COP1 16 // Coprocessor 1
176 #define C1LS 17 // Coprocessor 1 load/store
177 #define FJUMP 18 // Conditional branch (floating point)
178 #define FLOAT 19 // Floating point unit
179 #define FCONV 20 // Convert integer to float
180 #define FCOMP 21 // Floating point compare (sets FSREG)
181 #define SYSCALL 22// SYSCALL
182 #define OTHER 23 // Other
183 #define SPAN 24 // Branch/delay slot spans 2 pages
184 #define NI 25 // Not implemented
185 #define HLECALL 26// PCSX fake opcodes for HLE
186 #define COP2 27 // Coprocessor 2 move
187 #define C2LS 28 // Coprocessor 2 load/store
188 #define C2OP 29 // Coprocessor 2 operation
189 #define INTCALL 30// Call interpreter to handle rare corner cases
198 #define LOADBU_STUB 7
199 #define LOADHU_STUB 8
200 #define STOREB_STUB 9
201 #define STOREH_STUB 10
202 #define STOREW_STUB 11
203 #define STORED_STUB 12
204 #define STORELR_STUB 13
205 #define INVCODE_STUB 14
213 int new_recompile_block(int addr);
214 void *get_addr_ht(u_int vaddr);
215 void invalidate_block(u_int block);
216 void invalidate_addr(u_int addr);
217 void remove_hash(int vaddr);
220 void dyna_linker_ds();
222 void verify_code_vm();
223 void verify_code_ds();
226 void fp_exception_ds();
228 void jump_syscall_hle();
232 void new_dyna_leave();
237 void read_nomem_new();
238 void read_nomemb_new();
239 void read_nomemh_new();
240 void read_nomemd_new();
241 void write_nomem_new();
242 void write_nomemb_new();
243 void write_nomemh_new();
244 void write_nomemd_new();
245 void write_rdram_new();
246 void write_rdramb_new();
247 void write_rdramh_new();
248 void write_rdramd_new();
249 extern u_int memory_map[1048576];
251 // Needed by assembler
252 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
253 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
254 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
255 void load_all_regs(signed char i_regmap[]);
256 void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
257 void load_regs_entry(int t);
258 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
262 //#define DEBUG_CYCLE_COUNT 1
265 //#define assem_debug printf
266 //#define inv_debug printf
267 #define assem_debug nullf
268 #define inv_debug nullf
270 static void tlb_hacks()
274 if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
278 switch (ROM_HEADER->Country_code&0xFF)
290 // Unknown country code
294 u_int rom_addr=(u_int)rom;
296 // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
297 // in the lower 4G of memory to use this hack. Copy it if necessary.
298 if((void *)rom>(void *)0xffffffff) {
299 munmap(ROM_COPY, 67108864);
300 if(mmap(ROM_COPY, 12582912,
301 PROT_READ | PROT_WRITE,
302 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
303 -1, 0) <= 0) {printf("mmap() failed\n");}
304 memcpy(ROM_COPY,rom,12582912);
305 rom_addr=(u_int)ROM_COPY;
309 for(n=0x7F000;n<0x80000;n++) {
310 memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
317 static u_int get_page(u_int vaddr)
320 u_int page=(vaddr^0x80000000)>>12;
322 u_int page=vaddr&~0xe0000000;
323 if (page < 0x1000000)
324 page &= ~0x0e00000; // RAM mirrors
328 if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
330 if(page>2048) page=2048+(page&2047);
334 static u_int get_vpage(u_int vaddr)
336 u_int vpage=(vaddr^0x80000000)>>12;
338 if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
340 if(vpage>2048) vpage=2048+(vpage&2047);
344 // Get address from virtual address
345 // This is called from the recompiled JR/JALR instructions
346 void *get_addr(u_int vaddr)
348 u_int page=get_page(vaddr);
349 u_int vpage=get_vpage(vaddr);
350 struct ll_entry *head;
351 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
354 if(head->vaddr==vaddr&&head->reg32==0) {
355 //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
356 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
359 ht_bin[1]=(int)head->addr;
365 head=jump_dirty[vpage];
367 if(head->vaddr==vaddr&&head->reg32==0) {
368 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
369 // Don't restore blocks which are about to expire from the cache
370 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
371 if(verify_dirty(head->addr)) {
372 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
373 invalid_code[vaddr>>12]=0;
374 inv_code_start=inv_code_end=~0;
375 memory_map[vaddr>>12]|=0x40000000;
378 if(tlb_LUT_r[vaddr>>12]) {
379 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
380 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
383 restore_candidate[vpage>>3]|=1<<(vpage&7);
385 else restore_candidate[page>>3]|=1<<(page&7);
386 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
387 if(ht_bin[0]==vaddr) {
388 ht_bin[1]=(int)head->addr; // Replace existing entry
394 ht_bin[1]=(int)head->addr;
402 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
403 int r=new_recompile_block(vaddr);
404 if(r==0) return get_addr(vaddr);
405 // Execute in unmapped page, generate pagefault execption
407 Cause=(vaddr<<31)|0x8;
408 EPC=(vaddr&1)?vaddr-5:vaddr;
410 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
411 EntryHi=BadVAddr&0xFFFFE000;
412 return get_addr_ht(0x80000000);
414 // Look up address in hash table first
415 void *get_addr_ht(u_int vaddr)
417 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
418 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
419 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
420 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
421 return get_addr(vaddr);
424 void *get_addr_32(u_int vaddr,u_int flags)
427 return get_addr(vaddr);
429 //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
430 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
431 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
432 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
433 u_int page=get_page(vaddr);
434 u_int vpage=get_vpage(vaddr);
435 struct ll_entry *head;
438 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
439 //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
441 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
443 ht_bin[1]=(int)head->addr;
445 }else if(ht_bin[2]==-1) {
446 ht_bin[3]=(int)head->addr;
449 //ht_bin[3]=ht_bin[1];
450 //ht_bin[2]=ht_bin[0];
451 //ht_bin[1]=(int)head->addr;
458 head=jump_dirty[vpage];
460 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
461 //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
462 // Don't restore blocks which are about to expire from the cache
463 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
464 if(verify_dirty(head->addr)) {
465 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
466 invalid_code[vaddr>>12]=0;
467 inv_code_start=inv_code_end=~0;
468 memory_map[vaddr>>12]|=0x40000000;
471 if(tlb_LUT_r[vaddr>>12]) {
472 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
473 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
476 restore_candidate[vpage>>3]|=1<<(vpage&7);
478 else restore_candidate[page>>3]|=1<<(page&7);
480 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
482 ht_bin[1]=(int)head->addr;
484 }else if(ht_bin[2]==-1) {
485 ht_bin[3]=(int)head->addr;
488 //ht_bin[3]=ht_bin[1];
489 //ht_bin[2]=ht_bin[0];
490 //ht_bin[1]=(int)head->addr;
498 //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
499 int r=new_recompile_block(vaddr);
500 if(r==0) return get_addr(vaddr);
501 // Execute in unmapped page, generate pagefault execption
503 Cause=(vaddr<<31)|0x8;
504 EPC=(vaddr&1)?vaddr-5:vaddr;
506 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
507 EntryHi=BadVAddr&0xFFFFE000;
508 return get_addr_ht(0x80000000);
512 void clear_all_regs(signed char regmap[])
515 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
518 signed char get_reg(signed char regmap[],int r)
521 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map[hr]==r) return hr;
525 // Find a register that is available for two consecutive cycles
526 signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
529 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map1[hr]==r&®map2[hr]==r) return hr;
533 int count_free_regs(signed char regmap[])
537 for(hr=0;hr<HOST_REGS;hr++)
539 if(hr!=EXCLUDE_REG) {
540 if(regmap[hr]<0) count++;
546 void dirty_reg(struct regstat *cur,signed char reg)
550 for (hr=0;hr<HOST_REGS;hr++) {
551 if((cur->regmap[hr]&63)==reg) {
557 // If we dirty the lower half of a 64 bit register which is now being
558 // sign-extended, we need to dump the upper half.
559 // Note: Do this only after completion of the instruction, because
560 // some instructions may need to read the full 64-bit value even if
561 // overwriting it (eg SLTI, DSRA32).
562 static void flush_dirty_uppers(struct regstat *cur)
565 for (hr=0;hr<HOST_REGS;hr++) {
566 if((cur->dirty>>hr)&1) {
569 if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
574 void set_const(struct regstat *cur,signed char reg,uint64_t value)
578 for (hr=0;hr<HOST_REGS;hr++) {
579 if(cur->regmap[hr]==reg) {
581 cur->constmap[hr]=value;
583 else if((cur->regmap[hr]^64)==reg) {
585 cur->constmap[hr]=value>>32;
590 void clear_const(struct regstat *cur,signed char reg)
594 for (hr=0;hr<HOST_REGS;hr++) {
595 if((cur->regmap[hr]&63)==reg) {
596 cur->isconst&=~(1<<hr);
601 int is_const(struct regstat *cur,signed char reg)
606 for (hr=0;hr<HOST_REGS;hr++) {
607 if((cur->regmap[hr]&63)==reg) {
608 return (cur->isconst>>hr)&1;
613 uint64_t get_const(struct regstat *cur,signed char reg)
617 for (hr=0;hr<HOST_REGS;hr++) {
618 if(cur->regmap[hr]==reg) {
619 return cur->constmap[hr];
622 printf("Unknown constant in r%d\n",reg);
626 // Least soon needed registers
627 // Look at the next ten instructions and see which registers
628 // will be used. Try not to reallocate these.
629 void lsn(u_char hsn[], int i, int *preferred_reg)
639 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
641 // Don't go past an unconditonal jump
648 if(rs1[i+j]) hsn[rs1[i+j]]=j;
649 if(rs2[i+j]) hsn[rs2[i+j]]=j;
650 if(rt1[i+j]) hsn[rt1[i+j]]=j;
651 if(rt2[i+j]) hsn[rt2[i+j]]=j;
652 if(itype[i+j]==STORE || itype[i+j]==STORELR) {
653 // Stores can allocate zero
657 // On some architectures stores need invc_ptr
658 #if defined(HOST_IMM8)
659 if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
663 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
671 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
673 // Follow first branch
674 int t=(ba[i+b]-start)>>2;
675 j=7-b;if(t+j>=slen) j=slen-t-1;
678 if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
679 if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
680 //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
681 //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
684 // TODO: preferred register based on backward branch
686 // Delay slot should preferably not overwrite branch conditions or cycle count
687 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
688 if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
689 if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
695 // Coprocessor load/store needs FTEMP, even if not declared
696 if(itype[i]==C1LS||itype[i]==C2LS) {
699 // Load L/R also uses FTEMP as a temporary register
700 if(itype[i]==LOADLR) {
703 // Also SWL/SWR/SDL/SDR
704 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
707 // Don't remove the TLB registers either
708 if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
711 // Don't remove the miniht registers
712 if(itype[i]==UJUMP||itype[i]==RJUMP)
719 // We only want to allocate registers if we're going to use them again soon
720 int needed_again(int r, int i)
726 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
728 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
729 return 0; // Don't need any registers if exiting the block
737 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
739 // Don't go past an unconditonal jump
743 if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
750 if(rs1[i+j]==r) rn=j;
751 if(rs2[i+j]==r) rn=j;
752 if((unneeded_reg[i+j]>>r)&1) rn=10;
753 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
761 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
763 // Follow first branch
765 int t=(ba[i+b]-start)>>2;
766 j=7-b;if(t+j>=slen) j=slen-t-1;
769 if(!((unneeded_reg[t+j]>>r)&1)) {
770 if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
771 if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
781 // Try to match register allocations at the end of a loop with those
783 int loop_reg(int i, int r, int hr)
792 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
794 // Don't go past an unconditonal jump
801 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
806 if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
807 if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
808 if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
810 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
812 int t=(ba[i+k]-start)>>2;
813 int reg=get_reg(regs[t].regmap_entry,r);
814 if(reg>=0) return reg;
815 //reg=get_reg(regs[t+1].regmap_entry,r);
816 //if(reg>=0) return reg;
824 // Allocate every register, preserving source/target regs
825 void alloc_all(struct regstat *cur,int i)
829 for(hr=0;hr<HOST_REGS;hr++) {
830 if(hr!=EXCLUDE_REG) {
831 if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
832 ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
835 cur->dirty&=~(1<<hr);
838 if((cur->regmap[hr]&63)==0)
841 cur->dirty&=~(1<<hr);
848 void div64(int64_t dividend,int64_t divisor)
852 //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
853 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
855 void divu64(uint64_t dividend,uint64_t divisor)
859 //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
860 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
863 void mult64(uint64_t m1,uint64_t m2)
865 unsigned long long int op1, op2, op3, op4;
866 unsigned long long int result1, result2, result3, result4;
867 unsigned long long int temp1, temp2, temp3, temp4;
883 op1 = op2 & 0xFFFFFFFF;
884 op2 = (op2 >> 32) & 0xFFFFFFFF;
885 op3 = op4 & 0xFFFFFFFF;
886 op4 = (op4 >> 32) & 0xFFFFFFFF;
889 temp2 = (temp1 >> 32) + op1 * op4;
891 temp4 = (temp3 >> 32) + op2 * op4;
893 result1 = temp1 & 0xFFFFFFFF;
894 result2 = temp2 + (temp3 & 0xFFFFFFFF);
895 result3 = (result2 >> 32) + temp4;
896 result4 = (result3 >> 32);
898 lo = result1 | (result2 << 32);
899 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
908 void multu64(uint64_t m1,uint64_t m2)
910 unsigned long long int op1, op2, op3, op4;
911 unsigned long long int result1, result2, result3, result4;
912 unsigned long long int temp1, temp2, temp3, temp4;
914 op1 = m1 & 0xFFFFFFFF;
915 op2 = (m1 >> 32) & 0xFFFFFFFF;
916 op3 = m2 & 0xFFFFFFFF;
917 op4 = (m2 >> 32) & 0xFFFFFFFF;
920 temp2 = (temp1 >> 32) + op1 * op4;
922 temp4 = (temp3 >> 32) + op2 * op4;
924 result1 = temp1 & 0xFFFFFFFF;
925 result2 = temp2 + (temp3 & 0xFFFFFFFF);
926 result3 = (result2 >> 32) + temp4;
927 result4 = (result3 >> 32);
929 lo = result1 | (result2 << 32);
930 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
932 //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
933 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
936 uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
944 else original=loaded;
947 uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
950 original>>=64-(bits^56);
951 original<<=64-(bits^56);
955 else original=loaded;
960 #include "assem_x86.c"
963 #include "assem_x64.c"
966 #include "assem_arm.c"
969 // Add virtual address mapping to linked list
970 void ll_add(struct ll_entry **head,int vaddr,void *addr)
972 struct ll_entry *new_entry;
973 new_entry=malloc(sizeof(struct ll_entry));
974 assert(new_entry!=NULL);
975 new_entry->vaddr=vaddr;
977 new_entry->addr=addr;
978 new_entry->next=*head;
982 // Add virtual address mapping for 32-bit compiled block
983 void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
985 ll_add(head,vaddr,addr);
987 (*head)->reg32=reg32;
991 // Check if an address is already compiled
992 // but don't return addresses which are about to expire from the cache
993 void *check_addr(u_int vaddr)
995 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
996 if(ht_bin[0]==vaddr) {
997 if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
998 if(isclean(ht_bin[1])) return (void *)ht_bin[1];
1000 if(ht_bin[2]==vaddr) {
1001 if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1002 if(isclean(ht_bin[3])) return (void *)ht_bin[3];
1004 u_int page=get_page(vaddr);
1005 struct ll_entry *head;
1008 if(head->vaddr==vaddr&&head->reg32==0) {
1009 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1010 // Update existing entry with current address
1011 if(ht_bin[0]==vaddr) {
1012 ht_bin[1]=(int)head->addr;
1015 if(ht_bin[2]==vaddr) {
1016 ht_bin[3]=(int)head->addr;
1019 // Insert into hash table with low priority.
1020 // Don't evict existing entries, as they are probably
1021 // addresses that are being accessed frequently.
1023 ht_bin[1]=(int)head->addr;
1025 }else if(ht_bin[2]==-1) {
1026 ht_bin[3]=(int)head->addr;
1037 void remove_hash(int vaddr)
1039 //printf("remove hash: %x\n",vaddr);
1040 int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1041 if(ht_bin[2]==vaddr) {
1042 ht_bin[2]=ht_bin[3]=-1;
1044 if(ht_bin[0]==vaddr) {
1045 ht_bin[0]=ht_bin[2];
1046 ht_bin[1]=ht_bin[3];
1047 ht_bin[2]=ht_bin[3]=-1;
1051 void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1053 struct ll_entry *next;
1055 if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1056 ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1058 inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1059 remove_hash((*head)->vaddr);
1066 head=&((*head)->next);
1071 // Remove all entries from linked list
1072 void ll_clear(struct ll_entry **head)
1074 struct ll_entry *cur;
1075 struct ll_entry *next;
1086 // Dereference the pointers and remove if it matches
1087 void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1090 int ptr=get_pointer(head->addr);
1091 inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1092 if(((ptr>>shift)==(addr>>shift)) ||
1093 (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1095 inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1096 u_int host_addr=(u_int)kill_pointer(head->addr);
1098 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1105 // This is called when we write to a compiled block (see do_invstub)
1106 void invalidate_page(u_int page)
1108 struct ll_entry *head;
1109 struct ll_entry *next;
1113 inv_debug("INVALIDATE: %x\n",head->vaddr);
1114 remove_hash(head->vaddr);
1119 head=jump_out[page];
1122 inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
1123 u_int host_addr=(u_int)kill_pointer(head->addr);
1125 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1133 static void invalidate_block_range(u_int block, u_int first, u_int last)
1135 u_int page=get_page(block<<12);
1136 //printf("first=%d last=%d\n",first,last);
1137 invalidate_page(page);
1138 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1139 assert(last<page+5);
1140 // Invalidate the adjacent pages if a block crosses a 4K boundary
1142 invalidate_page(first);
1145 for(first=page+1;first<last;first++) {
1146 invalidate_page(first);
1152 // Don't trap writes
1153 invalid_code[block]=1;
1155 // If there is a valid TLB entry for this page, remove write protect
1156 if(tlb_LUT_w[block]) {
1157 assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1158 // CHECK: Is this right?
1159 memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1160 u_int real_block=tlb_LUT_w[block]>>12;
1161 invalid_code[real_block]=1;
1162 if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1164 else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
1168 memset(mini_ht,-1,sizeof(mini_ht));
1172 void invalidate_block(u_int block)
1174 u_int page=get_page(block<<12);
1175 u_int vpage=get_vpage(block<<12);
1176 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1177 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1180 struct ll_entry *head;
1181 head=jump_dirty[vpage];
1182 //printf("page=%d vpage=%d\n",page,vpage);
1185 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1186 get_bounds((int)head->addr,&start,&end);
1187 //printf("start: %x end: %x\n",start,end);
1188 if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) {
1189 if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1190 if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1191 if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1195 if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1196 if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1197 if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1198 if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1205 invalidate_block_range(block,first,last);
1208 void invalidate_addr(u_int addr)
1212 // this check is done by the caller
1213 //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
1214 u_int page=get_page(addr);
1215 if(page<2048) { // RAM
1216 struct ll_entry *head;
1217 u_int addr_min=~0, addr_max=0;
1218 int mask=RAM_SIZE-1;
1220 inv_code_start=addr&~0xfff;
1221 inv_code_end=addr|0xfff;
1224 // must check previous page too because of spans..
1226 inv_code_start-=0x1000;
1228 for(;pg1<=page;pg1++) {
1229 for(head=jump_dirty[pg1];head!=NULL;head=head->next) {
1231 get_bounds((int)head->addr,&start,&end);
1232 if((start&mask)<=(addr&mask)&&(addr&mask)<(end&mask)) {
1233 if(start<addr_min) addr_min=start;
1234 if(end>addr_max) addr_max=end;
1236 else if(addr<start) {
1237 if(start<inv_code_end)
1238 inv_code_end=start-1;
1241 if(end>inv_code_start)
1247 inv_debug("INV ADDR: %08x hit %08x-%08x\n", addr, addr_min, addr_max);
1248 inv_code_start=inv_code_end=~0;
1249 invalidate_block_range(addr>>12,(addr_min&mask)>>12,(addr_max&mask)>>12);
1253 inv_debug("INV ADDR: %08x miss, inv %08x-%08x, sk %d\n", addr, inv_code_start, inv_code_end, 0);//rhits);
1256 if(page!=0) // FIXME: don't know what's up with page 0 (Klonoa)
1260 invalidate_block(addr>>12);
1263 // This is called when loading a save state.
1264 // Anything could have changed, so invalidate everything.
1265 void invalidate_all_pages()
1268 for(page=0;page<4096;page++)
1269 invalidate_page(page);
1270 for(page=0;page<1048576;page++)
1271 if(!invalid_code[page]) {
1272 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1273 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1276 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1279 memset(mini_ht,-1,sizeof(mini_ht));
1283 for(page=0;page<0x100000;page++) {
1284 if(tlb_LUT_r[page]) {
1285 memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1286 if(!tlb_LUT_w[page]||!invalid_code[page])
1287 memory_map[page]|=0x40000000; // Write protect
1289 else memory_map[page]=-1;
1290 if(page==0x80000) page=0xC0000;
1296 // Add an entry to jump_out after making a link
1297 void add_link(u_int vaddr,void *src)
1299 u_int page=get_page(vaddr);
1300 inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1301 int *ptr=(int *)(src+4);
1302 assert((*ptr&0x0fff0000)==0x059f0000);
1303 ll_add(jump_out+page,vaddr,src);
1304 //int ptr=get_pointer(src);
1305 //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1308 // If a code block was found to be unmodified (bit was set in
1309 // restore_candidate) and it remains unmodified (bit is clear
1310 // in invalid_code) then move the entries for that 4K page from
1311 // the dirty list to the clean list.
1312 void clean_blocks(u_int page)
1314 struct ll_entry *head;
1315 inv_debug("INV: clean_blocks page=%d\n",page);
1316 head=jump_dirty[page];
1318 if(!invalid_code[head->vaddr>>12]) {
1319 // Don't restore blocks which are about to expire from the cache
1320 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1322 if(verify_dirty((int)head->addr)) {
1323 //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1326 get_bounds((int)head->addr,&start,&end);
1327 if(start-(u_int)rdram<RAM_SIZE) {
1328 for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1329 inv|=invalid_code[i];
1332 if((signed int)head->vaddr>=(signed int)0xC0000000) {
1333 u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1334 //printf("addr=%x start=%x end=%x\n",addr,start,end);
1335 if(addr<start||addr>=end) inv=1;
1337 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
1341 void * clean_addr=(void *)get_clean_addr((int)head->addr);
1342 if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1345 if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
1347 inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1348 //printf("page=%x, addr=%x\n",page,head->vaddr);
1349 //assert(head->vaddr>>12==(page|0x80000));
1350 ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1351 int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1353 if(ht_bin[0]==head->vaddr) {
1354 ht_bin[1]=(int)clean_addr; // Replace existing entry
1356 if(ht_bin[2]==head->vaddr) {
1357 ht_bin[3]=(int)clean_addr; // Replace existing entry
1370 void mov_alloc(struct regstat *current,int i)
1372 // Note: Don't need to actually alloc the source registers
1373 if((~current->is32>>rs1[i])&1) {
1374 //alloc_reg64(current,i,rs1[i]);
1375 alloc_reg64(current,i,rt1[i]);
1376 current->is32&=~(1LL<<rt1[i]);
1378 //alloc_reg(current,i,rs1[i]);
1379 alloc_reg(current,i,rt1[i]);
1380 current->is32|=(1LL<<rt1[i]);
1382 clear_const(current,rs1[i]);
1383 clear_const(current,rt1[i]);
1384 dirty_reg(current,rt1[i]);
1387 void shiftimm_alloc(struct regstat *current,int i)
1389 clear_const(current,rs1[i]);
1390 clear_const(current,rt1[i]);
1391 if(opcode2[i]<=0x3) // SLL/SRL/SRA
1394 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1396 alloc_reg(current,i,rt1[i]);
1397 current->is32|=1LL<<rt1[i];
1398 dirty_reg(current,rt1[i]);
1401 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1404 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1405 alloc_reg64(current,i,rt1[i]);
1406 current->is32&=~(1LL<<rt1[i]);
1407 dirty_reg(current,rt1[i]);
1410 if(opcode2[i]==0x3c) // DSLL32
1413 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1414 alloc_reg64(current,i,rt1[i]);
1415 current->is32&=~(1LL<<rt1[i]);
1416 dirty_reg(current,rt1[i]);
1419 if(opcode2[i]==0x3e) // DSRL32
1422 alloc_reg64(current,i,rs1[i]);
1424 alloc_reg64(current,i,rt1[i]);
1425 current->is32&=~(1LL<<rt1[i]);
1427 alloc_reg(current,i,rt1[i]);
1428 current->is32|=1LL<<rt1[i];
1430 dirty_reg(current,rt1[i]);
1433 if(opcode2[i]==0x3f) // DSRA32
1436 alloc_reg64(current,i,rs1[i]);
1437 alloc_reg(current,i,rt1[i]);
1438 current->is32|=1LL<<rt1[i];
1439 dirty_reg(current,rt1[i]);
1444 void shift_alloc(struct regstat *current,int i)
1447 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1449 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1450 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1451 alloc_reg(current,i,rt1[i]);
1452 if(rt1[i]==rs2[i]) {
1453 alloc_reg_temp(current,i,-1);
1454 minimum_free_regs[i]=1;
1456 current->is32|=1LL<<rt1[i];
1457 } else { // DSLLV/DSRLV/DSRAV
1458 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1459 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1460 alloc_reg64(current,i,rt1[i]);
1461 current->is32&=~(1LL<<rt1[i]);
1462 if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1464 alloc_reg_temp(current,i,-1);
1465 minimum_free_regs[i]=1;
1468 clear_const(current,rs1[i]);
1469 clear_const(current,rs2[i]);
1470 clear_const(current,rt1[i]);
1471 dirty_reg(current,rt1[i]);
1475 void alu_alloc(struct regstat *current,int i)
1477 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1479 if(rs1[i]&&rs2[i]) {
1480 alloc_reg(current,i,rs1[i]);
1481 alloc_reg(current,i,rs2[i]);
1484 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1485 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1487 alloc_reg(current,i,rt1[i]);
1489 current->is32|=1LL<<rt1[i];
1491 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1493 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1495 alloc_reg64(current,i,rs1[i]);
1496 alloc_reg64(current,i,rs2[i]);
1497 alloc_reg(current,i,rt1[i]);
1499 alloc_reg(current,i,rs1[i]);
1500 alloc_reg(current,i,rs2[i]);
1501 alloc_reg(current,i,rt1[i]);
1504 current->is32|=1LL<<rt1[i];
1506 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1508 if(rs1[i]&&rs2[i]) {
1509 alloc_reg(current,i,rs1[i]);
1510 alloc_reg(current,i,rs2[i]);
1514 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1515 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1517 alloc_reg(current,i,rt1[i]);
1518 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1520 if(!((current->uu>>rt1[i])&1)) {
1521 alloc_reg64(current,i,rt1[i]);
1523 if(get_reg(current->regmap,rt1[i]|64)>=0) {
1524 if(rs1[i]&&rs2[i]) {
1525 alloc_reg64(current,i,rs1[i]);
1526 alloc_reg64(current,i,rs2[i]);
1530 // Is is really worth it to keep 64-bit values in registers?
1532 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1533 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1537 current->is32&=~(1LL<<rt1[i]);
1539 current->is32|=1LL<<rt1[i];
1543 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1545 if(rs1[i]&&rs2[i]) {
1546 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1547 alloc_reg64(current,i,rs1[i]);
1548 alloc_reg64(current,i,rs2[i]);
1549 alloc_reg64(current,i,rt1[i]);
1551 alloc_reg(current,i,rs1[i]);
1552 alloc_reg(current,i,rs2[i]);
1553 alloc_reg(current,i,rt1[i]);
1557 alloc_reg(current,i,rt1[i]);
1558 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1559 // DADD used as move, or zeroing
1560 // If we have a 64-bit source, then make the target 64 bits too
1561 if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1562 if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1563 alloc_reg64(current,i,rt1[i]);
1564 } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1565 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1566 alloc_reg64(current,i,rt1[i]);
1568 if(opcode2[i]>=0x2e&&rs2[i]) {
1569 // DSUB used as negation - 64-bit result
1570 // If we have a 32-bit register, extend it to 64 bits
1571 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1572 alloc_reg64(current,i,rt1[i]);
1576 if(rs1[i]&&rs2[i]) {
1577 current->is32&=~(1LL<<rt1[i]);
1579 current->is32&=~(1LL<<rt1[i]);
1580 if((current->is32>>rs1[i])&1)
1581 current->is32|=1LL<<rt1[i];
1583 current->is32&=~(1LL<<rt1[i]);
1584 if((current->is32>>rs2[i])&1)
1585 current->is32|=1LL<<rt1[i];
1587 current->is32|=1LL<<rt1[i];
1591 clear_const(current,rs1[i]);
1592 clear_const(current,rs2[i]);
1593 clear_const(current,rt1[i]);
1594 dirty_reg(current,rt1[i]);
1597 void imm16_alloc(struct regstat *current,int i)
1599 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1601 if(rt1[i]) alloc_reg(current,i,rt1[i]);
1602 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1603 current->is32&=~(1LL<<rt1[i]);
1604 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1605 // TODO: Could preserve the 32-bit flag if the immediate is zero
1606 alloc_reg64(current,i,rt1[i]);
1607 alloc_reg64(current,i,rs1[i]);
1609 clear_const(current,rs1[i]);
1610 clear_const(current,rt1[i]);
1612 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1613 if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1614 current->is32|=1LL<<rt1[i];
1615 clear_const(current,rs1[i]);
1616 clear_const(current,rt1[i]);
1618 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1619 if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1620 if(rs1[i]!=rt1[i]) {
1621 if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1622 alloc_reg64(current,i,rt1[i]);
1623 current->is32&=~(1LL<<rt1[i]);
1626 else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1627 if(is_const(current,rs1[i])) {
1628 int v=get_const(current,rs1[i]);
1629 if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1630 if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1631 if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1633 else clear_const(current,rt1[i]);
1635 else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1636 if(is_const(current,rs1[i])) {
1637 int v=get_const(current,rs1[i]);
1638 set_const(current,rt1[i],v+imm[i]);
1640 else clear_const(current,rt1[i]);
1641 current->is32|=1LL<<rt1[i];
1644 set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1645 current->is32|=1LL<<rt1[i];
1647 dirty_reg(current,rt1[i]);
1650 void load_alloc(struct regstat *current,int i)
1652 clear_const(current,rt1[i]);
1653 //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1654 if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1655 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1656 if(rt1[i]&&!((current->u>>rt1[i])&1)) {
1657 alloc_reg(current,i,rt1[i]);
1658 assert(get_reg(current->regmap,rt1[i])>=0);
1659 if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1661 current->is32&=~(1LL<<rt1[i]);
1662 alloc_reg64(current,i,rt1[i]);
1664 else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1666 current->is32&=~(1LL<<rt1[i]);
1667 alloc_reg64(current,i,rt1[i]);
1668 alloc_all(current,i);
1669 alloc_reg64(current,i,FTEMP);
1670 minimum_free_regs[i]=HOST_REGS;
1672 else current->is32|=1LL<<rt1[i];
1673 dirty_reg(current,rt1[i]);
1674 // If using TLB, need a register for pointer to the mapping table
1675 if(using_tlb) alloc_reg(current,i,TLREG);
1676 // LWL/LWR need a temporary register for the old value
1677 if(opcode[i]==0x22||opcode[i]==0x26)
1679 alloc_reg(current,i,FTEMP);
1680 alloc_reg_temp(current,i,-1);
1681 minimum_free_regs[i]=1;
1686 // Load to r0 or unneeded register (dummy load)
1687 // but we still need a register to calculate the address
1688 if(opcode[i]==0x22||opcode[i]==0x26)
1690 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1692 // If using TLB, need a register for pointer to the mapping table
1693 if(using_tlb) alloc_reg(current,i,TLREG);
1694 alloc_reg_temp(current,i,-1);
1695 minimum_free_regs[i]=1;
1696 if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1698 alloc_all(current,i);
1699 alloc_reg64(current,i,FTEMP);
1700 minimum_free_regs[i]=HOST_REGS;
1705 void store_alloc(struct regstat *current,int i)
1707 clear_const(current,rs2[i]);
1708 if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1709 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1710 alloc_reg(current,i,rs2[i]);
1711 if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1712 alloc_reg64(current,i,rs2[i]);
1713 if(rs2[i]) alloc_reg(current,i,FTEMP);
1715 // If using TLB, need a register for pointer to the mapping table
1716 if(using_tlb) alloc_reg(current,i,TLREG);
1717 #if defined(HOST_IMM8)
1718 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1719 else alloc_reg(current,i,INVCP);
1721 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
1722 alloc_reg(current,i,FTEMP);
1724 // We need a temporary register for address generation
1725 alloc_reg_temp(current,i,-1);
1726 minimum_free_regs[i]=1;
1729 void c1ls_alloc(struct regstat *current,int i)
1731 //clear_const(current,rs1[i]); // FIXME
1732 clear_const(current,rt1[i]);
1733 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1734 alloc_reg(current,i,CSREG); // Status
1735 alloc_reg(current,i,FTEMP);
1736 if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1737 alloc_reg64(current,i,FTEMP);
1739 // If using TLB, need a register for pointer to the mapping table
1740 if(using_tlb) alloc_reg(current,i,TLREG);
1741 #if defined(HOST_IMM8)
1742 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1743 else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1744 alloc_reg(current,i,INVCP);
1746 // We need a temporary register for address generation
1747 alloc_reg_temp(current,i,-1);
1750 void c2ls_alloc(struct regstat *current,int i)
1752 clear_const(current,rt1[i]);
1753 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1754 alloc_reg(current,i,FTEMP);
1755 // If using TLB, need a register for pointer to the mapping table
1756 if(using_tlb) alloc_reg(current,i,TLREG);
1757 #if defined(HOST_IMM8)
1758 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1759 else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1760 alloc_reg(current,i,INVCP);
1762 // We need a temporary register for address generation
1763 alloc_reg_temp(current,i,-1);
1764 minimum_free_regs[i]=1;
1767 #ifndef multdiv_alloc
1768 void multdiv_alloc(struct regstat *current,int i)
1775 // case 0x1D: DMULTU
1778 clear_const(current,rs1[i]);
1779 clear_const(current,rs2[i]);
1782 if((opcode2[i]&4)==0) // 32-bit
1784 current->u&=~(1LL<<HIREG);
1785 current->u&=~(1LL<<LOREG);
1786 alloc_reg(current,i,HIREG);
1787 alloc_reg(current,i,LOREG);
1788 alloc_reg(current,i,rs1[i]);
1789 alloc_reg(current,i,rs2[i]);
1790 current->is32|=1LL<<HIREG;
1791 current->is32|=1LL<<LOREG;
1792 dirty_reg(current,HIREG);
1793 dirty_reg(current,LOREG);
1797 current->u&=~(1LL<<HIREG);
1798 current->u&=~(1LL<<LOREG);
1799 current->uu&=~(1LL<<HIREG);
1800 current->uu&=~(1LL<<LOREG);
1801 alloc_reg64(current,i,HIREG);
1802 //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1803 alloc_reg64(current,i,rs1[i]);
1804 alloc_reg64(current,i,rs2[i]);
1805 alloc_all(current,i);
1806 current->is32&=~(1LL<<HIREG);
1807 current->is32&=~(1LL<<LOREG);
1808 dirty_reg(current,HIREG);
1809 dirty_reg(current,LOREG);
1810 minimum_free_regs[i]=HOST_REGS;
1815 // Multiply by zero is zero.
1816 // MIPS does not have a divide by zero exception.
1817 // The result is undefined, we return zero.
1818 alloc_reg(current,i,HIREG);
1819 alloc_reg(current,i,LOREG);
1820 current->is32|=1LL<<HIREG;
1821 current->is32|=1LL<<LOREG;
1822 dirty_reg(current,HIREG);
1823 dirty_reg(current,LOREG);
1828 void cop0_alloc(struct regstat *current,int i)
1830 if(opcode2[i]==0) // MFC0
1833 clear_const(current,rt1[i]);
1834 alloc_all(current,i);
1835 alloc_reg(current,i,rt1[i]);
1836 current->is32|=1LL<<rt1[i];
1837 dirty_reg(current,rt1[i]);
1840 else if(opcode2[i]==4) // MTC0
1843 clear_const(current,rs1[i]);
1844 alloc_reg(current,i,rs1[i]);
1845 alloc_all(current,i);
1848 alloc_all(current,i); // FIXME: Keep r0
1850 alloc_reg(current,i,0);
1855 // TLBR/TLBWI/TLBWR/TLBP/ERET
1856 assert(opcode2[i]==0x10);
1857 alloc_all(current,i);
1859 minimum_free_regs[i]=HOST_REGS;
1862 void cop1_alloc(struct regstat *current,int i)
1864 alloc_reg(current,i,CSREG); // Load status
1865 if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1868 clear_const(current,rt1[i]);
1870 alloc_reg64(current,i,rt1[i]); // DMFC1
1871 current->is32&=~(1LL<<rt1[i]);
1873 alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1874 current->is32|=1LL<<rt1[i];
1876 dirty_reg(current,rt1[i]);
1878 alloc_reg_temp(current,i,-1);
1880 else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1883 clear_const(current,rs1[i]);
1885 alloc_reg64(current,i,rs1[i]); // DMTC1
1887 alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1888 alloc_reg_temp(current,i,-1);
1892 alloc_reg(current,i,0);
1893 alloc_reg_temp(current,i,-1);
1896 minimum_free_regs[i]=1;
1898 void fconv_alloc(struct regstat *current,int i)
1900 alloc_reg(current,i,CSREG); // Load status
1901 alloc_reg_temp(current,i,-1);
1902 minimum_free_regs[i]=1;
1904 void float_alloc(struct regstat *current,int i)
1906 alloc_reg(current,i,CSREG); // Load status
1907 alloc_reg_temp(current,i,-1);
1908 minimum_free_regs[i]=1;
1910 void c2op_alloc(struct regstat *current,int i)
1912 alloc_reg_temp(current,i,-1);
1914 void fcomp_alloc(struct regstat *current,int i)
1916 alloc_reg(current,i,CSREG); // Load status
1917 alloc_reg(current,i,FSREG); // Load flags
1918 dirty_reg(current,FSREG); // Flag will be modified
1919 alloc_reg_temp(current,i,-1);
1920 minimum_free_regs[i]=1;
1923 void syscall_alloc(struct regstat *current,int i)
1925 alloc_cc(current,i);
1926 dirty_reg(current,CCREG);
1927 alloc_all(current,i);
1928 minimum_free_regs[i]=HOST_REGS;
1932 void delayslot_alloc(struct regstat *current,int i)
1943 assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1);
1944 printf("Disabled speculative precompilation\n");
1948 imm16_alloc(current,i);
1952 load_alloc(current,i);
1956 store_alloc(current,i);
1959 alu_alloc(current,i);
1962 shift_alloc(current,i);
1965 multdiv_alloc(current,i);
1968 shiftimm_alloc(current,i);
1971 mov_alloc(current,i);
1974 cop0_alloc(current,i);
1978 cop1_alloc(current,i);
1981 c1ls_alloc(current,i);
1984 c2ls_alloc(current,i);
1987 fconv_alloc(current,i);
1990 float_alloc(current,i);
1993 fcomp_alloc(current,i);
1996 c2op_alloc(current,i);
2001 // Special case where a branch and delay slot span two pages in virtual memory
2002 static void pagespan_alloc(struct regstat *current,int i)
2005 current->wasconst=0;
2007 minimum_free_regs[i]=HOST_REGS;
2008 alloc_all(current,i);
2009 alloc_cc(current,i);
2010 dirty_reg(current,CCREG);
2011 if(opcode[i]==3) // JAL
2013 alloc_reg(current,i,31);
2014 dirty_reg(current,31);
2016 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
2018 alloc_reg(current,i,rs1[i]);
2020 alloc_reg(current,i,rt1[i]);
2021 dirty_reg(current,rt1[i]);
2024 if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
2026 if(rs1[i]) alloc_reg(current,i,rs1[i]);
2027 if(rs2[i]) alloc_reg(current,i,rs2[i]);
2028 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
2030 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2031 if(rs2[i]) alloc_reg64(current,i,rs2[i]);
2035 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
2037 if(rs1[i]) alloc_reg(current,i,rs1[i]);
2038 if(!((current->is32>>rs1[i])&1))
2040 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2044 if(opcode[i]==0x11) // BC1
2046 alloc_reg(current,i,FSREG);
2047 alloc_reg(current,i,CSREG);
2052 add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
2054 stubs[stubcount][0]=type;
2055 stubs[stubcount][1]=addr;
2056 stubs[stubcount][2]=retaddr;
2057 stubs[stubcount][3]=a;
2058 stubs[stubcount][4]=b;
2059 stubs[stubcount][5]=c;
2060 stubs[stubcount][6]=d;
2061 stubs[stubcount][7]=e;
2065 // Write out a single register
2066 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
2069 for(hr=0;hr<HOST_REGS;hr++) {
2070 if(hr!=EXCLUDE_REG) {
2071 if((regmap[hr]&63)==r) {
2074 emit_storereg(r,hr);
2076 if((is32>>regmap[hr])&1) {
2077 emit_sarimm(hr,31,hr);
2078 emit_storereg(r|64,hr);
2082 emit_storereg(r|64,hr);
2092 //if(!tracedebug) return 0;
2095 for(i=0;i<2097152;i++) {
2096 unsigned int temp=sum;
2099 sum^=((u_int *)rdram)[i];
2108 sum^=((u_int *)reg)[i];
2116 printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2118 #ifndef DISABLE_COP1
2121 printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2131 void memdebug(int i)
2133 //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2134 //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2137 //if(Count>=-2084597794) {
2138 if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2140 printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2141 //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2142 //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2145 printf("TRACE: %x\n",(&i)[-1]);
2149 printf("TRACE: %x \n",(&j)[10]);
2150 printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2154 //printf("TRACE: %x\n",(&i)[-1]);
2157 void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2159 printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2162 void alu_assemble(int i,struct regstat *i_regs)
2164 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2166 signed char s1,s2,t;
2167 t=get_reg(i_regs->regmap,rt1[i]);
2169 s1=get_reg(i_regs->regmap,rs1[i]);
2170 s2=get_reg(i_regs->regmap,rs2[i]);
2171 if(rs1[i]&&rs2[i]) {
2174 if(opcode2[i]&2) emit_sub(s1,s2,t);
2175 else emit_add(s1,s2,t);
2178 if(s1>=0) emit_mov(s1,t);
2179 else emit_loadreg(rs1[i],t);
2183 if(opcode2[i]&2) emit_neg(s2,t);
2184 else emit_mov(s2,t);
2187 emit_loadreg(rs2[i],t);
2188 if(opcode2[i]&2) emit_neg(t,t);
2191 else emit_zeroreg(t);
2195 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2197 signed char s1l,s2l,s1h,s2h,tl,th;
2198 tl=get_reg(i_regs->regmap,rt1[i]);
2199 th=get_reg(i_regs->regmap,rt1[i]|64);
2201 s1l=get_reg(i_regs->regmap,rs1[i]);
2202 s2l=get_reg(i_regs->regmap,rs2[i]);
2203 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2204 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2205 if(rs1[i]&&rs2[i]) {
2208 if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2209 else emit_adds(s1l,s2l,tl);
2211 #ifdef INVERTED_CARRY
2212 if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2214 if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2216 else emit_add(s1h,s2h,th);
2220 if(s1l>=0) emit_mov(s1l,tl);
2221 else emit_loadreg(rs1[i],tl);
2223 if(s1h>=0) emit_mov(s1h,th);
2224 else emit_loadreg(rs1[i]|64,th);
2229 if(opcode2[i]&2) emit_negs(s2l,tl);
2230 else emit_mov(s2l,tl);
2233 emit_loadreg(rs2[i],tl);
2234 if(opcode2[i]&2) emit_negs(tl,tl);
2237 #ifdef INVERTED_CARRY
2238 if(s2h>=0) emit_mov(s2h,th);
2239 else emit_loadreg(rs2[i]|64,th);
2241 emit_adcimm(-1,th); // x86 has inverted carry flag
2246 if(s2h>=0) emit_rscimm(s2h,0,th);
2248 emit_loadreg(rs2[i]|64,th);
2249 emit_rscimm(th,0,th);
2252 if(s2h>=0) emit_mov(s2h,th);
2253 else emit_loadreg(rs2[i]|64,th);
2260 if(th>=0) emit_zeroreg(th);
2265 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2267 signed char s1l,s1h,s2l,s2h,t;
2268 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2270 t=get_reg(i_regs->regmap,rt1[i]);
2273 s1l=get_reg(i_regs->regmap,rs1[i]);
2274 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2275 s2l=get_reg(i_regs->regmap,rs2[i]);
2276 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2277 if(rs2[i]==0) // rx<r0
2280 if(opcode2[i]==0x2a) // SLT
2281 emit_shrimm(s1h,31,t);
2282 else // SLTU (unsigned can not be less than zero)
2285 else if(rs1[i]==0) // r0<rx
2288 if(opcode2[i]==0x2a) // SLT
2289 emit_set_gz64_32(s2h,s2l,t);
2290 else // SLTU (set if not zero)
2291 emit_set_nz64_32(s2h,s2l,t);
2294 assert(s1l>=0);assert(s1h>=0);
2295 assert(s2l>=0);assert(s2h>=0);
2296 if(opcode2[i]==0x2a) // SLT
2297 emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2299 emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2303 t=get_reg(i_regs->regmap,rt1[i]);
2306 s1l=get_reg(i_regs->regmap,rs1[i]);
2307 s2l=get_reg(i_regs->regmap,rs2[i]);
2308 if(rs2[i]==0) // rx<r0
2311 if(opcode2[i]==0x2a) // SLT
2312 emit_shrimm(s1l,31,t);
2313 else // SLTU (unsigned can not be less than zero)
2316 else if(rs1[i]==0) // r0<rx
2319 if(opcode2[i]==0x2a) // SLT
2320 emit_set_gz32(s2l,t);
2321 else // SLTU (set if not zero)
2322 emit_set_nz32(s2l,t);
2325 assert(s1l>=0);assert(s2l>=0);
2326 if(opcode2[i]==0x2a) // SLT
2327 emit_set_if_less32(s1l,s2l,t);
2329 emit_set_if_carry32(s1l,s2l,t);
2335 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2337 signed char s1l,s1h,s2l,s2h,th,tl;
2338 tl=get_reg(i_regs->regmap,rt1[i]);
2339 th=get_reg(i_regs->regmap,rt1[i]|64);
2340 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2344 s1l=get_reg(i_regs->regmap,rs1[i]);
2345 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2346 s2l=get_reg(i_regs->regmap,rs2[i]);
2347 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2348 if(rs1[i]&&rs2[i]) {
2349 assert(s1l>=0);assert(s1h>=0);
2350 assert(s2l>=0);assert(s2h>=0);
2351 if(opcode2[i]==0x24) { // AND
2352 emit_and(s1l,s2l,tl);
2353 emit_and(s1h,s2h,th);
2355 if(opcode2[i]==0x25) { // OR
2356 emit_or(s1l,s2l,tl);
2357 emit_or(s1h,s2h,th);
2359 if(opcode2[i]==0x26) { // XOR
2360 emit_xor(s1l,s2l,tl);
2361 emit_xor(s1h,s2h,th);
2363 if(opcode2[i]==0x27) { // NOR
2364 emit_or(s1l,s2l,tl);
2365 emit_or(s1h,s2h,th);
2372 if(opcode2[i]==0x24) { // AND
2376 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2378 if(s1l>=0) emit_mov(s1l,tl);
2379 else emit_loadreg(rs1[i],tl);
2380 if(s1h>=0) emit_mov(s1h,th);
2381 else emit_loadreg(rs1[i]|64,th);
2385 if(s2l>=0) emit_mov(s2l,tl);
2386 else emit_loadreg(rs2[i],tl);
2387 if(s2h>=0) emit_mov(s2h,th);
2388 else emit_loadreg(rs2[i]|64,th);
2395 if(opcode2[i]==0x27) { // NOR
2397 if(s1l>=0) emit_not(s1l,tl);
2399 emit_loadreg(rs1[i],tl);
2402 if(s1h>=0) emit_not(s1h,th);
2404 emit_loadreg(rs1[i]|64,th);
2410 if(s2l>=0) emit_not(s2l,tl);
2412 emit_loadreg(rs2[i],tl);
2415 if(s2h>=0) emit_not(s2h,th);
2417 emit_loadreg(rs2[i]|64,th);
2433 s1l=get_reg(i_regs->regmap,rs1[i]);
2434 s2l=get_reg(i_regs->regmap,rs2[i]);
2435 if(rs1[i]&&rs2[i]) {
2438 if(opcode2[i]==0x24) { // AND
2439 emit_and(s1l,s2l,tl);
2441 if(opcode2[i]==0x25) { // OR
2442 emit_or(s1l,s2l,tl);
2444 if(opcode2[i]==0x26) { // XOR
2445 emit_xor(s1l,s2l,tl);
2447 if(opcode2[i]==0x27) { // NOR
2448 emit_or(s1l,s2l,tl);
2454 if(opcode2[i]==0x24) { // AND
2457 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2459 if(s1l>=0) emit_mov(s1l,tl);
2460 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2464 if(s2l>=0) emit_mov(s2l,tl);
2465 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2467 else emit_zeroreg(tl);
2469 if(opcode2[i]==0x27) { // NOR
2471 if(s1l>=0) emit_not(s1l,tl);
2473 emit_loadreg(rs1[i],tl);
2479 if(s2l>=0) emit_not(s2l,tl);
2481 emit_loadreg(rs2[i],tl);
2485 else emit_movimm(-1,tl);
2494 void imm16_assemble(int i,struct regstat *i_regs)
2496 if (opcode[i]==0x0f) { // LUI
2499 t=get_reg(i_regs->regmap,rt1[i]);
2502 if(!((i_regs->isconst>>t)&1))
2503 emit_movimm(imm[i]<<16,t);
2507 if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2510 t=get_reg(i_regs->regmap,rt1[i]);
2511 s=get_reg(i_regs->regmap,rs1[i]);
2516 if(!((i_regs->isconst>>t)&1)) {
2518 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2519 emit_addimm(t,imm[i],t);
2521 if(!((i_regs->wasconst>>s)&1))
2522 emit_addimm(s,imm[i],t);
2524 emit_movimm(constmap[i][s]+imm[i],t);
2530 if(!((i_regs->isconst>>t)&1))
2531 emit_movimm(imm[i],t);
2536 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2538 signed char sh,sl,th,tl;
2539 th=get_reg(i_regs->regmap,rt1[i]|64);
2540 tl=get_reg(i_regs->regmap,rt1[i]);
2541 sh=get_reg(i_regs->regmap,rs1[i]|64);
2542 sl=get_reg(i_regs->regmap,rs1[i]);
2548 emit_addimm64_32(sh,sl,imm[i],th,tl);
2551 emit_addimm(sl,imm[i],tl);
2554 emit_movimm(imm[i],tl);
2555 if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2560 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2562 //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2563 signed char sh,sl,t;
2564 t=get_reg(i_regs->regmap,rt1[i]);
2565 sh=get_reg(i_regs->regmap,rs1[i]|64);
2566 sl=get_reg(i_regs->regmap,rs1[i]);
2570 if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2571 if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2572 if(opcode[i]==0x0a) { // SLTI
2574 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2575 emit_slti32(t,imm[i],t);
2577 emit_slti32(sl,imm[i],t);
2582 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2583 emit_sltiu32(t,imm[i],t);
2585 emit_sltiu32(sl,imm[i],t);
2590 if(opcode[i]==0x0a) // SLTI
2591 emit_slti64_32(sh,sl,imm[i],t);
2593 emit_sltiu64_32(sh,sl,imm[i],t);
2596 // SLTI(U) with r0 is just stupid,
2597 // nonetheless examples can be found
2598 if(opcode[i]==0x0a) // SLTI
2599 if(0<imm[i]) emit_movimm(1,t);
2600 else emit_zeroreg(t);
2603 if(imm[i]) emit_movimm(1,t);
2604 else emit_zeroreg(t);
2610 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2612 signed char sh,sl,th,tl;
2613 th=get_reg(i_regs->regmap,rt1[i]|64);
2614 tl=get_reg(i_regs->regmap,rt1[i]);
2615 sh=get_reg(i_regs->regmap,rs1[i]|64);
2616 sl=get_reg(i_regs->regmap,rs1[i]);
2617 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2618 if(opcode[i]==0x0c) //ANDI
2622 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2623 emit_andimm(tl,imm[i],tl);
2625 if(!((i_regs->wasconst>>sl)&1))
2626 emit_andimm(sl,imm[i],tl);
2628 emit_movimm(constmap[i][sl]&imm[i],tl);
2633 if(th>=0) emit_zeroreg(th);
2639 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2643 emit_loadreg(rs1[i]|64,th);
2648 if(opcode[i]==0x0d) //ORI
2650 emit_orimm(tl,imm[i],tl);
2652 if(!((i_regs->wasconst>>sl)&1))
2653 emit_orimm(sl,imm[i],tl);
2655 emit_movimm(constmap[i][sl]|imm[i],tl);
2657 if(opcode[i]==0x0e) //XORI
2659 emit_xorimm(tl,imm[i],tl);
2661 if(!((i_regs->wasconst>>sl)&1))
2662 emit_xorimm(sl,imm[i],tl);
2664 emit_movimm(constmap[i][sl]^imm[i],tl);
2668 emit_movimm(imm[i],tl);
2669 if(th>=0) emit_zeroreg(th);
2677 void shiftimm_assemble(int i,struct regstat *i_regs)
2679 if(opcode2[i]<=0x3) // SLL/SRL/SRA
2683 t=get_reg(i_regs->regmap,rt1[i]);
2684 s=get_reg(i_regs->regmap,rs1[i]);
2693 if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2695 if(opcode2[i]==0) // SLL
2697 emit_shlimm(s<0?t:s,imm[i],t);
2699 if(opcode2[i]==2) // SRL
2701 emit_shrimm(s<0?t:s,imm[i],t);
2703 if(opcode2[i]==3) // SRA
2705 emit_sarimm(s<0?t:s,imm[i],t);
2709 if(s>=0 && s!=t) emit_mov(s,t);
2713 //emit_storereg(rt1[i],t); //DEBUG
2716 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2719 signed char sh,sl,th,tl;
2720 th=get_reg(i_regs->regmap,rt1[i]|64);
2721 tl=get_reg(i_regs->regmap,rt1[i]);
2722 sh=get_reg(i_regs->regmap,rs1[i]|64);
2723 sl=get_reg(i_regs->regmap,rs1[i]);
2728 if(th>=0) emit_zeroreg(th);
2735 if(opcode2[i]==0x38) // DSLL
2737 if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2738 emit_shlimm(sl,imm[i],tl);
2740 if(opcode2[i]==0x3a) // DSRL
2742 emit_shrdimm(sl,sh,imm[i],tl);
2743 if(th>=0) emit_shrimm(sh,imm[i],th);
2745 if(opcode2[i]==0x3b) // DSRA
2747 emit_shrdimm(sl,sh,imm[i],tl);
2748 if(th>=0) emit_sarimm(sh,imm[i],th);
2752 if(sl!=tl) emit_mov(sl,tl);
2753 if(th>=0&&sh!=th) emit_mov(sh,th);
2759 if(opcode2[i]==0x3c) // DSLL32
2762 signed char sl,tl,th;
2763 tl=get_reg(i_regs->regmap,rt1[i]);
2764 th=get_reg(i_regs->regmap,rt1[i]|64);
2765 sl=get_reg(i_regs->regmap,rs1[i]);
2774 emit_shlimm(th,imm[i]&31,th);
2779 if(opcode2[i]==0x3e) // DSRL32
2782 signed char sh,tl,th;
2783 tl=get_reg(i_regs->regmap,rt1[i]);
2784 th=get_reg(i_regs->regmap,rt1[i]|64);
2785 sh=get_reg(i_regs->regmap,rs1[i]|64);
2789 if(th>=0) emit_zeroreg(th);
2792 emit_shrimm(tl,imm[i]&31,tl);
2797 if(opcode2[i]==0x3f) // DSRA32
2801 tl=get_reg(i_regs->regmap,rt1[i]);
2802 sh=get_reg(i_regs->regmap,rs1[i]|64);
2808 emit_sarimm(tl,imm[i]&31,tl);
2815 #ifndef shift_assemble
2816 void shift_assemble(int i,struct regstat *i_regs)
2818 printf("Need shift_assemble for this architecture.\n");
2823 void load_assemble(int i,struct regstat *i_regs)
2825 int s,th,tl,addr,map=-1;
2828 int memtarget=0,c=0;
2829 int fastload_reg_override=0;
2831 th=get_reg(i_regs->regmap,rt1[i]|64);
2832 tl=get_reg(i_regs->regmap,rt1[i]);
2833 s=get_reg(i_regs->regmap,rs1[i]);
2835 for(hr=0;hr<HOST_REGS;hr++) {
2836 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2838 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2840 c=(i_regs->wasconst>>s)&1;
2842 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2843 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2846 //printf("load_assemble: c=%d\n",c);
2847 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2848 // FIXME: Even if the load is a NOP, we should check for pagefaults...
2850 if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2852 // could be FIFO, must perform the read
2854 assem_debug("(forced read)\n");
2855 tl=get_reg(i_regs->regmap,-1);
2859 if(offset||s<0||c) addr=tl;
2861 //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2863 //printf("load_assemble: c=%d\n",c);
2864 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2865 assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2867 if(th>=0) reglist&=~(1<<th);
2871 map=get_reg(i_regs->regmap,ROREG);
2872 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2874 //#define R29_HACK 1
2876 // Strmnnrmn's speed hack
2877 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2881 if(sp_in_mirror&&rs1[i]==29) {
2882 emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
2883 emit_cmpimm(HOST_TEMPREG,RAM_SIZE);
2884 fastload_reg_override=HOST_TEMPREG;
2888 emit_cmpimm(addr,RAM_SIZE);
2890 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2891 // Hint to branch predictor that the branch is unlikely to be taken
2893 emit_jno_unlikely(0);
2901 if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2902 if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2903 map=get_reg(i_regs->regmap,TLREG);
2906 map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2907 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2909 int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2910 if (opcode[i]==0x20) { // LB
2913 #ifdef HOST_IMM_ADDR32
2915 emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2919 //emit_xorimm(addr,3,tl);
2920 //gen_tlb_addr_r(tl,map);
2921 //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2923 #ifdef BIG_ENDIAN_MIPS
2924 if(!c) emit_xorimm(addr,3,tl);
2925 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2929 if(fastload_reg_override) a=fastload_reg_override;
2931 emit_movsbl_indexed_tlb(x,a,map,tl);
2935 add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2938 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2940 if (opcode[i]==0x21) { // LH
2943 #ifdef HOST_IMM_ADDR32
2945 emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2950 #ifdef BIG_ENDIAN_MIPS
2951 if(!c) emit_xorimm(addr,2,tl);
2952 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2956 if(fastload_reg_override) a=fastload_reg_override;
2958 //emit_movswl_indexed_tlb(x,tl,map,tl);
2961 gen_tlb_addr_r(a,map);
2962 emit_movswl_indexed(x,a,tl);
2965 emit_movswl_indexed(x,a,tl);
2967 emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
2973 add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2976 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2978 if (opcode[i]==0x23) { // LW
2982 if(fastload_reg_override) a=fastload_reg_override;
2983 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2984 #ifdef HOST_IMM_ADDR32
2986 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2989 emit_readword_indexed_tlb(0,a,map,tl);
2992 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2995 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2997 if (opcode[i]==0x24) { // LBU
3000 #ifdef HOST_IMM_ADDR32
3002 emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
3006 //emit_xorimm(addr,3,tl);
3007 //gen_tlb_addr_r(tl,map);
3008 //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
3010 #ifdef BIG_ENDIAN_MIPS
3011 if(!c) emit_xorimm(addr,3,tl);
3012 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3016 if(fastload_reg_override) a=fastload_reg_override;
3018 emit_movzbl_indexed_tlb(x,a,map,tl);
3022 add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3025 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3027 if (opcode[i]==0x25) { // LHU
3030 #ifdef HOST_IMM_ADDR32
3032 emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
3037 #ifdef BIG_ENDIAN_MIPS
3038 if(!c) emit_xorimm(addr,2,tl);
3039 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3043 if(fastload_reg_override) a=fastload_reg_override;
3045 //emit_movzwl_indexed_tlb(x,tl,map,tl);
3048 gen_tlb_addr_r(a,map);
3049 emit_movzwl_indexed(x,a,tl);
3052 emit_movzwl_indexed(x,a,tl);
3054 emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
3060 add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3063 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3065 if (opcode[i]==0x27) { // LWU
3070 if(fastload_reg_override) a=fastload_reg_override;
3071 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
3072 #ifdef HOST_IMM_ADDR32
3074 emit_readword_tlb(constmap[i][s]+offset,map,tl);
3077 emit_readword_indexed_tlb(0,a,map,tl);
3080 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3083 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3087 if (opcode[i]==0x37) { // LD
3091 if(fastload_reg_override) a=fastload_reg_override;
3092 //gen_tlb_addr_r(tl,map);
3093 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
3094 //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
3095 #ifdef HOST_IMM_ADDR32
3097 emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3100 emit_readdword_indexed_tlb(0,a,map,th,tl);
3103 add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3106 inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3109 //emit_storereg(rt1[i],tl); // DEBUG
3110 //if(opcode[i]==0x23)
3111 //if(opcode[i]==0x24)
3112 //if(opcode[i]==0x23||opcode[i]==0x24)
3113 /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
3117 emit_readword((int)&last_count,ECX);
3119 if(get_reg(i_regs->regmap,CCREG)<0)
3120 emit_loadreg(CCREG,HOST_CCREG);
3121 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3122 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3123 emit_writeword(HOST_CCREG,(int)&Count);
3126 if(get_reg(i_regs->regmap,CCREG)<0)
3127 emit_loadreg(CCREG,0);
3129 emit_mov(HOST_CCREG,0);
3131 emit_addimm(0,2*ccadj[i],0);
3132 emit_writeword(0,(int)&Count);
3134 emit_call((int)memdebug);
3136 restore_regs(0x100f);
3140 #ifndef loadlr_assemble
3141 void loadlr_assemble(int i,struct regstat *i_regs)
3143 printf("Need loadlr_assemble for this architecture.\n");
3148 void store_assemble(int i,struct regstat *i_regs)
3153 int jaddr=0,jaddr2,type;
3154 int memtarget=0,c=0;
3155 int agr=AGEN1+(i&1);
3156 int faststore_reg_override=0;
3158 th=get_reg(i_regs->regmap,rs2[i]|64);
3159 tl=get_reg(i_regs->regmap,rs2[i]);
3160 s=get_reg(i_regs->regmap,rs1[i]);
3161 temp=get_reg(i_regs->regmap,agr);
3162 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3165 c=(i_regs->wasconst>>s)&1;
3167 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3168 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3173 for(hr=0;hr<HOST_REGS;hr++) {
3174 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3176 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3177 if(offset||s<0||c) addr=temp;
3182 if(sp_in_mirror&&rs1[i]==29) {
3183 emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
3184 emit_cmpimm(HOST_TEMPREG,RAM_SIZE);
3185 faststore_reg_override=HOST_TEMPREG;
3190 // Strmnnrmn's speed hack
3191 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3193 emit_cmpimm(addr,RAM_SIZE);
3194 #ifdef DESTRUCTIVE_SHIFT
3195 if(s==addr) emit_mov(s,temp);
3199 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3203 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3204 // Hint to branch predictor that the branch is unlikely to be taken
3206 emit_jno_unlikely(0);
3214 if (opcode[i]==0x28) x=3; // SB
3215 if (opcode[i]==0x29) x=2; // SH
3216 map=get_reg(i_regs->regmap,TLREG);
3219 map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3220 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3223 if (opcode[i]==0x28) { // SB
3226 #ifdef BIG_ENDIAN_MIPS
3227 if(!c) emit_xorimm(addr,3,temp);
3228 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3232 if(faststore_reg_override) a=faststore_reg_override;
3233 //gen_tlb_addr_w(temp,map);
3234 //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3235 emit_writebyte_indexed_tlb(tl,x,a,map,a);
3239 if (opcode[i]==0x29) { // SH
3242 #ifdef BIG_ENDIAN_MIPS
3243 if(!c) emit_xorimm(addr,2,temp);
3244 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3248 if(faststore_reg_override) a=faststore_reg_override;
3250 //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3253 gen_tlb_addr_w(a,map);
3254 emit_writehword_indexed(tl,x,a);
3256 emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a);
3260 if (opcode[i]==0x2B) { // SW
3263 if(faststore_reg_override) a=faststore_reg_override;
3264 //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3265 emit_writeword_indexed_tlb(tl,0,a,map,temp);
3269 if (opcode[i]==0x3F) { // SD
3272 if(faststore_reg_override) a=faststore_reg_override;
3275 //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3276 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3277 emit_writedword_indexed_tlb(th,tl,0,a,map,temp);
3280 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3281 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3282 emit_writedword_indexed_tlb(tl,tl,0,a,map,temp);
3289 #ifdef DESTRUCTIVE_SHIFT
3290 // The x86 shift operation is 'destructive'; it overwrites the
3291 // source register, so we need to make a copy first and use that.
3294 #if defined(HOST_IMM8)
3295 int ir=get_reg(i_regs->regmap,INVCP);
3297 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3299 emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3301 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3302 emit_callne(invalidate_addr_reg[addr]);
3306 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3311 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3312 } else if(c&&!memtarget) {
3313 inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3315 //if(opcode[i]==0x2B || opcode[i]==0x3F)
3316 //if(opcode[i]==0x2B || opcode[i]==0x28)
3317 //if(opcode[i]==0x2B || opcode[i]==0x29)
3318 //if(opcode[i]==0x2B)
3319 /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3327 emit_readword((int)&last_count,ECX);
3329 if(get_reg(i_regs->regmap,CCREG)<0)
3330 emit_loadreg(CCREG,HOST_CCREG);
3331 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3332 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3333 emit_writeword(HOST_CCREG,(int)&Count);
3336 if(get_reg(i_regs->regmap,CCREG)<0)
3337 emit_loadreg(CCREG,0);
3339 emit_mov(HOST_CCREG,0);
3341 emit_addimm(0,2*ccadj[i],0);
3342 emit_writeword(0,(int)&Count);
3344 emit_call((int)memdebug);
3349 restore_regs(0x100f);
3354 void storelr_assemble(int i,struct regstat *i_regs)
3361 int case1,case2,case3;
3362 int done0,done1,done2;
3363 int memtarget=0,c=0;
3364 int agr=AGEN1+(i&1);
3366 th=get_reg(i_regs->regmap,rs2[i]|64);
3367 tl=get_reg(i_regs->regmap,rs2[i]);
3368 s=get_reg(i_regs->regmap,rs1[i]);
3369 temp=get_reg(i_regs->regmap,agr);
3370 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3373 c=(i_regs->isconst>>s)&1;
3375 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3376 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3380 for(hr=0;hr<HOST_REGS;hr++) {
3381 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3386 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3387 if(!offset&&s!=temp) emit_mov(s,temp);
3393 if(!memtarget||!rs1[i]) {
3399 int map=get_reg(i_regs->regmap,ROREG);
3400 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3401 gen_tlb_addr_w(temp,map);
3403 if((u_int)rdram!=0x80000000)
3404 emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3407 int map=get_reg(i_regs->regmap,TLREG);
3410 map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3411 if(!c&&!offset&&s>=0) emit_mov(s,temp);
3412 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3413 if(!jaddr&&!memtarget) {
3417 gen_tlb_addr_w(temp,map);
3420 if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3421 temp2=get_reg(i_regs->regmap,FTEMP);
3422 if(!rs2[i]) temp2=th=tl;
3425 #ifndef BIG_ENDIAN_MIPS
3426 emit_xorimm(temp,3,temp);
3428 emit_testimm(temp,2);
3431 emit_testimm(temp,1);
3435 if (opcode[i]==0x2A) { // SWL
3436 emit_writeword_indexed(tl,0,temp);
3438 if (opcode[i]==0x2E) { // SWR
3439 emit_writebyte_indexed(tl,3,temp);
3441 if (opcode[i]==0x2C) { // SDL
3442 emit_writeword_indexed(th,0,temp);
3443 if(rs2[i]) emit_mov(tl,temp2);
3445 if (opcode[i]==0x2D) { // SDR
3446 emit_writebyte_indexed(tl,3,temp);
3447 if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3452 set_jump_target(case1,(int)out);
3453 if (opcode[i]==0x2A) { // SWL
3454 // Write 3 msb into three least significant bytes
3455 if(rs2[i]) emit_rorimm(tl,8,tl);
3456 emit_writehword_indexed(tl,-1,temp);
3457 if(rs2[i]) emit_rorimm(tl,16,tl);
3458 emit_writebyte_indexed(tl,1,temp);
3459 if(rs2[i]) emit_rorimm(tl,8,tl);
3461 if (opcode[i]==0x2E) { // SWR
3462 // Write two lsb into two most significant bytes
3463 emit_writehword_indexed(tl,1,temp);
3465 if (opcode[i]==0x2C) { // SDL
3466 if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3467 // Write 3 msb into three least significant bytes
3468 if(rs2[i]) emit_rorimm(th,8,th);
3469 emit_writehword_indexed(th,-1,temp);
3470 if(rs2[i]) emit_rorimm(th,16,th);
3471 emit_writebyte_indexed(th,1,temp);
3472 if(rs2[i]) emit_rorimm(th,8,th);
3474 if (opcode[i]==0x2D) { // SDR
3475 if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3476 // Write two lsb into two most significant bytes
3477 emit_writehword_indexed(tl,1,temp);
3482 set_jump_target(case2,(int)out);
3483 emit_testimm(temp,1);
3486 if (opcode[i]==0x2A) { // SWL
3487 // Write two msb into two least significant bytes
3488 if(rs2[i]) emit_rorimm(tl,16,tl);
3489 emit_writehword_indexed(tl,-2,temp);
3490 if(rs2[i]) emit_rorimm(tl,16,tl);
3492 if (opcode[i]==0x2E) { // SWR
3493 // Write 3 lsb into three most significant bytes
3494 emit_writebyte_indexed(tl,-1,temp);
3495 if(rs2[i]) emit_rorimm(tl,8,tl);
3496 emit_writehword_indexed(tl,0,temp);
3497 if(rs2[i]) emit_rorimm(tl,24,tl);
3499 if (opcode[i]==0x2C) { // SDL
3500 if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3501 // Write two msb into two least significant bytes
3502 if(rs2[i]) emit_rorimm(th,16,th);
3503 emit_writehword_indexed(th,-2,temp);
3504 if(rs2[i]) emit_rorimm(th,16,th);
3506 if (opcode[i]==0x2D) { // SDR
3507 if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3508 // Write 3 lsb into three most significant bytes
3509 emit_writebyte_indexed(tl,-1,temp);
3510 if(rs2[i]) emit_rorimm(tl,8,tl);
3511 emit_writehword_indexed(tl,0,temp);
3512 if(rs2[i]) emit_rorimm(tl,24,tl);
3517 set_jump_target(case3,(int)out);
3518 if (opcode[i]==0x2A) { // SWL
3519 // Write msb into least significant byte
3520 if(rs2[i]) emit_rorimm(tl,24,tl);
3521 emit_writebyte_indexed(tl,-3,temp);
3522 if(rs2[i]) emit_rorimm(tl,8,tl);
3524 if (opcode[i]==0x2E) { // SWR
3525 // Write entire word
3526 emit_writeword_indexed(tl,-3,temp);
3528 if (opcode[i]==0x2C) { // SDL
3529 if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3530 // Write msb into least significant byte
3531 if(rs2[i]) emit_rorimm(th,24,th);
3532 emit_writebyte_indexed(th,-3,temp);
3533 if(rs2[i]) emit_rorimm(th,8,th);
3535 if (opcode[i]==0x2D) { // SDR
3536 if(rs2[i]) emit_mov(th,temp2);
3537 // Write entire word
3538 emit_writeword_indexed(tl,-3,temp);
3540 set_jump_target(done0,(int)out);
3541 set_jump_target(done1,(int)out);
3542 set_jump_target(done2,(int)out);
3543 if (opcode[i]==0x2C) { // SDL
3544 emit_testimm(temp,4);
3547 emit_andimm(temp,~3,temp);
3548 emit_writeword_indexed(temp2,4,temp);
3549 set_jump_target(done0,(int)out);
3551 if (opcode[i]==0x2D) { // SDR
3552 emit_testimm(temp,4);
3555 emit_andimm(temp,~3,temp);
3556 emit_writeword_indexed(temp2,-4,temp);
3557 set_jump_target(done0,(int)out);
3560 add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
3563 int map=get_reg(i_regs->regmap,ROREG);
3564 if(map<0) map=HOST_TEMPREG;
3565 gen_orig_addr_w(temp,map);
3567 emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
3569 #if defined(HOST_IMM8)
3570 int ir=get_reg(i_regs->regmap,INVCP);
3572 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3574 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3576 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3577 emit_callne(invalidate_addr_reg[temp]);
3581 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3586 //save_regs(0x100f);
3587 emit_readword((int)&last_count,ECX);
3588 if(get_reg(i_regs->regmap,CCREG)<0)
3589 emit_loadreg(CCREG,HOST_CCREG);
3590 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3591 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3592 emit_writeword(HOST_CCREG,(int)&Count);
3593 emit_call((int)memdebug);
3595 //restore_regs(0x100f);
3599 void c1ls_assemble(int i,struct regstat *i_regs)
3601 #ifndef DISABLE_COP1
3607 int jaddr,jaddr2=0,jaddr3,type;
3608 int agr=AGEN1+(i&1);
3610 th=get_reg(i_regs->regmap,FTEMP|64);
3611 tl=get_reg(i_regs->regmap,FTEMP);
3612 s=get_reg(i_regs->regmap,rs1[i]);
3613 temp=get_reg(i_regs->regmap,agr);
3614 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3619 for(hr=0;hr<HOST_REGS;hr++) {
3620 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3622 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3623 if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3625 // Loads use a temporary register which we need to save
3628 if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3632 //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3633 //else c=(i_regs->wasconst>>s)&1;
3634 if(s>=0) c=(i_regs->wasconst>>s)&1;
3635 // Check cop1 unusable
3637 signed char rs=get_reg(i_regs->regmap,CSREG);
3639 emit_testimm(rs,0x20000000);
3642 add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3645 if (opcode[i]==0x39) { // SWC1 (get float address)
3646 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],tl);
3648 if (opcode[i]==0x3D) { // SDC1 (get double address)
3649 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],tl);
3651 // Generate address + offset
3654 emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3658 map=get_reg(i_regs->regmap,TLREG);
3661 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3662 map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
3664 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3665 map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
3668 if (opcode[i]==0x39) { // SWC1 (read float)
3669 emit_readword_indexed(0,tl,tl);
3671 if (opcode[i]==0x3D) { // SDC1 (read double)
3672 emit_readword_indexed(4,tl,th);
3673 emit_readword_indexed(0,tl,tl);
3675 if (opcode[i]==0x31) { // LWC1 (get target address)
3676 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],temp);
3678 if (opcode[i]==0x35) { // LDC1 (get target address)
3679 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],temp);
3686 else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80000000+RAM_SIZE) {
3688 emit_jmp(0); // inline_readstub/inline_writestub? Very rare case
3690 #ifdef DESTRUCTIVE_SHIFT
3691 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3692 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3696 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3697 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3699 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3700 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3703 if (opcode[i]==0x31) { // LWC1
3704 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3705 //gen_tlb_addr_r(ar,map);
3706 //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3707 #ifdef HOST_IMM_ADDR32
3708 if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3711 emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3714 if (opcode[i]==0x35) { // LDC1
3716 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3717 //gen_tlb_addr_r(ar,map);
3718 //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3719 //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3720 #ifdef HOST_IMM_ADDR32
3721 if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3724 emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3727 if (opcode[i]==0x39) { // SWC1
3728 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3729 emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3732 if (opcode[i]==0x3D) { // SDC1
3734 //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3735 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3736 emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3740 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3741 #ifndef DESTRUCTIVE_SHIFT
3742 temp=offset||c||s<0?ar:s;
3744 #if defined(HOST_IMM8)
3745 int ir=get_reg(i_regs->regmap,INVCP);
3747 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3749 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3751 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3752 emit_callne(invalidate_addr_reg[temp]);
3756 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3760 if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3761 if (opcode[i]==0x31) { // LWC1 (write float)
3762 emit_writeword_indexed(tl,0,temp);
3764 if (opcode[i]==0x35) { // LDC1 (write double)
3765 emit_writeword_indexed(th,4,temp);
3766 emit_writeword_indexed(tl,0,temp);
3768 //if(opcode[i]==0x39)
3769 /*if(opcode[i]==0x39||opcode[i]==0x31)
3772 emit_readword((int)&last_count,ECX);
3773 if(get_reg(i_regs->regmap,CCREG)<0)
3774 emit_loadreg(CCREG,HOST_CCREG);
3775 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3776 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3777 emit_writeword(HOST_CCREG,(int)&Count);
3778 emit_call((int)memdebug);
3782 cop1_unusable(i, i_regs);
3786 void c2ls_assemble(int i,struct regstat *i_regs)
3791 int memtarget=0,c=0;
3792 int jaddr2=0,jaddr3,type;
3793 int agr=AGEN1+(i&1);
3795 u_int copr=(source[i]>>16)&0x1f;
3796 s=get_reg(i_regs->regmap,rs1[i]);
3797 tl=get_reg(i_regs->regmap,FTEMP);
3803 for(hr=0;hr<HOST_REGS;hr++) {
3804 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3806 if(i_regs->regmap[HOST_CCREG]==CCREG)
3807 reglist&=~(1<<HOST_CCREG);
3810 if (opcode[i]==0x3a) { // SWC2
3811 ar=get_reg(i_regs->regmap,agr);
3812 if(ar<0) ar=get_reg(i_regs->regmap,-1);
3817 if(s>=0) c=(i_regs->wasconst>>s)&1;
3818 memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
3819 if (!offset&&!c&&s>=0) ar=s;
3822 if (opcode[i]==0x3a) { // SWC2
3823 cop2_get_dreg(copr,tl,HOST_TEMPREG);
3831 emit_jmp(0); // inline_readstub/inline_writestub?
3835 emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3839 if (opcode[i]==0x32) { // LWC2
3840 #ifdef HOST_IMM_ADDR32
3841 if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
3844 emit_readword_indexed(0,ar,tl);
3846 if (opcode[i]==0x3a) { // SWC2
3847 #ifdef DESTRUCTIVE_SHIFT
3848 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3850 emit_writeword_indexed(tl,0,ar);
3854 add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist);
3855 if (opcode[i]==0x3a) { // SWC2
3856 #if defined(HOST_IMM8)
3857 int ir=get_reg(i_regs->regmap,INVCP);
3859 emit_cmpmem_indexedsr12_reg(ir,ar,1);
3861 emit_cmpmem_indexedsr12_imm((int)invalid_code,ar,1);
3863 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3864 emit_callne(invalidate_addr_reg[ar]);
3868 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),ar,0,0,0);
3871 if (opcode[i]==0x32) { // LWC2
3872 cop2_put_dreg(copr,tl,HOST_TEMPREG);
3876 #ifndef multdiv_assemble
3877 void multdiv_assemble(int i,struct regstat *i_regs)
3879 printf("Need multdiv_assemble for this architecture.\n");
3884 void mov_assemble(int i,struct regstat *i_regs)
3886 //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3887 //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
3889 signed char sh,sl,th,tl;
3890 th=get_reg(i_regs->regmap,rt1[i]|64);
3891 tl=get_reg(i_regs->regmap,rt1[i]);
3894 sh=get_reg(i_regs->regmap,rs1[i]|64);
3895 sl=get_reg(i_regs->regmap,rs1[i]);
3896 if(sl>=0) emit_mov(sl,tl);
3897 else emit_loadreg(rs1[i],tl);
3899 if(sh>=0) emit_mov(sh,th);
3900 else emit_loadreg(rs1[i]|64,th);
3906 #ifndef fconv_assemble
3907 void fconv_assemble(int i,struct regstat *i_regs)
3909 printf("Need fconv_assemble for this architecture.\n");
3915 void float_assemble(int i,struct regstat *i_regs)
3917 printf("Need float_assemble for this architecture.\n");
3922 void syscall_assemble(int i,struct regstat *i_regs)
3924 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3925 assert(ccreg==HOST_CCREG);
3926 assert(!is_delayslot);
3927 emit_movimm(start+i*4,EAX); // Get PC
3928 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
3929 emit_jmp((int)jump_syscall_hle); // XXX
3932 void hlecall_assemble(int i,struct regstat *i_regs)
3934 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3935 assert(ccreg==HOST_CCREG);
3936 assert(!is_delayslot);
3937 emit_movimm(start+i*4+4,0); // Get PC
3938 emit_movimm((int)psxHLEt[source[i]&7],1);
3939 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // XXX
3940 emit_jmp((int)jump_hlecall);
3943 void intcall_assemble(int i,struct regstat *i_regs)
3945 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3946 assert(ccreg==HOST_CCREG);
3947 assert(!is_delayslot);
3948 emit_movimm(start+i*4,0); // Get PC
3949 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG);
3950 emit_jmp((int)jump_intcall);
3953 void ds_assemble(int i,struct regstat *i_regs)
3958 alu_assemble(i,i_regs);break;
3960 imm16_assemble(i,i_regs);break;
3962 shift_assemble(i,i_regs);break;
3964 shiftimm_assemble(i,i_regs);break;
3966 load_assemble(i,i_regs);break;
3968 loadlr_assemble(i,i_regs);break;
3970 store_assemble(i,i_regs);break;
3972 storelr_assemble(i,i_regs);break;
3974 cop0_assemble(i,i_regs);break;
3976 cop1_assemble(i,i_regs);break;
3978 c1ls_assemble(i,i_regs);break;
3980 cop2_assemble(i,i_regs);break;
3982 c2ls_assemble(i,i_regs);break;
3984 c2op_assemble(i,i_regs);break;
3986 fconv_assemble(i,i_regs);break;
3988 float_assemble(i,i_regs);break;
3990 fcomp_assemble(i,i_regs);break;
3992 multdiv_assemble(i,i_regs);break;
3994 mov_assemble(i,i_regs);break;
4004 printf("Jump in the delay slot. This is probably a bug.\n");
4009 // Is the branch target a valid internal jump?
4010 int internal_branch(uint64_t i_is32,int addr)
4012 if(addr&1) return 0; // Indirect (register) jump
4013 if(addr>=start && addr<start+slen*4-4)
4015 int t=(addr-start)>>2;
4016 // Delay slots are not valid branch targets
4017 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4018 // 64 -> 32 bit transition requires a recompile
4019 /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
4021 if(requires_32bit[t]&~i_is32) printf("optimizable: no\n");
4022 else printf("optimizable: yes\n");
4024 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4026 if(requires_32bit[t]&~i_is32) return 0;
4034 #ifndef wb_invalidate
4035 void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
4036 uint64_t u,uint64_t uu)
4039 for(hr=0;hr<HOST_REGS;hr++) {
4040 if(hr!=EXCLUDE_REG) {
4041 if(pre[hr]!=entry[hr]) {
4044 if(get_reg(entry,pre[hr])<0) {
4046 if(!((u>>pre[hr])&1)) {
4047 emit_storereg(pre[hr],hr);
4048 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
4049 emit_sarimm(hr,31,hr);
4050 emit_storereg(pre[hr]|64,hr);
4054 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
4055 emit_storereg(pre[hr],hr);
4064 // Move from one register to another (no writeback)
4065 for(hr=0;hr<HOST_REGS;hr++) {
4066 if(hr!=EXCLUDE_REG) {
4067 if(pre[hr]!=entry[hr]) {
4068 if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
4070 if((nr=get_reg(entry,pre[hr]))>=0) {
4080 // Load the specified registers
4081 // This only loads the registers given as arguments because
4082 // we don't want to load things that will be overwritten
4083 void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
4087 for(hr=0;hr<HOST_REGS;hr++) {
4088 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4089 if(entry[hr]!=regmap[hr]) {
4090 if(regmap[hr]==rs1||regmap[hr]==rs2)
4097 emit_loadreg(regmap[hr],hr);
4104 for(hr=0;hr<HOST_REGS;hr++) {
4105 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4106 if(entry[hr]!=regmap[hr]) {
4107 if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
4109 assert(regmap[hr]!=64);
4110 if((is32>>(regmap[hr]&63))&1) {
4111 int lr=get_reg(regmap,regmap[hr]-64);
4113 emit_sarimm(lr,31,hr);
4115 emit_loadreg(regmap[hr],hr);
4119 emit_loadreg(regmap[hr],hr);
4127 // Load registers prior to the start of a loop
4128 // so that they are not loaded within the loop
4129 static void loop_preload(signed char pre[],signed char entry[])
4132 for(hr=0;hr<HOST_REGS;hr++) {
4133 if(hr!=EXCLUDE_REG) {
4134 if(pre[hr]!=entry[hr]) {
4136 if(get_reg(pre,entry[hr])<0) {
4137 assem_debug("loop preload:\n");
4138 //printf("loop preload: %d\n",hr);
4142 else if(entry[hr]<TEMPREG)
4144 emit_loadreg(entry[hr],hr);
4146 else if(entry[hr]-64<TEMPREG)
4148 emit_loadreg(entry[hr],hr);
4157 // Generate address for load/store instruction
4158 // goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
4159 void address_generation(int i,struct regstat *i_regs,signed char entry[])
4161 if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS||itype[i]==C2LS) {
4163 int agr=AGEN1+(i&1);
4164 int mgr=MGEN1+(i&1);
4165 if(itype[i]==LOAD) {
4166 ra=get_reg(i_regs->regmap,rt1[i]);
4167 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4170 if(itype[i]==LOADLR) {
4171 ra=get_reg(i_regs->regmap,FTEMP);
4173 if(itype[i]==STORE||itype[i]==STORELR) {
4174 ra=get_reg(i_regs->regmap,agr);
4175 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4177 if(itype[i]==C1LS||itype[i]==C2LS) {
4178 if ((opcode[i]&0x3b)==0x31||(opcode[i]&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
4179 ra=get_reg(i_regs->regmap,FTEMP);
4180 else { // SWC1/SDC1/SWC2/SDC2
4181 ra=get_reg(i_regs->regmap,agr);
4182 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4185 int rs=get_reg(i_regs->regmap,rs1[i]);
4186 int rm=get_reg(i_regs->regmap,TLREG);
4189 int c=(i_regs->wasconst>>rs)&1;
4191 // Using r0 as a base address
4193 if(!entry||entry[rm]!=mgr) {
4194 generate_map_const(offset,rm);
4195 } // else did it in the previous cycle
4197 if(!entry||entry[ra]!=agr) {
4198 if (opcode[i]==0x22||opcode[i]==0x26) {
4199 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4200 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4201 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4203 emit_movimm(offset,ra);
4205 } // else did it in the previous cycle
4208 if(!entry||entry[ra]!=rs1[i])
4209 emit_loadreg(rs1[i],ra);
4210 //if(!entry||entry[ra]!=rs1[i])
4211 // printf("poor load scheduling!\n");
4215 if(!entry||entry[rm]!=mgr) {
4216 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a) {
4217 // Stores to memory go thru the mapper to detect self-modifying
4218 // code, loads don't.
4219 if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
4220 (unsigned int)(constmap[i][rs]+offset)<0x80000000+RAM_SIZE )
4221 generate_map_const(constmap[i][rs]+offset,rm);
4223 if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
4224 generate_map_const(constmap[i][rs]+offset,rm);
4228 if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
4229 if(!entry||entry[ra]!=agr) {
4230 if (opcode[i]==0x22||opcode[i]==0x26) {
4231 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4232 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4233 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4235 #ifdef HOST_IMM_ADDR32
4236 if((itype[i]!=LOAD&&(opcode[i]&0x3b)!=0x31&&(opcode[i]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4237 (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
4239 emit_movimm(constmap[i][rs]+offset,ra);
4241 } // else did it in the previous cycle
4242 } // else load_consts already did it
4244 if(offset&&!c&&rs1[i]) {
4246 emit_addimm(rs,offset,ra);
4248 emit_addimm(ra,offset,ra);
4253 // Preload constants for next instruction
4254 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
4256 #ifndef HOST_IMM_ADDR32
4258 agr=MGEN1+((i+1)&1);
4259 ra=get_reg(i_regs->regmap,agr);
4261 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4262 int offset=imm[i+1];
4263 int c=(regs[i+1].wasconst>>rs)&1;
4265 if(itype[i+1]==STORE||itype[i+1]==STORELR
4266 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1, SWC2/SDC2
4267 // Stores to memory go thru the mapper to detect self-modifying
4268 // code, loads don't.
4269 if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
4270 (unsigned int)(constmap[i+1][rs]+offset)<0x80000000+RAM_SIZE )
4271 generate_map_const(constmap[i+1][rs]+offset,ra);
4273 if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
4274 generate_map_const(constmap[i+1][rs]+offset,ra);
4277 /*else if(rs1[i]==0) {
4278 generate_map_const(offset,ra);
4283 agr=AGEN1+((i+1)&1);
4284 ra=get_reg(i_regs->regmap,agr);
4286 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4287 int offset=imm[i+1];
4288 int c=(regs[i+1].wasconst>>rs)&1;
4289 if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
4290 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4291 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4292 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4293 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4295 #ifdef HOST_IMM_ADDR32
4296 if((itype[i+1]!=LOAD&&(opcode[i+1]&0x3b)!=0x31&&(opcode[i+1]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4297 (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000))
4299 emit_movimm(constmap[i+1][rs]+offset,ra);
4302 else if(rs1[i+1]==0) {
4303 // Using r0 as a base address
4304 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4305 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4306 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4307 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4309 emit_movimm(offset,ra);
4316 int get_final_value(int hr, int i, int *value)
4318 int reg=regs[i].regmap[hr];
4320 if(regs[i+1].regmap[hr]!=reg) break;
4321 if(!((regs[i+1].isconst>>hr)&1)) break;
4326 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
4327 *value=constmap[i][hr];
4331 if(itype[i+1]==UJUMP||itype[i+1]==RJUMP||itype[i+1]==CJUMP||itype[i+1]==SJUMP) {
4332 // Load in delay slot, out-of-order execution
4333 if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
4335 #ifdef HOST_IMM_ADDR32
4336 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+2])<(signed int)0xC0000000) return 0;
4338 // Precompute load address
4339 *value=constmap[i][hr]+imm[i+2];
4343 if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)
4345 #ifdef HOST_IMM_ADDR32
4346 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+1])<(signed int)0xC0000000) return 0;
4348 // Precompute load address
4349 *value=constmap[i][hr]+imm[i+1];
4350 //printf("c=%x imm=%x\n",(int)constmap[i][hr],imm[i+1]);
4355 *value=constmap[i][hr];
4356 //printf("c=%x\n",(int)constmap[i][hr]);
4357 if(i==slen-1) return 1;
4359 return !((unneeded_reg[i+1]>>reg)&1);
4361 return !((unneeded_reg_upper[i+1]>>reg)&1);
4365 // Load registers with known constants
4366 void load_consts(signed char pre[],signed char regmap[],int is32,int i)
4370 for(hr=0;hr<HOST_REGS;hr++) {
4371 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4372 //if(entry[hr]!=regmap[hr]) {
4373 if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4374 if(((regs[i].isconst>>hr)&1)&®map[hr]<64&®map[hr]>0) {
4376 if(get_final_value(hr,i,&value)) {
4381 emit_movimm(value,hr);
4389 for(hr=0;hr<HOST_REGS;hr++) {
4390 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4391 //if(entry[hr]!=regmap[hr]) {
4392 if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4393 if(((regs[i].isconst>>hr)&1)&®map[hr]>64) {
4394 if((is32>>(regmap[hr]&63))&1) {
4395 int lr=get_reg(regmap,regmap[hr]-64);
4397 emit_sarimm(lr,31,hr);
4402 if(get_final_value(hr,i,&value)) {
4407 emit_movimm(value,hr);
4416 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i)
4420 for(hr=0;hr<HOST_REGS;hr++) {
4421 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) {
4422 if(((regs[i].isconst>>hr)&1)&®map[hr]<64&®map[hr]>0) {
4423 int value=constmap[i][hr];
4428 emit_movimm(value,hr);
4434 for(hr=0;hr<HOST_REGS;hr++) {
4435 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) {
4436 if(((regs[i].isconst>>hr)&1)&®map[hr]>64) {
4437 if((is32>>(regmap[hr]&63))&1) {
4438 int lr=get_reg(regmap,regmap[hr]-64);
4440 emit_sarimm(lr,31,hr);
4444 int value=constmap[i][hr];
4449 emit_movimm(value,hr);
4457 // Write out all dirty registers (except cycle count)
4458 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty)
4461 for(hr=0;hr<HOST_REGS;hr++) {
4462 if(hr!=EXCLUDE_REG) {
4463 if(i_regmap[hr]>0) {
4464 if(i_regmap[hr]!=CCREG) {
4465 if((i_dirty>>hr)&1) {
4466 if(i_regmap[hr]<64) {
4467 emit_storereg(i_regmap[hr],hr);
4469 if( ((i_is32>>i_regmap[hr])&1) ) {
4470 #ifdef DESTRUCTIVE_WRITEBACK
4471 emit_sarimm(hr,31,hr);
4472 emit_storereg(i_regmap[hr]|64,hr);
4474 emit_sarimm(hr,31,HOST_TEMPREG);
4475 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4480 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4481 emit_storereg(i_regmap[hr],hr);
4490 // Write out dirty registers that we need to reload (pair with load_needed_regs)
4491 // This writes the registers not written by store_regs_bt
4492 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4495 int t=(addr-start)>>2;
4496 for(hr=0;hr<HOST_REGS;hr++) {
4497 if(hr!=EXCLUDE_REG) {
4498 if(i_regmap[hr]>0) {
4499 if(i_regmap[hr]!=CCREG) {
4500 if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1) && !(((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4501 if((i_dirty>>hr)&1) {
4502 if(i_regmap[hr]<64) {
4503 emit_storereg(i_regmap[hr],hr);
4505 if( ((i_is32>>i_regmap[hr])&1) ) {
4506 #ifdef DESTRUCTIVE_WRITEBACK
4507 emit_sarimm(hr,31,hr);
4508 emit_storereg(i_regmap[hr]|64,hr);
4510 emit_sarimm(hr,31,HOST_TEMPREG);
4511 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4516 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4517 emit_storereg(i_regmap[hr],hr);
4528 // Load all registers (except cycle count)
4529 void load_all_regs(signed char i_regmap[])
4532 for(hr=0;hr<HOST_REGS;hr++) {
4533 if(hr!=EXCLUDE_REG) {
4534 if(i_regmap[hr]==0) {
4538 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4540 emit_loadreg(i_regmap[hr],hr);
4546 // Load all current registers also needed by next instruction
4547 void load_needed_regs(signed char i_regmap[],signed char next_regmap[])
4550 for(hr=0;hr<HOST_REGS;hr++) {
4551 if(hr!=EXCLUDE_REG) {
4552 if(get_reg(next_regmap,i_regmap[hr])>=0) {
4553 if(i_regmap[hr]==0) {
4557 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4559 emit_loadreg(i_regmap[hr],hr);
4566 // Load all regs, storing cycle count if necessary
4567 void load_regs_entry(int t)
4570 if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER,HOST_CCREG);
4571 else if(ccadj[t]) emit_addimm(HOST_CCREG,-ccadj[t]*CLOCK_DIVIDER,HOST_CCREG);
4572 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4573 emit_storereg(CCREG,HOST_CCREG);
4576 for(hr=0;hr<HOST_REGS;hr++) {
4577 if(regs[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) {
4578 if(regs[t].regmap_entry[hr]==0) {
4581 else if(regs[t].regmap_entry[hr]!=CCREG)
4583 emit_loadreg(regs[t].regmap_entry[hr],hr);
4588 for(hr=0;hr<HOST_REGS;hr++) {
4589 if(regs[t].regmap_entry[hr]>=64&®s[t].regmap_entry[hr]<TEMPREG+64) {
4590 assert(regs[t].regmap_entry[hr]!=64);
4591 if((regs[t].was32>>(regs[t].regmap_entry[hr]&63))&1) {
4592 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4594 emit_loadreg(regs[t].regmap_entry[hr],hr);
4598 emit_sarimm(lr,31,hr);
4603 emit_loadreg(regs[t].regmap_entry[hr],hr);
4609 // Store dirty registers prior to branch
4610 void store_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4612 if(internal_branch(i_is32,addr))
4614 int t=(addr-start)>>2;
4616 for(hr=0;hr<HOST_REGS;hr++) {
4617 if(hr!=EXCLUDE_REG) {
4618 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4619 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4620 if((i_dirty>>hr)&1) {
4621 if(i_regmap[hr]<64) {
4622 if(!((unneeded_reg[t]>>i_regmap[hr])&1)) {
4623 emit_storereg(i_regmap[hr],hr);
4624 if( ((i_is32>>i_regmap[hr])&1) && !((unneeded_reg_upper[t]>>i_regmap[hr])&1) ) {
4625 #ifdef DESTRUCTIVE_WRITEBACK
4626 emit_sarimm(hr,31,hr);
4627 emit_storereg(i_regmap[hr]|64,hr);
4629 emit_sarimm(hr,31,HOST_TEMPREG);
4630 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4635 if( !((i_is32>>(i_regmap[hr]&63))&1) && !((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1) ) {
4636 emit_storereg(i_regmap[hr],hr);
4647 // Branch out of this block, write out all dirty regs
4648 wb_dirtys(i_regmap,i_is32,i_dirty);
4652 // Load all needed registers for branch target
4653 void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4655 //if(addr>=start && addr<(start+slen*4))
4656 if(internal_branch(i_is32,addr))
4658 int t=(addr-start)>>2;
4660 // Store the cycle count before loading something else
4661 if(i_regmap[HOST_CCREG]!=CCREG) {
4662 assert(i_regmap[HOST_CCREG]==-1);
4664 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4665 emit_storereg(CCREG,HOST_CCREG);
4668 for(hr=0;hr<HOST_REGS;hr++) {
4669 if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) {
4670 #ifdef DESTRUCTIVE_WRITEBACK
4671 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || ( !((regs[t].dirty>>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4673 if(i_regmap[hr]!=regs[t].regmap_entry[hr] ) {
4675 if(regs[t].regmap_entry[hr]==0) {
4678 else if(regs[t].regmap_entry[hr]!=CCREG)
4680 emit_loadreg(regs[t].regmap_entry[hr],hr);
4686 for(hr=0;hr<HOST_REGS;hr++) {
4687 if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=64&®s[t].regmap_entry[hr]<TEMPREG+64) {
4688 if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4689 assert(regs[t].regmap_entry[hr]!=64);
4690 if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4691 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4693 emit_loadreg(regs[t].regmap_entry[hr],hr);
4697 emit_sarimm(lr,31,hr);
4702 emit_loadreg(regs[t].regmap_entry[hr],hr);
4705 else if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4706 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4708 emit_sarimm(lr,31,hr);
4715 int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4717 if(addr>=start && addr<start+slen*4-4)
4719 int t=(addr-start)>>2;
4721 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4722 for(hr=0;hr<HOST_REGS;hr++)
4726 if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4728 if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
4735 if(i_regmap[hr]<TEMPREG)
4737 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4740 else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
4742 if(!((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1))
4747 else // Same register but is it 32-bit or dirty?
4750 if(!((regs[t].dirty>>hr)&1))
4754 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4756 //printf("%x: dirty no match\n",addr);
4761 if((((regs[t].was32^i_is32)&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)
4763 //printf("%x: is32 no match\n",addr);
4769 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4771 if(requires_32bit[t]&~i_is32) return 0;
4773 // Delay slots are not valid branch targets
4774 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4775 // Delay slots require additional processing, so do not match
4776 if(is_ds[t]) return 0;
4781 for(hr=0;hr<HOST_REGS;hr++)
4787 if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4801 // Used when a branch jumps into the delay slot of another branch
4802 void ds_assemble_entry(int i)
4804 int t=(ba[i]-start)>>2;
4805 if(!instr_addr[t]) instr_addr[t]=(u_int)out;
4806 assem_debug("Assemble delay slot at %x\n",ba[i]);
4807 assem_debug("<->\n");
4808 if(regs[t].regmap_entry[HOST_CCREG]==CCREG&®s[t].regmap[HOST_CCREG]!=CCREG)
4809 wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty,regs[t].was32);
4810 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,rs1[t],rs2[t]);
4811 address_generation(t,®s[t],regs[t].regmap_entry);
4812 if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39||(opcode[t]&0x3b)==0x3a)
4813 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,INVCP,INVCP);
4818 alu_assemble(t,®s[t]);break;
4820 imm16_assemble(t,®s[t]);break;
4822 shift_assemble(t,®s[t]);break;
4824 shiftimm_assemble(t,®s[t]);break;
4826 load_assemble(t,®s[t]);break;
4828 loadlr_assemble(t,®s[t]);break;
4830 store_assemble(t,®s[t]);break;
4832 storelr_assemble(t,®s[t]);break;
4834 cop0_assemble(t,®s[t]);break;
4836 cop1_assemble(t,®s[t]);break;
4838 c1ls_assemble(t,®s[t]);break;
4840 cop2_assemble(t,®s[t]);break;
4842 c2ls_assemble(t,®s[t]);break;
4844 c2op_assemble(t,®s[t]);break;
4846 fconv_assemble(t,®s[t]);break;
4848 float_assemble(t,®s[t]);break;
4850 fcomp_assemble(t,®s[t]);break;
4852 multdiv_assemble(t,®s[t]);break;
4854 mov_assemble(t,®s[t]);break;
4864 printf("Jump in the delay slot. This is probably a bug.\n");
4866 store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4867 load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4868 if(internal_branch(regs[t].is32,ba[i]+4))
4869 assem_debug("branch: internal\n");
4871 assem_debug("branch: external\n");
4872 assert(internal_branch(regs[t].is32,ba[i]+4));
4873 add_to_linker((int)out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4));
4877 void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
4886 //if(ba[i]>=start && ba[i]<(start+slen*4))
4887 if(internal_branch(branch_regs[i].is32,ba[i]))
4889 int t=(ba[i]-start)>>2;
4890 if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
4898 if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4900 if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
4902 //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4903 emit_andimm(HOST_CCREG,3,HOST_CCREG);
4907 else if(*adj==0||invert) {
4908 emit_addimm_and_set_flags(CLOCK_DIVIDER*(count+2),HOST_CCREG);
4914 emit_cmpimm(HOST_CCREG,-CLOCK_DIVIDER*(count+2));
4918 add_stub(CC_STUB,jaddr,idle?idle:(int)out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
4921 void do_ccstub(int n)
4924 assem_debug("do_ccstub %x\n",start+stubs[n][4]*4);
4925 set_jump_target(stubs[n][1],(int)out);
4927 if(stubs[n][6]==NULLDS) {
4928 // Delay slot instruction is nullified ("likely" branch)
4929 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
4931 else if(stubs[n][6]!=TAKEN) {
4932 wb_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty);
4935 if(internal_branch(branch_regs[i].is32,ba[i]))
4936 wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4940 // Save PC as return address
4941 emit_movimm(stubs[n][5],EAX);
4942 emit_writeword(EAX,(int)&pcaddr);
4946 // Return address depends on which way the branch goes
4947 if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
4949 int s1l=get_reg(branch_regs[i].regmap,rs1[i]);
4950 int s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
4951 int s2l=get_reg(branch_regs[i].regmap,rs2[i]);
4952 int s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
4962 if((branch_regs[i].is32>>rs1[i])&(branch_regs[i].is32>>rs2[i])&1) {
4966 #ifdef DESTRUCTIVE_WRITEBACK
4968 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1)
4969 emit_loadreg(rs1[i],s1l);
4972 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1)
4973 emit_loadreg(rs2[i],s1l);
4976 if((branch_regs[i].dirty>>s2l)&(branch_regs[i].is32>>rs2[i])&1)
4977 emit_loadreg(rs2[i],s2l);
4980 int addr=-1,alt=-1,ntaddr=-1;
4983 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4984 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4985 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4993 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4994 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4995 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5001 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
5005 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5006 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5007 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5013 assert(hr<HOST_REGS);
5015 if((opcode[i]&0x2f)==4) // BEQ
5017 #ifdef HAVE_CMOV_IMM
5019 if(s2l>=0) emit_cmp(s1l,s2l);
5020 else emit_test(s1l,s1l);
5021 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
5026 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5028 if(s2h>=0) emit_cmp(s1h,s2h);
5029 else emit_test(s1h,s1h);
5030 emit_cmovne_reg(alt,addr);
5032 if(s2l>=0) emit_cmp(s1l,s2l);
5033 else emit_test(s1l,s1l);
5034 emit_cmovne_reg(alt,addr);
5037 if((opcode[i]&0x2f)==5) // BNE
5039 #ifdef HAVE_CMOV_IMM
5041 if(s2l>=0) emit_cmp(s1l,s2l);
5042 else emit_test(s1l,s1l);
5043 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
5048 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
5050 if(s2h>=0) emit_cmp(s1h,s2h);
5051 else emit_test(s1h,s1h);
5052 emit_cmovne_reg(alt,addr);
5054 if(s2l>=0) emit_cmp(s1l,s2l);
5055 else emit_test(s1l,s1l);
5056 emit_cmovne_reg(alt,addr);
5059 if((opcode[i]&0x2f)==6) // BLEZ
5061 //emit_movimm(ba[i],alt);
5062 //emit_movimm(start+i*4+8,addr);
5063 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5065 if(s1h>=0) emit_mov(addr,ntaddr);
5066 emit_cmovl_reg(alt,addr);
5069 emit_cmovne_reg(ntaddr,addr);
5070 emit_cmovs_reg(alt,addr);
5073 if((opcode[i]&0x2f)==7) // BGTZ
5075 //emit_movimm(ba[i],addr);
5076 //emit_movimm(start+i*4+8,ntaddr);
5077 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
5079 if(s1h>=0) emit_mov(addr,alt);
5080 emit_cmovl_reg(ntaddr,addr);
5083 emit_cmovne_reg(alt,addr);
5084 emit_cmovs_reg(ntaddr,addr);
5087 if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ
5089 //emit_movimm(ba[i],alt);
5090 //emit_movimm(start+i*4+8,addr);
5091 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5092 if(s1h>=0) emit_test(s1h,s1h);
5093 else emit_test(s1l,s1l);
5094 emit_cmovs_reg(alt,addr);
5096 if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ
5098 //emit_movimm(ba[i],addr);
5099 //emit_movimm(start+i*4+8,alt);
5100 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5101 if(s1h>=0) emit_test(s1h,s1h);
5102 else emit_test(s1l,s1l);
5103 emit_cmovs_reg(alt,addr);
5105 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
5106 if(source[i]&0x10000) // BC1T
5108 //emit_movimm(ba[i],alt);
5109 //emit_movimm(start+i*4+8,addr);
5110 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5111 emit_testimm(s1l,0x800000);
5112 emit_cmovne_reg(alt,addr);
5116 //emit_movimm(ba[i],addr);
5117 //emit_movimm(start+i*4+8,alt);
5118 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5119 emit_testimm(s1l,0x800000);
5120 emit_cmovne_reg(alt,addr);
5123 emit_writeword(addr,(int)&pcaddr);
5128 int r=get_reg(branch_regs[i].regmap,rs1[i]);
5129 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5130 r=get_reg(branch_regs[i].regmap,RTEMP);
5132 emit_writeword(r,(int)&pcaddr);
5134 else {printf("Unknown branch type in do_ccstub\n");exit(1);}
5136 // Update cycle count
5137 assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
5138 if(stubs[n][3]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
5139 emit_call((int)cc_interrupt);
5140 if(stubs[n][3]) emit_addimm(HOST_CCREG,-CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
5141 if(stubs[n][6]==TAKEN) {
5142 if(internal_branch(branch_regs[i].is32,ba[i]))
5143 load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
5144 else if(itype[i]==RJUMP) {
5145 if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
5146 emit_readword((int)&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
5148 emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i]));
5150 }else if(stubs[n][6]==NOTTAKEN) {
5151 if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5152 else load_all_regs(branch_regs[i].regmap);
5153 }else if(stubs[n][6]==NULLDS) {
5154 // Delay slot instruction is nullified ("likely" branch)
5155 if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
5156 else load_all_regs(regs[i].regmap);
5158 load_all_regs(branch_regs[i].regmap);
5160 emit_jmp(stubs[n][2]); // return address
5162 /* This works but uses a lot of memory...
5163 emit_readword((int)&last_count,ECX);
5164 emit_add(HOST_CCREG,ECX,EAX);
5165 emit_writeword(EAX,(int)&Count);
5166 emit_call((int)gen_interupt);
5167 emit_readword((int)&Count,HOST_CCREG);
5168 emit_readword((int)&next_interupt,EAX);
5169 emit_readword((int)&pending_exception,EBX);
5170 emit_writeword(EAX,(int)&last_count);
5171 emit_sub(HOST_CCREG,EAX,HOST_CCREG);
5173 int jne_instr=(int)out;
5175 if(stubs[n][3]) emit_addimm(HOST_CCREG,-2*stubs[n][3],HOST_CCREG);
5176 load_all_regs(branch_regs[i].regmap);
5177 emit_jmp(stubs[n][2]); // return address
5178 set_jump_target(jne_instr,(int)out);
5179 emit_readword((int)&pcaddr,EAX);
5180 // Call get_addr_ht instead of doing the hash table here.
5181 // This code is executed infrequently and takes up a lot of space
5182 // so smaller is better.
5183 emit_storereg(CCREG,HOST_CCREG);
5185 emit_call((int)get_addr_ht);
5186 emit_loadreg(CCREG,HOST_CCREG);
5187 emit_addimm(ESP,4,ESP);
5191 add_to_linker(int addr,int target,int ext)
5193 link_addr[linkcount][0]=addr;
5194 link_addr[linkcount][1]=target;
5195 link_addr[linkcount][2]=ext;
5199 static void ujump_assemble_write_ra(int i)
5202 unsigned int return_address;
5203 rt=get_reg(branch_regs[i].regmap,31);
5204 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5206 return_address=start+i*4+8;
5209 if(internal_branch(branch_regs[i].is32,return_address)&&rt1[i+1]!=31) {
5210 int temp=-1; // note: must be ds-safe
5214 if(temp>=0) do_miniht_insert(return_address,rt,temp);
5215 else emit_movimm(return_address,rt);
5223 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5226 emit_movimm(return_address,rt); // PC into link register
5228 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5234 void ujump_assemble(int i,struct regstat *i_regs)
5236 signed char *i_regmap=i_regs->regmap;
5238 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5239 address_generation(i+1,i_regs,regs[i].regmap_entry);
5241 int temp=get_reg(branch_regs[i].regmap,PTEMP);
5242 if(rt1[i]==31&&temp>=0)
5244 int return_address=start+i*4+8;
5245 if(get_reg(branch_regs[i].regmap,31)>0)
5246 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5249 if(rt1[i]==31&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
5250 ujump_assemble_write_ra(i); // writeback ra for DS
5253 ds_assemble(i+1,i_regs);
5254 uint64_t bc_unneeded=branch_regs[i].u;
5255 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5256 bc_unneeded|=1|(1LL<<rt1[i]);
5257 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5258 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5259 bc_unneeded,bc_unneeded_upper);
5260 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5261 if(!ra_done&&rt1[i]==31)
5262 ujump_assemble_write_ra(i);
5264 cc=get_reg(branch_regs[i].regmap,CCREG);
5265 assert(cc==HOST_CCREG);
5266 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5268 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5270 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5271 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5272 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5273 if(internal_branch(branch_regs[i].is32,ba[i]))
5274 assem_debug("branch: internal\n");
5276 assem_debug("branch: external\n");
5277 if(internal_branch(branch_regs[i].is32,ba[i])&&is_ds[(ba[i]-start)>>2]) {
5278 ds_assemble_entry(i);
5281 add_to_linker((int)out,ba[i],internal_branch(branch_regs[i].is32,ba[i]));
5286 static void rjump_assemble_write_ra(int i)
5288 int rt,return_address;
5289 assert(rt1[i+1]!=rt1[i]);
5290 assert(rt2[i+1]!=rt1[i]);
5291 rt=get_reg(branch_regs[i].regmap,rt1[i]);
5292 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5294 return_address=start+i*4+8;
5298 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5301 emit_movimm(return_address,rt); // PC into link register
5303 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5307 void rjump_assemble(int i,struct regstat *i_regs)
5309 signed char *i_regmap=i_regs->regmap;
5313 rs=get_reg(branch_regs[i].regmap,rs1[i]);
5315 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5316 // Delay slot abuse, make a copy of the branch address register
5317 temp=get_reg(branch_regs[i].regmap,RTEMP);
5319 assert(regs[i].regmap[temp]==RTEMP);
5323 address_generation(i+1,i_regs,regs[i].regmap_entry);
5327 if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5328 int return_address=start+i*4+8;
5329 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5335 int rh=get_reg(regs[i].regmap,RHASH);
5336 if(rh>=0) do_preload_rhash(rh);
5339 if(rt1[i]!=0&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
5340 rjump_assemble_write_ra(i);
5343 ds_assemble(i+1,i_regs);
5344 uint64_t bc_unneeded=branch_regs[i].u;
5345 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5346 bc_unneeded|=1|(1LL<<rt1[i]);
5347 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5348 bc_unneeded&=~(1LL<<rs1[i]);
5349 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5350 bc_unneeded,bc_unneeded_upper);
5351 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
5352 if(!ra_done&&rt1[i]!=0)
5353 rjump_assemble_write_ra(i);
5354 cc=get_reg(branch_regs[i].regmap,CCREG);
5355 assert(cc==HOST_CCREG);
5357 int rh=get_reg(branch_regs[i].regmap,RHASH);
5358 int ht=get_reg(branch_regs[i].regmap,RHTBL);
5360 if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5361 do_preload_rhtbl(ht);
5365 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5366 #ifdef DESTRUCTIVE_WRITEBACK
5367 if((branch_regs[i].dirty>>rs)&(branch_regs[i].is32>>rs1[i])&1) {
5368 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
5369 emit_loadreg(rs1[i],rs);
5374 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5378 do_miniht_load(ht,rh);
5381 //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5382 //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5384 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5385 add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
5387 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5390 do_miniht_jump(rs,rh,ht);
5395 //if(rs!=EAX) emit_mov(rs,EAX);
5396 //emit_jmp((int)jump_vaddr_eax);
5397 emit_jmp(jump_vaddr_reg[rs]);
5402 emit_shrimm(rs,16,rs);
5403 emit_xor(temp,rs,rs);
5404 emit_movzwl_reg(rs,rs);
5405 emit_shlimm(rs,4,rs);
5406 emit_cmpmem_indexed((int)hash_table,rs,temp);
5407 emit_jne((int)out+14);
5408 emit_readword_indexed((int)hash_table+4,rs,rs);
5410 emit_cmpmem_indexed((int)hash_table+8,rs,temp);
5411 emit_addimm_no_flags(8,rs);
5412 emit_jeq((int)out-17);
5413 // No hit on hash table, call compiler
5416 #ifdef DEBUG_CYCLE_COUNT
5417 emit_readword((int)&last_count,ECX);
5418 emit_add(HOST_CCREG,ECX,HOST_CCREG);
5419 emit_readword((int)&next_interupt,ECX);
5420 emit_writeword(HOST_CCREG,(int)&Count);
5421 emit_sub(HOST_CCREG,ECX,HOST_CCREG);
5422 emit_writeword(ECX,(int)&last_count);
5425 emit_storereg(CCREG,HOST_CCREG);
5426 emit_call((int)get_addr);
5427 emit_loadreg(CCREG,HOST_CCREG);
5428 emit_addimm(ESP,4,ESP);
5430 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5431 if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5435 void cjump_assemble(int i,struct regstat *i_regs)
5437 signed char *i_regmap=i_regs->regmap;
5440 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5441 assem_debug("match=%d\n",match);
5442 int s1h,s1l,s2h,s2l;
5443 int prev_cop1_usable=cop1_usable;
5444 int unconditional=0,nop=0;
5447 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5448 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5449 if(!match) invert=1;
5450 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5451 if(i>(ba[i]-start)>>2) invert=1;
5455 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5456 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5457 s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5458 s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5461 s1l=get_reg(i_regmap,rs1[i]);
5462 s1h=get_reg(i_regmap,rs1[i]|64);
5463 s2l=get_reg(i_regmap,rs2[i]);
5464 s2h=get_reg(i_regmap,rs2[i]|64);
5466 if(rs1[i]==0&&rs2[i]==0)
5468 if(opcode[i]&1) nop=1;
5469 else unconditional=1;
5470 //assert(opcode[i]!=5);
5471 //assert(opcode[i]!=7);
5472 //assert(opcode[i]!=0x15);
5473 //assert(opcode[i]!=0x17);
5479 only32=(regs[i].was32>>rs2[i])&1;
5484 only32=(regs[i].was32>>rs1[i])&1;
5487 only32=(regs[i].was32>>rs1[i])&(regs[i].was32>>rs2[i])&1;
5491 // Out of order execution (delay slot first)
5493 address_generation(i+1,i_regs,regs[i].regmap_entry);
5494 ds_assemble(i+1,i_regs);
5496 uint64_t bc_unneeded=branch_regs[i].u;
5497 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5498 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5499 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5501 bc_unneeded_upper|=1;
5502 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5503 bc_unneeded,bc_unneeded_upper);
5504 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
5505 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5506 cc=get_reg(branch_regs[i].regmap,CCREG);
5507 assert(cc==HOST_CCREG);
5509 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5510 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5511 //assem_debug("cycle count (adj)\n");
5513 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5514 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5515 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5516 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5518 assem_debug("branch: internal\n");
5520 assem_debug("branch: external\n");
5521 if(internal&&is_ds[(ba[i]-start)>>2]) {
5522 ds_assemble_entry(i);
5525 add_to_linker((int)out,ba[i],internal);
5528 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5529 if(((u_int)out)&7) emit_addnop(0);
5534 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5537 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5540 int taken=0,nottaken=0,nottaken1=0;
5541 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5542 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5546 if(opcode[i]==4) // BEQ
5548 if(s2h>=0) emit_cmp(s1h,s2h);
5549 else emit_test(s1h,s1h);
5553 if(opcode[i]==5) // BNE
5555 if(s2h>=0) emit_cmp(s1h,s2h);
5556 else emit_test(s1h,s1h);
5557 if(invert) taken=(int)out;
5558 else add_to_linker((int)out,ba[i],internal);
5561 if(opcode[i]==6) // BLEZ
5564 if(invert) taken=(int)out;
5565 else add_to_linker((int)out,ba[i],internal);
5570 if(opcode[i]==7) // BGTZ
5575 if(invert) taken=(int)out;
5576 else add_to_linker((int)out,ba[i],internal);
5581 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5583 if(opcode[i]==4) // BEQ
5585 if(s2l>=0) emit_cmp(s1l,s2l);
5586 else emit_test(s1l,s1l);
5591 add_to_linker((int)out,ba[i],internal);
5595 if(opcode[i]==5) // BNE
5597 if(s2l>=0) emit_cmp(s1l,s2l);
5598 else emit_test(s1l,s1l);
5603 add_to_linker((int)out,ba[i],internal);
5607 if(opcode[i]==6) // BLEZ
5614 add_to_linker((int)out,ba[i],internal);
5618 if(opcode[i]==7) // BGTZ
5625 add_to_linker((int)out,ba[i],internal);
5630 if(taken) set_jump_target(taken,(int)out);
5631 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5632 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5634 emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5635 add_to_linker((int)out,ba[i],internal);
5638 add_to_linker((int)out,ba[i],internal*2);
5644 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5645 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5646 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5648 assem_debug("branch: internal\n");
5650 assem_debug("branch: external\n");
5651 if(internal&&is_ds[(ba[i]-start)>>2]) {
5652 ds_assemble_entry(i);
5655 add_to_linker((int)out,ba[i],internal);
5659 set_jump_target(nottaken,(int)out);
5662 if(nottaken1) set_jump_target(nottaken1,(int)out);
5664 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5666 } // (!unconditional)
5670 // In-order execution (branch first)
5671 //if(likely[i]) printf("IOL\n");
5674 int taken=0,nottaken=0,nottaken1=0;
5675 if(!unconditional&&!nop) {
5679 if((opcode[i]&0x2f)==4) // BEQ
5681 if(s2h>=0) emit_cmp(s1h,s2h);
5682 else emit_test(s1h,s1h);
5686 if((opcode[i]&0x2f)==5) // BNE
5688 if(s2h>=0) emit_cmp(s1h,s2h);
5689 else emit_test(s1h,s1h);
5693 if((opcode[i]&0x2f)==6) // BLEZ
5701 if((opcode[i]&0x2f)==7) // BGTZ
5711 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5713 if((opcode[i]&0x2f)==4) // BEQ
5715 if(s2l>=0) emit_cmp(s1l,s2l);
5716 else emit_test(s1l,s1l);
5720 if((opcode[i]&0x2f)==5) // BNE
5722 if(s2l>=0) emit_cmp(s1l,s2l);
5723 else emit_test(s1l,s1l);
5727 if((opcode[i]&0x2f)==6) // BLEZ
5733 if((opcode[i]&0x2f)==7) // BGTZ
5739 } // if(!unconditional)
5741 uint64_t ds_unneeded=branch_regs[i].u;
5742 uint64_t ds_unneeded_upper=branch_regs[i].uu;
5743 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5744 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5745 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5747 ds_unneeded_upper|=1;
5750 if(taken) set_jump_target(taken,(int)out);
5751 assem_debug("1:\n");
5752 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5753 ds_unneeded,ds_unneeded_upper);
5755 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5756 address_generation(i+1,&branch_regs[i],0);
5757 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5758 ds_assemble(i+1,&branch_regs[i]);
5759 cc=get_reg(branch_regs[i].regmap,CCREG);
5761 emit_loadreg(CCREG,cc=HOST_CCREG);
5762 // CHECK: Is the following instruction (fall thru) allocated ok?
5764 assert(cc==HOST_CCREG);
5765 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5766 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5767 assem_debug("cycle count (adj)\n");
5768 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5769 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5771 assem_debug("branch: internal\n");
5773 assem_debug("branch: external\n");
5774 if(internal&&is_ds[(ba[i]-start)>>2]) {
5775 ds_assemble_entry(i);
5778 add_to_linker((int)out,ba[i],internal);
5783 cop1_usable=prev_cop1_usable;
5784 if(!unconditional) {
5785 if(nottaken1) set_jump_target(nottaken1,(int)out);
5786 set_jump_target(nottaken,(int)out);
5787 assem_debug("2:\n");
5789 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5790 ds_unneeded,ds_unneeded_upper);
5791 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5792 address_generation(i+1,&branch_regs[i],0);
5793 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5794 ds_assemble(i+1,&branch_regs[i]);
5796 cc=get_reg(branch_regs[i].regmap,CCREG);
5797 if(cc==-1&&!likely[i]) {
5798 // Cycle count isn't in a register, temporarily load it then write it out
5799 emit_loadreg(CCREG,HOST_CCREG);
5800 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5803 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5804 emit_storereg(CCREG,HOST_CCREG);
5807 cc=get_reg(i_regmap,CCREG);
5808 assert(cc==HOST_CCREG);
5809 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5812 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5818 void sjump_assemble(int i,struct regstat *i_regs)
5820 signed char *i_regmap=i_regs->regmap;
5823 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5824 assem_debug("smatch=%d\n",match);
5826 int prev_cop1_usable=cop1_usable;
5827 int unconditional=0,nevertaken=0;
5830 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5831 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5832 if(!match) invert=1;
5833 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5834 if(i>(ba[i]-start)>>2) invert=1;
5837 //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
5838 //assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
5841 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5842 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5845 s1l=get_reg(i_regmap,rs1[i]);
5846 s1h=get_reg(i_regmap,rs1[i]|64);
5850 if(opcode2[i]&1) unconditional=1;
5852 // These are never taken (r0 is never less than zero)
5853 //assert(opcode2[i]!=0);
5854 //assert(opcode2[i]!=2);
5855 //assert(opcode2[i]!=0x10);
5856 //assert(opcode2[i]!=0x12);
5859 only32=(regs[i].was32>>rs1[i])&1;
5863 // Out of order execution (delay slot first)
5865 address_generation(i+1,i_regs,regs[i].regmap_entry);
5866 ds_assemble(i+1,i_regs);
5868 uint64_t bc_unneeded=branch_regs[i].u;
5869 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5870 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5871 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5873 bc_unneeded_upper|=1;
5874 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5875 bc_unneeded,bc_unneeded_upper);
5876 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5877 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5879 int rt,return_address;
5880 rt=get_reg(branch_regs[i].regmap,31);
5881 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5883 // Save the PC even if the branch is not taken
5884 return_address=start+i*4+8;
5885 emit_movimm(return_address,rt); // PC into link register
5887 if(!nevertaken) emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5891 cc=get_reg(branch_regs[i].regmap,CCREG);
5892 assert(cc==HOST_CCREG);
5894 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5895 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5896 assem_debug("cycle count (adj)\n");
5898 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5899 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5900 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5901 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5903 assem_debug("branch: internal\n");
5905 assem_debug("branch: external\n");
5906 if(internal&&is_ds[(ba[i]-start)>>2]) {
5907 ds_assemble_entry(i);
5910 add_to_linker((int)out,ba[i],internal);
5913 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5914 if(((u_int)out)&7) emit_addnop(0);
5918 else if(nevertaken) {
5919 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5922 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5926 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5927 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5931 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
5938 add_to_linker((int)out,ba[i],internal);
5942 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
5949 add_to_linker((int)out,ba[i],internal);
5957 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
5964 add_to_linker((int)out,ba[i],internal);
5968 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
5975 add_to_linker((int)out,ba[i],internal);
5982 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5983 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5985 emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5986 add_to_linker((int)out,ba[i],internal);
5989 add_to_linker((int)out,ba[i],internal*2);
5995 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5996 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5997 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5999 assem_debug("branch: internal\n");
6001 assem_debug("branch: external\n");
6002 if(internal&&is_ds[(ba[i]-start)>>2]) {
6003 ds_assemble_entry(i);
6006 add_to_linker((int)out,ba[i],internal);
6010 set_jump_target(nottaken,(int)out);
6014 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
6016 } // (!unconditional)
6020 // In-order execution (branch first)
6024 int rt,return_address;
6025 rt=get_reg(branch_regs[i].regmap,31);
6027 // Save the PC even if the branch is not taken
6028 return_address=start+i*4+8;
6029 emit_movimm(return_address,rt); // PC into link register
6031 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
6035 if(!unconditional) {
6036 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6040 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
6046 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
6056 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
6062 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
6069 } // if(!unconditional)
6071 uint64_t ds_unneeded=branch_regs[i].u;
6072 uint64_t ds_unneeded_upper=branch_regs[i].uu;
6073 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6074 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6075 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6077 ds_unneeded_upper|=1;
6080 //assem_debug("1:\n");
6081 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6082 ds_unneeded,ds_unneeded_upper);
6084 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6085 address_generation(i+1,&branch_regs[i],0);
6086 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6087 ds_assemble(i+1,&branch_regs[i]);
6088 cc=get_reg(branch_regs[i].regmap,CCREG);
6090 emit_loadreg(CCREG,cc=HOST_CCREG);
6091 // CHECK: Is the following instruction (fall thru) allocated ok?
6093 assert(cc==HOST_CCREG);
6094 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6095 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6096 assem_debug("cycle count (adj)\n");
6097 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6098 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6100 assem_debug("branch: internal\n");
6102 assem_debug("branch: external\n");
6103 if(internal&&is_ds[(ba[i]-start)>>2]) {
6104 ds_assemble_entry(i);
6107 add_to_linker((int)out,ba[i],internal);
6112 cop1_usable=prev_cop1_usable;
6113 if(!unconditional) {
6114 set_jump_target(nottaken,(int)out);
6115 assem_debug("1:\n");
6117 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6118 ds_unneeded,ds_unneeded_upper);
6119 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6120 address_generation(i+1,&branch_regs[i],0);
6121 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6122 ds_assemble(i+1,&branch_regs[i]);
6124 cc=get_reg(branch_regs[i].regmap,CCREG);
6125 if(cc==-1&&!likely[i]) {
6126 // Cycle count isn't in a register, temporarily load it then write it out
6127 emit_loadreg(CCREG,HOST_CCREG);
6128 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6131 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6132 emit_storereg(CCREG,HOST_CCREG);
6135 cc=get_reg(i_regmap,CCREG);
6136 assert(cc==HOST_CCREG);
6137 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
6140 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6146 void fjump_assemble(int i,struct regstat *i_regs)
6148 signed char *i_regmap=i_regs->regmap;
6151 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6152 assem_debug("fmatch=%d\n",match);
6156 int internal=internal_branch(branch_regs[i].is32,ba[i]);
6157 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
6158 if(!match) invert=1;
6159 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6160 if(i>(ba[i]-start)>>2) invert=1;
6164 fs=get_reg(branch_regs[i].regmap,FSREG);
6165 address_generation(i+1,i_regs,regs[i].regmap_entry); // Is this okay?
6168 fs=get_reg(i_regmap,FSREG);
6171 // Check cop1 unusable
6173 cs=get_reg(i_regmap,CSREG);
6175 emit_testimm(cs,0x20000000);
6178 add_stub(FP_STUB,eaddr,(int)out,i,cs,(int)i_regs,0,0);
6183 // Out of order execution (delay slot first)
6185 ds_assemble(i+1,i_regs);
6187 uint64_t bc_unneeded=branch_regs[i].u;
6188 uint64_t bc_unneeded_upper=branch_regs[i].uu;
6189 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6190 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
6192 bc_unneeded_upper|=1;
6193 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6194 bc_unneeded,bc_unneeded_upper);
6195 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
6196 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6197 cc=get_reg(branch_regs[i].regmap,CCREG);
6198 assert(cc==HOST_CCREG);
6199 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
6200 assem_debug("cycle count (adj)\n");
6203 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6206 emit_testimm(fs,0x800000);
6207 if(source[i]&0x10000) // BC1T
6213 add_to_linker((int)out,ba[i],internal);
6222 add_to_linker((int)out,ba[i],internal);
6230 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
6231 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6232 else if(match) emit_addnop(13);
6234 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6235 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6237 assem_debug("branch: internal\n");
6239 assem_debug("branch: external\n");
6240 if(internal&&is_ds[(ba[i]-start)>>2]) {
6241 ds_assemble_entry(i);
6244 add_to_linker((int)out,ba[i],internal);
6247 set_jump_target(nottaken,(int)out);
6251 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
6253 } // (!unconditional)
6257 // In-order execution (branch first)
6261 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6264 emit_testimm(fs,0x800000);
6265 if(source[i]&0x10000) // BC1T
6276 } // if(!unconditional)
6278 uint64_t ds_unneeded=branch_regs[i].u;
6279 uint64_t ds_unneeded_upper=branch_regs[i].uu;
6280 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6281 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6282 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6284 ds_unneeded_upper|=1;
6286 //assem_debug("1:\n");
6287 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6288 ds_unneeded,ds_unneeded_upper);
6290 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6291 address_generation(i+1,&branch_regs[i],0);
6292 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6293 ds_assemble(i+1,&branch_regs[i]);
6294 cc=get_reg(branch_regs[i].regmap,CCREG);
6296 emit_loadreg(CCREG,cc=HOST_CCREG);
6297 // CHECK: Is the following instruction (fall thru) allocated ok?
6299 assert(cc==HOST_CCREG);
6300 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6301 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6302 assem_debug("cycle count (adj)\n");
6303 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6304 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6306 assem_debug("branch: internal\n");
6308 assem_debug("branch: external\n");
6309 if(internal&&is_ds[(ba[i]-start)>>2]) {
6310 ds_assemble_entry(i);
6313 add_to_linker((int)out,ba[i],internal);
6318 if(1) { // <- FIXME (don't need this)
6319 set_jump_target(nottaken,(int)out);
6320 assem_debug("1:\n");
6322 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6323 ds_unneeded,ds_unneeded_upper);
6324 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6325 address_generation(i+1,&branch_regs[i],0);
6326 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6327 ds_assemble(i+1,&branch_regs[i]);
6329 cc=get_reg(branch_regs[i].regmap,CCREG);
6330 if(cc==-1&&!likely[i]) {
6331 // Cycle count isn't in a register, temporarily load it then write it out
6332 emit_loadreg(CCREG,HOST_CCREG);
6333 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6336 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6337 emit_storereg(CCREG,HOST_CCREG);
6340 cc=get_reg(i_regmap,CCREG);
6341 assert(cc==HOST_CCREG);
6342 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
6345 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6351 static void pagespan_assemble(int i,struct regstat *i_regs)
6353 int s1l=get_reg(i_regs->regmap,rs1[i]);
6354 int s1h=get_reg(i_regs->regmap,rs1[i]|64);
6355 int s2l=get_reg(i_regs->regmap,rs2[i]);
6356 int s2h=get_reg(i_regs->regmap,rs2[i]|64);
6357 void *nt_branch=NULL;
6360 int unconditional=0;
6370 if((i_regs->is32>>rs1[i])&(i_regs->is32>>rs2[i])&1) {
6374 int addr,alt,ntaddr;
6375 if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
6379 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
6380 (i_regs->regmap[hr]&63)!=rs1[i] &&
6381 (i_regs->regmap[hr]&63)!=rs2[i] )
6390 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6391 (i_regs->regmap[hr]&63)!=rs1[i] &&
6392 (i_regs->regmap[hr]&63)!=rs2[i] )
6398 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
6402 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6403 (i_regs->regmap[hr]&63)!=rs1[i] &&
6404 (i_regs->regmap[hr]&63)!=rs2[i] )
6411 assert(hr<HOST_REGS);
6412 if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
6413 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
6415 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6416 if(opcode[i]==2) // J
6420 if(opcode[i]==3) // JAL
6423 int rt=get_reg(i_regs->regmap,31);
6424 emit_movimm(start+i*4+8,rt);
6427 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
6430 if(opcode2[i]==9) // JALR
6432 int rt=get_reg(i_regs->regmap,rt1[i]);
6433 emit_movimm(start+i*4+8,rt);
6436 if((opcode[i]&0x3f)==4) // BEQ
6443 #ifdef HAVE_CMOV_IMM
6445 if(s2l>=0) emit_cmp(s1l,s2l);
6446 else emit_test(s1l,s1l);
6447 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
6453 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6455 if(s2h>=0) emit_cmp(s1h,s2h);
6456 else emit_test(s1h,s1h);
6457 emit_cmovne_reg(alt,addr);
6459 if(s2l>=0) emit_cmp(s1l,s2l);
6460 else emit_test(s1l,s1l);
6461 emit_cmovne_reg(alt,addr);
6464 if((opcode[i]&0x3f)==5) // BNE
6466 #ifdef HAVE_CMOV_IMM
6468 if(s2l>=0) emit_cmp(s1l,s2l);
6469 else emit_test(s1l,s1l);
6470 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
6476 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
6478 if(s2h>=0) emit_cmp(s1h,s2h);
6479 else emit_test(s1h,s1h);
6480 emit_cmovne_reg(alt,addr);
6482 if(s2l>=0) emit_cmp(s1l,s2l);
6483 else emit_test(s1l,s1l);
6484 emit_cmovne_reg(alt,addr);
6487 if((opcode[i]&0x3f)==0x14) // BEQL
6490 if(s2h>=0) emit_cmp(s1h,s2h);
6491 else emit_test(s1h,s1h);
6495 if(s2l>=0) emit_cmp(s1l,s2l);
6496 else emit_test(s1l,s1l);
6497 if(nottaken) set_jump_target(nottaken,(int)out);
6501 if((opcode[i]&0x3f)==0x15) // BNEL
6504 if(s2h>=0) emit_cmp(s1h,s2h);
6505 else emit_test(s1h,s1h);
6509 if(s2l>=0) emit_cmp(s1l,s2l);
6510 else emit_test(s1l,s1l);
6513 if(taken) set_jump_target(taken,(int)out);
6515 if((opcode[i]&0x3f)==6) // BLEZ
6517 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6519 if(s1h>=0) emit_mov(addr,ntaddr);
6520 emit_cmovl_reg(alt,addr);
6523 emit_cmovne_reg(ntaddr,addr);
6524 emit_cmovs_reg(alt,addr);
6527 if((opcode[i]&0x3f)==7) // BGTZ
6529 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
6531 if(s1h>=0) emit_mov(addr,alt);
6532 emit_cmovl_reg(ntaddr,addr);
6535 emit_cmovne_reg(alt,addr);
6536 emit_cmovs_reg(ntaddr,addr);
6539 if((opcode[i]&0x3f)==0x16) // BLEZL
6541 assert((opcode[i]&0x3f)!=0x16);
6543 if((opcode[i]&0x3f)==0x17) // BGTZL
6545 assert((opcode[i]&0x3f)!=0x17);
6547 assert(opcode[i]!=1); // BLTZ/BGEZ
6549 //FIXME: Check CSREG
6550 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
6551 if((source[i]&0x30000)==0) // BC1F
6553 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6554 emit_testimm(s1l,0x800000);
6555 emit_cmovne_reg(alt,addr);
6557 if((source[i]&0x30000)==0x10000) // BC1T
6559 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6560 emit_testimm(s1l,0x800000);
6561 emit_cmovne_reg(alt,addr);
6563 if((source[i]&0x30000)==0x20000) // BC1FL
6565 emit_testimm(s1l,0x800000);
6569 if((source[i]&0x30000)==0x30000) // BC1TL
6571 emit_testimm(s1l,0x800000);
6577 assert(i_regs->regmap[HOST_CCREG]==CCREG);
6578 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6579 if(likely[i]||unconditional)
6581 emit_movimm(ba[i],HOST_BTREG);
6583 else if(addr!=HOST_BTREG)
6585 emit_mov(addr,HOST_BTREG);
6587 void *branch_addr=out;
6589 int target_addr=start+i*4+5;
6591 void *compiled_target_addr=check_addr(target_addr);
6592 emit_extjump_ds((int)branch_addr,target_addr);
6593 if(compiled_target_addr) {
6594 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6595 add_link(target_addr,stub);
6597 else set_jump_target((int)branch_addr,(int)stub);
6600 set_jump_target((int)nottaken,(int)out);
6601 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6602 void *branch_addr=out;
6604 int target_addr=start+i*4+8;
6606 void *compiled_target_addr=check_addr(target_addr);
6607 emit_extjump_ds((int)branch_addr,target_addr);
6608 if(compiled_target_addr) {
6609 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6610 add_link(target_addr,stub);
6612 else set_jump_target((int)branch_addr,(int)stub);
6616 // Assemble the delay slot for the above
6617 static void pagespan_ds()
6619 assem_debug("initial delay slot:\n");
6620 u_int vaddr=start+1;
6621 u_int page=get_page(vaddr);
6622 u_int vpage=get_vpage(vaddr);
6623 ll_add(jump_dirty+vpage,vaddr,(void *)out);
6625 ll_add(jump_in+page,vaddr,(void *)out);
6626 assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6627 if(regs[0].regmap[HOST_CCREG]!=CCREG)
6628 wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty,regs[0].was32);
6629 if(regs[0].regmap[HOST_BTREG]!=BTREG)
6630 emit_writeword(HOST_BTREG,(int)&branch_target);
6631 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,rs1[0],rs2[0]);
6632 address_generation(0,®s[0],regs[0].regmap_entry);
6633 if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39||(opcode[0]&0x3b)==0x3a)
6634 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,INVCP,INVCP);
6639 alu_assemble(0,®s[0]);break;
6641 imm16_assemble(0,®s[0]);break;
6643 shift_assemble(0,®s[0]);break;
6645 shiftimm_assemble(0,®s[0]);break;
6647 load_assemble(0,®s[0]);break;
6649 loadlr_assemble(0,®s[0]);break;
6651 store_assemble(0,®s[0]);break;
6653 storelr_assemble(0,®s[0]);break;
6655 cop0_assemble(0,®s[0]);break;
6657 cop1_assemble(0,®s[0]);break;
6659 c1ls_assemble(0,®s[0]);break;
6661 cop2_assemble(0,®s[0]);break;
6663 c2ls_assemble(0,®s[0]);break;
6665 c2op_assemble(0,®s[0]);break;
6667 fconv_assemble(0,®s[0]);break;
6669 float_assemble(0,®s[0]);break;
6671 fcomp_assemble(0,®s[0]);break;
6673 multdiv_assemble(0,®s[0]);break;
6675 mov_assemble(0,®s[0]);break;
6685 printf("Jump in the delay slot. This is probably a bug.\n");
6687 int btaddr=get_reg(regs[0].regmap,BTREG);
6689 btaddr=get_reg(regs[0].regmap,-1);
6690 emit_readword((int)&branch_target,btaddr);
6692 assert(btaddr!=HOST_CCREG);
6693 if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6695 emit_movimm(start+4,HOST_TEMPREG);
6696 emit_cmp(btaddr,HOST_TEMPREG);
6698 emit_cmpimm(btaddr,start+4);
6700 int branch=(int)out;
6702 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,-1);
6703 emit_jmp(jump_vaddr_reg[btaddr]);
6704 set_jump_target(branch,(int)out);
6705 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6706 load_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6709 // Basic liveness analysis for MIPS registers
6710 void unneeded_registers(int istart,int iend,int r)
6714 uint64_t temp_u,temp_uu;
6719 u=unneeded_reg[iend+1];
6720 uu=unneeded_reg_upper[iend+1];
6723 for (i=iend;i>=istart;i--)
6725 //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
6726 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6728 // If subroutine call, flag return address as a possible branch target
6729 if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
6731 if(ba[i]<start || ba[i]>=(start+slen*4))
6733 // Branch out of this block, flush all regs
6737 if(itype[i]==UJUMP&&rt1[i]==31)
6739 uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
6741 if(itype[i]==RJUMP&&rs1[i]==31)
6743 uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9
6745 if(start>0x80000400&&start<0x80000000+RAM_SIZE) {
6746 if(itype[i]==UJUMP&&rt1[i]==31)
6748 //uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi
6749 uu=u=0x300FF0F; // Discard at, v0-v1, t0-t9
6751 if(itype[i]==RJUMP&&rs1[i]==31)
6753 //uu=u=0x30300FFF3LL; // Discard at, a0-a3, t0-t9, lo, hi
6754 uu=u=0x300FFF3; // Discard at, a0-a3, t0-t9
6757 branch_unneeded_reg[i]=u;
6758 branch_unneeded_reg_upper[i]=uu;
6759 // Merge in delay slot
6760 tdep=(~uu>>rt1[i+1])&1;
6761 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6762 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6763 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6764 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6765 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6767 // If branch is "likely" (and conditional)
6768 // then we skip the delay slot on the fall-thru path
6771 u&=unneeded_reg[i+2];
6772 uu&=unneeded_reg_upper[i+2];
6783 // Internal branch, flag target
6784 bt[(ba[i]-start)>>2]=1;
6785 if(ba[i]<=start+i*4) {
6787 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6789 // Unconditional branch
6792 // Conditional branch (not taken case)
6793 temp_u=unneeded_reg[i+2];
6794 temp_uu=unneeded_reg_upper[i+2];
6796 // Merge in delay slot
6797 tdep=(~temp_uu>>rt1[i+1])&1;
6798 temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6799 temp_uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6800 temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6801 temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6802 temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6803 temp_u|=1;temp_uu|=1;
6804 // If branch is "likely" (and conditional)
6805 // then we skip the delay slot on the fall-thru path
6808 temp_u&=unneeded_reg[i+2];
6809 temp_uu&=unneeded_reg_upper[i+2];
6817 tdep=(~temp_uu>>rt1[i])&1;
6818 temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6819 temp_uu|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6820 temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6821 temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
6822 temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i]));
6823 temp_u|=1;temp_uu|=1;
6824 unneeded_reg[i]=temp_u;
6825 unneeded_reg_upper[i]=temp_uu;
6826 // Only go three levels deep. This recursion can take an
6827 // excessive amount of time if there are a lot of nested loops.
6829 unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6831 unneeded_reg[(ba[i]-start)>>2]=1;
6832 unneeded_reg_upper[(ba[i]-start)>>2]=1;
6835 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6837 // Unconditional branch
6838 u=unneeded_reg[(ba[i]-start)>>2];
6839 uu=unneeded_reg_upper[(ba[i]-start)>>2];
6840 branch_unneeded_reg[i]=u;
6841 branch_unneeded_reg_upper[i]=uu;
6844 //branch_unneeded_reg[i]=u;
6845 //branch_unneeded_reg_upper[i]=uu;
6846 // Merge in delay slot
6847 tdep=(~uu>>rt1[i+1])&1;
6848 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6849 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6850 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6851 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6852 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6855 // Conditional branch
6856 b=unneeded_reg[(ba[i]-start)>>2];
6857 bu=unneeded_reg_upper[(ba[i]-start)>>2];
6858 branch_unneeded_reg[i]=b;
6859 branch_unneeded_reg_upper[i]=bu;
6862 //branch_unneeded_reg[i]=b;
6863 //branch_unneeded_reg_upper[i]=bu;
6864 // Branch delay slot
6865 tdep=(~uu>>rt1[i+1])&1;
6866 b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6867 bu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6868 b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6869 bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6870 bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6872 // If branch is "likely" then we skip the
6873 // delay slot on the fall-thru path
6878 u&=unneeded_reg[i+2];
6879 uu&=unneeded_reg_upper[i+2];
6890 branch_unneeded_reg[i]&=unneeded_reg[i+2];
6891 branch_unneeded_reg_upper[i]&=unneeded_reg_upper[i+2];
6892 //branch_unneeded_reg[i]=1;
6893 //branch_unneeded_reg_upper[i]=1;
6895 branch_unneeded_reg[i]=1;
6896 branch_unneeded_reg_upper[i]=1;
6902 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
6904 // SYSCALL instruction (software interrupt)
6908 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
6910 // ERET instruction (return from interrupt)
6915 tdep=(~uu>>rt1[i])&1;
6916 // Written registers are unneeded
6921 // Accessed registers are needed
6926 // Source-target dependencies
6927 uu&=~(tdep<<dep1[i]);
6928 uu&=~(tdep<<dep2[i]);
6929 // R0 is always unneeded
6933 unneeded_reg_upper[i]=uu;
6935 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
6938 for(r=1;r<=CCREG;r++) {
6939 if((unneeded_reg[i]>>r)&1) {
6940 if(r==HIREG) printf(" HI");
6941 else if(r==LOREG) printf(" LO");
6942 else printf(" r%d",r);
6946 for(r=1;r<=CCREG;r++) {
6947 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
6948 if(r==HIREG) printf(" HI");
6949 else if(r==LOREG) printf(" LO");
6950 else printf(" r%d",r);
6956 for (i=iend;i>=istart;i--)
6958 unneeded_reg_upper[i]=branch_unneeded_reg_upper[i]=-1LL;
6963 // Identify registers which are likely to contain 32-bit values
6964 // This is used to predict whether any branches will jump to a
6965 // location with 64-bit values in registers.
6966 static void provisional_32bit()
6970 uint64_t lastbranch=1;
6975 if(itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) {
6976 if(i>1) is32=lastbranch;
6982 if(itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP) {
6984 if(i>2) is32=lastbranch;
6988 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
6990 if(rs1[i-2]==0||rs2[i-2]==0)
6993 is32|=1LL<<rs1[i-2];
6996 is32|=1LL<<rs2[i-2];
7001 // If something jumps here with 64-bit values
7002 // then promote those registers to 64 bits
7005 uint64_t temp_is32=is32;
7008 if(ba[j]==start+i*4)
7009 //temp_is32&=branch_regs[j].is32;
7014 if(ba[j]==start+i*4)
7025 if(type==UJUMP||type==RJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
7026 // Branches don't write registers, consider the delay slot instead.
7037 if(opcode[i]==0x27||opcode[i]==0x37|| // LWU/LD
7038 opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
7047 if(op==0x1a||op==0x1b) is32&=~(1LL<<rt); // LDR/LDL
7048 if(op==0x22) is32|=1LL<<rt; // LWL
7051 if (op==0x08||op==0x09|| // ADDI/ADDIU
7052 op==0x0a||op==0x0b|| // SLTI/SLTIU
7058 if(op==0x18||op==0x19) { // DADDI/DADDIU
7061 // is32|=((is32>>s1)&1LL)<<rt;
7063 if(op==0x0d||op==0x0e) { // ORI/XORI
7064 uint64_t sr=((is32>>s1)&1LL);
7080 if(op2>=0x20&&op2<=0x23) { // ADD/ADDU/SUB/SUBU
7083 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
7086 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
7087 uint64_t sr=((is32>>s1)&(is32>>s2)&1LL);
7091 else if(op2>=0x2c&&op2<=0x2d) { // DADD/DADDU
7096 uint64_t sr=((is32>>s1)&1LL);
7101 uint64_t sr=((is32>>s2)&1LL);
7109 else if(op2>=0x2e&&op2<=0x2f) { // DSUB/DSUBU
7114 uint64_t sr=((is32>>s1)&1LL);
7124 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
7125 is32&=~((1LL<<HIREG)|(1LL<<LOREG));
7128 is32|=(1LL<<HIREG)|(1LL<<LOREG);
7133 uint64_t sr=((is32>>s1)&1LL);
7139 if(op2>=0x14&&op2<=0x17) is32&=~(1LL<<rt); // DSLLV/DSRLV/DSRAV
7140 else is32|=1LL<<rt; // SLLV/SRLV/SRAV
7144 // DSLL/DSRL/DSRA/DSLL32/DSRL32 but not DSRA32 have 64-bit result
7145 if(op2>=0x38&&op2<0x3f) is32&=~(1LL<<rt);
7148 if(op2==0) is32|=1LL<<rt; // MFC0
7152 if(op2==0) is32|=1LL<<rt; // MFC1
7153 if(op2==1) is32&=~(1LL<<rt); // DMFC1
7154 if(op2==2) is32|=1LL<<rt; // CFC1
7176 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
7178 if(rt1[i-1]==31) // JAL/JALR
7180 // Subroutine call will return here, don't alloc any registers
7185 // Internal branch will jump here, match registers to caller
7193 // Identify registers which may be assumed to contain 32-bit values
7194 // and where optimizations will rely on this.
7195 // This is used to determine whether backward branches can safely
7196 // jump to a location with 64-bit values in registers.
7197 static void provisional_r32()
7202 for (i=slen-1;i>=0;i--)
7205 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7207 if(ba[i]<start || ba[i]>=(start+slen*4))
7209 // Branch out of this block, don't need anything
7215 // Need whatever matches the target
7216 // (and doesn't get overwritten by the delay slot instruction)
7218 int t=(ba[i]-start)>>2;
7219 if(ba[i]>start+i*4) {
7221 //if(!(requires_32bit[t]&~regs[i].was32))
7222 // r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7223 if(!(pr32[t]&~regs[i].was32))
7224 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7227 if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
7228 r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7231 // Conditional branch may need registers for following instructions
7232 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
7235 //r32|=requires_32bit[i+2];
7238 // Mark this address as a branch target since it may be called
7239 // upon return from interrupt
7243 // Merge in delay slot
7245 // These are overwritten unless the branch is "likely"
7246 // and the delay slot is nullified if not taken
7247 r32&=~(1LL<<rt1[i+1]);
7248 r32&=~(1LL<<rt2[i+1]);
7250 // Assume these are needed (delay slot)
7253 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
7257 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
7259 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
7261 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
7263 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
7265 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
7268 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7270 // SYSCALL instruction (software interrupt)
7273 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7275 // ERET instruction (return from interrupt)
7279 r32&=~(1LL<<rt1[i]);
7280 r32&=~(1LL<<rt2[i]);
7283 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
7287 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
7289 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
7291 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
7293 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
7295 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
7297 //requires_32bit[i]=r32;
7300 // Dirty registers which are 32-bit, require 32-bit input
7301 // as they will be written as 32-bit values
7302 for(hr=0;hr<HOST_REGS;hr++)
7304 if(regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64) {
7305 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
7306 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
7307 pr32[i]|=1LL<<regs[i].regmap_entry[hr];
7308 //requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
7315 // Write back dirty registers as soon as we will no longer modify them,
7316 // so that we don't end up with lots of writes at the branches.
7317 void clean_registers(int istart,int iend,int wr)
7321 u_int will_dirty_i,will_dirty_next,temp_will_dirty;
7322 u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
7324 will_dirty_i=will_dirty_next=0;
7325 wont_dirty_i=wont_dirty_next=0;
7327 will_dirty_i=will_dirty_next=will_dirty[iend+1];
7328 wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
7330 for (i=iend;i>=istart;i--)
7332 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7334 if(ba[i]<start || ba[i]>=(start+slen*4))
7336 // Branch out of this block, flush all regs
7337 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7339 // Unconditional branch
7342 // Merge in delay slot (will dirty)
7343 for(r=0;r<HOST_REGS;r++) {
7344 if(r!=EXCLUDE_REG) {
7345 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7346 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7347 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7348 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7349 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7350 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7351 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7352 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7353 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7354 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7355 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7356 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7357 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7358 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7364 // Conditional branch
7366 wont_dirty_i=wont_dirty_next;
7367 // Merge in delay slot (will dirty)
7368 for(r=0;r<HOST_REGS;r++) {
7369 if(r!=EXCLUDE_REG) {
7371 // Might not dirty if likely branch is not taken
7372 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7373 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7374 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7375 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7376 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7377 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
7378 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7379 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7380 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7381 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7382 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7383 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7384 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7385 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7390 // Merge in delay slot (wont dirty)
7391 for(r=0;r<HOST_REGS;r++) {
7392 if(r!=EXCLUDE_REG) {
7393 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7394 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7395 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7396 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7397 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7398 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7399 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7400 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7401 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7402 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7406 #ifndef DESTRUCTIVE_WRITEBACK
7407 branch_regs[i].dirty&=wont_dirty_i;
7409 branch_regs[i].dirty|=will_dirty_i;
7415 if(ba[i]<=start+i*4) {
7417 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7419 // Unconditional branch
7422 // Merge in delay slot (will dirty)
7423 for(r=0;r<HOST_REGS;r++) {
7424 if(r!=EXCLUDE_REG) {
7425 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7426 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7427 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7428 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7429 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7430 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7431 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7432 if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7433 if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7434 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7435 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7436 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7437 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7438 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7442 // Conditional branch (not taken case)
7443 temp_will_dirty=will_dirty_next;
7444 temp_wont_dirty=wont_dirty_next;
7445 // Merge in delay slot (will dirty)
7446 for(r=0;r<HOST_REGS;r++) {
7447 if(r!=EXCLUDE_REG) {
7449 // Will not dirty if likely branch is not taken
7450 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7451 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7452 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7453 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7454 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7455 if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
7456 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7457 //if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7458 //if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7459 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7460 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7461 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7462 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7463 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7468 // Merge in delay slot (wont dirty)
7469 for(r=0;r<HOST_REGS;r++) {
7470 if(r!=EXCLUDE_REG) {
7471 if((regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7472 if((regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7473 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7474 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7475 if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7476 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7477 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7478 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7479 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7480 if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7483 // Deal with changed mappings
7485 for(r=0;r<HOST_REGS;r++) {
7486 if(r!=EXCLUDE_REG) {
7487 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
7488 temp_will_dirty&=~(1<<r);
7489 temp_wont_dirty&=~(1<<r);
7490 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7491 temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7492 temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7494 temp_will_dirty|=1<<r;
7495 temp_wont_dirty|=1<<r;
7502 will_dirty[i]=temp_will_dirty;
7503 wont_dirty[i]=temp_wont_dirty;
7504 clean_registers((ba[i]-start)>>2,i-1,0);
7506 // Limit recursion. It can take an excessive amount
7507 // of time if there are a lot of nested loops.
7508 will_dirty[(ba[i]-start)>>2]=0;
7509 wont_dirty[(ba[i]-start)>>2]=-1;
7514 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7516 // Unconditional branch
7519 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7520 for(r=0;r<HOST_REGS;r++) {
7521 if(r!=EXCLUDE_REG) {
7522 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7523 will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
7524 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7526 if(branch_regs[i].regmap[r]>=0) {
7527 will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7528 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7533 // Merge in delay slot
7534 for(r=0;r<HOST_REGS;r++) {
7535 if(r!=EXCLUDE_REG) {
7536 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7537 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7538 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7539 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7540 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7541 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7542 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7543 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7544 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7545 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7546 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7547 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7548 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7549 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7553 // Conditional branch
7554 will_dirty_i=will_dirty_next;
7555 wont_dirty_i=wont_dirty_next;
7556 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7557 for(r=0;r<HOST_REGS;r++) {
7558 if(r!=EXCLUDE_REG) {
7559 signed char target_reg=branch_regs[i].regmap[r];
7560 if(target_reg==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7561 will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7562 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7564 else if(target_reg>=0) {
7565 will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
7566 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
7568 // Treat delay slot as part of branch too
7569 /*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7570 will_dirty[i+1]&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7571 wont_dirty[i+1]|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7575 will_dirty[i+1]&=~(1<<r);
7580 // Merge in delay slot
7581 for(r=0;r<HOST_REGS;r++) {
7582 if(r!=EXCLUDE_REG) {
7584 // Might not dirty if likely branch is not taken
7585 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7586 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7587 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7588 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7589 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7590 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7591 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7592 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7593 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7594 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7595 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7596 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7597 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7598 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7603 // Merge in delay slot (won't dirty)
7604 for(r=0;r<HOST_REGS;r++) {
7605 if(r!=EXCLUDE_REG) {
7606 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7607 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7608 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7609 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7610 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7611 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7612 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7613 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7614 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7615 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7619 #ifndef DESTRUCTIVE_WRITEBACK
7620 branch_regs[i].dirty&=wont_dirty_i;
7622 branch_regs[i].dirty|=will_dirty_i;
7627 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7629 // SYSCALL instruction (software interrupt)
7633 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7635 // ERET instruction (return from interrupt)
7639 will_dirty_next=will_dirty_i;
7640 wont_dirty_next=wont_dirty_i;
7641 for(r=0;r<HOST_REGS;r++) {
7642 if(r!=EXCLUDE_REG) {
7643 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7644 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7645 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7646 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7647 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7648 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7649 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7650 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7652 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
7654 // Don't store a register immediately after writing it,
7655 // may prevent dual-issue.
7656 if((regs[i].regmap[r]&63)==rt1[i-1]) wont_dirty_i|=1<<r;
7657 if((regs[i].regmap[r]&63)==rt2[i-1]) wont_dirty_i|=1<<r;
7663 will_dirty[i]=will_dirty_i;
7664 wont_dirty[i]=wont_dirty_i;
7665 // Mark registers that won't be dirtied as not dirty
7667 /*printf("wr (%d,%d) %x will:",istart,iend,start+i*4);
7668 for(r=0;r<HOST_REGS;r++) {
7669 if((will_dirty_i>>r)&1) {
7675 //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=FJUMP)) {
7676 regs[i].dirty|=will_dirty_i;
7677 #ifndef DESTRUCTIVE_WRITEBACK
7678 regs[i].dirty&=wont_dirty_i;
7679 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7681 if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
7682 for(r=0;r<HOST_REGS;r++) {
7683 if(r!=EXCLUDE_REG) {
7684 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
7685 regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
7686 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7694 for(r=0;r<HOST_REGS;r++) {
7695 if(r!=EXCLUDE_REG) {
7696 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
7697 regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
7698 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7706 // Deal with changed mappings
7707 temp_will_dirty=will_dirty_i;
7708 temp_wont_dirty=wont_dirty_i;
7709 for(r=0;r<HOST_REGS;r++) {
7710 if(r!=EXCLUDE_REG) {
7712 if(regs[i].regmap[r]==regmap_pre[i][r]) {
7714 #ifndef DESTRUCTIVE_WRITEBACK
7715 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7717 regs[i].wasdirty|=will_dirty_i&(1<<r);
7720 else if(regmap_pre[i][r]>=0&&(nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
7721 // Register moved to a different register
7722 will_dirty_i&=~(1<<r);
7723 wont_dirty_i&=~(1<<r);
7724 will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
7725 wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
7727 #ifndef DESTRUCTIVE_WRITEBACK
7728 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7730 regs[i].wasdirty|=will_dirty_i&(1<<r);
7734 will_dirty_i&=~(1<<r);
7735 wont_dirty_i&=~(1<<r);
7736 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7737 will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7738 wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7741 /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);/*assert(!((will_dirty>>r)&1));*/
7750 void disassemble_inst(int i)
7752 if (bt[i]) printf("*"); else printf(" ");
7755 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7757 printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
7759 printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
7761 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7763 if (opcode[i]==0x9&&rt1[i]!=31)
7764 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i]);
7766 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7769 printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break;
7771 if(opcode[i]==0xf) //LUI
7772 printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],rt1[i],imm[i]&0xffff);
7774 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7778 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7782 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rs2[i],rs1[i],imm[i]);
7786 printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i],rs2[i]);
7789 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rs1[i],rs2[i]);
7792 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7795 if((opcode2[i]&0x1d)==0x10)
7796 printf (" %x: %s r%d\n",start+i*4,insn[i],rt1[i]);
7797 else if((opcode2[i]&0x1d)==0x11)
7798 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7800 printf (" %x: %s\n",start+i*4,insn[i]);
7804 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC0
7805 else if(opcode2[i]==4)
7806 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC0
7807 else printf (" %x: %s\n",start+i*4,insn[i]);
7811 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC1
7812 else if(opcode2[i]>3)
7813 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC1
7814 else printf (" %x: %s\n",start+i*4,insn[i]);
7818 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC2
7819 else if(opcode2[i]>3)
7820 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC2
7821 else printf (" %x: %s\n",start+i*4,insn[i]);
7824 printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7827 printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7830 printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
7833 //printf (" %s %8x\n",insn[i],source[i]);
7834 printf (" %x: %s\n",start+i*4,insn[i]);
7838 // clear the state completely, instead of just marking
7839 // things invalid like invalidate_all_pages() does
7840 void new_dynarec_clear_full()
7843 out=(u_char *)BASE_ADDR;
7844 memset(invalid_code,1,sizeof(invalid_code));
7845 memset(hash_table,0xff,sizeof(hash_table));
7846 memset(mini_ht,-1,sizeof(mini_ht));
7847 memset(restore_candidate,0,sizeof(restore_candidate));
7848 memset(shadow,0,sizeof(shadow));
7850 expirep=16384; // Expiry pointer, +2 blocks
7851 pending_exception=0;
7854 inv_code_start=inv_code_end=~0;
7860 for(n=0;n<524288;n++) // 0 .. 0x7FFFFFFF
7862 for(n=524288;n<526336;n++) // 0x80000000 .. 0x807FFFFF
7863 memory_map[n]=((u_int)rdram-0x80000000)>>2;
7864 for(n=526336;n<1048576;n++) // 0x80800000 .. 0xFFFFFFFF
7866 for(n=0;n<4096;n++) ll_clear(jump_in+n);
7867 for(n=0;n<4096;n++) ll_clear(jump_out+n);
7868 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7871 void new_dynarec_init()
7873 printf("Init new dynarec\n");
7874 out=(u_char *)BASE_ADDR;
7875 if (mmap (out, 1<<TARGET_SIZE_2,
7876 PROT_READ | PROT_WRITE | PROT_EXEC,
7877 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
7878 -1, 0) <= 0) {printf("mmap() failed\n");}
7880 rdword=&readmem_dword;
7881 fake_pc.f.r.rs=&readmem_dword;
7882 fake_pc.f.r.rt=&readmem_dword;
7883 fake_pc.f.r.rd=&readmem_dword;
7886 new_dynarec_clear_full();
7888 // Copy this into local area so we don't have to put it in every literal pool
7889 invc_ptr=invalid_code;
7892 for(n=0;n<0x8000;n++) { // 0 .. 0x7FFFFFFF
7893 writemem[n] = write_nomem_new;
7894 writememb[n] = write_nomemb_new;
7895 writememh[n] = write_nomemh_new;
7897 writememd[n] = write_nomemd_new;
7899 readmem[n] = read_nomem_new;
7900 readmemb[n] = read_nomemb_new;
7901 readmemh[n] = read_nomemh_new;
7903 readmemd[n] = read_nomemd_new;
7906 for(n=0x8000;n<0x8080;n++) { // 0x80000000 .. 0x807FFFFF
7907 writemem[n] = write_rdram_new;
7908 writememb[n] = write_rdramb_new;
7909 writememh[n] = write_rdramh_new;
7911 writememd[n] = write_rdramd_new;
7914 for(n=0xC000;n<0x10000;n++) { // 0xC0000000 .. 0xFFFFFFFF
7915 writemem[n] = write_nomem_new;
7916 writememb[n] = write_nomemb_new;
7917 writememh[n] = write_nomemh_new;
7919 writememd[n] = write_nomemd_new;
7921 readmem[n] = read_nomem_new;
7922 readmemb[n] = read_nomemb_new;
7923 readmemh[n] = read_nomemh_new;
7925 readmemd[n] = read_nomemd_new;
7933 void new_dynarec_cleanup()
7936 if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0) {printf("munmap() failed\n");}
7937 for(n=0;n<4096;n++) ll_clear(jump_in+n);
7938 for(n=0;n<4096;n++) ll_clear(jump_out+n);
7939 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7941 if (munmap (ROM_COPY, 67108864) < 0) {printf("munmap() failed\n");}
7945 int new_recompile_block(int addr)
7948 if(addr==0x800cd050) {
7950 for(block=0x80000;block<0x80800;block++) invalidate_block(block);
7952 for(n=0;n<=2048;n++) ll_clear(jump_dirty+n);
7955 //if(Count==365117028) tracedebug=1;
7956 assem_debug("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7957 //printf("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7958 //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
7960 //printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
7961 //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
7962 /*if(Count>=312978186) {
7966 start = (u_int)addr&~3;
7967 //assert(((u_int)addr&1)==0);
7969 if(!sp_in_mirror&&(signed int)(psxRegs.GPR.n.sp&0xffe00000)>0x80200000&&
7970 0x10000<=psxRegs.GPR.n.sp&&(psxRegs.GPR.n.sp&~0xe0e00000)<RAM_SIZE) {
7971 printf("SP hack enabled (%08x), @%08x\n", psxRegs.GPR.n.sp, psxRegs.pc);
7974 if (Config.HLE && start == 0x80001000) // hlecall
7976 // XXX: is this enough? Maybe check hleSoftCall?
7977 u_int beginning=(u_int)out;
7978 u_int page=get_page(start);
7979 invalid_code[start>>12]=0;
7980 emit_movimm(start,0);
7981 emit_writeword(0,(int)&pcaddr);
7982 emit_jmp((int)new_dyna_leave);
7985 __clear_cache((void *)beginning,out);
7987 ll_add(jump_in+page,start,(void *)beginning);
7990 else if ((u_int)addr < 0x00200000 ||
7991 (0xa0000000 <= addr && addr < 0xa0200000)) {
7992 // used for BIOS calls mostly?
7993 source = (u_int *)((u_int)rdram+(start&0x1fffff));
7994 pagelimit = (addr&0xa0000000)|0x00200000;
7996 else if (!Config.HLE && (
7997 /* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
7998 (0xbfc00000 <= addr && addr < 0xbfc80000))) {
8000 source = (u_int *)((u_int)psxR+(start&0x7ffff));
8001 pagelimit = (addr&0xfff00000)|0x80000;
8006 if ((int)addr >= 0xa4000000 && (int)addr < 0xa4001000) {
8007 source = (u_int *)((u_int)SP_DMEM+start-0xa4000000);
8008 pagelimit = 0xa4001000;
8012 if ((int)addr >= 0x80000000 && (int)addr < 0x80000000+RAM_SIZE) {
8013 source = (u_int *)((u_int)rdram+start-0x80000000);
8014 pagelimit = 0x80000000+RAM_SIZE;
8017 else if ((signed int)addr >= (signed int)0xC0000000) {
8018 //printf("addr=%x mm=%x\n",(u_int)addr,(memory_map[start>>12]<<2));
8019 //if(tlb_LUT_r[start>>12])
8020 //source = (u_int *)(((int)rdram)+(tlb_LUT_r[start>>12]&0xFFFFF000)+(((int)addr)&0xFFF)-0x80000000);
8021 if((signed int)memory_map[start>>12]>=0) {
8022 source = (u_int *)((u_int)(start+(memory_map[start>>12]<<2)));
8023 pagelimit=(start+4096)&0xFFFFF000;
8024 int map=memory_map[start>>12];
8027 //printf("start: %x next: %x\n",map,memory_map[pagelimit>>12]);
8028 if((map&0xBFFFFFFF)==(memory_map[pagelimit>>12]&0xBFFFFFFF)) pagelimit+=4096;
8030 assem_debug("pagelimit=%x\n",pagelimit);
8031 assem_debug("mapping=%x (%x)\n",memory_map[start>>12],(memory_map[start>>12]<<2)+start);
8034 assem_debug("Compile at unmapped memory address: %x \n", (int)addr);
8035 //assem_debug("start: %x next: %x\n",memory_map[start>>12],memory_map[(start+4096)>>12]);
8036 return -1; // Caller will invoke exception handler
8038 //printf("source= %x\n",(int)source);
8042 printf("Compile at bogus memory address: %x \n", (int)addr);
8046 /* Pass 1: disassemble */
8047 /* Pass 2: register dependencies, branch targets */
8048 /* Pass 3: register allocation */
8049 /* Pass 4: branch dependencies */
8050 /* Pass 5: pre-alloc */
8051 /* Pass 6: optimize clean/dirty state */
8052 /* Pass 7: flag 32-bit registers */
8053 /* Pass 8: assembly */
8054 /* Pass 9: linker */
8055 /* Pass 10: garbage collection / free memory */
8059 unsigned int type,op,op2;
8061 //printf("addr = %x source = %x %x\n", addr,source,source[0]);
8063 /* Pass 1 disassembly */
8065 for(i=0;!done;i++) {
8066 bt[i]=0;likely[i]=0;ooo[i]=0;op2=0;
8067 minimum_free_regs[i]=0;
8068 opcode[i]=op=source[i]>>26;
8071 case 0x00: strcpy(insn[i],"special"); type=NI;
8075 case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
8076 case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
8077 case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
8078 case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
8079 case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
8080 case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
8081 case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
8082 case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
8083 case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
8084 case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
8085 case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
8086 case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
8087 case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
8088 case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
8089 case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
8090 case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
8091 case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
8092 case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
8093 case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
8094 case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
8095 case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
8096 case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
8097 case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
8098 case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
8099 case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
8100 case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
8101 case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
8102 case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
8103 case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
8104 case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
8105 case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
8106 case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
8107 case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
8108 case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
8109 case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
8111 case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
8112 case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
8113 case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
8114 case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
8115 case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
8116 case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
8117 case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
8118 case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
8119 case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
8120 case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
8121 case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
8122 case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
8123 case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
8124 case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
8125 case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
8126 case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
8127 case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
8131 case 0x01: strcpy(insn[i],"regimm"); type=NI;
8132 op2=(source[i]>>16)&0x1f;
8135 case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
8136 case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
8137 case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
8138 case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
8139 case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
8140 case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
8141 case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
8142 case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
8143 case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
8144 case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
8145 case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
8146 case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
8147 case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
8148 case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
8151 case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
8152 case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
8153 case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
8154 case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
8155 case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
8156 case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
8157 case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
8158 case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
8159 case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
8160 case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
8161 case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
8162 case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
8163 case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
8164 case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
8165 case 0x10: strcpy(insn[i],"cop0"); type=NI;
8166 op2=(source[i]>>21)&0x1f;
8169 case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
8170 case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
8171 case 0x10: strcpy(insn[i],"tlb"); type=NI;
8172 switch(source[i]&0x3f)
8174 case 0x01: strcpy(insn[i],"TLBR"); type=COP0; break;
8175 case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break;
8176 case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break;
8177 case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break;
8179 case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
8181 case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
8186 case 0x11: strcpy(insn[i],"cop1"); type=NI;
8187 op2=(source[i]>>21)&0x1f;
8190 case 0x00: strcpy(insn[i],"MFC1"); type=COP1; break;
8191 case 0x01: strcpy(insn[i],"DMFC1"); type=COP1; break;
8192 case 0x02: strcpy(insn[i],"CFC1"); type=COP1; break;
8193 case 0x04: strcpy(insn[i],"MTC1"); type=COP1; break;
8194 case 0x05: strcpy(insn[i],"DMTC1"); type=COP1; break;
8195 case 0x06: strcpy(insn[i],"CTC1"); type=COP1; break;
8196 case 0x08: strcpy(insn[i],"BC1"); type=FJUMP;
8197 switch((source[i]>>16)&0x3)
8199 case 0x00: strcpy(insn[i],"BC1F"); break;
8200 case 0x01: strcpy(insn[i],"BC1T"); break;
8201 case 0x02: strcpy(insn[i],"BC1FL"); break;
8202 case 0x03: strcpy(insn[i],"BC1TL"); break;
8205 case 0x10: strcpy(insn[i],"C1.S"); type=NI;
8206 switch(source[i]&0x3f)
8208 case 0x00: strcpy(insn[i],"ADD.S"); type=FLOAT; break;
8209 case 0x01: strcpy(insn[i],"SUB.S"); type=FLOAT; break;
8210 case 0x02: strcpy(insn[i],"MUL.S"); type=FLOAT; break;
8211 case 0x03: strcpy(insn[i],"DIV.S"); type=FLOAT; break;
8212 case 0x04: strcpy(insn[i],"SQRT.S"); type=FLOAT; break;
8213 case 0x05: strcpy(insn[i],"ABS.S"); type=FLOAT; break;
8214 case 0x06: strcpy(insn[i],"MOV.S"); type=FLOAT; break;
8215 case 0x07: strcpy(insn[i],"NEG.S"); type=FLOAT; break;
8216 case 0x08: strcpy(insn[i],"ROUND.L.S"); type=FCONV; break;
8217 case 0x09: strcpy(insn[i],"TRUNC.L.S"); type=FCONV; break;
8218 case 0x0A: strcpy(insn[i],"CEIL.L.S"); type=FCONV; break;
8219 case 0x0B: strcpy(insn[i],"FLOOR.L.S"); type=FCONV; break;
8220 case 0x0C: strcpy(insn[i],"ROUND.W.S"); type=FCONV; break;
8221 case 0x0D: strcpy(insn[i],"TRUNC.W.S"); type=FCONV; break;
8222 case 0x0E: strcpy(insn[i],"CEIL.W.S"); type=FCONV; break;
8223 case 0x0F: strcpy(insn[i],"FLOOR.W.S"); type=FCONV; break;
8224 case 0x21: strcpy(insn[i],"CVT.D.S"); type=FCONV; break;
8225 case 0x24: strcpy(insn[i],"CVT.W.S"); type=FCONV; break;
8226 case 0x25: strcpy(insn[i],"CVT.L.S"); type=FCONV; break;
8227 case 0x30: strcpy(insn[i],"C.F.S"); type=FCOMP; break;
8228 case 0x31: strcpy(insn[i],"C.UN.S"); type=FCOMP; break;
8229 case 0x32: strcpy(insn[i],"C.EQ.S"); type=FCOMP; break;
8230 case 0x33: strcpy(insn[i],"C.UEQ.S"); type=FCOMP; break;
8231 case 0x34: strcpy(insn[i],"C.OLT.S"); type=FCOMP; break;
8232 case 0x35: strcpy(insn[i],"C.ULT.S"); type=FCOMP; break;
8233 case 0x36: strcpy(insn[i],"C.OLE.S"); type=FCOMP; break;
8234 case 0x37: strcpy(insn[i],"C.ULE.S"); type=FCOMP; break;
8235 case 0x38: strcpy(insn[i],"C.SF.S"); type=FCOMP; break;
8236 case 0x39: strcpy(insn[i],"C.NGLE.S"); type=FCOMP; break;
8237 case 0x3A: strcpy(insn[i],"C.SEQ.S"); type=FCOMP; break;
8238 case 0x3B: strcpy(insn[i],"C.NGL.S"); type=FCOMP; break;
8239 case 0x3C: strcpy(insn[i],"C.LT.S"); type=FCOMP; break;
8240 case 0x3D: strcpy(insn[i],"C.NGE.S"); type=FCOMP; break;
8241 case 0x3E: strcpy(insn[i],"C.LE.S"); type=FCOMP; break;
8242 case 0x3F: strcpy(insn[i],"C.NGT.S"); type=FCOMP; break;
8245 case 0x11: strcpy(insn[i],"C1.D"); type=NI;
8246 switch(source[i]&0x3f)
8248 case 0x00: strcpy(insn[i],"ADD.D"); type=FLOAT; break;
8249 case 0x01: strcpy(insn[i],"SUB.D"); type=FLOAT; break;
8250 case 0x02: strcpy(insn[i],"MUL.D"); type=FLOAT; break;
8251 case 0x03: strcpy(insn[i],"DIV.D"); type=FLOAT; break;
8252 case 0x04: strcpy(insn[i],"SQRT.D"); type=FLOAT; break;
8253 case 0x05: strcpy(insn[i],"ABS.D"); type=FLOAT; break;
8254 case 0x06: strcpy(insn[i],"MOV.D"); type=FLOAT; break;
8255 case 0x07: strcpy(insn[i],"NEG.D"); type=FLOAT; break;
8256 case 0x08: strcpy(insn[i],"ROUND.L.D"); type=FCONV; break;
8257 case 0x09: strcpy(insn[i],"TRUNC.L.D"); type=FCONV; break;
8258 case 0x0A: strcpy(insn[i],"CEIL.L.D"); type=FCONV; break;
8259 case 0x0B: strcpy(insn[i],"FLOOR.L.D"); type=FCONV; break;
8260 case 0x0C: strcpy(insn[i],"ROUND.W.D"); type=FCONV; break;
8261 case 0x0D: strcpy(insn[i],"TRUNC.W.D"); type=FCONV; break;
8262 case 0x0E: strcpy(insn[i],"CEIL.W.D"); type=FCONV; break;
8263 case 0x0F: strcpy(insn[i],"FLOOR.W.D"); type=FCONV; break;
8264 case 0x20: strcpy(insn[i],"CVT.S.D"); type=FCONV; break;
8265 case 0x24: strcpy(insn[i],"CVT.W.D"); type=FCONV; break;
8266 case 0x25: strcpy(insn[i],"CVT.L.D"); type=FCONV; break;
8267 case 0x30: strcpy(insn[i],"C.F.D"); type=FCOMP; break;
8268 case 0x31: strcpy(insn[i],"C.UN.D"); type=FCOMP; break;
8269 case 0x32: strcpy(insn[i],"C.EQ.D"); type=FCOMP; break;
8270 case 0x33: strcpy(insn[i],"C.UEQ.D"); type=FCOMP; break;
8271 case 0x34: strcpy(insn[i],"C.OLT.D"); type=FCOMP; break;
8272 case 0x35: strcpy(insn[i],"C.ULT.D"); type=FCOMP; break;
8273 case 0x36: strcpy(insn[i],"C.OLE.D"); type=FCOMP; break;
8274 case 0x37: strcpy(insn[i],"C.ULE.D"); type=FCOMP; break;
8275 case 0x38: strcpy(insn[i],"C.SF.D"); type=FCOMP; break;
8276 case 0x39: strcpy(insn[i],"C.NGLE.D"); type=FCOMP; break;
8277 case 0x3A: strcpy(insn[i],"C.SEQ.D"); type=FCOMP; break;
8278 case 0x3B: strcpy(insn[i],"C.NGL.D"); type=FCOMP; break;
8279 case 0x3C: strcpy(insn[i],"C.LT.D"); type=FCOMP; break;
8280 case 0x3D: strcpy(insn[i],"C.NGE.D"); type=FCOMP; break;
8281 case 0x3E: strcpy(insn[i],"C.LE.D"); type=FCOMP; break;
8282 case 0x3F: strcpy(insn[i],"C.NGT.D"); type=FCOMP; break;
8285 case 0x14: strcpy(insn[i],"C1.W"); type=NI;
8286 switch(source[i]&0x3f)
8288 case 0x20: strcpy(insn[i],"CVT.S.W"); type=FCONV; break;
8289 case 0x21: strcpy(insn[i],"CVT.D.W"); type=FCONV; break;
8292 case 0x15: strcpy(insn[i],"C1.L"); type=NI;
8293 switch(source[i]&0x3f)
8295 case 0x20: strcpy(insn[i],"CVT.S.L"); type=FCONV; break;
8296 case 0x21: strcpy(insn[i],"CVT.D.L"); type=FCONV; break;
8302 case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
8303 case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
8304 case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
8305 case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
8306 case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
8307 case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
8308 case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
8309 case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
8311 case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
8312 case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
8313 case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
8314 case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
8315 case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
8316 case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
8317 case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
8319 case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
8321 case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
8322 case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
8323 case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
8324 case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
8326 case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
8327 case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
8329 case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
8330 case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
8331 case 0x30: strcpy(insn[i],"LL"); type=NI; break;
8332 case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
8334 case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
8335 case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
8336 case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
8338 case 0x38: strcpy(insn[i],"SC"); type=NI; break;
8339 case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
8341 case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
8342 case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
8343 case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
8346 case 0x12: strcpy(insn[i],"COP2"); type=NI;
8347 // note: COP MIPS-1 encoding differs from MIPS32
8348 op2=(source[i]>>21)&0x1f;
8349 if (source[i]&0x3f) {
8350 if (gte_handlers[source[i]&0x3f]!=NULL) {
8351 snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
8357 case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
8358 case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
8359 case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
8360 case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
8363 case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
8364 case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
8365 case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
8367 default: strcpy(insn[i],"???"); type=NI;
8368 printf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
8373 /* Get registers/immediates */
8381 rs1[i]=(source[i]>>21)&0x1f;
8383 rt1[i]=(source[i]>>16)&0x1f;
8385 imm[i]=(short)source[i];
8389 rs1[i]=(source[i]>>21)&0x1f;
8390 rs2[i]=(source[i]>>16)&0x1f;
8393 imm[i]=(short)source[i];
8394 if(op==0x2c||op==0x2d||op==0x3f) us1[i]=rs2[i]; // 64-bit SDL/SDR/SD
8397 // LWL/LWR only load part of the register,
8398 // therefore the target register must be treated as a source too
8399 rs1[i]=(source[i]>>21)&0x1f;
8400 rs2[i]=(source[i]>>16)&0x1f;
8401 rt1[i]=(source[i]>>16)&0x1f;
8403 imm[i]=(short)source[i];
8404 if(op==0x1a||op==0x1b) us1[i]=rs2[i]; // LDR/LDL
8405 if(op==0x26) dep1[i]=rt1[i]; // LWR
8408 if (op==0x0f) rs1[i]=0; // LUI instruction has no source register
8409 else rs1[i]=(source[i]>>21)&0x1f;
8411 rt1[i]=(source[i]>>16)&0x1f;
8413 if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
8414 imm[i]=(unsigned short)source[i];
8416 imm[i]=(short)source[i];
8418 if(op==0x18||op==0x19) us1[i]=rs1[i]; // DADDI/DADDIU
8419 if(op==0x0a||op==0x0b) us1[i]=rs1[i]; // SLTI/SLTIU
8420 if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI
8427 // The JAL instruction writes to r31.
8434 rs1[i]=(source[i]>>21)&0x1f;
8438 // The JALR instruction writes to rd.
8440 rt1[i]=(source[i]>>11)&0x1f;
8445 rs1[i]=(source[i]>>21)&0x1f;
8446 rs2[i]=(source[i]>>16)&0x1f;
8449 if(op&2) { // BGTZ/BLEZ
8457 rs1[i]=(source[i]>>21)&0x1f;
8462 if(op2&0x10) { // BxxAL
8464 // NOTE: If the branch is not taken, r31 is still overwritten
8466 likely[i]=(op2&2)>>1;
8473 likely[i]=((source[i])>>17)&1;
8476 rs1[i]=(source[i]>>21)&0x1f; // source
8477 rs2[i]=(source[i]>>16)&0x1f; // subtract amount
8478 rt1[i]=(source[i]>>11)&0x1f; // destination
8480 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
8481 us1[i]=rs1[i];us2[i]=rs2[i];
8483 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
8484 dep1[i]=rs1[i];dep2[i]=rs2[i];
8486 else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB
8487 dep1[i]=rs1[i];dep2[i]=rs2[i];
8491 rs1[i]=(source[i]>>21)&0x1f; // source
8492 rs2[i]=(source[i]>>16)&0x1f; // divisor
8495 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
8496 us1[i]=rs1[i];us2[i]=rs2[i];
8504 if(op2==0x10) rs1[i]=HIREG; // MFHI
8505 if(op2==0x11) rt1[i]=HIREG; // MTHI
8506 if(op2==0x12) rs1[i]=LOREG; // MFLO
8507 if(op2==0x13) rt1[i]=LOREG; // MTLO
8508 if((op2&0x1d)==0x10) rt1[i]=(source[i]>>11)&0x1f; // MFxx
8509 if((op2&0x1d)==0x11) rs1[i]=(source[i]>>21)&0x1f; // MTxx
8513 rs1[i]=(source[i]>>16)&0x1f; // target of shift
8514 rs2[i]=(source[i]>>21)&0x1f; // shift amount
8515 rt1[i]=(source[i]>>11)&0x1f; // destination
8517 // DSLLV/DSRLV/DSRAV are 64-bit
8518 if(op2>=0x14&&op2<=0x17) us1[i]=rs1[i];
8521 rs1[i]=(source[i]>>16)&0x1f;
8523 rt1[i]=(source[i]>>11)&0x1f;
8525 imm[i]=(source[i]>>6)&0x1f;
8526 // DSxx32 instructions
8527 if(op2>=0x3c) imm[i]|=0x20;
8528 // DSLL/DSRL/DSRA/DSRA32/DSRL32 but not DSLL32 require 64-bit source
8529 if(op2>=0x38&&op2!=0x3c) us1[i]=rs1[i];
8536 if(op2==0) rt1[i]=(source[i]>>16)&0x1F; // MFC0
8537 if(op2==4) rs1[i]=(source[i]>>16)&0x1F; // MTC0
8538 if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status
8539 if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET
8547 if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
8548 if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
8549 if(op2==5) us1[i]=rs1[i]; // DMTC1
8553 rs1[i]=(source[i]>>21)&0x1F;
8557 imm[i]=(short)source[i];
8560 rs1[i]=(source[i]>>21)&0x1F;
8564 imm[i]=(short)source[i];
8593 /* Calculate branch target addresses */
8595 ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
8596 else if(type==CJUMP&&rs1[i]==rs2[i]&&(op&1))
8597 ba[i]=start+i*4+8; // Ignore never taken branch
8598 else if(type==SJUMP&&rs1[i]==0&&!(op2&1))
8599 ba[i]=start+i*4+8; // Ignore never taken branch
8600 else if(type==CJUMP||type==SJUMP||type==FJUMP)
8601 ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
8604 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
8606 // branch in delay slot?
8607 if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
8608 // don't handle first branch and call interpreter if it's hit
8609 printf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr);
8612 // basic load delay detection
8613 else if((type==LOAD||type==LOADLR||type==COP0||type==COP2||type==C2LS)&&rt1[i]!=0) {
8614 int t=(ba[i-1]-start)/4;
8615 if(0 <= t && t < i &&(rt1[i]==rs1[t]||rt1[i]==rs2[t])&&itype[t]!=CJUMP&&itype[t]!=SJUMP) {
8616 // jump target wants DS result - potential load delay effect
8617 printf("load delay @%08x (%08x)\n", addr + i*4, addr);
8619 bt[t+1]=1; // expected return from interpreter
8621 else if(i>=2&&rt1[i-2]==2&&rt1[i]==2&&rs1[i]!=2&&rs2[i]!=2&&rs1[i-1]!=2&&rs2[i-1]!=2&&
8622 !(i>=3&&(itype[i-3]==RJUMP||itype[i-3]==UJUMP||itype[i-3]==CJUMP||itype[i-3]==SJUMP))) {
8623 // v0 overwrite like this is a sign of trouble, bail out
8624 printf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr);
8630 rs2[i-1]=rt1[i-1]=rt2[i-1]=0;
8634 i--; // don't compile the DS
8638 /* Is this the end of the block? */
8639 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
8640 if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
8644 if(stop_after_jal) done=1;
8646 if((source[i+1]&0xfc00003f)==0x0d) done=1;
8648 // Don't recompile stuff that's already compiled
8649 if(check_addr(start+i*4+4)) done=1;
8650 // Don't get too close to the limit
8651 if(i>MAXBLOCK/2) done=1;
8653 if(itype[i]==SYSCALL&&stop_after_jal) done=1;
8654 if(itype[i]==HLECALL||itype[i]==INTCALL) done=2;
8656 // Does the block continue due to a branch?
8659 if(ba[j]==start+i*4) done=j=0; // Branch into delay slot
8660 if(ba[j]==start+i*4+4) done=j=0;
8661 if(ba[j]==start+i*4+8) done=j=0;
8664 //assert(i<MAXBLOCK-1);
8665 if(start+i*4==pagelimit-4) done=1;
8666 assert(start+i*4<pagelimit);
8667 if (i==MAXBLOCK-1) done=1;
8668 // Stop if we're compiling junk
8669 if(itype[i]==NI&&opcode[i]==0x11) {
8670 done=stop_after_jal=1;
8671 printf("Disabled speculative precompilation\n");
8675 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP||itype[i-1]==FJUMP) {
8676 if(start+i*4==pagelimit) {
8682 /* Pass 2 - Register dependencies and branch targets */
8684 unneeded_registers(0,slen-1,0);
8686 /* Pass 3 - Register allocation */
8688 struct regstat current; // Current register allocations/status
8691 current.u=unneeded_reg[0];
8692 current.uu=unneeded_reg_upper[0];
8693 clear_all_regs(current.regmap);
8694 alloc_reg(¤t,0,CCREG);
8695 dirty_reg(¤t,CCREG);
8703 provisional_32bit();
8706 // First instruction is delay slot
8711 unneeded_reg_upper[0]=1;
8712 current.regmap[HOST_BTREG]=BTREG;
8720 for(hr=0;hr<HOST_REGS;hr++)
8722 // Is this really necessary?
8723 if(current.regmap[hr]==0) current.regmap[hr]=-1;
8729 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
8731 if(rs1[i-2]==0||rs2[i-2]==0)
8734 current.is32|=1LL<<rs1[i-2];
8735 int hr=get_reg(current.regmap,rs1[i-2]|64);
8736 if(hr>=0) current.regmap[hr]=-1;
8739 current.is32|=1LL<<rs2[i-2];
8740 int hr=get_reg(current.regmap,rs2[i-2]|64);
8741 if(hr>=0) current.regmap[hr]=-1;
8747 // If something jumps here with 64-bit values
8748 // then promote those registers to 64 bits
8751 uint64_t temp_is32=current.is32;
8754 if(ba[j]==start+i*4)
8755 temp_is32&=branch_regs[j].is32;
8759 if(ba[j]==start+i*4)
8763 if(temp_is32!=current.is32) {
8764 //printf("dumping 32-bit regs (%x)\n",start+i*4);
8765 #ifndef DESTRUCTIVE_WRITEBACK
8768 for(hr=0;hr<HOST_REGS;hr++)
8770 int r=current.regmap[hr];
8773 if((current.dirty>>hr)&((current.is32&~temp_is32)>>r)&1) {
8775 //printf("restore %d\n",r);
8779 current.is32=temp_is32;
8786 memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
8787 regs[i].wasconst=current.isconst;
8788 regs[i].was32=current.is32;
8789 regs[i].wasdirty=current.dirty;
8790 #if defined(DESTRUCTIVE_WRITEBACK) && !defined(FORCE32)
8791 // To change a dirty register from 32 to 64 bits, we must write
8792 // it out during the previous cycle (for branches, 2 cycles)
8793 if(i<slen-1&&bt[i+1]&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP)
8795 uint64_t temp_is32=current.is32;
8798 if(ba[j]==start+i*4+4)
8799 temp_is32&=branch_regs[j].is32;
8803 if(ba[j]==start+i*4+4)
8807 if(temp_is32!=current.is32) {
8808 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8809 for(hr=0;hr<HOST_REGS;hr++)
8811 int r=current.regmap[hr];
8814 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8815 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP)
8817 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63))
8819 //printf("dump %d/r%d\n",hr,r);
8820 current.regmap[hr]=-1;
8821 if(get_reg(current.regmap,r|64)>=0)
8822 current.regmap[get_reg(current.regmap,r|64)]=-1;
8830 else if(i<slen-2&&bt[i+2]&&(source[i-1]>>16)!=0x1000&&(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP))
8832 uint64_t temp_is32=current.is32;
8835 if(ba[j]==start+i*4+8)
8836 temp_is32&=branch_regs[j].is32;
8840 if(ba[j]==start+i*4+8)
8844 if(temp_is32!=current.is32) {
8845 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8846 for(hr=0;hr<HOST_REGS;hr++)
8848 int r=current.regmap[hr];
8851 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8852 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63)&&rs1[i+1]!=(r&63)&&rs2[i+1]!=(r&63))
8854 //printf("dump %d/r%d\n",hr,r);
8855 current.regmap[hr]=-1;
8856 if(get_reg(current.regmap,r|64)>=0)
8857 current.regmap[get_reg(current.regmap,r|64)]=-1;
8865 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
8867 current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
8868 current.uu=unneeded_reg_upper[i+1]&~((1LL<<us1[i])|(1LL<<us2[i]));
8869 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8878 current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
8879 current.uu=branch_unneeded_reg_upper[i]&~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
8880 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
8881 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8882 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8885 } else { printf("oops, branch at end of block with no delay slot\n");exit(1); }
8889 ds=0; // Skip delay slot, already allocated as part of branch
8890 // ...but we need to alloc it in case something jumps here
8892 current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
8893 current.uu=branch_unneeded_reg_upper[i-1]&unneeded_reg_upper[i+1];
8895 current.u=branch_unneeded_reg[i-1];
8896 current.uu=branch_unneeded_reg_upper[i-1];
8898 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8899 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8900 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8903 struct regstat temp;
8904 memcpy(&temp,¤t,sizeof(current));
8905 temp.wasdirty=temp.dirty;
8906 temp.was32=temp.is32;
8907 // TODO: Take into account unconditional branches, as below
8908 delayslot_alloc(&temp,i);
8909 memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
8910 regs[i].wasdirty=temp.wasdirty;
8911 regs[i].was32=temp.was32;
8912 regs[i].dirty=temp.dirty;
8913 regs[i].is32=temp.is32;
8917 // Create entry (branch target) regmap
8918 for(hr=0;hr<HOST_REGS;hr++)
8920 int r=temp.regmap[hr];
8922 if(r!=regmap_pre[i][hr]) {
8923 regs[i].regmap_entry[hr]=-1;
8928 if((current.u>>r)&1) {
8929 regs[i].regmap_entry[hr]=-1;
8930 regs[i].regmap[hr]=-1;
8931 //Don't clear regs in the delay slot as the branch might need them
8932 //current.regmap[hr]=-1;
8934 regs[i].regmap_entry[hr]=r;
8937 if((current.uu>>(r&63))&1) {
8938 regs[i].regmap_entry[hr]=-1;
8939 regs[i].regmap[hr]=-1;
8940 //Don't clear regs in the delay slot as the branch might need them
8941 //current.regmap[hr]=-1;
8943 regs[i].regmap_entry[hr]=r;
8947 // First instruction expects CCREG to be allocated
8948 if(i==0&&hr==HOST_CCREG)
8949 regs[i].regmap_entry[hr]=CCREG;
8951 regs[i].regmap_entry[hr]=-1;
8955 else { // Not delay slot
8958 //current.isconst=0; // DEBUG
8959 //current.wasconst=0; // DEBUG
8960 //regs[i].wasconst=0; // DEBUG
8961 clear_const(¤t,rt1[i]);
8962 alloc_cc(¤t,i);
8963 dirty_reg(¤t,CCREG);
8965 alloc_reg(¤t,i,31);
8966 dirty_reg(¤t,31);
8967 //assert(rs1[i+1]!=31&&rs2[i+1]!=31);
8968 //assert(rt1[i+1]!=rt1[i]);
8970 alloc_reg(¤t,i,PTEMP);
8972 //current.is32|=1LL<<rt1[i];
8975 delayslot_alloc(¤t,i+1);
8976 //current.isconst=0; // DEBUG
8978 //printf("i=%d, isconst=%x\n",i,current.isconst);
8981 //current.isconst=0;
8982 //current.wasconst=0;
8983 //regs[i].wasconst=0;
8984 clear_const(¤t,rs1[i]);
8985 clear_const(¤t,rt1[i]);
8986 alloc_cc(¤t,i);
8987 dirty_reg(¤t,CCREG);
8988 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
8989 alloc_reg(¤t,i,rs1[i]);
8991 alloc_reg(¤t,i,rt1[i]);
8992 dirty_reg(¤t,rt1[i]);
8993 assert(rs1[i+1]!=rt1[i]&&rs2[i+1]!=rt1[i]);
8994 assert(rt1[i+1]!=rt1[i]);
8996 alloc_reg(¤t,i,PTEMP);
9000 if(rs1[i]==31) { // JALR
9001 alloc_reg(¤t,i,RHASH);
9002 #ifndef HOST_IMM_ADDR32
9003 alloc_reg(¤t,i,RHTBL);
9007 delayslot_alloc(¤t,i+1);
9009 // The delay slot overwrites our source register,
9010 // allocate a temporary register to hold the old value.
9014 delayslot_alloc(¤t,i+1);
9016 alloc_reg(¤t,i,RTEMP);
9018 //current.isconst=0; // DEBUG
9023 //current.isconst=0;
9024 //current.wasconst=0;
9025 //regs[i].wasconst=0;
9026 clear_const(¤t,rs1[i]);
9027 clear_const(¤t,rs2[i]);
9028 if((opcode[i]&0x3E)==4) // BEQ/BNE
9030 alloc_cc(¤t,i);
9031 dirty_reg(¤t,CCREG);
9032 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
9033 if(rs2[i]) alloc_reg(¤t,i,rs2[i]);
9034 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9036 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
9037 if(rs2[i]) alloc_reg64(¤t,i,rs2[i]);
9039 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
9040 (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) {
9041 // The delay slot overwrites one of our conditions.
9042 // Allocate the branch condition registers instead.
9046 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
9047 if(rs2[i]) alloc_reg(¤t,i,rs2[i]);
9048 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9050 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
9051 if(rs2[i]) alloc_reg64(¤t,i,rs2[i]);
9057 delayslot_alloc(¤t,i+1);
9061 if((opcode[i]&0x3E)==6) // BLEZ/BGTZ
9063 alloc_cc(¤t,i);
9064 dirty_reg(¤t,CCREG);
9065 alloc_reg(¤t,i,rs1[i]);
9066 if(!(current.is32>>rs1[i]&1))
9068 alloc_reg64(¤t,i,rs1[i]);
9070 if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
9071 // The delay slot overwrites one of our conditions.
9072 // Allocate the branch condition registers instead.
9076 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
9077 if(!((current.is32>>rs1[i])&1))
9079 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
9085 delayslot_alloc(¤t,i+1);
9089 // Don't alloc the delay slot yet because we might not execute it
9090 if((opcode[i]&0x3E)==0x14) // BEQL/BNEL
9095 alloc_cc(¤t,i);
9096 dirty_reg(¤t,CCREG);
9097 alloc_reg(¤t,i,rs1[i]);
9098 alloc_reg(¤t,i,rs2[i]);
9099 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9101 alloc_reg64(¤t,i,rs1[i]);
9102 alloc_reg64(¤t,i,rs2[i]);
9106 if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL
9111 alloc_cc(¤t,i);
9112 dirty_reg(¤t,CCREG);
9113 alloc_reg(¤t,i,rs1[i]);
9114 if(!(current.is32>>rs1[i]&1))
9116 alloc_reg64(¤t,i,rs1[i]);
9120 //current.isconst=0;
9123 //current.isconst=0;
9124 //current.wasconst=0;
9125 //regs[i].wasconst=0;
9126 clear_const(¤t,rs1[i]);
9127 clear_const(¤t,rt1[i]);
9128 //if((opcode2[i]&0x1E)==0x0) // BLTZ/BGEZ
9129 if((opcode2[i]&0x0E)==0x0) // BLTZ/BGEZ
9131 alloc_cc(¤t,i);
9132 dirty_reg(¤t,CCREG);
9133 alloc_reg(¤t,i,rs1[i]);
9134 if(!(current.is32>>rs1[i]&1))
9136 alloc_reg64(¤t,i,rs1[i]);
9138 if (rt1[i]==31) { // BLTZAL/BGEZAL
9139 alloc_reg(¤t,i,31);
9140 dirty_reg(¤t,31);
9141 //#ifdef REG_PREFETCH
9142 //alloc_reg(¤t,i,PTEMP);
9144 //current.is32|=1LL<<rt1[i];
9146 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) // The delay slot overwrites the branch condition.
9147 ||(rt1[i]==31&&(rs1[i+1]==31||rs2[i+1]==31||rt1[i+1]==31||rt2[i+1]==31))) { // DS touches $ra
9148 // Allocate the branch condition registers instead.
9152 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
9153 if(!((current.is32>>rs1[i])&1))
9155 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
9161 delayslot_alloc(¤t,i+1);
9165 // Don't alloc the delay slot yet because we might not execute it
9166 if((opcode2[i]&0x1E)==0x2) // BLTZL/BGEZL
9171 alloc_cc(¤t,i);
9172 dirty_reg(¤t,CCREG);
9173 alloc_reg(¤t,i,rs1[i]);
9174 if(!(current.is32>>rs1[i]&1))
9176 alloc_reg64(¤t,i,rs1[i]);
9180 //current.isconst=0;
9186 if(likely[i]==0) // BC1F/BC1T
9188 // TODO: Theoretically we can run out of registers here on x86.
9189 // The delay slot can allocate up to six, and we need to check
9190 // CSREG before executing the delay slot. Possibly we can drop
9191 // the cycle count and then reload it after checking that the
9192 // FPU is in a usable state, or don't do out-of-order execution.
9193 alloc_cc(¤t,i);
9194 dirty_reg(¤t,CCREG);
9195 alloc_reg(¤t,i,FSREG);
9196 alloc_reg(¤t,i,CSREG);
9197 if(itype[i+1]==FCOMP) {
9198 // The delay slot overwrites the branch condition.
9199 // Allocate the branch condition registers instead.
9200 alloc_cc(¤t,i);
9201 dirty_reg(¤t,CCREG);
9202 alloc_reg(¤t,i,CSREG);
9203 alloc_reg(¤t,i,FSREG);
9207 delayslot_alloc(¤t,i+1);
9208 alloc_reg(¤t,i+1,CSREG);
9212 // Don't alloc the delay slot yet because we might not execute it
9213 if(likely[i]) // BC1FL/BC1TL
9215 alloc_cc(¤t,i);
9216 dirty_reg(¤t,CCREG);
9217 alloc_reg(¤t,i,CSREG);
9218 alloc_reg(¤t,i,FSREG);
9224 imm16_alloc(¤t,i);
9228 load_alloc(¤t,i);
9232 store_alloc(¤t,i);
9235 alu_alloc(¤t,i);
9238 shift_alloc(¤t,i);
9241 multdiv_alloc(¤t,i);
9244 shiftimm_alloc(¤t,i);
9247 mov_alloc(¤t,i);
9250 cop0_alloc(¤t,i);
9254 cop1_alloc(¤t,i);
9257 c1ls_alloc(¤t,i);
9260 c2ls_alloc(¤t,i);
9263 c2op_alloc(¤t,i);
9266 fconv_alloc(¤t,i);
9269 float_alloc(¤t,i);
9272 fcomp_alloc(¤t,i);
9277 syscall_alloc(¤t,i);
9280 pagespan_alloc(¤t,i);
9284 // Drop the upper half of registers that have become 32-bit
9285 current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i]));
9286 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
9287 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9288 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9291 current.uu|=current.is32&((1LL<<rt1[i+1])|(1LL<<rt2[i+1]));
9292 current.uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
9293 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
9294 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9298 // Create entry (branch target) regmap
9299 for(hr=0;hr<HOST_REGS;hr++)
9302 r=current.regmap[hr];
9304 if(r!=regmap_pre[i][hr]) {
9305 // TODO: delay slot (?)
9306 or=get_reg(regmap_pre[i],r); // Get old mapping for this register
9307 if(or<0||(r&63)>=TEMPREG){
9308 regs[i].regmap_entry[hr]=-1;
9312 // Just move it to a different register
9313 regs[i].regmap_entry[hr]=r;
9314 // If it was dirty before, it's still dirty
9315 if((regs[i].wasdirty>>or)&1) dirty_reg(¤t,r&63);
9322 regs[i].regmap_entry[hr]=0;
9326 if((current.u>>r)&1) {
9327 regs[i].regmap_entry[hr]=-1;
9328 //regs[i].regmap[hr]=-1;
9329 current.regmap[hr]=-1;
9331 regs[i].regmap_entry[hr]=r;
9334 if((current.uu>>(r&63))&1) {
9335 regs[i].regmap_entry[hr]=-1;
9336 //regs[i].regmap[hr]=-1;
9337 current.regmap[hr]=-1;
9339 regs[i].regmap_entry[hr]=r;
9343 // Branches expect CCREG to be allocated at the target
9344 if(regmap_pre[i][hr]==CCREG)
9345 regs[i].regmap_entry[hr]=CCREG;
9347 regs[i].regmap_entry[hr]=-1;
9350 memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
9352 /* Branch post-alloc */
9355 current.was32=current.is32;
9356 current.wasdirty=current.dirty;
9357 switch(itype[i-1]) {
9359 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9360 branch_regs[i-1].isconst=0;
9361 branch_regs[i-1].wasconst=0;
9362 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9363 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9364 alloc_cc(&branch_regs[i-1],i-1);
9365 dirty_reg(&branch_regs[i-1],CCREG);
9366 if(rt1[i-1]==31) { // JAL
9367 alloc_reg(&branch_regs[i-1],i-1,31);
9368 dirty_reg(&branch_regs[i-1],31);
9369 branch_regs[i-1].is32|=1LL<<31;
9371 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9372 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9375 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9376 branch_regs[i-1].isconst=0;
9377 branch_regs[i-1].wasconst=0;
9378 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9379 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9380 alloc_cc(&branch_regs[i-1],i-1);
9381 dirty_reg(&branch_regs[i-1],CCREG);
9382 alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]);
9383 if(rt1[i-1]!=0) { // JALR
9384 alloc_reg(&branch_regs[i-1],i-1,rt1[i-1]);
9385 dirty_reg(&branch_regs[i-1],rt1[i-1]);
9386 branch_regs[i-1].is32|=1LL<<rt1[i-1];
9389 if(rs1[i-1]==31) { // JALR
9390 alloc_reg(&branch_regs[i-1],i-1,RHASH);
9391 #ifndef HOST_IMM_ADDR32
9392 alloc_reg(&branch_regs[i-1],i-1,RHTBL);
9396 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9397 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9400 if((opcode[i-1]&0x3E)==4) // BEQ/BNE
9402 alloc_cc(¤t,i-1);
9403 dirty_reg(¤t,CCREG);
9404 if((rs1[i-1]&&(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]))||
9405 (rs2[i-1]&&(rs2[i-1]==rt1[i]||rs2[i-1]==rt2[i]))) {
9406 // The delay slot overwrote one of our conditions
9407 // Delay slot goes after the test (in order)
9408 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9409 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9410 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9413 delayslot_alloc(¤t,i);
9418 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9419 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9420 // Alloc the branch condition registers
9421 if(rs1[i-1]) alloc_reg(¤t,i-1,rs1[i-1]);
9422 if(rs2[i-1]) alloc_reg(¤t,i-1,rs2[i-1]);
9423 if(!((current.is32>>rs1[i-1])&(current.is32>>rs2[i-1])&1))
9425 if(rs1[i-1]) alloc_reg64(¤t,i-1,rs1[i-1]);
9426 if(rs2[i-1]) alloc_reg64(¤t,i-1,rs2[i-1]);
9429 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9430 branch_regs[i-1].isconst=0;
9431 branch_regs[i-1].wasconst=0;
9432 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9433 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9436 if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ
9438 alloc_cc(¤t,i-1);
9439 dirty_reg(¤t,CCREG);
9440 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9441 // The delay slot overwrote the branch condition
9442 // Delay slot goes after the test (in order)
9443 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9444 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9445 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9448 delayslot_alloc(¤t,i);
9453 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9454 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9455 // Alloc the branch condition register
9456 alloc_reg(¤t,i-1,rs1[i-1]);
9457 if(!(current.is32>>rs1[i-1]&1))
9459 alloc_reg64(¤t,i-1,rs1[i-1]);
9462 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9463 branch_regs[i-1].isconst=0;
9464 branch_regs[i-1].wasconst=0;
9465 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9466 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9469 // Alloc the delay slot in case the branch is taken
9470 if((opcode[i-1]&0x3E)==0x14) // BEQL/BNEL
9472 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9473 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9474 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9475 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9476 alloc_cc(&branch_regs[i-1],i);
9477 dirty_reg(&branch_regs[i-1],CCREG);
9478 delayslot_alloc(&branch_regs[i-1],i);
9479 branch_regs[i-1].isconst=0;
9480 alloc_reg(¤t,i,CCREG); // Not taken path
9481 dirty_reg(¤t,CCREG);
9482 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9485 if((opcode[i-1]&0x3E)==0x16) // BLEZL/BGTZL
9487 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9488 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9489 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9490 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9491 alloc_cc(&branch_regs[i-1],i);
9492 dirty_reg(&branch_regs[i-1],CCREG);
9493 delayslot_alloc(&branch_regs[i-1],i);
9494 branch_regs[i-1].isconst=0;
9495 alloc_reg(¤t,i,CCREG); // Not taken path
9496 dirty_reg(¤t,CCREG);
9497 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9501 //if((opcode2[i-1]&0x1E)==0) // BLTZ/BGEZ
9502 if((opcode2[i-1]&0x0E)==0) // BLTZ/BGEZ
9504 alloc_cc(¤t,i-1);
9505 dirty_reg(¤t,CCREG);
9506 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9507 // The delay slot overwrote the branch condition
9508 // Delay slot goes after the test (in order)
9509 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9510 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9511 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9514 delayslot_alloc(¤t,i);
9519 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9520 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9521 // Alloc the branch condition register
9522 alloc_reg(¤t,i-1,rs1[i-1]);
9523 if(!(current.is32>>rs1[i-1]&1))
9525 alloc_reg64(¤t,i-1,rs1[i-1]);
9528 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9529 branch_regs[i-1].isconst=0;
9530 branch_regs[i-1].wasconst=0;
9531 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9532 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9535 // Alloc the delay slot in case the branch is taken
9536 if((opcode2[i-1]&0x1E)==2) // BLTZL/BGEZL
9538 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9539 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9540 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9541 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9542 alloc_cc(&branch_regs[i-1],i);
9543 dirty_reg(&branch_regs[i-1],CCREG);
9544 delayslot_alloc(&branch_regs[i-1],i);
9545 branch_regs[i-1].isconst=0;
9546 alloc_reg(¤t,i,CCREG); // Not taken path
9547 dirty_reg(¤t,CCREG);
9548 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9550 // FIXME: BLTZAL/BGEZAL
9551 if(opcode2[i-1]&0x10) { // BxxZAL
9552 alloc_reg(&branch_regs[i-1],i-1,31);
9553 dirty_reg(&branch_regs[i-1],31);
9554 branch_regs[i-1].is32|=1LL<<31;
9558 if(likely[i-1]==0) // BC1F/BC1T
9560 alloc_cc(¤t,i-1);
9561 dirty_reg(¤t,CCREG);
9562 if(itype[i]==FCOMP) {
9563 // The delay slot overwrote the branch condition
9564 // Delay slot goes after the test (in order)
9565 delayslot_alloc(¤t,i);
9570 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9571 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9572 // Alloc the branch condition register
9573 alloc_reg(¤t,i-1,FSREG);
9575 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9576 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9580 // Alloc the delay slot in case the branch is taken
9581 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9582 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9583 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9584 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9585 alloc_cc(&branch_regs[i-1],i);
9586 dirty_reg(&branch_regs[i-1],CCREG);
9587 delayslot_alloc(&branch_regs[i-1],i);
9588 branch_regs[i-1].isconst=0;
9589 alloc_reg(¤t,i,CCREG); // Not taken path
9590 dirty_reg(¤t,CCREG);
9591 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9596 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
9598 if(rt1[i-1]==31) // JAL/JALR
9600 // Subroutine call will return here, don't alloc any registers
9603 clear_all_regs(current.regmap);
9604 alloc_reg(¤t,i,CCREG);
9605 dirty_reg(¤t,CCREG);
9609 // Internal branch will jump here, match registers to caller
9610 current.is32=0x3FFFFFFFFLL;
9612 clear_all_regs(current.regmap);
9613 alloc_reg(¤t,i,CCREG);
9614 dirty_reg(¤t,CCREG);
9617 if(ba[j]==start+i*4+4) {
9618 memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
9619 current.is32=branch_regs[j].is32;
9620 current.dirty=branch_regs[j].dirty;
9625 if(ba[j]==start+i*4+4) {
9626 for(hr=0;hr<HOST_REGS;hr++) {
9627 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
9628 current.regmap[hr]=-1;
9630 current.is32&=branch_regs[j].is32;
9631 current.dirty&=branch_regs[j].dirty;
9640 // Count cycles in between branches
9642 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP||itype[i]==SYSCALL||itype[i]==HLECALL))
9647 else if(/*itype[i]==LOAD||*/itype[i]==STORE||itype[i]==C1LS) // load causes weird timing issues
9649 cc+=2; // 2 cycle penalty (after CLOCK_DIVIDER)
9651 else if(itype[i]==C2LS)
9661 flush_dirty_uppers(¤t);
9663 regs[i].is32=current.is32;
9664 regs[i].dirty=current.dirty;
9665 regs[i].isconst=current.isconst;
9666 memcpy(constmap[i],current.constmap,sizeof(current.constmap));
9668 for(hr=0;hr<HOST_REGS;hr++) {
9669 if(hr!=EXCLUDE_REG&®s[i].regmap[hr]>=0) {
9670 if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
9671 regs[i].wasconst&=~(1<<hr);
9675 if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
9678 /* Pass 4 - Cull unused host registers */
9682 for (i=slen-1;i>=0;i--)
9685 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9687 if(ba[i]<start || ba[i]>=(start+slen*4))
9689 // Branch out of this block, don't need anything
9695 // Need whatever matches the target
9697 int t=(ba[i]-start)>>2;
9698 for(hr=0;hr<HOST_REGS;hr++)
9700 if(regs[i].regmap_entry[hr]>=0) {
9701 if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
9705 // Conditional branch may need registers for following instructions
9706 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9709 nr|=needed_reg[i+2];
9710 for(hr=0;hr<HOST_REGS;hr++)
9712 if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
9713 //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
9717 // Don't need stuff which is overwritten
9718 //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9719 //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9720 // Merge in delay slot
9721 for(hr=0;hr<HOST_REGS;hr++)
9724 // These are overwritten unless the branch is "likely"
9725 // and the delay slot is nullified if not taken
9726 if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9727 if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9729 if(us1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9730 if(us2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9731 if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9732 if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9733 if(us1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9734 if(us2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9735 if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9736 if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9737 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1)) {
9738 if(dep1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9739 if(dep2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9741 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1)) {
9742 if(dep1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9743 if(dep2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9745 if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) {
9746 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9747 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9751 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
9753 // SYSCALL instruction (software interrupt)
9756 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
9758 // ERET instruction (return from interrupt)
9764 for(hr=0;hr<HOST_REGS;hr++) {
9765 if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
9766 if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
9767 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9768 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9772 for(hr=0;hr<HOST_REGS;hr++)
9774 // Overwritten registers are not needed
9775 if(rt1[i]&&rt1[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9776 if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9777 if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9778 // Source registers are needed
9779 if(us1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9780 if(us2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9781 if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr;
9782 if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr;
9783 if(us1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9784 if(us2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9785 if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9786 if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9787 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1)) {
9788 if(dep1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9789 if(dep1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9791 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1)) {
9792 if(dep2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9793 if(dep2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9795 if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) {
9796 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9797 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9799 // Don't store a register immediately after writing it,
9800 // may prevent dual-issue.
9801 // But do so if this is a branch target, otherwise we
9802 // might have to load the register before the branch.
9803 if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) {
9804 if((regmap_pre[i][hr]>0&®map_pre[i][hr]<64&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1)) ||
9805 (regmap_pre[i][hr]>64&&!((unneeded_reg_upper[i]>>(regmap_pre[i][hr]&63))&1)) ) {
9806 if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9807 if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9809 if((regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1)) ||
9810 (regs[i].regmap_entry[hr]>64&&!((unneeded_reg_upper[i]>>(regs[i].regmap_entry[hr]&63))&1)) ) {
9811 if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9812 if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9816 // Cycle count is needed at branches. Assume it is needed at the target too.
9817 if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==FJUMP||itype[i]==SPAN) {
9818 if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9819 if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9824 // Deallocate unneeded registers
9825 for(hr=0;hr<HOST_REGS;hr++)
9828 if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
9829 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9830 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9831 (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG)
9833 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9836 regs[i].regmap[hr]=-1;
9837 regs[i].isconst&=~(1<<hr);
9839 regmap_pre[i+2][hr]=-1;
9840 regs[i+2].wasconst&=~(1<<hr);
9845 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9847 int d1=0,d2=0,map=0,temp=0;
9848 if(get_reg(regs[i].regmap,rt1[i+1]|64)>=0||get_reg(branch_regs[i].regmap,rt1[i+1]|64)>=0)
9854 if(itype[i+1]==LOAD || itype[i+1]==LOADLR ||
9855 itype[i+1]==STORE || itype[i+1]==STORELR ||
9856 itype[i+1]==C1LS || itype[i+1]==C2LS)
9859 if(itype[i+1]==STORE || itype[i+1]==STORELR ||
9860 (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
9863 if(itype[i+1]==LOADLR || itype[i+1]==STORELR ||
9864 itype[i+1]==C1LS || itype[i+1]==C2LS)
9866 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9867 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9868 (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] &&
9869 (regs[i].regmap[hr]^64)!=us1[i+1] && (regs[i].regmap[hr]^64)!=us2[i+1] &&
9870 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9871 regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] &&
9872 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
9873 regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
9874 regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
9875 regs[i].regmap[hr]!=map )
9877 regs[i].regmap[hr]=-1;
9878 regs[i].isconst&=~(1<<hr);
9879 if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] &&
9880 (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] &&
9881 (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] &&
9882 (branch_regs[i].regmap[hr]^64)!=us1[i+1] && (branch_regs[i].regmap[hr]^64)!=us2[i+1] &&
9883 (branch_regs[i].regmap[hr]^64)!=d1 && (branch_regs[i].regmap[hr]^64)!=d2 &&
9884 branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] &&
9885 (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
9886 branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
9887 branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
9888 branch_regs[i].regmap[hr]!=map)
9890 branch_regs[i].regmap[hr]=-1;
9891 branch_regs[i].regmap_entry[hr]=-1;
9892 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9894 if(!likely[i]&&i<slen-2) {
9895 regmap_pre[i+2][hr]=-1;
9896 regs[i+2].wasconst&=~(1<<hr);
9907 int d1=0,d2=0,map=-1,temp=-1;
9908 if(get_reg(regs[i].regmap,rt1[i]|64)>=0)
9914 if(itype[i]==LOAD || itype[i]==LOADLR ||
9915 itype[i]==STORE || itype[i]==STORELR ||
9916 itype[i]==C1LS || itype[i]==C2LS)
9918 } else if(itype[i]==STORE || itype[i]==STORELR ||
9919 (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
9922 if(itype[i]==LOADLR || itype[i]==STORELR ||
9923 itype[i]==C1LS || itype[i]==C2LS)
9925 if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9926 (regs[i].regmap[hr]^64)!=us1[i] && (regs[i].regmap[hr]^64)!=us2[i] &&
9927 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9928 regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] &&
9929 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map &&
9930 (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG))
9932 if(i<slen-1&&!is_ds[i]) {
9933 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]!=-1)
9934 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
9935 if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
9937 printf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
9938 assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
9940 regmap_pre[i+1][hr]=-1;
9941 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
9942 regs[i+1].wasconst&=~(1<<hr);
9944 regs[i].regmap[hr]=-1;
9945 regs[i].isconst&=~(1<<hr);
9953 /* Pass 5 - Pre-allocate registers */
9955 // If a register is allocated during a loop, try to allocate it for the
9956 // entire loop, if possible. This avoids loading/storing registers
9957 // inside of the loop.
9959 signed char f_regmap[HOST_REGS];
9960 clear_all_regs(f_regmap);
9961 for(i=0;i<slen-1;i++)
9963 if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9965 if(ba[i]>=start && ba[i]<(start+i*4))
9966 if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
9967 ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
9968 ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
9969 ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
9970 ||itype[i+1]==FCOMP||itype[i+1]==FCONV
9971 ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
9973 int t=(ba[i]-start)>>2;
9974 if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots
9975 if(t<2||(itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||rt1[t-2]!=31) // call/ret assumes no registers allocated
9976 for(hr=0;hr<HOST_REGS;hr++)
9978 if(regs[i].regmap[hr]>64) {
9979 if(!((regs[i].dirty>>hr)&1))
9980 f_regmap[hr]=regs[i].regmap[hr];
9981 else f_regmap[hr]=-1;
9983 else if(regs[i].regmap[hr]>=0) {
9984 if(f_regmap[hr]!=regs[i].regmap[hr]) {
9985 // dealloc old register
9987 for(n=0;n<HOST_REGS;n++)
9989 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
9991 // and alloc new one
9992 f_regmap[hr]=regs[i].regmap[hr];
9995 if(branch_regs[i].regmap[hr]>64) {
9996 if(!((branch_regs[i].dirty>>hr)&1))
9997 f_regmap[hr]=branch_regs[i].regmap[hr];
9998 else f_regmap[hr]=-1;
10000 else if(branch_regs[i].regmap[hr]>=0) {
10001 if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
10002 // dealloc old register
10004 for(n=0;n<HOST_REGS;n++)
10006 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
10008 // and alloc new one
10009 f_regmap[hr]=branch_regs[i].regmap[hr];
10013 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
10014 f_regmap[hr]=branch_regs[i].regmap[hr];
10016 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
10017 f_regmap[hr]=branch_regs[i].regmap[hr];
10019 // Avoid dirty->clean transition
10020 #ifdef DESTRUCTIVE_WRITEBACK
10021 if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
10023 // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
10024 // case above, however it's always a good idea. We can't hoist the
10025 // load if the register was already allocated, so there's no point
10026 // wasting time analyzing most of these cases. It only "succeeds"
10027 // when the mapping was different and the load can be replaced with
10028 // a mov, which is of negligible benefit. So such cases are
10030 if(f_regmap[hr]>0) {
10031 if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
10032 int r=f_regmap[hr];
10035 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
10036 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
10037 if(r>63&&((unneeded_reg_upper[j]>>(r&63))&1)) break;
10039 // NB This can exclude the case where the upper-half
10040 // register is lower numbered than the lower-half
10041 // register. Not sure if it's worth fixing...
10042 if(get_reg(regs[j].regmap,r&63)<0) break;
10043 if(get_reg(regs[j].regmap_entry,r&63)<0) break;
10044 if(regs[j].is32&(1LL<<(r&63))) break;
10046 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
10047 //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
10049 if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
10050 if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
10052 if(get_reg(regs[i].regmap,r&63)<0) break;
10053 if(get_reg(branch_regs[i].regmap,r&63)<0) break;
10056 while(k>1&®s[k-1].regmap[hr]==-1) {
10057 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10058 //printf("no free regs for store %x\n",start+(k-1)*4);
10061 if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
10062 //printf("no-match due to different register\n");
10065 if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP||itype[k-2]==FJUMP) {
10066 //printf("no-match due to branch\n");
10069 // call/ret fast path assumes no registers allocated
10070 if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)&&rt1[k-3]==31) {
10074 // NB This can exclude the case where the upper-half
10075 // register is lower numbered than the lower-half
10076 // register. Not sure if it's worth fixing...
10077 if(get_reg(regs[k-1].regmap,r&63)<0) break;
10078 if(regs[k-1].is32&(1LL<<(r&63))) break;
10083 if((regs[k].is32&(1LL<<f_regmap[hr]))!=
10084 (regs[i+2].was32&(1LL<<f_regmap[hr]))) {
10085 //printf("bad match after branch\n");
10089 if(regs[k-1].regmap[hr]==f_regmap[hr]&®map_pre[k][hr]==f_regmap[hr]) {
10090 //printf("Extend r%d, %x ->\n",hr,start+k*4);
10092 regs[k].regmap_entry[hr]=f_regmap[hr];
10093 regs[k].regmap[hr]=f_regmap[hr];
10094 regmap_pre[k+1][hr]=f_regmap[hr];
10095 regs[k].wasdirty&=~(1<<hr);
10096 regs[k].dirty&=~(1<<hr);
10097 regs[k].wasdirty|=(1<<hr)®s[k-1].dirty;
10098 regs[k].dirty|=(1<<hr)®s[k].wasdirty;
10099 regs[k].wasconst&=~(1<<hr);
10100 regs[k].isconst&=~(1<<hr);
10105 //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
10108 assert(regs[i-1].regmap[hr]==f_regmap[hr]);
10109 if(regs[i-1].regmap[hr]==f_regmap[hr]&®map_pre[i][hr]==f_regmap[hr]) {
10110 //printf("OK fill %x (r%d)\n",start+i*4,hr);
10111 regs[i].regmap_entry[hr]=f_regmap[hr];
10112 regs[i].regmap[hr]=f_regmap[hr];
10113 regs[i].wasdirty&=~(1<<hr);
10114 regs[i].dirty&=~(1<<hr);
10115 regs[i].wasdirty|=(1<<hr)®s[i-1].dirty;
10116 regs[i].dirty|=(1<<hr)®s[i-1].dirty;
10117 regs[i].wasconst&=~(1<<hr);
10118 regs[i].isconst&=~(1<<hr);
10119 branch_regs[i].regmap_entry[hr]=f_regmap[hr];
10120 branch_regs[i].wasdirty&=~(1<<hr);
10121 branch_regs[i].wasdirty|=(1<<hr)®s[i].dirty;
10122 branch_regs[i].regmap[hr]=f_regmap[hr];
10123 branch_regs[i].dirty&=~(1<<hr);
10124 branch_regs[i].dirty|=(1<<hr)®s[i].dirty;
10125 branch_regs[i].wasconst&=~(1<<hr);
10126 branch_regs[i].isconst&=~(1<<hr);
10127 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
10128 regmap_pre[i+2][hr]=f_regmap[hr];
10129 regs[i+2].wasdirty&=~(1<<hr);
10130 regs[i+2].wasdirty|=(1<<hr)®s[i].dirty;
10131 assert((branch_regs[i].is32&(1LL<<f_regmap[hr]))==
10132 (regs[i+2].was32&(1LL<<f_regmap[hr])));
10137 // Alloc register clean at beginning of loop,
10138 // but may dirty it in pass 6
10139 regs[k].regmap_entry[hr]=f_regmap[hr];
10140 regs[k].regmap[hr]=f_regmap[hr];
10141 regs[k].dirty&=~(1<<hr);
10142 regs[k].wasconst&=~(1<<hr);
10143 regs[k].isconst&=~(1<<hr);
10144 if(itype[k]==UJUMP||itype[k]==RJUMP||itype[k]==CJUMP||itype[k]==SJUMP||itype[k]==FJUMP) {
10145 branch_regs[k].regmap_entry[hr]=f_regmap[hr];
10146 branch_regs[k].regmap[hr]=f_regmap[hr];
10147 branch_regs[k].dirty&=~(1<<hr);
10148 branch_regs[k].wasconst&=~(1<<hr);
10149 branch_regs[k].isconst&=~(1<<hr);
10150 if(itype[k]!=RJUMP&&itype[k]!=UJUMP&&(source[k]>>16)!=0x1000) {
10151 regmap_pre[k+2][hr]=f_regmap[hr];
10152 regs[k+2].wasdirty&=~(1<<hr);
10153 assert((branch_regs[k].is32&(1LL<<f_regmap[hr]))==
10154 (regs[k+2].was32&(1LL<<f_regmap[hr])));
10159 regmap_pre[k+1][hr]=f_regmap[hr];
10160 regs[k+1].wasdirty&=~(1<<hr);
10163 if(regs[j].regmap[hr]==f_regmap[hr])
10164 regs[j].regmap_entry[hr]=f_regmap[hr];
10168 if(regs[j].regmap[hr]>=0)
10170 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
10171 //printf("no-match due to different register\n");
10174 if((regs[j+1].is32&(1LL<<f_regmap[hr]))!=(regs[j].is32&(1LL<<f_regmap[hr]))) {
10175 //printf("32/64 mismatch %x %d\n",start+j*4,hr);
10178 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10180 // Stop on unconditional branch
10183 if(itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP)
10186 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
10189 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
10192 if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
10193 //printf("no-match due to different register (branch)\n");
10197 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10198 //printf("No free regs for store %x\n",start+j*4);
10201 if(f_regmap[hr]>=64) {
10202 if(regs[j].is32&(1LL<<(f_regmap[hr]&63))) {
10207 if(get_reg(regs[j].regmap,f_regmap[hr]&63)<0) {
10218 // Non branch or undetermined branch target
10219 for(hr=0;hr<HOST_REGS;hr++)
10221 if(hr!=EXCLUDE_REG) {
10222 if(regs[i].regmap[hr]>64) {
10223 if(!((regs[i].dirty>>hr)&1))
10224 f_regmap[hr]=regs[i].regmap[hr];
10226 else if(regs[i].regmap[hr]>=0) {
10227 if(f_regmap[hr]!=regs[i].regmap[hr]) {
10228 // dealloc old register
10230 for(n=0;n<HOST_REGS;n++)
10232 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
10234 // and alloc new one
10235 f_regmap[hr]=regs[i].regmap[hr];
10240 // Try to restore cycle count at branch targets
10242 for(j=i;j<slen-1;j++) {
10243 if(regs[j].regmap[HOST_CCREG]!=-1) break;
10244 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10245 //printf("no free regs for store %x\n",start+j*4);
10249 if(regs[j].regmap[HOST_CCREG]==CCREG) {
10251 //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
10253 regs[k].regmap_entry[HOST_CCREG]=CCREG;
10254 regs[k].regmap[HOST_CCREG]=CCREG;
10255 regmap_pre[k+1][HOST_CCREG]=CCREG;
10256 regs[k+1].wasdirty|=1<<HOST_CCREG;
10257 regs[k].dirty|=1<<HOST_CCREG;
10258 regs[k].wasconst&=~(1<<HOST_CCREG);
10259 regs[k].isconst&=~(1<<HOST_CCREG);
10262 regs[j].regmap_entry[HOST_CCREG]=CCREG;
10264 // Work backwards from the branch target
10265 if(j>i&&f_regmap[HOST_CCREG]==CCREG)
10267 //printf("Extend backwards\n");
10270 while(regs[k-1].regmap[HOST_CCREG]==-1) {
10271 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10272 //printf("no free regs for store %x\n",start+(k-1)*4);
10277 if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
10278 //printf("Extend CC, %x ->\n",start+k*4);
10280 regs[k].regmap_entry[HOST_CCREG]=CCREG;
10281 regs[k].regmap[HOST_CCREG]=CCREG;
10282 regmap_pre[k+1][HOST_CCREG]=CCREG;
10283 regs[k+1].wasdirty|=1<<HOST_CCREG;
10284 regs[k].dirty|=1<<HOST_CCREG;
10285 regs[k].wasconst&=~(1<<HOST_CCREG);
10286 regs[k].isconst&=~(1<<HOST_CCREG);
10291 //printf("Fail Extend CC, %x ->\n",start+k*4);
10295 if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&&
10296 itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&&
10297 itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1&&itype[i]!=FLOAT&&
10298 itype[i]!=FCONV&&itype[i]!=FCOMP)
10300 memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
10305 // Cache memory offset or tlb map pointer if a register is available
10306 #ifndef HOST_IMM_ADDR32
10311 int earliest_available[HOST_REGS];
10312 int loop_start[HOST_REGS];
10313 int score[HOST_REGS];
10314 int end[HOST_REGS];
10315 int reg=using_tlb?MMREG:ROREG;
10318 for(hr=0;hr<HOST_REGS;hr++) {
10319 score[hr]=0;earliest_available[hr]=0;
10320 loop_start[hr]=MAXBLOCK;
10322 for(i=0;i<slen-1;i++)
10324 // Can't do anything if no registers are available
10325 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i]) {
10326 for(hr=0;hr<HOST_REGS;hr++) {
10327 score[hr]=0;earliest_available[hr]=i+1;
10328 loop_start[hr]=MAXBLOCK;
10331 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10333 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1]) {
10334 for(hr=0;hr<HOST_REGS;hr++) {
10335 score[hr]=0;earliest_available[hr]=i+1;
10336 loop_start[hr]=MAXBLOCK;
10340 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1]) {
10341 for(hr=0;hr<HOST_REGS;hr++) {
10342 score[hr]=0;earliest_available[hr]=i+1;
10343 loop_start[hr]=MAXBLOCK;
10348 // Mark unavailable registers
10349 for(hr=0;hr<HOST_REGS;hr++) {
10350 if(regs[i].regmap[hr]>=0) {
10351 score[hr]=0;earliest_available[hr]=i+1;
10352 loop_start[hr]=MAXBLOCK;
10354 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10355 if(branch_regs[i].regmap[hr]>=0) {
10356 score[hr]=0;earliest_available[hr]=i+2;
10357 loop_start[hr]=MAXBLOCK;
10361 // No register allocations after unconditional jumps
10362 if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
10364 for(hr=0;hr<HOST_REGS;hr++) {
10365 score[hr]=0;earliest_available[hr]=i+2;
10366 loop_start[hr]=MAXBLOCK;
10368 i++; // Skip delay slot too
10369 //printf("skip delay slot: %x\n",start+i*4);
10373 if(itype[i]==LOAD||itype[i]==LOADLR||
10374 itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS) {
10375 for(hr=0;hr<HOST_REGS;hr++) {
10376 if(hr!=EXCLUDE_REG) {
10378 for(j=i;j<slen-1;j++) {
10379 if(regs[j].regmap[hr]>=0) break;
10380 if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10381 if(branch_regs[j].regmap[hr]>=0) break;
10383 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1]) break;
10385 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1]) break;
10388 else if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) break;
10389 if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10390 int t=(ba[j]-start)>>2;
10391 if(t<j&&t>=earliest_available[hr]) {
10392 if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) { // call/ret assumes no registers allocated
10393 // Score a point for hoisting loop invariant
10394 if(t<loop_start[hr]) loop_start[hr]=t;
10395 //printf("set loop_start: i=%x j=%x (%x)\n",start+i*4,start+j*4,start+t*4);
10401 if(regs[t].regmap[hr]==reg) {
10402 // Score a point if the branch target matches this register
10407 if(itype[j+1]==LOAD||itype[j+1]==LOADLR||
10408 itype[j+1]==STORE||itype[j+1]==STORELR||itype[j+1]==C1LS) {
10413 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10415 // Stop on unconditional branch
10419 if(itype[j]==LOAD||itype[j]==LOADLR||
10420 itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS) {
10427 // Find highest score and allocate that register
10429 for(hr=0;hr<HOST_REGS;hr++) {
10430 if(hr!=EXCLUDE_REG) {
10431 if(score[hr]>score[maxscore]) {
10433 //printf("highest score: %d %d (%x->%x)\n",score[hr],hr,start+i*4,start+end[hr]*4);
10437 if(score[maxscore]>1)
10439 if(i<loop_start[maxscore]) loop_start[maxscore]=i;
10440 for(j=loop_start[maxscore];j<slen&&j<=end[maxscore];j++) {
10441 //if(regs[j].regmap[maxscore]>=0) {printf("oops: %x %x was %d=%d\n",loop_start[maxscore]*4+start,j*4+start,maxscore,regs[j].regmap[maxscore]);}
10442 assert(regs[j].regmap[maxscore]<0);
10443 if(j>loop_start[maxscore]) regs[j].regmap_entry[maxscore]=reg;
10444 regs[j].regmap[maxscore]=reg;
10445 regs[j].dirty&=~(1<<maxscore);
10446 regs[j].wasconst&=~(1<<maxscore);
10447 regs[j].isconst&=~(1<<maxscore);
10448 if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10449 branch_regs[j].regmap[maxscore]=reg;
10450 branch_regs[j].wasdirty&=~(1<<maxscore);
10451 branch_regs[j].dirty&=~(1<<maxscore);
10452 branch_regs[j].wasconst&=~(1<<maxscore);
10453 branch_regs[j].isconst&=~(1<<maxscore);
10454 if(itype[j]!=RJUMP&&itype[j]!=UJUMP&&(source[j]>>16)!=0x1000) {
10455 regmap_pre[j+2][maxscore]=reg;
10456 regs[j+2].wasdirty&=~(1<<maxscore);
10458 // loop optimization (loop_preload)
10459 int t=(ba[j]-start)>>2;
10460 if(t==loop_start[maxscore]) {
10461 if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) // call/ret assumes no registers allocated
10462 regs[t].regmap_entry[maxscore]=reg;
10467 if(j<1||(itype[j-1]!=RJUMP&&itype[j-1]!=UJUMP&&itype[j-1]!=CJUMP&&itype[j-1]!=SJUMP&&itype[j-1]!=FJUMP)) {
10468 regmap_pre[j+1][maxscore]=reg;
10469 regs[j+1].wasdirty&=~(1<<maxscore);
10474 if(itype[j-1]==RJUMP||itype[j-1]==UJUMP||itype[j-1]==CJUMP||itype[j-1]==SJUMP||itype[j-1]==FJUMP) i++; // skip delay slot
10475 for(hr=0;hr<HOST_REGS;hr++) {
10476 score[hr]=0;earliest_available[hr]=i+i;
10477 loop_start[hr]=MAXBLOCK;
10485 // This allocates registers (if possible) one instruction prior
10486 // to use, which can avoid a load-use penalty on certain CPUs.
10487 for(i=0;i<slen-1;i++)
10489 if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP))
10493 if(itype[i]==ALU||itype[i]==MOV||itype[i]==LOAD||itype[i]==SHIFTIMM||itype[i]==IMM16
10494 ||((itype[i]==COP1||itype[i]==COP2)&&opcode2[i]<3))
10497 if((hr=get_reg(regs[i+1].regmap,rs1[i+1]))>=0)
10499 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10501 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10502 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10503 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10504 regs[i].isconst&=~(1<<hr);
10505 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10506 constmap[i][hr]=constmap[i+1][hr];
10507 regs[i+1].wasdirty&=~(1<<hr);
10508 regs[i].dirty&=~(1<<hr);
10513 if((hr=get_reg(regs[i+1].regmap,rs2[i+1]))>=0)
10515 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10517 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10518 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10519 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10520 regs[i].isconst&=~(1<<hr);
10521 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10522 constmap[i][hr]=constmap[i+1][hr];
10523 regs[i+1].wasdirty&=~(1<<hr);
10524 regs[i].dirty&=~(1<<hr);
10528 // Preload target address for load instruction (non-constant)
10529 if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10530 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10532 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10534 regs[i].regmap[hr]=rs1[i+1];
10535 regmap_pre[i+1][hr]=rs1[i+1];
10536 regs[i+1].regmap_entry[hr]=rs1[i+1];
10537 regs[i].isconst&=~(1<<hr);
10538 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10539 constmap[i][hr]=constmap[i+1][hr];
10540 regs[i+1].wasdirty&=~(1<<hr);
10541 regs[i].dirty&=~(1<<hr);
10545 // Load source into target register
10546 if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10547 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10549 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10551 regs[i].regmap[hr]=rs1[i+1];
10552 regmap_pre[i+1][hr]=rs1[i+1];
10553 regs[i+1].regmap_entry[hr]=rs1[i+1];
10554 regs[i].isconst&=~(1<<hr);
10555 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10556 constmap[i][hr]=constmap[i+1][hr];
10557 regs[i+1].wasdirty&=~(1<<hr);
10558 regs[i].dirty&=~(1<<hr);
10562 // Preload map address
10563 #ifndef HOST_IMM_ADDR32
10564 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
10565 hr=get_reg(regs[i+1].regmap,TLREG);
10567 int sr=get_reg(regs[i+1].regmap,rs1[i+1]);
10568 if(sr>=0&&((regs[i+1].wasconst>>sr)&1)) {
10570 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10572 regs[i].regmap[hr]=MGEN1+((i+1)&1);
10573 regmap_pre[i+1][hr]=MGEN1+((i+1)&1);
10574 regs[i+1].regmap_entry[hr]=MGEN1+((i+1)&1);
10575 regs[i].isconst&=~(1<<hr);
10576 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10577 constmap[i][hr]=constmap[i+1][hr];
10578 regs[i+1].wasdirty&=~(1<<hr);
10579 regs[i].dirty&=~(1<<hr);
10581 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10583 // move it to another register
10584 regs[i+1].regmap[hr]=-1;
10585 regmap_pre[i+2][hr]=-1;
10586 regs[i+1].regmap[nr]=TLREG;
10587 regmap_pre[i+2][nr]=TLREG;
10588 regs[i].regmap[nr]=MGEN1+((i+1)&1);
10589 regmap_pre[i+1][nr]=MGEN1+((i+1)&1);
10590 regs[i+1].regmap_entry[nr]=MGEN1+((i+1)&1);
10591 regs[i].isconst&=~(1<<nr);
10592 regs[i+1].isconst&=~(1<<nr);
10593 regs[i].dirty&=~(1<<nr);
10594 regs[i+1].wasdirty&=~(1<<nr);
10595 regs[i+1].dirty&=~(1<<nr);
10596 regs[i+2].wasdirty&=~(1<<nr);
10602 // Address for store instruction (non-constant)
10603 if(itype[i+1]==STORE||itype[i+1]==STORELR
10604 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
10605 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10606 hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
10607 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10608 else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
10610 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10612 regs[i].regmap[hr]=rs1[i+1];
10613 regmap_pre[i+1][hr]=rs1[i+1];
10614 regs[i+1].regmap_entry[hr]=rs1[i+1];
10615 regs[i].isconst&=~(1<<hr);
10616 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10617 constmap[i][hr]=constmap[i+1][hr];
10618 regs[i+1].wasdirty&=~(1<<hr);
10619 regs[i].dirty&=~(1<<hr);
10623 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
10624 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10626 hr=get_reg(regs[i+1].regmap,FTEMP);
10628 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10630 regs[i].regmap[hr]=rs1[i+1];
10631 regmap_pre[i+1][hr]=rs1[i+1];
10632 regs[i+1].regmap_entry[hr]=rs1[i+1];
10633 regs[i].isconst&=~(1<<hr);
10634 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10635 constmap[i][hr]=constmap[i+1][hr];
10636 regs[i+1].wasdirty&=~(1<<hr);
10637 regs[i].dirty&=~(1<<hr);
10639 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10641 // move it to another register
10642 regs[i+1].regmap[hr]=-1;
10643 regmap_pre[i+2][hr]=-1;
10644 regs[i+1].regmap[nr]=FTEMP;
10645 regmap_pre[i+2][nr]=FTEMP;
10646 regs[i].regmap[nr]=rs1[i+1];
10647 regmap_pre[i+1][nr]=rs1[i+1];
10648 regs[i+1].regmap_entry[nr]=rs1[i+1];
10649 regs[i].isconst&=~(1<<nr);
10650 regs[i+1].isconst&=~(1<<nr);
10651 regs[i].dirty&=~(1<<nr);
10652 regs[i+1].wasdirty&=~(1<<nr);
10653 regs[i+1].dirty&=~(1<<nr);
10654 regs[i+2].wasdirty&=~(1<<nr);
10658 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS||||itype[i+1]==C2LS*/) {
10659 if(itype[i+1]==LOAD)
10660 hr=get_reg(regs[i+1].regmap,rt1[i+1]);
10661 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
10662 hr=get_reg(regs[i+1].regmap,FTEMP);
10663 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
10664 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
10665 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10667 if(hr>=0&®s[i].regmap[hr]<0) {
10668 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
10669 if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
10670 regs[i].regmap[hr]=AGEN1+((i+1)&1);
10671 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
10672 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
10673 regs[i].isconst&=~(1<<hr);
10674 regs[i+1].wasdirty&=~(1<<hr);
10675 regs[i].dirty&=~(1<<hr);
10684 /* Pass 6 - Optimize clean/dirty state */
10685 clean_registers(0,slen-1,1);
10687 /* Pass 7 - Identify 32-bit registers */
10693 for (i=slen-1;i>=0;i--)
10696 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10698 if(ba[i]<start || ba[i]>=(start+slen*4))
10700 // Branch out of this block, don't need anything
10706 // Need whatever matches the target
10707 // (and doesn't get overwritten by the delay slot instruction)
10709 int t=(ba[i]-start)>>2;
10710 if(ba[i]>start+i*4) {
10712 if(!(requires_32bit[t]&~regs[i].was32))
10713 r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10716 //if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
10717 // r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10718 if(!(pr32[t]&~regs[i].was32))
10719 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10722 // Conditional branch may need registers for following instructions
10723 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10726 r32|=requires_32bit[i+2];
10727 r32&=regs[i].was32;
10728 // Mark this address as a branch target since it may be called
10729 // upon return from interrupt
10733 // Merge in delay slot
10735 // These are overwritten unless the branch is "likely"
10736 // and the delay slot is nullified if not taken
10737 r32&=~(1LL<<rt1[i+1]);
10738 r32&=~(1LL<<rt2[i+1]);
10740 // Assume these are needed (delay slot)
10743 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
10747 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
10749 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
10751 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
10753 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
10755 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
10758 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
10760 // SYSCALL instruction (software interrupt)
10763 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
10765 // ERET instruction (return from interrupt)
10769 r32&=~(1LL<<rt1[i]);
10770 r32&=~(1LL<<rt2[i]);
10773 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
10777 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
10779 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
10781 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
10783 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
10785 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
10787 requires_32bit[i]=r32;
10789 // Dirty registers which are 32-bit, require 32-bit input
10790 // as they will be written as 32-bit values
10791 for(hr=0;hr<HOST_REGS;hr++)
10793 if(regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64) {
10794 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
10795 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
10796 requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
10800 //requires_32bit[i]=is32[i]&~unneeded_reg_upper[i]; // DEBUG
10803 for (i=slen-1;i>=0;i--)
10805 if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10807 // Conditional branch
10808 if((source[i]>>16)!=0x1000&&i<slen-2) {
10809 // Mark this address as a branch target since it may be called
10810 // upon return from interrupt
10817 if(itype[slen-1]==SPAN) {
10818 bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
10821 /* Debug/disassembly */
10822 if((void*)assem_debug==(void*)printf)
10823 for(i=0;i<slen;i++)
10827 for(r=1;r<=CCREG;r++) {
10828 if((unneeded_reg[i]>>r)&1) {
10829 if(r==HIREG) printf(" HI");
10830 else if(r==LOREG) printf(" LO");
10831 else printf(" r%d",r);
10836 for(r=1;r<=CCREG;r++) {
10837 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
10838 if(r==HIREG) printf(" HI");
10839 else if(r==LOREG) printf(" LO");
10840 else printf(" r%d",r);
10844 for(r=0;r<=CCREG;r++) {
10845 //if(((is32[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10846 if((regs[i].was32>>r)&1) {
10847 if(r==CCREG) printf(" CC");
10848 else if(r==HIREG) printf(" HI");
10849 else if(r==LOREG) printf(" LO");
10850 else printf(" r%d",r);
10855 #if defined(__i386__) || defined(__x86_64__)
10856 printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
10859 printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
10862 if(needed_reg[i]&1) printf("eax ");
10863 if((needed_reg[i]>>1)&1) printf("ecx ");
10864 if((needed_reg[i]>>2)&1) printf("edx ");
10865 if((needed_reg[i]>>3)&1) printf("ebx ");
10866 if((needed_reg[i]>>5)&1) printf("ebp ");
10867 if((needed_reg[i]>>6)&1) printf("esi ");
10868 if((needed_reg[i]>>7)&1) printf("edi ");
10870 for(r=0;r<=CCREG;r++) {
10871 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10872 if((requires_32bit[i]>>r)&1) {
10873 if(r==CCREG) printf(" CC");
10874 else if(r==HIREG) printf(" HI");
10875 else if(r==LOREG) printf(" LO");
10876 else printf(" r%d",r);
10881 for(r=0;r<=CCREG;r++) {
10882 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10883 if((pr32[i]>>r)&1) {
10884 if(r==CCREG) printf(" CC");
10885 else if(r==HIREG) printf(" HI");
10886 else if(r==LOREG) printf(" LO");
10887 else printf(" r%d",r);
10890 if(pr32[i]!=requires_32bit[i]) printf(" OOPS");
10892 #if defined(__i386__) || defined(__x86_64__)
10893 printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
10895 if(regs[i].wasdirty&1) printf("eax ");
10896 if((regs[i].wasdirty>>1)&1) printf("ecx ");
10897 if((regs[i].wasdirty>>2)&1) printf("edx ");
10898 if((regs[i].wasdirty>>3)&1) printf("ebx ");
10899 if((regs[i].wasdirty>>5)&1) printf("ebp ");
10900 if((regs[i].wasdirty>>6)&1) printf("esi ");
10901 if((regs[i].wasdirty>>7)&1) printf("edi ");
10904 printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
10906 if(regs[i].wasdirty&1) printf("r0 ");
10907 if((regs[i].wasdirty>>1)&1) printf("r1 ");
10908 if((regs[i].wasdirty>>2)&1) printf("r2 ");
10909 if((regs[i].wasdirty>>3)&1) printf("r3 ");
10910 if((regs[i].wasdirty>>4)&1) printf("r4 ");
10911 if((regs[i].wasdirty>>5)&1) printf("r5 ");
10912 if((regs[i].wasdirty>>6)&1) printf("r6 ");
10913 if((regs[i].wasdirty>>7)&1) printf("r7 ");
10914 if((regs[i].wasdirty>>8)&1) printf("r8 ");
10915 if((regs[i].wasdirty>>9)&1) printf("r9 ");
10916 if((regs[i].wasdirty>>10)&1) printf("r10 ");
10917 if((regs[i].wasdirty>>12)&1) printf("r12 ");
10920 disassemble_inst(i);
10921 //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
10922 #if defined(__i386__) || defined(__x86_64__)
10923 printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
10924 if(regs[i].dirty&1) printf("eax ");
10925 if((regs[i].dirty>>1)&1) printf("ecx ");
10926 if((regs[i].dirty>>2)&1) printf("edx ");
10927 if((regs[i].dirty>>3)&1) printf("ebx ");
10928 if((regs[i].dirty>>5)&1) printf("ebp ");
10929 if((regs[i].dirty>>6)&1) printf("esi ");
10930 if((regs[i].dirty>>7)&1) printf("edi ");
10933 printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
10934 if(regs[i].dirty&1) printf("r0 ");
10935 if((regs[i].dirty>>1)&1) printf("r1 ");
10936 if((regs[i].dirty>>2)&1) printf("r2 ");
10937 if((regs[i].dirty>>3)&1) printf("r3 ");
10938 if((regs[i].dirty>>4)&1) printf("r4 ");
10939 if((regs[i].dirty>>5)&1) printf("r5 ");
10940 if((regs[i].dirty>>6)&1) printf("r6 ");
10941 if((regs[i].dirty>>7)&1) printf("r7 ");
10942 if((regs[i].dirty>>8)&1) printf("r8 ");
10943 if((regs[i].dirty>>9)&1) printf("r9 ");
10944 if((regs[i].dirty>>10)&1) printf("r10 ");
10945 if((regs[i].dirty>>12)&1) printf("r12 ");
10948 if(regs[i].isconst) {
10949 printf("constants: ");
10950 #if defined(__i386__) || defined(__x86_64__)
10951 if(regs[i].isconst&1) printf("eax=%x ",(int)constmap[i][0]);
10952 if((regs[i].isconst>>1)&1) printf("ecx=%x ",(int)constmap[i][1]);
10953 if((regs[i].isconst>>2)&1) printf("edx=%x ",(int)constmap[i][2]);
10954 if((regs[i].isconst>>3)&1) printf("ebx=%x ",(int)constmap[i][3]);
10955 if((regs[i].isconst>>5)&1) printf("ebp=%x ",(int)constmap[i][5]);
10956 if((regs[i].isconst>>6)&1) printf("esi=%x ",(int)constmap[i][6]);
10957 if((regs[i].isconst>>7)&1) printf("edi=%x ",(int)constmap[i][7]);
10960 if(regs[i].isconst&1) printf("r0=%x ",(int)constmap[i][0]);
10961 if((regs[i].isconst>>1)&1) printf("r1=%x ",(int)constmap[i][1]);
10962 if((regs[i].isconst>>2)&1) printf("r2=%x ",(int)constmap[i][2]);
10963 if((regs[i].isconst>>3)&1) printf("r3=%x ",(int)constmap[i][3]);
10964 if((regs[i].isconst>>4)&1) printf("r4=%x ",(int)constmap[i][4]);
10965 if((regs[i].isconst>>5)&1) printf("r5=%x ",(int)constmap[i][5]);
10966 if((regs[i].isconst>>6)&1) printf("r6=%x ",(int)constmap[i][6]);
10967 if((regs[i].isconst>>7)&1) printf("r7=%x ",(int)constmap[i][7]);
10968 if((regs[i].isconst>>8)&1) printf("r8=%x ",(int)constmap[i][8]);
10969 if((regs[i].isconst>>9)&1) printf("r9=%x ",(int)constmap[i][9]);
10970 if((regs[i].isconst>>10)&1) printf("r10=%x ",(int)constmap[i][10]);
10971 if((regs[i].isconst>>12)&1) printf("r12=%x ",(int)constmap[i][12]);
10977 for(r=0;r<=CCREG;r++) {
10978 if((regs[i].is32>>r)&1) {
10979 if(r==CCREG) printf(" CC");
10980 else if(r==HIREG) printf(" HI");
10981 else if(r==LOREG) printf(" LO");
10982 else printf(" r%d",r);
10988 for(r=0;r<=CCREG;r++) {
10989 if((p32[i]>>r)&1) {
10990 if(r==CCREG) printf(" CC");
10991 else if(r==HIREG) printf(" HI");
10992 else if(r==LOREG) printf(" LO");
10993 else printf(" r%d",r);
10996 if(p32[i]!=regs[i].is32) printf(" NO MATCH\n");
10997 else printf("\n");*/
10998 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10999 #if defined(__i386__) || defined(__x86_64__)
11000 printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
11001 if(branch_regs[i].dirty&1) printf("eax ");
11002 if((branch_regs[i].dirty>>1)&1) printf("ecx ");
11003 if((branch_regs[i].dirty>>2)&1) printf("edx ");
11004 if((branch_regs[i].dirty>>3)&1) printf("ebx ");
11005 if((branch_regs[i].dirty>>5)&1) printf("ebp ");
11006 if((branch_regs[i].dirty>>6)&1) printf("esi ");
11007 if((branch_regs[i].dirty>>7)&1) printf("edi ");
11010 printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
11011 if(branch_regs[i].dirty&1) printf("r0 ");
11012 if((branch_regs[i].dirty>>1)&1) printf("r1 ");
11013 if((branch_regs[i].dirty>>2)&1) printf("r2 ");
11014 if((branch_regs[i].dirty>>3)&1) printf("r3 ");
11015 if((branch_regs[i].dirty>>4)&1) printf("r4 ");
11016 if((branch_regs[i].dirty>>5)&1) printf("r5 ");
11017 if((branch_regs[i].dirty>>6)&1) printf("r6 ");
11018 if((branch_regs[i].dirty>>7)&1) printf("r7 ");
11019 if((branch_regs[i].dirty>>8)&1) printf("r8 ");
11020 if((branch_regs[i].dirty>>9)&1) printf("r9 ");
11021 if((branch_regs[i].dirty>>10)&1) printf("r10 ");
11022 if((branch_regs[i].dirty>>12)&1) printf("r12 ");
11026 for(r=0;r<=CCREG;r++) {
11027 if((branch_regs[i].is32>>r)&1) {
11028 if(r==CCREG) printf(" CC");
11029 else if(r==HIREG) printf(" HI");
11030 else if(r==LOREG) printf(" LO");
11031 else printf(" r%d",r);
11039 /* Pass 8 - Assembly */
11040 linkcount=0;stubcount=0;
11041 ds=0;is_delayslot=0;
11043 uint64_t is32_pre=0;
11045 u_int beginning=(u_int)out;
11046 if((u_int)addr&1) {
11050 u_int instr_addr0_override=0;
11053 if (start == 0x80030000) {
11054 // nasty hack for fastbios thing
11055 // override block entry to this code
11056 instr_addr0_override=(u_int)out;
11057 emit_movimm(start,0);
11058 // abuse io address var as a flag that we
11059 // have already returned here once
11060 emit_readword((int)&address,1);
11061 emit_writeword(0,(int)&pcaddr);
11062 emit_writeword(0,(int)&address);
11064 emit_jne((int)new_dyna_leave);
11067 for(i=0;i<slen;i++)
11069 //if(ds) printf("ds: ");
11070 if((void*)assem_debug==(void*)printf) disassemble_inst(i);
11072 ds=0; // Skip delay slot
11073 if(bt[i]) assem_debug("OOPS - branch into delay slot\n");
11076 #ifndef DESTRUCTIVE_WRITEBACK
11077 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
11079 wb_sx(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,is32_pre,regs[i].was32,
11080 unneeded_reg[i],unneeded_reg_upper[i]);
11081 wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre,
11082 unneeded_reg[i],unneeded_reg_upper[i]);
11084 if((itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)&&!likely[i]) {
11085 is32_pre=branch_regs[i].is32;
11086 dirty_pre=branch_regs[i].dirty;
11088 is32_pre=regs[i].is32;
11089 dirty_pre=regs[i].dirty;
11093 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
11095 wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32,
11096 unneeded_reg[i],unneeded_reg_upper[i]);
11097 loop_preload(regmap_pre[i],regs[i].regmap_entry);
11099 // branch target entry point
11100 instr_addr[i]=(u_int)out;
11101 assem_debug("<->\n");
11103 if(regs[i].regmap_entry[HOST_CCREG]==CCREG&®s[i].regmap[HOST_CCREG]!=CCREG)
11104 wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32);
11105 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
11106 address_generation(i,®s[i],regs[i].regmap_entry);
11107 load_consts(regmap_pre[i],regs[i].regmap,regs[i].was32,i);
11108 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
11110 // Load the delay slot registers if necessary
11111 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i]&&(rs1[i+1]!=rt1[i]||rt1[i]==0))
11112 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
11113 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i]&&(rs2[i+1]!=rt1[i]||rt1[i]==0))
11114 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
11115 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a)
11116 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
11120 // Preload registers for following instruction
11121 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
11122 if(rs1[i+1]!=rt1[i]&&rs1[i+1]!=rt2[i])
11123 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
11124 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
11125 if(rs2[i+1]!=rt1[i]&&rs2[i+1]!=rt2[i])
11126 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
11128 // TODO: if(is_ooo(i)) address_generation(i+1);
11129 if(itype[i]==CJUMP||itype[i]==FJUMP)
11130 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
11131 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a)
11132 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
11133 if(bt[i]) cop1_usable=0;
11137 alu_assemble(i,®s[i]);break;
11139 imm16_assemble(i,®s[i]);break;
11141 shift_assemble(i,®s[i]);break;
11143 shiftimm_assemble(i,®s[i]);break;
11145 load_assemble(i,®s[i]);break;
11147 loadlr_assemble(i,®s[i]);break;
11149 store_assemble(i,®s[i]);break;
11151 storelr_assemble(i,®s[i]);break;
11153 cop0_assemble(i,®s[i]);break;
11155 cop1_assemble(i,®s[i]);break;
11157 c1ls_assemble(i,®s[i]);break;
11159 cop2_assemble(i,®s[i]);break;
11161 c2ls_assemble(i,®s[i]);break;
11163 c2op_assemble(i,®s[i]);break;
11165 fconv_assemble(i,®s[i]);break;
11167 float_assemble(i,®s[i]);break;
11169 fcomp_assemble(i,®s[i]);break;
11171 multdiv_assemble(i,®s[i]);break;
11173 mov_assemble(i,®s[i]);break;
11175 syscall_assemble(i,®s[i]);break;
11177 hlecall_assemble(i,®s[i]);break;
11179 intcall_assemble(i,®s[i]);break;
11181 ujump_assemble(i,®s[i]);ds=1;break;
11183 rjump_assemble(i,®s[i]);ds=1;break;
11185 cjump_assemble(i,®s[i]);ds=1;break;
11187 sjump_assemble(i,®s[i]);ds=1;break;
11189 fjump_assemble(i,®s[i]);ds=1;break;
11191 pagespan_assemble(i,®s[i]);break;
11193 if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
11194 literal_pool(1024);
11196 literal_pool_jumpover(256);
11199 //assert(itype[i-2]==UJUMP||itype[i-2]==RJUMP||(source[i-2]>>16)==0x1000);
11200 // If the block did not end with an unconditional branch,
11201 // add a jump to the next instruction.
11203 if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) {
11204 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
11206 if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP&&itype[i-2]!=FJUMP) {
11207 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
11208 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
11209 emit_loadreg(CCREG,HOST_CCREG);
11210 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
11212 else if(!likely[i-2])
11214 store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].is32,branch_regs[i-2].dirty,start+i*4);
11215 assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
11219 store_regs_bt(regs[i-2].regmap,regs[i-2].is32,regs[i-2].dirty,start+i*4);
11220 assert(regs[i-2].regmap[HOST_CCREG]==CCREG);
11222 add_to_linker((int)out,start+i*4,0);
11229 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
11230 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
11231 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
11232 emit_loadreg(CCREG,HOST_CCREG);
11233 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
11234 add_to_linker((int)out,start+i*4,0);
11238 // TODO: delay slot stubs?
11240 for(i=0;i<stubcount;i++)
11242 switch(stubs[i][0])
11250 do_readstub(i);break;
11255 do_writestub(i);break;
11257 do_ccstub(i);break;
11259 do_invstub(i);break;
11261 do_cop1stub(i);break;
11263 do_unalignedwritestub(i);break;
11267 if (instr_addr0_override)
11268 instr_addr[0] = instr_addr0_override;
11270 /* Pass 9 - Linker */
11271 for(i=0;i<linkcount;i++)
11273 assem_debug("%8x -> %8x\n",link_addr[i][0],link_addr[i][1]);
11275 if(!link_addr[i][2])
11278 void *addr=check_addr(link_addr[i][1]);
11279 emit_extjump(link_addr[i][0],link_addr[i][1]);
11281 set_jump_target(link_addr[i][0],(int)addr);
11282 add_link(link_addr[i][1],stub);
11284 else set_jump_target(link_addr[i][0],(int)stub);
11289 int target=(link_addr[i][1]-start)>>2;
11290 assert(target>=0&&target<slen);
11291 assert(instr_addr[target]);
11292 //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11293 //set_jump_target_fillslot(link_addr[i][0],instr_addr[target],link_addr[i][2]>>1);
11295 set_jump_target(link_addr[i][0],instr_addr[target]);
11299 // External Branch Targets (jump_in)
11300 if(copy+slen*4>(void *)shadow+sizeof(shadow)) copy=shadow;
11301 for(i=0;i<slen;i++)
11305 if(instr_addr[i]) // TODO - delay slots (=null)
11307 u_int vaddr=start+i*4;
11308 u_int page=get_page(vaddr);
11309 u_int vpage=get_vpage(vaddr);
11311 //if(!(is32[i]&(~unneeded_reg_upper[i])&~(1LL<<CCREG)))
11313 if(!requires_32bit[i])
11318 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
11319 assem_debug("jump_in: %x\n",start+i*4);
11320 ll_add(jump_dirty+vpage,vaddr,(void *)out);
11321 int entry_point=do_dirty_stub(i);
11322 ll_add(jump_in+page,vaddr,(void *)entry_point);
11323 // If there was an existing entry in the hash table,
11324 // replace it with the new address.
11325 // Don't add new entries. We'll insert the
11326 // ones that actually get used in check_addr().
11327 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
11328 if(ht_bin[0]==vaddr) {
11329 ht_bin[1]=entry_point;
11331 if(ht_bin[2]==vaddr) {
11332 ht_bin[3]=entry_point;
11337 u_int r=requires_32bit[i]|!!(requires_32bit[i]>>32);
11338 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
11339 assem_debug("jump_in: %x (restricted - %x)\n",start+i*4,r);
11340 //int entry_point=(int)out;
11341 ////assem_debug("entry_point: %x\n",entry_point);
11342 //load_regs_entry(i);
11343 //if(entry_point==(int)out)
11344 // entry_point=instr_addr[i];
11346 // emit_jmp(instr_addr[i]);
11347 //ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11348 ll_add_32(jump_dirty+vpage,vaddr,r,(void *)out);
11349 int entry_point=do_dirty_stub(i);
11350 ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11355 // Write out the literal pool if necessary
11357 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11359 if(((u_int)out)&7) emit_addnop(13);
11361 assert((u_int)out-beginning<MAX_OUTPUT_BLOCK_SIZE);
11362 //printf("shadow buffer: %x-%x\n",(int)copy,(int)copy+slen*4);
11363 memcpy(copy,source,slen*4);
11367 __clear_cache((void *)beginning,out);
11370 // If we're within 256K of the end of the buffer,
11371 // start over from the beginning. (Is 256K enough?)
11372 if((int)out>BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR;
11374 // Trap writes to any of the pages we compiled
11375 for(i=start>>12;i<=(start+slen*4)>>12;i++) {
11377 #ifndef DISABLE_TLB
11378 memory_map[i]|=0x40000000;
11379 if((signed int)start>=(signed int)0xC0000000) {
11381 j=(((u_int)i<<12)+(memory_map[i]<<2)-(u_int)rdram+(u_int)0x80000000)>>12;
11383 memory_map[j]|=0x40000000;
11384 //printf("write protect physical page: %x (virtual %x)\n",j<<12,start);
11388 inv_code_start=inv_code_end=~0;
11390 // PCSX maps all RAM mirror invalid_code tests to 0x80000000..0x80000000+RAM_SIZE
11391 if(get_page(start)<(RAM_SIZE>>12))
11392 for(i=start>>12;i<=(start+slen*4)>>12;i++)
11393 invalid_code[((u_int)0x80000000>>12)|i]=0;
11396 /* Pass 10 - Free memory by expiring oldest blocks */
11398 int end=((((int)out-BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535;
11399 while(expirep!=end)
11401 int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
11402 int base=BASE_ADDR+((expirep>>13)<<shift); // Base address of this block
11403 inv_debug("EXP: Phase %d\n",expirep);
11404 switch((expirep>>11)&3)
11407 // Clear jump_in and jump_dirty
11408 ll_remove_matching_addrs(jump_in+(expirep&2047),base,shift);
11409 ll_remove_matching_addrs(jump_dirty+(expirep&2047),base,shift);
11410 ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base,shift);
11411 ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base,shift);
11415 ll_kill_pointers(jump_out[expirep&2047],base,shift);
11416 ll_kill_pointers(jump_out[(expirep&2047)+2048],base,shift);
11419 // Clear hash table
11420 for(i=0;i<32;i++) {
11421 int *ht_bin=hash_table[((expirep&2047)<<5)+i];
11422 if((ht_bin[3]>>shift)==(base>>shift) ||
11423 ((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11424 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[2],ht_bin[3]);
11425 ht_bin[2]=ht_bin[3]=-1;
11427 if((ht_bin[1]>>shift)==(base>>shift) ||
11428 ((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11429 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[0],ht_bin[1]);
11430 ht_bin[0]=ht_bin[2];
11431 ht_bin[1]=ht_bin[3];
11432 ht_bin[2]=ht_bin[3]=-1;
11439 if((expirep&2047)==0)
11442 ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);
11443 ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base,shift);
11446 expirep=(expirep+1)&65535;
11451 // vim:shiftwidth=2:expandtab