1 /***************************************************************************
2 * Copyright (C) 2010 by Blade_Arma *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. *
18 ***************************************************************************/
21 * Internal PSX counters.
24 #include "psxcounters.h"
27 /******************************************************************************/
32 u32 rate, irq, counterState, irqState;
33 u32 cycle, cycleStart;
38 Rc0Gate = 0x0001, // 0 not implemented
39 Rc1Gate = 0x0001, // 0 not implemented
40 Rc2Disable = 0x0001, // 0 partially implemented
41 RcUnknown1 = 0x0002, // 1 ?
42 RcUnknown2 = 0x0004, // 2 ?
43 RcCountToTarget = 0x0008, // 3
44 RcIrqOnTarget = 0x0010, // 4
45 RcIrqOnOverflow = 0x0020, // 5
46 RcIrqRegenerate = 0x0040, // 6
47 RcUnknown7 = 0x0080, // 7 ?
48 Rc0PixelClock = 0x0100, // 8 fake implementation
49 Rc1HSyncClock = 0x0100, // 8
50 Rc2Unknown8 = 0x0100, // 8 ?
51 Rc0Unknown9 = 0x0200, // 9 ?
52 Rc1Unknown9 = 0x0200, // 9 ?
53 Rc2OneEighthClock = 0x0200, // 9
54 RcUnknown10 = 0x0400, // 10 ?
55 RcCountEqTarget = 0x0800, // 11
56 RcOverflow = 0x1000, // 12
57 RcUnknown13 = 0x2000, // 13 ? (always zero)
58 RcUnknown14 = 0x4000, // 14 ? (always zero)
59 RcUnknown15 = 0x8000, // 15 ? (always zero)
62 #define CounterQuantity ( 4 )
63 //static const u32 CounterQuantity = 4;
65 static const u32 CountToOverflow = 0;
66 static const u32 CountToTarget = 1;
68 static const u32 FrameRate[] = { 60, 50 };
69 static const u32 VBlankStart[] = { 240, 256 };
70 static const u32 HSyncTotal[] = { 263, 313 };
71 static const u32 SpuUpdInterval[] = { 32, 32 };
73 #define VERBOSE_LEVEL 0
74 static const s32 VerboseLevel = VERBOSE_LEVEL;
76 /******************************************************************************/
78 static Rcnt rcnts[ CounterQuantity ];
80 static u32 hSyncCount = 0;
81 static u32 spuSyncCount = 0;
82 static u32 hsync_steps = 0;
83 static u32 gpu_wants_hcnt = 0;
85 u32 psxNextCounter = 0, psxNextsCounter = 0;
87 /******************************************************************************/
90 void setIrq( u32 irq )
92 psxHu32ref(0x1070) |= SWAPu32(irq);
96 void verboseLog( u32 level, const char *str, ... )
99 if( level <= VerboseLevel )
105 vsprintf( buf, str, va );
114 /******************************************************************************/
117 void _psxRcntWcount( u32 index, u32 value )
121 verboseLog( 1, "[RCNT %i] wcount > 0xffff: %x\n", index, value );
125 rcnts[index].cycleStart = psxRegs.cycle;
126 rcnts[index].cycleStart -= value * rcnts[index].rate;
129 if( value < rcnts[index].target )
131 rcnts[index].cycle = rcnts[index].target * rcnts[index].rate;
132 rcnts[index].counterState = CountToTarget;
136 rcnts[index].cycle = 0xffff * rcnts[index].rate;
137 rcnts[index].counterState = CountToOverflow;
142 u32 _psxRcntRcount( u32 index )
146 count = psxRegs.cycle;
147 count -= rcnts[index].cycleStart;
148 if (rcnts[index].rate > 1)
149 count /= rcnts[index].rate;
153 verboseLog( 1, "[RCNT %i] rcount > 0xffff: %x\n", index, count );
160 /******************************************************************************/
168 psxNextsCounter = psxRegs.cycle;
169 psxNextCounter = 0x7fffffff;
171 for( i = 0; i < CounterQuantity; ++i )
173 countToUpdate = rcnts[i].cycle - (psxNextsCounter - rcnts[i].cycleStart);
175 if( countToUpdate < 0 )
181 if( countToUpdate < (s32)psxNextCounter )
183 psxNextCounter = countToUpdate;
188 /******************************************************************************/
191 void psxRcntReset( u32 index )
195 if( rcnts[index].counterState == CountToTarget )
197 if( rcnts[index].mode & RcCountToTarget )
199 count = psxRegs.cycle;
200 count -= rcnts[index].cycleStart;
201 if (rcnts[index].rate > 1)
202 count /= rcnts[index].rate;
203 count -= rcnts[index].target;
207 count = _psxRcntRcount( index );
210 _psxRcntWcount( index, count );
212 if( rcnts[index].mode & RcIrqOnTarget )
214 if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) )
216 verboseLog( 3, "[RCNT %i] irq: %x\n", index, count );
217 setIrq( rcnts[index].irq );
218 rcnts[index].irqState = 1;
222 rcnts[index].mode |= RcCountEqTarget;
224 else if( rcnts[index].counterState == CountToOverflow )
226 count = psxRegs.cycle;
227 count -= rcnts[index].cycleStart;
228 if (rcnts[index].rate > 1)
229 count /= rcnts[index].rate;
232 _psxRcntWcount( index, count );
234 if( rcnts[index].mode & RcIrqOnOverflow )
236 if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) )
238 verboseLog( 3, "[RCNT %i] irq: %x\n", index, count );
239 setIrq( rcnts[index].irq );
240 rcnts[index].irqState = 1;
244 rcnts[index].mode |= RcOverflow;
247 rcnts[index].mode |= RcUnknown10;
256 cycle = psxRegs.cycle;
259 if( cycle - rcnts[0].cycleStart >= rcnts[0].cycle )
265 if( cycle - rcnts[1].cycleStart >= rcnts[1].cycle )
271 if( cycle - rcnts[2].cycleStart >= rcnts[2].cycle )
277 if( cycle - rcnts[3].cycleStart >= rcnts[3].cycle )
279 u32 leftover_cycles = cycle - rcnts[3].cycleStart - rcnts[3].cycle;
280 u32 next_vsync, next_lace;
282 spuSyncCount += hsync_steps;
283 hSyncCount += hsync_steps;
286 if( spuSyncCount >= SpuUpdInterval[Config.PsxType] )
292 SPU_async( SpuUpdInterval[Config.PsxType] * rcnts[3].target );
297 if( hSyncCount == VBlankStart[Config.PsxType] )
299 GPU_vBlank( 1, &hSyncCount, &gpu_wants_hcnt );
301 // For the best times. :D
305 // Update lace. (with InuYasha fix)
306 if( hSyncCount >= (Config.VSyncWA ? HSyncTotal[Config.PsxType] / BIAS : HSyncTotal[Config.PsxType]) )
310 GPU_vBlank( 0, &hSyncCount, &gpu_wants_hcnt );
317 // Schedule next call, in hsyncs
318 hsync_steps = SpuUpdInterval[Config.PsxType] - spuSyncCount;
319 next_vsync = VBlankStart[Config.PsxType] - hSyncCount; // ok to overflow
320 next_lace = HSyncTotal[Config.PsxType] - hSyncCount;
321 if( next_vsync && next_vsync < hsync_steps )
322 hsync_steps = next_vsync;
323 if( next_lace && next_lace < hsync_steps )
324 hsync_steps = next_lace;
328 rcnts[3].cycleStart = cycle - leftover_cycles;
329 rcnts[3].cycle = hsync_steps * rcnts[3].target;
338 /******************************************************************************/
340 void psxRcntWcount( u32 index, u32 value )
342 verboseLog( 2, "[RCNT %i] wcount: %x\n", index, value );
344 _psxRcntWcount( index, value );
348 void psxRcntWmode( u32 index, u32 value )
350 verboseLog( 1, "[RCNT %i] wmode: %x\n", index, value );
352 rcnts[index].mode = value;
353 rcnts[index].irqState = 0;
358 if( value & Rc0PixelClock )
360 rcnts[index].rate = 5;
364 rcnts[index].rate = 1;
368 if( value & Rc1HSyncClock )
370 rcnts[index].rate = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType]));
374 rcnts[index].rate = 1;
378 if( value & Rc2OneEighthClock )
380 rcnts[index].rate = 8;
384 rcnts[index].rate = 1;
387 // TODO: wcount must work.
388 if( value & Rc2Disable )
390 rcnts[index].rate = 0xffffffff;
395 _psxRcntWcount( index, 0 );
399 void psxRcntWtarget( u32 index, u32 value )
401 verboseLog( 1, "[RCNT %i] wtarget: %x\n", index, value );
403 rcnts[index].target = value;
405 _psxRcntWcount( index, _psxRcntRcount( index ) );
409 /******************************************************************************/
411 u32 psxRcntRcount( u32 index )
415 count = _psxRcntRcount( index );
417 // Parasite Eve 2 fix.
422 if( rcnts[index].counterState == CountToTarget )
429 verboseLog( 2, "[RCNT %i] rcount: %x\n", index, count );
434 u32 psxRcntRmode( u32 index )
438 mode = rcnts[index].mode;
439 rcnts[index].mode &= 0xe7ff;
441 verboseLog( 2, "[RCNT %i] rmode: %x\n", index, mode );
446 u32 psxRcntRtarget( u32 index )
448 verboseLog( 2, "[RCNT %i] rtarget: %x\n", index, rcnts[index].target );
450 return rcnts[index].target;
453 /******************************************************************************/
473 rcnts[3].mode = RcCountToTarget;
474 rcnts[3].target = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType]));
476 for( i = 0; i < CounterQuantity; ++i )
478 _psxRcntWcount( i, 0 );
488 /******************************************************************************/
490 s32 psxRcntFreeze( gzFile f, s32 Mode )
492 gzfreeze( &rcnts, sizeof(rcnts) );
493 gzfreeze( &hSyncCount, sizeof(hSyncCount) );
494 gzfreeze( &spuSyncCount, sizeof(spuSyncCount) );
495 gzfreeze( &psxNextCounter, sizeof(psxNextCounter) );
496 gzfreeze( &psxNextsCounter, sizeof(psxNextsCounter) );
499 hsync_steps = (psxRegs.cycle - rcnts[3].cycleStart) / rcnts[3].target;
504 /******************************************************************************/