libpcsxcore/psxcounters.c

   1 /***************************************************************************
   2  *   Copyright (C) 2010 by Blade_Arma                                      *
   3  *                                                                         *
   4  *   This program is free software; you can redistribute it and/or modify  *
   5  *   it under the terms of the GNU General Public License as published by  *
   6  *   the Free Software Foundation; either version 2 of the License, or     *
   7  *   (at your option) any later version.                                   *
   8  *                                                                         *
   9  *   This program is distributed in the hope that it will be useful,       *
  10  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  11  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  12  *   GNU General Public License for more details.                          *
  13  *                                                                         *
  14  *   You should have received a copy of the GNU General Public License     *
  15  *   along with this program; if not, write to the                         *
  16  *   Free Software Foundation, Inc.,                                       *
  17  *   51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA.           *
  18  ***************************************************************************/
  19
  20 /*
  21  * Internal PSX counters.
  22  */
  23
  24 #include "psxcounters.h"
  25 #include "gpu.h"
  26 //#include "debug.h"
  27 #define DebugVSync()
  28
  29 /******************************************************************************/
  30
  31 enum
  32 {
  33     Rc0Gate           = 0x0001, // 0    not implemented
  34     Rc1Gate           = 0x0001, // 0    not implemented
  35     Rc2Disable        = 0x0001, // 0    partially implemented
  36     RcUnknown1        = 0x0002, // 1    ?
  37     RcUnknown2        = 0x0004, // 2    ?
  38     RcCountToTarget   = 0x0008, // 3
  39     RcIrqOnTarget     = 0x0010, // 4
  40     RcIrqOnOverflow   = 0x0020, // 5
  41     RcIrqRegenerate   = 0x0040, // 6
  42     RcUnknown7        = 0x0080, // 7    ?
  43     Rc0PixelClock     = 0x0100, // 8    fake implementation
  44     Rc1HSyncClock     = 0x0100, // 8
  45     Rc2Unknown8       = 0x0100, // 8    ?
  46     Rc0Unknown9       = 0x0200, // 9    ?
  47     Rc1Unknown9       = 0x0200, // 9    ?
  48     Rc2OneEighthClock = 0x0200, // 9
  49     RcUnknown10       = 0x0400, // 10   ?
  50     RcCountEqTarget   = 0x0800, // 11
  51     RcOverflow        = 0x1000, // 12
  52     RcUnknown13       = 0x2000, // 13   ? (always zero)
  53     RcUnknown14       = 0x4000, // 14   ? (always zero)
  54     RcUnknown15       = 0x8000, // 15   ? (always zero)
  55 };
  56
  57 #define CounterQuantity           ( 4 )
  58 //static const u32 CounterQuantity  = 4;
  59
  60 static const u32 CountToOverflow  = 0;
  61 static const u32 CountToTarget    = 1;
  62
  63 static const u32 FrameRate[]      = { 60, 50 };
  64 static const u32 HSyncTotal[]     = { 263, 314 }; // actually one more on odd lines for PAL
  65 #define VBlankStart 240
  66
  67 #define VERBOSE_LEVEL 0
  68
  69 /******************************************************************************/
  70 #ifdef DRC_DISABLE
  71 Rcnt rcnts[ CounterQuantity ];
  72 #endif
  73 u32 hSyncCount = 0;
  74 u32 frame_counter = 0;
  75 static u32 hsync_steps = 0;
  76
  77 u32 psxNextCounter = 0, psxNextsCounter = 0;
  78
  79 /******************************************************************************/
  80
  81 static inline
  82 void setIrq( u32 irq )
  83 {
  84     psxHu32ref(0x1070) |= SWAPu32(irq);
  85 }
  86
  87 static
  88 void verboseLog( u32 level, const char *str, ... )
  89 {
  90 #if VERBOSE_LEVEL > 0
  91     if( level <= VERBOSE_LEVEL )
  92     {
  93         va_list va;
  94         char buf[ 4096 ];
  95
  96         va_start( va, str );
  97         vsprintf( buf, str, va );
  98         va_end( va );
  99
 100         printf( "%s", buf );
 101         fflush( stdout );
 102     }
 103 #endif
 104 }
 105
 106 /******************************************************************************/
 107
 108 static inline
 109 void _psxRcntWcount( u32 index, u32 value )
 110 {
 111     if( value > 0xffff )
 112     {
 113         verboseLog( 1, "[RCNT %i] wcount > 0xffff: %x\n", index, value );
 114         value &= 0xffff;
 115     }
 116
 117     rcnts[index].cycleStart  = psxRegs.cycle;
 118     rcnts[index].cycleStart -= value * rcnts[index].rate;
 119
 120     // TODO: <=.
 121     if( value < rcnts[index].target )
 122     {
 123         rcnts[index].cycle = rcnts[index].target * rcnts[index].rate;
 124         rcnts[index].counterState = CountToTarget;
 125     }
 126     else
 127     {
 128         rcnts[index].cycle = 0x10000 * rcnts[index].rate;
 129         rcnts[index].counterState = CountToOverflow;
 130     }
 131 }
 132
 133 static inline
 134 u32 _psxRcntRcount( u32 index )
 135 {
 136     u32 count;
 137
 138     count  = psxRegs.cycle;
 139     count -= rcnts[index].cycleStart;
 140     if (rcnts[index].rate > 1)
 141         count /= rcnts[index].rate;
 142
 143     if( count > 0x10000 )
 144     {
 145         verboseLog( 1, "[RCNT %i] rcount > 0x10000: %x\n", index, count );
 146     }
 147     count &= 0xffff;
 148
 149     return count;
 150 }
 151
 152 static
 153 void _psxRcntWmode( u32 index, u32 value )
 154 {
 155     rcnts[index].mode = value;
 156
 157     switch( index )
 158     {
 159         case 0:
 160             if( value & Rc0PixelClock )
 161             {
 162                 rcnts[index].rate = 5;
 163             }
 164             else
 165             {
 166                 rcnts[index].rate = 1;
 167             }
 168         break;
 169         case 1:
 170             if( value & Rc1HSyncClock )
 171             {
 172                 rcnts[index].rate = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType]));
 173             }
 174             else
 175             {
 176                 rcnts[index].rate = 1;
 177             }
 178         break;
 179         case 2:
 180             if( value & Rc2OneEighthClock )
 181             {
 182                 rcnts[index].rate = 8;
 183             }
 184             else
 185             {
 186                 rcnts[index].rate = 1;
 187             }
 188
 189             // TODO: wcount must work.
 190             if( value & Rc2Disable )
 191             {
 192                 rcnts[index].rate = 0xffffffff;
 193             }
 194         break;
 195     }
 196 }
 197
 198 /******************************************************************************/
 199
 200 static
 201 void psxRcntSet()
 202 {
 203     s32 countToUpdate;
 204     u32 i;
 205
 206     psxNextsCounter = psxRegs.cycle;
 207     psxNextCounter  = 0x7fffffff;
 208
 209     for( i = 0; i < CounterQuantity; ++i )
 210     {
 211         countToUpdate = rcnts[i].cycle - (psxNextsCounter - rcnts[i].cycleStart);
 212
 213         if( countToUpdate < 0 )
 214         {
 215             psxNextCounter = 0;
 216             break;
 217         }
 218
 219         if( countToUpdate < (s32)psxNextCounter )
 220         {
 221             psxNextCounter = countToUpdate;
 222         }
 223     }
 224
 225     psxRegs.interrupt |= (1 << PSXINT_RCNT);
 226     new_dyna_set_event(PSXINT_RCNT, psxNextCounter);
 227 }
 228
 229 /******************************************************************************/
 230
 231 static
 232 void psxRcntReset( u32 index )
 233 {
 234     u32 rcycles;
 235
 236     rcnts[index].mode |= RcUnknown10;
 237
 238     if( rcnts[index].counterState == CountToTarget )
 239     {
 240         rcycles = psxRegs.cycle - rcnts[index].cycleStart;
 241         if( rcnts[index].mode & RcCountToTarget )
 242         {
 243             rcycles -= rcnts[index].target * rcnts[index].rate;
 244             rcnts[index].cycleStart = psxRegs.cycle - rcycles;
 245         }
 246         else
 247         {
 248             rcnts[index].cycle = 0x10000 * rcnts[index].rate;
 249             rcnts[index].counterState = CountToOverflow;
 250         }
 251
 252         if( rcnts[index].mode & RcIrqOnTarget )
 253         {
 254             if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) )
 255             {
 256                 verboseLog( 3, "[RCNT %i] irq\n", index );
 257                 setIrq( rcnts[index].irq );
 258                 rcnts[index].irqState = 1;
 259             }
 260         }
 261
 262         rcnts[index].mode |= RcCountEqTarget;
 263
 264         if( rcycles < 0x10000 * rcnts[index].rate )
 265             return;
 266     }
 267
 268     if( rcnts[index].counterState == CountToOverflow )
 269     {
 270         rcycles = psxRegs.cycle - rcnts[index].cycleStart;
 271         rcycles -= 0x10000 * rcnts[index].rate;
 272
 273         rcnts[index].cycleStart = psxRegs.cycle - rcycles;
 274
 275         if( rcycles < rcnts[index].target * rcnts[index].rate )
 276         {
 277             rcnts[index].cycle = rcnts[index].target * rcnts[index].rate;
 278             rcnts[index].counterState = CountToTarget;
 279         }
 280
 281         if( rcnts[index].mode & RcIrqOnOverflow )
 282         {
 283             if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) )
 284             {
 285                 verboseLog( 3, "[RCNT %i] irq\n", index );
 286                 setIrq( rcnts[index].irq );
 287                 rcnts[index].irqState = 1;
 288             }
 289         }
 290
 291         rcnts[index].mode |= RcOverflow;
 292     }
 293 }
 294
 295 static void scheduleRcntBase(void)
 296 {
 297     // Schedule next call, in hsyncs
 298     if (hSyncCount < VBlankStart)
 299         hsync_steps = VBlankStart - hSyncCount;
 300     else
 301         hsync_steps = HSyncTotal[Config.PsxType] - hSyncCount;
 302
 303     if (hSyncCount + hsync_steps == HSyncTotal[Config.PsxType])
 304     {
 305         rcnts[3].cycle = Config.PsxType ? PSXCLK / 50 : PSXCLK / 60;
 306     }
 307     else
 308     {
 309         // clk / 50 / 314 ~= 2157.25
 310         // clk / 60 / 263 ~= 2146.31
 311         u32 mult = Config.PsxType ? 8836089 : 8791293;
 312         rcnts[3].cycle = hsync_steps * mult >> 12;
 313     }
 314 }
 315
 316 void psxRcntUpdate()
 317 {
 318     u32 cycle;
 319
 320     cycle = psxRegs.cycle;
 321
 322     // rcnt 0.
 323     while( cycle - rcnts[0].cycleStart >= rcnts[0].cycle )
 324     {
 325         psxRcntReset( 0 );
 326     }
 327
 328     // rcnt 1.
 329     while( cycle - rcnts[1].cycleStart >= rcnts[1].cycle )
 330     {
 331         psxRcntReset( 1 );
 332     }
 333
 334     // rcnt 2.
 335     while( cycle - rcnts[2].cycleStart >= rcnts[2].cycle )
 336     {
 337         psxRcntReset( 2 );
 338     }
 339
 340     // rcnt base.
 341     if( cycle - rcnts[3].cycleStart >= rcnts[3].cycle )
 342     {
 343         hSyncCount += hsync_steps;
 344
 345         // VSync irq.
 346         if( hSyncCount == VBlankStart )
 347         {
 348             HW_GPU_STATUS &= SWAP32(~PSXGPU_LCF);
 349             GPU_vBlank( 1, 0 );
 350             setIrq( 0x01 );
 351
 352             EmuUpdate();
 353             GPU_updateLace();
 354
 355             if( SPU_async )
 356             {
 357                 SPU_async( cycle, 1 );
 358             }
 359         }
 360
 361         // Update lace.
 362         if( hSyncCount >= HSyncTotal[Config.PsxType] )
 363         {
 364             u32 status, field = 0;
 365             rcnts[3].cycleStart += Config.PsxType ? PSXCLK / 50 : PSXCLK / 60;
 366             hSyncCount = 0;
 367             frame_counter++;
 368
 369             gpuSyncPluginSR();
 370             status = SWAP32(HW_GPU_STATUS) | PSXGPU_FIELD;
 371             if ((status & PSXGPU_ILACE_BITS) == PSXGPU_ILACE_BITS) {
 372                 field = frame_counter & 1;
 373                 status |= field << 31;
 374                 status ^= field << 13;
 375             }
 376             HW_GPU_STATUS = SWAP32(status);
 377             GPU_vBlank(0, field);
 378         }
 379
 380         scheduleRcntBase();
 381     }
 382
 383     psxRcntSet();
 384
 385 #if 0 //ndef NDEBUG
 386     DebugVSync();
 387 #endif
 388 }
 389
 390 /******************************************************************************/
 391
 392 void psxRcntWcount( u32 index, u32 value )
 393 {
 394     verboseLog( 2, "[RCNT %i] wcount: %x\n", index, value );
 395
 396     _psxRcntWcount( index, value );
 397     psxRcntSet();
 398 }
 399
 400 void psxRcntWmode( u32 index, u32 value )
 401 {
 402     verboseLog( 1, "[RCNT %i] wmode: %x\n", index, value );
 403
 404     _psxRcntWmode( index, value );
 405     _psxRcntWcount( index, 0 );
 406
 407     rcnts[index].irqState = 0;
 408     psxRcntSet();
 409 }
 410
 411 void psxRcntWtarget( u32 index, u32 value )
 412 {
 413     verboseLog( 1, "[RCNT %i] wtarget: %x\n", index, value );
 414
 415     rcnts[index].target = value;
 416
 417     _psxRcntWcount( index, _psxRcntRcount( index ) );
 418     psxRcntSet();
 419 }
 420
 421 /******************************************************************************/
 422
 423 u32 psxRcntRcount( u32 index )
 424 {
 425     u32 count;
 426
 427     count = _psxRcntRcount( index );
 428
 429     verboseLog( 2, "[RCNT %i] rcount: %x\n", index, count );
 430
 431     return count;
 432 }
 433
 434 u32 psxRcntRmode( u32 index )
 435 {
 436     u16 mode;
 437
 438     mode = rcnts[index].mode;
 439     rcnts[index].mode &= 0xe7ff;
 440
 441     verboseLog( 2, "[RCNT %i] rmode: %x\n", index, mode );
 442
 443     return mode;
 444 }
 445
 446 u32 psxRcntRtarget( u32 index )
 447 {
 448     verboseLog( 2, "[RCNT %i] rtarget: %x\n", index, rcnts[index].target );
 449
 450     return rcnts[index].target;
 451 }
 452
 453 /******************************************************************************/
 454
 455 void psxRcntInit()
 456 {
 457     s32 i;
 458
 459     // rcnt 0.
 460     rcnts[0].rate   = 1;
 461     rcnts[0].irq    = 0x10;
 462
 463     // rcnt 1.
 464     rcnts[1].rate   = 1;
 465     rcnts[1].irq    = 0x20;
 466
 467     // rcnt 2.
 468     rcnts[2].rate   = 1;
 469     rcnts[2].irq    = 0x40;
 470
 471     // rcnt base.
 472     rcnts[3].rate   = 1;
 473     rcnts[3].mode   = RcCountToTarget;
 474     rcnts[3].target = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType]));
 475
 476     for( i = 0; i < CounterQuantity; ++i )
 477     {
 478         _psxRcntWcount( i, 0 );
 479     }
 480
 481     hSyncCount = 0;
 482     hsync_steps = 1;
 483
 484     psxRcntSet();
 485 }
 486
 487 /******************************************************************************/
 488
 489 s32 psxRcntFreeze( void *f, s32 Mode )
 490 {
 491     u32 spuSyncCount = 0;
 492     u32 count;
 493     s32 i;
 494
 495     gzfreeze( &rcnts, sizeof(Rcnt) * CounterQuantity );
 496     gzfreeze( &hSyncCount, sizeof(hSyncCount) );
 497     gzfreeze( &spuSyncCount, sizeof(spuSyncCount) );
 498     gzfreeze( &psxNextCounter, sizeof(psxNextCounter) );
 499     gzfreeze( &psxNextsCounter, sizeof(psxNextsCounter) );
 500
 501     if (Mode == 0)
 502     {
 503         // don't trust things from a savestate
 504         rcnts[3].rate = 1;
 505         for( i = 0; i < CounterQuantity; ++i )
 506         {
 507             _psxRcntWmode( i, rcnts[i].mode );
 508             count = (psxRegs.cycle - rcnts[i].cycleStart) / rcnts[i].rate;
 509             _psxRcntWcount( i, count );
 510         }
 511         scheduleRcntBase();
 512         psxRcntSet();
 513     }
 514
 515     return 0;
 516 }
 517
 518 /******************************************************************************/
 519 // vim:ts=4:shiftwidth=4:expandtab