6003a768 |
1 | \r |
619b1824 |
2 | // This file is part of the Cyclone 68000 Emulator\r |
3 | \r |
4 | // This code is licensed under the GNU General Public License version 2.0 and the MAME License.\r |
5 | // You can choose the license that has the most advantages for you.\r |
6 | \r |
7 | // SVN repository can be found at http://code.google.com/p/cyclone68000/\r |
8 | \r |
6003a768 |
9 | #include "app.h"\r |
10 | \r |
11 | // ---------------------------------------------------------------------------\r |
12 | // Gets the offset of a register for an ea, and puts it in 'r'\r |
13 | // Shifted left by 'shift'\r |
14 | // Doesn't trash anything\r |
15 | static int EaCalcReg(int r,int ea,int mask,int forceor,int shift)\r |
16 | {\r |
17 | int i=0,low=0,needor=0;\r |
18 | int lsl=0;\r |
19 | \r |
20 | for (i=mask|0x8000; (i&1)==0; i>>=1) low++; // Find out how high up the EA mask is\r |
21 | mask&=0xf<<low; // This is the max we can do\r |
22 | \r |
23 | if (ea>=8) needor=1; // Need to OR to access A0-7\r |
24 | \r |
25 | if ((mask>>low)&8) if (ea&8) needor=0; // Ah - no we don't actually need to or, since the bit is high in r8\r |
26 | \r |
27 | if (forceor) needor=1; // Special case for 0x30-0x38 EAs ;)\r |
28 | \r |
29 | ot(" and r%d,r8,#0x%.4x\n",r,mask);\r |
30 | \r |
31 | // Find out amount to shift left:\r |
32 | lsl=shift-low;\r |
33 | \r |
34 | if (lsl)\r |
35 | {\r |
36 | ot(" mov r%d,r%d,",r,r);\r |
37 | if (lsl>0) ot("lsl #%d\n", lsl);\r |
38 | else ot("lsr #%d\n",-lsl);\r |
39 | }\r |
40 | \r |
41 | if (needor) ot(" orr r%d,r%d,#0x%x ;@ A0-7\n",r,r,8<<shift);\r |
42 | return 0;\r |
43 | }\r |
44 | \r |
45 | // EaCalc - ARM Register 'a' = Effective Address\r |
46 | // Trashes r0,r2 and r3\r |
47 | int EaCalc(int a,int mask,int ea,int size)\r |
48 | {\r |
49 | char text[32]="";\r |
50 | int func=0;\r |
51 | \r |
52 | DisaPc=2; DisaGetEa(text,ea,size); // Get text version of the effective address\r |
53 | func=0x68+(size<<2); // Get correct read handler\r |
54 | \r |
55 | if (ea<0x10)\r |
56 | {\r |
57 | int lsl=2;\r |
58 | if (size>=2) lsl=0; // Saves one opcode\r |
59 | \r |
60 | ot(";@ EaCalc : Get register index into r%d:\n",a);\r |
61 | \r |
62 | EaCalcReg(a,ea,mask,0,lsl);\r |
63 | return 0;\r |
64 | }\r |
65 | \r |
66 | ot(";@ EaCalc : Get '%s' into r%d:\n",text,a);\r |
67 | // (An), (An)+, -(An):\r |
68 | if (ea<0x28)\r |
69 | {\r |
70 | int step=1<<size;\r |
71 | \r |
72 | if ((ea&7)==7 && step<2) step=2; // move.b (a7)+ or -(a7) steps by 2 not 1\r |
73 | \r |
74 | EaCalcReg(2,ea,mask,0,2);\r |
75 | ot(" ldr r%d,[r7,r2]\n",a);\r |
76 | \r |
77 | if ((ea&0x38)==0x18)\r |
78 | {\r |
79 | ot(" add r3,r%d,#%d ;@ Post-increment An\n",a,step);\r |
80 | ot(" str r3,[r7,r2]\n");\r |
81 | }\r |
82 | \r |
83 | if ((ea&0x38)==0x20)\r |
84 | {\r |
85 | ot(" sub r%d,r%d,#%d ;@ Pre-decrement An\n",a,a,step);\r |
86 | ot(" str r%d,[r7,r2]\n",a);\r |
87 | }\r |
88 | \r |
89 | if ((ea&0x38)==0x20) Cycles+=size<2 ? 6:10; // -(An) Extra cycles\r |
90 | else Cycles+=size<2 ? 4:8; // (An),(An)+ Extra cycles\r |
91 | return 0;\r |
92 | }\r |
93 | \r |
94 | if (ea<0x30) // ($nn,An)\r |
95 | {\r |
96 | EaCalcReg(2,8,mask,0,2);\r |
97 | ot(" ldr r2,[r7,r2]\n");\r |
98 | ot(" ldrsh r0,[r4],#2 ;@ Fetch offset\n");\r |
99 | ot(" add r%d,r0,r2 ;@ Add on offset\n",a);\r |
100 | Cycles+=size<2 ? 8:12; // Extra cycles\r |
101 | return 0;\r |
102 | }\r |
103 | \r |
104 | if (ea<0x38) // ($nn,An,Rn)\r |
105 | {\r |
106 | ot(";@ Get extension word into r3:\n");\r |
107 | ot(" ldrh r3,[r4],#2 ;@ ($Disp,PC,Rn)\n");\r |
108 | ot(" mov r2,r3,lsr #10\n");\r |
109 | ot(" tst r3,#0x0800 ;@ Is Rn Word or Long\n");\r |
110 | ot(" and r2,r2,#0x3c ;@ r2=Index of Rn\n");\r |
111 | ot(" mov r0,r3,asl #24 ;@ r0=Get 8-bit signed Disp\n");\r |
112 | ot(" ldreqsh r2,[r7,r2] ;@ r2=Rn.w\n");\r |
113 | ot(" ldrne r2,[r7,r2] ;@ r2=Rn.l\n");\r |
114 | ot(" add r3,r2,r0,asr #24 ;@ r3=Disp+Rn\n");\r |
115 | \r |
116 | EaCalcReg(2,8,mask,1,2);\r |
117 | ot(" ldr r2,[r7,r2]\n");\r |
118 | ot(" add r%d,r2,r3 ;@ r%d=Disp+An+Rn\n",a,a);\r |
119 | Cycles+=size<2 ? 10:14; // Extra cycles\r |
120 | return 0;\r |
121 | }\r |
122 | \r |
123 | if (ea==0x38)\r |
124 | {\r |
125 | ot(" ldrsh r%d,[r4],#2 ;@ Fetch Absolute Short address\n",a);\r |
126 | Cycles+=size<2 ? 8:12; // Extra cycles\r |
127 | return 0;\r |
128 | }\r |
129 | \r |
130 | if (ea==0x39)\r |
131 | {\r |
132 | ot(" ldrh r2,[r4],#2 ;@ Fetch Absolute Long address\n");\r |
133 | ot(" ldrh r0,[r4],#2\n");\r |
134 | ot(" orr r%d,r0,r2,lsl #16\n",a);\r |
135 | Cycles+=size<2 ? 12:16; // Extra cycles\r |
136 | return 0;\r |
137 | }\r |
138 | \r |
139 | if (ea==0x3a)\r |
140 | {\r |
141 | ot(" ldr r0,[r7,#0x60] ;@ Get Memory base\n");\r |
142 | ot(" sub r0,r4,r0 ;@ Real PC\n");\r |
143 | ot(" ldrsh r2,[r4],#2 ;@ Fetch extension\n");\r |
144 | ot(" add r%d,r0,r2 ;@ ($nn,PC)\n",a);\r |
145 | Cycles+=size<2 ? 8:12; // Extra cycles\r |
146 | return 0;\r |
147 | }\r |
148 | \r |
149 | if (ea==0x3b) // ($nn,pc,Rn)\r |
150 | {\r |
151 | ot(";@ Get extension word into r3:\n");\r |
152 | ot(" ldrh r3,[r4]\n");\r |
153 | ot(" mov r2,r3,lsr #10\n");\r |
154 | ot(" tst r3,#0x0800 ;@ Is Rn Word or Long\n");\r |
155 | ot(" and r2,r2,#0x3c ;@ r2=Index of Rn\n");\r |
156 | ot(" mov r0,r3,asl #24 ;@ r0=Get 8-bit signed Disp\n");\r |
157 | ot(" ldreqsh r2,[r7,r2] ;@ r2=Rn.w\n");\r |
158 | ot(" ldrne r2,[r7,r2] ;@ r2=Rn.l\n");\r |
159 | ot(" add r2,r2,r0,asr #24 ;@ r2=Disp+Rn\n");\r |
160 | ot(" ldr r0,[r7,#0x60] ;@ Get Memory base\n");\r |
161 | ot(" add r2,r2,r4 ;@ r2=Disp+Rn + Base+PC\n");\r |
162 | ot(" add r4,r4,#2 ;@ Increase PC\n");\r |
163 | ot(" sub r%d,r2,r0 ;@ r%d=Disp+PC+Rn\n",a,a);\r |
164 | Cycles+=size<2 ? 10:14; // Extra cycles\r |
165 | return 0;\r |
166 | }\r |
167 | \r |
168 | if (ea==0x3c)\r |
169 | {\r |
170 | if (size<2)\r |
171 | {\r |
172 | ot(" ldr%s r%d,[r4],#2 ;@ Fetch immediate value\n",Sarm[size&3],a);\r |
173 | Cycles+=4; // Extra cycles\r |
174 | return 0;\r |
175 | }\r |
176 | \r |
177 | ot(" ldrh r2,[r4],#2 ;@ Fetch immediate value\n");\r |
178 | ot(" ldrh r0,[r4],#2\n");\r |
179 | ot(" orr r%d,r0,r2,lsl #16\n",a);\r |
180 | Cycles+=8; // Extra cycles\r |
181 | return 0;\r |
182 | }\r |
183 | \r |
184 | return 1;\r |
185 | }\r |
186 | \r |
187 | // ---------------------------------------------------------------------------\r |
188 | // Read effective address in (ARM Register 'a') to ARM register 'v'\r |
189 | // 'a' and 'v' can be anything but 0 is generally best (for both)\r |
190 | // If (ea<0x10) nothing is trashed, else r0-r3 is trashed\r |
191 | // If 'top' is 1, the ARM register v shifted to the top, e.g. 0xc000 -> 0xc0000000\r |
192 | // Otherwise the ARM register v is sign extended, e.g. 0xc000 -> 0xffffc000\r |
193 | \r |
194 | int EaRead(int a,int v,int ea,int size,int top)\r |
195 | {\r |
196 | char text[32]="";\r |
197 | int shift=0;\r |
198 | \r |
199 | shift=32-(8<<size);\r |
200 | \r |
201 | DisaPc=2; DisaGetEa(text,ea,size); // Get text version of the effective address\r |
202 | \r |
203 | if (ea<0x10)\r |
204 | {\r |
205 | int lsl=2;\r |
206 | if (size>=2) lsl=0; // Having a lsl #2 here saves one opcode\r |
207 | \r |
208 | ot(";@ EaRead : Read register[r%d] into r%d:\n",a,v);\r |
209 | \r |
210 | if (lsl==0) ot(" ldr r%d,[r7,r%d,lsl #2]\n",v,a);\r |
211 | else ot(" ldr%s r%d,[r7,r%d]\n",Sarm[size&3],v,a);\r |
212 | \r |
213 | if (top && shift) ot(" mov r%d,r%d,asl #%d\n",v,v,shift);\r |
214 | \r |
215 | ot("\n"); return 0;\r |
216 | }\r |
217 | \r |
218 | ot(";@ EaRead : Read '%s' (address in r%d) into r%d:\n",text,a,v);\r |
219 | \r |
220 | if (ea==0x3c)\r |
221 | {\r |
222 | int asl=0;\r |
223 | \r |
224 | if (top) asl=shift;\r |
225 | \r |
226 | if (v!=a || asl) ot(" mov r%d,r%d,asl #%d\n",v,a,asl);\r |
227 | ot("\n"); return 0;\r |
228 | }\r |
229 | \r |
230 | if (a!=0) ot(" mov r0,r%d\n",a);\r |
231 | \r |
232 | if (ea>=0x3a && ea<=0x3b) MemHandler(2,size); // Fetch\r |
233 | else MemHandler(0,size); // Read\r |
234 | \r |
235 | if (v!=0 || shift) ot(" mov r%d,r0,asl #%d\n",v,shift);\r |
236 | if (top==0 && shift) ot(" mov r%d,r%d,asr #%d\n",v,v,shift);\r |
237 | \r |
238 | ot("\n"); return 0;\r |
239 | }\r |
240 | \r |
241 | // Return 1 if we can read this ea\r |
242 | int EaCanRead(int ea,int size)\r |
243 | {\r |
244 | if (size<0)\r |
245 | {\r |
246 | // LEA:\r |
247 | // These don't make sense?:\r |
248 | if (ea<0x10) return 0; // Register\r |
249 | if (ea==0x3c) return 0; // Immediate\r |
250 | if (ea>=0x18 && ea<0x28) return 0; // Pre/Post inc/dec An\r |
251 | }\r |
252 | \r |
253 | if (ea<=0x3c) return 1;\r |
254 | return 0;\r |
255 | }\r |
256 | \r |
257 | // ---------------------------------------------------------------------------\r |
258 | // Write effective address (ARM Register 'a') with ARM register 'v'\r |
259 | // Trashes r0-r3, 'a' can be 0 or 2+, 'v' can be 1 or higher\r |
260 | // If a==0 and v==1 it's faster though.\r |
261 | int EaWrite(int a,int v,int ea,int size,int top)\r |
262 | {\r |
263 | char text[32]="";\r |
264 | int shift=0;\r |
265 | \r |
266 | if (top) shift=32-(8<<size);\r |
267 | \r |
268 | DisaPc=2; DisaGetEa(text,ea,size); // Get text version of the effective address\r |
269 | \r |
270 | if (ea<0x10)\r |
271 | {\r |
272 | int lsl=2;\r |
273 | if (size>=2) lsl=0; // Having a lsl #2 here saves one opcode\r |
274 | \r |
275 | ot(";@ EaWrite: r%d into register[r%d]:\n",v,a);\r |
276 | if (shift) ot(" mov r%d,r%d,asr #%d\n",v,v,shift);\r |
277 | \r |
278 | if (lsl==0) ot(" str r%d,[r7,r%d,lsl #2]\n",v,a);\r |
279 | else ot(" str%s r%d,[r7,r%d]\n",Narm[size&3],v,a);\r |
280 | \r |
281 | ot("\n"); return 0;\r |
282 | }\r |
283 | \r |
284 | ot(";@ EaWrite: Write r%d into '%s' (address in r%d):\n",v,text,a);\r |
285 | \r |
286 | if (ea==0x3c) { ot("Error! Write EA=0x%x\n\n",ea); return 1; }\r |
287 | \r |
288 | if (a!=0 && v!=0) ot(" mov r0,r%d\n",a);\r |
289 | if (v!=1 || shift) ot(" mov r1,r%d,asr #%d\n",v,shift);\r |
290 | if (a!=0 && v==0) ot(" mov r0,r%d\n",a);\r |
291 | \r |
292 | MemHandler(1,size); // Call write handler\r |
293 | \r |
294 | ot("\n"); return 0;\r |
295 | }\r |
296 | \r |
297 | // Return 1 if we can write this ea\r |
298 | int EaCanWrite(int ea)\r |
299 | {\r |
300 | if (ea<=0x3b) return 1;\r |
301 | return 0;\r |
302 | }\r |
303 | // ---------------------------------------------------------------------------\r |