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1 | \r |
2 | // Cyclone 68000 Emulator - Header File\r |
3 | \r |
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4 | // Copyright (c) 2004,2011 FinalDave (emudave (at) gmail.com)\r |
5 | // Copyright (c) 2005-2011 GraÅžvydas "notaz" Ignotas (notasas (at) gmail.com)\r |
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6 | \r |
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7 | // This code is licensed under the GNU General Public License version 2.0 and the MAME License.\r |
8 | // You can choose the license that has the most advantages for you.\r |
9 | \r |
10 | // SVN repository can be found at http://code.google.com/p/cyclone68000/\r |
11 | \r |
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12 | \r |
13 | #ifndef __CYCLONE_H__\r |
14 | #define __CYCLONE_H__\r |
15 | \r |
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16 | #ifdef __cplusplus\r |
17 | extern "C" {\r |
18 | #endif\r |
19 | \r |
20 | extern int CycloneVer; // Version number of library\r |
21 | \r |
22 | struct Cyclone\r |
23 | {\r |
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24 | unsigned int d[8]; // [r7,#0x00]\r |
25 | unsigned int a[8]; // [r7,#0x20]\r |
26 | unsigned int pc; // [r7,#0x40] Memory Base (.membase) + 68k PC\r |
27 | unsigned char srh; // [r7,#0x44] Status Register high (T_S__III)\r |
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28 | unsigned char not_pol;// [r7,#0x45] not polling\r |
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29 | unsigned char flags; // [r7,#0x46] Flags (ARM order: ____NZCV) [68k order is XNZVC]\r |
30 | unsigned char irq; // [r7,#0x47] IRQ level\r |
31 | unsigned int osp; // [r7,#0x48] Other Stack Pointer (USP/SSP)\r |
32 | unsigned int xc; // [r7,#0x4c] Extend flag (bit29: ??X? _)\r |
33 | unsigned int prev_pc; // [r7,#0x50] Set to start address of currently executed opcode + 2 (if enabled in config.h)\r |
34 | unsigned int jumptab; // [r7,#0x54] Jump table pointer\r |
35 | int state_flags; // [r7,#0x58] bit: 0: stopped state, 1: trace state, 2: activity bit, 3: addr error, 4: fatal halt\r |
36 | int cycles; // [r7,#0x5c] Number of cycles to execute - 1. Updates to cycles left after CycloneRun()\r |
37 | int membase; // [r7,#0x60] Memory Base (ARM address minus 68000 address)\r |
38 | unsigned int (*checkpc)(unsigned int pc); // [r7,#0x64] called to recalc Memory Base+pc\r |
39 | unsigned int (*read8 )(unsigned int a); // [r7,#0x68]\r |
40 | unsigned int (*read16 )(unsigned int a); // [r7,#0x6c]\r |
41 | unsigned int (*read32 )(unsigned int a); // [r7,#0x70]\r |
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42 | void (*write8 )(unsigned int a,unsigned char d); // [r7,#0x74]\r |
43 | void (*write16)(unsigned int a,unsigned short d); // [r7,#0x78]\r |
44 | void (*write32)(unsigned int a,unsigned int d); // [r7,#0x7c]\r |
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45 | unsigned int (*fetch8 )(unsigned int a); // [r7,#0x80]\r |
46 | unsigned int (*fetch16)(unsigned int a); // [r7,#0x84]\r |
47 | unsigned int (*fetch32)(unsigned int a); // [r7,#0x88]\r |
48 | int (*IrqCallback)(int int_level); // [r7,#0x8c] optional irq callback function, see config.h\r |
49 | void (*ResetCallback)(void); // [r7,#0x90] if enabled in config.h, calls this whenever RESET opcode is encountered.\r |
50 | int (*UnrecognizedCallback)(void); // [r7,#0x94] if enabled in config.h, calls this whenever unrecognized opcode is encountered.\r |
51 | unsigned int internal[6]; // [r7,#0x98] reserved for internal use, do not change.\r |
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52 | };\r |
53 | \r |
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54 | // Initialize. Used only if Cyclone was compiled with compressed jumptable, see config.h\r |
55 | void CycloneInit(void);\r |
56 | \r |
57 | // Reset\r |
58 | void CycloneReset(struct Cyclone *pcy);\r |
59 | \r |
60 | // Run cyclone. Cycles should be specified in context (pcy->cycles)\r |
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61 | void CycloneRun(struct Cyclone *pcy);\r |
62 | \r |
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63 | // Utility functions to get and set SR\r |
64 | void CycloneSetSr(struct Cyclone *pcy, unsigned int sr);\r |
65 | unsigned int CycloneGetSr(const struct Cyclone *pcy);\r |
66 | \r |
67 | // Generates irq exception if needed (if pcy->irq > mask).\r |
68 | // Returns cycles used for exception if it was generated, 0 otherwise.\r |
69 | int CycloneFlushIrq(struct Cyclone *pcy);\r |
70 | \r |
71 | // Functions for saving and restoring state.\r |
72 | // CycloneUnpack() uses checkpc(), so it must be initialized.\r |
73 | // save_buffer must point to buffer of 128 (0x80) bytes of size.\r |
74 | void CyclonePack(const struct Cyclone *pcy, void *save_buffer);\r |
75 | void CycloneUnpack(struct Cyclone *pcy, const void *save_buffer);\r |
76 | \r |
77 | // genesis: if 1, switch to normal TAS handlers\r |
78 | void CycloneSetRealTAS(int use_real);\r |
79 | \r |
80 | \r |
81 | // These values are special return values for IrqCallback.\r |
82 | \r |
83 | // Causes an interrupt autovector (0x18 + interrupt level) to be taken.\r |
84 | // This happens in a real 68K if VPA or AVEC is asserted during an interrupt\r |
85 | // acknowledge cycle instead of DTACK (the most common situation).\r |
86 | #define CYCLONE_INT_ACK_AUTOVECTOR -1\r |
87 | \r |
88 | // Causes the spurious interrupt vector (0x18) to be taken\r |
89 | // This happens in a real 68K if BERR is asserted during the interrupt\r |
90 | // acknowledge cycle (i.e. no devices responded to the acknowledge).\r |
91 | #define CYCLONE_INT_ACK_SPURIOUS -2\r |
92 | \r |
93 | \r |
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94 | #ifdef __cplusplus\r |
95 | } // End of extern "C"\r |
96 | #endif\r |
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97 | \r |
98 | #endif // __CYCLONE_H__\r |
99 | \r |