c62d2810 |
1 | MMC5 Bankswitching |
2 | by Kevin Horton |
3 | -------------------- |
4 | |
5 | 5100: Controls paging of RAM and ROM |
6 | |
7 | Bits: ???? ??xx |
8 | |
9 | For xx: |
10 | |
11 | 00: 32K bankswitching. Only 5117 can be used to control banks. 5114 thru |
12 | 5116 have no effect. |
13 | |
14 | |
15 | 01: 16K bankswitching. Only 5115 and 5117 can be used to control banks. |
16 | 5114 and 5116 have no effect. |
17 | |
18 | |
19 | 10: 8K/16K bankswitching. 5115-5117 are used. 5114 has no effect. |
20 | |
21 | 11: 8K bankswitching. 5114-5117 are used. |
22 | |
23 | (See below for detailed description) |
24 | |
25 | -- |
26 | |
27 | 5113: RAM page 6000-7FFF bank. Lower 3 bits are used, for a possible |
28 | 64K of WRAM. (Note more bits *may* be possible for more RAM. |
29 | This has not been confirmed yet). |
30 | |
31 | Bits: ???? ?xxx |
32 | |
33 | WRAM follows a certain convention, based on the style of MMC5 board used. |
34 | 8K and 32K carts are usually implemented with a single chip, while 16K |
35 | carts use two 8K'ers. This is important since enabling changes, and hence |
36 | valid banks. |
37 | |
38 | for xxx: |
39 | |
40 | 8K 16K 32K 40K 64K |
41 | |
42 | 0: bank 0 bank 0 bank 0 bank 0 bank 0 |
43 | 1: bank 0 bank 0 bank 1 bank 1 bank 1 |
44 | 2: bank 0 bank 0 bank 2 bank 2 bank 2 |
45 | 3: bank 0 bank 0 bank 3 bank 3 bank 3 |
46 | 4: open bus bank 1 open bus bank 4 bank 4 |
47 | 5: open bus bank 1 open bus bank 4 bank 5 |
48 | 6: open bus bank 1 open bus bank 4 bank 6 |
49 | 7: open bus bank 1 open bus bank 4 bank 7 |
50 | |
51 | Note that the 40K and 64K examples are hypothetical. The first three, |
52 | however *are* real and is what you find inside a real MMC5 cart. |
53 | |
54 | Also note, that 5114-5116 follow this identical convention, if set up |
55 | to switch in RAM banks. |
56 | |
57 | -- |
58 | |
59 | Bankswitching is a bit complicated. This table should make things clearer. |
60 | The numbers at the top are what you write to 5100 to select mode. |
61 | |
62 | Legend: |
63 | |
64 | - = this has no effect |
65 | --- = this register is not used, and writes to it are ignored |
66 | R = PRG ROM/WRAM select. 0=WRAM, 1=PRG ROM |
67 | b = bank bits |
68 | |
69 | |
70 | |
71 | 5100: 00 01 10 11 |
72 | |
73 | 5114 --- --- --- Rbbb bbbb |
74 | 5115 --- Rbbb bbb- Rbbb bbb- Rbbb bbbb |
75 | 5116 --- --- Rbbb bbbb Rbbb bbbb |
76 | 5117 -bbb bb-- -bbb bbb- -bbb bbbb -bbb bbbb |
77 | |
78 | |
79 | Mode 00 |
80 | ------- |
81 | |
82 | Only one 32K page can be selected. The lower 2 bits of the desired bank |
83 | are ANDed out. writing 084h, 085h, 086h, and 087h to 5117 in this mode |
84 | all result in selection of the same 32K. No RAM is available in this mode. |
85 | |
86 | Mode 01 |
87 | ------- |
88 | |
89 | There are two selectable 16K pages. Similar to above, the lowest bit written |
90 | is not used to select banks. In this mode, writing to 5115 selects 16K |
91 | at 8000-BFFF, and 5117 selects 16K at C000-FFFF. RAM can be enabled in this |
92 | mode for 8000-BFFF. If RAM is enabled for 8000-BFFF, remember that the |
93 | lowest bank select bit is not used. |
94 | |
95 | Mode 10 |
96 | ------- |
97 | |
98 | This is the oddest one. There is one 16K selectable page, and two 8K |
99 | selectable pages. 5115 selects the 16K page at 8000-BFFF, 5116 selects |
100 | an 8K page at C000-DFFF, and 5117 selects an 8K page at E000-FFFF. |
101 | RAM can be enabled for 8000-DFFF. (16K of RAM at 8000-BFFF via bit 7 of |
102 | D115, and 8K of RAM at C000-DFFF via bit 7 of d116). Note that RAM banking |
103 | works the same as mode 01, above for the 16K bank. |
104 | |
105 | |
106 | Mode 11 |
107 | ------- |
108 | |
109 | There are 4 8K selectable pages. 5114 controls 8000-9FFF, etc. all the way |
110 | up to 5117 that controls E000-FFFF. The first 3 pages can use RAM, while |
111 | the last page cannot. |
112 | |
113 | |
114 | -- |
115 | |
116 | WRAM write enable. |
117 | |
118 | 5102, 5103 |
119 | |
120 | To enable writing to RAM, 5102 must have 02h written to it, and 5103 |
121 | must have 01h written to it. If this is not the case, you can still |
122 | *read* the RAM, but writes to it have no effect. Supposidly only the |
123 | lower two bits of 5102 and 5103 are checked, but I didn't verify this. |
124 | I *did* however verify that setting the two registers to the above |
125 | values allows writing. If voltage goes out of tolerance (Read: you |
126 | turn the power on/off) the RAM writing is disabled. (To prevent |
127 | corruption of saved-games during power cycling) |
128 | |