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1 | \r |
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2 | // This file is part of the Cyclone 68000 Emulator\r |
3 | \r |
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4 | // Copyright (c) 2004,2011 FinalDave (emudave (at) gmail.com)\r |
5 | // Copyright (c) 2005-2011 GraÅžvydas "notaz" Ignotas (notasas (at) gmail.com)\r |
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6 | \r |
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7 | // This code is licensed under the GNU General Public License version 2.0 and the MAME License.\r |
8 | // You can choose the license that has the most advantages for you.\r |
9 | \r |
10 | // SVN repository can be found at http://code.google.com/p/cyclone68000/\r |
11 | \r |
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12 | \r |
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13 | #include "app.h"\r |
14 | \r |
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15 | int opend_op_changes_cycles, opend_check_interrupt, opend_check_trace;\r |
16 | \r |
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17 | static unsigned char OpData[16]={0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};\r |
18 | \r |
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19 | static unsigned short OpRead16(unsigned int a)\r |
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20 | {\r |
21 | return (unsigned short)( (OpData[a&15]<<8) | OpData[(a+1)&15] );\r |
22 | }\r |
23 | \r |
24 | // For opcode 'op' use handler 'use'\r |
25 | void OpUse(int op,int use)\r |
26 | {\r |
27 | char text[64]="";\r |
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28 | CyJump[op]=use;\r |
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29 | \r |
30 | if (op!=use) return;\r |
31 | \r |
32 | // Disassemble opcode\r |
33 | DisaPc=0;\r |
34 | DisaText=text;\r |
35 | DisaWord=OpRead16;\r |
36 | \r |
37 | DisaGet();\r |
38 | ot(";@ ---------- [%.4x] %s uses Op%.4x ----------\n",op,text,use);\r |
39 | }\r |
40 | \r |
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41 | void OpStart(int op, int sea, int tea, int op_changes_cycles, int supervisor_check)\r |
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42 | {\r |
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43 | int last_op_count=arm_op_count;\r |
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44 | \r |
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45 | Cycles=0;\r |
46 | OpUse(op,op); // This opcode obviously uses this handler\r |
47 | ot("Op%.4x%s\n", op, ms?"":":");\r |
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48 | \r |
49 | if (supervisor_check)\r |
50 | {\r |
51 | // checks for supervisor bit, if not set, jumps to SuperEnd()\r |
52 | // also sets r11 to SR high value, SuperChange() uses this\r |
53 | ot(" ldr r11,[r7,#0x44] ;@ Get SR high\n");\r |
54 | }\r |
55 | if ((sea >= 0x10 && sea != 0x3c) || (tea >= 0x10 && tea != 0x3c))\r |
56 | {\r |
57 | #if MEMHANDLERS_NEED_PREV_PC\r |
58 | ot(" str r4,[r7,#0x50] ;@ Save prev PC + 2\n");\r |
59 | #endif\r |
60 | #if MEMHANDLERS_NEED_CYCLES\r |
61 | ot(" str r5,[r7,#0x5c] ;@ Save Cycles\n");\r |
62 | #endif\r |
63 | }\r |
64 | if (supervisor_check)\r |
65 | {\r |
66 | ot(" tst r11,#0x20 ;@ Check we are in supervisor mode\n");\r |
67 | ot(" beq WrongPrivilegeMode ;@ No\n");\r |
68 | }\r |
69 | if ((sea >= 0x10 && sea != 0x3c) || (tea >= 0x10 && tea != 0x3c)) {\r |
70 | #if MEMHANDLERS_CHANGE_CYCLES\r |
71 | if (op_changes_cycles)\r |
72 | ot(" mov r5,#0\n");\r |
73 | #endif\r |
74 | }\r |
75 | if (last_op_count!=arm_op_count)\r |
76 | ot("\n");\r |
77 | pc_dirty = 1;\r |
78 | opend_op_changes_cycles = opend_check_interrupt = opend_check_trace = 0;\r |
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79 | }\r |
80 | \r |
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81 | void OpEnd(int sea, int tea)\r |
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82 | {\r |
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83 | int did_fetch=0;\r |
84 | opend_check_trace = opend_check_trace && EMULATE_TRACE;\r |
85 | #if MEMHANDLERS_CHANGE_CYCLES\r |
86 | if ((sea >= 0x10 && sea != 0x3c) || (tea >= 0x10 && tea != 0x3c))\r |
87 | {\r |
88 | if (opend_op_changes_cycles)\r |
89 | {\r |
90 | ot(" ldr r0,[r7,#0x5c] ;@ Load Cycles\n");\r |
91 | ot(" ldrh r8,[r4],#2 ;@ Fetch next opcode\n");\r |
92 | ot(" add r5,r0,r5\n");\r |
93 | did_fetch=1;\r |
94 | }\r |
95 | else\r |
96 | {\r |
97 | ot(" ldr r5,[r7,#0x5c] ;@ Load Cycles\n");\r |
98 | }\r |
99 | }\r |
100 | #endif\r |
101 | if (!did_fetch)\r |
102 | ot(" ldrh r8,[r4],#2 ;@ Fetch next opcode\n");\r |
103 | if (opend_check_trace)\r |
104 | ot(" ldr r1,[r7,#0x44]\n");\r |
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105 | ot(" subs r5,r5,#%d ;@ Subtract cycles\n",Cycles);\r |
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106 | if (opend_check_trace)\r |
107 | {\r |
108 | ot(";@ CheckTrace:\n");\r |
109 | ot(" tst r1,#0x80\n");\r |
110 | ot(" bne CycloneDoTraceWithChecks\n");\r |
111 | ot(" cmp r5,#0\n");\r |
112 | }\r |
113 | if (opend_check_interrupt)\r |
114 | {\r |
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115 | ot(" ble CycloneEnd\n");\r |
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116 | ot(";@ CheckInterrupt:\n");\r |
117 | if (!opend_check_trace)\r |
118 | ot(" ldr r1,[r7,#0x44]\n");\r |
119 | ot(" movs r0,r1,lsr #24 ;@ Get IRQ level\n"); // same as ldrb r0,[r7,#0x47]\r |
120 | ot(" ldreq pc,[r6,r8,asl #2] ;@ Jump to next opcode handler\n");\r |
121 | ot(" cmp r0,#6 ;@ irq>6 ?\n");\r |
122 | ot(" andle r1,r1,#7 ;@ Get interrupt mask\n");\r |
123 | ot(" cmple r0,r1 ;@ irq<=6: Is irq<=mask ?\n");\r |
124 | ot(" ldrle pc,[r6,r8,asl #2] ;@ Jump to next opcode handler\n");\r |
125 | ot(" b CycloneDoInterruptGoBack\n");\r |
126 | }\r |
127 | else\r |
128 | {\r |
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129 | ot(" ldrgt pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");\r |
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130 | ot(" b CycloneEnd\n");\r |
131 | }\r |
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132 | ot("\n");\r |
133 | }\r |
134 | \r |
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135 | int OpBase(int op,int size,int sepa)\r |
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136 | {\r |
137 | int ea=op&0x3f; // Get Effective Address\r |
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138 | if (ea<0x10) return sepa?(op&~0x7):(op&~0xf); // Use 1 handler for d0-d7 and a0-a7\r |
139 | if (size==0&&(ea==0x1f || ea==0x27)) return op; // Specific handler for (a7)+ and -(a7)\r |
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140 | if (ea<0x38) return op&~7; // Use 1 handler for (a0)-(a7), etc...\r |
141 | return op;\r |
142 | }\r |
143 | \r |
144 | // Get flags, trashes r2\r |
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145 | int OpGetFlags(int subtract,int xbit,int specialz)\r |
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146 | {\r |
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147 | if (specialz) ot(" orr r2,r10,#0xb0000000 ;@ for old Z\n");\r |
148 | \r |
149 | ot(" mrs r10,cpsr ;@ r10=flags\n");\r |
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150 | \r |
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151 | if (specialz) ot(" andeq r10,r10,r2 ;@ fix Z\n");\r |
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152 | \r |
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153 | if (subtract) ot(" eor r10,r10,#0x20000000 ;@ Invert carry\n");\r |
154 | \r |
155 | if (xbit)\r |
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156 | {\r |
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157 | ot(" str r10,[r7,#0x4c] ;@ Save X bit\n");\r |
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158 | }\r |
159 | return 0;\r |
160 | }\r |
161 | \r |
162 | // -----------------------------------------------------------------\r |
163 | \r |
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164 | int g_op;\r |
165 | \r |
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166 | void OpAny(int op)\r |
167 | {\r |
168 | memset(OpData,0x33,sizeof(OpData));\r |
169 | OpData[0]=(unsigned char)(op>>8);\r |
170 | OpData[1]=(unsigned char)op;\r |
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171 | g_op=op;\r |
172 | \r |
173 | if ((op&0xf100)==0x0000) OpArith(op); // +\r |
174 | if ((op&0xc000)==0x0000) OpMove(op); // +\r |
175 | if ((op&0xf5bf)==0x003c) OpArithSr(op); // + Ori/Andi/Eori $nnnn,sr\r |
176 | if ((op&0xf100)==0x0100) OpBtstReg(op); // +\r |
177 | if ((op&0xf138)==0x0108) OpMovep(op); // +\r |
178 | if ((op&0xff00)==0x0800) OpBtstImm(op); // +\r |
179 | if ((op&0xf900)==0x4000) OpNeg(op); // +\r |
180 | if ((op&0xf140)==0x4100) OpChk(op); // +\r |
181 | if ((op&0xf1c0)==0x41c0) OpLea(op); // +\r |
182 | if ((op&0xf9c0)==0x40c0) OpMoveSr(op); // +\r |
183 | if ((op&0xffc0)==0x4800) OpNbcd(op); // +\r |
184 | if ((op&0xfff8)==0x4840) OpSwap(op); // +\r |
185 | if ((op&0xffc0)==0x4840) OpPea(op); // +\r |
186 | if ((op&0xffb8)==0x4880) OpExt(op); // +\r |
187 | if ((op&0xfb80)==0x4880) OpMovem(op); // +\r |
188 | if ((op&0xff00)==0x4a00) OpTst(op); // +\r |
189 | if ((op&0xffc0)==0x4ac0) OpTas(op); // +\r |
190 | if ((op&0xfff0)==0x4e40) OpTrap(op); // +\r |
191 | if ((op&0xfff8)==0x4e50) OpLink(op); // +\r |
192 | if ((op&0xfff8)==0x4e58) OpUnlk(op); // +\r |
193 | if ((op&0xfff0)==0x4e60) OpMoveUsp(op); // +\r |
194 | if ((op&0xfff8)==0x4e70) Op4E70(op); // + Reset/Rts etc\r |
195 | if ((op&0xfffd)==0x4e70) OpStopReset(op);// +\r |
196 | if ((op&0xff80)==0x4e80) OpJsr(op); // +\r |
197 | if ((op&0xf000)==0x5000) OpAddq(op); // +\r |
198 | if ((op&0xf0c0)==0x50c0) OpSet(op); // +\r |
199 | if ((op&0xf0f8)==0x50c8) OpDbra(op); // +\r |
200 | if ((op&0xf000)==0x6000) OpBranch(op); // +\r |
201 | if ((op&0xf100)==0x7000) OpMoveq(op); // +\r |
202 | if ((op&0xa000)==0x8000) OpArithReg(op); // + Or/Sub/And/Add\r |
203 | if ((op&0xb1f0)==0x8100) OpAbcd(op); // +\r |
204 | if ((op&0xb0c0)==0x80c0) OpMul(op); // +\r |
205 | if ((op&0x90c0)==0x90c0) OpAritha(op); // +\r |
206 | if ((op&0xb130)==0x9100) OpAddx(op); // +\r |
207 | if ((op&0xf000)==0xb000) OpCmpEor(op); // +\r |
208 | if ((op&0xf138)==0xb108) OpCmpm(op); // +\r |
209 | if ((op&0xf130)==0xc100) OpExg(op); // +\r |
210 | if ((op&0xf000)==0xe000) OpAsr(op); // + Asr/l/Ror/l etc\r |
211 | if ((op&0xf8c0)==0xe0c0) OpAsrEa(op); // +\r |
212 | \r |
213 | if (op==0xffff)\r |
214 | {\r |
215 | SuperEnd();\r |
216 | }\r |
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217 | }\r |
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218 | \r |