15eb0001 |
1 | \r |
2 | #include "PicoInt.h"\r |
3 | \r |
4 | char PicoStatus[128]=""; // 68000 state for debug\r |
5 | \r |
6 | #ifdef EMU_C68K\r |
7 | // ---------------------- Cyclone 68000 ----------------------\r |
8 | \r |
9 | struct Cyclone PicoCpu;\r |
10 | \r |
11 | int SekInit()\r |
12 | {\r |
13 | memset(&PicoCpu,0,sizeof(PicoCpu));\r |
14 | return 0;\r |
15 | }\r |
16 | \r |
17 | // Reset the 68000:\r |
18 | int SekReset()\r |
19 | {\r |
20 | if (Pico.rom==NULL) return 1;\r |
21 | \r |
22 | PicoCpu.srh =0x27; // Supervisor mode\r |
23 | PicoCpu.a[7]=PicoCpu.read32(0); // Stack Pointer\r |
24 | PicoCpu.membase=0;\r |
25 | PicoCpu.pc=PicoCpu.checkpc(PicoCpu.read32(4)); // Program Counter\r |
26 | \r |
27 | return 0;\r |
28 | }\r |
29 | \r |
30 | \r |
31 | // Run the 68000 for 'cyc' number of cycles and return the number of cycles actually executed\r |
32 | static inline int DoRun(int cyc)\r |
33 | {\r |
34 | PicoCpu.cycles=cyc;\r |
35 | CycloneRun(&PicoCpu);\r |
36 | return cyc-PicoCpu.cycles;\r |
37 | }\r |
38 | \r |
39 | int SekInterrupt(int irq)\r |
40 | {\r |
41 | PicoCpu.irq=(unsigned char)irq;\r |
42 | return 0;\r |
43 | }\r |
44 | \r |
45 | int SekPc() { return PicoCpu.pc-PicoCpu.membase; }\r |
46 | \r |
47 | void SekState(unsigned char *data)\r |
48 | {\r |
49 | memcpy(data,PicoCpu.d,0x44);\r |
50 | }\r |
51 | \r |
52 | #endif\r |
53 | \r |
54 | #ifdef EMU_A68K\r |
55 | // ---------------------- A68K ----------------------\r |
56 | \r |
57 | extern "C" void __cdecl M68000_RUN();\r |
58 | extern "C" void __cdecl M68000_RESET();\r |
59 | extern "C" int m68k_ICount=0;\r |
60 | extern "C" unsigned int mem_amask=0xffffff; // 24-bit bus\r |
61 | extern "C" unsigned int mame_debug=0,cur_mrhard=0,m68k_illegal_opcode=0,illegal_op=0,illegal_pc=0,opcode_entry=0; // filler\r |
62 | \r |
63 | static int IrqCallback(int) { return -1; }\r |
64 | static int DoReset() { return 0; }\r |
65 | static int (*ResetCallback)()=DoReset;\r |
66 | \r |
67 | int SekInit()\r |
68 | {\r |
69 | memset(&M68000_regs,0,sizeof(M68000_regs));\r |
70 | M68000_regs.IrqCallback=IrqCallback;\r |
71 | M68000_regs.pResetCallback=ResetCallback;\r |
72 | M68000_RESET(); // Init cpu emulator\r |
73 | return 0;\r |
74 | }\r |
75 | \r |
76 | int SekReset()\r |
77 | {\r |
78 | // Reset CPU: fetch SP and PC\r |
79 | M68000_regs.srh=0x27; // Supervisor mode\r |
80 | M68000_regs.a[7]=PicoRead32(0);\r |
81 | M68000_regs.pc =PicoRead32(4);\r |
82 | PicoInitPc(M68000_regs.pc);\r |
83 | \r |
84 | return 0;\r |
85 | }\r |
86 | \r |
87 | static inline int DoRun(int cyc)\r |
88 | {\r |
89 | m68k_ICount=cyc;\r |
90 | M68000_RUN();\r |
91 | return cyc-m68k_ICount;\r |
92 | }\r |
93 | \r |
94 | int SekInterrupt(int irq)\r |
95 | {\r |
96 | M68000_regs.irq=irq; // raise irq (gets lowered after taken)\r |
97 | return 0;\r |
98 | }\r |
99 | \r |
100 | int SekPc() { return M68000_regs.pc; }\r |
101 | \r |
102 | void SekState(unsigned char *data)\r |
103 | {\r |
104 | memcpy(data, M68000_regs.d, 0x40);\r |
105 | memcpy(data+0x40,&M68000_regs.pc,0x04);\r |
106 | }\r |
107 | \r |
108 | #endif\r |
109 | \r |
110 | #ifdef EMU_NULL\r |
111 | // -----------------------------------------------------------\r |
112 | int SekInit() { return 0; }\r |
113 | int SekReset() { return 0; }\r |
114 | static inline int DoRun(int cyc) { return cyc; }\r |
115 | int SekInterrupt(int) { return 0; }\r |
116 | \r |
117 | int SekPc()\r |
118 | {\r |
119 | return 0;\r |
120 | }\r |
121 | \r |
122 | void SekState(unsigned char *) { }\r |
123 | \r |
124 | #endif\r |
125 | \r |
126 | int SekRun(int cyc)\r |
127 | {\r |
128 | int did=0;\r |
129 | \r |
130 | did=DoRun(cyc);\r |
131 | \r |
132 | return did;\r |
133 | }\r |