ips patches, 0.4 r162 rel?
[fceu.git] / drivers / gp2x / cpuctrl.h
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b2b95d2e 1#ifndef __CPUCTRL_H__
2#define __CPUCTRL_H__
3
4extern void cpuctrl_init(void); /* call this at first */
5extern void save_system_regs(void); /* save some registers */
6extern void cpuctrl_deinit(void);
7extern void set_display_clock_div(unsigned div);
8extern void set_FCLK(unsigned MHZ); /* adjust the clock frequency (in Mhz units) */
9extern void set_920_Div(unsigned short div); /* 0 to 7 divider (freq=FCLK/(1+div)) */
10extern void set_DCLK_Div(unsigned short div); /* 0 to 7 divider (freq=FCLK/(1+div)) */
11//extern void Disable_940(void); /* 940t down */
7b356ee3 12
b2b95d2e 13extern void set_RAM_Timings(int tRC, int tRAS, int tWR, int tMRD, int tRFC, int tRP, int tRCD);
14extern void set_gamma(int g100);
15
7b356ee3 16typedef enum
17{
18 LCDR_60 = 0, /* as close as possible to 60.00Hz, currently only managed to set to ~59.998Hz, has interlacing problems */
19 LCDR_50, /* 50Hz, has interlacing problems */
20 LCDR_120_20, /* ~60.10*2Hz, used by FCE Ultra */
21 LCDR_100_02, /* ~50.01*2Hz, used by FCE Ultra */
22} lcd_rate_t;
23
24extern void set_LCD_custom_rate(lcd_rate_t rate);
25extern void unset_LCD_custom_rate(void);
26
b2b95d2e 27#endif