e2d0dd92 |
1 | #include "mapinc.h" |
2 | |
3 | static uint32 regchr[9]; |
4 | |
5 | static DECLFW(Mapper27_write) |
6 | { |
7 | A&=0xF00F; |
8 | int regnum; |
9 | if((A>=0xB000) && (A<=0xE003)) { |
10 | regnum=((((A>>12)+1)&0x03)<<1)|((A&0x02)>>1); |
11 | if(A&1) |
12 | regchr[regnum]=(regchr[regnum]&0x0F)|(V<<4); |
13 | else |
14 | regchr[regnum]=(regchr[regnum]&0xFF0)|(V&0xF); |
15 | VROM_BANK1(regnum<<10,regchr[regnum]); |
16 | } |
17 | switch(A) |
18 | { |
19 | case 0x8000: if(regchr[8]&2) |
20 | ROM_BANK8(0xc000,V); |
21 | else |
22 | ROM_BANK8(0x8000,V); |
23 | break; |
24 | case 0xA000: ROM_BANK8(0xa000,V); break; |
25 | case 0x9000: |
26 | switch(V&3){ |
27 | case 0:setmirror(MI_V);break; |
28 | case 1:setmirror(MI_H);break; |
29 | case 2:setmirror(MI_0);break; |
30 | case 3:setmirror(MI_1);break; |
31 | } |
32 | case 0x9002: regchr[8]=V; break; |
33 | case 0xF000: //X6502_IRQEnd(FCEU_IQEXT); |
34 | IRQLatch=(IRQLatch&0xF0)|(V&0x0F); |
35 | break; |
36 | case 0xF001: //X6502_IRQEnd(FCEU_IQEXT); |
37 | IRQLatch=(IRQLatch&0x0F)|((V&0xF)<<4); |
38 | break; |
39 | case 0xF003: IRQa=((IRQa&0x1)<<1)|(IRQa&0x1); |
40 | X6502_IRQEnd(FCEU_IQEXT); |
41 | break; |
42 | case 0xF002: IRQa=V&3; |
43 | if(IRQa&0x02) IRQCount=IRQLatch; |
44 | X6502_IRQEnd(FCEU_IQEXT); |
45 | break; |
46 | } |
47 | // if((A&0xF000)==0xF000) FCEU_printf("$%04x:$%02x, %d\n",A,V, scanline); |
48 | } |
49 | |
50 | static void Mapper27_hb(void) |
51 | { |
52 | // FCEU_printf("%02x-%d,%d,%d\n",scanline,IRQa,IRQCount,IRQLatch); |
53 | if(IRQa&0x2){ |
54 | if(IRQCount==0xFF){ |
55 | X6502_IRQBegin(FCEU_IQEXT); |
56 | IRQCount=IRQLatch+1; |
57 | } else { |
58 | IRQCount++; |
59 | } |
60 | } |
61 | } |
62 | |
63 | void Mapper27_init(void) |
64 | { |
65 | int i; |
66 | for (i=0; i<9; i++) { |
67 | regchr[i]=0; |
68 | } |
69 | IRQa=0; |
70 | IRQCount=IRQLatch=0; |
71 | SetWriteHandler(0x8000,0xffff,Mapper27_write); |
72 | GameHBIRQHook=Mapper27_hb; |
73 | } |
74 | |