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DYNAREC: More work on DIV, no effect
[mupen64plus-pandora.git] / source / mupen64plus-core / src / r4300 / interpreter_cop1.def
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451ab91e 1/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - interpreter_cop1.def *
3 * Mupen64Plus homepage: http://code.google.com/p/mupen64plus/ *
4 * Copyright (C) 2002 Hacktarux *
5 * *
6 * This program is free software; you can redistribute it and/or modify *
7 * it under the terms of the GNU General Public License as published by *
8 * the Free Software Foundation; either version 2 of the License, or *
9 * (at your option) any later version. *
10 * *
11 * This program is distributed in the hope that it will be useful, *
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
14 * GNU General Public License for more details. *
15 * *
16 * You should have received a copy of the GNU General Public License *
17 * along with this program; if not, write to the *
18 * Free Software Foundation, Inc., *
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
20 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
21
22#include "fpu.h"
23
24DECLARE_JUMP(BC1F, PCADDR + (iimmediate+1)*4, (FCR31 & 0x800000)==0, &reg[0], 0, 1)
25DECLARE_JUMP(BC1T, PCADDR + (iimmediate+1)*4, (FCR31 & 0x800000)!=0, &reg[0], 0, 1)
26DECLARE_JUMP(BC1FL, PCADDR + (iimmediate+1)*4, (FCR31 & 0x800000)==0, &reg[0], 1, 1)
27DECLARE_JUMP(BC1TL, PCADDR + (iimmediate+1)*4, (FCR31 & 0x800000)!=0, &reg[0], 1, 1)
28
29DECLARE_INSTRUCTION(MFC1)
30{
31 if (check_cop1_unusable()) return;
32 rrt32 = *((int*)reg_cop1_simple[rfs]);
33 sign_extended(rrt);
34 ADD_TO_PC(1);
35}
36
37DECLARE_INSTRUCTION(DMFC1)
38{
39 if (check_cop1_unusable()) return;
40 rrt = *((long long*)reg_cop1_double[rfs]);
41 ADD_TO_PC(1);
42}
43
44DECLARE_INSTRUCTION(CFC1)
45{
46 if (check_cop1_unusable()) return;
47 if (rfs==31)
48 {
49 rrt32 = FCR31;
50 sign_extended(rrt);
51 }
52 if (rfs==0)
53 {
54 rrt32 = FCR0;
55 sign_extended(rrt);
56 }
57 ADD_TO_PC(1);
58}
59
60DECLARE_INSTRUCTION(MTC1)
61{
62 if (check_cop1_unusable()) return;
63 *((int*)reg_cop1_simple[rfs]) = rrt32;
64 ADD_TO_PC(1);
65}
66
67DECLARE_INSTRUCTION(DMTC1)
68{
69 if (check_cop1_unusable()) return;
70 *((long long*)reg_cop1_double[rfs]) = rrt;
71 ADD_TO_PC(1);
72}
73
74DECLARE_INSTRUCTION(CTC1)
75{
76 if (check_cop1_unusable()) return;
77 if (rfs==31)
78 FCR31 = rrt32;
79 switch((FCR31 & 3))
80 {
81 case 0:
82 rounding_mode = 0x33F; // Round to nearest, or to even if equidistant
83 break;
84 case 1:
85 rounding_mode = 0xF3F; // Truncate (toward 0)
86 break;
87 case 2:
88 rounding_mode = 0xB3F; // Round up (toward +infinity)
89 break;
90 case 3:
91 rounding_mode = 0x73F; // Round down (toward -infinity)
92 break;
93 }
94 //if ((FCR31 >> 7) & 0x1F) printf("FPU Exception enabled : %x\n",
95 // (int)((FCR31 >> 7) & 0x1F));
96 ADD_TO_PC(1);
97}
98
99// COP1_D
100DECLARE_INSTRUCTION(ADD_D)
101{
102 if (check_cop1_unusable()) return;
103 add_d(reg_cop1_double[cffs], reg_cop1_double[cfft], reg_cop1_double[cffd]);
104 ADD_TO_PC(1);
105}
106
107DECLARE_INSTRUCTION(SUB_D)
108{
109 if (check_cop1_unusable()) return;
110 sub_d(reg_cop1_double[cffs], reg_cop1_double[cfft], reg_cop1_double[cffd]);
111 ADD_TO_PC(1);
112}
113
114DECLARE_INSTRUCTION(MUL_D)
115{
116 if (check_cop1_unusable()) return;
117 mul_d(reg_cop1_double[cffs], reg_cop1_double[cfft], reg_cop1_double[cffd]);
118 ADD_TO_PC(1);
119}
120
121DECLARE_INSTRUCTION(DIV_D)
122{
123 if (check_cop1_unusable()) return;
124 if((FCR31 & 0x400) && *reg_cop1_double[cfft] == 0)
125 {
126 //FCR31 |= 0x8020;
127 /*FCR31 |= 0x8000;
128 Cause = 15 << 2;
129 exception_general();*/
130 DebugMessage(M64MSG_ERROR, "DIV_D by 0");
131 //return;
132 }
133 div_d(reg_cop1_double[cffs], reg_cop1_double[cfft], reg_cop1_double[cffd]);
134 ADD_TO_PC(1);
135}
136
137DECLARE_INSTRUCTION(SQRT_D)
138{
139 if (check_cop1_unusable()) return;
140 sqrt_d(reg_cop1_double[cffs], reg_cop1_double[cffd]);
141 ADD_TO_PC(1);
142}
143
144DECLARE_INSTRUCTION(ABS_D)
145{
146 if (check_cop1_unusable()) return;
147 abs_d(reg_cop1_double[cffs], reg_cop1_double[cffd]);
148 ADD_TO_PC(1);
149}
150
151DECLARE_INSTRUCTION(MOV_D)
152{
153 if (check_cop1_unusable()) return;
154 mov_d(reg_cop1_double[cffs], reg_cop1_double[cffd]);
155 ADD_TO_PC(1);
156}
157
158DECLARE_INSTRUCTION(NEG_D)
159{
160 if (check_cop1_unusable()) return;
161 neg_d(reg_cop1_double[cffs], reg_cop1_double[cffd]);
162 ADD_TO_PC(1);
163}
164
165DECLARE_INSTRUCTION(ROUND_L_D)
166{
167 if (check_cop1_unusable()) return;
168 round_l_d(reg_cop1_double[cffs], (long long*)(reg_cop1_double[cffd]));
169 ADD_TO_PC(1);
170}
171
172DECLARE_INSTRUCTION(TRUNC_L_D)
173{
174 if (check_cop1_unusable()) return;
175 trunc_l_d(reg_cop1_double[cffs], (long long*)(reg_cop1_double[cffd]));
176 ADD_TO_PC(1);
177}
178
179DECLARE_INSTRUCTION(CEIL_L_D)
180{
181 if (check_cop1_unusable()) return;
182 ceil_l_d(reg_cop1_double[cffs], (long long*)(reg_cop1_double[cffd]));
183 ADD_TO_PC(1);
184}
185
186DECLARE_INSTRUCTION(FLOOR_L_D)
187{
188 if (check_cop1_unusable()) return;
189 floor_l_d(reg_cop1_double[cffs], (long long*)(reg_cop1_double[cffd]));
190 ADD_TO_PC(1);
191}
192
193DECLARE_INSTRUCTION(ROUND_W_D)
194{
195 if (check_cop1_unusable()) return;
196 round_w_d(reg_cop1_double[cffs], (int*)reg_cop1_simple[cffd]);
197 ADD_TO_PC(1);
198}
199
200DECLARE_INSTRUCTION(TRUNC_W_D)
201{
202 if (check_cop1_unusable()) return;
203 trunc_w_d(reg_cop1_double[cffs], (int*)reg_cop1_simple[cffd]);
204 ADD_TO_PC(1);
205}
206
207DECLARE_INSTRUCTION(CEIL_W_D)
208{
209 if (check_cop1_unusable()) return;
210 ceil_w_d(reg_cop1_double[cffs], (int*)reg_cop1_simple[cffd]);
211 ADD_TO_PC(1);
212}
213
214DECLARE_INSTRUCTION(FLOOR_W_D)
215{
216 if (check_cop1_unusable()) return;
217 floor_w_d(reg_cop1_double[cffs], (int*)reg_cop1_simple[cffd]);
218 ADD_TO_PC(1);
219}
220
221DECLARE_INSTRUCTION(CVT_S_D)
222{
223 if (check_cop1_unusable()) return;
224 cvt_s_d(reg_cop1_double[cffs], reg_cop1_simple[cffd]);
225 ADD_TO_PC(1);
226}
227
228DECLARE_INSTRUCTION(CVT_W_D)
229{
230 if (check_cop1_unusable()) return;
231 cvt_w_d(reg_cop1_double[cffs], (int*)reg_cop1_simple[cffd]);
232 ADD_TO_PC(1);
233}
234
235DECLARE_INSTRUCTION(CVT_L_D)
236{
237 if (check_cop1_unusable()) return;
238 cvt_l_d(reg_cop1_double[cffs], (long long*)(reg_cop1_double[cffd]));
239 ADD_TO_PC(1);
240}
241
242DECLARE_INSTRUCTION(C_F_D)
243{
244 if (check_cop1_unusable()) return;
245 c_f_d();
246 ADD_TO_PC(1);
247}
248
249DECLARE_INSTRUCTION(C_UN_D)
250{
251 if (check_cop1_unusable()) return;
252 c_un_d(reg_cop1_double[cffs], reg_cop1_double[cfft]);
253 ADD_TO_PC(1);
254}
255
256DECLARE_INSTRUCTION(C_EQ_D)
257{
258 if (check_cop1_unusable()) return;
259 c_eq_d(reg_cop1_double[cffs], reg_cop1_double[cfft]);
260 ADD_TO_PC(1);
261}
262
263DECLARE_INSTRUCTION(C_UEQ_D)
264{
265 if (check_cop1_unusable()) return;
266 c_ueq_d(reg_cop1_double[cffs], reg_cop1_double[cfft]);
267 ADD_TO_PC(1);
268}
269
270DECLARE_INSTRUCTION(C_OLT_D)
271{
272 if (check_cop1_unusable()) return;
273 c_olt_d(reg_cop1_double[cffs], reg_cop1_double[cfft]);
274 ADD_TO_PC(1);
275}
276
277DECLARE_INSTRUCTION(C_ULT_D)
278{
279 if (check_cop1_unusable()) return;
280 c_ult_d(reg_cop1_double[cffs], reg_cop1_double[cfft]);
281 ADD_TO_PC(1);
282}
283
284DECLARE_INSTRUCTION(C_OLE_D)
285{
286 if (check_cop1_unusable()) return;
287 c_ole_d(reg_cop1_double[cffs], reg_cop1_double[cfft]);
288 ADD_TO_PC(1);
289}
290
291DECLARE_INSTRUCTION(C_ULE_D)
292{
293 if (check_cop1_unusable()) return;
294 c_ule_d(reg_cop1_double[cffs], reg_cop1_double[cfft]);
295 ADD_TO_PC(1);
296}
297
298DECLARE_INSTRUCTION(C_SF_D)
299{
300 if (isnan(*reg_cop1_double[cffs]) || isnan(*reg_cop1_double[cfft]))
301 {
302 DebugMessage(M64MSG_ERROR, "Invalid operation exception in C opcode");
303 stop=1;
304 }
305 c_sf_d(reg_cop1_double[cffs], reg_cop1_double[cfft]);
306 ADD_TO_PC(1);
307}
308
309DECLARE_INSTRUCTION(C_NGLE_D)
310{
311 if (isnan(*reg_cop1_double[cffs]) || isnan(*reg_cop1_double[cfft]))
312 {
313 DebugMessage(M64MSG_ERROR, "Invalid operation exception in C opcode");
314 stop=1;
315 }
316 c_ngle_d(reg_cop1_double[cffs], reg_cop1_double[cfft]);
317 ADD_TO_PC(1);
318}
319
320DECLARE_INSTRUCTION(C_SEQ_D)
321{
322 if (isnan(*reg_cop1_double[cffs]) || isnan(*reg_cop1_double[cfft]))
323 {
324 DebugMessage(M64MSG_ERROR, "Invalid operation exception in C opcode");
325 stop=1;
326 }
327 c_seq_d(reg_cop1_double[cffs], reg_cop1_double[cfft]);
328 ADD_TO_PC(1);
329}
330
331DECLARE_INSTRUCTION(C_NGL_D)
332{
333 if (isnan(*reg_cop1_double[cffs]) || isnan(*reg_cop1_double[cfft]))
334 {
335 DebugMessage(M64MSG_ERROR, "Invalid operation exception in C opcode");
336 stop=1;
337 }
338 c_ngl_d(reg_cop1_double[cffs], reg_cop1_double[cfft]);
339 ADD_TO_PC(1);
340}
341
342DECLARE_INSTRUCTION(C_LT_D)
343{
344 if (check_cop1_unusable()) return;
345 if (isnan(*reg_cop1_double[cffs]) || isnan(*reg_cop1_double[cfft]))
346 {
347 DebugMessage(M64MSG_ERROR, "Invalid operation exception in C opcode");
348 stop=1;
349 }
350 c_lt_d(reg_cop1_double[cffs], reg_cop1_double[cfft]);
351 ADD_TO_PC(1);
352}
353
354DECLARE_INSTRUCTION(C_NGE_D)
355{
356 if (check_cop1_unusable()) return;
357 if (isnan(*reg_cop1_double[cffs]) || isnan(*reg_cop1_double[cfft]))
358 {
359 DebugMessage(M64MSG_ERROR, "Invalid operation exception in C opcode");
360 stop=1;
361 }
362 c_nge_d(reg_cop1_double[cffs], reg_cop1_double[cfft]);
363 ADD_TO_PC(1);
364}
365
366DECLARE_INSTRUCTION(C_LE_D)
367{
368 if (check_cop1_unusable()) return;
369 if (isnan(*reg_cop1_double[cffs]) || isnan(*reg_cop1_double[cfft]))
370 {
371 DebugMessage(M64MSG_ERROR, "Invalid operation exception in C opcode");
372 stop=1;
373 }
374 c_le_d(reg_cop1_double[cffs], reg_cop1_double[cfft]);
375 ADD_TO_PC(1);
376}
377
378DECLARE_INSTRUCTION(C_NGT_D)
379{
380 if (check_cop1_unusable()) return;
381 if (isnan(*reg_cop1_double[cffs]) || isnan(*reg_cop1_double[cfft]))
382 {
383 DebugMessage(M64MSG_ERROR, "Invalid operation exception in C opcode");
384 stop=1;
385 }
386 c_ngt_d(reg_cop1_double[cffs], reg_cop1_double[cfft]);
387 ADD_TO_PC(1);
388}
389
390// COP1_L
391DECLARE_INSTRUCTION(CVT_S_L)
392{
393 if (check_cop1_unusable()) return;
394 cvt_s_l((long long*)(reg_cop1_double[cffs]), reg_cop1_simple[cffd]);
395 ADD_TO_PC(1);
396}
397
398DECLARE_INSTRUCTION(CVT_D_L)
399{
400 if (check_cop1_unusable()) return;
401 cvt_d_l((long long*)(reg_cop1_double[cffs]), reg_cop1_double[cffd]);
402 ADD_TO_PC(1);
403}
404
405// COP1_S
406DECLARE_INSTRUCTION(ADD_S)
407{
408 if (check_cop1_unusable()) return;
409 add_s(reg_cop1_simple[cffs], reg_cop1_simple[cfft], reg_cop1_simple[cffd]);
410 ADD_TO_PC(1);
411}
412
413DECLARE_INSTRUCTION(SUB_S)
414{
415 if (check_cop1_unusable()) return;
416 sub_s(reg_cop1_simple[cffs], reg_cop1_simple[cfft], reg_cop1_simple[cffd]);
417 ADD_TO_PC(1);
418}
419
420DECLARE_INSTRUCTION(MUL_S)
421{
422 if (check_cop1_unusable()) return;
423 mul_s(reg_cop1_simple[cffs], reg_cop1_simple[cfft], reg_cop1_simple[cffd]);
424 ADD_TO_PC(1);
425}
426
427DECLARE_INSTRUCTION(DIV_S)
428{
429 if (check_cop1_unusable()) return;
430 if((FCR31 & 0x400) && *reg_cop1_simple[cfft] == 0)
431 {
432 DebugMessage(M64MSG_ERROR, "DIV_S by 0");
433 }
434 div_s(reg_cop1_simple[cffs], reg_cop1_simple[cfft], reg_cop1_simple[cffd]);
435 ADD_TO_PC(1);
436}
437
438DECLARE_INSTRUCTION(SQRT_S)
439{
440 if (check_cop1_unusable()) return;
441 sqrt_s(reg_cop1_simple[cffs], reg_cop1_simple[cffd]);
442 ADD_TO_PC(1);
443}
444
445DECLARE_INSTRUCTION(ABS_S)
446{
447 if (check_cop1_unusable()) return;
448 abs_s(reg_cop1_simple[cffs], reg_cop1_simple[cffd]);
449 ADD_TO_PC(1);
450}
451
452DECLARE_INSTRUCTION(MOV_S)
453{
454 if (check_cop1_unusable()) return;
455 mov_s(reg_cop1_simple[cffs], reg_cop1_simple[cffd]);
456 ADD_TO_PC(1);
457}
458
459DECLARE_INSTRUCTION(NEG_S)
460{
461 if (check_cop1_unusable()) return;
462 neg_s(reg_cop1_simple[cffs], reg_cop1_simple[cffd]);
463 ADD_TO_PC(1);
464}
465
466DECLARE_INSTRUCTION(ROUND_L_S)
467{
468 if (check_cop1_unusable()) return;
469 round_l_s(reg_cop1_simple[cffs], (long long*)(reg_cop1_double[cffd]));
470 ADD_TO_PC(1);
471}
472
473DECLARE_INSTRUCTION(TRUNC_L_S)
474{
475 if (check_cop1_unusable()) return;
476 trunc_l_s(reg_cop1_simple[cffs], (long long*)(reg_cop1_double[cffd]));
477 ADD_TO_PC(1);
478}
479
480DECLARE_INSTRUCTION(CEIL_L_S)
481{
482 if (check_cop1_unusable()) return;
483 ceil_l_s(reg_cop1_simple[cffs], (long long*)(reg_cop1_double[cffd]));
484 ADD_TO_PC(1);
485}
486
487DECLARE_INSTRUCTION(FLOOR_L_S)
488{
489 if (check_cop1_unusable()) return;
490 floor_l_s(reg_cop1_simple[cffs], (long long*)(reg_cop1_double[cffd]));
491 ADD_TO_PC(1);
492}
493
494DECLARE_INSTRUCTION(ROUND_W_S)
495{
496 if (check_cop1_unusable()) return;
497 round_w_s(reg_cop1_simple[cffs], (int*)reg_cop1_simple[cffd]);
498 ADD_TO_PC(1);
499}
500
501DECLARE_INSTRUCTION(TRUNC_W_S)
502{
503 if (check_cop1_unusable()) return;
504 trunc_w_s(reg_cop1_simple[cffs], (int*)reg_cop1_simple[cffd]);
505 ADD_TO_PC(1);
506}
507
508DECLARE_INSTRUCTION(CEIL_W_S)
509{
510 if (check_cop1_unusable()) return;
511 ceil_w_s(reg_cop1_simple[cffs], (int*)reg_cop1_simple[cffd]);
512 ADD_TO_PC(1);
513}
514
515DECLARE_INSTRUCTION(FLOOR_W_S)
516{
517 if (check_cop1_unusable()) return;
518 floor_w_s(reg_cop1_simple[cffs], (int*)reg_cop1_simple[cffd]);
519 ADD_TO_PC(1);
520}
521
522DECLARE_INSTRUCTION(CVT_D_S)
523{
524 if (check_cop1_unusable()) return;
525 cvt_d_s(reg_cop1_simple[cffs], reg_cop1_double[cffd]);
526 ADD_TO_PC(1);
527}
528
529DECLARE_INSTRUCTION(CVT_W_S)
530{
531 if (check_cop1_unusable()) return;
532 cvt_w_s(reg_cop1_simple[cffs], (int*)reg_cop1_simple[cffd]);
533 ADD_TO_PC(1);
534}
535
536DECLARE_INSTRUCTION(CVT_L_S)
537{
538 if (check_cop1_unusable()) return;
539 cvt_l_s(reg_cop1_simple[cffs], (long long*)(reg_cop1_double[cffd]));
540 ADD_TO_PC(1);
541}
542
543DECLARE_INSTRUCTION(C_F_S)
544{
545 if (check_cop1_unusable()) return;
546 c_f_s();
547 ADD_TO_PC(1);
548}
549
550DECLARE_INSTRUCTION(C_UN_S)
551{
552 if (check_cop1_unusable()) return;
553 c_un_s(reg_cop1_simple[cffs], reg_cop1_simple[cfft]);
554 ADD_TO_PC(1);
555}
556
557DECLARE_INSTRUCTION(C_EQ_S)
558{
559 if (check_cop1_unusable()) return;
560 c_eq_s(reg_cop1_simple[cffs], reg_cop1_simple[cfft]);
561 ADD_TO_PC(1);
562}
563
564DECLARE_INSTRUCTION(C_UEQ_S)
565{
566 if (check_cop1_unusable()) return;
567 c_ueq_s(reg_cop1_simple[cffs], reg_cop1_simple[cfft]);
568 ADD_TO_PC(1);
569}
570
571DECLARE_INSTRUCTION(C_OLT_S)
572{
573 if (check_cop1_unusable()) return;
574 c_olt_s(reg_cop1_simple[cffs], reg_cop1_simple[cfft]);
575 ADD_TO_PC(1);
576}
577
578DECLARE_INSTRUCTION(C_ULT_S)
579{
580 if (check_cop1_unusable()) return;
581 c_ult_s(reg_cop1_simple[cffs], reg_cop1_simple[cfft]);
582 ADD_TO_PC(1);
583}
584
585DECLARE_INSTRUCTION(C_OLE_S)
586{
587 if (check_cop1_unusable()) return;
588 c_ole_s(reg_cop1_simple[cffs], reg_cop1_simple[cfft]);
589 ADD_TO_PC(1);
590}
591
592DECLARE_INSTRUCTION(C_ULE_S)
593{
594 if (check_cop1_unusable()) return;
595 c_ule_s(reg_cop1_simple[cffs], reg_cop1_simple[cfft]);
596 ADD_TO_PC(1);
597}
598
599DECLARE_INSTRUCTION(C_SF_S)
600{
601 if (check_cop1_unusable()) return;
602 if (isnan(*reg_cop1_simple[cffs]) || isnan(*reg_cop1_simple[cfft]))
603 {
604 DebugMessage(M64MSG_ERROR, "Invalid operation exception in C opcode");
605 stop=1;
606 }
607 c_sf_s(reg_cop1_simple[cffs], reg_cop1_simple[cfft]);
608 ADD_TO_PC(1);
609}
610
611DECLARE_INSTRUCTION(C_NGLE_S)
612{
613 if (check_cop1_unusable()) return;
614 if (isnan(*reg_cop1_simple[cffs]) || isnan(*reg_cop1_simple[cfft]))
615 {
616 DebugMessage(M64MSG_ERROR, "Invalid operation exception in C opcode");
617 stop=1;
618 }
619 c_ngle_s(reg_cop1_simple[cffs], reg_cop1_simple[cfft]);
620 ADD_TO_PC(1);
621}
622
623DECLARE_INSTRUCTION(C_SEQ_S)
624{
625 if (check_cop1_unusable()) return;
626 if (isnan(*reg_cop1_simple[cffs]) || isnan(*reg_cop1_simple[cfft]))
627 {
628 DebugMessage(M64MSG_ERROR, "Invalid operation exception in C opcode");
629 stop=1;
630 }
631 c_seq_s(reg_cop1_simple[cffs], reg_cop1_simple[cfft]);
632 ADD_TO_PC(1);
633}
634
635DECLARE_INSTRUCTION(C_NGL_S)
636{
637 if (check_cop1_unusable()) return;
638 if (isnan(*reg_cop1_simple[cffs]) || isnan(*reg_cop1_simple[cfft]))
639 {
640 DebugMessage(M64MSG_ERROR, "Invalid operation exception in C opcode");
641 stop=1;
642 }
643 c_ngl_s(reg_cop1_simple[cffs], reg_cop1_simple[cfft]);
644 ADD_TO_PC(1);
645}
646
647DECLARE_INSTRUCTION(C_LT_S)
648{
649 if (check_cop1_unusable()) return;
650 if (isnan(*reg_cop1_simple[cffs]) || isnan(*reg_cop1_simple[cfft]))
651 {
652 DebugMessage(M64MSG_ERROR, "Invalid operation exception in C opcode");
653 stop=1;
654 }
655 c_lt_s(reg_cop1_simple[cffs], reg_cop1_simple[cfft]);
656 ADD_TO_PC(1);
657}
658
659DECLARE_INSTRUCTION(C_NGE_S)
660{
661 if (check_cop1_unusable()) return;
662 if (isnan(*reg_cop1_simple[cffs]) || isnan(*reg_cop1_simple[cfft]))
663 {
664 DebugMessage(M64MSG_ERROR, "Invalid operation exception in C opcode");
665 stop=1;
666 }
667 c_nge_s(reg_cop1_simple[cffs], reg_cop1_simple[cfft]);
668 ADD_TO_PC(1);
669}
670
671DECLARE_INSTRUCTION(C_LE_S)
672{
673 if (check_cop1_unusable()) return;
674 if (isnan(*reg_cop1_simple[cffs]) || isnan(*reg_cop1_simple[cfft]))
675 {
676 DebugMessage(M64MSG_ERROR, "Invalid operation exception in C opcode");
677 stop=1;
678 }
679 c_le_s(reg_cop1_simple[cffs], reg_cop1_simple[cfft]);
680 ADD_TO_PC(1);
681}
682
683DECLARE_INSTRUCTION(C_NGT_S)
684{
685 if (check_cop1_unusable()) return;
686 if (isnan(*reg_cop1_simple[cffs]) || isnan(*reg_cop1_simple[cfft]))
687 {
688 DebugMessage(M64MSG_ERROR, "Invalid operation exception in C opcode");
689 stop=1;
690 }
691 c_ngt_s(reg_cop1_simple[cffs], reg_cop1_simple[cfft]);
692 ADD_TO_PC(1);
693}
694
695// COP1_W
696DECLARE_INSTRUCTION(CVT_S_W)
697{
698 if (check_cop1_unusable()) return;
699 cvt_s_w((int*)reg_cop1_simple[cffs], reg_cop1_simple[cffd]);
700 ADD_TO_PC(1);
701}
702
703DECLARE_INSTRUCTION(CVT_D_W)
704{
705 if (check_cop1_unusable()) return;
706 cvt_d_w((int*)reg_cop1_simple[cffs], reg_cop1_double[cffd]);
707 ADD_TO_PC(1);
708}
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