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1 | /* FCE Ultra - NES/Famicom Emulator |
2 | * |
3 | * Copyright notice for this file: |
4 | * Copyright (C) 2002 Ben Parnell |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify |
7 | * it under the terms of the GNU General Public License as published by |
8 | * the Free Software Foundation; either version 2 of the License, or |
9 | * (at your option) any later version. |
10 | * |
11 | * This program is distributed in the hope that it will be useful, |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
14 | * GNU General Public License for more details. |
15 | * |
16 | * You should have received a copy of the GNU General Public License |
17 | * along with this program; if not, write to the Free Software |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
19 | */ |
20 | |
21 | typedef struct { |
22 | int32 count; /* Cycle counter */ |
23 | int32 tcount; /* Temporary cycle counter */ |
24 | uint16 PC; /* I'll change this to uint32 later... */ |
25 | /* I'll need to AND PC after increments to 0xFFFF */ |
26 | /* when I do, though. Perhaps an IPC() macro? */ |
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27 | uint8 A,X,Y,S,P,mooPI; |
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28 | uint8 DB; /* Data bus "cache" for reads from certain areas */ |
29 | uint8 IRQlow; /* Simulated IRQ pin held low(or is it high?). */ |
30 | uint8 jammed; |
31 | } X6502; |
32 | |
33 | extern X6502 X; |
34 | |
35 | #define N_FLAG 0x80 |
36 | #define V_FLAG 0x40 |
37 | #define U_FLAG 0x20 |
38 | #define B_FLAG 0x10 |
39 | #define D_FLAG 0x08 |
40 | #define I_FLAG 0x04 |
41 | #define Z_FLAG 0x02 |
42 | #define C_FLAG 0x01 |
43 | |
44 | extern uint32 timestamp; |
45 | extern void FP_FASTAPASS(1) (*MapIRQHook)(int a); |
46 | |
47 | #define NTSC_CPU 1789772.7272727272727272 |
48 | #define PAL_CPU 1662607.125 |
49 | |
50 | #define FCEU_IQEXT 0x01 |
51 | #define FCEU_IQNMI 0x08 |
52 | #define FCEU_IQDPCM 0x10 |
53 | #define FCEU_IQFCOUNT 0x20 |
54 | #define FCEU_IQTEMP 0x80 |
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55 | // from 0.98.15 |
56 | #define FCEU_IQEXT2 0x02 |
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57 | |
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58 | #if defined(DEBUG_ASM_6502) |
59 | #define TriggerIRQ TriggerIRQ_d |
60 | #define TriggerNMI TriggerNMI_d |
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61 | #define X6502_Run X6502_Run_d |
62 | #define X6502_Reset X6502_Reset_d |
63 | #define X6502_Power X6502_Power_d |
64 | #define X6502_AddCycles X6502_AddCycles_d |
65 | #define X6502_IRQBegin X6502_IRQBegin_d |
66 | #define X6502_IRQEnd X6502_IRQEnd_d |
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67 | #define X6502_Rebase X6502_Rebase_d |
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68 | #define X6502_GetCycleCount() g_cnt |
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69 | #define X6502_C |
70 | #define X6502_A |
71 | #define X6502_D |
72 | |
73 | #elif defined(ASM_6502) |
74 | #define TriggerIRQ TriggerIRQ_a |
75 | #define TriggerNMI TriggerNMI_a |
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76 | #define X6502_Reset X6502_Reset_a |
77 | #define X6502_Power X6502_Power_a |
78 | #define X6502_AddCycles X6502_AddCycles_a |
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79 | //#define X6502_IRQBegin X6502_IRQBegin_a |
80 | //#define X6502_IRQEnd X6502_IRQEnd_a |
81 | #define X6502_IRQBegin(w) nes_registers[4]|=w<<8 |
82 | #define X6502_IRQEnd(w) nes_registers[4]&=~(w<<8) |
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83 | #define X6502_Rebase X6502_Rebase_a |
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84 | #define X6502_GetCycleCount() ((int32)nes_registers[7]>>16) |
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85 | #define X6502_A |
86 | |
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87 | #define X6502_Run(c) \ |
88 | { \ |
89 | int32 cycles = (c) << 4; /* *16 */ \ |
90 | if (PAL) cycles -= (c); /* *15 */ \ |
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91 | nes_registers[7]+=cycles<<16; \ |
92 | cycles=(int32)nes_registers[7]>>16; \ |
93 | if (cycles > 0) { \ |
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94 | X6502_Run_a(); \ |
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95 | cycles -= (int32)nes_registers[7]>>16; \ |
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96 | asmcpu_update(cycles); \ |
97 | } \ |
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98 | } |
99 | |
100 | #else |
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101 | #define TriggerIRQ TriggerIRQ_c |
102 | #define TriggerNMI TriggerNMI_c |
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103 | #define X6502_Reset X6502_Reset_c |
104 | #define X6502_Power X6502_Power_c |
105 | #define X6502_AddCycles X6502_AddCycles_c |
106 | #define X6502_IRQBegin X6502_IRQBegin_c |
107 | #define X6502_IRQEnd X6502_IRQEnd_c |
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108 | #define X6502_Rebase(...) |
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109 | #define X6502_GetCycleCount() X.count |
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110 | #define X6502_C |
111 | |
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112 | #define X6502_Run(c) \ |
113 | { \ |
114 | int32 cycles = (c) << 4; /* *16 */ \ |
115 | if (PAL) cycles -= (c); /* *15 */ \ |
116 | X.count+=cycles; \ |
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117 | if (X.count > 0) X6502_Run_c(); \ |
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118 | } |
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119 | #define X6502_C |
120 | #endif |
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121 | |
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122 | // c |
123 | #ifdef X6502_C |
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124 | extern int32 g_cnt; |
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125 | void TriggerIRQ_c(void); |
126 | void TriggerNMI_c(void); |
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127 | void X6502_Run_c(void); |
128 | void X6502_Reset_c(void); |
129 | void X6502_Power_c(void); |
130 | void FASTAPASS(1) X6502_AddCycles_c(int x); |
131 | void FASTAPASS(1) X6502_IRQBegin_c(int w); |
132 | void FASTAPASS(1) X6502_IRQEnd_c(int w); |
133 | #endif |
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134 | |
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135 | // asm |
136 | #ifdef X6502_A |
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137 | extern uint32 nes_registers[0x10]; |
138 | extern uint32 pc_base; |
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139 | void TriggerIRQ_a(void); |
140 | void TriggerNMI_a(void); |
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141 | void X6502_Run_a(void); |
142 | void X6502_Reset_a(void); |
143 | void X6502_Power_a(void); |
144 | void X6502_AddCycles_a(int x); |
145 | void X6502_IRQBegin_a(int w); |
146 | void X6502_IRQEnd_a(int w); |
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147 | void X6502_Rebase_a(void); |
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148 | #endif |
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149 | |
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150 | // debug |
151 | #ifdef X6502_D |
152 | void TriggerIRQ_d(void); |
153 | void TriggerNMI_d(void); |
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154 | void X6502_Run_d(int32 c); |
155 | void X6502_Reset_d(void); |
156 | void X6502_Power_d(void); |
157 | void X6502_AddCycles_d(int x); |
158 | void X6502_IRQBegin_d(int w); |
159 | void X6502_IRQEnd_d(int w); |
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160 | void X6502_Rebase_d(void); |
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161 | #endif |
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162 | |