| 1 | The NES sound channel guide 1.8 |
| 2 | Written by Brad Taylor. |
| 3 | btmine@hotmail.com |
| 4 | |
| 5 | Last updated: July 27th, 2000. |
| 6 | |
| 7 | All results were obtained by studying prior information available (from |
| 8 | nestech 1.00, and postings on NESDev from miscellanious people), and through |
| 9 | a series of experiments conducted by me. Results acquired by individuals |
| 10 | prior to my reverse-engineering have been double checked, and final results |
| 11 | have been confirmed. Credit is due to those individual(s) who contributed |
| 12 | any information in regards to the the miscellanious sound channels wihtin |
| 13 | the NES. |
| 14 | |
| 15 | A special thanks goes out to Matthew Conte, for his expertise on |
| 16 | pseudo-random number generation (amoung other things), which allowed for the |
| 17 | full reverse engineering of the NES's noise channel to take place. Without |
| 18 | his help, I would still be trying to find a needle in a haystack, as far as |
| 19 | the noise's method of pseudo-random number generation goes. Additionally, |
| 20 | his previous findings / reverse engineering work on the NES's sound hardware |
| 21 | really got the ball of NES sound emulation rolling. If it weren't for Matt's |
| 22 | original work, this document wouldn't exist. |
| 23 | |
| 24 | Thanks to Kentaro Ishihara, for his excellent work on finding the difference |
| 25 | in upward frequency sweep between the 2 square wave channels. |
| 26 | |
| 27 | **************** |
| 28 | * Introduction * |
| 29 | **************** |
| 30 | |
| 31 | The 2A03 (NES's integrated CPU) has 4 internal channels to it that have the |
| 32 | ability to generate semi-analog sound, for musical playback purposes. These |
| 33 | channels are 2 square wave channels, one triangle wave channel, and a noise |
| 34 | generation channel. This document will go into full detail on every aspect |
| 35 | of the operation and timing of the mentioned sound channels. |
| 36 | |
| 37 | |
| 38 | ******************* |
| 39 | * Channel details * |
| 40 | ******************* |
| 41 | |
| 42 | Each channel has different characteristics to it that make up it's |
| 43 | operation. |
| 44 | |
| 45 | The square channel(s) have the ability to generate a square wave frequency |
| 46 | in the range of 54.6 Hz to 12.4 KHz. It's key features are frequency sweep |
| 47 | abilities, and output duty cycle adjustment. |
| 48 | |
| 49 | The triangle wave channel has the ability to generate an output triangle |
| 50 | wave with a resolution of 4-bits (16 steps), in the range of 27.3 Hz to 55.9 |
| 51 | KHz. The key features this channel has is it's analog triangle wave output, |
| 52 | and it's linear counter, which can be set to automatically disable the |
| 53 | channel's sound after a certain period of time has gone by. |
| 54 | |
| 55 | The noise channel is used for producing random frequencys, which results in |
| 56 | a "noisey" sounding output. Output frequencys can range anywhere from 29.3 |
| 57 | Hz to 447 KHz. It's key feature is it's pseudo- random number generator, |
| 58 | which generates the random output frequencys heard by the channel. |
| 59 | |
| 60 | |
| 61 | ***************** |
| 62 | * Frame counter * |
| 63 | ***************** |
| 64 | |
| 65 | The 2A03 has an internal frame counter. It has the ability to generate 60 Hz |
| 66 | (1/1 framerate), 120 Hz (1/2 framerate), and 240 Hz (1/4 framerate) signals, |
| 67 | used by some of the sound hardware. The 1/4 framerate is calculated by |
| 68 | taking twice the CPU clock speed (3579545.454545 Hz), and dividing it by |
| 69 | 14915 (i.e., the divide-by-14915 counter is decremented on the rising AND |
| 70 | falling edge of the CPU's clock signal). |
| 71 | |
| 72 | |
| 73 | ************************ |
| 74 | * Sound hardware delay * |
| 75 | ************************ |
| 76 | |
| 77 | After resetting the 2A03, the first time any sound channel(s) length counter |
| 78 | contains a non-zero value (channel is enabled), there will be a 2048 CPU |
| 79 | clock cycle delay before any of the sound hardware is clocked. After the 2K |
| 80 | clock cycles go by, the NES sound hardware will be clocked normally. This |
| 81 | phenomenon only occurs prior to a system reset, and only occurs during the |
| 82 | first 2048 CPU clocks for any sound channel prior to a sound channel being |
| 83 | enabled. |
| 84 | |
| 85 | The information in regards to this delay is only provided to keep this |
| 86 | entire document persistently accurate on the 2A03's sound hardware, but may |
| 87 | not be 100% accurate in itself. I haven't done much tests on the behaviour |
| 88 | of this delay (mainly because I don't care, as I view it as a inconvenience |
| 89 | anyway), so that's why I believe there could be some inaccuracies. |
| 90 | |
| 91 | |
| 92 | ************************ |
| 93 | * Register Assignments * |
| 94 | ************************ |
| 95 | |
| 96 | The sound hardware internal to the 2A03 has been designated these special |
| 97 | memory addresses in the CPU's memory map. |
| 98 | |
| 99 | $4000-$4003 Square wave 1 |
| 100 | $4004-$4007 Square wave 2 (identical to the first, except for upward |
| 101 | frequency sweeps (see "sweep unit" section)) |
| 102 | $4008-$400B Triangle |
| 103 | $400C-$400F Noise |
| 104 | $4015 Channel enable / length counter status |
| 105 | |
| 106 | Note that $4015 is the only R/W register. All others are write only (attempt |
| 107 | to read them will most likely result in a returned 040H, due to heavy |
| 108 | capacitance on the NES's data bus). Reading a "write only" register, will |
| 109 | have no effect on the specific register, or channel. |
| 110 | |
| 111 | Every sound channel has 4 registers affiliated with it. The description of |
| 112 | the register sets are as follows: |
| 113 | |
| 114 | +----------------+ |
| 115 | | Register set 1 | |
| 116 | +----------------+ |
| 117 | |
| 118 | $4000(sq1)/$4004(sq2)/$400C(noise) bits |
| 119 | --------------------------------------- |
| 120 | 0-3 volume / envelope decay rate |
| 121 | 4 envelope decay disable |
| 122 | 5 length counter clock disable / envelope decay looping enable |
| 123 | 6-7 duty cycle type (unused on noise channel) |
| 124 | |
| 125 | $4008(tri) bits |
| 126 | --------------- |
| 127 | 0-6 linear counter load register |
| 128 | 7 length counter clock disable / linear counter start |
| 129 | |
| 130 | |
| 131 | +----------------+ |
| 132 | | Register set 2 | |
| 133 | +----------------+ |
| 134 | |
| 135 | $4001(sq1)/$4005(sq2) bits |
| 136 | -------------------------- |
| 137 | 0-2 right shift amount |
| 138 | 3 decrease / increase (1/0) wavelength |
| 139 | 4-6 sweep update rate |
| 140 | 7 sweep enable |
| 141 | |
| 142 | $4009(tri)/$400D(noise) bits |
| 143 | ---------------------------- |
| 144 | 0-7 unused |
| 145 | |
| 146 | |
| 147 | +----------------+ |
| 148 | | Register set 3 | |
| 149 | +----------------+ |
| 150 | |
| 151 | $4002(sq1)/$4006(sq2)/$400A(Tri) bits |
| 152 | ------------------------------------- |
| 153 | 0-7 8 LSB of wavelength |
| 154 | |
| 155 | $400E(noise) bits |
| 156 | ----------------- |
| 157 | 0-3 playback sample rate |
| 158 | 4-6 unused |
| 159 | 7 random number type generation |
| 160 | |
| 161 | |
| 162 | +----------------+ |
| 163 | | Register set 4 | |
| 164 | +----------------+ |
| 165 | |
| 166 | $4003(sq1)/$4007(sq2)/$400B(tri)/$400F(noise) bits |
| 167 | -------------------------------------------------- |
| 168 | 0-2 3 MS bits of wavelength (unused on noise channel) |
| 169 | 3-7 length counter load register |
| 170 | |
| 171 | |
| 172 | +--------------------------------+ |
| 173 | | length counter status register | |
| 174 | +--------------------------------+ |
| 175 | |
| 176 | $4015(read) |
| 177 | ----------- |
| 178 | 0 square wave channel 1 |
| 179 | 1 square wave channel 2 |
| 180 | 2 triangle wave channel |
| 181 | 3 noise channel |
| 182 | 4 DMC (see "DMC.TXT" for details) |
| 183 | 5-6 unused |
| 184 | 7 IRQ status of DMC (see "DMC.TXT" for details) |
| 185 | |
| 186 | |
| 187 | +-------------------------+ |
| 188 | | channel enable register | |
| 189 | +-------------------------+ |
| 190 | |
| 191 | $4015(write) |
| 192 | ------------ |
| 193 | 0 square wave channel 1 |
| 194 | 1 square wave channel 2 |
| 195 | 2 triangle wave channel |
| 196 | 3 noise channel |
| 197 | 4 DMC channel (see "DMC.TXT" for details) |
| 198 | 5-7 unused |
| 199 | |
| 200 | |
| 201 | ************************ |
| 202 | * Channel architecture * |
| 203 | ************************ |
| 204 | |
| 205 | This section will describe the internal components making up each individual |
| 206 | channel. Each component will then be described in full detail. |
| 207 | |
| 208 | Device Triangle Noise Square |
| 209 | ------ -------- ------ ------ |
| 210 | triangle step generator X |
| 211 | linear counter X |
| 212 | programmable timer X X X |
| 213 | length counter X X X |
| 214 | 4-bit DAC X X X |
| 215 | volume/envelope decay unit X X |
| 216 | sweep unit X |
| 217 | duty cycle generator X |
| 218 | wavelength converter X |
| 219 | random number generator X |
| 220 | |
| 221 | |
| 222 | +-------------------------+ |
| 223 | | Triangle step generator | |
| 224 | +-------------------------+ |
| 225 | |
| 226 | This is a 5-bit, single direction counter, and it is only used in the |
| 227 | triangle channel. Each of the 4 LSB outputs of the counter lead to one input |
| 228 | on a corresponding mutually exclusive XNOR gate. The 4 XNOR gates have been |
| 229 | strobed together, which results in the inverted representation of the 4 LSB |
| 230 | of the counter appearing on the outputs of the gates when the strobe is 0, |
| 231 | and a non-inverting action taking place when the strobe is 1. The strobe is |
| 232 | naturally connected to the MSB of the counter, which effectively produces on |
| 233 | the output of the XNOR gates a count sequence which reflects the scenario of |
| 234 | a near- ideal triangle step generator (D,E,F,F,E,D,...,2,1,0,0,1,2,...). At |
| 235 | this point, the outputs of the XNOR gates will be fed into the input of a |
| 236 | 4-bit DAC. |
| 237 | |
| 238 | This 5-bit counter will be halted whenever the Triangle channel's length or |
| 239 | linear counter contains a count of 0. This results in a "latching" |
| 240 | behaviour; the counter will NOT be reset to any definite state. |
| 241 | |
| 242 | On system reset, this counter is loaded with 0. |
| 243 | |
| 244 | The counter's clock input is connected directly to the terminal count output |
| 245 | pin of the 11-bit programmable timer in the triangle channel. As a result of |
| 246 | the 5-bit triangle step generator, the output triangle wave frequency will |
| 247 | be 32 times less than the frequency of the triangle channel's programmable |
| 248 | timer is set to generate. |
| 249 | |
| 250 | |
| 251 | +----------------+ |
| 252 | | Linear counter | |
| 253 | +----------------+ |
| 254 | |
| 255 | The linear counter is only found in the triangle channel. It is a 7-bit |
| 256 | presettable down counter, with a decoded output condition of 0 available |
| 257 | (not exactly the same as terminal count). Here's the bit assignments: |
| 258 | |
| 259 | $4008 bits |
| 260 | ---------- |
| 261 | 0-6 bits 0-6 of the linear counter load register (NOT the linear counter |
| 262 | itself) |
| 263 | 7 linear counter start |
| 264 | |
| 265 | The counter is clocked at 240 Hz (1/4 framerate), and the calculated length |
| 266 | in frames is 0.25*N, where N is the 7-bit loaded value. The counter is |
| 267 | always being clocked, except when 0 appears on the output of the counter. At |
| 268 | this point, the linear counter & triangle step counter clocks signals are |
| 269 | disabled, which results in both counters latching their current state (the |
| 270 | linear counter will stay at 0, and the triangle step counter will stop, and |
| 271 | the channel will be silenced due to this). |
| 272 | |
| 273 | The linear counter has 2 modes: load, and count. When the linear counter is |
| 274 | in load mode, it essentially becomes transparent (i.e. whatever value is |
| 275 | currently in, or being written to $4008, will appear on the output of the |
| 276 | counter). Because of this, no count action can occur in load mode. When the |
| 277 | mode changes from load to count, the counter will now latch the value |
| 278 | currently in it, and start counting down from there. In the count mode, the |
| 279 | current value of $4008 is ignored by the counter (but still retained in |
| 280 | $4008). Described below is how the mode of the linear counter is set: |
| 281 | |
| 282 | Writes to $400B |
| 283 | --------------- |
| 284 | cur mode |
| 285 | --- ---- |
| 286 | 1 load |
| 287 | 0 load (during the write cycle), count |
| 288 | |
| 289 | Cur is the current state of the MSB of $4008. |
| 290 | |
| 291 | Writes to $4008 |
| 292 | --------------- |
| 293 | old new mode |
| 294 | --- --- ---- |
| 295 | 0 X count |
| 296 | 1 0 no change (during the write cycle), count |
| 297 | 1 1 no change |
| 298 | |
| 299 | Old and new represent the state(s) of the MSB of $4008. Old is the value |
| 300 | being replaced in the MSB of $4008 on the write, and new is the value |
| 301 | replacing the old one. |
| 302 | |
| 303 | "no change" indicates that the mode of the linear counter will not change |
| 304 | from the last. |
| 305 | |
| 306 | |
| 307 | +--------------------+ |
| 308 | | Programmable timer | |
| 309 | +--------------------+ |
| 310 | |
| 311 | The programmable timer is a 11-bit presettable down counter, and is found in |
| 312 | the square, triangle, and noise channel(s). The bit assignments are as |
| 313 | follows: |
| 314 | |
| 315 | $4002(sq1)/$4006(sq2)/$400A(Tri) bits |
| 316 | ------------------------------------- |
| 317 | 0-7 represent bits 0-7 of the 11-bit wavelength |
| 318 | |
| 319 | $4003(sq1)/$4007(sq2)/$400B(Tri) bits |
| 320 | ------------------------------------- |
| 321 | 0-2 represent bits 8-A of the 11-bit wavelength |
| 322 | |
| 323 | Note that on the noise channel, the 11 bits are not available directly. See |
| 324 | the wavelength converter section, for more details. |
| 325 | |
| 326 | The counter has automatic syncronous reloading upon terminal count |
| 327 | (count=0), therefore the counter will count for N+1 (N is the 11-bit loaded |
| 328 | value) clock cycles before arriving at terminal count, and reloading. This |
| 329 | counter will typically be clocked at the 2A03's internal 6502 speed (1.79 |
| 330 | MHz), and produces an output frequency of 1.79 MHz/(N+1). The terminal |
| 331 | count's output spike length is typically no longer than half a CPU clock. |
| 332 | The TC signal will then be fed to the appropriate device for the particular |
| 333 | sound channel (for square, this terminal count spike will lead to the duty |
| 334 | cycle generator. For the triangle, the spike will be fed to the triangle |
| 335 | step generator. For noise, this signal will go to the random number |
| 336 | generator unit). |
| 337 | |
| 338 | |
| 339 | +----------------+ |
| 340 | | Length counter | |
| 341 | +----------------+ |
| 342 | |
| 343 | The length counter is found in all sound channels. It is essentially a 7-bit |
| 344 | down counter, and is conditionally clocked at a frequency of 60 Hz. |
| 345 | |
| 346 | When the length counter arrives at a count of 0, the counter will be stopped |
| 347 | (stay on 0), and the appropriate channel will be silenced. |
| 348 | |
| 349 | The length counter clock disable bit, found in all the channels, can also be |
| 350 | used to halt the count sequence of the length counter for the appropriate |
| 351 | channel, by writing a 1 out to it. A 0 condition will permit counting |
| 352 | (unless of course, the counter's current count = 0). Location(s) of the |
| 353 | length counter clock disable bit: |
| 354 | |
| 355 | $4000(sq1)/$4004(sq2)/$400C(noise) bits |
| 356 | --------------------------------------- |
| 357 | 5 length counter clock disable |
| 358 | |
| 359 | $4008(tri) bits |
| 360 | --------------- |
| 361 | 7 length counter clock disable |
| 362 | |
| 363 | To load the length counter with a specified count, a write must be made out |
| 364 | to the length register. Location(s) of the length register: |
| 365 | |
| 366 | $4003(sq1)/$4007(sq2)/$400B(tri)/$400F(noise) bits |
| 367 | -------------------------------------------------- |
| 368 | 3-7 length |
| 369 | |
| 370 | The 5-bit length value written, determines what 7-bit value the length |
| 371 | counter will start counting from. A conversion table here will show how the |
| 372 | values are translated. |
| 373 | |
| 374 | +-----------------------+ |
| 375 | | bit3=0 | |
| 376 | +-------+---------------+ |
| 377 | | |frames | |
| 378 | |bits +-------+-------+ |
| 379 | |4-6 |bit7=0 |bit7=1 | |
| 380 | +-------+-------+-------+ |
| 381 | |0 |05 |06 | |
| 382 | |1 |0A |0C | |
| 383 | |2 |14 |18 | |
| 384 | |3 |28 |30 | |
| 385 | |4 |50 |60 | |
| 386 | |5 |1E |24 | |
| 387 | |6 |07 |08 | |
| 388 | |7 |0E |10 | |
| 389 | +-------+-------+-------+ |
| 390 | |
| 391 | +---------------+ |
| 392 | | bit3=1 | |
| 393 | +-------+-------+ |
| 394 | |bits | | |
| 395 | |4-7 |frames | |
| 396 | +-------+-------+ |
| 397 | |0 |7F | |
| 398 | |1 |01 | |
| 399 | |2 |02 | |
| 400 | |3 |03 | |
| 401 | |4 |04 | |
| 402 | |5 |05 | |
| 403 | |6 |06 | |
| 404 | |7 |07 | |
| 405 | |8 |08 | |
| 406 | |9 |09 | |
| 407 | |A |0A | |
| 408 | |B |0B | |
| 409 | |C |0C | |
| 410 | |D |0D | |
| 411 | |E |0E | |
| 412 | |F |0F | |
| 413 | +-------+-------+ |
| 414 | |
| 415 | The length counter's real-time status for each channel can be attained. A 0 |
| 416 | is returned for a zero count status in the length counter (channel's sound |
| 417 | is disabled), and 1 for a non-zero status. Here's the bit description of the |
| 418 | length counter status register: |
| 419 | |
| 420 | $4015(read) |
| 421 | ----------- |
| 422 | 0 length counter status of square wave channel 1 |
| 423 | 1 length counter status of square wave channel 2 |
| 424 | 2 length counter status of triangle wave channel |
| 425 | 3 length counter status of noise channel |
| 426 | 4 length counter status of DMC (see "DMC.TXT" for details) |
| 427 | 5-6 unused |
| 428 | 7 IRQ status of DMC (see "DMC.TXT" for details) |
| 429 | |
| 430 | Writing a 0 to the channel enable register will force the length counters to |
| 431 | always contain a count equal to 0, which renders that specific channel |
| 432 | disabled (as if it doesn't exist). Writing a 1 to the channel enable |
| 433 | register disables the forced length counter value of 0, but will not change |
| 434 | the count itself (it will still be whatever it was prior to the writing of |
| 435 | 1). |
| 436 | |
| 437 | Bit description of the channel enable register: |
| 438 | |
| 439 | $4015(write) |
| 440 | ------------ |
| 441 | 0 enable square wave channel 1 |
| 442 | 1 enable square wave channel 2 |
| 443 | 2 enable triangle wave channel |
| 444 | 3 enable noise channel |
| 445 | 4 enable DMC channel (see "DMC.TXT" for details) |
| 446 | 5-7 unused |
| 447 | |
| 448 | Note that all 5 used bits in this register will be set to 0 upon system |
| 449 | reset. |
| 450 | |
| 451 | |
| 452 | +-----------+ |
| 453 | | 4-bit DAC | |
| 454 | +-----------+ |
| 455 | |
| 456 | This is just a standard 4-bit DAC with 16 steps of output voltage |
| 457 | resolution, and is used by all 4 sound channels. |
| 458 | |
| 459 | On the 2A03, square wave 1 & 2 are mixed together, and are available via pin |
| 460 | 1. Triangle & noise are available on pin 2. These analog outputs require a |
| 461 | negative current source, to attain linear symmetry on the various output |
| 462 | voltage levels generated by the channel(s) (moreover, to get the sound to be |
| 463 | audible). Since the NES just uses external 100 ohm pull-down resistors, this |
| 464 | results in the output waveforms being of very small amplitude, but with |
| 465 | minimal linearity asymmetry. |
| 466 | |
| 467 | |
| 468 | +------------------------------+ |
| 469 | | Volume / envelope decay unit | |
| 470 | +------------------------------+ |
| 471 | |
| 472 | The volume / envelope decay hardware is found only in the square wave and |
| 473 | noise channels. |
| 474 | |
| 475 | $4000(sq1)/$4004(sq2)/$400C(noise) |
| 476 | ---------------------------------- |
| 477 | 0-3 volume / envelope decay rate |
| 478 | 4 envelope decay disable |
| 479 | 5 envelope decay looping enable |
| 480 | |
| 481 | When the envelope decay disable bit (bit 4) is set (1), the current volume |
| 482 | value (bits 0-3) is sent directly to the channel's DAC. However, depending |
| 483 | on certain conditions, this 4-bit volume value will be ignored, and a value |
| 484 | of 0 will be sent to the DAC instead. This means that while the channel is |
| 485 | enabled (producing sound), the output of the channel (what you'll hear from |
| 486 | the DAC) will either be the 4-bit volume value, or 0. This also means that a |
| 487 | 4-bit volume value of 0 will result in no audible sound. These conditions |
| 488 | are as follows: |
| 489 | |
| 490 | - When hardware in the channel wants to disable it's sound output (like the |
| 491 | length counter, or sweep unit (square channels only)). |
| 492 | |
| 493 | - On the negative portion of the output frequency signal coming from the |
| 494 | duty cycle / random number generator hardware (square wave channel / noise |
| 495 | channel). |
| 496 | |
| 497 | When the envelope decay disable bit is cleared, bits 0-3 now control the |
| 498 | envelope decay rate, and an internal 4-bit down counter (hereon the envelope |
| 499 | decay counter) now controls the channel's volume level. "Envelope decay" is |
| 500 | used to describe the action of the channel's audio output volume starting |
| 501 | from a certain value, and decreasing by 1 at a fixed (linear) rate (which |
| 502 | produces a "fade-out" sounding effect). This fixed decrement rate is |
| 503 | controlled by the envelope decay rate (bits 0-3). The calculated decrement |
| 504 | rate is 240Hz/(N+1), where N is any value between $0-$F. |
| 505 | |
| 506 | When the channel's envelope decay counter reaches a value of 0, depending on |
| 507 | the status of the envelope decay looping enable bit (bit 5, which is shared |
| 508 | with the length counter's clock disable bit), 2 different things will |
| 509 | happen: |
| 510 | |
| 511 | bit 5 action |
| 512 | ----- ------ |
| 513 | 0 The envelope decay count will stay at 0 (channel silenced). |
| 514 | 1 The envelope decay count will wrap-around to $F (upon the next clock |
| 515 | cycle). The envelope decay counter will then continue to count down |
| 516 | normally. |
| 517 | |
| 518 | Only a write out to $4003/$4007/$400F will reset the current envelope decay |
| 519 | counter to a known state (to $F, the maximum volume level) for the |
| 520 | appropriate channel's envelope decay hardware. Otherwise, the envelope decay |
| 521 | counter is always counting down (by 1) at the frequency currently contained |
| 522 | in the volume / envelope decay rate bits (even when envelope decays are |
| 523 | disabled (setting bit 4)), except when the envelope decay counter contains a |
| 524 | value of 0, and envelope decay looping (bit 5) is disabled (0). |
| 525 | |
| 526 | |
| 527 | +------------+ |
| 528 | | Sweep unit | |
| 529 | +------------+ |
| 530 | |
| 531 | The sweep unit is only found in the square wave channels. The controls for |
| 532 | the sweep unit have been mapped in at $4001 for square 1, and $4005 for |
| 533 | square 2. |
| 534 | |
| 535 | The controls |
| 536 | ------------ |
| 537 | Bit 7 when this bit is set (1), sweeping is active. This results in |
| 538 | real-time increasing or decreasing of the the current wavelength value (the |
| 539 | audible frequency will decrease or increase, respectively). The wavelength |
| 540 | value in $4002/3 ($4006/7) is constantly read & updated by the sweep. |
| 541 | Modifying the contents of $4002/3 will be immediately audible, and will |
| 542 | result in the sweep now starting from this new wavelength value. |
| 543 | |
| 544 | Bits 6-4 These 3 bits represent the sweep refresh rate, or the frequency at |
| 545 | which $4002/3 is updated with the new calculated wavelength. The refresh |
| 546 | rate frequency is 120Hz/(N+1), where N is the value written, between 0 and |
| 547 | 7. |
| 548 | |
| 549 | Bit 3 This bit controls the sweep mode. When this bit is set (1), sweeps |
| 550 | will decrease the current wavelength value, as a 0 will increase the current |
| 551 | wavelength. |
| 552 | |
| 553 | Bits 2-0 These bits control the right shift amount of the new calculated |
| 554 | sweep update wavelength. Code that shows how the sweep unit calculates a new |
| 555 | sweep wavelength is as follows: |
| 556 | |
| 557 | bit 3 |
| 558 | ----- |
| 559 | 0 New = Wavelength + (Wavelength >> N) |
| 560 | 1 New = Wavelength - (Wavelength >> N) (minus an additional 1, if using |
| 561 | square wave channel 1) |
| 562 | |
| 563 | where N is the the shift right value, between 0-7. |
| 564 | |
| 565 | Note that in decrease mode, for subtracting the 2 values: |
| 566 | 1's compliment (NOT) is being used for square wave channel 1 |
| 567 | 2's compliment (NEG) is being used for square wave channel 2 |
| 568 | |
| 569 | This information is currently the only known difference between the 2 square |
| 570 | wave channels. |
| 571 | |
| 572 | On each sweep refresh clock, the Wavelength register will be updated with |
| 573 | the New value, but only if all 3 of these conditions are met: |
| 574 | |
| 575 | - bit 7 is set (sweeping enabled) |
| 576 | - the shift value (which is N in the formula) does not equal to 0 |
| 577 | - the channel's length counter contains a non-zero value |
| 578 | |
| 579 | Notes |
| 580 | ----- |
| 581 | There are certain conditions that will cause the sweep unit to silence the |
| 582 | channel, and halt the sweep refresh clock (which effectively stops sweep |
| 583 | action, if any). Note that these conditions pertain regardless of any sweep |
| 584 | refresh rate values, or if sweeping is enabled/disabled (via bit 7). |
| 585 | |
| 586 | - an 11-bit wavelength value less than $008 will cause this condition |
| 587 | - if the sweep unit is currently set to increase mode, the New calculated |
| 588 | wavelength value will always be tested to see if a carry (bit $B) was |
| 589 | generated or not (if sweeping is enabled, this carry will be examined before |
| 590 | the Wavelength register is updated) from the shift addition calculation. If |
| 591 | carry equals 1, the channel is silenced, and sweep action is halted. |
| 592 | |
| 593 | |
| 594 | +----------------------+ |
| 595 | | Duty cycle generator | |
| 596 | +----------------------+ |
| 597 | |
| 598 | The duty cycle generator takes the fequency produced from the 11-bit |
| 599 | programmable timer, and uses a 4 bit counter to produce 4 types of duty |
| 600 | cycles. The output frequency is then 1/16 that of the programmable timer. |
| 601 | The duty cycle hardware is only found in the square wave channels. The bit |
| 602 | assignments are as follows: |
| 603 | |
| 604 | $4000(sq1)/$4004(sq2) |
| 605 | --------------------- |
| 606 | 6-7 Duty cycle type |
| 607 | |
| 608 | duty (positive/negative) |
| 609 | val in clock cycles |
| 610 | --- --------------- |
| 611 | 00 2/14 |
| 612 | 01 4/12 |
| 613 | 10 8/ 8 |
| 614 | 11 12/ 4 |
| 615 | |
| 616 | Where val represents bits 6-7 of $4000/$4004. |
| 617 | |
| 618 | The output frequency at this point will now be fed to the volume/envelope |
| 619 | decay hardware. |
| 620 | |
| 621 | |
| 622 | +----------------------+ |
| 623 | | Wavelength converter | |
| 624 | +----------------------+ |
| 625 | |
| 626 | The wavelength converter is only used in the noise channel. It is used to |
| 627 | convert a given 4-bit value to an 11-bit wavelength, which then is sent to |
| 628 | the noise's own programmable timer. Here is the bit descriptions: |
| 629 | |
| 630 | $400E bits |
| 631 | ---------- |
| 632 | 0-3 The 4-bit value to be converted |
| 633 | |
| 634 | Below is a conversion chart that shows what 4-bit value will represent the |
| 635 | 11-bit wavelength to be fed to the channel's programmable timer: |
| 636 | |
| 637 | value octave scale CPU clock cycles (11-bit wavelength+1) |
| 638 | ----- ------ ----- -------------------------------------- |
| 639 | 0 15 A 002 |
| 640 | 1 14 A 004 |
| 641 | 2 13 A 008 |
| 642 | 3 12 A 010 |
| 643 | 4 11 A 020 |
| 644 | 5 11 D 030 |
| 645 | 6 10 A 040 |
| 646 | 7 10 F 050 |
| 647 | 8 10 C 065 |
| 648 | 9 9 A 07F |
| 649 | A 9 D 0BE |
| 650 | B 8 A 0FE |
| 651 | C 8 D 17D |
| 652 | D 7 A 1FC |
| 653 | E 6 A 3F9 |
| 654 | F 5 A 7F2 |
| 655 | |
| 656 | Octave and scale information is provided for the music enthusiast programmer |
| 657 | who is more familiar with notes than clock cycles. |
| 658 | |
| 659 | |
| 660 | +-------------------------+ |
| 661 | | Random number generator | |
| 662 | +-------------------------+ |
| 663 | |
| 664 | The noise channel has a 1-bit pseudo-random number generator. It's based on |
| 665 | a 15-bit shift register, and an exclusive or gate. The generator can produce |
| 666 | two types of random number sequences: long, and short. The long sequence |
| 667 | generates 32,767-bit long number patterns. The short sequence generates |
| 668 | 93-bit long number patterns. The 93-bit mode will generally produce higher |
| 669 | sounding playback frequencys on the channel. Here is the bit that controls |
| 670 | the mode: |
| 671 | |
| 672 | $400E bits |
| 673 | ---------- |
| 674 | 7 mode |
| 675 | |
| 676 | If mode=0, then 32,767-bit long number sequences will be produced (32K |
| 677 | mode), otherwise 93-bit long number sequences will be produced (93-bit |
| 678 | mode). |
| 679 | |
| 680 | The following diagram shows where the XOR taps are taken off the shift |
| 681 | register to produce the 1-bit pseudo-random number sequences for each mode. |
| 682 | |
| 683 | mode <----- |
| 684 | ---- EDCBA9876543210 |
| 685 | 32K ** |
| 686 | 93-bit * * |
| 687 | |
| 688 | The current result of the XOR will be transferred into bit position 0 of the |
| 689 | SR, upon the next shift cycle. The 1-bit random number output is taken from |
| 690 | pin E, is inverted, then is sent to the volume/envelope decay hardware for |
| 691 | the noise channel. The shift register is shifted upon recieving 2 clock |
| 692 | pulses from the programmable timer (the shift frequency will be half that of |
| 693 | the frequency from the programmable timer (one octave lower)). |
| 694 | |
| 695 | On system reset, this shift register is loaded with a value of 1. |
| 696 | |
| 697 | |