2 // This file is part of the Cyclone 68000 Emulator
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4 // Copyright (c) 2004,2011 FinalDave (emudave (at) gmail.com)
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5 // Copyright (c) 2005-2011 GraÅžvydas "notaz" Ignotas (notasas (at) gmail.com)
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7 // This code is licensed under the GNU General Public License version 2.0 and the MAME License.
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8 // You can choose the license that has the most advantages for you.
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10 // SVN repository can be found at http://code.google.com/p/cyclone68000/
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15 // Pack our flags into r1, in SR/CCR register format
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17 void OpFlagsToReg(int high)
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19 ot(" ldr r0,[r7,#0x4c] ;@ X bit\n");
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20 ot(" mov r1,r10,lsr #28 ;@ ____NZCV\n");
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21 ot(" eor r2,r1,r1,ror #1 ;@ Bit 0=C^V\n");
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22 ot(" tst r2,#1 ;@ 1 if C!=V\n");
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23 ot(" eorne r1,r1,#3 ;@ ____NZVC\n");
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25 if (high) ot(" ldrb r2,[r7,#0x44] ;@ Include SR high\n");
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26 ot(" and r0,r0,#0x20000000\n");
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27 ot(" orr r1,r1,r0,lsr #25 ;@ ___XNZVC\n");
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28 if (high) ot(" orr r1,r1,r2,lsl #8\n");
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32 // Convert SR/CRR register in r0 to our flags
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34 void OpRegToFlags(int high, int srh_reg)
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36 ot(" eor r1,r0,r0,ror #1 ;@ Bit 0=C^V\n");
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37 ot(" mov r2,r0,lsl #25\n");
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38 ot(" tst r1,#1 ;@ 1 if C!=V\n");
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39 ot(" eorne r0,r0,#3 ;@ ___XNZCV\n");
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40 ot(" str r2,[r7,#0x4c] ;@ Store X bit\n");
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41 ot(" mov r10,r0,lsl #28 ;@ r10=NZCV...\n");
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45 int mask=EMULATE_TRACE?0xa7:0x27;
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46 ot(" mov r%i,r0,ror #8\n",srh_reg);
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47 ot(" and r%i,r%i,#0x%02x ;@ only take defined bits\n",srh_reg,srh_reg,mask);
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48 ot(" strb r%i,[r7,#0x44] ;@ Store SR high\n",srh_reg);
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55 ot(";@ ----------\n");
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56 ot(";@ tried execute privileged instruction in user mode\n");
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57 ot("WrongPrivilegeMode%s\n",ms?"":":");
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58 #if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO
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59 ot(" ldr r1,[r7,#0x58]\n");
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60 ot(" sub r4,r4,#2 ;@ last opcode wasn't executed - go back\n");
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61 ot(" orr r1,r1,#4 ;@ set activity bit: 'not processing instruction'\n");
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62 ot(" str r1,[r7,#0x58]\n");
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64 ot(" sub r4,r4,#2 ;@ last opcode wasn't executed - go back\n");
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66 ot(" mov r0,#8 ;@ privilege violation\n");
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67 ot(" bl Exception\n");
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72 // does OSP and A7 swapping if needed
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73 // new or old SR (not the one already in [r7,#0x44]) should be passed in r11
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74 // uses srh from srh_reg (loads if < 0), trashes r0,r11
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75 void SuperChange(int op,int srh_reg)
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77 ot(";@ A7 <-> OSP?\n");
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79 ot(" ldr r0,[r7,#0x44] ;@ Get other SR high\n");
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82 ot(" eor r0,r%i,r11\n",srh_reg);
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83 ot(" tst r0,#0x20\n");
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84 ot(" beq no_sp_swap%.4x\n",op);
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85 ot(" ;@ swap OSP and A7:\n");
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86 ot(" ldr r11,[r7,#0x3C] ;@ Get A7\n");
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87 ot(" ldr r0, [r7,#0x48] ;@ Get OSP\n");
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88 ot(" str r11,[r7,#0x48]\n");
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89 ot(" str r0, [r7,#0x3C]\n");
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90 ot("no_sp_swap%.4x%s\n", op, ms?"":":");
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95 // --------------------- Opcodes 0x1000+ ---------------------
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96 // Emit a Move opcode, 00xxdddd ddssssss
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103 // Get source and target EA
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105 tea =(op&0x01c0)>>3;
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106 tea|=(op&0x0e00)>>9;
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108 if (tea>=8 && tea<0x10) movea=1;
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110 // Find size extension
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114 case 0x1000: size=0; break;
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115 case 0x3000: size=1; break;
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116 case 0x2000: size=2; break;
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119 if (size<1 && (movea || EaAn(sea))) return 1; // move.b An,* and movea.b * are invalid
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121 // See if we can do this opcode:
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122 if (EaCanRead (sea,size)==0) return 1;
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123 if (EaCanWrite(tea )==0) return 1;
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125 use=OpBase(op,size);
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126 if (tea<0x38) use&=~0x0e00; // Use same handler for register ?0-7
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128 if (tea==0x1f || tea==0x27) use|=0x0e00; // Specific handler for (a7)+ and -(a7)
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130 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
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132 OpStart(op,sea,tea); Cycles=4;
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136 EaCalcRead(-1,0,sea,size,0x003f);
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137 ot(" adds r1,r0,#0 ;@ Defines NZ, clears CV\n");
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138 ot(" mrs r10,cpsr ;@ r10=NZCV flags\n");
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143 EaCalcRead(-1,1,sea,size,0x003f);
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144 size=2; // movea always expands to 32-bits
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147 eawrite_check_addrerr=1;
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149 if ((tea&0x38)==0x20 && size==2) { // -(An)
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150 EaCalc (8,0x0e00,tea,size,0,0);
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151 ot(" mov r11,r1\n");
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152 ot(" add r0,r8,#2\n");
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153 EaWrite(0, 1,tea,1,0x0e00,0,0);
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154 EaWrite(8, 11,tea,1,0x0e00,1);
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159 EaCalc (0,0x0e00,tea,size,0,0);
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160 EaWrite(0, 1,tea,size,0x0e00,0,0);
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163 #if CYCLONE_FOR_GENESIS && !MEMHANDLERS_CHANGE_CYCLES
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164 // this is a bit hacky (device handlers might modify cycles)
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165 if (tea==0x39||((0x10<=tea&&tea<0x30)&&size>=1))
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166 ot(" ldr r5,[r7,#0x5c] ;@ Load Cycles\n");
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169 if((tea&0x38)==0x20) Cycles-=2; // less cycles when dest is -(An)
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175 // --------------------- Opcodes 0x41c0+ ---------------------
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176 // Emit an Lea opcode, 0100nnn1 11aaaaaa
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183 tea=(op&0x0e00)>>9; tea|=8;
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185 if (EaCanRead(sea,-1)==0) return 1; // See if we can do this opcode
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188 use&=~0x0e00; // Also use 1 handler for target ?0-7
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189 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
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191 OpStart(op,sea,tea);
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193 eawrite_check_addrerr=1;
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194 EaCalc (1,0x003f,sea,0); // Lea
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195 EaCalc (0,0x0e00,tea,2);
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196 EaWrite(0, 1,tea,2,0x0e00);
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198 Cycles=Ea_add_ns(g_lea_cycle_table,sea);
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205 // --------------------- Opcodes 0x40c0+ ---------------------
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206 // Move SR opcode, 01000tt0 11aaaaaa move SR
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207 int OpMoveSr(int op)
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212 type=(op>>9)&3; // from SR, from CCR, to CCR, to SR
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215 if(EaAn(ea)) return 1; // can't use An regs
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220 if (EaCanWrite(ea)==0) return 1; // See if we can do this opcode:
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224 return 1; // no such op in 68000
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227 if (EaCanRead(ea,size)==0) return 1; // See if we can do this opcode:
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231 use=OpBase(op,size);
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232 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
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234 // 68000 model allows reading whole SR in user mode (but newer models don't)
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235 OpStart(op,ea,0,0,type==3);
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237 if (type==0) Cycles=(ea>=8)?8:6;
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239 if (type==0 || type==1)
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241 eawrite_check_addrerr=1;
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242 OpFlagsToReg(type==0);
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243 EaCalc (0,0x003f,ea,size,0,0);
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244 EaWrite(0, 1,ea,size,0x003f,0,0);
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247 if (type==2 || type==3)
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249 EaCalcReadNoSE(-1,0,ea,size,0x003f);
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250 OpRegToFlags(type==3,1);
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253 opend_check_interrupt = 1;
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254 opend_check_trace = 1;
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266 // Ori/Andi/Eori $nnnn,sr 0000t0t0 01111100
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267 int OpArithSr(int op)
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271 int sr_mask=EMULATE_TRACE?0xa7:0x27;
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273 type=(op>>9)&5; if (type==4) return 1;
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274 size=(op>>6)&1; // ccr or sr?
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277 use=OpBase(op,size);
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278 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
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280 OpStart(op,ea,0,0,size!=0); Cycles=16;
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282 EaCalcRead(-1,0,ea,size,0x003f);
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284 ot(" eor r1,r0,r0,ror #1 ;@ Bit 0=C^V\n");
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285 ot(" tst r1,#1 ;@ 1 if C!=V\n");
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286 ot(" eorne r0,r0,#3 ;@ ___XNZCV\n");
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287 ot(" ldr r2,[r7,#0x4c] ;@ Load old X bit\n");
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289 // note: old srh is already in r11 (done by OpStart)
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291 ot(" orr r10,r10,r0,lsl #28\n");
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292 ot(" orr r2,r2,r0,lsl #25 ;@ X bit\n");
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294 ot(" orr r1,r11,r0,lsr #8\n");
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295 ot(" and r1,r1,#0x%02x ;@ mask-out unused bits\n",sr_mask);
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299 ot(" and r10,r10,r0,lsl #28\n");
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300 ot(" and r2,r2,r0,lsl #25 ;@ X bit\n");
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302 ot(" and r1,r11,r0,lsr #8\n");
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305 ot(" eor r10,r10,r0,lsl #28\n");
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306 ot(" eor r2,r2,r0,lsl #25 ;@ X bit\n");
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308 ot(" eor r1,r11,r0,lsr #8\n");
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309 ot(" and r1,r1,#0x%02x ;@ mask-out unused bits\n",sr_mask);
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313 ot(" str r2,[r7,#0x4c] ;@ Save X bit\n");
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315 ot(" strb r1,[r7,#0x44]\n");
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318 // we can't enter supervisor mode, nor unmask irqs just by using OR
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319 if (size!=0 && type!=0) {
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322 opend_check_interrupt = 1;
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324 // also can't set trace bit with AND
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325 if (size!=0 && type!=1)
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326 opend_check_trace = 1;
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333 // --------------------- Opcodes 0x4850+ ---------------------
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334 // Emit an Pea opcode, 01001000 01aaaaaa
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340 ea=op&0x003f; if (ea<0x10) return 1; // Swap opcode
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341 if (EaCanRead(ea,-1)==0) return 1; // See if we can do this opcode:
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344 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
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348 ot(" ldr r11,[r7,#0x3c]\n");
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349 EaCalc (1,0x003f, ea,0);
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351 ot(" sub r0,r11,#4 ;@ Predecrement A7\n");
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352 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");
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354 MemHandler(1,2); // Write 32-bit
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357 Cycles=6+Ea_add_ns(g_pea_cycle_table,ea);
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364 // --------------------- Opcodes 0x4880+ ---------------------
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365 // Emit a Movem opcode, 01001d00 1xeeeeee regmask
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366 int OpMovem(int op)
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368 int size=0,ea=0,cea=0,dir=0;
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369 int use=0,decr=0,change=0;
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371 size=((op>>6)&1)+1; // word, long
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373 dir=(op>>10)&1; // Direction (1==ea2reg)
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376 if (ea<0x10 || ea>0x3b || (ea&0x38)==0x20) return 1; // Invalid EA
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378 if (ea<0x10 || ea>0x39 || (ea&0x38)==0x18) return 1;
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381 if ((ea&0x38)==0x18 || (ea&0x38)==0x20) change=1;
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382 if ((ea&0x38)==0x20) decr=1; // -(An), bitfield is decr
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384 cea=ea; if (change) cea=0x10;
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386 use=OpBase(op,size);
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387 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
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389 OpStart(op,ea,0,1);
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391 ot(" ldrh r11,[r4],#2 ;@ r11=register mask\n");
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393 ot(";@ Get the address into r6:\n");
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394 EaCalc(6,0x003f,cea,size);
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396 #if !MEMHANDLERS_NEED_PREV_PC
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397 // must save PC, need a spare register
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398 ot(" str r4,[r7,#0x40] ;@ Save PC\n");
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401 ot(";@ r4=Register Index*4:\n");
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402 if (decr) ot(" mov r4,#0x40 ;@ order reversed for -(An)\n");
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403 else ot(" mov r4,#-4\n");
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406 ot(" tst r11,r11\n"); // sanity check
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407 ot(" beq NoRegs%.4x\n",op);
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409 #if EMULATE_ADDRESS_ERRORS_IO
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411 ot(" tst r6,#1 ;@ address error?\n");
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412 ot(" movne r0,r6\n");
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413 ot(" bne ExceptionAddressError_%c_data\n",dir?'r':'w');
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417 ot("Movemloop%.4x%s\n",op, ms?"":":");
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418 ot(" add r4,r4,#%d ;@ r4=Next Register\n",decr?-4:4);
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419 ot(" movs r11,r11,lsr #1\n");
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420 ot(" bcc Movemloop%.4x\n",op);
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423 if (decr) ot(" sub r6,r6,#%d ;@ Pre-decrement address\n",1<<size);
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427 ot(" ;@ Copy memory to register:\n",1<<size);
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428 earead_check_addrerr=0; // already checked
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429 EaRead (6,0,ea,size,0x003f);
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430 ot(" str r0,[r7,r4] ;@ Save value into Dn/An\n");
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434 ot(" ;@ Copy register to memory:\n",1<<size);
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435 ot(" ldr r1,[r7,r4] ;@ Load value from Dn/An\n");
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437 if (decr && size==2) { // -(An)
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438 ot(" add r0,r6,#2\n");
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439 EaWrite(0,1,ea,1,0x003f,0,0);
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440 ot(" ldr r1,[r7,r4] ;@ Load value from Dn/An\n");
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441 ot(" mov r0,r6\n");
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442 EaWrite(0,1,ea,1,0x003f,1);
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447 EaWrite(6,1,ea,size,0x003f);
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451 if (decr==0) ot(" add r6,r6,#%d ;@ Post-increment address\n",1<<size);
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453 ot(" sub r5,r5,#%d ;@ Take some cycles\n",2<<size);
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454 ot(" tst r11,r11\n");
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455 ot(" bne Movemloop%.4x\n",op);
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460 ot(";@ Write back address:\n");
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461 EaCalc (0,0x0007,8|(ea&7),2);
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462 EaWrite(0, 6,8|(ea&7),2,0x0007);
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465 ot("NoRegs%.4x%s\n",op, ms?"":":");
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466 ot(" ldr r4,[r7,#0x40]\n");
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467 ot(" ldr r6,[r7,#0x54] ;@ restore Opcode Jump table\n");
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471 if (ea==0x3a) Cycles=16; // ($nn,PC)
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472 else if (ea==0x3b) Cycles=18; // ($nn,pc,Rn)
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478 Cycles+=Ea_add_ns(g_movem_cycle_table,ea);
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480 opend_op_changes_cycles = 1;
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487 // --------------------- Opcodes 0x4e60+ ---------------------
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488 // Emit a Move USP opcode, 01001110 0110dnnn move An to/from USP
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489 int OpMoveUsp(int op)
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493 dir=(op>>3)&1; // Direction
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494 use=op&~0x0007; // Use same opcode for all An
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496 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
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498 OpStart(op,0,0,0,1); Cycles=4;
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502 eawrite_check_addrerr=1;
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503 ot(" ldr r1,[r7,#0x48] ;@ Get from USP\n\n");
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504 EaCalc (0,0x000f,8,2,1);
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505 EaWrite(0, 1,8,2,0x000f,1);
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509 EaCalc (0,0x000f,8,2,1);
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510 EaRead (0, 0,8,2,0x000f,1);
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511 ot(" str r0,[r7,#0x48] ;@ Put in USP\n\n");
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519 // --------------------- Opcodes 0x7000+ ---------------------
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520 // Emit a Move Quick opcode, 0111nnn0 dddddddd moveq #dd,Dn
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521 int OpMoveq(int op)
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525 use=op&0xf100; // Use same opcode for all values
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526 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
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528 OpStart(op); Cycles=4;
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530 ot(" movs r0,r8,asl #24\n");
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531 ot(" and r1,r8,#0x0e00\n");
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532 ot(" mov r0,r0,asr #24 ;@ Sign extended Quick value\n");
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533 ot(" mrs r10,cpsr ;@ r10=NZ flags\n");
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534 ot(" str r0,[r7,r1,lsr #7] ;@ Store into Dn\n");
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542 // --------------------- Opcodes 0xc140+ ---------------------
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543 // Emit a Exchange opcode:
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544 // 1100ttt1 01000sss exg ds,dt
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545 // 1100ttt1 01001sss exg as,at
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546 // 1100ttt1 10001sss exg as,dt
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553 if (type!=0x40 && type!=0x48 && type!=0x88) return 1; // Not an exg opcode
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555 use=op&0xf1f8; // Use same opcode for all values
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556 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
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558 OpStart(op); Cycles=6;
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560 ot(" and r2,r8,#0x0e00 ;@ Find T register\n");
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561 ot(" and r3,r8,#0x000f ;@ Find S register\n");
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562 if (type==0x48) ot(" orr r2,r2,#0x1000 ;@ T is an address register\n");
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564 ot(" ldr r0,[r7,r2,lsr #7] ;@ Get T\n");
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565 ot(" ldr r1,[r7,r3,lsl #2] ;@ Get S\n");
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567 ot(" str r0,[r7,r3,lsl #2] ;@ T->S\n");
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568 ot(" str r1,[r7,r2,lsr #7] ;@ S->T\n");
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576 // ------------------------- movep -------------------------------
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577 // 0000ddd1 0z001sss
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578 // 0000sss1 1z001ddd (to mem)
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579 int OpMovep(int op)
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582 int size=1,use=0,dir,aadd=0;
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585 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler (for all dests, srcs)
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588 ea = (op&0x0007)|0x28;
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589 rea= (op&0x0e00)>>9;
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592 // Find size extension
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593 if(op&0x0040) size=2;
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597 if(dir) // reg to mem
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599 EaCalcReadNoSE(-1,11,rea,size,0x0e00);
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601 EaCalc(8,0x000f,ea,size);
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602 if(size==2) { // if operand is long
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603 ot(" mov r1,r11,lsr #24 ;@ first byte\n");
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604 EaWrite(8,1,ea,0,0x000f); // store first byte
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605 ot(" add r0,r8,#%i\n",(aadd+=2));
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606 ot(" mov r1,r11,lsr #16 ;@ second byte\n");
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607 EaWrite(0,1,ea,0,0x000f); // store second byte
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608 ot(" add r0,r8,#%i\n",(aadd+=2));
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610 ot(" mov r0,r8\n");
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612 ot(" mov r1,r11,lsr #8 ;@ first or third byte\n");
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613 EaWrite(0,1,ea,0,0x000f);
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614 ot(" add r0,r8,#%i\n",(aadd+=2));
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615 ot(" and r1,r11,#0xff\n");
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616 EaWrite(0,1,ea,0,0x000f);
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620 EaCalc(6,0x000f,ea,size,1);
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621 EaRead(6,11,ea,0,0x000f,1); // read first byte
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622 ot(" add r0,r6,#2\n");
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623 EaRead(0,1,ea,0,0x000f,1); // read second byte
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624 if(size==2) { // if operand is long
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625 ot(" orr r11,r11,r1,lsr #8 ;@ second byte\n");
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626 ot(" add r0,r6,#4\n");
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627 EaRead(0,1,ea,0,0x000f,1);
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628 ot(" orr r11,r11,r1,lsr #16 ;@ third byte\n");
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629 ot(" add r0,r6,#6\n");
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630 EaRead(0,1,ea,0,0x000f,1);
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631 ot(" orr r1,r11,r1,lsr #24 ;@ fourth byte\n");
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633 ot(" orr r1,r11,r1,lsr #8 ;@ second byte\n");
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635 // store the result
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636 EaCalc(0,0x0e00,rea,size,1);
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637 EaWrite(0,1,rea,size,0x0e00,1);
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638 ot(" ldr r6,[r7,#0x54]\n");
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641 Cycles=(size==2)?24:16;
\r
647 // Emit a Stop/Reset opcodes, 01001110 011100t0 imm
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648 int OpStopReset(int op)
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650 int type=(op>>1)&1; // stop/reset
\r
652 OpStart(op,0,0,0,1);
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655 // copy immediate to SR, stop the CPU and eat all remaining cycles.
\r
656 ot(" ldrh r0,[r4],#2 ;@ Fetch the immediate\n");
\r
662 ot(" ldr r0,[r7,#0x58]\n");
\r
663 ot(" mov r5,#0 ;@ eat cycles\n");
\r
664 ot(" orr r0,r0,#1 ;@ stopped\n");
\r
665 ot(" str r0,[r7,#0x58]\n");
\r
674 #if USE_RESET_CALLBACK
\r
675 ot(" str r4,[r7,#0x40] ;@ Save PC\n");
\r
676 ot(" mov r1,r10,lsr #28\n");
\r
677 ot(" strb r1,[r7,#0x46] ;@ Save Flags (NZCV)\n");
\r
678 ot(" str r5,[r7,#0x5c] ;@ Save Cycles\n");
\r
679 ot(" ldr r11,[r7,#0x90] ;@ ResetCallback\n");
\r
680 ot(" tst r11,r11\n");
\r
681 ot(" movne lr,pc\n");
\r
682 ot(" bxne r11 ;@ call ResetCallback if it is defined\n");
\r
683 ot(" ldrb r10,[r7,#0x46] ;@ r10 = Load Flags (NZCV)\n");
\r
684 ot(" ldr r5,[r7,#0x5c] ;@ Load Cycles\n");
\r
685 ot(" ldr r4,[r7,#0x40] ;@ Load PC\n");
\r
686 ot(" mov r10,r10,lsl #28\n");
\r