1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - assem_arm.c *
3 * Copyright (C) 2009-2011 Ari64 *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
21 extern int cycle_count;
22 extern int last_count;
24 extern int pending_exception;
25 extern int branch_target;
26 extern uint64_t readmem_dword;
28 extern precomp_instr fake_pc;
30 extern void *dynarec_local;
31 extern u_int memory_map[1048576];
32 extern u_int mini_ht[32][2];
33 extern u_int rounding_modes[4];
35 void indirect_jump_indexed();
48 void jump_vaddr_r10();
49 void jump_vaddr_r12();
51 const u_int jump_vaddr_reg[16] = {
69 void invalidate_addr_r0();
70 void invalidate_addr_r1();
71 void invalidate_addr_r2();
72 void invalidate_addr_r3();
73 void invalidate_addr_r4();
74 void invalidate_addr_r5();
75 void invalidate_addr_r6();
76 void invalidate_addr_r7();
77 void invalidate_addr_r8();
78 void invalidate_addr_r9();
79 void invalidate_addr_r10();
80 void invalidate_addr_r12();
82 const u_int invalidate_addr_reg[16] = {
83 (int)invalidate_addr_r0,
84 (int)invalidate_addr_r1,
85 (int)invalidate_addr_r2,
86 (int)invalidate_addr_r3,
87 (int)invalidate_addr_r4,
88 (int)invalidate_addr_r5,
89 (int)invalidate_addr_r6,
90 (int)invalidate_addr_r7,
91 (int)invalidate_addr_r8,
92 (int)invalidate_addr_r9,
93 (int)invalidate_addr_r10,
95 (int)invalidate_addr_r12,
102 unsigned int needs_clear_cache[1<<(TARGET_SIZE_2-17)];
106 void set_jump_target(int addr,u_int target)
108 u_char *ptr=(u_char *)addr;
109 u_int *ptr2=(u_int *)ptr;
111 assert((target-(u_int)ptr2-8)<1024);
113 assert((target&3)==0);
114 *ptr2=(*ptr2&0xFFFFF000)|((target-(u_int)ptr2-8)>>2)|0xF00;
115 //printf("target=%x addr=%x insn=%x\n",target,addr,*ptr2);
117 else if(ptr[3]==0x72) {
118 // generated by emit_jno_unlikely
119 if((target-(u_int)ptr2-8)<1024) {
121 assert((target&3)==0);
122 *ptr2=(*ptr2&0xFFFFF000)|((target-(u_int)ptr2-8)>>2)|0xF00;
124 else if((target-(u_int)ptr2-8)<4096&&!((target-(u_int)ptr2-8)&15)) {
126 assert((target&3)==0);
127 *ptr2=(*ptr2&0xFFFFF000)|((target-(u_int)ptr2-8)>>4)|0xE00;
129 else *ptr2=(0x7A000000)|(((target-(u_int)ptr2-8)<<6)>>8);
132 assert((ptr[3]&0x0e)==0xa);
133 *ptr2=(*ptr2&0xFF000000)|(((target-(u_int)ptr2-8)<<6)>>8);
137 // This optionally copies the instruction from the target of the branch into
138 // the space before the branch. Works, but the difference in speed is
139 // usually insignificant.
140 void set_jump_target_fillslot(int addr,u_int target,int copy)
142 u_char *ptr=(u_char *)addr;
143 u_int *ptr2=(u_int *)ptr;
144 assert(!copy||ptr2[-1]==0xe28dd000);
147 assert((target-(u_int)ptr2-8)<4096);
148 *ptr2=(*ptr2&0xFFFFF000)|(target-(u_int)ptr2-8);
151 assert((ptr[3]&0x0e)==0xa);
152 u_int target_insn=*(u_int *)target;
153 if((target_insn&0x0e100000)==0) { // ALU, no immediate, no flags
156 if((target_insn&0x0c100000)==0x04100000) { // Load
159 if(target_insn&0x08000000) {
163 ptr2[-1]=target_insn;
166 *ptr2=(*ptr2&0xFF000000)|(((target-(u_int)ptr2-8)<<6)>>8);
171 add_literal(int addr,int val)
173 assert(literalcount<sizeof(literals)/sizeof(literals[0]));
174 literals[literalcount][0]=addr;
175 literals[literalcount][1]=val;
179 void *kill_pointer(void *stub)
181 int *ptr=(int *)(stub+4);
182 assert((*ptr&0x0ff00000)==0x05900000);
183 u_int offset=*ptr&0xfff;
184 int **l_ptr=(void *)ptr+offset+8;
186 set_jump_target((int)i_ptr,(int)stub);
190 // find where external branch is liked to using addr of it's stub:
191 // get address that insn one after stub loads (dyna_linker arg1),
192 // treat it as a pointer to branch insn,
193 // return addr where that branch jumps to
194 int get_pointer(void *stub)
196 //printf("get_pointer(%x)\n",(int)stub);
197 int *ptr=(int *)(stub+4);
198 assert((*ptr&0x0fff0000)==0x059f0000);
199 u_int offset=*ptr&0xfff;
200 int **l_ptr=(void *)ptr+offset+8;
202 assert((*i_ptr&0x0f000000)==0x0a000000);
203 return (int)i_ptr+((*i_ptr<<8)>>6)+8;
206 // Find the "clean" entry point from a "dirty" entry point
207 // by skipping past the call to verify_code
208 u_int get_clean_addr(int addr)
210 int *ptr=(int *)addr;
216 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
217 assert((*ptr&0xFF000000)==0xeb000000); // bl instruction
219 if((*ptr&0xFF000000)==0xea000000) {
220 return (int)ptr+((*ptr<<8)>>6)+8; // follow jump
225 int verify_dirty(int addr)
227 u_int *ptr=(u_int *)addr;
229 // get from literal pool
230 assert((*ptr&0xFFFF0000)==0xe59f0000);
231 u_int offset=*ptr&0xfff;
232 u_int *l_ptr=(void *)ptr+offset+8;
233 u_int source=l_ptr[0];
239 assert((*ptr&0xFFF00000)==0xe3000000);
240 u_int source=(ptr[0]&0xFFF)+((ptr[0]>>4)&0xF000)+((ptr[2]<<16)&0xFFF0000)+((ptr[2]<<12)&0xF0000000);
241 u_int copy=(ptr[1]&0xFFF)+((ptr[1]>>4)&0xF000)+((ptr[3]<<16)&0xFFF0000)+((ptr[3]<<12)&0xF0000000);
242 u_int len=(ptr[4]&0xFFF)+((ptr[4]>>4)&0xF000);
245 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
246 assert((*ptr&0xFF000000)==0xeb000000); // bl instruction
247 u_int verifier=(int)ptr+((signed int)(*ptr<<8)>>6)+8; // get target of bl
248 if(verifier==(u_int)verify_code_vm||verifier==(u_int)verify_code_ds) {
249 unsigned int page=source>>12;
250 unsigned int map_value=memory_map[page];
251 if(map_value>=0x80000000) return 0;
252 while(page<((source+len-1)>>12)) {
253 if((memory_map[++page]<<2)!=(map_value<<2)) return 0;
255 source = source+(map_value<<2);
257 //printf("verify_dirty: %x %x %x\n",source,copy,len);
258 return !memcmp((void *)source,(void *)copy,len);
261 // This doesn't necessarily find all clean entry points, just
262 // guarantees that it's not dirty
263 int isclean(int addr)
266 int *ptr=((u_int *)addr)+4;
268 int *ptr=((u_int *)addr)+6;
270 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
271 if((*ptr&0xFF000000)!=0xeb000000) return 1; // bl instruction
272 if((int)ptr+((*ptr<<8)>>6)+8==(int)verify_code) return 0;
273 if((int)ptr+((*ptr<<8)>>6)+8==(int)verify_code_vm) return 0;
274 if((int)ptr+((*ptr<<8)>>6)+8==(int)verify_code_ds) return 0;
278 void get_bounds(int addr,u_int *start,u_int *end)
280 u_int *ptr=(u_int *)addr;
282 // get from literal pool
283 assert((*ptr&0xFFFF0000)==0xe59f0000);
284 u_int offset=*ptr&0xfff;
285 u_int *l_ptr=(void *)ptr+offset+8;
286 u_int source=l_ptr[0];
287 //u_int copy=l_ptr[1];
292 assert((*ptr&0xFFF00000)==0xe3000000);
293 u_int source=(ptr[0]&0xFFF)+((ptr[0]>>4)&0xF000)+((ptr[2]<<16)&0xFFF0000)+((ptr[2]<<12)&0xF0000000);
294 //u_int copy=(ptr[1]&0xFFF)+((ptr[1]>>4)&0xF000)+((ptr[3]<<16)&0xFFF0000)+((ptr[3]<<12)&0xF0000000);
295 u_int len=(ptr[4]&0xFFF)+((ptr[4]>>4)&0xF000);
298 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
299 assert((*ptr&0xFF000000)==0xeb000000); // bl instruction
300 u_int verifier=(int)ptr+((signed int)(*ptr<<8)>>6)+8; // get target of bl
301 if(verifier==(u_int)verify_code_vm||verifier==(u_int)verify_code_ds) {
302 if(memory_map[source>>12]>=0x80000000) source = 0;
303 else source = source+(memory_map[source>>12]<<2);
309 /* Register allocation */
311 // Note: registers are allocated clean (unmodified state)
312 // if you intend to modify the register, you must call dirty_reg().
313 void alloc_reg(struct regstat *cur,int i,signed char reg)
316 int preferred_reg = (reg&7);
317 if(reg==CCREG) preferred_reg=HOST_CCREG;
318 if(reg==PTEMP||reg==FTEMP) preferred_reg=12;
320 // Don't allocate unused registers
321 if((cur->u>>reg)&1) return;
323 // see if it's already allocated
324 for(hr=0;hr<HOST_REGS;hr++)
326 if(cur->regmap[hr]==reg) return;
329 // Keep the same mapping if the register was already allocated in a loop
330 preferred_reg = loop_reg(i,reg,preferred_reg);
332 // Try to allocate the preferred register
333 if(cur->regmap[preferred_reg]==-1) {
334 cur->regmap[preferred_reg]=reg;
335 cur->dirty&=~(1<<preferred_reg);
336 cur->isconst&=~(1<<preferred_reg);
339 r=cur->regmap[preferred_reg];
340 if(r<64&&((cur->u>>r)&1)) {
341 cur->regmap[preferred_reg]=reg;
342 cur->dirty&=~(1<<preferred_reg);
343 cur->isconst&=~(1<<preferred_reg);
346 if(r>=64&&((cur->uu>>(r&63))&1)) {
347 cur->regmap[preferred_reg]=reg;
348 cur->dirty&=~(1<<preferred_reg);
349 cur->isconst&=~(1<<preferred_reg);
353 // Clear any unneeded registers
354 // We try to keep the mapping consistent, if possible, because it
355 // makes branches easier (especially loops). So we try to allocate
356 // first (see above) before removing old mappings. If this is not
357 // possible then go ahead and clear out the registers that are no
359 for(hr=0;hr<HOST_REGS;hr++)
364 if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
368 if((cur->uu>>(r&63))&1) {cur->regmap[hr]=-1;break;}
372 // Try to allocate any available register, but prefer
373 // registers that have not been used recently.
375 for(hr=0;hr<HOST_REGS;hr++) {
376 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
377 if(regs[i-1].regmap[hr]!=rs1[i-1]&®s[i-1].regmap[hr]!=rs2[i-1]&®s[i-1].regmap[hr]!=rt1[i-1]&®s[i-1].regmap[hr]!=rt2[i-1]) {
379 cur->dirty&=~(1<<hr);
380 cur->isconst&=~(1<<hr);
386 // Try to allocate any available register
387 for(hr=0;hr<HOST_REGS;hr++) {
388 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
390 cur->dirty&=~(1<<hr);
391 cur->isconst&=~(1<<hr);
396 // Ok, now we have to evict someone
397 // Pick a register we hopefully won't need soon
398 u_char hsn[MAXREG+1];
399 memset(hsn,10,sizeof(hsn));
401 lsn(hsn,i,&preferred_reg);
402 //printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",cur->regmap[0],cur->regmap[1],cur->regmap[2],cur->regmap[3],cur->regmap[5],cur->regmap[6],cur->regmap[7]);
403 //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
405 // Don't evict the cycle count at entry points, otherwise the entry
406 // stub will have to write it.
407 if(bt[i]&&hsn[CCREG]>2) hsn[CCREG]=2;
408 if(i>1&&hsn[CCREG]>2&&(itype[i-2]==RJUMP||itype[i-2]==UJUMP||itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP)) hsn[CCREG]=2;
411 // Alloc preferred register if available
412 if(hsn[r=cur->regmap[preferred_reg]&63]==j) {
413 for(hr=0;hr<HOST_REGS;hr++) {
414 // Evict both parts of a 64-bit register
415 if((cur->regmap[hr]&63)==r) {
417 cur->dirty&=~(1<<hr);
418 cur->isconst&=~(1<<hr);
421 cur->regmap[preferred_reg]=reg;
424 for(r=1;r<=MAXREG;r++)
426 if(hsn[r]==j&&r!=rs1[i-1]&&r!=rs2[i-1]&&r!=rt1[i-1]&&r!=rt2[i-1]) {
427 for(hr=0;hr<HOST_REGS;hr++) {
428 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
429 if(cur->regmap[hr]==r+64) {
431 cur->dirty&=~(1<<hr);
432 cur->isconst&=~(1<<hr);
437 for(hr=0;hr<HOST_REGS;hr++) {
438 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
439 if(cur->regmap[hr]==r) {
441 cur->dirty&=~(1<<hr);
442 cur->isconst&=~(1<<hr);
453 for(r=1;r<=MAXREG;r++)
456 for(hr=0;hr<HOST_REGS;hr++) {
457 if(cur->regmap[hr]==r+64) {
459 cur->dirty&=~(1<<hr);
460 cur->isconst&=~(1<<hr);
464 for(hr=0;hr<HOST_REGS;hr++) {
465 if(cur->regmap[hr]==r) {
467 cur->dirty&=~(1<<hr);
468 cur->isconst&=~(1<<hr);
475 printf("This shouldn't happen (alloc_reg)");exit(1);
478 void alloc_reg64(struct regstat *cur,int i,signed char reg)
480 int preferred_reg = 8+(reg&1);
483 // allocate the lower 32 bits
484 alloc_reg(cur,i,reg);
486 // Don't allocate unused registers
487 if((cur->uu>>reg)&1) return;
489 // see if the upper half is already allocated
490 for(hr=0;hr<HOST_REGS;hr++)
492 if(cur->regmap[hr]==reg+64) return;
495 // Keep the same mapping if the register was already allocated in a loop
496 preferred_reg = loop_reg(i,reg,preferred_reg);
498 // Try to allocate the preferred register
499 if(cur->regmap[preferred_reg]==-1) {
500 cur->regmap[preferred_reg]=reg|64;
501 cur->dirty&=~(1<<preferred_reg);
502 cur->isconst&=~(1<<preferred_reg);
505 r=cur->regmap[preferred_reg];
506 if(r<64&&((cur->u>>r)&1)) {
507 cur->regmap[preferred_reg]=reg|64;
508 cur->dirty&=~(1<<preferred_reg);
509 cur->isconst&=~(1<<preferred_reg);
512 if(r>=64&&((cur->uu>>(r&63))&1)) {
513 cur->regmap[preferred_reg]=reg|64;
514 cur->dirty&=~(1<<preferred_reg);
515 cur->isconst&=~(1<<preferred_reg);
519 // Clear any unneeded registers
520 // We try to keep the mapping consistent, if possible, because it
521 // makes branches easier (especially loops). So we try to allocate
522 // first (see above) before removing old mappings. If this is not
523 // possible then go ahead and clear out the registers that are no
525 for(hr=HOST_REGS-1;hr>=0;hr--)
530 if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
534 if((cur->uu>>(r&63))&1) {cur->regmap[hr]=-1;break;}
538 // Try to allocate any available register, but prefer
539 // registers that have not been used recently.
541 for(hr=0;hr<HOST_REGS;hr++) {
542 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
543 if(regs[i-1].regmap[hr]!=rs1[i-1]&®s[i-1].regmap[hr]!=rs2[i-1]&®s[i-1].regmap[hr]!=rt1[i-1]&®s[i-1].regmap[hr]!=rt2[i-1]) {
544 cur->regmap[hr]=reg|64;
545 cur->dirty&=~(1<<hr);
546 cur->isconst&=~(1<<hr);
552 // Try to allocate any available register
553 for(hr=0;hr<HOST_REGS;hr++) {
554 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
555 cur->regmap[hr]=reg|64;
556 cur->dirty&=~(1<<hr);
557 cur->isconst&=~(1<<hr);
562 // Ok, now we have to evict someone
563 // Pick a register we hopefully won't need soon
564 u_char hsn[MAXREG+1];
565 memset(hsn,10,sizeof(hsn));
567 lsn(hsn,i,&preferred_reg);
568 //printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",cur->regmap[0],cur->regmap[1],cur->regmap[2],cur->regmap[3],cur->regmap[5],cur->regmap[6],cur->regmap[7]);
569 //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
571 // Don't evict the cycle count at entry points, otherwise the entry
572 // stub will have to write it.
573 if(bt[i]&&hsn[CCREG]>2) hsn[CCREG]=2;
574 if(i>1&&hsn[CCREG]>2&&(itype[i-2]==RJUMP||itype[i-2]==UJUMP||itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP)) hsn[CCREG]=2;
577 // Alloc preferred register if available
578 if(hsn[r=cur->regmap[preferred_reg]&63]==j) {
579 for(hr=0;hr<HOST_REGS;hr++) {
580 // Evict both parts of a 64-bit register
581 if((cur->regmap[hr]&63)==r) {
583 cur->dirty&=~(1<<hr);
584 cur->isconst&=~(1<<hr);
587 cur->regmap[preferred_reg]=reg|64;
590 for(r=1;r<=MAXREG;r++)
592 if(hsn[r]==j&&r!=rs1[i-1]&&r!=rs2[i-1]&&r!=rt1[i-1]&&r!=rt2[i-1]) {
593 for(hr=0;hr<HOST_REGS;hr++) {
594 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
595 if(cur->regmap[hr]==r+64) {
596 cur->regmap[hr]=reg|64;
597 cur->dirty&=~(1<<hr);
598 cur->isconst&=~(1<<hr);
603 for(hr=0;hr<HOST_REGS;hr++) {
604 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
605 if(cur->regmap[hr]==r) {
606 cur->regmap[hr]=reg|64;
607 cur->dirty&=~(1<<hr);
608 cur->isconst&=~(1<<hr);
619 for(r=1;r<=MAXREG;r++)
622 for(hr=0;hr<HOST_REGS;hr++) {
623 if(cur->regmap[hr]==r+64) {
624 cur->regmap[hr]=reg|64;
625 cur->dirty&=~(1<<hr);
626 cur->isconst&=~(1<<hr);
630 for(hr=0;hr<HOST_REGS;hr++) {
631 if(cur->regmap[hr]==r) {
632 cur->regmap[hr]=reg|64;
633 cur->dirty&=~(1<<hr);
634 cur->isconst&=~(1<<hr);
641 printf("This shouldn't happen");exit(1);
644 // Allocate a temporary register. This is done without regard to
645 // dirty status or whether the register we request is on the unneeded list
646 // Note: This will only allocate one register, even if called multiple times
647 void alloc_reg_temp(struct regstat *cur,int i,signed char reg)
650 int preferred_reg = -1;
652 // see if it's already allocated
653 for(hr=0;hr<HOST_REGS;hr++)
655 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==reg) return;
658 // Try to allocate any available register
659 for(hr=HOST_REGS-1;hr>=0;hr--) {
660 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
662 cur->dirty&=~(1<<hr);
663 cur->isconst&=~(1<<hr);
668 // Find an unneeded register
669 for(hr=HOST_REGS-1;hr>=0;hr--)
675 if(i==0||((unneeded_reg[i-1]>>r)&1)) {
677 cur->dirty&=~(1<<hr);
678 cur->isconst&=~(1<<hr);
685 if((cur->uu>>(r&63))&1) {
686 if(i==0||((unneeded_reg_upper[i-1]>>(r&63))&1)) {
688 cur->dirty&=~(1<<hr);
689 cur->isconst&=~(1<<hr);
697 // Ok, now we have to evict someone
698 // Pick a register we hopefully won't need soon
699 // TODO: we might want to follow unconditional jumps here
700 // TODO: get rid of dupe code and make this into a function
701 u_char hsn[MAXREG+1];
702 memset(hsn,10,sizeof(hsn));
704 lsn(hsn,i,&preferred_reg);
705 //printf("hsn: %d %d %d %d %d %d %d\n",hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
707 // Don't evict the cycle count at entry points, otherwise the entry
708 // stub will have to write it.
709 if(bt[i]&&hsn[CCREG]>2) hsn[CCREG]=2;
710 if(i>1&&hsn[CCREG]>2&&(itype[i-2]==RJUMP||itype[i-2]==UJUMP||itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP)) hsn[CCREG]=2;
713 for(r=1;r<=MAXREG;r++)
715 if(hsn[r]==j&&r!=rs1[i-1]&&r!=rs2[i-1]&&r!=rt1[i-1]&&r!=rt2[i-1]) {
716 for(hr=0;hr<HOST_REGS;hr++) {
717 if(hr!=HOST_CCREG||hsn[CCREG]>2) {
718 if(cur->regmap[hr]==r+64) {
720 cur->dirty&=~(1<<hr);
721 cur->isconst&=~(1<<hr);
726 for(hr=0;hr<HOST_REGS;hr++) {
727 if(hr!=HOST_CCREG||hsn[CCREG]>2) {
728 if(cur->regmap[hr]==r) {
730 cur->dirty&=~(1<<hr);
731 cur->isconst&=~(1<<hr);
742 for(r=1;r<=MAXREG;r++)
745 for(hr=0;hr<HOST_REGS;hr++) {
746 if(cur->regmap[hr]==r+64) {
748 cur->dirty&=~(1<<hr);
749 cur->isconst&=~(1<<hr);
753 for(hr=0;hr<HOST_REGS;hr++) {
754 if(cur->regmap[hr]==r) {
756 cur->dirty&=~(1<<hr);
757 cur->isconst&=~(1<<hr);
764 printf("This shouldn't happen");exit(1);
766 // Allocate a specific ARM register.
767 void alloc_arm_reg(struct regstat *cur,int i,signed char reg,char hr)
772 // see if it's already allocated (and dealloc it)
773 for(n=0;n<HOST_REGS;n++)
775 if(n!=EXCLUDE_REG&&cur->regmap[n]==reg) {
776 dirty=(cur->dirty>>n)&1;
782 cur->dirty&=~(1<<hr);
783 cur->dirty|=dirty<<hr;
784 cur->isconst&=~(1<<hr);
787 // Alloc cycle count into dedicated register
788 alloc_cc(struct regstat *cur,int i)
790 alloc_arm_reg(cur,i,CCREG,HOST_CCREG);
798 char regname[16][4] = {
816 void output_byte(u_char byte)
820 void output_modrm(u_char mod,u_char rm,u_char ext)
825 u_char byte=(mod<<6)|(ext<<3)|rm;
828 void output_sib(u_char scale,u_char index,u_char base)
833 u_char byte=(scale<<6)|(index<<3)|base;
836 void output_w32(u_int word)
838 *((u_int *)out)=word;
841 u_int rd_rn_rm(u_int rd, u_int rn, u_int rm)
846 return((rn<<16)|(rd<<12)|rm);
848 u_int rd_rn_imm_shift(u_int rd, u_int rn, u_int imm, u_int shift)
853 assert((shift&1)==0);
854 return((rn<<16)|(rd<<12)|(((32-shift)&30)<<7)|imm);
856 u_int genimm(u_int imm,u_int *encoded)
864 *encoded=((i&30)<<7)|imm;
867 imm=(imm>>2)|(imm<<30);i-=2;
871 void genimm_checked(u_int imm,u_int *encoded)
873 u_int ret=genimm(imm,encoded);
876 u_int genjmp(u_int addr)
878 int offset=addr-(int)out-8;
879 if(offset<-33554432||offset>=33554432) {
881 printf("genjmp: out of range: %08x\n", offset);
886 return ((u_int)offset>>2)&0xffffff;
889 void emit_mov(int rs,int rt)
891 assem_debug("mov %s,%s\n",regname[rt],regname[rs]);
892 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs));
895 void emit_movs(int rs,int rt)
897 assem_debug("movs %s,%s\n",regname[rt],regname[rs]);
898 output_w32(0xe1b00000|rd_rn_rm(rt,0,rs));
901 void emit_add(int rs1,int rs2,int rt)
903 assem_debug("add %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
904 output_w32(0xe0800000|rd_rn_rm(rt,rs1,rs2));
907 void emit_adds(int rs1,int rs2,int rt)
909 assem_debug("adds %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
910 output_w32(0xe0900000|rd_rn_rm(rt,rs1,rs2));
913 void emit_adcs(int rs1,int rs2,int rt)
915 assem_debug("adcs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
916 output_w32(0xe0b00000|rd_rn_rm(rt,rs1,rs2));
919 void emit_sbc(int rs1,int rs2,int rt)
921 assem_debug("sbc %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
922 output_w32(0xe0c00000|rd_rn_rm(rt,rs1,rs2));
925 void emit_sbcs(int rs1,int rs2,int rt)
927 assem_debug("sbcs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
928 output_w32(0xe0d00000|rd_rn_rm(rt,rs1,rs2));
931 void emit_neg(int rs, int rt)
933 assem_debug("rsb %s,%s,#0\n",regname[rt],regname[rs]);
934 output_w32(0xe2600000|rd_rn_rm(rt,rs,0));
937 void emit_negs(int rs, int rt)
939 assem_debug("rsbs %s,%s,#0\n",regname[rt],regname[rs]);
940 output_w32(0xe2700000|rd_rn_rm(rt,rs,0));
943 void emit_sub(int rs1,int rs2,int rt)
945 assem_debug("sub %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
946 output_w32(0xe0400000|rd_rn_rm(rt,rs1,rs2));
949 void emit_subs(int rs1,int rs2,int rt)
951 assem_debug("subs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
952 output_w32(0xe0500000|rd_rn_rm(rt,rs1,rs2));
955 void emit_zeroreg(int rt)
957 assem_debug("mov %s,#0\n",regname[rt]);
958 output_w32(0xe3a00000|rd_rn_rm(rt,0,0));
961 void emit_loadlp(u_int imm,u_int rt)
963 add_literal((int)out,imm);
964 assem_debug("ldr %s,pc+? [=%x]\n",regname[rt],imm);
965 output_w32(0xe5900000|rd_rn_rm(rt,15,0));
967 void emit_movw(u_int imm,u_int rt)
970 assem_debug("movw %s,#%d (0x%x)\n",regname[rt],imm,imm);
971 output_w32(0xe3000000|rd_rn_rm(rt,0,0)|(imm&0xfff)|((imm<<4)&0xf0000));
973 void emit_movt(u_int imm,u_int rt)
975 assem_debug("movt %s,#%d (0x%x)\n",regname[rt],imm&0xffff0000,imm&0xffff0000);
976 output_w32(0xe3400000|rd_rn_rm(rt,0,0)|((imm>>16)&0xfff)|((imm>>12)&0xf0000));
978 void emit_movimm(u_int imm,u_int rt)
981 if(genimm(imm,&armval)) {
982 assem_debug("mov %s,#%d\n",regname[rt],imm);
983 output_w32(0xe3a00000|rd_rn_rm(rt,0,0)|armval);
984 }else if(genimm(~imm,&armval)) {
985 assem_debug("mvn %s,#%d\n",regname[rt],imm);
986 output_w32(0xe3e00000|rd_rn_rm(rt,0,0)|armval);
987 }else if(imm<65536) {
989 assem_debug("mov %s,#%d\n",regname[rt],imm&0xFF00);
990 output_w32(0xe3a00000|rd_rn_imm_shift(rt,0,imm>>8,8));
991 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF);
992 output_w32(0xe2800000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1000 emit_movw(imm&0x0000FFFF,rt);
1001 emit_movt(imm&0xFFFF0000,rt);
1005 void emit_pcreladdr(u_int rt)
1007 assem_debug("add %s,pc,#?\n",regname[rt]);
1008 output_w32(0xe2800000|rd_rn_rm(rt,15,0));
1011 void emit_loadreg(int r, int hr)
1015 printf("64bit load in 32bit mode!\n");
1023 int addr=((int)reg)+((r&63)<<REG_SHIFT)+((r&64)>>4);
1024 if((r&63)==HIREG) addr=(int)&hi+((r&64)>>4);
1025 if((r&63)==LOREG) addr=(int)&lo+((r&64)>>4);
1026 if(r==CCREG) addr=(int)&cycle_count;
1027 if(r==CSREG) addr=(int)&Status;
1028 if(r==FSREG) addr=(int)&FCR31;
1029 if(r==INVCP) addr=(int)&invc_ptr;
1030 u_int offset = addr-(u_int)&dynarec_local;
1031 assert(offset<4096);
1032 assem_debug("ldr %s,fp+%d\n",regname[hr],offset);
1033 output_w32(0xe5900000|rd_rn_rm(hr,FP,0)|offset);
1036 void emit_storereg(int r, int hr)
1040 printf("64bit store in 32bit mode!\n");
1045 int addr=((int)reg)+((r&63)<<REG_SHIFT)+((r&64)>>4);
1046 if((r&63)==HIREG) addr=(int)&hi+((r&64)>>4);
1047 if((r&63)==LOREG) addr=(int)&lo+((r&64)>>4);
1048 if(r==CCREG) addr=(int)&cycle_count;
1049 if(r==FSREG) addr=(int)&FCR31;
1050 u_int offset = addr-(u_int)&dynarec_local;
1051 assert(offset<4096);
1052 assem_debug("str %s,fp+%d\n",regname[hr],offset);
1053 output_w32(0xe5800000|rd_rn_rm(hr,FP,0)|offset);
1056 void emit_test(int rs, int rt)
1058 assem_debug("tst %s,%s\n",regname[rs],regname[rt]);
1059 output_w32(0xe1100000|rd_rn_rm(0,rs,rt));
1062 void emit_testimm(int rs,int imm)
1065 assem_debug("tst %s,#%d\n",regname[rs],imm);
1066 genimm_checked(imm,&armval);
1067 output_w32(0xe3100000|rd_rn_rm(0,rs,0)|armval);
1070 void emit_testeqimm(int rs,int imm)
1073 assem_debug("tsteq %s,$%d\n",regname[rs],imm);
1074 genimm_checked(imm,&armval);
1075 output_w32(0x03100000|rd_rn_rm(0,rs,0)|armval);
1078 void emit_not(int rs,int rt)
1080 assem_debug("mvn %s,%s\n",regname[rt],regname[rs]);
1081 output_w32(0xe1e00000|rd_rn_rm(rt,0,rs));
1084 void emit_mvnmi(int rs,int rt)
1086 assem_debug("mvnmi %s,%s\n",regname[rt],regname[rs]);
1087 output_w32(0x41e00000|rd_rn_rm(rt,0,rs));
1090 void emit_and(u_int rs1,u_int rs2,u_int rt)
1092 assem_debug("and %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1093 output_w32(0xe0000000|rd_rn_rm(rt,rs1,rs2));
1096 void emit_or(u_int rs1,u_int rs2,u_int rt)
1098 assem_debug("orr %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1099 output_w32(0xe1800000|rd_rn_rm(rt,rs1,rs2));
1101 void emit_or_and_set_flags(int rs1,int rs2,int rt)
1103 assem_debug("orrs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1104 output_w32(0xe1900000|rd_rn_rm(rt,rs1,rs2));
1107 void emit_orrshl_imm(u_int rs,u_int imm,u_int rt)
1112 assem_debug("orr %s,%s,%s,lsl #%d\n",regname[rt],regname[rt],regname[rs],imm);
1113 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs)|(imm<<7));
1116 void emit_orrshr_imm(u_int rs,u_int imm,u_int rt)
1121 assem_debug("orr %s,%s,%s,lsr #%d\n",regname[rt],regname[rt],regname[rs],imm);
1122 output_w32(0xe1800020|rd_rn_rm(rt,rt,rs)|(imm<<7));
1125 void emit_xor(u_int rs1,u_int rs2,u_int rt)
1127 assem_debug("eor %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1128 output_w32(0xe0200000|rd_rn_rm(rt,rs1,rs2));
1131 void emit_addimm(u_int rs,int imm,u_int rt)
1136 assert(imm>-65536&&imm<65536);
1138 if(genimm(imm,&armval)) {
1139 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rs],imm);
1140 output_w32(0xe2800000|rd_rn_rm(rt,rs,0)|armval);
1141 }else if(genimm(-imm,&armval)) {
1142 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rs],imm);
1143 output_w32(0xe2400000|rd_rn_rm(rt,rs,0)|armval);
1145 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rs],(-imm)&0xFF00);
1146 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rt],(-imm)&0xFF);
1147 output_w32(0xe2400000|rd_rn_imm_shift(rt,rs,(-imm)>>8,8));
1148 output_w32(0xe2400000|rd_rn_imm_shift(rt,rt,(-imm)&0xff,0));
1150 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF00);
1151 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF);
1152 output_w32(0xe2800000|rd_rn_imm_shift(rt,rs,imm>>8,8));
1153 output_w32(0xe2800000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1156 else if(rs!=rt) emit_mov(rs,rt);
1159 void emit_addimm_and_set_flags(int imm,int rt)
1161 assert(imm>-65536&&imm<65536);
1163 if(genimm(imm,&armval)) {
1164 assem_debug("adds %s,%s,#%d\n",regname[rt],regname[rt],imm);
1165 output_w32(0xe2900000|rd_rn_rm(rt,rt,0)|armval);
1166 }else if(genimm(-imm,&armval)) {
1167 assem_debug("subs %s,%s,#%d\n",regname[rt],regname[rt],imm);
1168 output_w32(0xe2500000|rd_rn_rm(rt,rt,0)|armval);
1170 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rt],(-imm)&0xFF00);
1171 assem_debug("subs %s,%s,#%d\n",regname[rt],regname[rt],(-imm)&0xFF);
1172 output_w32(0xe2400000|rd_rn_imm_shift(rt,rt,(-imm)>>8,8));
1173 output_w32(0xe2500000|rd_rn_imm_shift(rt,rt,(-imm)&0xff,0));
1175 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF00);
1176 assem_debug("adds %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF);
1177 output_w32(0xe2800000|rd_rn_imm_shift(rt,rt,imm>>8,8));
1178 output_w32(0xe2900000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1181 void emit_addimm_no_flags(u_int imm,u_int rt)
1183 emit_addimm(rt,imm,rt);
1186 void emit_addnop(u_int r)
1189 assem_debug("add %s,%s,#0 (nop)\n",regname[r],regname[r]);
1190 output_w32(0xe2800000|rd_rn_rm(r,r,0));
1193 void emit_adcimm(u_int rs,int imm,u_int rt)
1196 genimm_checked(imm,&armval);
1197 assem_debug("adc %s,%s,#%d\n",regname[rt],regname[rs],imm);
1198 output_w32(0xe2a00000|rd_rn_rm(rt,rs,0)|armval);
1200 /*void emit_sbcimm(int imm,u_int rt)
1203 genimm_checked(imm,&armval);
1204 assem_debug("sbc %s,%s,#%d\n",regname[rt],regname[rt],imm);
1205 output_w32(0xe2c00000|rd_rn_rm(rt,rt,0)|armval);
1207 void emit_sbbimm(int imm,u_int rt)
1209 assem_debug("sbb $%d,%%%s\n",imm,regname[rt]);
1211 if(imm<128&&imm>=-128) {
1213 output_modrm(3,rt,3);
1219 output_modrm(3,rt,3);
1223 void emit_rscimm(int rs,int imm,u_int rt)
1227 genimm_checked(imm,&armval);
1228 assem_debug("rsc %s,%s,#%d\n",regname[rt],regname[rs],imm);
1229 output_w32(0xe2e00000|rd_rn_rm(rt,rs,0)|armval);
1232 void emit_addimm64_32(int rsh,int rsl,int imm,int rth,int rtl)
1234 // TODO: if(genimm(imm,&armval)) ...
1236 emit_movimm(imm,HOST_TEMPREG);
1237 emit_adds(HOST_TEMPREG,rsl,rtl);
1238 emit_adcimm(rsh,0,rth);
1241 void emit_sbb(int rs1,int rs2)
1243 assem_debug("sbb %%%s,%%%s\n",regname[rs2],regname[rs1]);
1245 output_modrm(3,rs1,rs2);
1248 void emit_andimm(int rs,int imm,int rt)
1253 }else if(genimm(imm,&armval)) {
1254 assem_debug("and %s,%s,#%d\n",regname[rt],regname[rs],imm);
1255 output_w32(0xe2000000|rd_rn_rm(rt,rs,0)|armval);
1256 }else if(genimm(~imm,&armval)) {
1257 assem_debug("bic %s,%s,#%d\n",regname[rt],regname[rs],imm);
1258 output_w32(0xe3c00000|rd_rn_rm(rt,rs,0)|armval);
1259 }else if(imm==65535) {
1261 assem_debug("bic %s,%s,#FF000000\n",regname[rt],regname[rs]);
1262 output_w32(0xe3c00000|rd_rn_rm(rt,rs,0)|0x4FF);
1263 assem_debug("bic %s,%s,#00FF0000\n",regname[rt],regname[rt]);
1264 output_w32(0xe3c00000|rd_rn_rm(rt,rt,0)|0x8FF);
1266 assem_debug("uxth %s,%s\n",regname[rt],regname[rs]);
1267 output_w32(0xe6ff0070|rd_rn_rm(rt,0,rs));
1270 assert(imm>0&&imm<65535);
1272 assem_debug("mov r14,#%d\n",imm&0xFF00);
1273 output_w32(0xe3a00000|rd_rn_imm_shift(HOST_TEMPREG,0,imm>>8,8));
1274 assem_debug("add r14,r14,#%d\n",imm&0xFF);
1275 output_w32(0xe2800000|rd_rn_imm_shift(HOST_TEMPREG,HOST_TEMPREG,imm&0xff,0));
1277 emit_movw(imm,HOST_TEMPREG);
1279 assem_debug("and %s,%s,r14\n",regname[rt],regname[rs]);
1280 output_w32(0xe0000000|rd_rn_rm(rt,rs,HOST_TEMPREG));
1284 void emit_orimm(int rs,int imm,int rt)
1288 if(rs!=rt) emit_mov(rs,rt);
1289 }else if(genimm(imm,&armval)) {
1290 assem_debug("orr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1291 output_w32(0xe3800000|rd_rn_rm(rt,rs,0)|armval);
1293 assert(imm>0&&imm<65536);
1294 assem_debug("orr %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF00);
1295 assem_debug("orr %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF);
1296 output_w32(0xe3800000|rd_rn_imm_shift(rt,rs,imm>>8,8));
1297 output_w32(0xe3800000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1301 void emit_xorimm(int rs,int imm,int rt)
1305 if(rs!=rt) emit_mov(rs,rt);
1306 }else if(genimm(imm,&armval)) {
1307 assem_debug("eor %s,%s,#%d\n",regname[rt],regname[rs],imm);
1308 output_w32(0xe2200000|rd_rn_rm(rt,rs,0)|armval);
1310 assert(imm>0&&imm<65536);
1311 assem_debug("eor %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF00);
1312 assem_debug("eor %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF);
1313 output_w32(0xe2200000|rd_rn_imm_shift(rt,rs,imm>>8,8));
1314 output_w32(0xe2200000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1318 void emit_shlimm(int rs,u_int imm,int rt)
1323 assem_debug("lsl %s,%s,#%d\n",regname[rt],regname[rs],imm);
1324 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|(imm<<7));
1327 void emit_shrimm(int rs,u_int imm,int rt)
1331 assem_debug("lsr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1332 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x20|(imm<<7));
1335 void emit_sarimm(int rs,u_int imm,int rt)
1339 assem_debug("asr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1340 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x40|(imm<<7));
1343 void emit_rorimm(int rs,u_int imm,int rt)
1347 assem_debug("ror %s,%s,#%d\n",regname[rt],regname[rs],imm);
1348 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x60|(imm<<7));
1351 void emit_shldimm(int rs,int rs2,u_int imm,int rt)
1353 assem_debug("shld %%%s,%%%s,%d\n",regname[rt],regname[rs2],imm);
1357 assem_debug("lsl %s,%s,#%d\n",regname[rt],regname[rs],imm);
1358 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|(imm<<7));
1359 assem_debug("orr %s,%s,%s,lsr #%d\n",regname[rt],regname[rt],regname[rs2],32-imm);
1360 output_w32(0xe1800020|rd_rn_rm(rt,rt,rs2)|((32-imm)<<7));
1363 void emit_shrdimm(int rs,int rs2,u_int imm,int rt)
1365 assem_debug("shrd %%%s,%%%s,%d\n",regname[rt],regname[rs2],imm);
1369 assem_debug("lsr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1370 output_w32(0xe1a00020|rd_rn_rm(rt,0,rs)|(imm<<7));
1371 assem_debug("orr %s,%s,%s,lsl #%d\n",regname[rt],regname[rt],regname[rs2],32-imm);
1372 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs2)|((32-imm)<<7));
1375 void emit_signextend16(int rs,int rt)
1378 emit_shlimm(rs,16,rt);
1379 emit_sarimm(rt,16,rt);
1381 assem_debug("sxth %s,%s\n",regname[rt],regname[rs]);
1382 output_w32(0xe6bf0070|rd_rn_rm(rt,0,rs));
1386 void emit_shl(u_int rs,u_int shift,u_int rt)
1392 assem_debug("lsl %s,%s,%s\n",regname[rt],regname[rs],regname[shift]);
1393 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x10|(shift<<8));
1395 void emit_shr(u_int rs,u_int shift,u_int rt)
1400 assem_debug("lsr %s,%s,%s\n",regname[rt],regname[rs],regname[shift]);
1401 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x30|(shift<<8));
1403 void emit_sar(u_int rs,u_int shift,u_int rt)
1408 assem_debug("asr %s,%s,%s\n",regname[rt],regname[rs],regname[shift]);
1409 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x50|(shift<<8));
1411 void emit_shlcl(int r)
1413 assem_debug("shl %%%s,%%cl\n",regname[r]);
1416 void emit_shrcl(int r)
1418 assem_debug("shr %%%s,%%cl\n",regname[r]);
1421 void emit_sarcl(int r)
1423 assem_debug("sar %%%s,%%cl\n",regname[r]);
1427 void emit_shldcl(int r1,int r2)
1429 assem_debug("shld %%%s,%%%s,%%cl\n",regname[r1],regname[r2]);
1432 void emit_shrdcl(int r1,int r2)
1434 assem_debug("shrd %%%s,%%%s,%%cl\n",regname[r1],regname[r2]);
1437 void emit_orrshl(u_int rs,u_int shift,u_int rt)
1442 assem_debug("orr %s,%s,%s,lsl %s\n",regname[rt],regname[rt],regname[rs],regname[shift]);
1443 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs)|0x10|(shift<<8));
1445 void emit_orrshr(u_int rs,u_int shift,u_int rt)
1450 assem_debug("orr %s,%s,%s,lsr %s\n",regname[rt],regname[rt],regname[rs],regname[shift]);
1451 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs)|0x30|(shift<<8));
1454 void emit_cmpimm(int rs,int imm)
1457 if(genimm(imm,&armval)) {
1458 assem_debug("cmp %s,#%d\n",regname[rs],imm);
1459 output_w32(0xe3500000|rd_rn_rm(0,rs,0)|armval);
1460 }else if(genimm(-imm,&armval)) {
1461 assem_debug("cmn %s,#%d\n",regname[rs],imm);
1462 output_w32(0xe3700000|rd_rn_rm(0,rs,0)|armval);
1466 emit_movimm(imm,HOST_TEMPREG);
1468 emit_movw(imm,HOST_TEMPREG);
1470 assem_debug("cmp %s,r14\n",regname[rs]);
1471 output_w32(0xe1500000|rd_rn_rm(0,rs,HOST_TEMPREG));
1475 emit_movimm(-imm,HOST_TEMPREG);
1477 emit_movw(-imm,HOST_TEMPREG);
1479 assem_debug("cmn %s,r14\n",regname[rs]);
1480 output_w32(0xe1700000|rd_rn_rm(0,rs,HOST_TEMPREG));
1484 void emit_cmovne(u_int *addr,int rt)
1486 assem_debug("cmovne %x,%%%s",(int)addr,regname[rt]);
1489 void emit_cmovl(u_int *addr,int rt)
1491 assem_debug("cmovl %x,%%%s",(int)addr,regname[rt]);
1494 void emit_cmovs(u_int *addr,int rt)
1496 assem_debug("cmovs %x,%%%s",(int)addr,regname[rt]);
1499 void emit_cmovne_imm(int imm,int rt)
1501 assem_debug("movne %s,#%d\n",regname[rt],imm);
1503 genimm_checked(imm,&armval);
1504 output_w32(0x13a00000|rd_rn_rm(rt,0,0)|armval);
1506 void emit_cmovl_imm(int imm,int rt)
1508 assem_debug("movlt %s,#%d\n",regname[rt],imm);
1510 genimm_checked(imm,&armval);
1511 output_w32(0xb3a00000|rd_rn_rm(rt,0,0)|armval);
1513 void emit_cmovb_imm(int imm,int rt)
1515 assem_debug("movcc %s,#%d\n",regname[rt],imm);
1517 genimm_checked(imm,&armval);
1518 output_w32(0x33a00000|rd_rn_rm(rt,0,0)|armval);
1520 void emit_cmovs_imm(int imm,int rt)
1522 assem_debug("movmi %s,#%d\n",regname[rt],imm);
1524 genimm_checked(imm,&armval);
1525 output_w32(0x43a00000|rd_rn_rm(rt,0,0)|armval);
1527 void emit_cmove_reg(int rs,int rt)
1529 assem_debug("moveq %s,%s\n",regname[rt],regname[rs]);
1530 output_w32(0x01a00000|rd_rn_rm(rt,0,rs));
1532 void emit_cmovne_reg(int rs,int rt)
1534 assem_debug("movne %s,%s\n",regname[rt],regname[rs]);
1535 output_w32(0x11a00000|rd_rn_rm(rt,0,rs));
1537 void emit_cmovl_reg(int rs,int rt)
1539 assem_debug("movlt %s,%s\n",regname[rt],regname[rs]);
1540 output_w32(0xb1a00000|rd_rn_rm(rt,0,rs));
1542 void emit_cmovs_reg(int rs,int rt)
1544 assem_debug("movmi %s,%s\n",regname[rt],regname[rs]);
1545 output_w32(0x41a00000|rd_rn_rm(rt,0,rs));
1548 void emit_slti32(int rs,int imm,int rt)
1550 if(rs!=rt) emit_zeroreg(rt);
1551 emit_cmpimm(rs,imm);
1552 if(rs==rt) emit_movimm(0,rt);
1553 emit_cmovl_imm(1,rt);
1555 void emit_sltiu32(int rs,int imm,int rt)
1557 if(rs!=rt) emit_zeroreg(rt);
1558 emit_cmpimm(rs,imm);
1559 if(rs==rt) emit_movimm(0,rt);
1560 emit_cmovb_imm(1,rt);
1562 void emit_slti64_32(int rsh,int rsl,int imm,int rt)
1565 emit_slti32(rsl,imm,rt);
1569 emit_cmovne_imm(0,rt);
1570 emit_cmovs_imm(1,rt);
1574 emit_cmpimm(rsh,-1);
1575 emit_cmovne_imm(0,rt);
1576 emit_cmovl_imm(1,rt);
1579 void emit_sltiu64_32(int rsh,int rsl,int imm,int rt)
1582 emit_sltiu32(rsl,imm,rt);
1586 emit_cmovne_imm(0,rt);
1590 emit_cmpimm(rsh,-1);
1591 emit_cmovne_imm(1,rt);
1595 void emit_cmp(int rs,int rt)
1597 assem_debug("cmp %s,%s\n",regname[rs],regname[rt]);
1598 output_w32(0xe1500000|rd_rn_rm(0,rs,rt));
1600 void emit_set_gz32(int rs, int rt)
1602 //assem_debug("set_gz32\n");
1605 emit_cmovl_imm(0,rt);
1607 void emit_set_nz32(int rs, int rt)
1609 //assem_debug("set_nz32\n");
1610 if(rs!=rt) emit_movs(rs,rt);
1611 else emit_test(rs,rs);
1612 emit_cmovne_imm(1,rt);
1614 void emit_set_gz64_32(int rsh, int rsl, int rt)
1616 //assem_debug("set_gz64\n");
1617 emit_set_gz32(rsl,rt);
1619 emit_cmovne_imm(1,rt);
1620 emit_cmovs_imm(0,rt);
1622 void emit_set_nz64_32(int rsh, int rsl, int rt)
1624 //assem_debug("set_nz64\n");
1625 emit_or_and_set_flags(rsh,rsl,rt);
1626 emit_cmovne_imm(1,rt);
1628 void emit_set_if_less32(int rs1, int rs2, int rt)
1630 //assem_debug("set if less (%%%s,%%%s),%%%s\n",regname[rs1],regname[rs2],regname[rt]);
1631 if(rs1!=rt&&rs2!=rt) emit_zeroreg(rt);
1633 if(rs1==rt||rs2==rt) emit_movimm(0,rt);
1634 emit_cmovl_imm(1,rt);
1636 void emit_set_if_carry32(int rs1, int rs2, int rt)
1638 //assem_debug("set if carry (%%%s,%%%s),%%%s\n",regname[rs1],regname[rs2],regname[rt]);
1639 if(rs1!=rt&&rs2!=rt) emit_zeroreg(rt);
1641 if(rs1==rt||rs2==rt) emit_movimm(0,rt);
1642 emit_cmovb_imm(1,rt);
1644 void emit_set_if_less64_32(int u1, int l1, int u2, int l2, int rt)
1646 //assem_debug("set if less64 (%%%s,%%%s,%%%s,%%%s),%%%s\n",regname[u1],regname[l1],regname[u2],regname[l2],regname[rt]);
1651 emit_sbcs(u1,u2,HOST_TEMPREG);
1652 emit_cmovl_imm(1,rt);
1654 void emit_set_if_carry64_32(int u1, int l1, int u2, int l2, int rt)
1656 //assem_debug("set if carry64 (%%%s,%%%s,%%%s,%%%s),%%%s\n",regname[u1],regname[l1],regname[u2],regname[l2],regname[rt]);
1661 emit_sbcs(u1,u2,HOST_TEMPREG);
1662 emit_cmovb_imm(1,rt);
1665 void emit_call(int a)
1667 assem_debug("bl %x (%x+%x)\n",a,(int)out,a-(int)out-8);
1668 u_int offset=genjmp(a);
1669 output_w32(0xeb000000|offset);
1671 void emit_jmp(int a)
1673 assem_debug("b %x (%x+%x)\n",a,(int)out,a-(int)out-8);
1674 u_int offset=genjmp(a);
1675 output_w32(0xea000000|offset);
1677 void emit_jne(int a)
1679 assem_debug("bne %x\n",a);
1680 u_int offset=genjmp(a);
1681 output_w32(0x1a000000|offset);
1683 void emit_jeq(int a)
1685 assem_debug("beq %x\n",a);
1686 u_int offset=genjmp(a);
1687 output_w32(0x0a000000|offset);
1691 assem_debug("bmi %x\n",a);
1692 u_int offset=genjmp(a);
1693 output_w32(0x4a000000|offset);
1695 void emit_jns(int a)
1697 assem_debug("bpl %x\n",a);
1698 u_int offset=genjmp(a);
1699 output_w32(0x5a000000|offset);
1703 assem_debug("blt %x\n",a);
1704 u_int offset=genjmp(a);
1705 output_w32(0xba000000|offset);
1707 void emit_jge(int a)
1709 assem_debug("bge %x\n",a);
1710 u_int offset=genjmp(a);
1711 output_w32(0xaa000000|offset);
1713 void emit_jno(int a)
1715 assem_debug("bvc %x\n",a);
1716 u_int offset=genjmp(a);
1717 output_w32(0x7a000000|offset);
1721 assem_debug("bcs %x\n",a);
1722 u_int offset=genjmp(a);
1723 output_w32(0x2a000000|offset);
1725 void emit_jcc(int a)
1727 assem_debug("bcc %x\n",a);
1728 u_int offset=genjmp(a);
1729 output_w32(0x3a000000|offset);
1732 void emit_pushimm(int imm)
1734 assem_debug("push $%x\n",imm);
1739 assem_debug("pusha\n");
1744 assem_debug("popa\n");
1747 void emit_pushreg(u_int r)
1749 assem_debug("push %%%s\n",regname[r]);
1752 void emit_popreg(u_int r)
1754 assem_debug("pop %%%s\n",regname[r]);
1757 void emit_callreg(u_int r)
1759 assem_debug("call *%%%s\n",regname[r]);
1762 void emit_jmpreg(u_int r)
1764 assem_debug("mov pc,%s\n",regname[r]);
1765 output_w32(0xe1a00000|rd_rn_rm(15,0,r));
1768 void emit_readword_indexed(int offset, int rs, int rt)
1770 assert(offset>-4096&&offset<4096);
1771 assem_debug("ldr %s,%s+%d\n",regname[rt],regname[rs],offset);
1773 output_w32(0xe5900000|rd_rn_rm(rt,rs,0)|offset);
1775 output_w32(0xe5100000|rd_rn_rm(rt,rs,0)|(-offset));
1778 void emit_readword_dualindexedx4(int rs1, int rs2, int rt)
1780 assem_debug("ldr %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
1781 output_w32(0xe7900000|rd_rn_rm(rt,rs1,rs2)|0x100);
1783 void emit_readword_indexed_tlb(int addr, int rs, int map, int rt)
1785 if(map<0) emit_readword_indexed(addr, rs, rt);
1788 emit_readword_dualindexedx4(rs, map, rt);
1791 void emit_readdword_indexed_tlb(int addr, int rs, int map, int rh, int rl)
1794 if(rh>=0) emit_readword_indexed(addr, rs, rh);
1795 emit_readword_indexed(addr+4, rs, rl);
1798 if(rh>=0) emit_readword_indexed_tlb(addr, rs, map, rh);
1799 emit_addimm(map,1,map);
1800 emit_readword_indexed_tlb(addr, rs, map, rl);
1803 void emit_movsbl_indexed(int offset, int rs, int rt)
1805 assert(offset>-256&&offset<256);
1806 assem_debug("ldrsb %s,%s+%d\n",regname[rt],regname[rs],offset);
1808 output_w32(0xe1d000d0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1810 output_w32(0xe15000d0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1813 void emit_movsbl_indexed_tlb(int addr, int rs, int map, int rt)
1815 if(map<0) emit_movsbl_indexed(addr, rs, rt);
1818 emit_shlimm(map,2,map);
1819 assem_debug("ldrsb %s,%s+%s\n",regname[rt],regname[rs],regname[map]);
1820 output_w32(0xe19000d0|rd_rn_rm(rt,rs,map));
1822 assert(addr>-256&&addr<256);
1823 assem_debug("add %s,%s,%s,lsl #2\n",regname[rt],regname[rs],regname[map]);
1824 output_w32(0xe0800000|rd_rn_rm(rt,rs,map)|(2<<7));
1825 emit_movsbl_indexed(addr, rt, rt);
1829 void emit_movswl_indexed(int offset, int rs, int rt)
1831 assert(offset>-256&&offset<256);
1832 assem_debug("ldrsh %s,%s+%d\n",regname[rt],regname[rs],offset);
1834 output_w32(0xe1d000f0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1836 output_w32(0xe15000f0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1839 void emit_movzbl_indexed(int offset, int rs, int rt)
1841 assert(offset>-4096&&offset<4096);
1842 assem_debug("ldrb %s,%s+%d\n",regname[rt],regname[rs],offset);
1844 output_w32(0xe5d00000|rd_rn_rm(rt,rs,0)|offset);
1846 output_w32(0xe5500000|rd_rn_rm(rt,rs,0)|(-offset));
1849 void emit_movzbl_dualindexedx4(int rs1, int rs2, int rt)
1851 assem_debug("ldrb %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
1852 output_w32(0xe7d00000|rd_rn_rm(rt,rs1,rs2)|0x100);
1854 void emit_movzbl_indexed_tlb(int addr, int rs, int map, int rt)
1856 if(map<0) emit_movzbl_indexed(addr, rs, rt);
1859 emit_movzbl_dualindexedx4(rs, map, rt);
1861 emit_addimm(rs,addr,rt);
1862 emit_movzbl_dualindexedx4(rt, map, rt);
1866 void emit_movzwl_indexed(int offset, int rs, int rt)
1868 assert(offset>-256&&offset<256);
1869 assem_debug("ldrh %s,%s+%d\n",regname[rt],regname[rs],offset);
1871 output_w32(0xe1d000b0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1873 output_w32(0xe15000b0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1876 void emit_readword(int addr, int rt)
1878 u_int offset = addr-(u_int)&dynarec_local;
1879 assert(offset<4096);
1880 assem_debug("ldr %s,fp+%d\n",regname[rt],offset);
1881 output_w32(0xe5900000|rd_rn_rm(rt,FP,0)|offset);
1883 void emit_movsbl(int addr, int rt)
1885 u_int offset = addr-(u_int)&dynarec_local;
1887 assem_debug("ldrsb %s,fp+%d\n",regname[rt],offset);
1888 output_w32(0xe1d000d0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
1890 void emit_movswl(int addr, int rt)
1892 u_int offset = addr-(u_int)&dynarec_local;
1894 assem_debug("ldrsh %s,fp+%d\n",regname[rt],offset);
1895 output_w32(0xe1d000f0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
1897 void emit_movzbl(int addr, int rt)
1899 u_int offset = addr-(u_int)&dynarec_local;
1900 assert(offset<4096);
1901 assem_debug("ldrb %s,fp+%d\n",regname[rt],offset);
1902 output_w32(0xe5d00000|rd_rn_rm(rt,FP,0)|offset);
1904 void emit_movzwl(int addr, int rt)
1906 u_int offset = addr-(u_int)&dynarec_local;
1908 assem_debug("ldrh %s,fp+%d\n",regname[rt],offset);
1909 output_w32(0xe1d000b0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
1911 void emit_movzwl_reg(int rs, int rt)
1913 assem_debug("movzwl %%%s,%%%s\n",regname[rs]+1,regname[rt]);
1917 void emit_xchg(int rs, int rt)
1919 assem_debug("xchg %%%s,%%%s\n",regname[rs],regname[rt]);
1922 void emit_writeword_indexed(int rt, int offset, int rs)
1924 assert(offset>-4096&&offset<4096);
1925 assem_debug("str %s,%s+%d\n",regname[rt],regname[rs],offset);
1927 output_w32(0xe5800000|rd_rn_rm(rt,rs,0)|offset);
1929 output_w32(0xe5000000|rd_rn_rm(rt,rs,0)|(-offset));
1932 void emit_writeword_dualindexedx4(int rt, int rs1, int rs2)
1934 assem_debug("str %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
1935 output_w32(0xe7800000|rd_rn_rm(rt,rs1,rs2)|0x100);
1937 void emit_writeword_indexed_tlb(int rt, int addr, int rs, int map, int temp)
1939 if(map<0) emit_writeword_indexed(rt, addr, rs);
1942 emit_writeword_dualindexedx4(rt, rs, map);
1945 void emit_writedword_indexed_tlb(int rh, int rl, int addr, int rs, int map, int temp)
1948 if(rh>=0) emit_writeword_indexed(rh, addr, rs);
1949 emit_writeword_indexed(rl, addr+4, rs);
1952 if(temp!=rs) emit_addimm(map,1,temp);
1953 emit_writeword_indexed_tlb(rh, addr, rs, map, temp);
1954 if(temp!=rs) emit_writeword_indexed_tlb(rl, addr, rs, temp, temp);
1956 emit_addimm(rs,4,rs);
1957 emit_writeword_indexed_tlb(rl, addr, rs, map, temp);
1961 void emit_writehword_indexed(int rt, int offset, int rs)
1963 assert(offset>-256&&offset<256);
1964 assem_debug("strh %s,%s+%d\n",regname[rt],regname[rs],offset);
1966 output_w32(0xe1c000b0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1968 output_w32(0xe14000b0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1971 void emit_writebyte_indexed(int rt, int offset, int rs)
1973 assert(offset>-4096&&offset<4096);
1974 assem_debug("strb %s,%s+%d\n",regname[rt],regname[rs],offset);
1976 output_w32(0xe5c00000|rd_rn_rm(rt,rs,0)|offset);
1978 output_w32(0xe5400000|rd_rn_rm(rt,rs,0)|(-offset));
1981 void emit_writebyte_dualindexedx4(int rt, int rs1, int rs2)
1983 assem_debug("strb %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
1984 output_w32(0xe7c00000|rd_rn_rm(rt,rs1,rs2)|0x100);
1986 void emit_writebyte_indexed_tlb(int rt, int addr, int rs, int map, int temp)
1988 if(map<0) emit_writebyte_indexed(rt, addr, rs);
1991 emit_writebyte_dualindexedx4(rt, rs, map);
1993 emit_addimm(rs,addr,temp);
1994 emit_writebyte_dualindexedx4(rt, temp, map);
1998 void emit_writeword(int rt, int addr)
2000 u_int offset = addr-(u_int)&dynarec_local;
2001 assert(offset<4096);
2002 assem_debug("str %s,fp+%d\n",regname[rt],offset);
2003 output_w32(0xe5800000|rd_rn_rm(rt,FP,0)|offset);
2005 void emit_writehword(int rt, int addr)
2007 u_int offset = addr-(u_int)&dynarec_local;
2009 assem_debug("strh %s,fp+%d\n",regname[rt],offset);
2010 output_w32(0xe1c000b0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
2012 void emit_writebyte(int rt, int addr)
2014 u_int offset = addr-(u_int)&dynarec_local;
2015 assert(offset<4096);
2016 assem_debug("strb %s,fp+%d\n",regname[rt],offset);
2017 output_w32(0xe5c00000|rd_rn_rm(rt,FP,0)|offset);
2019 void emit_writeword_imm(int imm, int addr)
2021 assem_debug("movl $%x,%x\n",imm,addr);
2024 void emit_writebyte_imm(int imm, int addr)
2026 assem_debug("movb $%x,%x\n",imm,addr);
2030 void emit_mul(int rs)
2032 assem_debug("mul %%%s\n",regname[rs]);
2035 void emit_imul(int rs)
2037 assem_debug("imul %%%s\n",regname[rs]);
2040 void emit_umull(u_int rs1, u_int rs2, u_int hi, u_int lo)
2042 assem_debug("umull %s, %s, %s, %s\n",regname[lo],regname[hi],regname[rs1],regname[rs2]);
2047 output_w32(0xe0800090|(hi<<16)|(lo<<12)|(rs2<<8)|rs1);
2049 void emit_smull(u_int rs1, u_int rs2, u_int hi, u_int lo)
2051 assem_debug("smull %s, %s, %s, %s\n",regname[lo],regname[hi],regname[rs1],regname[rs2]);
2056 output_w32(0xe0c00090|(hi<<16)|(lo<<12)|(rs2<<8)|rs1);
2059 void emit_div(int rs)
2061 assem_debug("div %%%s\n",regname[rs]);
2064 void emit_idiv(int rs)
2066 assem_debug("idiv %%%s\n",regname[rs]);
2071 assem_debug("cdq\n");
2075 void emit_clz(int rs,int rt)
2077 assem_debug("clz %s,%s\n",regname[rt],regname[rs]);
2078 output_w32(0xe16f0f10|rd_rn_rm(rt,0,rs));
2081 void emit_subcs(int rs1,int rs2,int rt)
2083 assem_debug("subcs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2084 output_w32(0x20400000|rd_rn_rm(rt,rs1,rs2));
2087 void emit_shrcc_imm(int rs,u_int imm,int rt)
2091 assem_debug("lsrcc %s,%s,#%d\n",regname[rt],regname[rs],imm);
2092 output_w32(0x31a00000|rd_rn_rm(rt,0,rs)|0x20|(imm<<7));
2095 void emit_negmi(int rs, int rt)
2097 assem_debug("rsbmi %s,%s,#0\n",regname[rt],regname[rs]);
2098 output_w32(0x42600000|rd_rn_rm(rt,rs,0));
2101 void emit_negsmi(int rs, int rt)
2103 assem_debug("rsbsmi %s,%s,#0\n",regname[rt],regname[rs]);
2104 output_w32(0x42700000|rd_rn_rm(rt,rs,0));
2107 void emit_orreq(u_int rs1,u_int rs2,u_int rt)
2109 assem_debug("orreq %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2110 output_w32(0x01800000|rd_rn_rm(rt,rs1,rs2));
2113 void emit_orrne(u_int rs1,u_int rs2,u_int rt)
2115 assem_debug("orrne %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2116 output_w32(0x11800000|rd_rn_rm(rt,rs1,rs2));
2119 void emit_bic_lsl(u_int rs1,u_int rs2,u_int shift,u_int rt)
2121 assem_debug("bic %s,%s,%s lsl %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2122 output_w32(0xe1C00000|rd_rn_rm(rt,rs1,rs2)|0x10|(shift<<8));
2125 void emit_biceq_lsl(u_int rs1,u_int rs2,u_int shift,u_int rt)
2127 assem_debug("biceq %s,%s,%s lsl %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2128 output_w32(0x01C00000|rd_rn_rm(rt,rs1,rs2)|0x10|(shift<<8));
2131 void emit_bicne_lsl(u_int rs1,u_int rs2,u_int shift,u_int rt)
2133 assem_debug("bicne %s,%s,%s lsl %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2134 output_w32(0x11C00000|rd_rn_rm(rt,rs1,rs2)|0x10|(shift<<8));
2137 void emit_bic_lsr(u_int rs1,u_int rs2,u_int shift,u_int rt)
2139 assem_debug("bic %s,%s,%s lsr %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2140 output_w32(0xe1C00000|rd_rn_rm(rt,rs1,rs2)|0x30|(shift<<8));
2143 void emit_biceq_lsr(u_int rs1,u_int rs2,u_int shift,u_int rt)
2145 assem_debug("biceq %s,%s,%s lsr %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2146 output_w32(0x01C00000|rd_rn_rm(rt,rs1,rs2)|0x30|(shift<<8));
2149 void emit_bicne_lsr(u_int rs1,u_int rs2,u_int shift,u_int rt)
2151 assem_debug("bicne %s,%s,%s lsr %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2152 output_w32(0x11C00000|rd_rn_rm(rt,rs1,rs2)|0x30|(shift<<8));
2155 void emit_teq(int rs, int rt)
2157 assem_debug("teq %s,%s\n",regname[rs],regname[rt]);
2158 output_w32(0xe1300000|rd_rn_rm(0,rs,rt));
2161 void emit_rsbimm(int rs, int imm, int rt)
2164 genimm_checked(imm,&armval);
2165 assem_debug("rsb %s,%s,#%d\n",regname[rt],regname[rs],imm);
2166 output_w32(0xe2600000|rd_rn_rm(rt,rs,0)|armval);
2169 // Load 2 immediates optimizing for small code size
2170 void emit_mov2imm_compact(int imm1,u_int rt1,int imm2,u_int rt2)
2172 emit_movimm(imm1,rt1);
2174 if(genimm(imm2-imm1,&armval)) {
2175 assem_debug("add %s,%s,#%d\n",regname[rt2],regname[rt1],imm2-imm1);
2176 output_w32(0xe2800000|rd_rn_rm(rt2,rt1,0)|armval);
2177 }else if(genimm(imm1-imm2,&armval)) {
2178 assem_debug("sub %s,%s,#%d\n",regname[rt2],regname[rt1],imm1-imm2);
2179 output_w32(0xe2400000|rd_rn_rm(rt2,rt1,0)|armval);
2181 else emit_movimm(imm2,rt2);
2184 // Conditionally select one of two immediates, optimizing for small code size
2185 // This will only be called if HAVE_CMOV_IMM is defined
2186 void emit_cmov2imm_e_ne_compact(int imm1,int imm2,u_int rt)
2189 if(genimm(imm2-imm1,&armval)) {
2190 emit_movimm(imm1,rt);
2191 assem_debug("addne %s,%s,#%d\n",regname[rt],regname[rt],imm2-imm1);
2192 output_w32(0x12800000|rd_rn_rm(rt,rt,0)|armval);
2193 }else if(genimm(imm1-imm2,&armval)) {
2194 emit_movimm(imm1,rt);
2195 assem_debug("subne %s,%s,#%d\n",regname[rt],regname[rt],imm1-imm2);
2196 output_w32(0x12400000|rd_rn_rm(rt,rt,0)|armval);
2200 emit_movimm(imm1,rt);
2201 add_literal((int)out,imm2);
2202 assem_debug("ldrne %s,pc+? [=%x]\n",regname[rt],imm2);
2203 output_w32(0x15900000|rd_rn_rm(rt,15,0));
2205 emit_movw(imm1&0x0000FFFF,rt);
2206 if((imm1&0xFFFF)!=(imm2&0xFFFF)) {
2207 assem_debug("movwne %s,#%d (0x%x)\n",regname[rt],imm2&0xFFFF,imm2&0xFFFF);
2208 output_w32(0x13000000|rd_rn_rm(rt,0,0)|(imm2&0xfff)|((imm2<<4)&0xf0000));
2210 emit_movt(imm1&0xFFFF0000,rt);
2211 if((imm1&0xFFFF0000)!=(imm2&0xFFFF0000)) {
2212 assem_debug("movtne %s,#%d (0x%x)\n",regname[rt],imm2&0xffff0000,imm2&0xffff0000);
2213 output_w32(0x13400000|rd_rn_rm(rt,0,0)|((imm2>>16)&0xfff)|((imm2>>12)&0xf0000));
2219 // special case for checking invalid_code
2220 void emit_cmpmem_indexedsr12_imm(int addr,int r,int imm)
2225 // special case for checking invalid_code
2226 void emit_cmpmem_indexedsr12_reg(int base,int r,int imm)
2228 assert(imm<128&&imm>=0);
2230 assem_debug("ldrb lr,%s,%s lsr #12\n",regname[base],regname[r]);
2231 output_w32(0xe7d00000|rd_rn_rm(HOST_TEMPREG,base,r)|0x620);
2232 emit_cmpimm(HOST_TEMPREG,imm);
2235 // special case for tlb mapping
2236 void emit_addsr12(int rs1,int rs2,int rt)
2238 assem_debug("add %s,%s,%s lsr #12\n",regname[rt],regname[rs1],regname[rs2]);
2239 output_w32(0xe0800620|rd_rn_rm(rt,rs1,rs2));
2242 void emit_callne(int a)
2244 assem_debug("blne %x\n",a);
2245 u_int offset=genjmp(a);
2246 output_w32(0x1b000000|offset);
2249 // Used to preload hash table entries
2250 void emit_prefetch(void *addr)
2252 assem_debug("prefetch %x\n",(int)addr);
2255 output_modrm(0,5,1);
2256 output_w32((int)addr);
2258 void emit_prefetchreg(int r)
2260 assem_debug("pld %s\n",regname[r]);
2261 output_w32(0xf5d0f000|rd_rn_rm(0,r,0));
2264 // Special case for mini_ht
2265 void emit_ldreq_indexed(int rs, u_int offset, int rt)
2267 assert(offset<4096);
2268 assem_debug("ldreq %s,[%s, #%d]\n",regname[rt],regname[rs],offset);
2269 output_w32(0x05900000|rd_rn_rm(rt,rs,0)|offset);
2272 void emit_flds(int r,int sr)
2274 assem_debug("flds s%d,[%s]\n",sr,regname[r]);
2275 output_w32(0xed900a00|((sr&14)<<11)|((sr&1)<<22)|(r<<16));
2278 void emit_vldr(int r,int vr)
2280 assem_debug("vldr d%d,[%s]\n",vr,regname[r]);
2281 output_w32(0xed900b00|(vr<<12)|(r<<16));
2284 void emit_fsts(int sr,int r)
2286 assem_debug("fsts s%d,[%s]\n",sr,regname[r]);
2287 output_w32(0xed800a00|((sr&14)<<11)|((sr&1)<<22)|(r<<16));
2290 void emit_vstr(int vr,int r)
2292 assem_debug("vstr d%d,[%s]\n",vr,regname[r]);
2293 output_w32(0xed800b00|(vr<<12)|(r<<16));
2296 void emit_ftosizs(int s,int d)
2298 assem_debug("ftosizs s%d,s%d\n",d,s);
2299 output_w32(0xeebd0ac0|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
2302 void emit_ftosizd(int s,int d)
2304 assem_debug("ftosizd s%d,d%d\n",d,s);
2305 output_w32(0xeebd0bc0|((d&14)<<11)|((d&1)<<22)|(s&7));
2308 void emit_fsitos(int s,int d)
2310 assem_debug("fsitos s%d,s%d\n",d,s);
2311 output_w32(0xeeb80ac0|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
2314 void emit_fsitod(int s,int d)
2316 assem_debug("fsitod d%d,s%d\n",d,s);
2317 output_w32(0xeeb80bc0|((d&7)<<12)|((s&14)>>1)|((s&1)<<5));
2320 void emit_fcvtds(int s,int d)
2322 assem_debug("fcvtds d%d,s%d\n",d,s);
2323 output_w32(0xeeb70ac0|((d&7)<<12)|((s&14)>>1)|((s&1)<<5));
2326 void emit_fcvtsd(int s,int d)
2328 assem_debug("fcvtsd s%d,d%d\n",d,s);
2329 output_w32(0xeeb70bc0|((d&14)<<11)|((d&1)<<22)|(s&7));
2332 void emit_fsqrts(int s,int d)
2334 assem_debug("fsqrts d%d,s%d\n",d,s);
2335 output_w32(0xeeb10ac0|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
2338 void emit_fsqrtd(int s,int d)
2340 assem_debug("fsqrtd s%d,d%d\n",d,s);
2341 output_w32(0xeeb10bc0|((d&7)<<12)|(s&7));
2344 void emit_fabss(int s,int d)
2346 assem_debug("fabss d%d,s%d\n",d,s);
2347 output_w32(0xeeb00ac0|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
2350 void emit_fabsd(int s,int d)
2352 assem_debug("fabsd s%d,d%d\n",d,s);
2353 output_w32(0xeeb00bc0|((d&7)<<12)|(s&7));
2356 void emit_fnegs(int s,int d)
2358 assem_debug("fnegs d%d,s%d\n",d,s);
2359 output_w32(0xeeb10a40|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
2362 void emit_fnegd(int s,int d)
2364 assem_debug("fnegd s%d,d%d\n",d,s);
2365 output_w32(0xeeb10b40|((d&7)<<12)|(s&7));
2368 void emit_fadds(int s1,int s2,int d)
2370 assem_debug("fadds s%d,s%d,s%d\n",d,s1,s2);
2371 output_w32(0xee300a00|((d&14)<<11)|((d&1)<<22)|((s1&14)<<15)|((s1&1)<<7)|((s2&14)>>1)|((s2&1)<<5));
2374 void emit_faddd(int s1,int s2,int d)
2376 assem_debug("faddd d%d,d%d,d%d\n",d,s1,s2);
2377 output_w32(0xee300b00|((d&7)<<12)|((s1&7)<<16)|(s2&7));
2380 void emit_fsubs(int s1,int s2,int d)
2382 assem_debug("fsubs s%d,s%d,s%d\n",d,s1,s2);
2383 output_w32(0xee300a40|((d&14)<<11)|((d&1)<<22)|((s1&14)<<15)|((s1&1)<<7)|((s2&14)>>1)|((s2&1)<<5));
2386 void emit_fsubd(int s1,int s2,int d)
2388 assem_debug("fsubd d%d,d%d,d%d\n",d,s1,s2);
2389 output_w32(0xee300b40|((d&7)<<12)|((s1&7)<<16)|(s2&7));
2392 void emit_fmuls(int s1,int s2,int d)
2394 assem_debug("fmuls s%d,s%d,s%d\n",d,s1,s2);
2395 output_w32(0xee200a00|((d&14)<<11)|((d&1)<<22)|((s1&14)<<15)|((s1&1)<<7)|((s2&14)>>1)|((s2&1)<<5));
2398 void emit_fmuld(int s1,int s2,int d)
2400 assem_debug("fmuld d%d,d%d,d%d\n",d,s1,s2);
2401 output_w32(0xee200b00|((d&7)<<12)|((s1&7)<<16)|(s2&7));
2404 void emit_fdivs(int s1,int s2,int d)
2406 assem_debug("fdivs s%d,s%d,s%d\n",d,s1,s2);
2407 output_w32(0xee800a00|((d&14)<<11)|((d&1)<<22)|((s1&14)<<15)|((s1&1)<<7)|((s2&14)>>1)|((s2&1)<<5));
2410 void emit_fdivd(int s1,int s2,int d)
2412 assem_debug("fdivd d%d,d%d,d%d\n",d,s1,s2);
2413 output_w32(0xee800b00|((d&7)<<12)|((s1&7)<<16)|(s2&7));
2416 void emit_fcmps(int x,int y)
2418 assem_debug("fcmps s14, s15\n");
2419 output_w32(0xeeb47a67);
2422 void emit_fcmpd(int x,int y)
2424 assem_debug("fcmpd d6, d7\n");
2425 output_w32(0xeeb46b47);
2430 assem_debug("fmstat\n");
2431 output_w32(0xeef1fa10);
2434 void emit_bicne_imm(int rs,int imm,int rt)
2437 genimm_checked(imm,&armval);
2438 assem_debug("bicne %s,%s,#%d\n",regname[rt],regname[rs],imm);
2439 output_w32(0x13c00000|rd_rn_rm(rt,rs,0)|armval);
2442 void emit_biccs_imm(int rs,int imm,int rt)
2445 genimm_checked(imm,&armval);
2446 assem_debug("biccs %s,%s,#%d\n",regname[rt],regname[rs],imm);
2447 output_w32(0x23c00000|rd_rn_rm(rt,rs,0)|armval);
2450 void emit_bicvc_imm(int rs,int imm,int rt)
2453 genimm_checked(imm,&armval);
2454 assem_debug("bicvc %s,%s,#%d\n",regname[rt],regname[rs],imm);
2455 output_w32(0x73c00000|rd_rn_rm(rt,rs,0)|armval);
2458 void emit_bichi_imm(int rs,int imm,int rt)
2461 genimm_checked(imm,&armval);
2462 assem_debug("bichi %s,%s,#%d\n",regname[rt],regname[rs],imm);
2463 output_w32(0x83c00000|rd_rn_rm(rt,rs,0)|armval);
2466 void emit_orrvs_imm(int rs,int imm,int rt)
2469 genimm_checked(imm,&armval);
2470 assem_debug("orrvs %s,%s,#%d\n",regname[rt],regname[rs],imm);
2471 output_w32(0x63800000|rd_rn_rm(rt,rs,0)|armval);
2474 void emit_orrne_imm(int rs,int imm,int rt)
2477 genimm_checked(imm,&armval);
2478 assem_debug("orrne %s,%s,#%d\n",regname[rt],regname[rs],imm);
2479 output_w32(0x13800000|rd_rn_rm(rt,rs,0)|armval);
2482 void emit_andne_imm(int rs,int imm,int rt)
2485 genimm_checked(imm,&armval);
2486 assem_debug("andne %s,%s,#%d\n",regname[rt],regname[rs],imm);
2487 output_w32(0x12000000|rd_rn_rm(rt,rs,0)|armval);
2490 void emit_jno_unlikely(int a)
2493 assem_debug("addvc pc,pc,#? (%x)\n",/*a-(int)out-8,*/a);
2494 output_w32(0x72800000|rd_rn_rm(15,15,0));
2497 // Save registers before function call
2498 void save_regs(u_int reglist)
2500 reglist&=0x100f; // only save the caller-save registers, r0-r3, r12
2501 if(!reglist) return;
2502 assem_debug("stmia fp,{");
2503 if(reglist&1) assem_debug("r0, ");
2504 if(reglist&2) assem_debug("r1, ");
2505 if(reglist&4) assem_debug("r2, ");
2506 if(reglist&8) assem_debug("r3, ");
2507 if(reglist&0x1000) assem_debug("r12");
2509 output_w32(0xe88b0000|reglist);
2511 // Restore registers after function call
2512 void restore_regs(u_int reglist)
2514 reglist&=0x100f; // only restore the caller-save registers, r0-r3, r12
2515 if(!reglist) return;
2516 assem_debug("ldmia fp,{");
2517 if(reglist&1) assem_debug("r0, ");
2518 if(reglist&2) assem_debug("r1, ");
2519 if(reglist&4) assem_debug("r2, ");
2520 if(reglist&8) assem_debug("r3, ");
2521 if(reglist&0x1000) assem_debug("r12");
2523 output_w32(0xe89b0000|reglist);
2526 // Write back consts using r14 so we don't disturb the other registers
2527 void wb_consts(signed char i_regmap[],uint64_t i_is32,u_int i_dirty,int i)
2530 for(hr=0;hr<HOST_REGS;hr++) {
2531 if(hr!=EXCLUDE_REG&&i_regmap[hr]>=0&&((i_dirty>>hr)&1)) {
2532 if(((regs[i].isconst>>hr)&1)&&i_regmap[hr]>0) {
2533 if(i_regmap[hr]<64 || !((i_is32>>(i_regmap[hr]&63))&1) ) {
2534 int value=constmap[i][hr];
2536 emit_zeroreg(HOST_TEMPREG);
2539 emit_movimm(value,HOST_TEMPREG);
2541 emit_storereg(i_regmap[hr],HOST_TEMPREG);
2543 if((i_is32>>i_regmap[hr])&1) {
2544 if(value!=-1&&value!=0) emit_sarimm(HOST_TEMPREG,31,HOST_TEMPREG);
2545 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
2554 /* Stubs/epilogue */
2556 void literal_pool(int n)
2558 if(!literalcount) return;
2560 if((int)out-literals[0][0]<4096-n) return;
2564 for(i=0;i<literalcount;i++)
2566 ptr=(u_int *)literals[i][0];
2567 u_int offset=(u_int)out-(u_int)ptr-8;
2568 assert(offset<4096);
2569 assert(!(offset&3));
2571 output_w32(literals[i][1]);
2576 void literal_pool_jumpover(int n)
2578 if(!literalcount) return;
2580 if((int)out-literals[0][0]<4096-n) return;
2585 set_jump_target(jaddr,(int)out);
2588 emit_extjump2(int addr, int target, int linker)
2590 u_char *ptr=(u_char *)addr;
2591 assert((ptr[3]&0x0e)==0xa);
2592 emit_loadlp(target,0);
2593 emit_loadlp(addr,1);
2594 assert(addr>=BASE_ADDR&&addr<(BASE_ADDR+(1<<TARGET_SIZE_2)));
2595 //assert((target>=0x80000000&&target<0x80800000)||(target>0xA4000000&&target<0xA4001000));
2597 #ifdef DEBUG_CYCLE_COUNT
2598 emit_readword((int)&last_count,ECX);
2599 emit_add(HOST_CCREG,ECX,HOST_CCREG);
2600 emit_readword((int)&next_interupt,ECX);
2601 emit_writeword(HOST_CCREG,(int)&Count);
2602 emit_sub(HOST_CCREG,ECX,HOST_CCREG);
2603 emit_writeword(ECX,(int)&last_count);
2609 emit_extjump(int addr, int target)
2611 emit_extjump2(addr, target, (int)dyna_linker);
2613 emit_extjump_ds(int addr, int target)
2615 emit_extjump2(addr, target, (int)dyna_linker_ds);
2619 #include "pcsxmem_inline.c"
2624 assem_debug("do_readstub %x\n",start+stubs[n][3]*4);
2626 set_jump_target(stubs[n][1],(int)out);
2627 int type=stubs[n][0];
2630 struct regstat *i_regs=(struct regstat *)stubs[n][5];
2631 u_int reglist=stubs[n][7];
2632 signed char *i_regmap=i_regs->regmap;
2633 int addr=get_reg(i_regmap,AGEN1+(i&1));
2636 if(itype[i]==C1LS||itype[i]==C2LS||itype[i]==LOADLR) {
2637 rth=get_reg(i_regmap,FTEMP|64);
2638 rt=get_reg(i_regmap,FTEMP);
2640 rth=get_reg(i_regmap,rt1[i]|64);
2641 rt=get_reg(i_regmap,rt1[i]);
2645 if(addr<0&&itype[i]!=C1LS&&itype[i]!=C2LS&&itype[i]!=LOADLR) addr=get_reg(i_regmap,-1);
2648 if(type==LOADB_STUB||type==LOADBU_STUB)
2649 ftable=(int)readmemb;
2650 if(type==LOADH_STUB||type==LOADHU_STUB)
2651 ftable=(int)readmemh;
2652 if(type==LOADW_STUB)
2653 ftable=(int)readmem;
2655 if(type==LOADD_STUB)
2656 ftable=(int)readmemd;
2659 emit_writeword(rs,(int)&address);
2663 ds=i_regs!=®s[i];
2664 int real_rs=(itype[i]==LOADLR)?-1:get_reg(i_regmap,rs1[i]);
2665 u_int cmask=ds?-1:(0x100f|~i_regs->wasconst);
2666 if(!ds) load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&0x100f,i);
2667 wb_dirtys(i_regs->regmap_entry,i_regs->was32,i_regs->wasdirty&cmask&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs)));
2668 if(!ds) wb_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&~0x100f,i);
2670 emit_shrimm(rs,16,1);
2671 int cc=get_reg(i_regmap,CCREG);
2673 emit_loadreg(CCREG,2);
2675 emit_movimm(ftable,0);
2676 emit_addimm(cc<0?2:cc,2*stubs[n][6]+2,2);
2678 emit_movimm(start+stubs[n][3]*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3);
2680 //emit_readword((int)&last_count,temp);
2681 //emit_add(cc,temp,cc);
2682 //emit_writeword(cc,(int)&Count);
2684 emit_call((int)&indirect_jump_indexed);
2686 //emit_readword_dualindexedx4(rs,HOST_TEMPREG,15);
2688 // We really shouldn't need to update the count here,
2689 // but not doing so causes random crashes...
2690 emit_readword((int)&Count,HOST_TEMPREG);
2691 emit_readword((int)&next_interupt,2);
2692 emit_addimm(HOST_TEMPREG,-2*stubs[n][6]-2,HOST_TEMPREG);
2693 emit_writeword(2,(int)&last_count);
2694 emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
2696 emit_storereg(CCREG,HOST_TEMPREG);
2700 restore_regs(reglist);
2701 //if((cc=get_reg(regmap,CCREG))>=0) {
2702 // emit_loadreg(CCREG,cc);
2704 if(itype[i]==C1LS||itype[i]==C2LS||(rt>=0&&rt1[i]!=0)) {
2706 if(type==LOADB_STUB)
2707 emit_movsbl((int)&readmem_dword,rt);
2708 if(type==LOADBU_STUB)
2709 emit_movzbl((int)&readmem_dword,rt);
2710 if(type==LOADH_STUB)
2711 emit_movswl((int)&readmem_dword,rt);
2712 if(type==LOADHU_STUB)
2713 emit_movzwl((int)&readmem_dword,rt);
2714 if(type==LOADW_STUB)
2715 emit_readword((int)&readmem_dword,rt);
2716 if(type==LOADD_STUB) {
2717 emit_readword((int)&readmem_dword,rt);
2718 if(rth>=0) emit_readword(((int)&readmem_dword)+4,rth);
2721 emit_jmp(stubs[n][2]); // return address
2724 inline_readstub(int type, int i, u_int addr, signed char regmap[], int target, int adj, u_int reglist)
2726 int rs=get_reg(regmap,target);
2727 int rth=get_reg(regmap,target|64);
2728 int rt=get_reg(regmap,target);
2729 if(rs<0) rs=get_reg(regmap,-1);
2732 if(type==LOADB_STUB||type==LOADBU_STUB)
2733 ftable=(int)readmemb;
2734 if(type==LOADH_STUB||type==LOADHU_STUB)
2735 ftable=(int)readmemh;
2736 if(type==LOADW_STUB)
2737 ftable=(int)readmem;
2739 if(type==LOADD_STUB)
2740 ftable=(int)readmemd;
2744 if(pcsx_direct_read(type,addr,target?rs:-1,rt))
2748 emit_movimm(addr,rs);
2749 emit_writeword(rs,(int)&address);
2753 if((signed int)addr>=(signed int)0xC0000000) {
2754 // Theoretically we can have a pagefault here, if the TLB has never
2755 // been enabled and the address is outside the range 80000000..BFFFFFFF
2756 // Write out the registers so the pagefault can be handled. This is
2757 // a very rare case and likely represents a bug.
2758 int ds=regmap!=regs[i].regmap;
2759 if(!ds) load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty,i);
2760 if(!ds) wb_dirtys(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty);
2761 else wb_dirtys(branch_regs[i-1].regmap_entry,branch_regs[i-1].was32,branch_regs[i-1].wasdirty);
2764 //emit_shrimm(rs,16,1);
2765 int cc=get_reg(regmap,CCREG);
2767 emit_loadreg(CCREG,2);
2769 //emit_movimm(ftable,0);
2770 emit_movimm(((u_int *)ftable)[addr>>16],0);
2771 //emit_readword((int)&last_count,12);
2772 emit_addimm(cc<0?2:cc,CLOCK_DIVIDER*(adj+1),2);
2774 if((signed int)addr>=(signed int)0xC0000000) {
2775 // Pagefault address
2776 int ds=regmap!=regs[i].regmap;
2777 emit_movimm(start+i*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3);
2781 //emit_writeword(2,(int)&Count);
2782 //emit_call(((u_int *)ftable)[addr>>16]);
2783 emit_call((int)&indirect_jump);
2785 // We really shouldn't need to update the count here,
2786 // but not doing so causes random crashes...
2787 emit_readword((int)&Count,HOST_TEMPREG);
2788 emit_readword((int)&next_interupt,2);
2789 emit_addimm(HOST_TEMPREG,-CLOCK_DIVIDER*(adj+1),HOST_TEMPREG);
2790 emit_writeword(2,(int)&last_count);
2791 emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
2793 emit_storereg(CCREG,HOST_TEMPREG);
2797 restore_regs(reglist);
2799 if(type==LOADB_STUB)
2800 emit_movsbl((int)&readmem_dword,rt);
2801 if(type==LOADBU_STUB)
2802 emit_movzbl((int)&readmem_dword,rt);
2803 if(type==LOADH_STUB)
2804 emit_movswl((int)&readmem_dword,rt);
2805 if(type==LOADHU_STUB)
2806 emit_movzwl((int)&readmem_dword,rt);
2807 if(type==LOADW_STUB)
2808 emit_readword((int)&readmem_dword,rt);
2809 if(type==LOADD_STUB) {
2810 emit_readword((int)&readmem_dword,rt);
2811 if(rth>=0) emit_readword(((int)&readmem_dword)+4,rth);
2818 assem_debug("do_writestub %x\n",start+stubs[n][3]*4);
2820 set_jump_target(stubs[n][1],(int)out);
2821 int type=stubs[n][0];
2824 struct regstat *i_regs=(struct regstat *)stubs[n][5];
2825 u_int reglist=stubs[n][7];
2826 signed char *i_regmap=i_regs->regmap;
2827 int addr=get_reg(i_regmap,AGEN1+(i&1));
2830 if(itype[i]==C1LS||itype[i]==C2LS) {
2831 rth=get_reg(i_regmap,FTEMP|64);
2832 rt=get_reg(i_regmap,r=FTEMP);
2834 rth=get_reg(i_regmap,rs2[i]|64);
2835 rt=get_reg(i_regmap,r=rs2[i]);
2839 if(addr<0) addr=get_reg(i_regmap,-1);
2842 if(type==STOREB_STUB)
2843 ftable=(int)writememb;
2844 if(type==STOREH_STUB)
2845 ftable=(int)writememh;
2846 if(type==STOREW_STUB)
2847 ftable=(int)writemem;
2849 if(type==STORED_STUB)
2850 ftable=(int)writememd;
2853 emit_writeword(rs,(int)&address);
2854 //emit_shrimm(rs,16,rs);
2855 //emit_movmem_indexedx4(ftable,rs,rs);
2856 if(type==STOREB_STUB)
2857 emit_writebyte(rt,(int)&byte);
2858 if(type==STOREH_STUB)
2859 emit_writehword(rt,(int)&hword);
2860 if(type==STOREW_STUB)
2861 emit_writeword(rt,(int)&word);
2862 if(type==STORED_STUB) {
2864 emit_writeword(rt,(int)&dword);
2865 emit_writeword(r?rth:rt,(int)&dword+4);
2867 printf("STORED_STUB\n");
2873 ds=i_regs!=®s[i];
2874 int real_rs=get_reg(i_regmap,rs1[i]);
2875 u_int cmask=ds?-1:(0x100f|~i_regs->wasconst);
2876 if(!ds) load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&0x100f,i);
2877 wb_dirtys(i_regs->regmap_entry,i_regs->was32,i_regs->wasdirty&cmask&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs)));
2878 if(!ds) wb_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&~0x100f,i);
2880 emit_shrimm(rs,16,1);
2881 int cc=get_reg(i_regmap,CCREG);
2883 emit_loadreg(CCREG,2);
2885 emit_movimm(ftable,0);
2886 emit_addimm(cc<0?2:cc,2*stubs[n][6]+2,2);
2888 emit_movimm(start+stubs[n][3]*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3);
2890 //emit_readword((int)&last_count,temp);
2891 //emit_addimm(cc,2*stubs[n][5]+2,cc);
2892 //emit_add(cc,temp,cc);
2893 //emit_writeword(cc,(int)&Count);
2894 emit_call((int)&indirect_jump_indexed);
2896 emit_readword((int)&Count,HOST_TEMPREG);
2897 emit_readword((int)&next_interupt,2);
2898 emit_addimm(HOST_TEMPREG,-2*stubs[n][6]-2,HOST_TEMPREG);
2899 emit_writeword(2,(int)&last_count);
2900 emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
2902 emit_storereg(CCREG,HOST_TEMPREG);
2905 restore_regs(reglist);
2906 //if((cc=get_reg(regmap,CCREG))>=0) {
2907 // emit_loadreg(CCREG,cc);
2909 emit_jmp(stubs[n][2]); // return address
2912 inline_writestub(int type, int i, u_int addr, signed char regmap[], int target, int adj, u_int reglist)
2914 int rs=get_reg(regmap,-1);
2915 int rth=get_reg(regmap,target|64);
2916 int rt=get_reg(regmap,target);
2920 if(pcsx_direct_write(type,addr,rs,rt,regmap))
2924 if(type==STOREB_STUB)
2925 ftable=(int)writememb;
2926 if(type==STOREH_STUB)
2927 ftable=(int)writememh;
2928 if(type==STOREW_STUB)
2929 ftable=(int)writemem;
2931 if(type==STORED_STUB)
2932 ftable=(int)writememd;
2935 emit_writeword(rs,(int)&address);
2936 //emit_shrimm(rs,16,rs);
2937 //emit_movmem_indexedx4(ftable,rs,rs);
2938 if(type==STOREB_STUB)
2939 emit_writebyte(rt,(int)&byte);
2940 if(type==STOREH_STUB)
2941 emit_writehword(rt,(int)&hword);
2942 if(type==STOREW_STUB)
2943 emit_writeword(rt,(int)&word);
2944 if(type==STORED_STUB) {
2946 emit_writeword(rt,(int)&dword);
2947 emit_writeword(target?rth:rt,(int)&dword+4);
2949 printf("STORED_STUB\n");
2955 // rearmed note: load_all_consts prevents BIOS boot, some bug?
2956 if((signed int)addr>=(signed int)0xC0000000) {
2957 // Theoretically we can have a pagefault here, if the TLB has never
2958 // been enabled and the address is outside the range 80000000..BFFFFFFF
2959 // Write out the registers so the pagefault can be handled. This is
2960 // a very rare case and likely represents a bug.
2961 int ds=regmap!=regs[i].regmap;
2962 if(!ds) load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty,i);
2963 if(!ds) wb_dirtys(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty);
2964 else wb_dirtys(branch_regs[i-1].regmap_entry,branch_regs[i-1].was32,branch_regs[i-1].wasdirty);
2967 //emit_shrimm(rs,16,1);
2968 int cc=get_reg(regmap,CCREG);
2970 emit_loadreg(CCREG,2);
2972 //emit_movimm(ftable,0);
2973 emit_movimm(((u_int *)ftable)[addr>>16],0);
2974 //emit_readword((int)&last_count,12);
2975 emit_addimm(cc<0?2:cc,CLOCK_DIVIDER*(adj+1),2);
2977 if((signed int)addr>=(signed int)0xC0000000) {
2978 // Pagefault address
2979 int ds=regmap!=regs[i].regmap;
2980 emit_movimm(start+i*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3);
2984 //emit_writeword(2,(int)&Count);
2985 //emit_call(((u_int *)ftable)[addr>>16]);
2986 emit_call((int)&indirect_jump);
2987 emit_readword((int)&Count,HOST_TEMPREG);
2988 emit_readword((int)&next_interupt,2);
2989 emit_addimm(HOST_TEMPREG,-CLOCK_DIVIDER*(adj+1),HOST_TEMPREG);
2990 emit_writeword(2,(int)&last_count);
2991 emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
2993 emit_storereg(CCREG,HOST_TEMPREG);
2996 restore_regs(reglist);
2999 do_unalignedwritestub(int n)
3001 assem_debug("do_unalignedwritestub %x\n",start+stubs[n][3]*4);
3003 set_jump_target(stubs[n][1],(int)out);
3006 struct regstat *i_regs=(struct regstat *)stubs[n][4];
3007 int addr=stubs[n][5];
3008 u_int reglist=stubs[n][7];
3009 signed char *i_regmap=i_regs->regmap;
3010 int temp2=get_reg(i_regmap,FTEMP);
3013 rt=get_reg(i_regmap,rs2[i]);
3016 assert(opcode[i]==0x2a||opcode[i]==0x2e); // SWL/SWR only implemented
3018 reglist&=~(1<<temp2);
3020 emit_andimm(addr,0xfffffffc,temp2);
3021 emit_writeword(temp2,(int)&address);
3025 ds=i_regs!=®s[i];
3026 real_rs=get_reg(i_regmap,rs1[i]);
3027 u_int cmask=ds?-1:(0x100f|~i_regs->wasconst);
3028 if(!ds) load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&0x100f,i);
3029 wb_dirtys(i_regs->regmap_entry,i_regs->was32,i_regs->wasdirty&cmask&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs)));
3030 if(!ds) wb_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&~0x100f,i);
3032 emit_shrimm(addr,16,1);
3033 int cc=get_reg(i_regmap,CCREG);
3035 emit_loadreg(CCREG,2);
3037 emit_movimm((u_int)readmem,0);
3038 emit_addimm(cc<0?2:cc,2*stubs[n][6]+2,2);
3040 // pagefault address
3041 emit_movimm(start+stubs[n][3]*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3);
3043 emit_call((int)&indirect_jump_indexed);
3044 restore_regs(reglist);
3046 emit_readword((int)&readmem_dword,temp2);
3047 int temp=addr; //hmh
3048 emit_shlimm(addr,3,temp);
3049 emit_andimm(temp,24,temp);
3050 #ifdef BIG_ENDIAN_MIPS
3051 if (opcode[i]==0x2e) // SWR
3053 if (opcode[i]==0x2a) // SWL
3055 emit_xorimm(temp,24,temp);
3056 emit_movimm(-1,HOST_TEMPREG);
3057 if (opcode[i]==0x2a) { // SWL
3058 emit_bic_lsr(temp2,HOST_TEMPREG,temp,temp2);
3059 emit_orrshr(rt,temp,temp2);
3061 emit_bic_lsl(temp2,HOST_TEMPREG,temp,temp2);
3062 emit_orrshl(rt,temp,temp2);
3064 emit_readword((int)&address,addr);
3065 emit_writeword(temp2,(int)&word);
3066 //save_regs(reglist); // don't need to, no state changes
3067 emit_shrimm(addr,16,1);
3068 emit_movimm((u_int)writemem,0);
3069 //emit_call((int)&indirect_jump_indexed);
3071 emit_readword_dualindexedx4(0,1,15);
3072 emit_readword((int)&Count,HOST_TEMPREG);
3073 emit_readword((int)&next_interupt,2);
3074 emit_addimm(HOST_TEMPREG,-2*stubs[n][6]-2,HOST_TEMPREG);
3075 emit_writeword(2,(int)&last_count);
3076 emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
3078 emit_storereg(CCREG,HOST_TEMPREG);
3080 restore_regs(reglist);
3081 emit_jmp(stubs[n][2]); // return address
3084 void printregs(int edi,int esi,int ebp,int esp,int b,int d,int c,int a)
3086 printf("regs: %x %x %x %x %x %x %x (%x)\n",a,b,c,d,ebp,esi,edi,(&edi)[-1]);
3092 u_int reglist=stubs[n][3];
3093 set_jump_target(stubs[n][1],(int)out);
3095 if(stubs[n][4]!=0) emit_mov(stubs[n][4],0);
3096 emit_call((int)&invalidate_addr);
3097 restore_regs(reglist);
3098 emit_jmp(stubs[n][2]); // return address
3101 int do_dirty_stub(int i)
3103 assem_debug("do_dirty_stub %x\n",start+i*4);
3104 u_int addr=(int)start<(int)0xC0000000?(u_int)source:(u_int)start;
3108 // Careful about the code output here, verify_dirty needs to parse it.
3110 emit_loadlp(addr,1);
3111 emit_loadlp((int)copy,2);
3112 emit_loadlp(slen*4,3);
3114 emit_movw(addr&0x0000FFFF,1);
3115 emit_movw(((u_int)copy)&0x0000FFFF,2);
3116 emit_movt(addr&0xFFFF0000,1);
3117 emit_movt(((u_int)copy)&0xFFFF0000,2);
3118 emit_movw(slen*4,3);
3120 emit_movimm(start+i*4,0);
3121 emit_call((int)start<(int)0xC0000000?(int)&verify_code:(int)&verify_code_vm);
3124 if(entry==(int)out) entry=instr_addr[i];
3125 emit_jmp(instr_addr[i]);
3129 void do_dirty_stub_ds()
3131 // Careful about the code output here, verify_dirty needs to parse it.
3133 emit_loadlp((int)start<(int)0xC0000000?(int)source:(int)start,1);
3134 emit_loadlp((int)copy,2);
3135 emit_loadlp(slen*4,3);
3137 emit_movw(((int)start<(int)0xC0000000?(u_int)source:(u_int)start)&0x0000FFFF,1);
3138 emit_movw(((u_int)copy)&0x0000FFFF,2);
3139 emit_movt(((int)start<(int)0xC0000000?(u_int)source:(u_int)start)&0xFFFF0000,1);
3140 emit_movt(((u_int)copy)&0xFFFF0000,2);
3141 emit_movw(slen*4,3);
3143 emit_movimm(start+1,0);
3144 emit_call((int)&verify_code_ds);
3150 assem_debug("do_cop1stub %x\n",start+stubs[n][3]*4);
3151 set_jump_target(stubs[n][1],(int)out);
3153 // int rs=stubs[n][4];
3154 struct regstat *i_regs=(struct regstat *)stubs[n][5];
3157 load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty,i);
3158 //if(i_regs!=®s[i]) printf("oops: regs[i]=%x i_regs=%x",(int)®s[i],(int)i_regs);
3160 //else {printf("fp exception in delay slot\n");}
3161 wb_dirtys(i_regs->regmap_entry,i_regs->was32,i_regs->wasdirty);
3162 if(regs[i].regmap_entry[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
3163 emit_movimm(start+(i-ds)*4,EAX); // Get PC
3164 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
3165 emit_jmp(ds?(int)fp_exception_ds:(int)fp_exception);
3170 int do_tlb_r(int s,int ar,int map,int x,int a,int shift,int c,u_int addr)
3173 if((signed int)addr>=(signed int)0xC0000000) {
3174 // address_generation already loaded the const
3175 emit_readword_dualindexedx4(FP,map,map);
3178 return -1; // No mapping
3182 emit_movimm(((int)memory_map-(int)&dynarec_local)>>2,map);
3183 emit_addsr12(map,s,map);
3184 // Schedule this while we wait on the load
3185 //if(x) emit_xorimm(s,x,ar);
3186 if(shift>=0) emit_shlimm(s,3,shift);
3187 if(~a) emit_andimm(s,a,ar);
3188 emit_readword_dualindexedx4(FP,map,map);
3192 int do_tlb_r_branch(int map, int c, u_int addr, int *jaddr)
3194 if(!c||(signed int)addr>=(signed int)0xC0000000) {
3202 int gen_tlb_addr_r(int ar, int map) {
3204 assem_debug("add %s,%s,%s lsl #2\n",regname[ar],regname[ar],regname[map]);
3205 output_w32(0xe0800100|rd_rn_rm(ar,ar,map));
3209 int do_tlb_w(int s,int ar,int map,int x,int c,u_int addr)
3212 if(addr<0x80800000||addr>=0xC0000000) {
3213 // address_generation already loaded the const
3214 emit_readword_dualindexedx4(FP,map,map);
3217 return -1; // No mapping
3221 emit_movimm(((int)memory_map-(int)&dynarec_local)>>2,map);
3222 emit_addsr12(map,s,map);
3223 // Schedule this while we wait on the load
3224 //if(x) emit_xorimm(s,x,ar);
3225 emit_readword_dualindexedx4(FP,map,map);
3229 int do_tlb_w_branch(int map, int c, u_int addr, int *jaddr)
3231 if(!c||addr<0x80800000||addr>=0xC0000000) {
3232 emit_testimm(map,0x40000000);
3238 int gen_tlb_addr_w(int ar, int map) {
3240 assem_debug("add %s,%s,%s lsl #2\n",regname[ar],regname[ar],regname[map]);
3241 output_w32(0xe0800100|rd_rn_rm(ar,ar,map));
3245 // Generate the address of the memory_map entry, relative to dynarec_local
3246 generate_map_const(u_int addr,int reg) {
3247 //printf("generate_map_const(%x,%s)\n",addr,regname[reg]);
3248 emit_movimm((addr>>12)+(((u_int)memory_map-(u_int)&dynarec_local)>>2),reg);
3253 void shift_assemble_arm(int i,struct regstat *i_regs)
3256 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
3258 signed char s,t,shift;
3259 t=get_reg(i_regs->regmap,rt1[i]);
3260 s=get_reg(i_regs->regmap,rs1[i]);
3261 shift=get_reg(i_regs->regmap,rs2[i]);
3270 if(s!=t) emit_mov(s,t);
3274 emit_andimm(shift,31,HOST_TEMPREG);
3275 if(opcode2[i]==4) // SLLV
3277 emit_shl(s,HOST_TEMPREG,t);
3279 if(opcode2[i]==6) // SRLV
3281 emit_shr(s,HOST_TEMPREG,t);
3283 if(opcode2[i]==7) // SRAV
3285 emit_sar(s,HOST_TEMPREG,t);
3289 } else { // DSLLV/DSRLV/DSRAV
3290 signed char sh,sl,th,tl,shift;
3291 th=get_reg(i_regs->regmap,rt1[i]|64);
3292 tl=get_reg(i_regs->regmap,rt1[i]);
3293 sh=get_reg(i_regs->regmap,rs1[i]|64);
3294 sl=get_reg(i_regs->regmap,rs1[i]);
3295 shift=get_reg(i_regs->regmap,rs2[i]);
3300 if(th>=0) emit_zeroreg(th);
3305 if(sl!=tl) emit_mov(sl,tl);
3306 if(th>=0&&sh!=th) emit_mov(sh,th);
3310 // FIXME: What if shift==tl ?
3312 int temp=get_reg(i_regs->regmap,-1);
3314 if(th<0&&opcode2[i]!=0x14) {th=temp;} // DSLLV doesn't need a temporary register
3317 emit_andimm(shift,31,HOST_TEMPREG);
3318 if(opcode2[i]==0x14) // DSLLV
3320 if(th>=0) emit_shl(sh,HOST_TEMPREG,th);
3321 emit_rsbimm(HOST_TEMPREG,32,HOST_TEMPREG);
3322 emit_orrshr(sl,HOST_TEMPREG,th);
3323 emit_andimm(shift,31,HOST_TEMPREG);
3324 emit_testimm(shift,32);
3325 emit_shl(sl,HOST_TEMPREG,tl);
3326 if(th>=0) emit_cmovne_reg(tl,th);
3327 emit_cmovne_imm(0,tl);
3329 if(opcode2[i]==0x16) // DSRLV
3332 emit_shr(sl,HOST_TEMPREG,tl);
3333 emit_rsbimm(HOST_TEMPREG,32,HOST_TEMPREG);
3334 emit_orrshl(sh,HOST_TEMPREG,tl);
3335 emit_andimm(shift,31,HOST_TEMPREG);
3336 emit_testimm(shift,32);
3337 emit_shr(sh,HOST_TEMPREG,th);
3338 emit_cmovne_reg(th,tl);
3339 if(real_th>=0) emit_cmovne_imm(0,th);
3341 if(opcode2[i]==0x17) // DSRAV
3344 emit_shr(sl,HOST_TEMPREG,tl);
3345 emit_rsbimm(HOST_TEMPREG,32,HOST_TEMPREG);
3348 emit_sarimm(th,31,temp);
3350 emit_orrshl(sh,HOST_TEMPREG,tl);
3351 emit_andimm(shift,31,HOST_TEMPREG);
3352 emit_testimm(shift,32);
3353 emit_sar(sh,HOST_TEMPREG,th);
3354 emit_cmovne_reg(th,tl);
3355 if(real_th>=0) emit_cmovne_reg(temp,th);
3362 #define shift_assemble shift_assemble_arm
3364 void loadlr_assemble_arm(int i,struct regstat *i_regs)
3366 int s,th,tl,temp,temp2,addr,map=-1;
3369 int memtarget=0,c=0;
3371 th=get_reg(i_regs->regmap,rt1[i]|64);
3372 tl=get_reg(i_regs->regmap,rt1[i]);
3373 s=get_reg(i_regs->regmap,rs1[i]);
3374 temp=get_reg(i_regs->regmap,-1);
3375 temp2=get_reg(i_regs->regmap,FTEMP);
3376 addr=get_reg(i_regs->regmap,AGEN1+(i&1));
3379 for(hr=0;hr<HOST_REGS;hr++) {
3380 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3383 if(offset||s<0||c) addr=temp2;
3386 c=(i_regs->wasconst>>s)&1;
3388 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3389 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3395 map=get_reg(i_regs->regmap,ROREG);
3396 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3398 emit_shlimm(addr,3,temp);
3399 if (opcode[i]==0x22||opcode[i]==0x26) {
3400 emit_andimm(addr,0xFFFFFFFC,temp2); // LWL/LWR
3402 emit_andimm(addr,0xFFFFFFF8,temp2); // LDL/LDR
3404 emit_cmpimm(addr,RAM_SIZE);
3409 if (opcode[i]==0x22||opcode[i]==0x26) {
3410 emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR
3412 emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR
3419 }else if (opcode[i]==0x22||opcode[i]==0x26) {
3420 a=0xFFFFFFFC; // LWL/LWR
3422 a=0xFFFFFFF8; // LDL/LDR
3424 map=get_reg(i_regs->regmap,TLREG);
3427 map=do_tlb_r(addr,temp2,map,0,a,c?-1:temp,c,constmap[i][s]+offset);
3429 if (opcode[i]==0x22||opcode[i]==0x26) {
3430 emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR
3432 emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR
3435 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
3437 if (opcode[i]==0x22||opcode[i]==0x26) { // LWL/LWR
3439 //emit_readword_indexed((int)rdram-0x80000000,temp2,temp2);
3440 emit_readword_indexed_tlb(0,temp2,map,temp2);
3441 if(jaddr) add_stub(LOADW_STUB,jaddr,(int)out,i,temp2,(int)i_regs,ccadj[i],reglist);
3444 inline_readstub(LOADW_STUB,i,(constmap[i][s]+offset)&0xFFFFFFFC,i_regs->regmap,FTEMP,ccadj[i],reglist);
3447 emit_andimm(temp,24,temp);
3448 #ifdef BIG_ENDIAN_MIPS
3449 if (opcode[i]==0x26) // LWR
3451 if (opcode[i]==0x22) // LWL
3453 emit_xorimm(temp,24,temp);
3454 emit_movimm(-1,HOST_TEMPREG);
3455 if (opcode[i]==0x26) {
3456 emit_shr(temp2,temp,temp2);
3457 emit_bic_lsr(tl,HOST_TEMPREG,temp,tl);
3459 emit_shl(temp2,temp,temp2);
3460 emit_bic_lsl(tl,HOST_TEMPREG,temp,tl);
3462 emit_or(temp2,tl,tl);
3464 //emit_storereg(rt1[i],tl); // DEBUG
3466 if (opcode[i]==0x1A||opcode[i]==0x1B) { // LDL/LDR
3467 // FIXME: little endian
3468 int temp2h=get_reg(i_regs->regmap,FTEMP|64);
3470 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,temp2,temp2h);
3471 //emit_readword_indexed((int)rdram-0x7FFFFFFC,temp2,temp2);
3472 emit_readdword_indexed_tlb(0,temp2,map,temp2h,temp2);
3473 if(jaddr) add_stub(LOADD_STUB,jaddr,(int)out,i,temp2,(int)i_regs,ccadj[i],reglist);
3476 inline_readstub(LOADD_STUB,i,(constmap[i][s]+offset)&0xFFFFFFF8,i_regs->regmap,FTEMP,ccadj[i],reglist);
3480 emit_testimm(temp,32);
3481 emit_andimm(temp,24,temp);
3482 if (opcode[i]==0x1A) { // LDL
3483 emit_rsbimm(temp,32,HOST_TEMPREG);
3484 emit_shl(temp2h,temp,temp2h);
3485 emit_orrshr(temp2,HOST_TEMPREG,temp2h);
3486 emit_movimm(-1,HOST_TEMPREG);
3487 emit_shl(temp2,temp,temp2);
3488 emit_cmove_reg(temp2h,th);
3489 emit_biceq_lsl(tl,HOST_TEMPREG,temp,tl);
3490 emit_bicne_lsl(th,HOST_TEMPREG,temp,th);
3491 emit_orreq(temp2,tl,tl);
3492 emit_orrne(temp2,th,th);
3494 if (opcode[i]==0x1B) { // LDR
3495 emit_xorimm(temp,24,temp);
3496 emit_rsbimm(temp,32,HOST_TEMPREG);
3497 emit_shr(temp2,temp,temp2);
3498 emit_orrshl(temp2h,HOST_TEMPREG,temp2);
3499 emit_movimm(-1,HOST_TEMPREG);
3500 emit_shr(temp2h,temp,temp2h);
3501 emit_cmovne_reg(temp2,tl);
3502 emit_bicne_lsr(th,HOST_TEMPREG,temp,th);
3503 emit_biceq_lsr(tl,HOST_TEMPREG,temp,tl);
3504 emit_orrne(temp2h,th,th);
3505 emit_orreq(temp2h,tl,tl);
3510 #define loadlr_assemble loadlr_assemble_arm
3512 void cop0_assemble(int i,struct regstat *i_regs)
3514 if(opcode2[i]==0) // MFC0
3516 signed char t=get_reg(i_regs->regmap,rt1[i]);
3517 char copr=(source[i]>>11)&0x1f;
3518 //assert(t>=0); // Why does this happen? OOT is weird
3519 if(t>=0&&rt1[i]!=0) {
3521 emit_addimm(FP,(int)&fake_pc-(int)&dynarec_local,0);
3522 emit_movimm((source[i]>>11)&0x1f,1);
3523 emit_writeword(0,(int)&PC);
3524 emit_writebyte(1,(int)&(fake_pc.f.r.nrd));
3526 emit_readword((int)&last_count,ECX);
3527 emit_loadreg(CCREG,HOST_CCREG); // TODO: do proper reg alloc
3528 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3529 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG);
3530 emit_writeword(HOST_CCREG,(int)&Count);
3532 emit_call((int)MFC0);
3533 emit_readword((int)&readmem_dword,t);
3535 emit_readword((int)®_cop0+copr*4,t);
3539 else if(opcode2[i]==4) // MTC0
3541 signed char s=get_reg(i_regs->regmap,rs1[i]);
3542 char copr=(source[i]>>11)&0x1f;
3544 emit_writeword(s,(int)&readmem_dword);
3545 wb_register(rs1[i],i_regs->regmap,i_regs->dirty,i_regs->is32);
3547 emit_addimm(FP,(int)&fake_pc-(int)&dynarec_local,0);
3548 emit_movimm((source[i]>>11)&0x1f,1);
3549 emit_writeword(0,(int)&PC);
3550 emit_writebyte(1,(int)&(fake_pc.f.r.nrd));
3552 if(copr==9||copr==11||copr==12||copr==13) {
3553 emit_readword((int)&last_count,ECX);
3554 emit_loadreg(CCREG,HOST_CCREG); // TODO: do proper reg alloc
3555 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3556 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG);
3557 emit_writeword(HOST_CCREG,(int)&Count);
3559 // What a mess. The status register (12) can enable interrupts,
3560 // so needs a special case to handle a pending interrupt.
3561 // The interrupt must be taken immediately, because a subsequent
3562 // instruction might disable interrupts again.
3563 if(copr==12||copr==13) {
3566 // burn cycles to cause cc_interrupt, which will
3567 // reschedule next_interupt. Relies on CCREG from above.
3568 assem_debug("MTC0 DS %d\n", copr);
3569 emit_writeword(HOST_CCREG,(int)&last_count);
3570 emit_movimm(0,HOST_CCREG);
3571 emit_storereg(CCREG,HOST_CCREG);
3572 emit_movimm(copr,0);
3573 emit_call((int)pcsx_mtc0_ds);
3577 emit_movimm(start+i*4+4,0);
3579 emit_writeword(0,(int)&pcaddr);
3580 emit_writeword(1,(int)&pending_exception);
3582 //else if(copr==12&&is_delayslot) emit_call((int)MTC0_R12);
3585 emit_movimm(copr,0);
3586 emit_call((int)pcsx_mtc0);
3588 emit_call((int)MTC0);
3590 if(copr==9||copr==11||copr==12||copr==13) {
3591 emit_readword((int)&Count,HOST_CCREG);
3592 emit_readword((int)&next_interupt,ECX);
3593 emit_addimm(HOST_CCREG,-CLOCK_DIVIDER*ccadj[i],HOST_CCREG);
3594 emit_sub(HOST_CCREG,ECX,HOST_CCREG);
3595 emit_writeword(ECX,(int)&last_count);
3596 emit_storereg(CCREG,HOST_CCREG);
3598 if(copr==12||copr==13) {
3599 assert(!is_delayslot);
3600 emit_readword((int)&pending_exception,14);
3602 emit_loadreg(rs1[i],s);
3603 if(get_reg(i_regs->regmap,rs1[i]|64)>=0)
3604 emit_loadreg(rs1[i]|64,get_reg(i_regs->regmap,rs1[i]|64));
3605 if(copr==12||copr==13) {
3607 emit_jne((int)&do_interrupt);
3613 assert(opcode2[i]==0x10);
3615 if((source[i]&0x3f)==0x01) // TLBR
3616 emit_call((int)TLBR);
3617 if((source[i]&0x3f)==0x02) // TLBWI
3618 emit_call((int)TLBWI_new);
3619 if((source[i]&0x3f)==0x06) { // TLBWR
3620 // The TLB entry written by TLBWR is dependent on the count,
3621 // so update the cycle count
3622 emit_readword((int)&last_count,ECX);
3623 if(i_regs->regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
3624 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3625 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG);
3626 emit_writeword(HOST_CCREG,(int)&Count);
3627 emit_call((int)TLBWR_new);
3629 if((source[i]&0x3f)==0x08) // TLBP
3630 emit_call((int)TLBP);
3633 if((source[i]&0x3f)==0x10) // RFE
3635 emit_readword((int)&Status,0);
3636 emit_andimm(0,0x3c,1);
3637 emit_andimm(0,~0xf,0);
3638 emit_orrshr_imm(1,2,0);
3639 emit_writeword(0,(int)&Status);
3642 if((source[i]&0x3f)==0x18) // ERET
3645 if(i_regs->regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
3646 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*count,HOST_CCREG); // TODO: Should there be an extra cycle here?
3647 emit_jmp((int)jump_eret);
3653 static void cop2_get_dreg(u_int copr,signed char tl,signed char temp)
3663 emit_readword((int)®_cop2d[copr],tl);
3664 emit_signextend16(tl,tl);
3665 emit_writeword(tl,(int)®_cop2d[copr]); // hmh
3672 emit_readword((int)®_cop2d[copr],tl);
3673 emit_andimm(tl,0xffff,tl);
3674 emit_writeword(tl,(int)®_cop2d[copr]);
3677 emit_readword((int)®_cop2d[14],tl); // SXY2
3678 emit_writeword(tl,(int)®_cop2d[copr]);
3682 emit_readword((int)®_cop2d[9],temp);
3683 emit_testimm(temp,0x8000); // do we need this?
3684 emit_andimm(temp,0xf80,temp);
3685 emit_andne_imm(temp,0,temp);
3686 emit_shrimm(temp,7,tl);
3687 emit_readword((int)®_cop2d[10],temp);
3688 emit_testimm(temp,0x8000);
3689 emit_andimm(temp,0xf80,temp);
3690 emit_andne_imm(temp,0,temp);
3691 emit_orrshr_imm(temp,2,tl);
3692 emit_readword((int)®_cop2d[11],temp);
3693 emit_testimm(temp,0x8000);
3694 emit_andimm(temp,0xf80,temp);
3695 emit_andne_imm(temp,0,temp);
3696 emit_orrshl_imm(temp,3,tl);
3697 emit_writeword(tl,(int)®_cop2d[copr]);
3700 emit_readword((int)®_cop2d[copr],tl);
3705 static void cop2_put_dreg(u_int copr,signed char sl,signed char temp)
3709 emit_readword((int)®_cop2d[13],temp); // SXY1
3710 emit_writeword(sl,(int)®_cop2d[copr]);
3711 emit_writeword(temp,(int)®_cop2d[12]); // SXY0
3712 emit_readword((int)®_cop2d[14],temp); // SXY2
3713 emit_writeword(sl,(int)®_cop2d[14]);
3714 emit_writeword(temp,(int)®_cop2d[13]); // SXY1
3717 emit_andimm(sl,0x001f,temp);
3718 emit_shlimm(temp,7,temp);
3719 emit_writeword(temp,(int)®_cop2d[9]);
3720 emit_andimm(sl,0x03e0,temp);
3721 emit_shlimm(temp,2,temp);
3722 emit_writeword(temp,(int)®_cop2d[10]);
3723 emit_andimm(sl,0x7c00,temp);
3724 emit_shrimm(temp,3,temp);
3725 emit_writeword(temp,(int)®_cop2d[11]);
3726 emit_writeword(sl,(int)®_cop2d[28]);
3730 emit_mvnmi(temp,temp);
3731 emit_clz(temp,temp);
3732 emit_writeword(sl,(int)®_cop2d[30]);
3733 emit_writeword(temp,(int)®_cop2d[31]);
3738 emit_writeword(sl,(int)®_cop2d[copr]);
3743 void cop2_assemble(int i,struct regstat *i_regs)
3745 u_int copr=(source[i]>>11)&0x1f;
3746 signed char temp=get_reg(i_regs->regmap,-1);
3747 if (opcode2[i]==0) { // MFC2
3748 signed char tl=get_reg(i_regs->regmap,rt1[i]);
3749 if(tl>=0&&rt1[i]!=0)
3750 cop2_get_dreg(copr,tl,temp);
3752 else if (opcode2[i]==4) { // MTC2
3753 signed char sl=get_reg(i_regs->regmap,rs1[i]);
3754 cop2_put_dreg(copr,sl,temp);
3756 else if (opcode2[i]==2) // CFC2
3758 signed char tl=get_reg(i_regs->regmap,rt1[i]);
3759 if(tl>=0&&rt1[i]!=0)
3760 emit_readword((int)®_cop2c[copr],tl);
3762 else if (opcode2[i]==6) // CTC2
3764 signed char sl=get_reg(i_regs->regmap,rs1[i]);
3773 emit_signextend16(sl,temp);
3776 //value = value & 0x7ffff000;
3777 //if (value & 0x7f87e000) value |= 0x80000000;
3778 emit_shrimm(sl,12,temp);
3779 emit_shlimm(temp,12,temp);
3780 emit_testimm(temp,0x7f000000);
3781 emit_testeqimm(temp,0x00870000);
3782 emit_testeqimm(temp,0x0000e000);
3783 emit_orrne_imm(temp,0x80000000,temp);
3789 emit_writeword(temp,(int)®_cop2c[copr]);
3794 void c2op_assemble(int i,struct regstat *i_regs)
3796 signed char temp=get_reg(i_regs->regmap,-1);
3797 u_int c2op=source[i]&0x3f;
3799 for(hr=0;hr<HOST_REGS;hr++) {
3800 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3802 if(i==0||itype[i-1]!=C2OP)
3805 if (gte_handlers[c2op]!=NULL) {
3806 int cc=get_reg(i_regs->regmap,CCREG);
3807 emit_movimm(source[i],1); // opcode
3808 if (cc>=0&>e_cycletab[c2op])
3809 emit_addimm(cc,gte_cycletab[c2op]/2,cc); // XXX: could just adjust ccadj?
3810 emit_addimm(FP,(int)&psxRegs.CP2D.r[0]-(int)&dynarec_local,0); // cop2 regs
3811 emit_writeword(1,(int)&psxRegs.code);
3812 emit_call((int)gte_handlers[c2op]);
3815 if(i>=slen-1||itype[i+1]!=C2OP)
3816 restore_regs(reglist);
3819 void cop1_unusable(int i,struct regstat *i_regs)
3821 // XXX: should just just do the exception instead
3825 add_stub(FP_STUB,jaddr,(int)out,i,0,(int)i_regs,is_delayslot,0);
3830 void cop1_assemble(int i,struct regstat *i_regs)
3832 #ifndef DISABLE_COP1
3833 // Check cop1 unusable
3835 signed char rs=get_reg(i_regs->regmap,CSREG);
3837 emit_testimm(rs,0x20000000);
3840 add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3843 if (opcode2[i]==0) { // MFC1
3844 signed char tl=get_reg(i_regs->regmap,rt1[i]);
3846 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],tl);
3847 emit_readword_indexed(0,tl,tl);
3850 else if (opcode2[i]==1) { // DMFC1
3851 signed char tl=get_reg(i_regs->regmap,rt1[i]);
3852 signed char th=get_reg(i_regs->regmap,rt1[i]|64);
3854 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],tl);
3855 if(th>=0) emit_readword_indexed(4,tl,th);
3856 emit_readword_indexed(0,tl,tl);
3859 else if (opcode2[i]==4) { // MTC1
3860 signed char sl=get_reg(i_regs->regmap,rs1[i]);
3861 signed char temp=get_reg(i_regs->regmap,-1);
3862 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
3863 emit_writeword_indexed(sl,0,temp);
3865 else if (opcode2[i]==5) { // DMTC1
3866 signed char sl=get_reg(i_regs->regmap,rs1[i]);
3867 signed char sh=rs1[i]>0?get_reg(i_regs->regmap,rs1[i]|64):sl;
3868 signed char temp=get_reg(i_regs->regmap,-1);
3869 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],temp);
3870 emit_writeword_indexed(sh,4,temp);
3871 emit_writeword_indexed(sl,0,temp);
3873 else if (opcode2[i]==2) // CFC1
3875 signed char tl=get_reg(i_regs->regmap,rt1[i]);
3877 u_int copr=(source[i]>>11)&0x1f;
3878 if(copr==0) emit_readword((int)&FCR0,tl);
3879 if(copr==31) emit_readword((int)&FCR31,tl);
3882 else if (opcode2[i]==6) // CTC1
3884 signed char sl=get_reg(i_regs->regmap,rs1[i]);
3885 u_int copr=(source[i]>>11)&0x1f;
3889 emit_writeword(sl,(int)&FCR31);
3890 // Set the rounding mode
3892 //char temp=get_reg(i_regs->regmap,-1);
3893 //emit_andimm(sl,3,temp);
3894 //emit_fldcw_indexed((int)&rounding_modes,temp);
3898 cop1_unusable(i, i_regs);
3902 void fconv_assemble_arm(int i,struct regstat *i_regs)
3904 #ifndef DISABLE_COP1
3905 signed char temp=get_reg(i_regs->regmap,-1);
3907 // Check cop1 unusable
3909 signed char rs=get_reg(i_regs->regmap,CSREG);
3911 emit_testimm(rs,0x20000000);
3914 add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3918 #if(defined(__VFP_FP__) && !defined(__SOFTFP__))
3919 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x0d) { // trunc_w_s
3920 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
3922 emit_ftosizs(15,15); // float->int, truncate
3923 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f))
3924 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],temp);
3928 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x0d) { // trunc_w_d
3929 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],temp);
3931 emit_ftosizd(7,13); // double->int, truncate
3932 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],temp);
3937 if(opcode2[i]==0x14&&(source[i]&0x3f)==0x20) { // cvt_s_w
3938 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
3940 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f))
3941 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],temp);
3946 if(opcode2[i]==0x14&&(source[i]&0x3f)==0x21) { // cvt_d_w
3947 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
3949 emit_readword((int)®_cop1_double[(source[i]>>6)&0x1f],temp);
3955 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x21) { // cvt_d_s
3956 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
3958 emit_readword((int)®_cop1_double[(source[i]>>6)&0x1f],temp);
3963 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x20) { // cvt_s_d
3964 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],temp);
3966 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],temp);
3976 for(hr=0;hr<HOST_REGS;hr++) {
3977 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3981 if(opcode2[i]==0x14&&(source[i]&0x3f)==0x20) {
3982 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
3983 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
3984 emit_call((int)cvt_s_w);
3986 if(opcode2[i]==0x14&&(source[i]&0x3f)==0x21) {
3987 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
3988 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
3989 emit_call((int)cvt_d_w);
3991 if(opcode2[i]==0x15&&(source[i]&0x3f)==0x20) {
3992 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
3993 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
3994 emit_call((int)cvt_s_l);
3996 if(opcode2[i]==0x15&&(source[i]&0x3f)==0x21) {
3997 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
3998 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
3999 emit_call((int)cvt_d_l);
4002 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x21) {
4003 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
4004 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
4005 emit_call((int)cvt_d_s);
4007 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x24) {
4008 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
4009 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
4010 emit_call((int)cvt_w_s);
4012 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x25) {
4013 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
4014 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
4015 emit_call((int)cvt_l_s);
4018 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x20) {
4019 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
4020 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
4021 emit_call((int)cvt_s_d);
4023 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x24) {
4024 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
4025 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
4026 emit_call((int)cvt_w_d);
4028 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x25) {
4029 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
4030 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
4031 emit_call((int)cvt_l_d);
4034 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x08) {
4035 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
4036 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
4037 emit_call((int)round_l_s);
4039 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x09) {
4040 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
4041 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
4042 emit_call((int)trunc_l_s);
4044 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x0a) {
4045 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
4046 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
4047 emit_call((int)ceil_l_s);
4049 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x0b) {
4050 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
4051 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
4052 emit_call((int)floor_l_s);
4054 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x0c) {
4055 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
4056 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
4057 emit_call((int)round_w_s);
4059 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x0d) {
4060 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
4061 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
4062 emit_call((int)trunc_w_s);
4064 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x0e) {
4065 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
4066 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
4067 emit_call((int)ceil_w_s);
4069 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x0f) {
4070 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
4071 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
4072 emit_call((int)floor_w_s);
4075 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x08) {
4076 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
4077 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
4078 emit_call((int)round_l_d);
4080 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x09) {
4081 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
4082 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
4083 emit_call((int)trunc_l_d);
4085 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x0a) {
4086 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
4087 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
4088 emit_call((int)ceil_l_d);
4090 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x0b) {
4091 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
4092 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
4093 emit_call((int)floor_l_d);
4095 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x0c) {
4096 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
4097 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
4098 emit_call((int)round_w_d);
4100 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x0d) {
4101 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
4102 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
4103 emit_call((int)trunc_w_d);
4105 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x0e) {
4106 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
4107 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
4108 emit_call((int)ceil_w_d);
4110 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x0f) {
4111 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
4112 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
4113 emit_call((int)floor_w_d);
4116 restore_regs(reglist);
4118 cop1_unusable(i, i_regs);
4121 #define fconv_assemble fconv_assemble_arm
4123 void fcomp_assemble(int i,struct regstat *i_regs)
4125 #ifndef DISABLE_COP1
4126 signed char fs=get_reg(i_regs->regmap,FSREG);
4127 signed char temp=get_reg(i_regs->regmap,-1);
4129 // Check cop1 unusable
4131 signed char cs=get_reg(i_regs->regmap,CSREG);
4133 emit_testimm(cs,0x20000000);
4136 add_stub(FP_STUB,jaddr,(int)out,i,cs,(int)i_regs,is_delayslot,0);
4140 if((source[i]&0x3f)==0x30) {
4141 emit_andimm(fs,~0x800000,fs);
4145 if((source[i]&0x3e)==0x38) {
4146 // sf/ngle - these should throw exceptions for NaNs
4147 emit_andimm(fs,~0x800000,fs);
4151 #if(defined(__VFP_FP__) && !defined(__SOFTFP__))
4152 if(opcode2[i]==0x10) {
4153 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
4154 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],HOST_TEMPREG);
4155 emit_orimm(fs,0x800000,fs);
4157 emit_flds(HOST_TEMPREG,15);
4160 if((source[i]&0x3f)==0x31) emit_bicvc_imm(fs,0x800000,fs); // c_un_s
4161 if((source[i]&0x3f)==0x32) emit_bicne_imm(fs,0x800000,fs); // c_eq_s
4162 if((source[i]&0x3f)==0x33) {emit_bicne_imm(fs,0x800000,fs);emit_orrvs_imm(fs,0x800000,fs);} // c_ueq_s
4163 if((source[i]&0x3f)==0x34) emit_biccs_imm(fs,0x800000,fs); // c_olt_s
4164 if((source[i]&0x3f)==0x35) {emit_biccs_imm(fs,0x800000,fs);emit_orrvs_imm(fs,0x800000,fs);} // c_ult_s
4165 if((source[i]&0x3f)==0x36) emit_bichi_imm(fs,0x800000,fs); // c_ole_s
4166 if((source[i]&0x3f)==0x37) {emit_bichi_imm(fs,0x800000,fs);emit_orrvs_imm(fs,0x800000,fs);} // c_ule_s
4167 if((source[i]&0x3f)==0x3a) emit_bicne_imm(fs,0x800000,fs); // c_seq_s
4168 if((source[i]&0x3f)==0x3b) emit_bicne_imm(fs,0x800000,fs); // c_ngl_s
4169 if((source[i]&0x3f)==0x3c) emit_biccs_imm(fs,0x800000,fs); // c_lt_s
4170 if((source[i]&0x3f)==0x3d) emit_biccs_imm(fs,0x800000,fs); // c_nge_s
4171 if((source[i]&0x3f)==0x3e) emit_bichi_imm(fs,0x800000,fs); // c_le_s
4172 if((source[i]&0x3f)==0x3f) emit_bichi_imm(fs,0x800000,fs); // c_ngt_s
4175 if(opcode2[i]==0x11) {
4176 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],temp);
4177 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],HOST_TEMPREG);
4178 emit_orimm(fs,0x800000,fs);
4180 emit_vldr(HOST_TEMPREG,7);
4183 if((source[i]&0x3f)==0x31) emit_bicvc_imm(fs,0x800000,fs); // c_un_d
4184 if((source[i]&0x3f)==0x32) emit_bicne_imm(fs,0x800000,fs); // c_eq_d
4185 if((source[i]&0x3f)==0x33) {emit_bicne_imm(fs,0x800000,fs);emit_orrvs_imm(fs,0x800000,fs);} // c_ueq_d
4186 if((source[i]&0x3f)==0x34) emit_biccs_imm(fs,0x800000,fs); // c_olt_d
4187 if((source[i]&0x3f)==0x35) {emit_biccs_imm(fs,0x800000,fs);emit_orrvs_imm(fs,0x800000,fs);} // c_ult_d
4188 if((source[i]&0x3f)==0x36) emit_bichi_imm(fs,0x800000,fs); // c_ole_d
4189 if((source[i]&0x3f)==0x37) {emit_bichi_imm(fs,0x800000,fs);emit_orrvs_imm(fs,0x800000,fs);} // c_ule_d
4190 if((source[i]&0x3f)==0x3a) emit_bicne_imm(fs,0x800000,fs); // c_seq_d
4191 if((source[i]&0x3f)==0x3b) emit_bicne_imm(fs,0x800000,fs); // c_ngl_d
4192 if((source[i]&0x3f)==0x3c) emit_biccs_imm(fs,0x800000,fs); // c_lt_d
4193 if((source[i]&0x3f)==0x3d) emit_biccs_imm(fs,0x800000,fs); // c_nge_d
4194 if((source[i]&0x3f)==0x3e) emit_bichi_imm(fs,0x800000,fs); // c_le_d
4195 if((source[i]&0x3f)==0x3f) emit_bichi_imm(fs,0x800000,fs); // c_ngt_d
4203 for(hr=0;hr<HOST_REGS;hr++) {
4204 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
4208 if(opcode2[i]==0x10) {
4209 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
4210 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],ARG2_REG);
4211 if((source[i]&0x3f)==0x30) emit_call((int)c_f_s);
4212 if((source[i]&0x3f)==0x31) emit_call((int)c_un_s);
4213 if((source[i]&0x3f)==0x32) emit_call((int)c_eq_s);
4214 if((source[i]&0x3f)==0x33) emit_call((int)c_ueq_s);
4215 if((source[i]&0x3f)==0x34) emit_call((int)c_olt_s);
4216 if((source[i]&0x3f)==0x35) emit_call((int)c_ult_s);
4217 if((source[i]&0x3f)==0x36) emit_call((int)c_ole_s);
4218 if((source[i]&0x3f)==0x37) emit_call((int)c_ule_s);
4219 if((source[i]&0x3f)==0x38) emit_call((int)c_sf_s);
4220 if((source[i]&0x3f)==0x39) emit_call((int)c_ngle_s);
4221 if((source[i]&0x3f)==0x3a) emit_call((int)c_seq_s);
4222 if((source[i]&0x3f)==0x3b) emit_call((int)c_ngl_s);
4223 if((source[i]&0x3f)==0x3c) emit_call((int)c_lt_s);
4224 if((source[i]&0x3f)==0x3d) emit_call((int)c_nge_s);
4225 if((source[i]&0x3f)==0x3e) emit_call((int)c_le_s);
4226 if((source[i]&0x3f)==0x3f) emit_call((int)c_ngt_s);
4228 if(opcode2[i]==0x11) {
4229 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
4230 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],ARG2_REG);
4231 if((source[i]&0x3f)==0x30) emit_call((int)c_f_d);
4232 if((source[i]&0x3f)==0x31) emit_call((int)c_un_d);
4233 if((source[i]&0x3f)==0x32) emit_call((int)c_eq_d);
4234 if((source[i]&0x3f)==0x33) emit_call((int)c_ueq_d);
4235 if((source[i]&0x3f)==0x34) emit_call((int)c_olt_d);
4236 if((source[i]&0x3f)==0x35) emit_call((int)c_ult_d);
4237 if((source[i]&0x3f)==0x36) emit_call((int)c_ole_d);
4238 if((source[i]&0x3f)==0x37) emit_call((int)c_ule_d);
4239 if((source[i]&0x3f)==0x38) emit_call((int)c_sf_d);
4240 if((source[i]&0x3f)==0x39) emit_call((int)c_ngle_d);
4241 if((source[i]&0x3f)==0x3a) emit_call((int)c_seq_d);
4242 if((source[i]&0x3f)==0x3b) emit_call((int)c_ngl_d);
4243 if((source[i]&0x3f)==0x3c) emit_call((int)c_lt_d);
4244 if((source[i]&0x3f)==0x3d) emit_call((int)c_nge_d);
4245 if((source[i]&0x3f)==0x3e) emit_call((int)c_le_d);
4246 if((source[i]&0x3f)==0x3f) emit_call((int)c_ngt_d);
4248 restore_regs(reglist);
4249 emit_loadreg(FSREG,fs);
4251 cop1_unusable(i, i_regs);
4255 void float_assemble(int i,struct regstat *i_regs)
4257 #ifndef DISABLE_COP1
4258 signed char temp=get_reg(i_regs->regmap,-1);
4260 // Check cop1 unusable
4262 signed char cs=get_reg(i_regs->regmap,CSREG);
4264 emit_testimm(cs,0x20000000);
4267 add_stub(FP_STUB,jaddr,(int)out,i,cs,(int)i_regs,is_delayslot,0);
4271 #if(defined(__VFP_FP__) && !defined(__SOFTFP__))
4272 if((source[i]&0x3f)==6) // mov
4274 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f)) {
4275 if(opcode2[i]==0x10) {
4276 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
4277 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],HOST_TEMPREG);
4278 emit_readword_indexed(0,temp,temp);
4279 emit_writeword_indexed(temp,0,HOST_TEMPREG);
4281 if(opcode2[i]==0x11) {
4282 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],temp);
4283 emit_readword((int)®_cop1_double[(source[i]>>6)&0x1f],HOST_TEMPREG);
4285 emit_vstr(7,HOST_TEMPREG);
4291 if((source[i]&0x3f)>3)
4293 if(opcode2[i]==0x10) {
4294 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
4296 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f)) {
4297 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],temp);
4299 if((source[i]&0x3f)==4) // sqrt
4301 if((source[i]&0x3f)==5) // abs
4303 if((source[i]&0x3f)==7) // neg
4307 if(opcode2[i]==0x11) {
4308 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],temp);
4310 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f)) {
4311 emit_readword((int)®_cop1_double[(source[i]>>6)&0x1f],temp);
4313 if((source[i]&0x3f)==4) // sqrt
4315 if((source[i]&0x3f)==5) // abs
4317 if((source[i]&0x3f)==7) // neg
4323 if((source[i]&0x3f)<4)
4325 if(opcode2[i]==0x10) {
4326 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
4328 if(opcode2[i]==0x11) {
4329 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],temp);
4331 if(((source[i]>>11)&0x1f)!=((source[i]>>16)&0x1f)) {
4332 if(opcode2[i]==0x10) {
4333 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],HOST_TEMPREG);
4335 emit_flds(HOST_TEMPREG,13);
4336 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f)) {
4337 if(((source[i]>>16)&0x1f)!=((source[i]>>6)&0x1f)) {
4338 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],temp);
4341 if((source[i]&0x3f)==0) emit_fadds(15,13,15);
4342 if((source[i]&0x3f)==1) emit_fsubs(15,13,15);
4343 if((source[i]&0x3f)==2) emit_fmuls(15,13,15);
4344 if((source[i]&0x3f)==3) emit_fdivs(15,13,15);
4345 if(((source[i]>>16)&0x1f)==((source[i]>>6)&0x1f)) {
4346 emit_fsts(15,HOST_TEMPREG);
4351 else if(opcode2[i]==0x11) {
4352 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],HOST_TEMPREG);
4354 emit_vldr(HOST_TEMPREG,6);
4355 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f)) {
4356 if(((source[i]>>16)&0x1f)!=((source[i]>>6)&0x1f)) {
4357 emit_readword((int)®_cop1_double[(source[i]>>6)&0x1f],temp);
4360 if((source[i]&0x3f)==0) emit_faddd(7,6,7);
4361 if((source[i]&0x3f)==1) emit_fsubd(7,6,7);
4362 if((source[i]&0x3f)==2) emit_fmuld(7,6,7);
4363 if((source[i]&0x3f)==3) emit_fdivd(7,6,7);
4364 if(((source[i]>>16)&0x1f)==((source[i]>>6)&0x1f)) {
4365 emit_vstr(7,HOST_TEMPREG);
4372 if(opcode2[i]==0x10) {
4374 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f)) {
4375 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],temp);
4377 if((source[i]&0x3f)==0) emit_fadds(15,15,15);
4378 if((source[i]&0x3f)==1) emit_fsubs(15,15,15);
4379 if((source[i]&0x3f)==2) emit_fmuls(15,15,15);
4380 if((source[i]&0x3f)==3) emit_fdivs(15,15,15);
4383 else if(opcode2[i]==0x11) {
4385 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f)) {
4386 emit_readword((int)®_cop1_double[(source[i]>>6)&0x1f],temp);
4388 if((source[i]&0x3f)==0) emit_faddd(7,7,7);
4389 if((source[i]&0x3f)==1) emit_fsubd(7,7,7);
4390 if((source[i]&0x3f)==2) emit_fmuld(7,7,7);
4391 if((source[i]&0x3f)==3) emit_fdivd(7,7,7);
4400 for(hr=0;hr<HOST_REGS;hr++) {
4401 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
4403 if(opcode2[i]==0x10) { // Single precision
4405 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
4406 if((source[i]&0x3f)<4) {
4407 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],ARG2_REG);
4408 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG3_REG);
4410 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
4412 switch(source[i]&0x3f)
4414 case 0x00: emit_call((int)add_s);break;
4415 case 0x01: emit_call((int)sub_s);break;
4416 case 0x02: emit_call((int)mul_s);break;
4417 case 0x03: emit_call((int)div_s);break;
4418 case 0x04: emit_call((int)sqrt_s);break;
4419 case 0x05: emit_call((int)abs_s);break;
4420 case 0x06: emit_call((int)mov_s);break;
4421 case 0x07: emit_call((int)neg_s);break;
4423 restore_regs(reglist);
4425 if(opcode2[i]==0x11) { // Double precision
4427 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
4428 if((source[i]&0x3f)<4) {
4429 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],ARG2_REG);
4430 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG3_REG);
4432 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
4434 switch(source[i]&0x3f)
4436 case 0x00: emit_call((int)add_d);break;
4437 case 0x01: emit_call((int)sub_d);break;
4438 case 0x02: emit_call((int)mul_d);break;
4439 case 0x03: emit_call((int)div_d);break;
4440 case 0x04: emit_call((int)sqrt_d);break;
4441 case 0x05: emit_call((int)abs_d);break;
4442 case 0x06: emit_call((int)mov_d);break;
4443 case 0x07: emit_call((int)neg_d);break;
4445 restore_regs(reglist);
4448 cop1_unusable(i, i_regs);
4452 void multdiv_assemble_arm(int i,struct regstat *i_regs)
4459 // case 0x1D: DMULTU
4464 if((opcode2[i]&4)==0) // 32-bit
4466 if(opcode2[i]==0x18) // MULT
4468 signed char m1=get_reg(i_regs->regmap,rs1[i]);
4469 signed char m2=get_reg(i_regs->regmap,rs2[i]);
4470 signed char hi=get_reg(i_regs->regmap,HIREG);
4471 signed char lo=get_reg(i_regs->regmap,LOREG);
4476 emit_smull(m1,m2,hi,lo);
4478 if(opcode2[i]==0x19) // MULTU
4480 signed char m1=get_reg(i_regs->regmap,rs1[i]);
4481 signed char m2=get_reg(i_regs->regmap,rs2[i]);
4482 signed char hi=get_reg(i_regs->regmap,HIREG);
4483 signed char lo=get_reg(i_regs->regmap,LOREG);
4488 emit_umull(m1,m2,hi,lo);
4490 if(opcode2[i]==0x1A) // DIV
4492 signed char d1=get_reg(i_regs->regmap,rs1[i]);
4493 signed char d2=get_reg(i_regs->regmap,rs2[i]);
4496 signed char quotient=get_reg(i_regs->regmap,LOREG);
4497 signed char remainder=get_reg(i_regs->regmap,HIREG);
4498 assert(quotient>=0);
4499 assert(remainder>=0);
4500 emit_movs(d1,remainder);
4501 emit_movimm(0xffffffff,quotient);
4502 emit_negmi(quotient,quotient); // .. quotient and ..
4503 emit_negmi(remainder,remainder); // .. remainder for div0 case (will be negated back after jump)
4504 emit_movs(d2,HOST_TEMPREG);
4505 emit_jeq((int)out+52); // Division by zero
4506 emit_negmi(HOST_TEMPREG,HOST_TEMPREG);
4507 emit_clz(HOST_TEMPREG,quotient);
4508 emit_shl(HOST_TEMPREG,quotient,HOST_TEMPREG);
4509 emit_orimm(quotient,1<<31,quotient);
4510 emit_shr(quotient,quotient,quotient);
4511 emit_cmp(remainder,HOST_TEMPREG);
4512 emit_subcs(remainder,HOST_TEMPREG,remainder);
4513 emit_adcs(quotient,quotient,quotient);
4514 emit_shrimm(HOST_TEMPREG,1,HOST_TEMPREG);
4515 emit_jcc((int)out-16); // -4
4517 emit_negmi(quotient,quotient);
4519 emit_negmi(remainder,remainder);
4521 if(opcode2[i]==0x1B) // DIVU
4523 signed char d1=get_reg(i_regs->regmap,rs1[i]); // dividend
4524 signed char d2=get_reg(i_regs->regmap,rs2[i]); // divisor
4527 signed char quotient=get_reg(i_regs->regmap,LOREG);
4528 signed char remainder=get_reg(i_regs->regmap,HIREG);
4529 assert(quotient>=0);
4530 assert(remainder>=0);
4531 emit_mov(d1,remainder);
4532 emit_movimm(0xffffffff,quotient); // div0 case
4534 emit_jeq((int)out+40); // Division by zero
4535 emit_clz(d2,HOST_TEMPREG);
4536 emit_movimm(1<<31,quotient);
4537 emit_shl(d2,HOST_TEMPREG,d2);
4538 emit_shr(quotient,HOST_TEMPREG,quotient);
4539 emit_cmp(remainder,d2);
4540 emit_subcs(remainder,d2,remainder);
4541 emit_adcs(quotient,quotient,quotient);
4542 emit_shrcc_imm(d2,1,d2);
4543 emit_jcc((int)out-16); // -4
4548 if(opcode2[i]==0x1C) // DMULT
4550 assert(opcode2[i]!=0x1C);
4551 signed char m1h=get_reg(i_regs->regmap,rs1[i]|64);
4552 signed char m1l=get_reg(i_regs->regmap,rs1[i]);
4553 signed char m2h=get_reg(i_regs->regmap,rs2[i]|64);
4554 signed char m2l=get_reg(i_regs->regmap,rs2[i]);
4563 emit_call((int)&mult64);
4568 signed char hih=get_reg(i_regs->regmap,HIREG|64);
4569 signed char hil=get_reg(i_regs->regmap,HIREG);
4570 if(hih>=0) emit_loadreg(HIREG|64,hih);
4571 if(hil>=0) emit_loadreg(HIREG,hil);
4572 signed char loh=get_reg(i_regs->regmap,LOREG|64);
4573 signed char lol=get_reg(i_regs->regmap,LOREG);
4574 if(loh>=0) emit_loadreg(LOREG|64,loh);
4575 if(lol>=0) emit_loadreg(LOREG,lol);
4577 if(opcode2[i]==0x1D) // DMULTU
4579 signed char m1h=get_reg(i_regs->regmap,rs1[i]|64);
4580 signed char m1l=get_reg(i_regs->regmap,rs1[i]);
4581 signed char m2h=get_reg(i_regs->regmap,rs2[i]|64);
4582 signed char m2l=get_reg(i_regs->regmap,rs2[i]);
4588 if(m1l!=0) emit_mov(m1l,0);
4589 if(m1h==0) emit_readword((int)&dynarec_local,1);
4590 else if(m1h>1) emit_mov(m1h,1);
4591 if(m2l<2) emit_readword((int)&dynarec_local+m2l*4,2);
4592 else if(m2l>2) emit_mov(m2l,2);
4593 if(m2h<3) emit_readword((int)&dynarec_local+m2h*4,3);
4594 else if(m2h>3) emit_mov(m2h,3);
4595 emit_call((int)&multu64);
4596 restore_regs(0x100f);
4597 signed char hih=get_reg(i_regs->regmap,HIREG|64);
4598 signed char hil=get_reg(i_regs->regmap,HIREG);
4599 signed char loh=get_reg(i_regs->regmap,LOREG|64);
4600 signed char lol=get_reg(i_regs->regmap,LOREG);
4601 /*signed char temp=get_reg(i_regs->regmap,-1);
4602 signed char rh=get_reg(i_regs->regmap,HIREG|64);
4603 signed char rl=get_reg(i_regs->regmap,HIREG);
4609 //emit_mov(m1l,EAX);
4611 emit_umull(rl,rh,m1l,m2l);
4612 emit_storereg(LOREG,rl);
4614 //emit_mov(m1h,EAX);
4616 emit_umull(rl,rh,m1h,m2l);
4617 emit_adds(rl,temp,temp);
4618 emit_adcimm(rh,0,rh);
4619 emit_storereg(HIREG,rh);
4620 //emit_mov(m2h,EAX);
4622 emit_umull(rl,rh,m1l,m2h);
4623 emit_adds(rl,temp,temp);
4624 emit_adcimm(rh,0,rh);
4625 emit_storereg(LOREG|64,temp);
4627 //emit_mov(m2h,EAX);
4629 emit_umull(rl,rh,m1h,m2h);
4630 emit_adds(rl,temp,rl);
4631 emit_loadreg(HIREG,temp);
4632 emit_adcimm(rh,0,rh);
4633 emit_adds(rl,temp,rl);
4634 emit_adcimm(rh,0,rh);
4641 emit_call((int)&multu64);
4646 signed char hih=get_reg(i_regs->regmap,HIREG|64);
4647 signed char hil=get_reg(i_regs->regmap,HIREG);
4648 if(hih>=0) emit_loadreg(HIREG|64,hih); // DEBUG
4649 if(hil>=0) emit_loadreg(HIREG,hil); // DEBUG
4651 // Shouldn't be necessary
4652 //char loh=get_reg(i_regs->regmap,LOREG|64);
4653 //char lol=get_reg(i_regs->regmap,LOREG);
4654 //if(loh>=0) emit_loadreg(LOREG|64,loh);
4655 //if(lol>=0) emit_loadreg(LOREG,lol);
4657 if(opcode2[i]==0x1E) // DDIV
4659 signed char d1h=get_reg(i_regs->regmap,rs1[i]|64);
4660 signed char d1l=get_reg(i_regs->regmap,rs1[i]);
4661 signed char d2h=get_reg(i_regs->regmap,rs2[i]|64);
4662 signed char d2l=get_reg(i_regs->regmap,rs2[i]);
4668 if(d1l!=0) emit_mov(d1l,0);
4669 if(d1h==0) emit_readword((int)&dynarec_local,1);
4670 else if(d1h>1) emit_mov(d1h,1);
4671 if(d2l<2) emit_readword((int)&dynarec_local+d2l*4,2);
4672 else if(d2l>2) emit_mov(d2l,2);
4673 if(d2h<3) emit_readword((int)&dynarec_local+d2h*4,3);
4674 else if(d2h>3) emit_mov(d2h,3);
4675 emit_call((int)&div64);
4676 restore_regs(0x100f);
4677 signed char hih=get_reg(i_regs->regmap,HIREG|64);
4678 signed char hil=get_reg(i_regs->regmap,HIREG);
4679 signed char loh=get_reg(i_regs->regmap,LOREG|64);
4680 signed char lol=get_reg(i_regs->regmap,LOREG);
4681 if(hih>=0) emit_loadreg(HIREG|64,hih);
4682 if(hil>=0) emit_loadreg(HIREG,hil);
4683 if(loh>=0) emit_loadreg(LOREG|64,loh);
4684 if(lol>=0) emit_loadreg(LOREG,lol);
4686 if(opcode2[i]==0x1F) // DDIVU
4688 //u_int hr,reglist=0;
4689 //for(hr=0;hr<HOST_REGS;hr++) {
4690 // if(i_regs->regmap[hr]>=0 && (i_regs->regmap[hr]&62)!=HIREG) reglist|=1<<hr;
4692 signed char d1h=get_reg(i_regs->regmap,rs1[i]|64);
4693 signed char d1l=get_reg(i_regs->regmap,rs1[i]);
4694 signed char d2h=get_reg(i_regs->regmap,rs2[i]|64);
4695 signed char d2l=get_reg(i_regs->regmap,rs2[i]);
4701 if(d1l!=0) emit_mov(d1l,0);
4702 if(d1h==0) emit_readword((int)&dynarec_local,1);
4703 else if(d1h>1) emit_mov(d1h,1);
4704 if(d2l<2) emit_readword((int)&dynarec_local+d2l*4,2);
4705 else if(d2l>2) emit_mov(d2l,2);
4706 if(d2h<3) emit_readword((int)&dynarec_local+d2h*4,3);
4707 else if(d2h>3) emit_mov(d2h,3);
4708 emit_call((int)&divu64);
4709 restore_regs(0x100f);
4710 signed char hih=get_reg(i_regs->regmap,HIREG|64);
4711 signed char hil=get_reg(i_regs->regmap,HIREG);
4712 signed char loh=get_reg(i_regs->regmap,LOREG|64);
4713 signed char lol=get_reg(i_regs->regmap,LOREG);
4714 if(hih>=0) emit_loadreg(HIREG|64,hih);
4715 if(hil>=0) emit_loadreg(HIREG,hil);
4716 if(loh>=0) emit_loadreg(LOREG|64,loh);
4717 if(lol>=0) emit_loadreg(LOREG,lol);
4723 // Multiply by zero is zero.
4724 // MIPS does not have a divide by zero exception.
4725 // The result is undefined, we return zero.
4726 signed char hr=get_reg(i_regs->regmap,HIREG);
4727 signed char lr=get_reg(i_regs->regmap,LOREG);
4728 if(hr>=0) emit_zeroreg(hr);
4729 if(lr>=0) emit_zeroreg(lr);
4732 #define multdiv_assemble multdiv_assemble_arm
4734 void do_preload_rhash(int r) {
4735 // Don't need this for ARM. On x86, this puts the value 0xf8 into the
4736 // register. On ARM the hash can be done with a single instruction (below)
4739 void do_preload_rhtbl(int ht) {
4740 emit_addimm(FP,(int)&mini_ht-(int)&dynarec_local,ht);
4743 void do_rhash(int rs,int rh) {
4744 emit_andimm(rs,0xf8,rh);
4747 void do_miniht_load(int ht,int rh) {
4748 assem_debug("ldr %s,[%s,%s]!\n",regname[rh],regname[ht],regname[rh]);
4749 output_w32(0xe7b00000|rd_rn_rm(rh,ht,rh));
4752 void do_miniht_jump(int rs,int rh,int ht) {
4754 emit_ldreq_indexed(ht,4,15);
4755 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
4757 emit_jmp(jump_vaddr_reg[7]);
4759 emit_jmp(jump_vaddr_reg[rs]);
4763 void do_miniht_insert(u_int return_address,int rt,int temp) {
4765 emit_movimm(return_address,rt); // PC into link register
4766 add_to_linker((int)out,return_address,1);
4767 emit_pcreladdr(temp);
4768 emit_writeword(rt,(int)&mini_ht[(return_address&0xFF)>>3][0]);
4769 emit_writeword(temp,(int)&mini_ht[(return_address&0xFF)>>3][1]);
4771 emit_movw(return_address&0x0000FFFF,rt);
4772 add_to_linker((int)out,return_address,1);
4773 emit_pcreladdr(temp);
4774 emit_writeword(temp,(int)&mini_ht[(return_address&0xFF)>>3][1]);
4775 emit_movt(return_address&0xFFFF0000,rt);
4776 emit_writeword(rt,(int)&mini_ht[(return_address&0xFF)>>3][0]);
4780 // Sign-extend to 64 bits and write out upper half of a register
4781 // This is useful where we have a 32-bit value in a register, and want to
4782 // keep it in a 32-bit register, but can't guarantee that it won't be read
4783 // as a 64-bit value later.
4784 void wb_sx(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32_pre,uint64_t is32,uint64_t u,uint64_t uu)
4787 if(is32_pre==is32) return;
4789 for(hr=0;hr<HOST_REGS;hr++) {
4790 if(hr!=EXCLUDE_REG) {
4791 //if(pre[hr]==entry[hr]) {
4792 if((reg=pre[hr])>=0) {
4794 if( ((is32_pre&~is32&~uu)>>reg)&1 ) {
4795 emit_sarimm(hr,31,HOST_TEMPREG);
4796 emit_storereg(reg|64,HOST_TEMPREG);
4806 void wb_valid(signed char pre[],signed char entry[],u_int dirty_pre,u_int dirty,uint64_t is32_pre,uint64_t u,uint64_t uu)
4808 //if(dirty_pre==dirty) return;
4810 for(hr=0;hr<HOST_REGS;hr++) {
4811 if(hr!=EXCLUDE_REG) {
4813 if(((~u)>>(reg&63))&1) {
4815 if(((dirty_pre&~dirty)>>hr)&1) {
4817 emit_storereg(reg,hr);
4818 if( ((is32_pre&~uu)>>reg)&1 ) {
4819 emit_sarimm(hr,31,HOST_TEMPREG);
4820 emit_storereg(reg|64,HOST_TEMPREG);
4824 emit_storereg(reg,hr);
4834 /* using strd could possibly help but you'd have to allocate registers in pairs
4835 void wb_invalidate_arm(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,uint64_t u,uint64_t uu)
4839 for(hr=HOST_REGS-1;hr>=0;hr--) {
4840 if(hr!=EXCLUDE_REG) {
4841 if(pre[hr]!=entry[hr]) {
4844 if(get_reg(entry,pre[hr])<0) {
4846 if(!((u>>pre[hr])&1)) {
4847 if(hr<10&&(~hr&1)&&(pre[hr+1]<0||wrote==hr+1)) {
4848 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
4849 emit_sarimm(hr,31,hr+1);
4850 emit_strdreg(pre[hr],hr);
4853 emit_storereg(pre[hr],hr);
4855 emit_storereg(pre[hr],hr);
4856 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
4857 emit_sarimm(hr,31,hr);
4858 emit_storereg(pre[hr]|64,hr);
4863 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
4864 emit_storereg(pre[hr],hr);
4874 for(hr=0;hr<HOST_REGS;hr++) {
4875 if(hr!=EXCLUDE_REG) {
4876 if(pre[hr]!=entry[hr]) {
4879 if((nr=get_reg(entry,pre[hr]))>=0) {
4887 #define wb_invalidate wb_invalidate_arm
4890 // Clearing the cache is rather slow on ARM Linux, so mark the areas
4891 // that need to be cleared, and then only clear these areas once.
4892 void do_clear_cache()
4895 for (i=0;i<(1<<(TARGET_SIZE_2-17));i++)
4897 u_int bitmap=needs_clear_cache[i];
4903 start=BASE_ADDR+i*131072+j*4096;
4911 __clear_cache((void *)start,(void *)end);
4917 needs_clear_cache[i]=0;
4922 // CPU-architecture-specific initialization
4924 #ifndef DISABLE_COP1
4925 rounding_modes[0]=0x0<<22; // round
4926 rounding_modes[1]=0x3<<22; // trunc
4927 rounding_modes[2]=0x1<<22; // ceil
4928 rounding_modes[3]=0x2<<22; // floor
4932 // vim:shiftwidth=2:expandtab