1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus/PCSX - assem_arm.c *
3 * Copyright (C) 2009-2011 Ari64 *
4 * Copyright (C) 2010-2011 GraÅžvydas "notaz" Ignotas *
6 * This program is free software; you can redistribute it and/or modify *
7 * it under the terms of the GNU General Public License as published by *
8 * the Free Software Foundation; either version 2 of the License, or *
9 * (at your option) any later version. *
11 * This program is distributed in the hope that it will be useful, *
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
14 * GNU General Public License for more details. *
16 * You should have received a copy of the GNU General Public License *
17 * along with this program; if not, write to the *
18 * Free Software Foundation, Inc., *
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
20 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
27 #include "../gte_arm.h"
28 #include "../gte_neon.h"
31 #include "arm_features.h"
34 char translation_cache[1 << TARGET_SIZE_2] __attribute__((aligned(4096)));
38 #define CALLER_SAVE_REGS 0x100f
40 #define CALLER_SAVE_REGS 0x120f
43 extern int cycle_count;
44 extern int last_count;
46 extern int pending_exception;
47 extern int branch_target;
48 extern uint64_t readmem_dword;
50 extern precomp_instr fake_pc;
52 extern void *dynarec_local;
53 extern u_int memory_map[1048576];
54 extern u_int mini_ht[32][2];
55 extern u_int rounding_modes[4];
57 void indirect_jump_indexed();
70 void jump_vaddr_r10();
71 void jump_vaddr_r12();
73 const u_int jump_vaddr_reg[16] = {
91 void invalidate_addr_r0();
92 void invalidate_addr_r1();
93 void invalidate_addr_r2();
94 void invalidate_addr_r3();
95 void invalidate_addr_r4();
96 void invalidate_addr_r5();
97 void invalidate_addr_r6();
98 void invalidate_addr_r7();
99 void invalidate_addr_r8();
100 void invalidate_addr_r9();
101 void invalidate_addr_r10();
102 void invalidate_addr_r12();
104 const u_int invalidate_addr_reg[16] = {
105 (int)invalidate_addr_r0,
106 (int)invalidate_addr_r1,
107 (int)invalidate_addr_r2,
108 (int)invalidate_addr_r3,
109 (int)invalidate_addr_r4,
110 (int)invalidate_addr_r5,
111 (int)invalidate_addr_r6,
112 (int)invalidate_addr_r7,
113 (int)invalidate_addr_r8,
114 (int)invalidate_addr_r9,
115 (int)invalidate_addr_r10,
117 (int)invalidate_addr_r12,
124 unsigned int needs_clear_cache[1<<(TARGET_SIZE_2-17)];
128 void set_jump_target(int addr,u_int target)
130 u_char *ptr=(u_char *)addr;
131 u_int *ptr2=(u_int *)ptr;
133 assert((target-(u_int)ptr2-8)<1024);
135 assert((target&3)==0);
136 *ptr2=(*ptr2&0xFFFFF000)|((target-(u_int)ptr2-8)>>2)|0xF00;
137 //printf("target=%x addr=%x insn=%x\n",target,addr,*ptr2);
139 else if(ptr[3]==0x72) {
140 // generated by emit_jno_unlikely
141 if((target-(u_int)ptr2-8)<1024) {
143 assert((target&3)==0);
144 *ptr2=(*ptr2&0xFFFFF000)|((target-(u_int)ptr2-8)>>2)|0xF00;
146 else if((target-(u_int)ptr2-8)<4096&&!((target-(u_int)ptr2-8)&15)) {
148 assert((target&3)==0);
149 *ptr2=(*ptr2&0xFFFFF000)|((target-(u_int)ptr2-8)>>4)|0xE00;
151 else *ptr2=(0x7A000000)|(((target-(u_int)ptr2-8)<<6)>>8);
154 assert((ptr[3]&0x0e)==0xa);
155 *ptr2=(*ptr2&0xFF000000)|(((target-(u_int)ptr2-8)<<6)>>8);
159 // This optionally copies the instruction from the target of the branch into
160 // the space before the branch. Works, but the difference in speed is
161 // usually insignificant.
162 void set_jump_target_fillslot(int addr,u_int target,int copy)
164 u_char *ptr=(u_char *)addr;
165 u_int *ptr2=(u_int *)ptr;
166 assert(!copy||ptr2[-1]==0xe28dd000);
169 assert((target-(u_int)ptr2-8)<4096);
170 *ptr2=(*ptr2&0xFFFFF000)|(target-(u_int)ptr2-8);
173 assert((ptr[3]&0x0e)==0xa);
174 u_int target_insn=*(u_int *)target;
175 if((target_insn&0x0e100000)==0) { // ALU, no immediate, no flags
178 if((target_insn&0x0c100000)==0x04100000) { // Load
181 if(target_insn&0x08000000) {
185 ptr2[-1]=target_insn;
188 *ptr2=(*ptr2&0xFF000000)|(((target-(u_int)ptr2-8)<<6)>>8);
193 add_literal(int addr,int val)
195 assert(literalcount<sizeof(literals)/sizeof(literals[0]));
196 literals[literalcount][0]=addr;
197 literals[literalcount][1]=val;
201 void *kill_pointer(void *stub)
203 int *ptr=(int *)(stub+4);
204 assert((*ptr&0x0ff00000)==0x05900000);
205 u_int offset=*ptr&0xfff;
206 int **l_ptr=(void *)ptr+offset+8;
208 set_jump_target((int)i_ptr,(int)stub);
212 // find where external branch is liked to using addr of it's stub:
213 // get address that insn one after stub loads (dyna_linker arg1),
214 // treat it as a pointer to branch insn,
215 // return addr where that branch jumps to
216 int get_pointer(void *stub)
218 //printf("get_pointer(%x)\n",(int)stub);
219 int *ptr=(int *)(stub+4);
220 assert((*ptr&0x0fff0000)==0x059f0000);
221 u_int offset=*ptr&0xfff;
222 int **l_ptr=(void *)ptr+offset+8;
224 assert((*i_ptr&0x0f000000)==0x0a000000);
225 return (int)i_ptr+((*i_ptr<<8)>>6)+8;
228 // Find the "clean" entry point from a "dirty" entry point
229 // by skipping past the call to verify_code
230 u_int get_clean_addr(int addr)
232 int *ptr=(int *)addr;
238 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
239 assert((*ptr&0xFF000000)==0xeb000000); // bl instruction
241 if((*ptr&0xFF000000)==0xea000000) {
242 return (int)ptr+((*ptr<<8)>>6)+8; // follow jump
247 int verify_dirty(int addr)
249 u_int *ptr=(u_int *)addr;
251 // get from literal pool
252 assert((*ptr&0xFFFF0000)==0xe59f0000);
253 u_int offset=*ptr&0xfff;
254 u_int *l_ptr=(void *)ptr+offset+8;
255 u_int source=l_ptr[0];
261 assert((*ptr&0xFFF00000)==0xe3000000);
262 u_int source=(ptr[0]&0xFFF)+((ptr[0]>>4)&0xF000)+((ptr[2]<<16)&0xFFF0000)+((ptr[2]<<12)&0xF0000000);
263 u_int copy=(ptr[1]&0xFFF)+((ptr[1]>>4)&0xF000)+((ptr[3]<<16)&0xFFF0000)+((ptr[3]<<12)&0xF0000000);
264 u_int len=(ptr[4]&0xFFF)+((ptr[4]>>4)&0xF000);
267 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
268 assert((*ptr&0xFF000000)==0xeb000000); // bl instruction
270 u_int verifier=(int)ptr+((signed int)(*ptr<<8)>>6)+8; // get target of bl
271 if(verifier==(u_int)verify_code_vm||verifier==(u_int)verify_code_ds) {
272 unsigned int page=source>>12;
273 unsigned int map_value=memory_map[page];
274 if(map_value>=0x80000000) return 0;
275 while(page<((source+len-1)>>12)) {
276 if((memory_map[++page]<<2)!=(map_value<<2)) return 0;
278 source = source+(map_value<<2);
281 //printf("verify_dirty: %x %x %x\n",source,copy,len);
282 return !memcmp((void *)source,(void *)copy,len);
285 // This doesn't necessarily find all clean entry points, just
286 // guarantees that it's not dirty
287 int isclean(int addr)
290 int *ptr=((u_int *)addr)+4;
292 int *ptr=((u_int *)addr)+6;
294 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
295 if((*ptr&0xFF000000)!=0xeb000000) return 1; // bl instruction
296 if((int)ptr+((*ptr<<8)>>6)+8==(int)verify_code) return 0;
297 if((int)ptr+((*ptr<<8)>>6)+8==(int)verify_code_vm) return 0;
298 if((int)ptr+((*ptr<<8)>>6)+8==(int)verify_code_ds) return 0;
302 // get source that block at addr was compiled from (host pointers)
303 void get_bounds(int addr,u_int *start,u_int *end)
305 u_int *ptr=(u_int *)addr;
307 // get from literal pool
308 assert((*ptr&0xFFFF0000)==0xe59f0000);
309 u_int offset=*ptr&0xfff;
310 u_int *l_ptr=(void *)ptr+offset+8;
311 u_int source=l_ptr[0];
312 //u_int copy=l_ptr[1];
317 assert((*ptr&0xFFF00000)==0xe3000000);
318 u_int source=(ptr[0]&0xFFF)+((ptr[0]>>4)&0xF000)+((ptr[2]<<16)&0xFFF0000)+((ptr[2]<<12)&0xF0000000);
319 //u_int copy=(ptr[1]&0xFFF)+((ptr[1]>>4)&0xF000)+((ptr[3]<<16)&0xFFF0000)+((ptr[3]<<12)&0xF0000000);
320 u_int len=(ptr[4]&0xFFF)+((ptr[4]>>4)&0xF000);
323 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
324 assert((*ptr&0xFF000000)==0xeb000000); // bl instruction
326 u_int verifier=(int)ptr+((signed int)(*ptr<<8)>>6)+8; // get target of bl
327 if(verifier==(u_int)verify_code_vm||verifier==(u_int)verify_code_ds) {
328 if(memory_map[source>>12]>=0x80000000) source = 0;
329 else source = source+(memory_map[source>>12]<<2);
336 /* Register allocation */
338 // Note: registers are allocated clean (unmodified state)
339 // if you intend to modify the register, you must call dirty_reg().
340 void alloc_reg(struct regstat *cur,int i,signed char reg)
343 int preferred_reg = (reg&7);
344 if(reg==CCREG) preferred_reg=HOST_CCREG;
345 if(reg==PTEMP||reg==FTEMP) preferred_reg=12;
347 // Don't allocate unused registers
348 if((cur->u>>reg)&1) return;
350 // see if it's already allocated
351 for(hr=0;hr<HOST_REGS;hr++)
353 if(cur->regmap[hr]==reg) return;
356 // Keep the same mapping if the register was already allocated in a loop
357 preferred_reg = loop_reg(i,reg,preferred_reg);
359 // Try to allocate the preferred register
360 if(cur->regmap[preferred_reg]==-1) {
361 cur->regmap[preferred_reg]=reg;
362 cur->dirty&=~(1<<preferred_reg);
363 cur->isconst&=~(1<<preferred_reg);
366 r=cur->regmap[preferred_reg];
367 if(r<64&&((cur->u>>r)&1)) {
368 cur->regmap[preferred_reg]=reg;
369 cur->dirty&=~(1<<preferred_reg);
370 cur->isconst&=~(1<<preferred_reg);
373 if(r>=64&&((cur->uu>>(r&63))&1)) {
374 cur->regmap[preferred_reg]=reg;
375 cur->dirty&=~(1<<preferred_reg);
376 cur->isconst&=~(1<<preferred_reg);
380 // Clear any unneeded registers
381 // We try to keep the mapping consistent, if possible, because it
382 // makes branches easier (especially loops). So we try to allocate
383 // first (see above) before removing old mappings. If this is not
384 // possible then go ahead and clear out the registers that are no
386 for(hr=0;hr<HOST_REGS;hr++)
391 if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
395 if((cur->uu>>(r&63))&1) {cur->regmap[hr]=-1;break;}
399 // Try to allocate any available register, but prefer
400 // registers that have not been used recently.
402 for(hr=0;hr<HOST_REGS;hr++) {
403 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
404 if(regs[i-1].regmap[hr]!=rs1[i-1]&®s[i-1].regmap[hr]!=rs2[i-1]&®s[i-1].regmap[hr]!=rt1[i-1]&®s[i-1].regmap[hr]!=rt2[i-1]) {
406 cur->dirty&=~(1<<hr);
407 cur->isconst&=~(1<<hr);
413 // Try to allocate any available register
414 for(hr=0;hr<HOST_REGS;hr++) {
415 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
417 cur->dirty&=~(1<<hr);
418 cur->isconst&=~(1<<hr);
423 // Ok, now we have to evict someone
424 // Pick a register we hopefully won't need soon
425 u_char hsn[MAXREG+1];
426 memset(hsn,10,sizeof(hsn));
428 lsn(hsn,i,&preferred_reg);
429 //printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",cur->regmap[0],cur->regmap[1],cur->regmap[2],cur->regmap[3],cur->regmap[5],cur->regmap[6],cur->regmap[7]);
430 //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
432 // Don't evict the cycle count at entry points, otherwise the entry
433 // stub will have to write it.
434 if(bt[i]&&hsn[CCREG]>2) hsn[CCREG]=2;
435 if(i>1&&hsn[CCREG]>2&&(itype[i-2]==RJUMP||itype[i-2]==UJUMP||itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP)) hsn[CCREG]=2;
438 // Alloc preferred register if available
439 if(hsn[r=cur->regmap[preferred_reg]&63]==j) {
440 for(hr=0;hr<HOST_REGS;hr++) {
441 // Evict both parts of a 64-bit register
442 if((cur->regmap[hr]&63)==r) {
444 cur->dirty&=~(1<<hr);
445 cur->isconst&=~(1<<hr);
448 cur->regmap[preferred_reg]=reg;
451 for(r=1;r<=MAXREG;r++)
453 if(hsn[r]==j&&r!=rs1[i-1]&&r!=rs2[i-1]&&r!=rt1[i-1]&&r!=rt2[i-1]) {
454 for(hr=0;hr<HOST_REGS;hr++) {
455 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
456 if(cur->regmap[hr]==r+64) {
458 cur->dirty&=~(1<<hr);
459 cur->isconst&=~(1<<hr);
464 for(hr=0;hr<HOST_REGS;hr++) {
465 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
466 if(cur->regmap[hr]==r) {
468 cur->dirty&=~(1<<hr);
469 cur->isconst&=~(1<<hr);
480 for(r=1;r<=MAXREG;r++)
483 for(hr=0;hr<HOST_REGS;hr++) {
484 if(cur->regmap[hr]==r+64) {
486 cur->dirty&=~(1<<hr);
487 cur->isconst&=~(1<<hr);
491 for(hr=0;hr<HOST_REGS;hr++) {
492 if(cur->regmap[hr]==r) {
494 cur->dirty&=~(1<<hr);
495 cur->isconst&=~(1<<hr);
502 SysPrintf("This shouldn't happen (alloc_reg)");exit(1);
505 void alloc_reg64(struct regstat *cur,int i,signed char reg)
507 int preferred_reg = 8+(reg&1);
510 // allocate the lower 32 bits
511 alloc_reg(cur,i,reg);
513 // Don't allocate unused registers
514 if((cur->uu>>reg)&1) return;
516 // see if the upper half is already allocated
517 for(hr=0;hr<HOST_REGS;hr++)
519 if(cur->regmap[hr]==reg+64) return;
522 // Keep the same mapping if the register was already allocated in a loop
523 preferred_reg = loop_reg(i,reg,preferred_reg);
525 // Try to allocate the preferred register
526 if(cur->regmap[preferred_reg]==-1) {
527 cur->regmap[preferred_reg]=reg|64;
528 cur->dirty&=~(1<<preferred_reg);
529 cur->isconst&=~(1<<preferred_reg);
532 r=cur->regmap[preferred_reg];
533 if(r<64&&((cur->u>>r)&1)) {
534 cur->regmap[preferred_reg]=reg|64;
535 cur->dirty&=~(1<<preferred_reg);
536 cur->isconst&=~(1<<preferred_reg);
539 if(r>=64&&((cur->uu>>(r&63))&1)) {
540 cur->regmap[preferred_reg]=reg|64;
541 cur->dirty&=~(1<<preferred_reg);
542 cur->isconst&=~(1<<preferred_reg);
546 // Clear any unneeded registers
547 // We try to keep the mapping consistent, if possible, because it
548 // makes branches easier (especially loops). So we try to allocate
549 // first (see above) before removing old mappings. If this is not
550 // possible then go ahead and clear out the registers that are no
552 for(hr=HOST_REGS-1;hr>=0;hr--)
557 if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
561 if((cur->uu>>(r&63))&1) {cur->regmap[hr]=-1;break;}
565 // Try to allocate any available register, but prefer
566 // registers that have not been used recently.
568 for(hr=0;hr<HOST_REGS;hr++) {
569 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
570 if(regs[i-1].regmap[hr]!=rs1[i-1]&®s[i-1].regmap[hr]!=rs2[i-1]&®s[i-1].regmap[hr]!=rt1[i-1]&®s[i-1].regmap[hr]!=rt2[i-1]) {
571 cur->regmap[hr]=reg|64;
572 cur->dirty&=~(1<<hr);
573 cur->isconst&=~(1<<hr);
579 // Try to allocate any available register
580 for(hr=0;hr<HOST_REGS;hr++) {
581 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
582 cur->regmap[hr]=reg|64;
583 cur->dirty&=~(1<<hr);
584 cur->isconst&=~(1<<hr);
589 // Ok, now we have to evict someone
590 // Pick a register we hopefully won't need soon
591 u_char hsn[MAXREG+1];
592 memset(hsn,10,sizeof(hsn));
594 lsn(hsn,i,&preferred_reg);
595 //printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",cur->regmap[0],cur->regmap[1],cur->regmap[2],cur->regmap[3],cur->regmap[5],cur->regmap[6],cur->regmap[7]);
596 //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
598 // Don't evict the cycle count at entry points, otherwise the entry
599 // stub will have to write it.
600 if(bt[i]&&hsn[CCREG]>2) hsn[CCREG]=2;
601 if(i>1&&hsn[CCREG]>2&&(itype[i-2]==RJUMP||itype[i-2]==UJUMP||itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP)) hsn[CCREG]=2;
604 // Alloc preferred register if available
605 if(hsn[r=cur->regmap[preferred_reg]&63]==j) {
606 for(hr=0;hr<HOST_REGS;hr++) {
607 // Evict both parts of a 64-bit register
608 if((cur->regmap[hr]&63)==r) {
610 cur->dirty&=~(1<<hr);
611 cur->isconst&=~(1<<hr);
614 cur->regmap[preferred_reg]=reg|64;
617 for(r=1;r<=MAXREG;r++)
619 if(hsn[r]==j&&r!=rs1[i-1]&&r!=rs2[i-1]&&r!=rt1[i-1]&&r!=rt2[i-1]) {
620 for(hr=0;hr<HOST_REGS;hr++) {
621 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
622 if(cur->regmap[hr]==r+64) {
623 cur->regmap[hr]=reg|64;
624 cur->dirty&=~(1<<hr);
625 cur->isconst&=~(1<<hr);
630 for(hr=0;hr<HOST_REGS;hr++) {
631 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
632 if(cur->regmap[hr]==r) {
633 cur->regmap[hr]=reg|64;
634 cur->dirty&=~(1<<hr);
635 cur->isconst&=~(1<<hr);
646 for(r=1;r<=MAXREG;r++)
649 for(hr=0;hr<HOST_REGS;hr++) {
650 if(cur->regmap[hr]==r+64) {
651 cur->regmap[hr]=reg|64;
652 cur->dirty&=~(1<<hr);
653 cur->isconst&=~(1<<hr);
657 for(hr=0;hr<HOST_REGS;hr++) {
658 if(cur->regmap[hr]==r) {
659 cur->regmap[hr]=reg|64;
660 cur->dirty&=~(1<<hr);
661 cur->isconst&=~(1<<hr);
668 SysPrintf("This shouldn't happen");exit(1);
671 // Allocate a temporary register. This is done without regard to
672 // dirty status or whether the register we request is on the unneeded list
673 // Note: This will only allocate one register, even if called multiple times
674 void alloc_reg_temp(struct regstat *cur,int i,signed char reg)
677 int preferred_reg = -1;
679 // see if it's already allocated
680 for(hr=0;hr<HOST_REGS;hr++)
682 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==reg) return;
685 // Try to allocate any available register
686 for(hr=HOST_REGS-1;hr>=0;hr--) {
687 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
689 cur->dirty&=~(1<<hr);
690 cur->isconst&=~(1<<hr);
695 // Find an unneeded register
696 for(hr=HOST_REGS-1;hr>=0;hr--)
702 if(i==0||((unneeded_reg[i-1]>>r)&1)) {
704 cur->dirty&=~(1<<hr);
705 cur->isconst&=~(1<<hr);
712 if((cur->uu>>(r&63))&1) {
713 if(i==0||((unneeded_reg_upper[i-1]>>(r&63))&1)) {
715 cur->dirty&=~(1<<hr);
716 cur->isconst&=~(1<<hr);
724 // Ok, now we have to evict someone
725 // Pick a register we hopefully won't need soon
726 // TODO: we might want to follow unconditional jumps here
727 // TODO: get rid of dupe code and make this into a function
728 u_char hsn[MAXREG+1];
729 memset(hsn,10,sizeof(hsn));
731 lsn(hsn,i,&preferred_reg);
732 //printf("hsn: %d %d %d %d %d %d %d\n",hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
734 // Don't evict the cycle count at entry points, otherwise the entry
735 // stub will have to write it.
736 if(bt[i]&&hsn[CCREG]>2) hsn[CCREG]=2;
737 if(i>1&&hsn[CCREG]>2&&(itype[i-2]==RJUMP||itype[i-2]==UJUMP||itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP)) hsn[CCREG]=2;
740 for(r=1;r<=MAXREG;r++)
742 if(hsn[r]==j&&r!=rs1[i-1]&&r!=rs2[i-1]&&r!=rt1[i-1]&&r!=rt2[i-1]) {
743 for(hr=0;hr<HOST_REGS;hr++) {
744 if(hr!=HOST_CCREG||hsn[CCREG]>2) {
745 if(cur->regmap[hr]==r+64) {
747 cur->dirty&=~(1<<hr);
748 cur->isconst&=~(1<<hr);
753 for(hr=0;hr<HOST_REGS;hr++) {
754 if(hr!=HOST_CCREG||hsn[CCREG]>2) {
755 if(cur->regmap[hr]==r) {
757 cur->dirty&=~(1<<hr);
758 cur->isconst&=~(1<<hr);
769 for(r=1;r<=MAXREG;r++)
772 for(hr=0;hr<HOST_REGS;hr++) {
773 if(cur->regmap[hr]==r+64) {
775 cur->dirty&=~(1<<hr);
776 cur->isconst&=~(1<<hr);
780 for(hr=0;hr<HOST_REGS;hr++) {
781 if(cur->regmap[hr]==r) {
783 cur->dirty&=~(1<<hr);
784 cur->isconst&=~(1<<hr);
791 SysPrintf("This shouldn't happen");exit(1);
793 // Allocate a specific ARM register.
794 void alloc_arm_reg(struct regstat *cur,int i,signed char reg,char hr)
799 // see if it's already allocated (and dealloc it)
800 for(n=0;n<HOST_REGS;n++)
802 if(n!=EXCLUDE_REG&&cur->regmap[n]==reg) {
803 dirty=(cur->dirty>>n)&1;
809 cur->dirty&=~(1<<hr);
810 cur->dirty|=dirty<<hr;
811 cur->isconst&=~(1<<hr);
814 // Alloc cycle count into dedicated register
815 alloc_cc(struct regstat *cur,int i)
817 alloc_arm_reg(cur,i,CCREG,HOST_CCREG);
825 char regname[16][4] = {
843 void output_byte(u_char byte)
847 void output_modrm(u_char mod,u_char rm,u_char ext)
852 u_char byte=(mod<<6)|(ext<<3)|rm;
855 void output_sib(u_char scale,u_char index,u_char base)
860 u_char byte=(scale<<6)|(index<<3)|base;
863 void output_w32(u_int word)
865 *((u_int *)out)=word;
868 u_int rd_rn_rm(u_int rd, u_int rn, u_int rm)
873 return((rn<<16)|(rd<<12)|rm);
875 u_int rd_rn_imm_shift(u_int rd, u_int rn, u_int imm, u_int shift)
880 assert((shift&1)==0);
881 return((rn<<16)|(rd<<12)|(((32-shift)&30)<<7)|imm);
883 u_int genimm(u_int imm,u_int *encoded)
891 *encoded=((i&30)<<7)|imm;
894 imm=(imm>>2)|(imm<<30);i-=2;
898 void genimm_checked(u_int imm,u_int *encoded)
900 u_int ret=genimm(imm,encoded);
903 u_int genjmp(u_int addr)
905 int offset=addr-(int)out-8;
906 if(offset<-33554432||offset>=33554432) {
908 SysPrintf("genjmp: out of range: %08x\n", offset);
913 return ((u_int)offset>>2)&0xffffff;
916 void emit_mov(int rs,int rt)
918 assem_debug("mov %s,%s\n",regname[rt],regname[rs]);
919 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs));
922 void emit_movs(int rs,int rt)
924 assem_debug("movs %s,%s\n",regname[rt],regname[rs]);
925 output_w32(0xe1b00000|rd_rn_rm(rt,0,rs));
928 void emit_add(int rs1,int rs2,int rt)
930 assem_debug("add %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
931 output_w32(0xe0800000|rd_rn_rm(rt,rs1,rs2));
934 void emit_adds(int rs1,int rs2,int rt)
936 assem_debug("adds %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
937 output_w32(0xe0900000|rd_rn_rm(rt,rs1,rs2));
940 void emit_adcs(int rs1,int rs2,int rt)
942 assem_debug("adcs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
943 output_w32(0xe0b00000|rd_rn_rm(rt,rs1,rs2));
946 void emit_sbc(int rs1,int rs2,int rt)
948 assem_debug("sbc %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
949 output_w32(0xe0c00000|rd_rn_rm(rt,rs1,rs2));
952 void emit_sbcs(int rs1,int rs2,int rt)
954 assem_debug("sbcs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
955 output_w32(0xe0d00000|rd_rn_rm(rt,rs1,rs2));
958 void emit_neg(int rs, int rt)
960 assem_debug("rsb %s,%s,#0\n",regname[rt],regname[rs]);
961 output_w32(0xe2600000|rd_rn_rm(rt,rs,0));
964 void emit_negs(int rs, int rt)
966 assem_debug("rsbs %s,%s,#0\n",regname[rt],regname[rs]);
967 output_w32(0xe2700000|rd_rn_rm(rt,rs,0));
970 void emit_sub(int rs1,int rs2,int rt)
972 assem_debug("sub %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
973 output_w32(0xe0400000|rd_rn_rm(rt,rs1,rs2));
976 void emit_subs(int rs1,int rs2,int rt)
978 assem_debug("subs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
979 output_w32(0xe0500000|rd_rn_rm(rt,rs1,rs2));
982 void emit_zeroreg(int rt)
984 assem_debug("mov %s,#0\n",regname[rt]);
985 output_w32(0xe3a00000|rd_rn_rm(rt,0,0));
988 void emit_loadlp(u_int imm,u_int rt)
990 add_literal((int)out,imm);
991 assem_debug("ldr %s,pc+? [=%x]\n",regname[rt],imm);
992 output_w32(0xe5900000|rd_rn_rm(rt,15,0));
994 void emit_movw(u_int imm,u_int rt)
997 assem_debug("movw %s,#%d (0x%x)\n",regname[rt],imm,imm);
998 output_w32(0xe3000000|rd_rn_rm(rt,0,0)|(imm&0xfff)|((imm<<4)&0xf0000));
1000 void emit_movt(u_int imm,u_int rt)
1002 assem_debug("movt %s,#%d (0x%x)\n",regname[rt],imm&0xffff0000,imm&0xffff0000);
1003 output_w32(0xe3400000|rd_rn_rm(rt,0,0)|((imm>>16)&0xfff)|((imm>>12)&0xf0000));
1005 void emit_movimm(u_int imm,u_int rt)
1008 if(genimm(imm,&armval)) {
1009 assem_debug("mov %s,#%d\n",regname[rt],imm);
1010 output_w32(0xe3a00000|rd_rn_rm(rt,0,0)|armval);
1011 }else if(genimm(~imm,&armval)) {
1012 assem_debug("mvn %s,#%d\n",regname[rt],imm);
1013 output_w32(0xe3e00000|rd_rn_rm(rt,0,0)|armval);
1014 }else if(imm<65536) {
1016 assem_debug("mov %s,#%d\n",regname[rt],imm&0xFF00);
1017 output_w32(0xe3a00000|rd_rn_imm_shift(rt,0,imm>>8,8));
1018 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF);
1019 output_w32(0xe2800000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1025 emit_loadlp(imm,rt);
1027 emit_movw(imm&0x0000FFFF,rt);
1028 emit_movt(imm&0xFFFF0000,rt);
1032 void emit_pcreladdr(u_int rt)
1034 assem_debug("add %s,pc,#?\n",regname[rt]);
1035 output_w32(0xe2800000|rd_rn_rm(rt,15,0));
1038 void emit_loadreg(int r, int hr)
1042 SysPrintf("64bit load in 32bit mode!\n");
1050 int addr=((int)reg)+((r&63)<<REG_SHIFT)+((r&64)>>4);
1051 if((r&63)==HIREG) addr=(int)&hi+((r&64)>>4);
1052 if((r&63)==LOREG) addr=(int)&lo+((r&64)>>4);
1053 if(r==CCREG) addr=(int)&cycle_count;
1054 if(r==CSREG) addr=(int)&Status;
1055 if(r==FSREG) addr=(int)&FCR31;
1056 if(r==INVCP) addr=(int)&invc_ptr;
1057 u_int offset = addr-(u_int)&dynarec_local;
1058 assert(offset<4096);
1059 assem_debug("ldr %s,fp+%d\n",regname[hr],offset);
1060 output_w32(0xe5900000|rd_rn_rm(hr,FP,0)|offset);
1063 void emit_storereg(int r, int hr)
1067 SysPrintf("64bit store in 32bit mode!\n");
1072 int addr=((int)reg)+((r&63)<<REG_SHIFT)+((r&64)>>4);
1073 if((r&63)==HIREG) addr=(int)&hi+((r&64)>>4);
1074 if((r&63)==LOREG) addr=(int)&lo+((r&64)>>4);
1075 if(r==CCREG) addr=(int)&cycle_count;
1076 if(r==FSREG) addr=(int)&FCR31;
1077 u_int offset = addr-(u_int)&dynarec_local;
1078 assert(offset<4096);
1079 assem_debug("str %s,fp+%d\n",regname[hr],offset);
1080 output_w32(0xe5800000|rd_rn_rm(hr,FP,0)|offset);
1083 void emit_test(int rs, int rt)
1085 assem_debug("tst %s,%s\n",regname[rs],regname[rt]);
1086 output_w32(0xe1100000|rd_rn_rm(0,rs,rt));
1089 void emit_testimm(int rs,int imm)
1092 assem_debug("tst %s,#%d\n",regname[rs],imm);
1093 genimm_checked(imm,&armval);
1094 output_w32(0xe3100000|rd_rn_rm(0,rs,0)|armval);
1097 void emit_testeqimm(int rs,int imm)
1100 assem_debug("tsteq %s,$%d\n",regname[rs],imm);
1101 genimm_checked(imm,&armval);
1102 output_w32(0x03100000|rd_rn_rm(0,rs,0)|armval);
1105 void emit_not(int rs,int rt)
1107 assem_debug("mvn %s,%s\n",regname[rt],regname[rs]);
1108 output_w32(0xe1e00000|rd_rn_rm(rt,0,rs));
1111 void emit_mvnmi(int rs,int rt)
1113 assem_debug("mvnmi %s,%s\n",regname[rt],regname[rs]);
1114 output_w32(0x41e00000|rd_rn_rm(rt,0,rs));
1117 void emit_and(u_int rs1,u_int rs2,u_int rt)
1119 assem_debug("and %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1120 output_w32(0xe0000000|rd_rn_rm(rt,rs1,rs2));
1123 void emit_or(u_int rs1,u_int rs2,u_int rt)
1125 assem_debug("orr %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1126 output_w32(0xe1800000|rd_rn_rm(rt,rs1,rs2));
1128 void emit_or_and_set_flags(int rs1,int rs2,int rt)
1130 assem_debug("orrs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1131 output_w32(0xe1900000|rd_rn_rm(rt,rs1,rs2));
1134 void emit_orrshl_imm(u_int rs,u_int imm,u_int rt)
1139 assem_debug("orr %s,%s,%s,lsl #%d\n",regname[rt],regname[rt],regname[rs],imm);
1140 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs)|(imm<<7));
1143 void emit_orrshr_imm(u_int rs,u_int imm,u_int rt)
1148 assem_debug("orr %s,%s,%s,lsr #%d\n",regname[rt],regname[rt],regname[rs],imm);
1149 output_w32(0xe1800020|rd_rn_rm(rt,rt,rs)|(imm<<7));
1152 void emit_xor(u_int rs1,u_int rs2,u_int rt)
1154 assem_debug("eor %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1155 output_w32(0xe0200000|rd_rn_rm(rt,rs1,rs2));
1158 void emit_addimm(u_int rs,int imm,u_int rt)
1164 if(genimm(imm,&armval)) {
1165 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rs],imm);
1166 output_w32(0xe2800000|rd_rn_rm(rt,rs,0)|armval);
1167 }else if(genimm(-imm,&armval)) {
1168 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rs],-imm);
1169 output_w32(0xe2400000|rd_rn_rm(rt,rs,0)|armval);
1172 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rs],(-imm)&0xFF00);
1173 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rt],(-imm)&0xFF);
1174 output_w32(0xe2400000|rd_rn_imm_shift(rt,rs,(-imm)>>8,8));
1175 output_w32(0xe2400000|rd_rn_imm_shift(rt,rt,(-imm)&0xff,0));
1178 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF00);
1179 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF);
1180 output_w32(0xe2800000|rd_rn_imm_shift(rt,rs,imm>>8,8));
1181 output_w32(0xe2800000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1184 else if(rs!=rt) emit_mov(rs,rt);
1187 void emit_addimm_and_set_flags(int imm,int rt)
1189 assert(imm>-65536&&imm<65536);
1191 if(genimm(imm,&armval)) {
1192 assem_debug("adds %s,%s,#%d\n",regname[rt],regname[rt],imm);
1193 output_w32(0xe2900000|rd_rn_rm(rt,rt,0)|armval);
1194 }else if(genimm(-imm,&armval)) {
1195 assem_debug("subs %s,%s,#%d\n",regname[rt],regname[rt],imm);
1196 output_w32(0xe2500000|rd_rn_rm(rt,rt,0)|armval);
1198 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rt],(-imm)&0xFF00);
1199 assem_debug("subs %s,%s,#%d\n",regname[rt],regname[rt],(-imm)&0xFF);
1200 output_w32(0xe2400000|rd_rn_imm_shift(rt,rt,(-imm)>>8,8));
1201 output_w32(0xe2500000|rd_rn_imm_shift(rt,rt,(-imm)&0xff,0));
1203 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF00);
1204 assem_debug("adds %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF);
1205 output_w32(0xe2800000|rd_rn_imm_shift(rt,rt,imm>>8,8));
1206 output_w32(0xe2900000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1209 void emit_addimm_no_flags(u_int imm,u_int rt)
1211 emit_addimm(rt,imm,rt);
1214 void emit_addnop(u_int r)
1217 assem_debug("add %s,%s,#0 (nop)\n",regname[r],regname[r]);
1218 output_w32(0xe2800000|rd_rn_rm(r,r,0));
1221 void emit_adcimm(u_int rs,int imm,u_int rt)
1224 genimm_checked(imm,&armval);
1225 assem_debug("adc %s,%s,#%d\n",regname[rt],regname[rs],imm);
1226 output_w32(0xe2a00000|rd_rn_rm(rt,rs,0)|armval);
1228 /*void emit_sbcimm(int imm,u_int rt)
1231 genimm_checked(imm,&armval);
1232 assem_debug("sbc %s,%s,#%d\n",regname[rt],regname[rt],imm);
1233 output_w32(0xe2c00000|rd_rn_rm(rt,rt,0)|armval);
1235 void emit_sbbimm(int imm,u_int rt)
1237 assem_debug("sbb $%d,%%%s\n",imm,regname[rt]);
1239 if(imm<128&&imm>=-128) {
1241 output_modrm(3,rt,3);
1247 output_modrm(3,rt,3);
1251 void emit_rscimm(int rs,int imm,u_int rt)
1255 genimm_checked(imm,&armval);
1256 assem_debug("rsc %s,%s,#%d\n",regname[rt],regname[rs],imm);
1257 output_w32(0xe2e00000|rd_rn_rm(rt,rs,0)|armval);
1260 void emit_addimm64_32(int rsh,int rsl,int imm,int rth,int rtl)
1262 // TODO: if(genimm(imm,&armval)) ...
1264 emit_movimm(imm,HOST_TEMPREG);
1265 emit_adds(HOST_TEMPREG,rsl,rtl);
1266 emit_adcimm(rsh,0,rth);
1269 void emit_sbb(int rs1,int rs2)
1271 assem_debug("sbb %%%s,%%%s\n",regname[rs2],regname[rs1]);
1273 output_modrm(3,rs1,rs2);
1276 void emit_andimm(int rs,int imm,int rt)
1281 }else if(genimm(imm,&armval)) {
1282 assem_debug("and %s,%s,#%d\n",regname[rt],regname[rs],imm);
1283 output_w32(0xe2000000|rd_rn_rm(rt,rs,0)|armval);
1284 }else if(genimm(~imm,&armval)) {
1285 assem_debug("bic %s,%s,#%d\n",regname[rt],regname[rs],imm);
1286 output_w32(0xe3c00000|rd_rn_rm(rt,rs,0)|armval);
1287 }else if(imm==65535) {
1289 assem_debug("bic %s,%s,#FF000000\n",regname[rt],regname[rs]);
1290 output_w32(0xe3c00000|rd_rn_rm(rt,rs,0)|0x4FF);
1291 assem_debug("bic %s,%s,#00FF0000\n",regname[rt],regname[rt]);
1292 output_w32(0xe3c00000|rd_rn_rm(rt,rt,0)|0x8FF);
1294 assem_debug("uxth %s,%s\n",regname[rt],regname[rs]);
1295 output_w32(0xe6ff0070|rd_rn_rm(rt,0,rs));
1298 assert(imm>0&&imm<65535);
1300 assem_debug("mov r14,#%d\n",imm&0xFF00);
1301 output_w32(0xe3a00000|rd_rn_imm_shift(HOST_TEMPREG,0,imm>>8,8));
1302 assem_debug("add r14,r14,#%d\n",imm&0xFF);
1303 output_w32(0xe2800000|rd_rn_imm_shift(HOST_TEMPREG,HOST_TEMPREG,imm&0xff,0));
1305 emit_movw(imm,HOST_TEMPREG);
1307 assem_debug("and %s,%s,r14\n",regname[rt],regname[rs]);
1308 output_w32(0xe0000000|rd_rn_rm(rt,rs,HOST_TEMPREG));
1312 void emit_orimm(int rs,int imm,int rt)
1316 if(rs!=rt) emit_mov(rs,rt);
1317 }else if(genimm(imm,&armval)) {
1318 assem_debug("orr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1319 output_w32(0xe3800000|rd_rn_rm(rt,rs,0)|armval);
1321 assert(imm>0&&imm<65536);
1322 assem_debug("orr %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF00);
1323 assem_debug("orr %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF);
1324 output_w32(0xe3800000|rd_rn_imm_shift(rt,rs,imm>>8,8));
1325 output_w32(0xe3800000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1329 void emit_xorimm(int rs,int imm,int rt)
1333 if(rs!=rt) emit_mov(rs,rt);
1334 }else if(genimm(imm,&armval)) {
1335 assem_debug("eor %s,%s,#%d\n",regname[rt],regname[rs],imm);
1336 output_w32(0xe2200000|rd_rn_rm(rt,rs,0)|armval);
1338 assert(imm>0&&imm<65536);
1339 assem_debug("eor %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF00);
1340 assem_debug("eor %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF);
1341 output_w32(0xe2200000|rd_rn_imm_shift(rt,rs,imm>>8,8));
1342 output_w32(0xe2200000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1346 void emit_shlimm(int rs,u_int imm,int rt)
1351 assem_debug("lsl %s,%s,#%d\n",regname[rt],regname[rs],imm);
1352 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|(imm<<7));
1355 void emit_lsls_imm(int rs,int imm,int rt)
1359 assem_debug("lsls %s,%s,#%d\n",regname[rt],regname[rs],imm);
1360 output_w32(0xe1b00000|rd_rn_rm(rt,0,rs)|(imm<<7));
1363 void emit_lslpls_imm(int rs,int imm,int rt)
1367 assem_debug("lslpls %s,%s,#%d\n",regname[rt],regname[rs],imm);
1368 output_w32(0x51b00000|rd_rn_rm(rt,0,rs)|(imm<<7));
1371 void emit_shrimm(int rs,u_int imm,int rt)
1375 assem_debug("lsr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1376 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x20|(imm<<7));
1379 void emit_sarimm(int rs,u_int imm,int rt)
1383 assem_debug("asr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1384 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x40|(imm<<7));
1387 void emit_rorimm(int rs,u_int imm,int rt)
1391 assem_debug("ror %s,%s,#%d\n",regname[rt],regname[rs],imm);
1392 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x60|(imm<<7));
1395 void emit_shldimm(int rs,int rs2,u_int imm,int rt)
1397 assem_debug("shld %%%s,%%%s,%d\n",regname[rt],regname[rs2],imm);
1401 assem_debug("lsl %s,%s,#%d\n",regname[rt],regname[rs],imm);
1402 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|(imm<<7));
1403 assem_debug("orr %s,%s,%s,lsr #%d\n",regname[rt],regname[rt],regname[rs2],32-imm);
1404 output_w32(0xe1800020|rd_rn_rm(rt,rt,rs2)|((32-imm)<<7));
1407 void emit_shrdimm(int rs,int rs2,u_int imm,int rt)
1409 assem_debug("shrd %%%s,%%%s,%d\n",regname[rt],regname[rs2],imm);
1413 assem_debug("lsr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1414 output_w32(0xe1a00020|rd_rn_rm(rt,0,rs)|(imm<<7));
1415 assem_debug("orr %s,%s,%s,lsl #%d\n",regname[rt],regname[rt],regname[rs2],32-imm);
1416 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs2)|((32-imm)<<7));
1419 void emit_signextend16(int rs,int rt)
1422 emit_shlimm(rs,16,rt);
1423 emit_sarimm(rt,16,rt);
1425 assem_debug("sxth %s,%s\n",regname[rt],regname[rs]);
1426 output_w32(0xe6bf0070|rd_rn_rm(rt,0,rs));
1430 void emit_signextend8(int rs,int rt)
1433 emit_shlimm(rs,24,rt);
1434 emit_sarimm(rt,24,rt);
1436 assem_debug("sxtb %s,%s\n",regname[rt],regname[rs]);
1437 output_w32(0xe6af0070|rd_rn_rm(rt,0,rs));
1441 void emit_shl(u_int rs,u_int shift,u_int rt)
1447 assem_debug("lsl %s,%s,%s\n",regname[rt],regname[rs],regname[shift]);
1448 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x10|(shift<<8));
1450 void emit_shr(u_int rs,u_int shift,u_int rt)
1455 assem_debug("lsr %s,%s,%s\n",regname[rt],regname[rs],regname[shift]);
1456 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x30|(shift<<8));
1458 void emit_sar(u_int rs,u_int shift,u_int rt)
1463 assem_debug("asr %s,%s,%s\n",regname[rt],regname[rs],regname[shift]);
1464 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x50|(shift<<8));
1466 void emit_shlcl(int r)
1468 assem_debug("shl %%%s,%%cl\n",regname[r]);
1471 void emit_shrcl(int r)
1473 assem_debug("shr %%%s,%%cl\n",regname[r]);
1476 void emit_sarcl(int r)
1478 assem_debug("sar %%%s,%%cl\n",regname[r]);
1482 void emit_shldcl(int r1,int r2)
1484 assem_debug("shld %%%s,%%%s,%%cl\n",regname[r1],regname[r2]);
1487 void emit_shrdcl(int r1,int r2)
1489 assem_debug("shrd %%%s,%%%s,%%cl\n",regname[r1],regname[r2]);
1492 void emit_orrshl(u_int rs,u_int shift,u_int rt)
1497 assem_debug("orr %s,%s,%s,lsl %s\n",regname[rt],regname[rt],regname[rs],regname[shift]);
1498 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs)|0x10|(shift<<8));
1500 void emit_orrshr(u_int rs,u_int shift,u_int rt)
1505 assem_debug("orr %s,%s,%s,lsr %s\n",regname[rt],regname[rt],regname[rs],regname[shift]);
1506 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs)|0x30|(shift<<8));
1509 void emit_cmpimm(int rs,int imm)
1512 if(genimm(imm,&armval)) {
1513 assem_debug("cmp %s,#%d\n",regname[rs],imm);
1514 output_w32(0xe3500000|rd_rn_rm(0,rs,0)|armval);
1515 }else if(genimm(-imm,&armval)) {
1516 assem_debug("cmn %s,#%d\n",regname[rs],imm);
1517 output_w32(0xe3700000|rd_rn_rm(0,rs,0)|armval);
1520 emit_movimm(imm,HOST_TEMPREG);
1521 assem_debug("cmp %s,r14\n",regname[rs]);
1522 output_w32(0xe1500000|rd_rn_rm(0,rs,HOST_TEMPREG));
1525 emit_movimm(-imm,HOST_TEMPREG);
1526 assem_debug("cmn %s,r14\n",regname[rs]);
1527 output_w32(0xe1700000|rd_rn_rm(0,rs,HOST_TEMPREG));
1531 void emit_cmovne(u_int *addr,int rt)
1533 assem_debug("cmovne %x,%%%s",(int)addr,regname[rt]);
1536 void emit_cmovl(u_int *addr,int rt)
1538 assem_debug("cmovl %x,%%%s",(int)addr,regname[rt]);
1541 void emit_cmovs(u_int *addr,int rt)
1543 assem_debug("cmovs %x,%%%s",(int)addr,regname[rt]);
1546 void emit_cmovne_imm(int imm,int rt)
1548 assem_debug("movne %s,#%d\n",regname[rt],imm);
1550 genimm_checked(imm,&armval);
1551 output_w32(0x13a00000|rd_rn_rm(rt,0,0)|armval);
1553 void emit_cmovl_imm(int imm,int rt)
1555 assem_debug("movlt %s,#%d\n",regname[rt],imm);
1557 genimm_checked(imm,&armval);
1558 output_w32(0xb3a00000|rd_rn_rm(rt,0,0)|armval);
1560 void emit_cmovb_imm(int imm,int rt)
1562 assem_debug("movcc %s,#%d\n",regname[rt],imm);
1564 genimm_checked(imm,&armval);
1565 output_w32(0x33a00000|rd_rn_rm(rt,0,0)|armval);
1567 void emit_cmovs_imm(int imm,int rt)
1569 assem_debug("movmi %s,#%d\n",regname[rt],imm);
1571 genimm_checked(imm,&armval);
1572 output_w32(0x43a00000|rd_rn_rm(rt,0,0)|armval);
1574 void emit_cmove_reg(int rs,int rt)
1576 assem_debug("moveq %s,%s\n",regname[rt],regname[rs]);
1577 output_w32(0x01a00000|rd_rn_rm(rt,0,rs));
1579 void emit_cmovne_reg(int rs,int rt)
1581 assem_debug("movne %s,%s\n",regname[rt],regname[rs]);
1582 output_w32(0x11a00000|rd_rn_rm(rt,0,rs));
1584 void emit_cmovl_reg(int rs,int rt)
1586 assem_debug("movlt %s,%s\n",regname[rt],regname[rs]);
1587 output_w32(0xb1a00000|rd_rn_rm(rt,0,rs));
1589 void emit_cmovs_reg(int rs,int rt)
1591 assem_debug("movmi %s,%s\n",regname[rt],regname[rs]);
1592 output_w32(0x41a00000|rd_rn_rm(rt,0,rs));
1595 void emit_slti32(int rs,int imm,int rt)
1597 if(rs!=rt) emit_zeroreg(rt);
1598 emit_cmpimm(rs,imm);
1599 if(rs==rt) emit_movimm(0,rt);
1600 emit_cmovl_imm(1,rt);
1602 void emit_sltiu32(int rs,int imm,int rt)
1604 if(rs!=rt) emit_zeroreg(rt);
1605 emit_cmpimm(rs,imm);
1606 if(rs==rt) emit_movimm(0,rt);
1607 emit_cmovb_imm(1,rt);
1609 void emit_slti64_32(int rsh,int rsl,int imm,int rt)
1612 emit_slti32(rsl,imm,rt);
1616 emit_cmovne_imm(0,rt);
1617 emit_cmovs_imm(1,rt);
1621 emit_cmpimm(rsh,-1);
1622 emit_cmovne_imm(0,rt);
1623 emit_cmovl_imm(1,rt);
1626 void emit_sltiu64_32(int rsh,int rsl,int imm,int rt)
1629 emit_sltiu32(rsl,imm,rt);
1633 emit_cmovne_imm(0,rt);
1637 emit_cmpimm(rsh,-1);
1638 emit_cmovne_imm(1,rt);
1642 void emit_cmp(int rs,int rt)
1644 assem_debug("cmp %s,%s\n",regname[rs],regname[rt]);
1645 output_w32(0xe1500000|rd_rn_rm(0,rs,rt));
1647 void emit_set_gz32(int rs, int rt)
1649 //assem_debug("set_gz32\n");
1652 emit_cmovl_imm(0,rt);
1654 void emit_set_nz32(int rs, int rt)
1656 //assem_debug("set_nz32\n");
1657 if(rs!=rt) emit_movs(rs,rt);
1658 else emit_test(rs,rs);
1659 emit_cmovne_imm(1,rt);
1661 void emit_set_gz64_32(int rsh, int rsl, int rt)
1663 //assem_debug("set_gz64\n");
1664 emit_set_gz32(rsl,rt);
1666 emit_cmovne_imm(1,rt);
1667 emit_cmovs_imm(0,rt);
1669 void emit_set_nz64_32(int rsh, int rsl, int rt)
1671 //assem_debug("set_nz64\n");
1672 emit_or_and_set_flags(rsh,rsl,rt);
1673 emit_cmovne_imm(1,rt);
1675 void emit_set_if_less32(int rs1, int rs2, int rt)
1677 //assem_debug("set if less (%%%s,%%%s),%%%s\n",regname[rs1],regname[rs2],regname[rt]);
1678 if(rs1!=rt&&rs2!=rt) emit_zeroreg(rt);
1680 if(rs1==rt||rs2==rt) emit_movimm(0,rt);
1681 emit_cmovl_imm(1,rt);
1683 void emit_set_if_carry32(int rs1, int rs2, int rt)
1685 //assem_debug("set if carry (%%%s,%%%s),%%%s\n",regname[rs1],regname[rs2],regname[rt]);
1686 if(rs1!=rt&&rs2!=rt) emit_zeroreg(rt);
1688 if(rs1==rt||rs2==rt) emit_movimm(0,rt);
1689 emit_cmovb_imm(1,rt);
1691 void emit_set_if_less64_32(int u1, int l1, int u2, int l2, int rt)
1693 //assem_debug("set if less64 (%%%s,%%%s,%%%s,%%%s),%%%s\n",regname[u1],regname[l1],regname[u2],regname[l2],regname[rt]);
1698 emit_sbcs(u1,u2,HOST_TEMPREG);
1699 emit_cmovl_imm(1,rt);
1701 void emit_set_if_carry64_32(int u1, int l1, int u2, int l2, int rt)
1703 //assem_debug("set if carry64 (%%%s,%%%s,%%%s,%%%s),%%%s\n",regname[u1],regname[l1],regname[u2],regname[l2],regname[rt]);
1708 emit_sbcs(u1,u2,HOST_TEMPREG);
1709 emit_cmovb_imm(1,rt);
1712 void emit_call(int a)
1714 assem_debug("bl %x (%x+%x)\n",a,(int)out,a-(int)out-8);
1715 u_int offset=genjmp(a);
1716 output_w32(0xeb000000|offset);
1718 void emit_jmp(int a)
1720 assem_debug("b %x (%x+%x)\n",a,(int)out,a-(int)out-8);
1721 u_int offset=genjmp(a);
1722 output_w32(0xea000000|offset);
1724 void emit_jne(int a)
1726 assem_debug("bne %x\n",a);
1727 u_int offset=genjmp(a);
1728 output_w32(0x1a000000|offset);
1730 void emit_jeq(int a)
1732 assem_debug("beq %x\n",a);
1733 u_int offset=genjmp(a);
1734 output_w32(0x0a000000|offset);
1738 assem_debug("bmi %x\n",a);
1739 u_int offset=genjmp(a);
1740 output_w32(0x4a000000|offset);
1742 void emit_jns(int a)
1744 assem_debug("bpl %x\n",a);
1745 u_int offset=genjmp(a);
1746 output_w32(0x5a000000|offset);
1750 assem_debug("blt %x\n",a);
1751 u_int offset=genjmp(a);
1752 output_w32(0xba000000|offset);
1754 void emit_jge(int a)
1756 assem_debug("bge %x\n",a);
1757 u_int offset=genjmp(a);
1758 output_w32(0xaa000000|offset);
1760 void emit_jno(int a)
1762 assem_debug("bvc %x\n",a);
1763 u_int offset=genjmp(a);
1764 output_w32(0x7a000000|offset);
1768 assem_debug("bcs %x\n",a);
1769 u_int offset=genjmp(a);
1770 output_w32(0x2a000000|offset);
1772 void emit_jcc(int a)
1774 assem_debug("bcc %x\n",a);
1775 u_int offset=genjmp(a);
1776 output_w32(0x3a000000|offset);
1779 void emit_pushimm(int imm)
1781 assem_debug("push $%x\n",imm);
1786 assem_debug("pusha\n");
1791 assem_debug("popa\n");
1794 void emit_pushreg(u_int r)
1796 assem_debug("push %%%s\n",regname[r]);
1799 void emit_popreg(u_int r)
1801 assem_debug("pop %%%s\n",regname[r]);
1804 void emit_callreg(u_int r)
1807 assem_debug("blx %s\n",regname[r]);
1808 output_w32(0xe12fff30|r);
1810 void emit_jmpreg(u_int r)
1812 assem_debug("mov pc,%s\n",regname[r]);
1813 output_w32(0xe1a00000|rd_rn_rm(15,0,r));
1816 void emit_readword_indexed(int offset, int rs, int rt)
1818 assert(offset>-4096&&offset<4096);
1819 assem_debug("ldr %s,%s+%d\n",regname[rt],regname[rs],offset);
1821 output_w32(0xe5900000|rd_rn_rm(rt,rs,0)|offset);
1823 output_w32(0xe5100000|rd_rn_rm(rt,rs,0)|(-offset));
1826 void emit_readword_dualindexedx4(int rs1, int rs2, int rt)
1828 assem_debug("ldr %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
1829 output_w32(0xe7900000|rd_rn_rm(rt,rs1,rs2)|0x100);
1831 void emit_ldrcc_dualindexed(int rs1, int rs2, int rt)
1833 assem_debug("ldrcc %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1834 output_w32(0x37900000|rd_rn_rm(rt,rs1,rs2));
1836 void emit_ldrccb_dualindexed(int rs1, int rs2, int rt)
1838 assem_debug("ldrccb %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1839 output_w32(0x37d00000|rd_rn_rm(rt,rs1,rs2));
1841 void emit_ldrccsb_dualindexed(int rs1, int rs2, int rt)
1843 assem_debug("ldrccsb %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1844 output_w32(0x319000d0|rd_rn_rm(rt,rs1,rs2));
1846 void emit_ldrcch_dualindexed(int rs1, int rs2, int rt)
1848 assem_debug("ldrcch %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1849 output_w32(0x319000b0|rd_rn_rm(rt,rs1,rs2));
1851 void emit_ldrccsh_dualindexed(int rs1, int rs2, int rt)
1853 assem_debug("ldrccsh %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1854 output_w32(0x319000f0|rd_rn_rm(rt,rs1,rs2));
1856 void emit_readword_indexed_tlb(int addr, int rs, int map, int rt)
1858 if(map<0) emit_readword_indexed(addr, rs, rt);
1861 emit_readword_dualindexedx4(rs, map, rt);
1864 void emit_readdword_indexed_tlb(int addr, int rs, int map, int rh, int rl)
1867 if(rh>=0) emit_readword_indexed(addr, rs, rh);
1868 emit_readword_indexed(addr+4, rs, rl);
1871 if(rh>=0) emit_readword_indexed_tlb(addr, rs, map, rh);
1872 emit_addimm(map,1,map);
1873 emit_readword_indexed_tlb(addr, rs, map, rl);
1876 void emit_movsbl_indexed(int offset, int rs, int rt)
1878 assert(offset>-256&&offset<256);
1879 assem_debug("ldrsb %s,%s+%d\n",regname[rt],regname[rs],offset);
1881 output_w32(0xe1d000d0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1883 output_w32(0xe15000d0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1886 void emit_movsbl_indexed_tlb(int addr, int rs, int map, int rt)
1888 if(map<0) emit_movsbl_indexed(addr, rs, rt);
1891 emit_shlimm(map,2,map);
1892 assem_debug("ldrsb %s,%s+%s\n",regname[rt],regname[rs],regname[map]);
1893 output_w32(0xe19000d0|rd_rn_rm(rt,rs,map));
1895 assert(addr>-256&&addr<256);
1896 assem_debug("add %s,%s,%s,lsl #2\n",regname[rt],regname[rs],regname[map]);
1897 output_w32(0xe0800000|rd_rn_rm(rt,rs,map)|(2<<7));
1898 emit_movsbl_indexed(addr, rt, rt);
1902 void emit_movswl_indexed(int offset, int rs, int rt)
1904 assert(offset>-256&&offset<256);
1905 assem_debug("ldrsh %s,%s+%d\n",regname[rt],regname[rs],offset);
1907 output_w32(0xe1d000f0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1909 output_w32(0xe15000f0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1912 void emit_movzbl_indexed(int offset, int rs, int rt)
1914 assert(offset>-4096&&offset<4096);
1915 assem_debug("ldrb %s,%s+%d\n",regname[rt],regname[rs],offset);
1917 output_w32(0xe5d00000|rd_rn_rm(rt,rs,0)|offset);
1919 output_w32(0xe5500000|rd_rn_rm(rt,rs,0)|(-offset));
1922 void emit_movzbl_dualindexedx4(int rs1, int rs2, int rt)
1924 assem_debug("ldrb %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
1925 output_w32(0xe7d00000|rd_rn_rm(rt,rs1,rs2)|0x100);
1927 void emit_movzbl_indexed_tlb(int addr, int rs, int map, int rt)
1929 if(map<0) emit_movzbl_indexed(addr, rs, rt);
1932 emit_movzbl_dualindexedx4(rs, map, rt);
1934 emit_addimm(rs,addr,rt);
1935 emit_movzbl_dualindexedx4(rt, map, rt);
1939 void emit_movzwl_indexed(int offset, int rs, int rt)
1941 assert(offset>-256&&offset<256);
1942 assem_debug("ldrh %s,%s+%d\n",regname[rt],regname[rs],offset);
1944 output_w32(0xe1d000b0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1946 output_w32(0xe15000b0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1949 static void emit_ldrd(int offset, int rs, int rt)
1951 assert(offset>-256&&offset<256);
1952 assem_debug("ldrd %s,%s+%d\n",regname[rt],regname[rs],offset);
1954 output_w32(0xe1c000d0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1956 output_w32(0xe14000d0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1959 void emit_readword(int addr, int rt)
1961 u_int offset = addr-(u_int)&dynarec_local;
1962 assert(offset<4096);
1963 assem_debug("ldr %s,fp+%d\n",regname[rt],offset);
1964 output_w32(0xe5900000|rd_rn_rm(rt,FP,0)|offset);
1966 void emit_movsbl(int addr, int rt)
1968 u_int offset = addr-(u_int)&dynarec_local;
1970 assem_debug("ldrsb %s,fp+%d\n",regname[rt],offset);
1971 output_w32(0xe1d000d0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
1973 void emit_movswl(int addr, int rt)
1975 u_int offset = addr-(u_int)&dynarec_local;
1977 assem_debug("ldrsh %s,fp+%d\n",regname[rt],offset);
1978 output_w32(0xe1d000f0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
1980 void emit_movzbl(int addr, int rt)
1982 u_int offset = addr-(u_int)&dynarec_local;
1983 assert(offset<4096);
1984 assem_debug("ldrb %s,fp+%d\n",regname[rt],offset);
1985 output_w32(0xe5d00000|rd_rn_rm(rt,FP,0)|offset);
1987 void emit_movzwl(int addr, int rt)
1989 u_int offset = addr-(u_int)&dynarec_local;
1991 assem_debug("ldrh %s,fp+%d\n",regname[rt],offset);
1992 output_w32(0xe1d000b0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
1994 void emit_movzwl_reg(int rs, int rt)
1996 assem_debug("movzwl %%%s,%%%s\n",regname[rs]+1,regname[rt]);
2000 void emit_xchg(int rs, int rt)
2002 assem_debug("xchg %%%s,%%%s\n",regname[rs],regname[rt]);
2005 void emit_writeword_indexed(int rt, int offset, int rs)
2007 assert(offset>-4096&&offset<4096);
2008 assem_debug("str %s,%s+%d\n",regname[rt],regname[rs],offset);
2010 output_w32(0xe5800000|rd_rn_rm(rt,rs,0)|offset);
2012 output_w32(0xe5000000|rd_rn_rm(rt,rs,0)|(-offset));
2015 void emit_writeword_dualindexedx4(int rt, int rs1, int rs2)
2017 assem_debug("str %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
2018 output_w32(0xe7800000|rd_rn_rm(rt,rs1,rs2)|0x100);
2020 void emit_writeword_indexed_tlb(int rt, int addr, int rs, int map, int temp)
2022 if(map<0) emit_writeword_indexed(rt, addr, rs);
2025 emit_writeword_dualindexedx4(rt, rs, map);
2028 void emit_writedword_indexed_tlb(int rh, int rl, int addr, int rs, int map, int temp)
2031 if(rh>=0) emit_writeword_indexed(rh, addr, rs);
2032 emit_writeword_indexed(rl, addr+4, rs);
2035 if(temp!=rs) emit_addimm(map,1,temp);
2036 emit_writeword_indexed_tlb(rh, addr, rs, map, temp);
2037 if(temp!=rs) emit_writeword_indexed_tlb(rl, addr, rs, temp, temp);
2039 emit_addimm(rs,4,rs);
2040 emit_writeword_indexed_tlb(rl, addr, rs, map, temp);
2044 void emit_writehword_indexed(int rt, int offset, int rs)
2046 assert(offset>-256&&offset<256);
2047 assem_debug("strh %s,%s+%d\n",regname[rt],regname[rs],offset);
2049 output_w32(0xe1c000b0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
2051 output_w32(0xe14000b0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
2054 void emit_writebyte_indexed(int rt, int offset, int rs)
2056 assert(offset>-4096&&offset<4096);
2057 assem_debug("strb %s,%s+%d\n",regname[rt],regname[rs],offset);
2059 output_w32(0xe5c00000|rd_rn_rm(rt,rs,0)|offset);
2061 output_w32(0xe5400000|rd_rn_rm(rt,rs,0)|(-offset));
2064 void emit_writebyte_dualindexedx4(int rt, int rs1, int rs2)
2066 assem_debug("strb %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
2067 output_w32(0xe7c00000|rd_rn_rm(rt,rs1,rs2)|0x100);
2069 void emit_writebyte_indexed_tlb(int rt, int addr, int rs, int map, int temp)
2071 if(map<0) emit_writebyte_indexed(rt, addr, rs);
2074 emit_writebyte_dualindexedx4(rt, rs, map);
2076 emit_addimm(rs,addr,temp);
2077 emit_writebyte_dualindexedx4(rt, temp, map);
2081 void emit_strcc_dualindexed(int rs1, int rs2, int rt)
2083 assem_debug("strcc %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2084 output_w32(0x37800000|rd_rn_rm(rt,rs1,rs2));
2086 void emit_strccb_dualindexed(int rs1, int rs2, int rt)
2088 assem_debug("strccb %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2089 output_w32(0x37c00000|rd_rn_rm(rt,rs1,rs2));
2091 void emit_strcch_dualindexed(int rs1, int rs2, int rt)
2093 assem_debug("strcch %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2094 output_w32(0x318000b0|rd_rn_rm(rt,rs1,rs2));
2096 void emit_writeword(int rt, int addr)
2098 u_int offset = addr-(u_int)&dynarec_local;
2099 assert(offset<4096);
2100 assem_debug("str %s,fp+%d\n",regname[rt],offset);
2101 output_w32(0xe5800000|rd_rn_rm(rt,FP,0)|offset);
2103 void emit_writehword(int rt, int addr)
2105 u_int offset = addr-(u_int)&dynarec_local;
2107 assem_debug("strh %s,fp+%d\n",regname[rt],offset);
2108 output_w32(0xe1c000b0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
2110 void emit_writebyte(int rt, int addr)
2112 u_int offset = addr-(u_int)&dynarec_local;
2113 assert(offset<4096);
2114 assem_debug("strb %s,fp+%d\n",regname[rt],offset);
2115 output_w32(0xe5c00000|rd_rn_rm(rt,FP,0)|offset);
2117 void emit_writeword_imm(int imm, int addr)
2119 assem_debug("movl $%x,%x\n",imm,addr);
2122 void emit_writebyte_imm(int imm, int addr)
2124 assem_debug("movb $%x,%x\n",imm,addr);
2128 void emit_mul(int rs)
2130 assem_debug("mul %%%s\n",regname[rs]);
2133 void emit_imul(int rs)
2135 assem_debug("imul %%%s\n",regname[rs]);
2138 void emit_umull(u_int rs1, u_int rs2, u_int hi, u_int lo)
2140 assem_debug("umull %s, %s, %s, %s\n",regname[lo],regname[hi],regname[rs1],regname[rs2]);
2145 output_w32(0xe0800090|(hi<<16)|(lo<<12)|(rs2<<8)|rs1);
2147 void emit_smull(u_int rs1, u_int rs2, u_int hi, u_int lo)
2149 assem_debug("smull %s, %s, %s, %s\n",regname[lo],regname[hi],regname[rs1],regname[rs2]);
2154 output_w32(0xe0c00090|(hi<<16)|(lo<<12)|(rs2<<8)|rs1);
2157 void emit_div(int rs)
2159 assem_debug("div %%%s\n",regname[rs]);
2162 void emit_idiv(int rs)
2164 assem_debug("idiv %%%s\n",regname[rs]);
2169 assem_debug("cdq\n");
2173 void emit_clz(int rs,int rt)
2175 assem_debug("clz %s,%s\n",regname[rt],regname[rs]);
2176 output_w32(0xe16f0f10|rd_rn_rm(rt,0,rs));
2179 void emit_subcs(int rs1,int rs2,int rt)
2181 assem_debug("subcs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2182 output_w32(0x20400000|rd_rn_rm(rt,rs1,rs2));
2185 void emit_shrcc_imm(int rs,u_int imm,int rt)
2189 assem_debug("lsrcc %s,%s,#%d\n",regname[rt],regname[rs],imm);
2190 output_w32(0x31a00000|rd_rn_rm(rt,0,rs)|0x20|(imm<<7));
2193 void emit_shrne_imm(int rs,u_int imm,int rt)
2197 assem_debug("lsrne %s,%s,#%d\n",regname[rt],regname[rs],imm);
2198 output_w32(0x11a00000|rd_rn_rm(rt,0,rs)|0x20|(imm<<7));
2201 void emit_negmi(int rs, int rt)
2203 assem_debug("rsbmi %s,%s,#0\n",regname[rt],regname[rs]);
2204 output_w32(0x42600000|rd_rn_rm(rt,rs,0));
2207 void emit_negsmi(int rs, int rt)
2209 assem_debug("rsbsmi %s,%s,#0\n",regname[rt],regname[rs]);
2210 output_w32(0x42700000|rd_rn_rm(rt,rs,0));
2213 void emit_orreq(u_int rs1,u_int rs2,u_int rt)
2215 assem_debug("orreq %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2216 output_w32(0x01800000|rd_rn_rm(rt,rs1,rs2));
2219 void emit_orrne(u_int rs1,u_int rs2,u_int rt)
2221 assem_debug("orrne %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2222 output_w32(0x11800000|rd_rn_rm(rt,rs1,rs2));
2225 void emit_bic_lsl(u_int rs1,u_int rs2,u_int shift,u_int rt)
2227 assem_debug("bic %s,%s,%s lsl %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2228 output_w32(0xe1C00000|rd_rn_rm(rt,rs1,rs2)|0x10|(shift<<8));
2231 void emit_biceq_lsl(u_int rs1,u_int rs2,u_int shift,u_int rt)
2233 assem_debug("biceq %s,%s,%s lsl %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2234 output_w32(0x01C00000|rd_rn_rm(rt,rs1,rs2)|0x10|(shift<<8));
2237 void emit_bicne_lsl(u_int rs1,u_int rs2,u_int shift,u_int rt)
2239 assem_debug("bicne %s,%s,%s lsl %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2240 output_w32(0x11C00000|rd_rn_rm(rt,rs1,rs2)|0x10|(shift<<8));
2243 void emit_bic_lsr(u_int rs1,u_int rs2,u_int shift,u_int rt)
2245 assem_debug("bic %s,%s,%s lsr %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2246 output_w32(0xe1C00000|rd_rn_rm(rt,rs1,rs2)|0x30|(shift<<8));
2249 void emit_biceq_lsr(u_int rs1,u_int rs2,u_int shift,u_int rt)
2251 assem_debug("biceq %s,%s,%s lsr %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2252 output_w32(0x01C00000|rd_rn_rm(rt,rs1,rs2)|0x30|(shift<<8));
2255 void emit_bicne_lsr(u_int rs1,u_int rs2,u_int shift,u_int rt)
2257 assem_debug("bicne %s,%s,%s lsr %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2258 output_w32(0x11C00000|rd_rn_rm(rt,rs1,rs2)|0x30|(shift<<8));
2261 void emit_teq(int rs, int rt)
2263 assem_debug("teq %s,%s\n",regname[rs],regname[rt]);
2264 output_w32(0xe1300000|rd_rn_rm(0,rs,rt));
2267 void emit_rsbimm(int rs, int imm, int rt)
2270 genimm_checked(imm,&armval);
2271 assem_debug("rsb %s,%s,#%d\n",regname[rt],regname[rs],imm);
2272 output_w32(0xe2600000|rd_rn_rm(rt,rs,0)|armval);
2275 // Load 2 immediates optimizing for small code size
2276 void emit_mov2imm_compact(int imm1,u_int rt1,int imm2,u_int rt2)
2278 emit_movimm(imm1,rt1);
2280 if(genimm(imm2-imm1,&armval)) {
2281 assem_debug("add %s,%s,#%d\n",regname[rt2],regname[rt1],imm2-imm1);
2282 output_w32(0xe2800000|rd_rn_rm(rt2,rt1,0)|armval);
2283 }else if(genimm(imm1-imm2,&armval)) {
2284 assem_debug("sub %s,%s,#%d\n",regname[rt2],regname[rt1],imm1-imm2);
2285 output_w32(0xe2400000|rd_rn_rm(rt2,rt1,0)|armval);
2287 else emit_movimm(imm2,rt2);
2290 // Conditionally select one of two immediates, optimizing for small code size
2291 // This will only be called if HAVE_CMOV_IMM is defined
2292 void emit_cmov2imm_e_ne_compact(int imm1,int imm2,u_int rt)
2295 if(genimm(imm2-imm1,&armval)) {
2296 emit_movimm(imm1,rt);
2297 assem_debug("addne %s,%s,#%d\n",regname[rt],regname[rt],imm2-imm1);
2298 output_w32(0x12800000|rd_rn_rm(rt,rt,0)|armval);
2299 }else if(genimm(imm1-imm2,&armval)) {
2300 emit_movimm(imm1,rt);
2301 assem_debug("subne %s,%s,#%d\n",regname[rt],regname[rt],imm1-imm2);
2302 output_w32(0x12400000|rd_rn_rm(rt,rt,0)|armval);
2306 emit_movimm(imm1,rt);
2307 add_literal((int)out,imm2);
2308 assem_debug("ldrne %s,pc+? [=%x]\n",regname[rt],imm2);
2309 output_w32(0x15900000|rd_rn_rm(rt,15,0));
2311 emit_movw(imm1&0x0000FFFF,rt);
2312 if((imm1&0xFFFF)!=(imm2&0xFFFF)) {
2313 assem_debug("movwne %s,#%d (0x%x)\n",regname[rt],imm2&0xFFFF,imm2&0xFFFF);
2314 output_w32(0x13000000|rd_rn_rm(rt,0,0)|(imm2&0xfff)|((imm2<<4)&0xf0000));
2316 emit_movt(imm1&0xFFFF0000,rt);
2317 if((imm1&0xFFFF0000)!=(imm2&0xFFFF0000)) {
2318 assem_debug("movtne %s,#%d (0x%x)\n",regname[rt],imm2&0xffff0000,imm2&0xffff0000);
2319 output_w32(0x13400000|rd_rn_rm(rt,0,0)|((imm2>>16)&0xfff)|((imm2>>12)&0xf0000));
2325 // special case for checking invalid_code
2326 void emit_cmpmem_indexedsr12_imm(int addr,int r,int imm)
2331 // special case for checking invalid_code
2332 void emit_cmpmem_indexedsr12_reg(int base,int r,int imm)
2334 assert(imm<128&&imm>=0);
2336 assem_debug("ldrb lr,%s,%s lsr #12\n",regname[base],regname[r]);
2337 output_w32(0xe7d00000|rd_rn_rm(HOST_TEMPREG,base,r)|0x620);
2338 emit_cmpimm(HOST_TEMPREG,imm);
2341 // special case for tlb mapping
2342 void emit_addsr12(int rs1,int rs2,int rt)
2344 assem_debug("add %s,%s,%s lsr #12\n",regname[rt],regname[rs1],regname[rs2]);
2345 output_w32(0xe0800620|rd_rn_rm(rt,rs1,rs2));
2348 void emit_callne(int a)
2350 assem_debug("blne %x\n",a);
2351 u_int offset=genjmp(a);
2352 output_w32(0x1b000000|offset);
2355 // Used to preload hash table entries
2356 void emit_prefetch(void *addr)
2358 assem_debug("prefetch %x\n",(int)addr);
2361 output_modrm(0,5,1);
2362 output_w32((int)addr);
2364 void emit_prefetchreg(int r)
2366 assem_debug("pld %s\n",regname[r]);
2367 output_w32(0xf5d0f000|rd_rn_rm(0,r,0));
2370 // Special case for mini_ht
2371 void emit_ldreq_indexed(int rs, u_int offset, int rt)
2373 assert(offset<4096);
2374 assem_debug("ldreq %s,[%s, #%d]\n",regname[rt],regname[rs],offset);
2375 output_w32(0x05900000|rd_rn_rm(rt,rs,0)|offset);
2378 void emit_flds(int r,int sr)
2380 assem_debug("flds s%d,[%s]\n",sr,regname[r]);
2381 output_w32(0xed900a00|((sr&14)<<11)|((sr&1)<<22)|(r<<16));
2384 void emit_vldr(int r,int vr)
2386 assem_debug("vldr d%d,[%s]\n",vr,regname[r]);
2387 output_w32(0xed900b00|(vr<<12)|(r<<16));
2390 void emit_fsts(int sr,int r)
2392 assem_debug("fsts s%d,[%s]\n",sr,regname[r]);
2393 output_w32(0xed800a00|((sr&14)<<11)|((sr&1)<<22)|(r<<16));
2396 void emit_vstr(int vr,int r)
2398 assem_debug("vstr d%d,[%s]\n",vr,regname[r]);
2399 output_w32(0xed800b00|(vr<<12)|(r<<16));
2402 void emit_ftosizs(int s,int d)
2404 assem_debug("ftosizs s%d,s%d\n",d,s);
2405 output_w32(0xeebd0ac0|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
2408 void emit_ftosizd(int s,int d)
2410 assem_debug("ftosizd s%d,d%d\n",d,s);
2411 output_w32(0xeebd0bc0|((d&14)<<11)|((d&1)<<22)|(s&7));
2414 void emit_fsitos(int s,int d)
2416 assem_debug("fsitos s%d,s%d\n",d,s);
2417 output_w32(0xeeb80ac0|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
2420 void emit_fsitod(int s,int d)
2422 assem_debug("fsitod d%d,s%d\n",d,s);
2423 output_w32(0xeeb80bc0|((d&7)<<12)|((s&14)>>1)|((s&1)<<5));
2426 void emit_fcvtds(int s,int d)
2428 assem_debug("fcvtds d%d,s%d\n",d,s);
2429 output_w32(0xeeb70ac0|((d&7)<<12)|((s&14)>>1)|((s&1)<<5));
2432 void emit_fcvtsd(int s,int d)
2434 assem_debug("fcvtsd s%d,d%d\n",d,s);
2435 output_w32(0xeeb70bc0|((d&14)<<11)|((d&1)<<22)|(s&7));
2438 void emit_fsqrts(int s,int d)
2440 assem_debug("fsqrts d%d,s%d\n",d,s);
2441 output_w32(0xeeb10ac0|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
2444 void emit_fsqrtd(int s,int d)
2446 assem_debug("fsqrtd s%d,d%d\n",d,s);
2447 output_w32(0xeeb10bc0|((d&7)<<12)|(s&7));
2450 void emit_fabss(int s,int d)
2452 assem_debug("fabss d%d,s%d\n",d,s);
2453 output_w32(0xeeb00ac0|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
2456 void emit_fabsd(int s,int d)
2458 assem_debug("fabsd s%d,d%d\n",d,s);
2459 output_w32(0xeeb00bc0|((d&7)<<12)|(s&7));
2462 void emit_fnegs(int s,int d)
2464 assem_debug("fnegs d%d,s%d\n",d,s);
2465 output_w32(0xeeb10a40|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
2468 void emit_fnegd(int s,int d)
2470 assem_debug("fnegd s%d,d%d\n",d,s);
2471 output_w32(0xeeb10b40|((d&7)<<12)|(s&7));
2474 void emit_fadds(int s1,int s2,int d)
2476 assem_debug("fadds s%d,s%d,s%d\n",d,s1,s2);
2477 output_w32(0xee300a00|((d&14)<<11)|((d&1)<<22)|((s1&14)<<15)|((s1&1)<<7)|((s2&14)>>1)|((s2&1)<<5));
2480 void emit_faddd(int s1,int s2,int d)
2482 assem_debug("faddd d%d,d%d,d%d\n",d,s1,s2);
2483 output_w32(0xee300b00|((d&7)<<12)|((s1&7)<<16)|(s2&7));
2486 void emit_fsubs(int s1,int s2,int d)
2488 assem_debug("fsubs s%d,s%d,s%d\n",d,s1,s2);
2489 output_w32(0xee300a40|((d&14)<<11)|((d&1)<<22)|((s1&14)<<15)|((s1&1)<<7)|((s2&14)>>1)|((s2&1)<<5));
2492 void emit_fsubd(int s1,int s2,int d)
2494 assem_debug("fsubd d%d,d%d,d%d\n",d,s1,s2);
2495 output_w32(0xee300b40|((d&7)<<12)|((s1&7)<<16)|(s2&7));
2498 void emit_fmuls(int s1,int s2,int d)
2500 assem_debug("fmuls s%d,s%d,s%d\n",d,s1,s2);
2501 output_w32(0xee200a00|((d&14)<<11)|((d&1)<<22)|((s1&14)<<15)|((s1&1)<<7)|((s2&14)>>1)|((s2&1)<<5));
2504 void emit_fmuld(int s1,int s2,int d)
2506 assem_debug("fmuld d%d,d%d,d%d\n",d,s1,s2);
2507 output_w32(0xee200b00|((d&7)<<12)|((s1&7)<<16)|(s2&7));
2510 void emit_fdivs(int s1,int s2,int d)
2512 assem_debug("fdivs s%d,s%d,s%d\n",d,s1,s2);
2513 output_w32(0xee800a00|((d&14)<<11)|((d&1)<<22)|((s1&14)<<15)|((s1&1)<<7)|((s2&14)>>1)|((s2&1)<<5));
2516 void emit_fdivd(int s1,int s2,int d)
2518 assem_debug("fdivd d%d,d%d,d%d\n",d,s1,s2);
2519 output_w32(0xee800b00|((d&7)<<12)|((s1&7)<<16)|(s2&7));
2522 void emit_fcmps(int x,int y)
2524 assem_debug("fcmps s14, s15\n");
2525 output_w32(0xeeb47a67);
2528 void emit_fcmpd(int x,int y)
2530 assem_debug("fcmpd d6, d7\n");
2531 output_w32(0xeeb46b47);
2536 assem_debug("fmstat\n");
2537 output_w32(0xeef1fa10);
2540 void emit_bicne_imm(int rs,int imm,int rt)
2543 genimm_checked(imm,&armval);
2544 assem_debug("bicne %s,%s,#%d\n",regname[rt],regname[rs],imm);
2545 output_w32(0x13c00000|rd_rn_rm(rt,rs,0)|armval);
2548 void emit_biccs_imm(int rs,int imm,int rt)
2551 genimm_checked(imm,&armval);
2552 assem_debug("biccs %s,%s,#%d\n",regname[rt],regname[rs],imm);
2553 output_w32(0x23c00000|rd_rn_rm(rt,rs,0)|armval);
2556 void emit_bicvc_imm(int rs,int imm,int rt)
2559 genimm_checked(imm,&armval);
2560 assem_debug("bicvc %s,%s,#%d\n",regname[rt],regname[rs],imm);
2561 output_w32(0x73c00000|rd_rn_rm(rt,rs,0)|armval);
2564 void emit_bichi_imm(int rs,int imm,int rt)
2567 genimm_checked(imm,&armval);
2568 assem_debug("bichi %s,%s,#%d\n",regname[rt],regname[rs],imm);
2569 output_w32(0x83c00000|rd_rn_rm(rt,rs,0)|armval);
2572 void emit_orrvs_imm(int rs,int imm,int rt)
2575 genimm_checked(imm,&armval);
2576 assem_debug("orrvs %s,%s,#%d\n",regname[rt],regname[rs],imm);
2577 output_w32(0x63800000|rd_rn_rm(rt,rs,0)|armval);
2580 void emit_orrne_imm(int rs,int imm,int rt)
2583 genimm_checked(imm,&armval);
2584 assem_debug("orrne %s,%s,#%d\n",regname[rt],regname[rs],imm);
2585 output_w32(0x13800000|rd_rn_rm(rt,rs,0)|armval);
2588 void emit_andne_imm(int rs,int imm,int rt)
2591 genimm_checked(imm,&armval);
2592 assem_debug("andne %s,%s,#%d\n",regname[rt],regname[rs],imm);
2593 output_w32(0x12000000|rd_rn_rm(rt,rs,0)|armval);
2596 void emit_addpl_imm(int rs,int imm,int rt)
2599 genimm_checked(imm,&armval);
2600 assem_debug("addpl %s,%s,#%d\n",regname[rt],regname[rs],imm);
2601 output_w32(0x52800000|rd_rn_rm(rt,rs,0)|armval);
2604 void emit_jno_unlikely(int a)
2607 assem_debug("addvc pc,pc,#? (%x)\n",/*a-(int)out-8,*/a);
2608 output_w32(0x72800000|rd_rn_rm(15,15,0));
2611 static void save_regs_all(u_int reglist)
2614 if(!reglist) return;
2615 assem_debug("stmia fp,{");
2618 assem_debug("r%d,",i);
2620 output_w32(0xe88b0000|reglist);
2622 static void restore_regs_all(u_int reglist)
2625 if(!reglist) return;
2626 assem_debug("ldmia fp,{");
2629 assem_debug("r%d,",i);
2631 output_w32(0xe89b0000|reglist);
2633 // Save registers before function call
2634 static void save_regs(u_int reglist)
2636 reglist&=CALLER_SAVE_REGS; // only save the caller-save registers, r0-r3, r12
2637 save_regs_all(reglist);
2639 // Restore registers after function call
2640 static void restore_regs(u_int reglist)
2642 reglist&=CALLER_SAVE_REGS;
2643 restore_regs_all(reglist);
2646 // Write back consts using r14 so we don't disturb the other registers
2647 void wb_consts(signed char i_regmap[],uint64_t i_is32,u_int i_dirty,int i)
2650 for(hr=0;hr<HOST_REGS;hr++) {
2651 if(hr!=EXCLUDE_REG&&i_regmap[hr]>=0&&((i_dirty>>hr)&1)) {
2652 if(((regs[i].isconst>>hr)&1)&&i_regmap[hr]>0) {
2653 if(i_regmap[hr]<64 || !((i_is32>>(i_regmap[hr]&63))&1) ) {
2654 int value=constmap[i][hr];
2656 emit_zeroreg(HOST_TEMPREG);
2659 emit_movimm(value,HOST_TEMPREG);
2661 emit_storereg(i_regmap[hr],HOST_TEMPREG);
2663 if((i_is32>>i_regmap[hr])&1) {
2664 if(value!=-1&&value!=0) emit_sarimm(HOST_TEMPREG,31,HOST_TEMPREG);
2665 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
2674 /* Stubs/epilogue */
2676 void literal_pool(int n)
2678 if(!literalcount) return;
2680 if((int)out-literals[0][0]<4096-n) return;
2684 for(i=0;i<literalcount;i++)
2686 u_int l_addr=(u_int)out;
2689 if(literals[j][1]==literals[i][1]) {
2690 //printf("dup %08x\n",literals[i][1]);
2691 l_addr=literals[j][0];
2695 ptr=(u_int *)literals[i][0];
2696 u_int offset=l_addr-(u_int)ptr-8;
2697 assert(offset<4096);
2698 assert(!(offset&3));
2700 if(l_addr==(u_int)out) {
2701 literals[i][0]=l_addr; // remember for dupes
2702 output_w32(literals[i][1]);
2708 void literal_pool_jumpover(int n)
2710 if(!literalcount) return;
2712 if((int)out-literals[0][0]<4096-n) return;
2717 set_jump_target(jaddr,(int)out);
2720 emit_extjump2(u_int addr, int target, int linker)
2722 u_char *ptr=(u_char *)addr;
2723 assert((ptr[3]&0x0e)==0xa);
2724 emit_loadlp(target,0);
2725 emit_loadlp(addr,1);
2726 assert(addr>=BASE_ADDR&&addr<(BASE_ADDR+(1<<TARGET_SIZE_2)));
2727 //assert((target>=0x80000000&&target<0x80800000)||(target>0xA4000000&&target<0xA4001000));
2729 #ifdef DEBUG_CYCLE_COUNT
2730 emit_readword((int)&last_count,ECX);
2731 emit_add(HOST_CCREG,ECX,HOST_CCREG);
2732 emit_readword((int)&next_interupt,ECX);
2733 emit_writeword(HOST_CCREG,(int)&Count);
2734 emit_sub(HOST_CCREG,ECX,HOST_CCREG);
2735 emit_writeword(ECX,(int)&last_count);
2741 emit_extjump(int addr, int target)
2743 emit_extjump2(addr, target, (int)dyna_linker);
2745 emit_extjump_ds(int addr, int target)
2747 emit_extjump2(addr, target, (int)dyna_linker_ds);
2750 // put rt_val into rt, potentially making use of rs with value rs_val
2751 static void emit_movimm_from(u_int rs_val,int rs,u_int rt_val,int rt)
2755 if(genimm(rt_val,&armval)) {
2756 assem_debug("mov %s,#%d\n",regname[rt],rt_val);
2757 output_w32(0xe3a00000|rd_rn_rm(rt,0,0)|armval);
2760 if(genimm(~rt_val,&armval)) {
2761 assem_debug("mvn %s,#%d\n",regname[rt],rt_val);
2762 output_w32(0xe3e00000|rd_rn_rm(rt,0,0)|armval);
2766 if(genimm(diff,&armval)) {
2767 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rs],diff);
2768 output_w32(0xe2800000|rd_rn_rm(rt,rs,0)|armval);
2770 }else if(genimm(-diff,&armval)) {
2771 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rs],-diff);
2772 output_w32(0xe2400000|rd_rn_rm(rt,rs,0)|armval);
2775 emit_movimm(rt_val,rt);
2778 // return 1 if above function can do it's job cheaply
2779 static int is_similar_value(u_int v1,u_int v2)
2783 if(v1==v2) return 1;
2785 for(xs=diff;xs!=0&&(xs&3)==0;xs>>=2)
2787 if(xs<0x100) return 1;
2788 for(xs=-diff;xs!=0&&(xs&3)==0;xs>>=2)
2790 if(xs<0x100) return 1;
2795 static void pass_args(int a0, int a1)
2799 emit_mov(a0,2); emit_mov(a1,1); emit_mov(2,0);
2801 else if(a0!=0&&a1==0) {
2803 if (a0>=0) emit_mov(a0,0);
2806 if(a0>=0&&a0!=0) emit_mov(a0,0);
2807 if(a1>=0&&a1!=1) emit_mov(a1,1);
2811 static void mov_loadtype_adj(int type,int rs,int rt)
2814 case LOADB_STUB: emit_signextend8(rs,rt); break;
2815 case LOADBU_STUB: emit_andimm(rs,0xff,rt); break;
2816 case LOADH_STUB: emit_signextend16(rs,rt); break;
2817 case LOADHU_STUB: emit_andimm(rs,0xffff,rt); break;
2818 case LOADW_STUB: if(rs!=rt) emit_mov(rs,rt); break;
2824 #include "pcsxmem.h"
2825 #include "pcsxmem_inline.c"
2830 assem_debug("do_readstub %x\n",start+stubs[n][3]*4);
2832 set_jump_target(stubs[n][1],(int)out);
2833 int type=stubs[n][0];
2836 struct regstat *i_regs=(struct regstat *)stubs[n][5];
2837 u_int reglist=stubs[n][7];
2838 signed char *i_regmap=i_regs->regmap;
2839 int addr=get_reg(i_regmap,AGEN1+(i&1));
2842 if(itype[i]==C1LS||itype[i]==C2LS||itype[i]==LOADLR) {
2843 rth=get_reg(i_regmap,FTEMP|64);
2844 rt=get_reg(i_regmap,FTEMP);
2846 rth=get_reg(i_regmap,rt1[i]|64);
2847 rt=get_reg(i_regmap,rt1[i]);
2851 int r,temp=-1,temp2=HOST_TEMPREG,regs_saved=0,restore_jump=0;
2853 for(r=0;r<=12;r++) {
2854 if(((1<<r)&0x13ff)&&((1<<r)®list)==0) {
2858 if(rt>=0&&rt1[i]!=0)
2865 if((regs_saved||(reglist&2)==0)&&temp!=1&&rs!=1)
2867 emit_readword((int)&mem_rtab,temp);
2868 emit_shrimm(rs,12,temp2);
2869 emit_readword_dualindexedx4(temp,temp2,temp2);
2870 emit_lsls_imm(temp2,1,temp2);
2871 if(itype[i]==C1LS||itype[i]==C2LS||(rt>=0&&rt1[i]!=0)) {
2873 case LOADB_STUB: emit_ldrccsb_dualindexed(temp2,rs,rt); break;
2874 case LOADBU_STUB: emit_ldrccb_dualindexed(temp2,rs,rt); break;
2875 case LOADH_STUB: emit_ldrccsh_dualindexed(temp2,rs,rt); break;
2876 case LOADHU_STUB: emit_ldrcch_dualindexed(temp2,rs,rt); break;
2877 case LOADW_STUB: emit_ldrcc_dualindexed(temp2,rs,rt); break;
2881 restore_jump=(int)out;
2882 emit_jcc(0); // jump to reg restore
2885 emit_jcc(stubs[n][2]); // return address
2890 if(type==LOADB_STUB||type==LOADBU_STUB)
2891 handler=(int)jump_handler_read8;
2892 if(type==LOADH_STUB||type==LOADHU_STUB)
2893 handler=(int)jump_handler_read16;
2894 if(type==LOADW_STUB)
2895 handler=(int)jump_handler_read32;
2897 pass_args(rs,temp2);
2898 int cc=get_reg(i_regmap,CCREG);
2900 emit_loadreg(CCREG,2);
2901 emit_addimm(cc<0?2:cc,CLOCK_ADJUST((int)stubs[n][6]+1),2);
2903 if(itype[i]==C1LS||itype[i]==C2LS||(rt>=0&&rt1[i]!=0)) {
2904 mov_loadtype_adj(type,0,rt);
2907 set_jump_target(restore_jump,(int)out);
2908 restore_regs(reglist);
2909 emit_jmp(stubs[n][2]); // return address
2912 if(addr<0&&itype[i]!=C1LS&&itype[i]!=C2LS&&itype[i]!=LOADLR) addr=get_reg(i_regmap,-1);
2915 if(type==LOADB_STUB||type==LOADBU_STUB)
2916 ftable=(int)readmemb;
2917 if(type==LOADH_STUB||type==LOADHU_STUB)
2918 ftable=(int)readmemh;
2919 if(type==LOADW_STUB)
2920 ftable=(int)readmem;
2922 if(type==LOADD_STUB)
2923 ftable=(int)readmemd;
2926 emit_writeword(rs,(int)&address);
2930 ds=i_regs!=®s[i];
2931 int real_rs=(itype[i]==LOADLR)?-1:get_reg(i_regmap,rs1[i]);
2932 u_int cmask=ds?-1:(0x100f|~i_regs->wasconst);
2933 if(!ds) load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&0x100f,i);
2934 wb_dirtys(i_regs->regmap_entry,i_regs->was32,i_regs->wasdirty&cmask&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs)));
2935 if(!ds) wb_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&~0x100f,i);
2937 emit_shrimm(rs,16,1);
2938 int cc=get_reg(i_regmap,CCREG);
2940 emit_loadreg(CCREG,2);
2942 emit_movimm(ftable,0);
2943 emit_addimm(cc<0?2:cc,2*stubs[n][6]+2,2);
2945 emit_movimm(start+stubs[n][3]*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3);
2947 //emit_readword((int)&last_count,temp);
2948 //emit_add(cc,temp,cc);
2949 //emit_writeword(cc,(int)&Count);
2951 emit_call((int)&indirect_jump_indexed);
2953 //emit_readword_dualindexedx4(rs,HOST_TEMPREG,15);
2955 // We really shouldn't need to update the count here,
2956 // but not doing so causes random crashes...
2957 emit_readword((int)&Count,HOST_TEMPREG);
2958 emit_readword((int)&next_interupt,2);
2959 emit_addimm(HOST_TEMPREG,-2*stubs[n][6]-2,HOST_TEMPREG);
2960 emit_writeword(2,(int)&last_count);
2961 emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
2963 emit_storereg(CCREG,HOST_TEMPREG);
2967 restore_regs(reglist);
2968 //if((cc=get_reg(regmap,CCREG))>=0) {
2969 // emit_loadreg(CCREG,cc);
2971 if(itype[i]==C1LS||itype[i]==C2LS||(rt>=0&&rt1[i]!=0)) {
2973 if(type==LOADB_STUB)
2974 emit_movsbl((int)&readmem_dword,rt);
2975 if(type==LOADBU_STUB)
2976 emit_movzbl((int)&readmem_dword,rt);
2977 if(type==LOADH_STUB)
2978 emit_movswl((int)&readmem_dword,rt);
2979 if(type==LOADHU_STUB)
2980 emit_movzwl((int)&readmem_dword,rt);
2981 if(type==LOADW_STUB)
2982 emit_readword((int)&readmem_dword,rt);
2983 if(type==LOADD_STUB) {
2984 emit_readword((int)&readmem_dword,rt);
2985 if(rth>=0) emit_readword(((int)&readmem_dword)+4,rth);
2988 emit_jmp(stubs[n][2]); // return address
2993 // return memhandler, or get directly accessable address and return 0
2994 u_int get_direct_memhandler(void *table,u_int addr,int type,u_int *addr_host)
2997 l1=((u_int *)table)[addr>>12];
2998 if((l1&(1<<31))==0) {
3005 if(type==LOADB_STUB||type==LOADBU_STUB||type==STOREB_STUB)
3006 l2=((u_int *)l1)[0x1000/4 + 0x1000/2 + (addr&0xfff)];
3007 else if(type==LOADH_STUB||type==LOADHU_STUB||type==STOREH_STUB)
3008 l2=((u_int *)l1)[0x1000/4 + (addr&0xfff)/2];
3010 l2=((u_int *)l1)[(addr&0xfff)/4];
3011 if((l2&(1<<31))==0) {
3013 *addr_host=v+(addr&0xfff);
3021 inline_readstub(int type, int i, u_int addr, signed char regmap[], int target, int adj, u_int reglist)
3023 int rs=get_reg(regmap,target);
3024 int rth=get_reg(regmap,target|64);
3025 int rt=get_reg(regmap,target);
3026 if(rs<0) rs=get_reg(regmap,-1);
3029 u_int handler,host_addr=0,is_dynamic,far_call=0;
3030 int cc=get_reg(regmap,CCREG);
3031 if(pcsx_direct_read(type,addr,CLOCK_ADJUST(adj+1),cc,target?rs:-1,rt))
3033 handler=get_direct_memhandler(mem_rtab,addr,type,&host_addr);
3038 emit_movimm_from(addr,rs,host_addr,rs);
3040 case LOADB_STUB: emit_movsbl_indexed(0,rs,rt); break;
3041 case LOADBU_STUB: emit_movzbl_indexed(0,rs,rt); break;
3042 case LOADH_STUB: emit_movswl_indexed(0,rs,rt); break;
3043 case LOADHU_STUB: emit_movzwl_indexed(0,rs,rt); break;
3044 case LOADW_STUB: emit_readword_indexed(0,rs,rt); break;
3049 is_dynamic=pcsxmem_is_handler_dynamic(addr);
3051 if(type==LOADB_STUB||type==LOADBU_STUB)
3052 handler=(int)jump_handler_read8;
3053 if(type==LOADH_STUB||type==LOADHU_STUB)
3054 handler=(int)jump_handler_read16;
3055 if(type==LOADW_STUB)
3056 handler=(int)jump_handler_read32;
3059 // call a memhandler
3060 if(rt>=0&&rt1[i]!=0)
3064 emit_movimm(addr,0);
3067 int offset=(int)handler-(int)out-8;
3068 if(offset<-33554432||offset>=33554432) {
3069 // unreachable memhandler, a plugin func perhaps
3070 emit_movimm(handler,12);
3074 emit_loadreg(CCREG,2);
3076 emit_movimm(((u_int *)mem_rtab)[addr>>12]<<1,1);
3077 emit_addimm(cc<0?2:cc,CLOCK_ADJUST(adj+1),2);
3080 emit_readword((int)&last_count,3);
3081 emit_addimm(cc<0?2:cc,CLOCK_ADJUST(adj+1),2);
3083 emit_writeword(2,(int)&Count);
3091 if(rt>=0&&rt1[i]!=0) {
3093 case LOADB_STUB: emit_signextend8(0,rt); break;
3094 case LOADBU_STUB: emit_andimm(0,0xff,rt); break;
3095 case LOADH_STUB: emit_signextend16(0,rt); break;
3096 case LOADHU_STUB: emit_andimm(0,0xffff,rt); break;
3097 case LOADW_STUB: if(rt!=0) emit_mov(0,rt); break;
3101 restore_regs(reglist);
3104 if(type==LOADB_STUB||type==LOADBU_STUB)
3105 ftable=(int)readmemb;
3106 if(type==LOADH_STUB||type==LOADHU_STUB)
3107 ftable=(int)readmemh;
3108 if(type==LOADW_STUB)
3109 ftable=(int)readmem;
3111 if(type==LOADD_STUB)
3112 ftable=(int)readmemd;
3116 emit_movimm(addr,rs);
3117 emit_writeword(rs,(int)&address);
3121 if((signed int)addr>=(signed int)0xC0000000) {
3122 // Theoretically we can have a pagefault here, if the TLB has never
3123 // been enabled and the address is outside the range 80000000..BFFFFFFF
3124 // Write out the registers so the pagefault can be handled. This is
3125 // a very rare case and likely represents a bug.
3126 int ds=regmap!=regs[i].regmap;
3127 if(!ds) load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty,i);
3128 if(!ds) wb_dirtys(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty);
3129 else wb_dirtys(branch_regs[i-1].regmap_entry,branch_regs[i-1].was32,branch_regs[i-1].wasdirty);
3132 //emit_shrimm(rs,16,1);
3133 int cc=get_reg(regmap,CCREG);
3135 emit_loadreg(CCREG,2);
3137 //emit_movimm(ftable,0);
3138 emit_movimm(((u_int *)ftable)[addr>>16],0);
3139 //emit_readword((int)&last_count,12);
3140 emit_addimm(cc<0?2:cc,CLOCK_ADJUST(adj+1),2);
3142 if((signed int)addr>=(signed int)0xC0000000) {
3143 // Pagefault address
3144 int ds=regmap!=regs[i].regmap;
3145 emit_movimm(start+i*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3);
3149 //emit_writeword(2,(int)&Count);
3150 //emit_call(((u_int *)ftable)[addr>>16]);
3151 emit_call((int)&indirect_jump);
3153 // We really shouldn't need to update the count here,
3154 // but not doing so causes random crashes...
3155 emit_readword((int)&Count,HOST_TEMPREG);
3156 emit_readword((int)&next_interupt,2);
3157 emit_addimm(HOST_TEMPREG,-CLOCK_ADJUST(adj+1),HOST_TEMPREG);
3158 emit_writeword(2,(int)&last_count);
3159 emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
3161 emit_storereg(CCREG,HOST_TEMPREG);
3165 restore_regs(reglist);
3167 if(type==LOADB_STUB)
3168 emit_movsbl((int)&readmem_dword,rt);
3169 if(type==LOADBU_STUB)
3170 emit_movzbl((int)&readmem_dword,rt);
3171 if(type==LOADH_STUB)
3172 emit_movswl((int)&readmem_dword,rt);
3173 if(type==LOADHU_STUB)
3174 emit_movzwl((int)&readmem_dword,rt);
3175 if(type==LOADW_STUB)
3176 emit_readword((int)&readmem_dword,rt);
3177 if(type==LOADD_STUB) {
3178 emit_readword((int)&readmem_dword,rt);
3179 if(rth>=0) emit_readword(((int)&readmem_dword)+4,rth);
3187 assem_debug("do_writestub %x\n",start+stubs[n][3]*4);
3189 set_jump_target(stubs[n][1],(int)out);
3190 int type=stubs[n][0];
3193 struct regstat *i_regs=(struct regstat *)stubs[n][5];
3194 u_int reglist=stubs[n][7];
3195 signed char *i_regmap=i_regs->regmap;
3196 int addr=get_reg(i_regmap,AGEN1+(i&1));
3199 if(itype[i]==C1LS||itype[i]==C2LS) {
3200 rth=get_reg(i_regmap,FTEMP|64);
3201 rt=get_reg(i_regmap,r=FTEMP);
3203 rth=get_reg(i_regmap,rs2[i]|64);
3204 rt=get_reg(i_regmap,r=rs2[i]);
3209 int rtmp,temp=-1,temp2=HOST_TEMPREG,regs_saved=0,restore_jump=0,ra;
3210 int reglist2=reglist|(1<<rs)|(1<<rt);
3211 for(rtmp=0;rtmp<=12;rtmp++) {
3212 if(((1<<rtmp)&0x13ff)&&((1<<rtmp)®list2)==0) {
3219 for(rtmp=0;rtmp<=3;rtmp++)
3220 if(rtmp!=rs&&rtmp!=rt)
3223 if((regs_saved||(reglist2&8)==0)&&temp!=3&&rs!=3&&rt!=3)
3225 emit_readword((int)&mem_wtab,temp);
3226 emit_shrimm(rs,12,temp2);
3227 emit_readword_dualindexedx4(temp,temp2,temp2);
3228 emit_lsls_imm(temp2,1,temp2);
3230 case STOREB_STUB: emit_strccb_dualindexed(temp2,rs,rt); break;
3231 case STOREH_STUB: emit_strcch_dualindexed(temp2,rs,rt); break;
3232 case STOREW_STUB: emit_strcc_dualindexed(temp2,rs,rt); break;
3236 restore_jump=(int)out;
3237 emit_jcc(0); // jump to reg restore
3240 emit_jcc(stubs[n][2]); // return address (invcode check)
3246 case STOREB_STUB: handler=(int)jump_handler_write8; break;
3247 case STOREH_STUB: handler=(int)jump_handler_write16; break;
3248 case STOREW_STUB: handler=(int)jump_handler_write32; break;
3254 int cc=get_reg(i_regmap,CCREG);
3256 emit_loadreg(CCREG,2);
3257 emit_addimm(cc<0?2:cc,CLOCK_ADJUST((int)stubs[n][6]+1),2);
3258 // returns new cycle_count
3260 emit_addimm(0,-CLOCK_ADJUST((int)stubs[n][6]+1),cc<0?2:cc);
3262 emit_storereg(CCREG,2);
3264 set_jump_target(restore_jump,(int)out);
3265 restore_regs(reglist);
3269 if(addr<0) addr=get_reg(i_regmap,-1);
3272 if(type==STOREB_STUB)
3273 ftable=(int)writememb;
3274 if(type==STOREH_STUB)
3275 ftable=(int)writememh;
3276 if(type==STOREW_STUB)
3277 ftable=(int)writemem;
3279 if(type==STORED_STUB)
3280 ftable=(int)writememd;
3283 emit_writeword(rs,(int)&address);
3284 //emit_shrimm(rs,16,rs);
3285 //emit_movmem_indexedx4(ftable,rs,rs);
3286 if(type==STOREB_STUB)
3287 emit_writebyte(rt,(int)&byte);
3288 if(type==STOREH_STUB)
3289 emit_writehword(rt,(int)&hword);
3290 if(type==STOREW_STUB)
3291 emit_writeword(rt,(int)&word);
3292 if(type==STORED_STUB) {
3294 emit_writeword(rt,(int)&dword);
3295 emit_writeword(r?rth:rt,(int)&dword+4);
3297 SysPrintf("STORED_STUB\n");
3303 ds=i_regs!=®s[i];
3304 int real_rs=get_reg(i_regmap,rs1[i]);
3305 u_int cmask=ds?-1:(0x100f|~i_regs->wasconst);
3306 if(!ds) load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&0x100f,i);
3307 wb_dirtys(i_regs->regmap_entry,i_regs->was32,i_regs->wasdirty&cmask&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs)));
3308 if(!ds) wb_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&~0x100f,i);
3310 emit_shrimm(rs,16,1);
3311 int cc=get_reg(i_regmap,CCREG);
3313 emit_loadreg(CCREG,2);
3315 emit_movimm(ftable,0);
3316 emit_addimm(cc<0?2:cc,2*stubs[n][6]+2,2);
3318 emit_movimm(start+stubs[n][3]*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3);
3320 //emit_readword((int)&last_count,temp);
3321 //emit_addimm(cc,2*stubs[n][5]+2,cc);
3322 //emit_add(cc,temp,cc);
3323 //emit_writeword(cc,(int)&Count);
3324 emit_call((int)&indirect_jump_indexed);
3326 emit_readword((int)&Count,HOST_TEMPREG);
3327 emit_readword((int)&next_interupt,2);
3328 emit_addimm(HOST_TEMPREG,-2*stubs[n][6]-2,HOST_TEMPREG);
3329 emit_writeword(2,(int)&last_count);
3330 emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
3332 emit_storereg(CCREG,HOST_TEMPREG);
3335 restore_regs(reglist);
3336 //if((cc=get_reg(regmap,CCREG))>=0) {
3337 // emit_loadreg(CCREG,cc);
3339 emit_jmp(stubs[n][2]); // return address
3343 inline_writestub(int type, int i, u_int addr, signed char regmap[], int target, int adj, u_int reglist)
3345 int rs=get_reg(regmap,-1);
3346 int rth=get_reg(regmap,target|64);
3347 int rt=get_reg(regmap,target);
3351 u_int handler,host_addr=0;
3352 handler=get_direct_memhandler(mem_wtab,addr,type,&host_addr);
3355 emit_movimm_from(addr,rs,host_addr,rs);
3357 case STOREB_STUB: emit_writebyte_indexed(rt,0,rs); break;
3358 case STOREH_STUB: emit_writehword_indexed(rt,0,rs); break;
3359 case STOREW_STUB: emit_writeword_indexed(rt,0,rs); break;
3365 // call a memhandler
3368 int cc=get_reg(regmap,CCREG);
3370 emit_loadreg(CCREG,2);
3371 emit_addimm(cc<0?2:cc,CLOCK_ADJUST(adj+1),2);
3372 emit_movimm(handler,3);
3373 // returns new cycle_count
3374 emit_call((int)jump_handler_write_h);
3375 emit_addimm(0,-CLOCK_ADJUST(adj+1),cc<0?2:cc);
3377 emit_storereg(CCREG,2);
3378 restore_regs(reglist);
3381 if(type==STOREB_STUB)
3382 ftable=(int)writememb;
3383 if(type==STOREH_STUB)
3384 ftable=(int)writememh;
3385 if(type==STOREW_STUB)
3386 ftable=(int)writemem;
3388 if(type==STORED_STUB)
3389 ftable=(int)writememd;
3392 emit_writeword(rs,(int)&address);
3393 //emit_shrimm(rs,16,rs);
3394 //emit_movmem_indexedx4(ftable,rs,rs);
3395 if(type==STOREB_STUB)
3396 emit_writebyte(rt,(int)&byte);
3397 if(type==STOREH_STUB)
3398 emit_writehword(rt,(int)&hword);
3399 if(type==STOREW_STUB)
3400 emit_writeword(rt,(int)&word);
3401 if(type==STORED_STUB) {
3403 emit_writeword(rt,(int)&dword);
3404 emit_writeword(target?rth:rt,(int)&dword+4);
3406 SysPrintf("STORED_STUB\n");
3412 // rearmed note: load_all_consts prevents BIOS boot, some bug?
3413 if((signed int)addr>=(signed int)0xC0000000) {
3414 // Theoretically we can have a pagefault here, if the TLB has never
3415 // been enabled and the address is outside the range 80000000..BFFFFFFF
3416 // Write out the registers so the pagefault can be handled. This is
3417 // a very rare case and likely represents a bug.
3418 int ds=regmap!=regs[i].regmap;
3419 if(!ds) load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty,i);
3420 if(!ds) wb_dirtys(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty);
3421 else wb_dirtys(branch_regs[i-1].regmap_entry,branch_regs[i-1].was32,branch_regs[i-1].wasdirty);
3424 //emit_shrimm(rs,16,1);
3425 int cc=get_reg(regmap,CCREG);
3427 emit_loadreg(CCREG,2);
3429 //emit_movimm(ftable,0);
3430 emit_movimm(((u_int *)ftable)[addr>>16],0);
3431 //emit_readword((int)&last_count,12);
3432 emit_addimm(cc<0?2:cc,CLOCK_ADJUST(adj+1),2);
3434 if((signed int)addr>=(signed int)0xC0000000) {
3435 // Pagefault address
3436 int ds=regmap!=regs[i].regmap;
3437 emit_movimm(start+i*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3);
3441 //emit_writeword(2,(int)&Count);
3442 //emit_call(((u_int *)ftable)[addr>>16]);
3443 emit_call((int)&indirect_jump);
3444 emit_readword((int)&Count,HOST_TEMPREG);
3445 emit_readword((int)&next_interupt,2);
3446 emit_addimm(HOST_TEMPREG,-CLOCK_ADJUST(adj+1),HOST_TEMPREG);
3447 emit_writeword(2,(int)&last_count);
3448 emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
3450 emit_storereg(CCREG,HOST_TEMPREG);
3453 restore_regs(reglist);
3457 do_unalignedwritestub(int n)
3459 assem_debug("do_unalignedwritestub %x\n",start+stubs[n][3]*4);
3461 set_jump_target(stubs[n][1],(int)out);
3464 struct regstat *i_regs=(struct regstat *)stubs[n][4];
3465 int addr=stubs[n][5];
3466 u_int reglist=stubs[n][7];
3467 signed char *i_regmap=i_regs->regmap;
3468 int temp2=get_reg(i_regmap,FTEMP);
3471 rt=get_reg(i_regmap,rs2[i]);
3474 assert(opcode[i]==0x2a||opcode[i]==0x2e); // SWL/SWR only implemented
3476 reglist&=~(1<<temp2);
3479 // don't bother with it and call write handler
3482 int cc=get_reg(i_regmap,CCREG);
3484 emit_loadreg(CCREG,2);
3485 emit_addimm(cc<0?2:cc,CLOCK_ADJUST((int)stubs[n][6]+1),2);
3486 emit_call((int)(opcode[i]==0x2a?jump_handle_swl:jump_handle_swr));
3487 emit_addimm(0,-CLOCK_ADJUST((int)stubs[n][6]+1),cc<0?2:cc);
3489 emit_storereg(CCREG,2);
3490 restore_regs(reglist);
3491 emit_jmp(stubs[n][2]); // return address
3493 emit_andimm(addr,0xfffffffc,temp2);
3494 emit_writeword(temp2,(int)&address);
3498 ds=i_regs!=®s[i];
3499 real_rs=get_reg(i_regmap,rs1[i]);
3500 u_int cmask=ds?-1:(0x100f|~i_regs->wasconst);
3501 if(!ds) load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&0x100f,i);
3502 wb_dirtys(i_regs->regmap_entry,i_regs->was32,i_regs->wasdirty&cmask&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs)));
3503 if(!ds) wb_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&~0x100f,i);
3505 emit_shrimm(addr,16,1);
3506 int cc=get_reg(i_regmap,CCREG);
3508 emit_loadreg(CCREG,2);
3510 emit_movimm((u_int)readmem,0);
3511 emit_addimm(cc<0?2:cc,2*stubs[n][6]+2,2);
3513 // pagefault address
3514 emit_movimm(start+stubs[n][3]*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3);
3516 emit_call((int)&indirect_jump_indexed);
3517 restore_regs(reglist);
3519 emit_readword((int)&readmem_dword,temp2);
3520 int temp=addr; //hmh
3521 emit_shlimm(addr,3,temp);
3522 emit_andimm(temp,24,temp);
3523 #ifdef BIG_ENDIAN_MIPS
3524 if (opcode[i]==0x2e) // SWR
3526 if (opcode[i]==0x2a) // SWL
3528 emit_xorimm(temp,24,temp);
3529 emit_movimm(-1,HOST_TEMPREG);
3530 if (opcode[i]==0x2a) { // SWL
3531 emit_bic_lsr(temp2,HOST_TEMPREG,temp,temp2);
3532 emit_orrshr(rt,temp,temp2);
3534 emit_bic_lsl(temp2,HOST_TEMPREG,temp,temp2);
3535 emit_orrshl(rt,temp,temp2);
3537 emit_readword((int)&address,addr);
3538 emit_writeword(temp2,(int)&word);
3539 //save_regs(reglist); // don't need to, no state changes
3540 emit_shrimm(addr,16,1);
3541 emit_movimm((u_int)writemem,0);
3542 //emit_call((int)&indirect_jump_indexed);
3544 emit_readword_dualindexedx4(0,1,15);
3545 emit_readword((int)&Count,HOST_TEMPREG);
3546 emit_readword((int)&next_interupt,2);
3547 emit_addimm(HOST_TEMPREG,-2*stubs[n][6]-2,HOST_TEMPREG);
3548 emit_writeword(2,(int)&last_count);
3549 emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
3551 emit_storereg(CCREG,HOST_TEMPREG);
3553 restore_regs(reglist);
3554 emit_jmp(stubs[n][2]); // return address
3558 void printregs(int edi,int esi,int ebp,int esp,int b,int d,int c,int a)
3560 printf("regs: %x %x %x %x %x %x %x (%x)\n",a,b,c,d,ebp,esi,edi,(&edi)[-1]);
3566 u_int reglist=stubs[n][3];
3567 set_jump_target(stubs[n][1],(int)out);
3569 if(stubs[n][4]!=0) emit_mov(stubs[n][4],0);
3570 emit_call((int)&invalidate_addr);
3571 restore_regs(reglist);
3572 emit_jmp(stubs[n][2]); // return address
3575 int do_dirty_stub(int i)
3577 assem_debug("do_dirty_stub %x\n",start+i*4);
3578 u_int addr=(int)start<(int)0xC0000000?(u_int)source:(u_int)start;
3582 // Careful about the code output here, verify_dirty needs to parse it.
3584 emit_loadlp(addr,1);
3585 emit_loadlp((int)copy,2);
3586 emit_loadlp(slen*4,3);
3588 emit_movw(addr&0x0000FFFF,1);
3589 emit_movw(((u_int)copy)&0x0000FFFF,2);
3590 emit_movt(addr&0xFFFF0000,1);
3591 emit_movt(((u_int)copy)&0xFFFF0000,2);
3592 emit_movw(slen*4,3);
3594 emit_movimm(start+i*4,0);
3595 emit_call((int)start<(int)0xC0000000?(int)&verify_code:(int)&verify_code_vm);
3598 if(entry==(int)out) entry=instr_addr[i];
3599 emit_jmp(instr_addr[i]);
3603 void do_dirty_stub_ds()
3605 // Careful about the code output here, verify_dirty needs to parse it.
3607 emit_loadlp((int)start<(int)0xC0000000?(int)source:(int)start,1);
3608 emit_loadlp((int)copy,2);
3609 emit_loadlp(slen*4,3);
3611 emit_movw(((int)start<(int)0xC0000000?(u_int)source:(u_int)start)&0x0000FFFF,1);
3612 emit_movw(((u_int)copy)&0x0000FFFF,2);
3613 emit_movt(((int)start<(int)0xC0000000?(u_int)source:(u_int)start)&0xFFFF0000,1);
3614 emit_movt(((u_int)copy)&0xFFFF0000,2);
3615 emit_movw(slen*4,3);
3617 emit_movimm(start+1,0);
3618 emit_call((int)&verify_code_ds);
3624 assem_debug("do_cop1stub %x\n",start+stubs[n][3]*4);
3625 set_jump_target(stubs[n][1],(int)out);
3627 // int rs=stubs[n][4];
3628 struct regstat *i_regs=(struct regstat *)stubs[n][5];
3631 load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty,i);
3632 //if(i_regs!=®s[i]) printf("oops: regs[i]=%x i_regs=%x",(int)®s[i],(int)i_regs);
3634 //else {printf("fp exception in delay slot\n");}
3635 wb_dirtys(i_regs->regmap_entry,i_regs->was32,i_regs->wasdirty);
3636 if(regs[i].regmap_entry[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
3637 emit_movimm(start+(i-ds)*4,EAX); // Get PC
3638 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
3639 emit_jmp(ds?(int)fp_exception_ds:(int)fp_exception);
3646 int do_tlb_r(int s,int ar,int map,int x,int a,int shift,int c,u_int addr)
3649 if((signed int)addr>=(signed int)0xC0000000) {
3650 // address_generation already loaded the const
3651 emit_readword_dualindexedx4(FP,map,map);
3654 return -1; // No mapping
3658 emit_movimm(((int)memory_map-(int)&dynarec_local)>>2,map);
3659 emit_addsr12(map,s,map);
3660 // Schedule this while we wait on the load
3661 //if(x) emit_xorimm(s,x,ar);
3662 if(shift>=0) emit_shlimm(s,3,shift);
3663 if(~a) emit_andimm(s,a,ar);
3664 emit_readword_dualindexedx4(FP,map,map);
3668 int do_tlb_r_branch(int map, int c, u_int addr, int *jaddr)
3670 if(!c||(signed int)addr>=(signed int)0xC0000000) {
3678 int gen_tlb_addr_r(int ar, int map) {
3680 assem_debug("add %s,%s,%s lsl #2\n",regname[ar],regname[ar],regname[map]);
3681 output_w32(0xe0800100|rd_rn_rm(ar,ar,map));
3685 int do_tlb_w(int s,int ar,int map,int x,int c,u_int addr)
3688 if(addr<0x80800000||addr>=0xC0000000) {
3689 // address_generation already loaded the const
3690 emit_readword_dualindexedx4(FP,map,map);
3693 return -1; // No mapping
3697 emit_movimm(((int)memory_map-(int)&dynarec_local)>>2,map);
3698 emit_addsr12(map,s,map);
3699 // Schedule this while we wait on the load
3700 //if(x) emit_xorimm(s,x,ar);
3701 emit_readword_dualindexedx4(FP,map,map);
3705 int do_tlb_w_branch(int map, int c, u_int addr, int *jaddr)
3707 if(!c||addr<0x80800000||addr>=0xC0000000) {
3708 emit_testimm(map,0x40000000);
3714 int gen_tlb_addr_w(int ar, int map) {
3716 assem_debug("add %s,%s,%s lsl #2\n",regname[ar],regname[ar],regname[map]);
3717 output_w32(0xe0800100|rd_rn_rm(ar,ar,map));
3721 // Generate the address of the memory_map entry, relative to dynarec_local
3722 generate_map_const(u_int addr,int reg) {
3723 //printf("generate_map_const(%x,%s)\n",addr,regname[reg]);
3724 emit_movimm((addr>>12)+(((u_int)memory_map-(u_int)&dynarec_local)>>2),reg);
3729 static int do_tlb_r(int a, ...) { return 0; }
3730 static int do_tlb_r_branch(int a, ...) { return 0; }
3731 static int gen_tlb_addr_r(int a, ...) { return 0; }
3732 static int do_tlb_w(int a, ...) { return 0; }
3733 static int do_tlb_w_branch(int a, ...) { return 0; }
3734 static int gen_tlb_addr_w(int a, ...) { return 0; }
3736 #endif // DISABLE_TLB
3740 void shift_assemble_arm(int i,struct regstat *i_regs)
3743 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
3745 signed char s,t,shift;
3746 t=get_reg(i_regs->regmap,rt1[i]);
3747 s=get_reg(i_regs->regmap,rs1[i]);
3748 shift=get_reg(i_regs->regmap,rs2[i]);
3757 if(s!=t) emit_mov(s,t);
3761 emit_andimm(shift,31,HOST_TEMPREG);
3762 if(opcode2[i]==4) // SLLV
3764 emit_shl(s,HOST_TEMPREG,t);
3766 if(opcode2[i]==6) // SRLV
3768 emit_shr(s,HOST_TEMPREG,t);
3770 if(opcode2[i]==7) // SRAV
3772 emit_sar(s,HOST_TEMPREG,t);
3776 } else { // DSLLV/DSRLV/DSRAV
3777 signed char sh,sl,th,tl,shift;
3778 th=get_reg(i_regs->regmap,rt1[i]|64);
3779 tl=get_reg(i_regs->regmap,rt1[i]);
3780 sh=get_reg(i_regs->regmap,rs1[i]|64);
3781 sl=get_reg(i_regs->regmap,rs1[i]);
3782 shift=get_reg(i_regs->regmap,rs2[i]);
3787 if(th>=0) emit_zeroreg(th);
3792 if(sl!=tl) emit_mov(sl,tl);
3793 if(th>=0&&sh!=th) emit_mov(sh,th);
3797 // FIXME: What if shift==tl ?
3799 int temp=get_reg(i_regs->regmap,-1);
3801 if(th<0&&opcode2[i]!=0x14) {th=temp;} // DSLLV doesn't need a temporary register
3804 emit_andimm(shift,31,HOST_TEMPREG);
3805 if(opcode2[i]==0x14) // DSLLV
3807 if(th>=0) emit_shl(sh,HOST_TEMPREG,th);
3808 emit_rsbimm(HOST_TEMPREG,32,HOST_TEMPREG);
3809 emit_orrshr(sl,HOST_TEMPREG,th);
3810 emit_andimm(shift,31,HOST_TEMPREG);
3811 emit_testimm(shift,32);
3812 emit_shl(sl,HOST_TEMPREG,tl);
3813 if(th>=0) emit_cmovne_reg(tl,th);
3814 emit_cmovne_imm(0,tl);
3816 if(opcode2[i]==0x16) // DSRLV
3819 emit_shr(sl,HOST_TEMPREG,tl);
3820 emit_rsbimm(HOST_TEMPREG,32,HOST_TEMPREG);
3821 emit_orrshl(sh,HOST_TEMPREG,tl);
3822 emit_andimm(shift,31,HOST_TEMPREG);
3823 emit_testimm(shift,32);
3824 emit_shr(sh,HOST_TEMPREG,th);
3825 emit_cmovne_reg(th,tl);
3826 if(real_th>=0) emit_cmovne_imm(0,th);
3828 if(opcode2[i]==0x17) // DSRAV
3831 emit_shr(sl,HOST_TEMPREG,tl);
3832 emit_rsbimm(HOST_TEMPREG,32,HOST_TEMPREG);
3835 emit_sarimm(th,31,temp);
3837 emit_orrshl(sh,HOST_TEMPREG,tl);
3838 emit_andimm(shift,31,HOST_TEMPREG);
3839 emit_testimm(shift,32);
3840 emit_sar(sh,HOST_TEMPREG,th);
3841 emit_cmovne_reg(th,tl);
3842 if(real_th>=0) emit_cmovne_reg(temp,th);
3851 static void speculate_mov(int rs,int rt)
3854 smrv_strong_next|=1<<rt;
3859 static void speculate_mov_weak(int rs,int rt)
3862 smrv_weak_next|=1<<rt;
3867 static void speculate_register_values(int i)
3870 memcpy(smrv,psxRegs.GPR.r,sizeof(smrv));
3871 // gp,sp are likely to stay the same throughout the block
3872 smrv_strong_next=(1<<28)|(1<<29)|(1<<30);
3873 smrv_weak_next=~smrv_strong_next;
3874 //printf(" llr %08x\n", smrv[4]);
3876 smrv_strong=smrv_strong_next;
3877 smrv_weak=smrv_weak_next;
3880 if ((smrv_strong>>rs1[i])&1) speculate_mov(rs1[i],rt1[i]);
3881 else if((smrv_strong>>rs2[i])&1) speculate_mov(rs2[i],rt1[i]);
3882 else if((smrv_weak>>rs1[i])&1) speculate_mov_weak(rs1[i],rt1[i]);
3883 else if((smrv_weak>>rs2[i])&1) speculate_mov_weak(rs2[i],rt1[i]);
3885 smrv_strong_next&=~(1<<rt1[i]);
3886 smrv_weak_next&=~(1<<rt1[i]);
3890 smrv_strong_next&=~(1<<rt1[i]);
3891 smrv_weak_next&=~(1<<rt1[i]);
3894 if(rt1[i]&&is_const(®s[i],rt1[i])) {
3895 int value,hr=get_reg(regs[i].regmap,rt1[i]);
3897 if(get_final_value(hr,i,&value))
3899 else smrv[rt1[i]]=constmap[i][hr];
3900 smrv_strong_next|=1<<rt1[i];
3904 if ((smrv_strong>>rs1[i])&1) speculate_mov(rs1[i],rt1[i]);
3905 else if((smrv_weak>>rs1[i])&1) speculate_mov_weak(rs1[i],rt1[i]);
3909 if(start<0x2000&&(rt1[i]==26||(smrv[rt1[i]]>>24)==0xa0)) {
3910 // special case for BIOS
3911 smrv[rt1[i]]=0xa0000000;
3912 smrv_strong_next|=1<<rt1[i];
3919 smrv_strong_next&=~(1<<rt1[i]);
3920 smrv_weak_next&=~(1<<rt1[i]);
3924 if(opcode2[i]==0||opcode2[i]==2) { // MFC/CFC
3925 smrv_strong_next&=~(1<<rt1[i]);
3926 smrv_weak_next&=~(1<<rt1[i]);
3930 if (opcode[i]==0x32) { // LWC2
3931 smrv_strong_next&=~(1<<rt1[i]);
3932 smrv_weak_next&=~(1<<rt1[i]);
3938 printf("x %08x %08x %d %d c %08x %08x\n",smrv[r],start+i*4,
3939 ((smrv_strong>>r)&1),(smrv_weak>>r)&1,regs[i].isconst,regs[i].wasconst);
3951 static int get_ptr_mem_type(u_int a)
3953 if(a < 0x00200000) {
3954 if(a<0x1000&&((start>>20)==0xbfc||(start>>24)==0xa0))
3955 // return wrong, must use memhandler for BIOS self-test to pass
3956 // 007 does similar stuff from a00 mirror, weird stuff
3960 if(0x1f800000 <= a && a < 0x1f801000)
3962 if(0x80200000 <= a && a < 0x80800000)
3964 if(0xa0000000 <= a && a < 0xa0200000)
3970 static int emit_fastpath_cmp_jump(int i,int addr,int *addr_reg_override)
3976 if(((smrv_strong|smrv_weak)>>mr)&1) {
3977 type=get_ptr_mem_type(smrv[mr]);
3978 //printf("set %08x @%08x r%d %d\n", smrv[mr], start+i*4, mr, type);
3981 // use the mirror we are running on
3982 type=get_ptr_mem_type(start);
3983 //printf("set nospec @%08x r%d %d\n", start+i*4, mr, type);
3986 if(type==MTYPE_8020) { // RAM 80200000+ mirror
3987 emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
3988 addr=*addr_reg_override=HOST_TEMPREG;
3991 else if(type==MTYPE_0000) { // RAM 0 mirror
3992 emit_orimm(addr,0x80000000,HOST_TEMPREG);
3993 addr=*addr_reg_override=HOST_TEMPREG;
3996 else if(type==MTYPE_A000) { // RAM A mirror
3997 emit_andimm(addr,~0x20000000,HOST_TEMPREG);
3998 addr=*addr_reg_override=HOST_TEMPREG;
4001 else if(type==MTYPE_1F80) { // scratchpad
4002 if (psxH == (void *)0x1f800000) {
4003 emit_addimm(addr,-0x1f800000,HOST_TEMPREG);
4004 emit_cmpimm(HOST_TEMPREG,0x1000);
4009 // do usual RAM check, jump will go to the right handler
4017 emit_cmpimm(addr,RAM_SIZE);
4019 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
4020 // Hint to branch predictor that the branch is unlikely to be taken
4022 emit_jno_unlikely(0);
4027 emit_addimm(addr,ram_offset,HOST_TEMPREG);
4028 addr=*addr_reg_override=HOST_TEMPREG;
4035 #define shift_assemble shift_assemble_arm
4037 void loadlr_assemble_arm(int i,struct regstat *i_regs)
4039 int s,th,tl,temp,temp2,addr,map=-1;
4042 int memtarget=0,c=0;
4043 int fastload_reg_override=0;
4045 th=get_reg(i_regs->regmap,rt1[i]|64);
4046 tl=get_reg(i_regs->regmap,rt1[i]);
4047 s=get_reg(i_regs->regmap,rs1[i]);
4048 temp=get_reg(i_regs->regmap,-1);
4049 temp2=get_reg(i_regs->regmap,FTEMP);
4050 addr=get_reg(i_regs->regmap,AGEN1+(i&1));
4053 for(hr=0;hr<HOST_REGS;hr++) {
4054 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
4057 if(offset||s<0||c) addr=temp2;
4060 c=(i_regs->wasconst>>s)&1;
4062 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
4063 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
4069 map=get_reg(i_regs->regmap,ROREG);
4070 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
4072 emit_shlimm(addr,3,temp);
4073 if (opcode[i]==0x22||opcode[i]==0x26) {
4074 emit_andimm(addr,0xFFFFFFFC,temp2); // LWL/LWR
4076 emit_andimm(addr,0xFFFFFFF8,temp2); // LDL/LDR
4078 jaddr=emit_fastpath_cmp_jump(i,temp2,&fastload_reg_override);
4081 if(ram_offset&&memtarget) {
4082 emit_addimm(temp2,ram_offset,HOST_TEMPREG);
4083 fastload_reg_override=HOST_TEMPREG;
4085 if (opcode[i]==0x22||opcode[i]==0x26) {
4086 emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR
4088 emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR
4095 }else if (opcode[i]==0x22||opcode[i]==0x26) {
4096 a=0xFFFFFFFC; // LWL/LWR
4098 a=0xFFFFFFF8; // LDL/LDR
4100 map=get_reg(i_regs->regmap,TLREG);
4103 map=do_tlb_r(addr,temp2,map,0,a,c?-1:temp,c,constmap[i][s]+offset);
4105 if (opcode[i]==0x22||opcode[i]==0x26) {
4106 emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR
4108 emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR
4111 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
4113 if (opcode[i]==0x22||opcode[i]==0x26) { // LWL/LWR
4116 if(fastload_reg_override) a=fastload_reg_override;
4117 //emit_readword_indexed((int)rdram-0x80000000,temp2,temp2);
4118 emit_readword_indexed_tlb(0,a,map,temp2);
4119 if(jaddr) add_stub(LOADW_STUB,jaddr,(int)out,i,temp2,(int)i_regs,ccadj[i],reglist);
4122 inline_readstub(LOADW_STUB,i,(constmap[i][s]+offset)&0xFFFFFFFC,i_regs->regmap,FTEMP,ccadj[i],reglist);
4125 emit_andimm(temp,24,temp);
4126 #ifdef BIG_ENDIAN_MIPS
4127 if (opcode[i]==0x26) // LWR
4129 if (opcode[i]==0x22) // LWL
4131 emit_xorimm(temp,24,temp);
4132 emit_movimm(-1,HOST_TEMPREG);
4133 if (opcode[i]==0x26) {
4134 emit_shr(temp2,temp,temp2);
4135 emit_bic_lsr(tl,HOST_TEMPREG,temp,tl);
4137 emit_shl(temp2,temp,temp2);
4138 emit_bic_lsl(tl,HOST_TEMPREG,temp,tl);
4140 emit_or(temp2,tl,tl);
4142 //emit_storereg(rt1[i],tl); // DEBUG
4144 if (opcode[i]==0x1A||opcode[i]==0x1B) { // LDL/LDR
4145 // FIXME: little endian, fastload_reg_override
4146 int temp2h=get_reg(i_regs->regmap,FTEMP|64);
4148 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,temp2,temp2h);
4149 //emit_readword_indexed((int)rdram-0x7FFFFFFC,temp2,temp2);
4150 emit_readdword_indexed_tlb(0,temp2,map,temp2h,temp2);
4151 if(jaddr) add_stub(LOADD_STUB,jaddr,(int)out,i,temp2,(int)i_regs,ccadj[i],reglist);
4154 inline_readstub(LOADD_STUB,i,(constmap[i][s]+offset)&0xFFFFFFF8,i_regs->regmap,FTEMP,ccadj[i],reglist);
4158 emit_testimm(temp,32);
4159 emit_andimm(temp,24,temp);
4160 if (opcode[i]==0x1A) { // LDL
4161 emit_rsbimm(temp,32,HOST_TEMPREG);
4162 emit_shl(temp2h,temp,temp2h);
4163 emit_orrshr(temp2,HOST_TEMPREG,temp2h);
4164 emit_movimm(-1,HOST_TEMPREG);
4165 emit_shl(temp2,temp,temp2);
4166 emit_cmove_reg(temp2h,th);
4167 emit_biceq_lsl(tl,HOST_TEMPREG,temp,tl);
4168 emit_bicne_lsl(th,HOST_TEMPREG,temp,th);
4169 emit_orreq(temp2,tl,tl);
4170 emit_orrne(temp2,th,th);
4172 if (opcode[i]==0x1B) { // LDR
4173 emit_xorimm(temp,24,temp);
4174 emit_rsbimm(temp,32,HOST_TEMPREG);
4175 emit_shr(temp2,temp,temp2);
4176 emit_orrshl(temp2h,HOST_TEMPREG,temp2);
4177 emit_movimm(-1,HOST_TEMPREG);
4178 emit_shr(temp2h,temp,temp2h);
4179 emit_cmovne_reg(temp2,tl);
4180 emit_bicne_lsr(th,HOST_TEMPREG,temp,th);
4181 emit_biceq_lsr(tl,HOST_TEMPREG,temp,tl);
4182 emit_orrne(temp2h,th,th);
4183 emit_orreq(temp2h,tl,tl);
4188 #define loadlr_assemble loadlr_assemble_arm
4190 void cop0_assemble(int i,struct regstat *i_regs)
4192 if(opcode2[i]==0) // MFC0
4194 signed char t=get_reg(i_regs->regmap,rt1[i]);
4195 char copr=(source[i]>>11)&0x1f;
4196 //assert(t>=0); // Why does this happen? OOT is weird
4197 if(t>=0&&rt1[i]!=0) {
4199 emit_addimm(FP,(int)&fake_pc-(int)&dynarec_local,0);
4200 emit_movimm((source[i]>>11)&0x1f,1);
4201 emit_writeword(0,(int)&PC);
4202 emit_writebyte(1,(int)&(fake_pc.f.r.nrd));
4204 emit_readword((int)&last_count,ECX);
4205 emit_loadreg(CCREG,HOST_CCREG); // TODO: do proper reg alloc
4206 emit_add(HOST_CCREG,ECX,HOST_CCREG);
4207 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG);
4208 emit_writeword(HOST_CCREG,(int)&Count);
4210 emit_call((int)MFC0);
4211 emit_readword((int)&readmem_dword,t);
4213 emit_readword((int)®_cop0+copr*4,t);
4217 else if(opcode2[i]==4) // MTC0
4219 signed char s=get_reg(i_regs->regmap,rs1[i]);
4220 char copr=(source[i]>>11)&0x1f;
4223 emit_writeword(s,(int)&readmem_dword);
4224 wb_register(rs1[i],i_regs->regmap,i_regs->dirty,i_regs->is32);
4225 emit_addimm(FP,(int)&fake_pc-(int)&dynarec_local,0);
4226 emit_movimm((source[i]>>11)&0x1f,1);
4227 emit_writeword(0,(int)&PC);
4228 emit_writebyte(1,(int)&(fake_pc.f.r.nrd));
4230 wb_register(rs1[i],i_regs->regmap,i_regs->dirty,i_regs->is32);
4232 if(copr==9||copr==11||copr==12||copr==13) {
4233 emit_readword((int)&last_count,HOST_TEMPREG);
4234 emit_loadreg(CCREG,HOST_CCREG); // TODO: do proper reg alloc
4235 emit_add(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
4236 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG);
4237 emit_writeword(HOST_CCREG,(int)&Count);
4239 // What a mess. The status register (12) can enable interrupts,
4240 // so needs a special case to handle a pending interrupt.
4241 // The interrupt must be taken immediately, because a subsequent
4242 // instruction might disable interrupts again.
4243 if(copr==12||copr==13) {
4246 // burn cycles to cause cc_interrupt, which will
4247 // reschedule next_interupt. Relies on CCREG from above.
4248 assem_debug("MTC0 DS %d\n", copr);
4249 emit_writeword(HOST_CCREG,(int)&last_count);
4250 emit_movimm(0,HOST_CCREG);
4251 emit_storereg(CCREG,HOST_CCREG);
4252 emit_loadreg(rs1[i],1);
4253 emit_movimm(copr,0);
4254 emit_call((int)pcsx_mtc0_ds);
4255 emit_loadreg(rs1[i],s);
4259 emit_movimm(start+i*4+4,HOST_TEMPREG);
4260 emit_writeword(HOST_TEMPREG,(int)&pcaddr);
4261 emit_movimm(0,HOST_TEMPREG);
4262 emit_writeword(HOST_TEMPREG,(int)&pending_exception);
4264 //else if(copr==12&&is_delayslot) emit_call((int)MTC0_R12);
4268 emit_loadreg(rs1[i],1);
4271 emit_movimm(copr,0);
4272 emit_call((int)pcsx_mtc0);
4274 emit_call((int)MTC0);
4276 if(copr==9||copr==11||copr==12||copr==13) {
4277 emit_readword((int)&Count,HOST_CCREG);
4278 emit_readword((int)&next_interupt,HOST_TEMPREG);
4279 emit_addimm(HOST_CCREG,-CLOCK_ADJUST(ccadj[i]),HOST_CCREG);
4280 emit_sub(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
4281 emit_writeword(HOST_TEMPREG,(int)&last_count);
4282 emit_storereg(CCREG,HOST_CCREG);
4284 if(copr==12||copr==13) {
4285 assert(!is_delayslot);
4286 emit_readword((int)&pending_exception,14);
4288 emit_jne((int)&do_interrupt);
4290 emit_loadreg(rs1[i],s);
4291 if(get_reg(i_regs->regmap,rs1[i]|64)>=0)
4292 emit_loadreg(rs1[i]|64,get_reg(i_regs->regmap,rs1[i]|64));
4297 assert(opcode2[i]==0x10);
4299 if((source[i]&0x3f)==0x01) // TLBR
4300 emit_call((int)TLBR);
4301 if((source[i]&0x3f)==0x02) // TLBWI
4302 emit_call((int)TLBWI_new);
4303 if((source[i]&0x3f)==0x06) { // TLBWR
4304 // The TLB entry written by TLBWR is dependent on the count,
4305 // so update the cycle count
4306 emit_readword((int)&last_count,ECX);
4307 if(i_regs->regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
4308 emit_add(HOST_CCREG,ECX,HOST_CCREG);
4309 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG);
4310 emit_writeword(HOST_CCREG,(int)&Count);
4311 emit_call((int)TLBWR_new);
4313 if((source[i]&0x3f)==0x08) // TLBP
4314 emit_call((int)TLBP);
4317 if((source[i]&0x3f)==0x10) // RFE
4319 emit_readword((int)&Status,0);
4320 emit_andimm(0,0x3c,1);
4321 emit_andimm(0,~0xf,0);
4322 emit_orrshr_imm(1,2,0);
4323 emit_writeword(0,(int)&Status);
4326 if((source[i]&0x3f)==0x18) // ERET
4329 if(i_regs->regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
4330 emit_addimm(HOST_CCREG,CLOCK_ADJUST(count),HOST_CCREG); // TODO: Should there be an extra cycle here?
4331 emit_jmp((int)jump_eret);
4337 static void cop2_get_dreg(u_int copr,signed char tl,signed char temp)
4347 emit_readword((int)®_cop2d[copr],tl);
4348 emit_signextend16(tl,tl);
4349 emit_writeword(tl,(int)®_cop2d[copr]); // hmh
4356 emit_readword((int)®_cop2d[copr],tl);
4357 emit_andimm(tl,0xffff,tl);
4358 emit_writeword(tl,(int)®_cop2d[copr]);
4361 emit_readword((int)®_cop2d[14],tl); // SXY2
4362 emit_writeword(tl,(int)®_cop2d[copr]);
4366 emit_readword((int)®_cop2d[9],temp);
4367 emit_testimm(temp,0x8000); // do we need this?
4368 emit_andimm(temp,0xf80,temp);
4369 emit_andne_imm(temp,0,temp);
4370 emit_shrimm(temp,7,tl);
4371 emit_readword((int)®_cop2d[10],temp);
4372 emit_testimm(temp,0x8000);
4373 emit_andimm(temp,0xf80,temp);
4374 emit_andne_imm(temp,0,temp);
4375 emit_orrshr_imm(temp,2,tl);
4376 emit_readword((int)®_cop2d[11],temp);
4377 emit_testimm(temp,0x8000);
4378 emit_andimm(temp,0xf80,temp);
4379 emit_andne_imm(temp,0,temp);
4380 emit_orrshl_imm(temp,3,tl);
4381 emit_writeword(tl,(int)®_cop2d[copr]);
4384 emit_readword((int)®_cop2d[copr],tl);
4389 static void cop2_put_dreg(u_int copr,signed char sl,signed char temp)
4393 emit_readword((int)®_cop2d[13],temp); // SXY1
4394 emit_writeword(sl,(int)®_cop2d[copr]);
4395 emit_writeword(temp,(int)®_cop2d[12]); // SXY0
4396 emit_readword((int)®_cop2d[14],temp); // SXY2
4397 emit_writeword(sl,(int)®_cop2d[14]);
4398 emit_writeword(temp,(int)®_cop2d[13]); // SXY1
4401 emit_andimm(sl,0x001f,temp);
4402 emit_shlimm(temp,7,temp);
4403 emit_writeword(temp,(int)®_cop2d[9]);
4404 emit_andimm(sl,0x03e0,temp);
4405 emit_shlimm(temp,2,temp);
4406 emit_writeword(temp,(int)®_cop2d[10]);
4407 emit_andimm(sl,0x7c00,temp);
4408 emit_shrimm(temp,3,temp);
4409 emit_writeword(temp,(int)®_cop2d[11]);
4410 emit_writeword(sl,(int)®_cop2d[28]);
4414 emit_mvnmi(temp,temp);
4416 emit_clz(temp,temp);
4418 emit_movs(temp,HOST_TEMPREG);
4419 emit_movimm(0,temp);
4420 emit_jeq((int)out+4*4);
4421 emit_addpl_imm(temp,1,temp);
4422 emit_lslpls_imm(HOST_TEMPREG,1,HOST_TEMPREG);
4423 emit_jns((int)out-2*4);
4425 emit_writeword(sl,(int)®_cop2d[30]);
4426 emit_writeword(temp,(int)®_cop2d[31]);
4431 emit_writeword(sl,(int)®_cop2d[copr]);
4436 void cop2_assemble(int i,struct regstat *i_regs)
4438 u_int copr=(source[i]>>11)&0x1f;
4439 signed char temp=get_reg(i_regs->regmap,-1);
4440 if (opcode2[i]==0) { // MFC2
4441 signed char tl=get_reg(i_regs->regmap,rt1[i]);
4442 if(tl>=0&&rt1[i]!=0)
4443 cop2_get_dreg(copr,tl,temp);
4445 else if (opcode2[i]==4) { // MTC2
4446 signed char sl=get_reg(i_regs->regmap,rs1[i]);
4447 cop2_put_dreg(copr,sl,temp);
4449 else if (opcode2[i]==2) // CFC2
4451 signed char tl=get_reg(i_regs->regmap,rt1[i]);
4452 if(tl>=0&&rt1[i]!=0)
4453 emit_readword((int)®_cop2c[copr],tl);
4455 else if (opcode2[i]==6) // CTC2
4457 signed char sl=get_reg(i_regs->regmap,rs1[i]);
4466 emit_signextend16(sl,temp);
4469 //value = value & 0x7ffff000;
4470 //if (value & 0x7f87e000) value |= 0x80000000;
4471 emit_shrimm(sl,12,temp);
4472 emit_shlimm(temp,12,temp);
4473 emit_testimm(temp,0x7f000000);
4474 emit_testeqimm(temp,0x00870000);
4475 emit_testeqimm(temp,0x0000e000);
4476 emit_orrne_imm(temp,0x80000000,temp);
4482 emit_writeword(temp,(int)®_cop2c[copr]);
4487 static void c2op_prologue(u_int op,u_int reglist)
4489 save_regs_all(reglist);
4492 emit_call((int)pcnt_gte_start);
4494 emit_addimm(FP,(int)&psxRegs.CP2D.r[0]-(int)&dynarec_local,0); // cop2 regs
4497 static void c2op_epilogue(u_int op,u_int reglist)
4501 emit_call((int)pcnt_gte_end);
4503 restore_regs_all(reglist);
4506 static void c2op_call_MACtoIR(int lm,int need_flags)
4509 emit_call((int)(lm?gteMACtoIR_lm1:gteMACtoIR_lm0));
4511 emit_call((int)(lm?gteMACtoIR_lm1_nf:gteMACtoIR_lm0_nf));
4514 static void c2op_call_rgb_func(void *func,int lm,int need_ir,int need_flags)
4516 emit_call((int)func);
4517 // func is C code and trashes r0
4518 emit_addimm(FP,(int)&psxRegs.CP2D.r[0]-(int)&dynarec_local,0);
4519 if(need_flags||need_ir)
4520 c2op_call_MACtoIR(lm,need_flags);
4521 emit_call((int)(need_flags?gteMACtoRGB:gteMACtoRGB_nf));
4524 static void c2op_assemble(int i,struct regstat *i_regs)
4526 signed char temp=get_reg(i_regs->regmap,-1);
4527 u_int c2op=source[i]&0x3f;
4528 u_int hr,reglist_full=0,reglist;
4529 int need_flags,need_ir;
4530 for(hr=0;hr<HOST_REGS;hr++) {
4531 if(i_regs->regmap[hr]>=0) reglist_full|=1<<hr;
4533 reglist=reglist_full&CALLER_SAVE_REGS;
4535 if (gte_handlers[c2op]!=NULL) {
4536 need_flags=!(gte_unneeded[i+1]>>63); // +1 because of how liveness detection works
4537 need_ir=(gte_unneeded[i+1]&0xe00)!=0xe00;
4538 assem_debug("gte op %08x, unneeded %016llx, need_flags %d, need_ir %d\n",
4539 source[i],gte_unneeded[i+1],need_flags,need_ir);
4540 if(new_dynarec_hacks&NDHACK_GTE_NO_FLAGS)
4542 int shift = (source[i] >> 19) & 1;
4543 int lm = (source[i] >> 10) & 1;
4548 int v = (source[i] >> 15) & 3;
4549 int cv = (source[i] >> 13) & 3;
4550 int mx = (source[i] >> 17) & 3;
4551 reglist=reglist_full&(CALLER_SAVE_REGS|0xf0); // +{r4-r7}
4552 c2op_prologue(c2op,reglist);
4553 /* r4,r5 = VXYZ(v) packed; r6 = &MX11(mx); r7 = &CV1(cv) */
4557 emit_movzwl_indexed(9*4,0,4); // gteIR
4558 emit_movzwl_indexed(10*4,0,6);
4559 emit_movzwl_indexed(11*4,0,5);
4560 emit_orrshl_imm(6,16,4);
4563 emit_addimm(0,32*4+mx*8*4,6);
4565 emit_readword((int)&zeromem_ptr,6);
4567 emit_addimm(0,32*4+(cv*8+5)*4,7);
4569 emit_readword((int)&zeromem_ptr,7);
4571 emit_movimm(source[i],1); // opcode
4572 emit_call((int)gteMVMVA_part_neon);
4575 emit_call((int)gteMACtoIR_flags_neon);
4579 emit_call((int)gteMVMVA_part_cv3sh12_arm);
4581 emit_movimm(shift,1);
4582 emit_call((int)(need_flags?gteMVMVA_part_arm:gteMVMVA_part_nf_arm));
4584 if(need_flags||need_ir)
4585 c2op_call_MACtoIR(lm,need_flags);
4587 #else /* if not HAVE_ARMV5 */
4588 c2op_prologue(c2op,reglist);
4589 emit_movimm(source[i],1); // opcode
4590 emit_writeword(1,(int)&psxRegs.code);
4591 emit_call((int)(need_flags?gte_handlers[c2op]:gte_handlers_nf[c2op]));
4596 c2op_prologue(c2op,reglist);
4597 emit_call((int)(shift?gteOP_part_shift:gteOP_part_noshift));
4598 if(need_flags||need_ir) {
4599 emit_addimm(FP,(int)&psxRegs.CP2D.r[0]-(int)&dynarec_local,0);
4600 c2op_call_MACtoIR(lm,need_flags);
4604 c2op_prologue(c2op,reglist);
4605 c2op_call_rgb_func(shift?gteDPCS_part_shift:gteDPCS_part_noshift,lm,need_ir,need_flags);
4608 c2op_prologue(c2op,reglist);
4609 c2op_call_rgb_func(shift?gteINTPL_part_shift:gteINTPL_part_noshift,lm,need_ir,need_flags);
4612 c2op_prologue(c2op,reglist);
4613 emit_call((int)(shift?gteSQR_part_shift:gteSQR_part_noshift));
4614 if(need_flags||need_ir) {
4615 emit_addimm(FP,(int)&psxRegs.CP2D.r[0]-(int)&dynarec_local,0);
4616 c2op_call_MACtoIR(lm,need_flags);
4620 c2op_prologue(c2op,reglist);
4621 c2op_call_rgb_func(gteDCPL_part,lm,need_ir,need_flags);
4624 c2op_prologue(c2op,reglist);
4625 c2op_call_rgb_func(shift?gteGPF_part_shift:gteGPF_part_noshift,lm,need_ir,need_flags);
4628 c2op_prologue(c2op,reglist);
4629 c2op_call_rgb_func(shift?gteGPL_part_shift:gteGPL_part_noshift,lm,need_ir,need_flags);
4633 c2op_prologue(c2op,reglist);
4635 emit_movimm(source[i],1); // opcode
4636 emit_writeword(1,(int)&psxRegs.code);
4638 emit_call((int)(need_flags?gte_handlers[c2op]:gte_handlers_nf[c2op]));
4641 c2op_epilogue(c2op,reglist);
4645 void cop1_unusable(int i,struct regstat *i_regs)
4647 // XXX: should just just do the exception instead
4651 add_stub(FP_STUB,jaddr,(int)out,i,0,(int)i_regs,is_delayslot,0);
4656 void cop1_assemble(int i,struct regstat *i_regs)
4658 #ifndef DISABLE_COP1
4659 // Check cop1 unusable
4661 signed char rs=get_reg(i_regs->regmap,CSREG);
4663 emit_testimm(rs,0x20000000);
4666 add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
4669 if (opcode2[i]==0) { // MFC1
4670 signed char tl=get_reg(i_regs->regmap,rt1[i]);
4672 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],tl);
4673 emit_readword_indexed(0,tl,tl);
4676 else if (opcode2[i]==1) { // DMFC1
4677 signed char tl=get_reg(i_regs->regmap,rt1[i]);
4678 signed char th=get_reg(i_regs->regmap,rt1[i]|64);
4680 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],tl);
4681 if(th>=0) emit_readword_indexed(4,tl,th);
4682 emit_readword_indexed(0,tl,tl);
4685 else if (opcode2[i]==4) { // MTC1
4686 signed char sl=get_reg(i_regs->regmap,rs1[i]);
4687 signed char temp=get_reg(i_regs->regmap,-1);
4688 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
4689 emit_writeword_indexed(sl,0,temp);
4691 else if (opcode2[i]==5) { // DMTC1
4692 signed char sl=get_reg(i_regs->regmap,rs1[i]);
4693 signed char sh=rs1[i]>0?get_reg(i_regs->regmap,rs1[i]|64):sl;
4694 signed char temp=get_reg(i_regs->regmap,-1);
4695 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],temp);
4696 emit_writeword_indexed(sh,4,temp);
4697 emit_writeword_indexed(sl,0,temp);
4699 else if (opcode2[i]==2) // CFC1
4701 signed char tl=get_reg(i_regs->regmap,rt1[i]);
4703 u_int copr=(source[i]>>11)&0x1f;
4704 if(copr==0) emit_readword((int)&FCR0,tl);
4705 if(copr==31) emit_readword((int)&FCR31,tl);
4708 else if (opcode2[i]==6) // CTC1
4710 signed char sl=get_reg(i_regs->regmap,rs1[i]);
4711 u_int copr=(source[i]>>11)&0x1f;
4715 emit_writeword(sl,(int)&FCR31);
4716 // Set the rounding mode
4718 //char temp=get_reg(i_regs->regmap,-1);
4719 //emit_andimm(sl,3,temp);
4720 //emit_fldcw_indexed((int)&rounding_modes,temp);
4724 cop1_unusable(i, i_regs);
4728 void fconv_assemble_arm(int i,struct regstat *i_regs)
4730 #ifndef DISABLE_COP1
4731 signed char temp=get_reg(i_regs->regmap,-1);
4733 // Check cop1 unusable
4735 signed char rs=get_reg(i_regs->regmap,CSREG);
4737 emit_testimm(rs,0x20000000);
4740 add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
4744 #if(defined(__VFP_FP__) && !defined(__SOFTFP__))
4745 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x0d) { // trunc_w_s
4746 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
4748 emit_ftosizs(15,15); // float->int, truncate
4749 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f))
4750 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],temp);
4754 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x0d) { // trunc_w_d
4755 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],temp);
4757 emit_ftosizd(7,13); // double->int, truncate
4758 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],temp);
4763 if(opcode2[i]==0x14&&(source[i]&0x3f)==0x20) { // cvt_s_w
4764 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
4766 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f))
4767 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],temp);
4772 if(opcode2[i]==0x14&&(source[i]&0x3f)==0x21) { // cvt_d_w
4773 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
4775 emit_readword((int)®_cop1_double[(source[i]>>6)&0x1f],temp);
4781 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x21) { // cvt_d_s
4782 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
4784 emit_readword((int)®_cop1_double[(source[i]>>6)&0x1f],temp);
4789 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x20) { // cvt_s_d
4790 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],temp);
4792 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],temp);
4802 for(hr=0;hr<HOST_REGS;hr++) {
4803 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
4807 if(opcode2[i]==0x14&&(source[i]&0x3f)==0x20) {
4808 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
4809 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
4810 emit_call((int)cvt_s_w);
4812 if(opcode2[i]==0x14&&(source[i]&0x3f)==0x21) {
4813 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
4814 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
4815 emit_call((int)cvt_d_w);
4817 if(opcode2[i]==0x15&&(source[i]&0x3f)==0x20) {
4818 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
4819 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
4820 emit_call((int)cvt_s_l);
4822 if(opcode2[i]==0x15&&(source[i]&0x3f)==0x21) {
4823 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
4824 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
4825 emit_call((int)cvt_d_l);
4828 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x21) {
4829 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
4830 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
4831 emit_call((int)cvt_d_s);
4833 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x24) {
4834 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
4835 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
4836 emit_call((int)cvt_w_s);
4838 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x25) {
4839 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
4840 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
4841 emit_call((int)cvt_l_s);
4844 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x20) {
4845 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
4846 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
4847 emit_call((int)cvt_s_d);
4849 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x24) {
4850 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
4851 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
4852 emit_call((int)cvt_w_d);
4854 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x25) {
4855 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
4856 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
4857 emit_call((int)cvt_l_d);
4860 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x08) {
4861 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
4862 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
4863 emit_call((int)round_l_s);
4865 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x09) {
4866 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
4867 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
4868 emit_call((int)trunc_l_s);
4870 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x0a) {
4871 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
4872 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
4873 emit_call((int)ceil_l_s);
4875 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x0b) {
4876 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
4877 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
4878 emit_call((int)floor_l_s);
4880 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x0c) {
4881 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
4882 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
4883 emit_call((int)round_w_s);
4885 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x0d) {
4886 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
4887 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
4888 emit_call((int)trunc_w_s);
4890 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x0e) {
4891 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
4892 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
4893 emit_call((int)ceil_w_s);
4895 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x0f) {
4896 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
4897 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
4898 emit_call((int)floor_w_s);
4901 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x08) {
4902 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
4903 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
4904 emit_call((int)round_l_d);
4906 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x09) {
4907 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
4908 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
4909 emit_call((int)trunc_l_d);
4911 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x0a) {
4912 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
4913 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
4914 emit_call((int)ceil_l_d);
4916 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x0b) {
4917 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
4918 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
4919 emit_call((int)floor_l_d);
4921 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x0c) {
4922 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
4923 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
4924 emit_call((int)round_w_d);
4926 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x0d) {
4927 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
4928 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
4929 emit_call((int)trunc_w_d);
4931 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x0e) {
4932 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
4933 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
4934 emit_call((int)ceil_w_d);
4936 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x0f) {
4937 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
4938 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
4939 emit_call((int)floor_w_d);
4942 restore_regs(reglist);
4944 cop1_unusable(i, i_regs);
4947 #define fconv_assemble fconv_assemble_arm
4949 void fcomp_assemble(int i,struct regstat *i_regs)
4951 #ifndef DISABLE_COP1
4952 signed char fs=get_reg(i_regs->regmap,FSREG);
4953 signed char temp=get_reg(i_regs->regmap,-1);
4955 // Check cop1 unusable
4957 signed char cs=get_reg(i_regs->regmap,CSREG);
4959 emit_testimm(cs,0x20000000);
4962 add_stub(FP_STUB,jaddr,(int)out,i,cs,(int)i_regs,is_delayslot,0);
4966 if((source[i]&0x3f)==0x30) {
4967 emit_andimm(fs,~0x800000,fs);
4971 if((source[i]&0x3e)==0x38) {
4972 // sf/ngle - these should throw exceptions for NaNs
4973 emit_andimm(fs,~0x800000,fs);
4977 #if(defined(__VFP_FP__) && !defined(__SOFTFP__))
4978 if(opcode2[i]==0x10) {
4979 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
4980 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],HOST_TEMPREG);
4981 emit_orimm(fs,0x800000,fs);
4983 emit_flds(HOST_TEMPREG,15);
4986 if((source[i]&0x3f)==0x31) emit_bicvc_imm(fs,0x800000,fs); // c_un_s
4987 if((source[i]&0x3f)==0x32) emit_bicne_imm(fs,0x800000,fs); // c_eq_s
4988 if((source[i]&0x3f)==0x33) {emit_bicne_imm(fs,0x800000,fs);emit_orrvs_imm(fs,0x800000,fs);} // c_ueq_s
4989 if((source[i]&0x3f)==0x34) emit_biccs_imm(fs,0x800000,fs); // c_olt_s
4990 if((source[i]&0x3f)==0x35) {emit_biccs_imm(fs,0x800000,fs);emit_orrvs_imm(fs,0x800000,fs);} // c_ult_s
4991 if((source[i]&0x3f)==0x36) emit_bichi_imm(fs,0x800000,fs); // c_ole_s
4992 if((source[i]&0x3f)==0x37) {emit_bichi_imm(fs,0x800000,fs);emit_orrvs_imm(fs,0x800000,fs);} // c_ule_s
4993 if((source[i]&0x3f)==0x3a) emit_bicne_imm(fs,0x800000,fs); // c_seq_s
4994 if((source[i]&0x3f)==0x3b) emit_bicne_imm(fs,0x800000,fs); // c_ngl_s
4995 if((source[i]&0x3f)==0x3c) emit_biccs_imm(fs,0x800000,fs); // c_lt_s
4996 if((source[i]&0x3f)==0x3d) emit_biccs_imm(fs,0x800000,fs); // c_nge_s
4997 if((source[i]&0x3f)==0x3e) emit_bichi_imm(fs,0x800000,fs); // c_le_s
4998 if((source[i]&0x3f)==0x3f) emit_bichi_imm(fs,0x800000,fs); // c_ngt_s
5001 if(opcode2[i]==0x11) {
5002 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],temp);
5003 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],HOST_TEMPREG);
5004 emit_orimm(fs,0x800000,fs);
5006 emit_vldr(HOST_TEMPREG,7);
5009 if((source[i]&0x3f)==0x31) emit_bicvc_imm(fs,0x800000,fs); // c_un_d
5010 if((source[i]&0x3f)==0x32) emit_bicne_imm(fs,0x800000,fs); // c_eq_d
5011 if((source[i]&0x3f)==0x33) {emit_bicne_imm(fs,0x800000,fs);emit_orrvs_imm(fs,0x800000,fs);} // c_ueq_d
5012 if((source[i]&0x3f)==0x34) emit_biccs_imm(fs,0x800000,fs); // c_olt_d
5013 if((source[i]&0x3f)==0x35) {emit_biccs_imm(fs,0x800000,fs);emit_orrvs_imm(fs,0x800000,fs);} // c_ult_d
5014 if((source[i]&0x3f)==0x36) emit_bichi_imm(fs,0x800000,fs); // c_ole_d
5015 if((source[i]&0x3f)==0x37) {emit_bichi_imm(fs,0x800000,fs);emit_orrvs_imm(fs,0x800000,fs);} // c_ule_d
5016 if((source[i]&0x3f)==0x3a) emit_bicne_imm(fs,0x800000,fs); // c_seq_d
5017 if((source[i]&0x3f)==0x3b) emit_bicne_imm(fs,0x800000,fs); // c_ngl_d
5018 if((source[i]&0x3f)==0x3c) emit_biccs_imm(fs,0x800000,fs); // c_lt_d
5019 if((source[i]&0x3f)==0x3d) emit_biccs_imm(fs,0x800000,fs); // c_nge_d
5020 if((source[i]&0x3f)==0x3e) emit_bichi_imm(fs,0x800000,fs); // c_le_d
5021 if((source[i]&0x3f)==0x3f) emit_bichi_imm(fs,0x800000,fs); // c_ngt_d
5029 for(hr=0;hr<HOST_REGS;hr++) {
5030 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
5034 if(opcode2[i]==0x10) {
5035 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
5036 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],ARG2_REG);
5037 if((source[i]&0x3f)==0x30) emit_call((int)c_f_s);
5038 if((source[i]&0x3f)==0x31) emit_call((int)c_un_s);
5039 if((source[i]&0x3f)==0x32) emit_call((int)c_eq_s);
5040 if((source[i]&0x3f)==0x33) emit_call((int)c_ueq_s);
5041 if((source[i]&0x3f)==0x34) emit_call((int)c_olt_s);
5042 if((source[i]&0x3f)==0x35) emit_call((int)c_ult_s);
5043 if((source[i]&0x3f)==0x36) emit_call((int)c_ole_s);
5044 if((source[i]&0x3f)==0x37) emit_call((int)c_ule_s);
5045 if((source[i]&0x3f)==0x38) emit_call((int)c_sf_s);
5046 if((source[i]&0x3f)==0x39) emit_call((int)c_ngle_s);
5047 if((source[i]&0x3f)==0x3a) emit_call((int)c_seq_s);
5048 if((source[i]&0x3f)==0x3b) emit_call((int)c_ngl_s);
5049 if((source[i]&0x3f)==0x3c) emit_call((int)c_lt_s);
5050 if((source[i]&0x3f)==0x3d) emit_call((int)c_nge_s);
5051 if((source[i]&0x3f)==0x3e) emit_call((int)c_le_s);
5052 if((source[i]&0x3f)==0x3f) emit_call((int)c_ngt_s);
5054 if(opcode2[i]==0x11) {
5055 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
5056 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],ARG2_REG);
5057 if((source[i]&0x3f)==0x30) emit_call((int)c_f_d);
5058 if((source[i]&0x3f)==0x31) emit_call((int)c_un_d);
5059 if((source[i]&0x3f)==0x32) emit_call((int)c_eq_d);
5060 if((source[i]&0x3f)==0x33) emit_call((int)c_ueq_d);
5061 if((source[i]&0x3f)==0x34) emit_call((int)c_olt_d);
5062 if((source[i]&0x3f)==0x35) emit_call((int)c_ult_d);
5063 if((source[i]&0x3f)==0x36) emit_call((int)c_ole_d);
5064 if((source[i]&0x3f)==0x37) emit_call((int)c_ule_d);
5065 if((source[i]&0x3f)==0x38) emit_call((int)c_sf_d);
5066 if((source[i]&0x3f)==0x39) emit_call((int)c_ngle_d);
5067 if((source[i]&0x3f)==0x3a) emit_call((int)c_seq_d);
5068 if((source[i]&0x3f)==0x3b) emit_call((int)c_ngl_d);
5069 if((source[i]&0x3f)==0x3c) emit_call((int)c_lt_d);
5070 if((source[i]&0x3f)==0x3d) emit_call((int)c_nge_d);
5071 if((source[i]&0x3f)==0x3e) emit_call((int)c_le_d);
5072 if((source[i]&0x3f)==0x3f) emit_call((int)c_ngt_d);
5074 restore_regs(reglist);
5075 emit_loadreg(FSREG,fs);
5077 cop1_unusable(i, i_regs);
5081 void float_assemble(int i,struct regstat *i_regs)
5083 #ifndef DISABLE_COP1
5084 signed char temp=get_reg(i_regs->regmap,-1);
5086 // Check cop1 unusable
5088 signed char cs=get_reg(i_regs->regmap,CSREG);
5090 emit_testimm(cs,0x20000000);
5093 add_stub(FP_STUB,jaddr,(int)out,i,cs,(int)i_regs,is_delayslot,0);
5097 #if(defined(__VFP_FP__) && !defined(__SOFTFP__))
5098 if((source[i]&0x3f)==6) // mov
5100 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f)) {
5101 if(opcode2[i]==0x10) {
5102 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
5103 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],HOST_TEMPREG);
5104 emit_readword_indexed(0,temp,temp);
5105 emit_writeword_indexed(temp,0,HOST_TEMPREG);
5107 if(opcode2[i]==0x11) {
5108 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],temp);
5109 emit_readword((int)®_cop1_double[(source[i]>>6)&0x1f],HOST_TEMPREG);
5111 emit_vstr(7,HOST_TEMPREG);
5117 if((source[i]&0x3f)>3)
5119 if(opcode2[i]==0x10) {
5120 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
5122 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f)) {
5123 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],temp);
5125 if((source[i]&0x3f)==4) // sqrt
5127 if((source[i]&0x3f)==5) // abs
5129 if((source[i]&0x3f)==7) // neg
5133 if(opcode2[i]==0x11) {
5134 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],temp);
5136 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f)) {
5137 emit_readword((int)®_cop1_double[(source[i]>>6)&0x1f],temp);
5139 if((source[i]&0x3f)==4) // sqrt
5141 if((source[i]&0x3f)==5) // abs
5143 if((source[i]&0x3f)==7) // neg
5149 if((source[i]&0x3f)<4)
5151 if(opcode2[i]==0x10) {
5152 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
5154 if(opcode2[i]==0x11) {
5155 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],temp);
5157 if(((source[i]>>11)&0x1f)!=((source[i]>>16)&0x1f)) {
5158 if(opcode2[i]==0x10) {
5159 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],HOST_TEMPREG);
5161 emit_flds(HOST_TEMPREG,13);
5162 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f)) {
5163 if(((source[i]>>16)&0x1f)!=((source[i]>>6)&0x1f)) {
5164 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],temp);
5167 if((source[i]&0x3f)==0) emit_fadds(15,13,15);
5168 if((source[i]&0x3f)==1) emit_fsubs(15,13,15);
5169 if((source[i]&0x3f)==2) emit_fmuls(15,13,15);
5170 if((source[i]&0x3f)==3) emit_fdivs(15,13,15);
5171 if(((source[i]>>16)&0x1f)==((source[i]>>6)&0x1f)) {
5172 emit_fsts(15,HOST_TEMPREG);
5177 else if(opcode2[i]==0x11) {
5178 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],HOST_TEMPREG);
5180 emit_vldr(HOST_TEMPREG,6);
5181 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f)) {
5182 if(((source[i]>>16)&0x1f)!=((source[i]>>6)&0x1f)) {
5183 emit_readword((int)®_cop1_double[(source[i]>>6)&0x1f],temp);
5186 if((source[i]&0x3f)==0) emit_faddd(7,6,7);
5187 if((source[i]&0x3f)==1) emit_fsubd(7,6,7);
5188 if((source[i]&0x3f)==2) emit_fmuld(7,6,7);
5189 if((source[i]&0x3f)==3) emit_fdivd(7,6,7);
5190 if(((source[i]>>16)&0x1f)==((source[i]>>6)&0x1f)) {
5191 emit_vstr(7,HOST_TEMPREG);
5198 if(opcode2[i]==0x10) {
5200 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f)) {
5201 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],temp);
5203 if((source[i]&0x3f)==0) emit_fadds(15,15,15);
5204 if((source[i]&0x3f)==1) emit_fsubs(15,15,15);
5205 if((source[i]&0x3f)==2) emit_fmuls(15,15,15);
5206 if((source[i]&0x3f)==3) emit_fdivs(15,15,15);
5209 else if(opcode2[i]==0x11) {
5211 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f)) {
5212 emit_readword((int)®_cop1_double[(source[i]>>6)&0x1f],temp);
5214 if((source[i]&0x3f)==0) emit_faddd(7,7,7);
5215 if((source[i]&0x3f)==1) emit_fsubd(7,7,7);
5216 if((source[i]&0x3f)==2) emit_fmuld(7,7,7);
5217 if((source[i]&0x3f)==3) emit_fdivd(7,7,7);
5226 for(hr=0;hr<HOST_REGS;hr++) {
5227 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
5229 if(opcode2[i]==0x10) { // Single precision
5231 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
5232 if((source[i]&0x3f)<4) {
5233 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],ARG2_REG);
5234 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG3_REG);
5236 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
5238 switch(source[i]&0x3f)
5240 case 0x00: emit_call((int)add_s);break;
5241 case 0x01: emit_call((int)sub_s);break;
5242 case 0x02: emit_call((int)mul_s);break;
5243 case 0x03: emit_call((int)div_s);break;
5244 case 0x04: emit_call((int)sqrt_s);break;
5245 case 0x05: emit_call((int)abs_s);break;
5246 case 0x06: emit_call((int)mov_s);break;
5247 case 0x07: emit_call((int)neg_s);break;
5249 restore_regs(reglist);
5251 if(opcode2[i]==0x11) { // Double precision
5253 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
5254 if((source[i]&0x3f)<4) {
5255 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],ARG2_REG);
5256 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG3_REG);
5258 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
5260 switch(source[i]&0x3f)
5262 case 0x00: emit_call((int)add_d);break;
5263 case 0x01: emit_call((int)sub_d);break;
5264 case 0x02: emit_call((int)mul_d);break;
5265 case 0x03: emit_call((int)div_d);break;
5266 case 0x04: emit_call((int)sqrt_d);break;
5267 case 0x05: emit_call((int)abs_d);break;
5268 case 0x06: emit_call((int)mov_d);break;
5269 case 0x07: emit_call((int)neg_d);break;
5271 restore_regs(reglist);
5274 cop1_unusable(i, i_regs);
5278 void multdiv_assemble_arm(int i,struct regstat *i_regs)
5285 // case 0x1D: DMULTU
5290 if((opcode2[i]&4)==0) // 32-bit
5292 if(opcode2[i]==0x18) // MULT
5294 signed char m1=get_reg(i_regs->regmap,rs1[i]);
5295 signed char m2=get_reg(i_regs->regmap,rs2[i]);
5296 signed char hi=get_reg(i_regs->regmap,HIREG);
5297 signed char lo=get_reg(i_regs->regmap,LOREG);
5302 emit_smull(m1,m2,hi,lo);
5304 if(opcode2[i]==0x19) // MULTU
5306 signed char m1=get_reg(i_regs->regmap,rs1[i]);
5307 signed char m2=get_reg(i_regs->regmap,rs2[i]);
5308 signed char hi=get_reg(i_regs->regmap,HIREG);
5309 signed char lo=get_reg(i_regs->regmap,LOREG);
5314 emit_umull(m1,m2,hi,lo);
5316 if(opcode2[i]==0x1A) // DIV
5318 signed char d1=get_reg(i_regs->regmap,rs1[i]);
5319 signed char d2=get_reg(i_regs->regmap,rs2[i]);
5322 signed char quotient=get_reg(i_regs->regmap,LOREG);
5323 signed char remainder=get_reg(i_regs->regmap,HIREG);
5324 assert(quotient>=0);
5325 assert(remainder>=0);
5326 emit_movs(d1,remainder);
5327 emit_movimm(0xffffffff,quotient);
5328 emit_negmi(quotient,quotient); // .. quotient and ..
5329 emit_negmi(remainder,remainder); // .. remainder for div0 case (will be negated back after jump)
5330 emit_movs(d2,HOST_TEMPREG);
5331 emit_jeq((int)out+52); // Division by zero
5332 emit_negsmi(HOST_TEMPREG,HOST_TEMPREG);
5334 emit_clz(HOST_TEMPREG,quotient);
5335 emit_shl(HOST_TEMPREG,quotient,HOST_TEMPREG);
5337 emit_movimm(0,quotient);
5338 emit_addpl_imm(quotient,1,quotient);
5339 emit_lslpls_imm(HOST_TEMPREG,1,HOST_TEMPREG);
5340 emit_jns((int)out-2*4);
5342 emit_orimm(quotient,1<<31,quotient);
5343 emit_shr(quotient,quotient,quotient);
5344 emit_cmp(remainder,HOST_TEMPREG);
5345 emit_subcs(remainder,HOST_TEMPREG,remainder);
5346 emit_adcs(quotient,quotient,quotient);
5347 emit_shrimm(HOST_TEMPREG,1,HOST_TEMPREG);
5348 emit_jcc((int)out-16); // -4
5350 emit_negmi(quotient,quotient);
5352 emit_negmi(remainder,remainder);
5354 if(opcode2[i]==0x1B) // DIVU
5356 signed char d1=get_reg(i_regs->regmap,rs1[i]); // dividend
5357 signed char d2=get_reg(i_regs->regmap,rs2[i]); // divisor
5360 signed char quotient=get_reg(i_regs->regmap,LOREG);
5361 signed char remainder=get_reg(i_regs->regmap,HIREG);
5362 assert(quotient>=0);
5363 assert(remainder>=0);
5364 emit_mov(d1,remainder);
5365 emit_movimm(0xffffffff,quotient); // div0 case
5367 emit_jeq((int)out+40); // Division by zero
5369 emit_clz(d2,HOST_TEMPREG);
5370 emit_movimm(1<<31,quotient);
5371 emit_shl(d2,HOST_TEMPREG,d2);
5373 emit_movimm(0,HOST_TEMPREG);
5374 emit_addpl_imm(HOST_TEMPREG,1,HOST_TEMPREG);
5375 emit_lslpls_imm(d2,1,d2);
5376 emit_jns((int)out-2*4);
5377 emit_movimm(1<<31,quotient);
5379 emit_shr(quotient,HOST_TEMPREG,quotient);
5380 emit_cmp(remainder,d2);
5381 emit_subcs(remainder,d2,remainder);
5382 emit_adcs(quotient,quotient,quotient);
5383 emit_shrcc_imm(d2,1,d2);
5384 emit_jcc((int)out-16); // -4
5390 if(opcode2[i]==0x1C) // DMULT
5392 assert(opcode2[i]!=0x1C);
5393 signed char m1h=get_reg(i_regs->regmap,rs1[i]|64);
5394 signed char m1l=get_reg(i_regs->regmap,rs1[i]);
5395 signed char m2h=get_reg(i_regs->regmap,rs2[i]|64);
5396 signed char m2l=get_reg(i_regs->regmap,rs2[i]);
5405 emit_call((int)&mult64);
5410 signed char hih=get_reg(i_regs->regmap,HIREG|64);
5411 signed char hil=get_reg(i_regs->regmap,HIREG);
5412 if(hih>=0) emit_loadreg(HIREG|64,hih);
5413 if(hil>=0) emit_loadreg(HIREG,hil);
5414 signed char loh=get_reg(i_regs->regmap,LOREG|64);
5415 signed char lol=get_reg(i_regs->regmap,LOREG);
5416 if(loh>=0) emit_loadreg(LOREG|64,loh);
5417 if(lol>=0) emit_loadreg(LOREG,lol);
5419 if(opcode2[i]==0x1D) // DMULTU
5421 signed char m1h=get_reg(i_regs->regmap,rs1[i]|64);
5422 signed char m1l=get_reg(i_regs->regmap,rs1[i]);
5423 signed char m2h=get_reg(i_regs->regmap,rs2[i]|64);
5424 signed char m2l=get_reg(i_regs->regmap,rs2[i]);
5429 save_regs(CALLER_SAVE_REGS);
5430 if(m1l!=0) emit_mov(m1l,0);
5431 if(m1h==0) emit_readword((int)&dynarec_local,1);
5432 else if(m1h>1) emit_mov(m1h,1);
5433 if(m2l<2) emit_readword((int)&dynarec_local+m2l*4,2);
5434 else if(m2l>2) emit_mov(m2l,2);
5435 if(m2h<3) emit_readword((int)&dynarec_local+m2h*4,3);
5436 else if(m2h>3) emit_mov(m2h,3);
5437 emit_call((int)&multu64);
5438 restore_regs(CALLER_SAVE_REGS);
5439 signed char hih=get_reg(i_regs->regmap,HIREG|64);
5440 signed char hil=get_reg(i_regs->regmap,HIREG);
5441 signed char loh=get_reg(i_regs->regmap,LOREG|64);
5442 signed char lol=get_reg(i_regs->regmap,LOREG);
5443 /*signed char temp=get_reg(i_regs->regmap,-1);
5444 signed char rh=get_reg(i_regs->regmap,HIREG|64);
5445 signed char rl=get_reg(i_regs->regmap,HIREG);
5451 //emit_mov(m1l,EAX);
5453 emit_umull(rl,rh,m1l,m2l);
5454 emit_storereg(LOREG,rl);
5456 //emit_mov(m1h,EAX);
5458 emit_umull(rl,rh,m1h,m2l);
5459 emit_adds(rl,temp,temp);
5460 emit_adcimm(rh,0,rh);
5461 emit_storereg(HIREG,rh);
5462 //emit_mov(m2h,EAX);
5464 emit_umull(rl,rh,m1l,m2h);
5465 emit_adds(rl,temp,temp);
5466 emit_adcimm(rh,0,rh);
5467 emit_storereg(LOREG|64,temp);
5469 //emit_mov(m2h,EAX);
5471 emit_umull(rl,rh,m1h,m2h);
5472 emit_adds(rl,temp,rl);
5473 emit_loadreg(HIREG,temp);
5474 emit_adcimm(rh,0,rh);
5475 emit_adds(rl,temp,rl);
5476 emit_adcimm(rh,0,rh);
5483 emit_call((int)&multu64);
5488 signed char hih=get_reg(i_regs->regmap,HIREG|64);
5489 signed char hil=get_reg(i_regs->regmap,HIREG);
5490 if(hih>=0) emit_loadreg(HIREG|64,hih); // DEBUG
5491 if(hil>=0) emit_loadreg(HIREG,hil); // DEBUG
5493 // Shouldn't be necessary
5494 //char loh=get_reg(i_regs->regmap,LOREG|64);
5495 //char lol=get_reg(i_regs->regmap,LOREG);
5496 //if(loh>=0) emit_loadreg(LOREG|64,loh);
5497 //if(lol>=0) emit_loadreg(LOREG,lol);
5499 if(opcode2[i]==0x1E) // DDIV
5501 signed char d1h=get_reg(i_regs->regmap,rs1[i]|64);
5502 signed char d1l=get_reg(i_regs->regmap,rs1[i]);
5503 signed char d2h=get_reg(i_regs->regmap,rs2[i]|64);
5504 signed char d2l=get_reg(i_regs->regmap,rs2[i]);
5509 save_regs(CALLER_SAVE_REGS);
5510 if(d1l!=0) emit_mov(d1l,0);
5511 if(d1h==0) emit_readword((int)&dynarec_local,1);
5512 else if(d1h>1) emit_mov(d1h,1);
5513 if(d2l<2) emit_readword((int)&dynarec_local+d2l*4,2);
5514 else if(d2l>2) emit_mov(d2l,2);
5515 if(d2h<3) emit_readword((int)&dynarec_local+d2h*4,3);
5516 else if(d2h>3) emit_mov(d2h,3);
5517 emit_call((int)&div64);
5518 restore_regs(CALLER_SAVE_REGS);
5519 signed char hih=get_reg(i_regs->regmap,HIREG|64);
5520 signed char hil=get_reg(i_regs->regmap,HIREG);
5521 signed char loh=get_reg(i_regs->regmap,LOREG|64);
5522 signed char lol=get_reg(i_regs->regmap,LOREG);
5523 if(hih>=0) emit_loadreg(HIREG|64,hih);
5524 if(hil>=0) emit_loadreg(HIREG,hil);
5525 if(loh>=0) emit_loadreg(LOREG|64,loh);
5526 if(lol>=0) emit_loadreg(LOREG,lol);
5528 if(opcode2[i]==0x1F) // DDIVU
5530 //u_int hr,reglist=0;
5531 //for(hr=0;hr<HOST_REGS;hr++) {
5532 // if(i_regs->regmap[hr]>=0 && (i_regs->regmap[hr]&62)!=HIREG) reglist|=1<<hr;
5534 signed char d1h=get_reg(i_regs->regmap,rs1[i]|64);
5535 signed char d1l=get_reg(i_regs->regmap,rs1[i]);
5536 signed char d2h=get_reg(i_regs->regmap,rs2[i]|64);
5537 signed char d2l=get_reg(i_regs->regmap,rs2[i]);
5542 save_regs(CALLER_SAVE_REGS);
5543 if(d1l!=0) emit_mov(d1l,0);
5544 if(d1h==0) emit_readword((int)&dynarec_local,1);
5545 else if(d1h>1) emit_mov(d1h,1);
5546 if(d2l<2) emit_readword((int)&dynarec_local+d2l*4,2);
5547 else if(d2l>2) emit_mov(d2l,2);
5548 if(d2h<3) emit_readword((int)&dynarec_local+d2h*4,3);
5549 else if(d2h>3) emit_mov(d2h,3);
5550 emit_call((int)&divu64);
5551 restore_regs(CALLER_SAVE_REGS);
5552 signed char hih=get_reg(i_regs->regmap,HIREG|64);
5553 signed char hil=get_reg(i_regs->regmap,HIREG);
5554 signed char loh=get_reg(i_regs->regmap,LOREG|64);
5555 signed char lol=get_reg(i_regs->regmap,LOREG);
5556 if(hih>=0) emit_loadreg(HIREG|64,hih);
5557 if(hil>=0) emit_loadreg(HIREG,hil);
5558 if(loh>=0) emit_loadreg(LOREG|64,loh);
5559 if(lol>=0) emit_loadreg(LOREG,lol);
5568 // Multiply by zero is zero.
5569 // MIPS does not have a divide by zero exception.
5570 // The result is undefined, we return zero.
5571 signed char hr=get_reg(i_regs->regmap,HIREG);
5572 signed char lr=get_reg(i_regs->regmap,LOREG);
5573 if(hr>=0) emit_zeroreg(hr);
5574 if(lr>=0) emit_zeroreg(lr);
5577 #define multdiv_assemble multdiv_assemble_arm
5579 void do_preload_rhash(int r) {
5580 // Don't need this for ARM. On x86, this puts the value 0xf8 into the
5581 // register. On ARM the hash can be done with a single instruction (below)
5584 void do_preload_rhtbl(int ht) {
5585 emit_addimm(FP,(int)&mini_ht-(int)&dynarec_local,ht);
5588 void do_rhash(int rs,int rh) {
5589 emit_andimm(rs,0xf8,rh);
5592 void do_miniht_load(int ht,int rh) {
5593 assem_debug("ldr %s,[%s,%s]!\n",regname[rh],regname[ht],regname[rh]);
5594 output_w32(0xe7b00000|rd_rn_rm(rh,ht,rh));
5597 void do_miniht_jump(int rs,int rh,int ht) {
5599 emit_ldreq_indexed(ht,4,15);
5600 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5602 emit_jmp(jump_vaddr_reg[7]);
5604 emit_jmp(jump_vaddr_reg[rs]);
5608 void do_miniht_insert(u_int return_address,int rt,int temp) {
5610 emit_movimm(return_address,rt); // PC into link register
5611 add_to_linker((int)out,return_address,1);
5612 emit_pcreladdr(temp);
5613 emit_writeword(rt,(int)&mini_ht[(return_address&0xFF)>>3][0]);
5614 emit_writeword(temp,(int)&mini_ht[(return_address&0xFF)>>3][1]);
5616 emit_movw(return_address&0x0000FFFF,rt);
5617 add_to_linker((int)out,return_address,1);
5618 emit_pcreladdr(temp);
5619 emit_writeword(temp,(int)&mini_ht[(return_address&0xFF)>>3][1]);
5620 emit_movt(return_address&0xFFFF0000,rt);
5621 emit_writeword(rt,(int)&mini_ht[(return_address&0xFF)>>3][0]);
5625 // Sign-extend to 64 bits and write out upper half of a register
5626 // This is useful where we have a 32-bit value in a register, and want to
5627 // keep it in a 32-bit register, but can't guarantee that it won't be read
5628 // as a 64-bit value later.
5629 void wb_sx(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32_pre,uint64_t is32,uint64_t u,uint64_t uu)
5632 if(is32_pre==is32) return;
5634 for(hr=0;hr<HOST_REGS;hr++) {
5635 if(hr!=EXCLUDE_REG) {
5636 //if(pre[hr]==entry[hr]) {
5637 if((reg=pre[hr])>=0) {
5639 if( ((is32_pre&~is32&~uu)>>reg)&1 ) {
5640 emit_sarimm(hr,31,HOST_TEMPREG);
5641 emit_storereg(reg|64,HOST_TEMPREG);
5651 void wb_valid(signed char pre[],signed char entry[],u_int dirty_pre,u_int dirty,uint64_t is32_pre,uint64_t u,uint64_t uu)
5653 //if(dirty_pre==dirty) return;
5655 for(hr=0;hr<HOST_REGS;hr++) {
5656 if(hr!=EXCLUDE_REG) {
5658 if(((~u)>>(reg&63))&1) {
5660 if(((dirty_pre&~dirty)>>hr)&1) {
5662 emit_storereg(reg,hr);
5663 if( ((is32_pre&~uu)>>reg)&1 ) {
5664 emit_sarimm(hr,31,HOST_TEMPREG);
5665 emit_storereg(reg|64,HOST_TEMPREG);
5669 emit_storereg(reg,hr);
5679 /* using strd could possibly help but you'd have to allocate registers in pairs
5680 void wb_invalidate_arm(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,uint64_t u,uint64_t uu)
5684 for(hr=HOST_REGS-1;hr>=0;hr--) {
5685 if(hr!=EXCLUDE_REG) {
5686 if(pre[hr]!=entry[hr]) {
5689 if(get_reg(entry,pre[hr])<0) {
5691 if(!((u>>pre[hr])&1)) {
5692 if(hr<10&&(~hr&1)&&(pre[hr+1]<0||wrote==hr+1)) {
5693 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
5694 emit_sarimm(hr,31,hr+1);
5695 emit_strdreg(pre[hr],hr);
5698 emit_storereg(pre[hr],hr);
5700 emit_storereg(pre[hr],hr);
5701 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
5702 emit_sarimm(hr,31,hr);
5703 emit_storereg(pre[hr]|64,hr);
5708 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
5709 emit_storereg(pre[hr],hr);
5719 for(hr=0;hr<HOST_REGS;hr++) {
5720 if(hr!=EXCLUDE_REG) {
5721 if(pre[hr]!=entry[hr]) {
5724 if((nr=get_reg(entry,pre[hr]))>=0) {
5732 #define wb_invalidate wb_invalidate_arm
5735 // Clearing the cache is rather slow on ARM Linux, so mark the areas
5736 // that need to be cleared, and then only clear these areas once.
5737 void do_clear_cache()
5740 for (i=0;i<(1<<(TARGET_SIZE_2-17));i++)
5742 u_int bitmap=needs_clear_cache[i];
5748 start=(u_int)BASE_ADDR+i*131072+j*4096;
5756 __clear_cache((void *)start,(void *)end);
5762 needs_clear_cache[i]=0;
5767 // CPU-architecture-specific initialization
5769 #ifndef DISABLE_COP1
5770 rounding_modes[0]=0x0<<22; // round
5771 rounding_modes[1]=0x3<<22; // trunc
5772 rounding_modes[2]=0x1<<22; // ceil
5773 rounding_modes[3]=0x2<<22; // floor
5777 // vim:shiftwidth=2:expandtab