1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - assem_arm.c *
3 * Copyright (C) 2009-2010 Ari64 *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
21 extern int cycle_count;
22 extern int last_count;
24 extern int pending_exception;
25 extern int branch_target;
26 extern uint64_t readmem_dword;
28 extern precomp_instr fake_pc;
30 extern void *dynarec_local;
31 extern u_int memory_map[1048576];
32 extern u_int mini_ht[32][2];
33 extern u_int rounding_modes[4];
35 void indirect_jump_indexed();
48 void jump_vaddr_r10();
49 void jump_vaddr_r12();
51 const u_int jump_vaddr_reg[16] = {
69 void invalidate_addr_r0();
70 void invalidate_addr_r1();
71 void invalidate_addr_r2();
72 void invalidate_addr_r3();
73 void invalidate_addr_r4();
74 void invalidate_addr_r5();
75 void invalidate_addr_r6();
76 void invalidate_addr_r7();
77 void invalidate_addr_r8();
78 void invalidate_addr_r9();
79 void invalidate_addr_r10();
80 void invalidate_addr_r12();
82 const u_int invalidate_addr_reg[16] = {
83 (int)invalidate_addr_r0,
84 (int)invalidate_addr_r1,
85 (int)invalidate_addr_r2,
86 (int)invalidate_addr_r3,
87 (int)invalidate_addr_r4,
88 (int)invalidate_addr_r5,
89 (int)invalidate_addr_r6,
90 (int)invalidate_addr_r7,
91 (int)invalidate_addr_r8,
92 (int)invalidate_addr_r9,
93 (int)invalidate_addr_r10,
95 (int)invalidate_addr_r12,
102 unsigned int needs_clear_cache[1<<(TARGET_SIZE_2-17)];
106 void set_jump_target(int addr,u_int target)
108 u_char *ptr=(u_char *)addr;
109 u_int *ptr2=(u_int *)ptr;
111 assert((target-(u_int)ptr2-8)<1024);
113 assert((target&3)==0);
114 *ptr2=(*ptr2&0xFFFFF000)|((target-(u_int)ptr2-8)>>2)|0xF00;
115 //printf("target=%x addr=%x insn=%x\n",target,addr,*ptr2);
117 else if(ptr[3]==0x72) {
118 // generated by emit_jno_unlikely
119 if((target-(u_int)ptr2-8)<1024) {
121 assert((target&3)==0);
122 *ptr2=(*ptr2&0xFFFFF000)|((target-(u_int)ptr2-8)>>2)|0xF00;
124 else if((target-(u_int)ptr2-8)<4096&&!((target-(u_int)ptr2-8)&15)) {
126 assert((target&3)==0);
127 *ptr2=(*ptr2&0xFFFFF000)|((target-(u_int)ptr2-8)>>4)|0xE00;
129 else *ptr2=(0x7A000000)|(((target-(u_int)ptr2-8)<<6)>>8);
132 assert((ptr[3]&0x0e)==0xa);
133 *ptr2=(*ptr2&0xFF000000)|(((target-(u_int)ptr2-8)<<6)>>8);
137 // This optionally copies the instruction from the target of the branch into
138 // the space before the branch. Works, but the difference in speed is
139 // usually insignificant.
140 void set_jump_target_fillslot(int addr,u_int target,int copy)
142 u_char *ptr=(u_char *)addr;
143 u_int *ptr2=(u_int *)ptr;
144 assert(!copy||ptr2[-1]==0xe28dd000);
147 assert((target-(u_int)ptr2-8)<4096);
148 *ptr2=(*ptr2&0xFFFFF000)|(target-(u_int)ptr2-8);
151 assert((ptr[3]&0x0e)==0xa);
152 u_int target_insn=*(u_int *)target;
153 if((target_insn&0x0e100000)==0) { // ALU, no immediate, no flags
156 if((target_insn&0x0c100000)==0x04100000) { // Load
159 if(target_insn&0x08000000) {
163 ptr2[-1]=target_insn;
166 *ptr2=(*ptr2&0xFF000000)|(((target-(u_int)ptr2-8)<<6)>>8);
171 add_literal(int addr,int val)
173 literals[literalcount][0]=addr;
174 literals[literalcount][1]=val;
178 void *kill_pointer(void *stub)
180 int *ptr=(int *)(stub+4);
181 assert((*ptr&0x0ff00000)==0x05900000);
182 u_int offset=*ptr&0xfff;
183 int **l_ptr=(void *)ptr+offset+8;
185 set_jump_target((int)i_ptr,(int)stub);
189 int get_pointer(void *stub)
191 //printf("get_pointer(%x)\n",(int)stub);
192 int *ptr=(int *)(stub+4);
193 assert((*ptr&0x0ff00000)==0x05900000);
194 u_int offset=*ptr&0xfff;
195 int **l_ptr=(void *)ptr+offset+8;
197 assert((*i_ptr&0x0f000000)==0x0a000000);
198 return (int)i_ptr+((*i_ptr<<8)>>6)+8;
201 // Find the "clean" entry point from a "dirty" entry point
202 // by skipping past the call to verify_code
203 u_int get_clean_addr(int addr)
205 int *ptr=(int *)addr;
211 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
212 assert((*ptr&0xFF000000)==0xeb000000); // bl instruction
214 if((*ptr&0xFF000000)==0xea000000) {
215 return (int)ptr+((*ptr<<8)>>6)+8; // follow jump
220 int verify_dirty(int addr)
222 u_int *ptr=(u_int *)addr;
224 // get from literal pool
225 assert((*ptr&0xFFF00000)==0xe5900000);
226 u_int offset=*ptr&0xfff;
227 u_int *l_ptr=(void *)ptr+offset+8;
228 u_int source=l_ptr[0];
234 assert((*ptr&0xFFF00000)==0xe3000000);
235 u_int source=(ptr[0]&0xFFF)+((ptr[0]>>4)&0xF000)+((ptr[2]<<16)&0xFFF0000)+((ptr[2]<<12)&0xF0000000);
236 u_int copy=(ptr[1]&0xFFF)+((ptr[1]>>4)&0xF000)+((ptr[3]<<16)&0xFFF0000)+((ptr[3]<<12)&0xF0000000);
237 u_int len=(ptr[4]&0xFFF)+((ptr[4]>>4)&0xF000);
240 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
241 assert((*ptr&0xFF000000)==0xeb000000); // bl instruction
242 u_int verifier=(int)ptr+((signed int)(*ptr<<8)>>6)+8; // get target of bl
243 if(verifier==(u_int)verify_code_vm||verifier==(u_int)verify_code_ds) {
244 unsigned int page=source>>12;
245 unsigned int map_value=memory_map[page];
246 if(map_value>=0x80000000) return 0;
247 while(page<((source+len-1)>>12)) {
248 if((memory_map[++page]<<2)!=(map_value<<2)) return 0;
250 source = source+(map_value<<2);
252 //printf("verify_dirty: %x %x %x\n",source,copy,len);
253 return !memcmp((void *)source,(void *)copy,len);
256 // This doesn't necessarily find all clean entry points, just
257 // guarantees that it's not dirty
258 int isclean(int addr)
261 int *ptr=((u_int *)addr)+4;
263 int *ptr=((u_int *)addr)+6;
265 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
266 if((*ptr&0xFF000000)!=0xeb000000) return 1; // bl instruction
267 if((int)ptr+((*ptr<<8)>>6)+8==(int)verify_code) return 0;
268 if((int)ptr+((*ptr<<8)>>6)+8==(int)verify_code_vm) return 0;
269 if((int)ptr+((*ptr<<8)>>6)+8==(int)verify_code_ds) return 0;
273 void get_bounds(int addr,u_int *start,u_int *end)
275 u_int *ptr=(u_int *)addr;
277 // get from literal pool
278 assert((*ptr&0xFFF00000)==0xe5900000);
279 u_int offset=*ptr&0xfff;
280 u_int *l_ptr=(void *)ptr+offset+8;
281 u_int source=l_ptr[0];
282 //u_int copy=l_ptr[1];
287 assert((*ptr&0xFFF00000)==0xe3000000);
288 u_int source=(ptr[0]&0xFFF)+((ptr[0]>>4)&0xF000)+((ptr[2]<<16)&0xFFF0000)+((ptr[2]<<12)&0xF0000000);
289 //u_int copy=(ptr[1]&0xFFF)+((ptr[1]>>4)&0xF000)+((ptr[3]<<16)&0xFFF0000)+((ptr[3]<<12)&0xF0000000);
290 u_int len=(ptr[4]&0xFFF)+((ptr[4]>>4)&0xF000);
293 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
294 assert((*ptr&0xFF000000)==0xeb000000); // bl instruction
295 u_int verifier=(int)ptr+((signed int)(*ptr<<8)>>6)+8; // get target of bl
296 if(verifier==(u_int)verify_code_vm||verifier==(u_int)verify_code_ds) {
297 if(memory_map[source>>12]>=0x80000000) source = 0;
298 else source = source+(memory_map[source>>12]<<2);
304 /* Register allocation */
306 // Note: registers are allocated clean (unmodified state)
307 // if you intend to modify the register, you must call dirty_reg().
308 void alloc_reg(struct regstat *cur,int i,signed char reg)
311 int preferred_reg = (reg&7);
312 if(reg==CCREG) preferred_reg=HOST_CCREG;
313 if(reg==PTEMP||reg==FTEMP) preferred_reg=12;
315 // Don't allocate unused registers
316 if((cur->u>>reg)&1) return;
318 // see if it's already allocated
319 for(hr=0;hr<HOST_REGS;hr++)
321 if(cur->regmap[hr]==reg) return;
324 // Keep the same mapping if the register was already allocated in a loop
325 preferred_reg = loop_reg(i,reg,preferred_reg);
327 // Try to allocate the preferred register
328 if(cur->regmap[preferred_reg]==-1) {
329 cur->regmap[preferred_reg]=reg;
330 cur->dirty&=~(1<<preferred_reg);
331 cur->isconst&=~(1<<preferred_reg);
334 r=cur->regmap[preferred_reg];
335 if(r<64&&((cur->u>>r)&1)) {
336 cur->regmap[preferred_reg]=reg;
337 cur->dirty&=~(1<<preferred_reg);
338 cur->isconst&=~(1<<preferred_reg);
341 if(r>=64&&((cur->uu>>(r&63))&1)) {
342 cur->regmap[preferred_reg]=reg;
343 cur->dirty&=~(1<<preferred_reg);
344 cur->isconst&=~(1<<preferred_reg);
348 // Clear any unneeded registers
349 // We try to keep the mapping consistent, if possible, because it
350 // makes branches easier (especially loops). So we try to allocate
351 // first (see above) before removing old mappings. If this is not
352 // possible then go ahead and clear out the registers that are no
354 for(hr=0;hr<HOST_REGS;hr++)
359 if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
363 if((cur->uu>>(r&63))&1) {cur->regmap[hr]=-1;break;}
367 // Try to allocate any available register, but prefer
368 // registers that have not been used recently.
370 for(hr=0;hr<HOST_REGS;hr++) {
371 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
372 if(regs[i-1].regmap[hr]!=rs1[i-1]&®s[i-1].regmap[hr]!=rs2[i-1]&®s[i-1].regmap[hr]!=rt1[i-1]&®s[i-1].regmap[hr]!=rt2[i-1]) {
374 cur->dirty&=~(1<<hr);
375 cur->isconst&=~(1<<hr);
381 // Try to allocate any available register
382 for(hr=0;hr<HOST_REGS;hr++) {
383 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
385 cur->dirty&=~(1<<hr);
386 cur->isconst&=~(1<<hr);
391 // Ok, now we have to evict someone
392 // Pick a register we hopefully won't need soon
393 u_char hsn[MAXREG+1];
394 memset(hsn,10,sizeof(hsn));
396 lsn(hsn,i,&preferred_reg);
397 //printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",cur->regmap[0],cur->regmap[1],cur->regmap[2],cur->regmap[3],cur->regmap[5],cur->regmap[6],cur->regmap[7]);
398 //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
400 // Don't evict the cycle count at entry points, otherwise the entry
401 // stub will have to write it.
402 if(bt[i]&&hsn[CCREG]>2) hsn[CCREG]=2;
403 if(i>1&&hsn[CCREG]>2&&(itype[i-2]==RJUMP||itype[i-2]==UJUMP||itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP)) hsn[CCREG]=2;
406 // Alloc preferred register if available
407 if(hsn[r=cur->regmap[preferred_reg]&63]==j) {
408 for(hr=0;hr<HOST_REGS;hr++) {
409 // Evict both parts of a 64-bit register
410 if((cur->regmap[hr]&63)==r) {
412 cur->dirty&=~(1<<hr);
413 cur->isconst&=~(1<<hr);
416 cur->regmap[preferred_reg]=reg;
419 for(r=1;r<=MAXREG;r++)
421 if(hsn[r]==j&&r!=rs1[i-1]&&r!=rs2[i-1]&&r!=rt1[i-1]&&r!=rt2[i-1]) {
422 for(hr=0;hr<HOST_REGS;hr++) {
423 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
424 if(cur->regmap[hr]==r+64) {
426 cur->dirty&=~(1<<hr);
427 cur->isconst&=~(1<<hr);
432 for(hr=0;hr<HOST_REGS;hr++) {
433 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
434 if(cur->regmap[hr]==r) {
436 cur->dirty&=~(1<<hr);
437 cur->isconst&=~(1<<hr);
448 for(r=1;r<=MAXREG;r++)
451 for(hr=0;hr<HOST_REGS;hr++) {
452 if(cur->regmap[hr]==r+64) {
454 cur->dirty&=~(1<<hr);
455 cur->isconst&=~(1<<hr);
459 for(hr=0;hr<HOST_REGS;hr++) {
460 if(cur->regmap[hr]==r) {
462 cur->dirty&=~(1<<hr);
463 cur->isconst&=~(1<<hr);
470 printf("This shouldn't happen (alloc_reg)");exit(1);
473 void alloc_reg64(struct regstat *cur,int i,signed char reg)
475 int preferred_reg = 8+(reg&1);
478 // allocate the lower 32 bits
479 alloc_reg(cur,i,reg);
481 // Don't allocate unused registers
482 if((cur->uu>>reg)&1) return;
484 // see if the upper half is already allocated
485 for(hr=0;hr<HOST_REGS;hr++)
487 if(cur->regmap[hr]==reg+64) return;
490 // Keep the same mapping if the register was already allocated in a loop
491 preferred_reg = loop_reg(i,reg,preferred_reg);
493 // Try to allocate the preferred register
494 if(cur->regmap[preferred_reg]==-1) {
495 cur->regmap[preferred_reg]=reg|64;
496 cur->dirty&=~(1<<preferred_reg);
497 cur->isconst&=~(1<<preferred_reg);
500 r=cur->regmap[preferred_reg];
501 if(r<64&&((cur->u>>r)&1)) {
502 cur->regmap[preferred_reg]=reg|64;
503 cur->dirty&=~(1<<preferred_reg);
504 cur->isconst&=~(1<<preferred_reg);
507 if(r>=64&&((cur->uu>>(r&63))&1)) {
508 cur->regmap[preferred_reg]=reg|64;
509 cur->dirty&=~(1<<preferred_reg);
510 cur->isconst&=~(1<<preferred_reg);
514 // Clear any unneeded registers
515 // We try to keep the mapping consistent, if possible, because it
516 // makes branches easier (especially loops). So we try to allocate
517 // first (see above) before removing old mappings. If this is not
518 // possible then go ahead and clear out the registers that are no
520 for(hr=HOST_REGS-1;hr>=0;hr--)
525 if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
529 if((cur->uu>>(r&63))&1) {cur->regmap[hr]=-1;break;}
533 // Try to allocate any available register, but prefer
534 // registers that have not been used recently.
536 for(hr=0;hr<HOST_REGS;hr++) {
537 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
538 if(regs[i-1].regmap[hr]!=rs1[i-1]&®s[i-1].regmap[hr]!=rs2[i-1]&®s[i-1].regmap[hr]!=rt1[i-1]&®s[i-1].regmap[hr]!=rt2[i-1]) {
539 cur->regmap[hr]=reg|64;
540 cur->dirty&=~(1<<hr);
541 cur->isconst&=~(1<<hr);
547 // Try to allocate any available register
548 for(hr=0;hr<HOST_REGS;hr++) {
549 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
550 cur->regmap[hr]=reg|64;
551 cur->dirty&=~(1<<hr);
552 cur->isconst&=~(1<<hr);
557 // Ok, now we have to evict someone
558 // Pick a register we hopefully won't need soon
559 u_char hsn[MAXREG+1];
560 memset(hsn,10,sizeof(hsn));
562 lsn(hsn,i,&preferred_reg);
563 //printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",cur->regmap[0],cur->regmap[1],cur->regmap[2],cur->regmap[3],cur->regmap[5],cur->regmap[6],cur->regmap[7]);
564 //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
566 // Don't evict the cycle count at entry points, otherwise the entry
567 // stub will have to write it.
568 if(bt[i]&&hsn[CCREG]>2) hsn[CCREG]=2;
569 if(i>1&&hsn[CCREG]>2&&(itype[i-2]==RJUMP||itype[i-2]==UJUMP||itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP)) hsn[CCREG]=2;
572 // Alloc preferred register if available
573 if(hsn[r=cur->regmap[preferred_reg]&63]==j) {
574 for(hr=0;hr<HOST_REGS;hr++) {
575 // Evict both parts of a 64-bit register
576 if((cur->regmap[hr]&63)==r) {
578 cur->dirty&=~(1<<hr);
579 cur->isconst&=~(1<<hr);
582 cur->regmap[preferred_reg]=reg|64;
585 for(r=1;r<=MAXREG;r++)
587 if(hsn[r]==j&&r!=rs1[i-1]&&r!=rs2[i-1]&&r!=rt1[i-1]&&r!=rt2[i-1]) {
588 for(hr=0;hr<HOST_REGS;hr++) {
589 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
590 if(cur->regmap[hr]==r+64) {
591 cur->regmap[hr]=reg|64;
592 cur->dirty&=~(1<<hr);
593 cur->isconst&=~(1<<hr);
598 for(hr=0;hr<HOST_REGS;hr++) {
599 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
600 if(cur->regmap[hr]==r) {
601 cur->regmap[hr]=reg|64;
602 cur->dirty&=~(1<<hr);
603 cur->isconst&=~(1<<hr);
614 for(r=1;r<=MAXREG;r++)
617 for(hr=0;hr<HOST_REGS;hr++) {
618 if(cur->regmap[hr]==r+64) {
619 cur->regmap[hr]=reg|64;
620 cur->dirty&=~(1<<hr);
621 cur->isconst&=~(1<<hr);
625 for(hr=0;hr<HOST_REGS;hr++) {
626 if(cur->regmap[hr]==r) {
627 cur->regmap[hr]=reg|64;
628 cur->dirty&=~(1<<hr);
629 cur->isconst&=~(1<<hr);
636 printf("This shouldn't happen");exit(1);
639 // Allocate a temporary register. This is done without regard to
640 // dirty status or whether the register we request is on the unneeded list
641 // Note: This will only allocate one register, even if called multiple times
642 void alloc_reg_temp(struct regstat *cur,int i,signed char reg)
645 int preferred_reg = -1;
647 // see if it's already allocated
648 for(hr=0;hr<HOST_REGS;hr++)
650 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==reg) return;
653 // Try to allocate any available register
654 for(hr=HOST_REGS-1;hr>=0;hr--) {
655 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
657 cur->dirty&=~(1<<hr);
658 cur->isconst&=~(1<<hr);
663 // Find an unneeded register
664 for(hr=HOST_REGS-1;hr>=0;hr--)
670 if(i==0||((unneeded_reg[i-1]>>r)&1)) {
672 cur->dirty&=~(1<<hr);
673 cur->isconst&=~(1<<hr);
680 if((cur->uu>>(r&63))&1) {
681 if(i==0||((unneeded_reg_upper[i-1]>>(r&63))&1)) {
683 cur->dirty&=~(1<<hr);
684 cur->isconst&=~(1<<hr);
692 // Ok, now we have to evict someone
693 // Pick a register we hopefully won't need soon
694 // TODO: we might want to follow unconditional jumps here
695 // TODO: get rid of dupe code and make this into a function
696 u_char hsn[MAXREG+1];
697 memset(hsn,10,sizeof(hsn));
699 lsn(hsn,i,&preferred_reg);
700 //printf("hsn: %d %d %d %d %d %d %d\n",hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
702 // Don't evict the cycle count at entry points, otherwise the entry
703 // stub will have to write it.
704 if(bt[i]&&hsn[CCREG]>2) hsn[CCREG]=2;
705 if(i>1&&hsn[CCREG]>2&&(itype[i-2]==RJUMP||itype[i-2]==UJUMP||itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP)) hsn[CCREG]=2;
708 for(r=1;r<=MAXREG;r++)
710 if(hsn[r]==j&&r!=rs1[i-1]&&r!=rs2[i-1]&&r!=rt1[i-1]&&r!=rt2[i-1]) {
711 for(hr=0;hr<HOST_REGS;hr++) {
712 if(hr!=HOST_CCREG||hsn[CCREG]>2) {
713 if(cur->regmap[hr]==r+64) {
715 cur->dirty&=~(1<<hr);
716 cur->isconst&=~(1<<hr);
721 for(hr=0;hr<HOST_REGS;hr++) {
722 if(hr!=HOST_CCREG||hsn[CCREG]>2) {
723 if(cur->regmap[hr]==r) {
725 cur->dirty&=~(1<<hr);
726 cur->isconst&=~(1<<hr);
737 for(r=1;r<=MAXREG;r++)
740 for(hr=0;hr<HOST_REGS;hr++) {
741 if(cur->regmap[hr]==r+64) {
743 cur->dirty&=~(1<<hr);
744 cur->isconst&=~(1<<hr);
748 for(hr=0;hr<HOST_REGS;hr++) {
749 if(cur->regmap[hr]==r) {
751 cur->dirty&=~(1<<hr);
752 cur->isconst&=~(1<<hr);
759 printf("This shouldn't happen");exit(1);
761 // Allocate a specific ARM register.
762 void alloc_arm_reg(struct regstat *cur,int i,signed char reg,char hr)
766 // see if it's already allocated (and dealloc it)
767 for(n=0;n<HOST_REGS;n++)
769 if(n!=EXCLUDE_REG&&cur->regmap[n]==reg) {cur->regmap[n]=-1;}
773 cur->dirty&=~(1<<hr);
774 cur->isconst&=~(1<<hr);
777 // Alloc cycle count into dedicated register
778 alloc_cc(struct regstat *cur,int i)
780 alloc_arm_reg(cur,i,CCREG,HOST_CCREG);
788 char regname[16][4] = {
806 void output_byte(u_char byte)
810 void output_modrm(u_char mod,u_char rm,u_char ext)
815 u_char byte=(mod<<6)|(ext<<3)|rm;
818 void output_sib(u_char scale,u_char index,u_char base)
823 u_char byte=(scale<<6)|(index<<3)|base;
826 void output_w32(u_int word)
828 *((u_int *)out)=word;
831 u_int rd_rn_rm(u_int rd, u_int rn, u_int rm)
836 return((rn<<16)|(rd<<12)|rm);
838 u_int rd_rn_imm_shift(u_int rd, u_int rn, u_int imm, u_int shift)
843 assert((shift&1)==0);
844 return((rn<<16)|(rd<<12)|(((32-shift)&30)<<7)|imm);
846 u_int genimm(u_int imm,u_int *encoded)
848 if(imm==0) {*encoded=0;return 1;}
853 *encoded=((i&30)<<7)|imm;
856 imm=(imm>>2)|(imm<<30);i-=2;
860 void genimm_checked(u_int imm,u_int *encoded)
862 u_int ret=genimm(imm,encoded);
865 u_int genjmp(u_int addr)
867 int offset=addr-(int)out-8;
868 if(offset<-33554432||offset>=33554432) {
870 printf("genjmp: out of range: %08x\n", offset);
875 return ((u_int)offset>>2)&0xffffff;
878 void emit_mov(int rs,int rt)
880 assem_debug("mov %s,%s\n",regname[rt],regname[rs]);
881 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs));
884 void emit_movs(int rs,int rt)
886 assem_debug("movs %s,%s\n",regname[rt],regname[rs]);
887 output_w32(0xe1b00000|rd_rn_rm(rt,0,rs));
890 void emit_add(int rs1,int rs2,int rt)
892 assem_debug("add %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
893 output_w32(0xe0800000|rd_rn_rm(rt,rs1,rs2));
896 void emit_adds(int rs1,int rs2,int rt)
898 assem_debug("adds %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
899 output_w32(0xe0900000|rd_rn_rm(rt,rs1,rs2));
902 void emit_adcs(int rs1,int rs2,int rt)
904 assem_debug("adcs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
905 output_w32(0xe0b00000|rd_rn_rm(rt,rs1,rs2));
908 void emit_sbc(int rs1,int rs2,int rt)
910 assem_debug("sbc %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
911 output_w32(0xe0c00000|rd_rn_rm(rt,rs1,rs2));
914 void emit_sbcs(int rs1,int rs2,int rt)
916 assem_debug("sbcs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
917 output_w32(0xe0d00000|rd_rn_rm(rt,rs1,rs2));
920 void emit_neg(int rs, int rt)
922 assem_debug("rsb %s,%s,#0\n",regname[rt],regname[rs]);
923 output_w32(0xe2600000|rd_rn_rm(rt,rs,0));
926 void emit_negs(int rs, int rt)
928 assem_debug("rsbs %s,%s,#0\n",regname[rt],regname[rs]);
929 output_w32(0xe2700000|rd_rn_rm(rt,rs,0));
932 void emit_sub(int rs1,int rs2,int rt)
934 assem_debug("sub %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
935 output_w32(0xe0400000|rd_rn_rm(rt,rs1,rs2));
938 void emit_subs(int rs1,int rs2,int rt)
940 assem_debug("subs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
941 output_w32(0xe0500000|rd_rn_rm(rt,rs1,rs2));
944 void emit_zeroreg(int rt)
946 assem_debug("mov %s,#0\n",regname[rt]);
947 output_w32(0xe3a00000|rd_rn_rm(rt,0,0));
950 void emit_loadlp(u_int imm,u_int rt)
952 add_literal((int)out,imm);
953 assem_debug("ldr %s,pc+? [=%x]\n",regname[rt],imm);
954 output_w32(0xe5900000|rd_rn_rm(rt,15,0));
956 void emit_movw(u_int imm,u_int rt)
959 assem_debug("movw %s,#%d (0x%x)\n",regname[rt],imm,imm);
960 output_w32(0xe3000000|rd_rn_rm(rt,0,0)|(imm&0xfff)|((imm<<4)&0xf0000));
962 void emit_movt(u_int imm,u_int rt)
964 assem_debug("movt %s,#%d (0x%x)\n",regname[rt],imm&0xffff0000,imm&0xffff0000);
965 output_w32(0xe3400000|rd_rn_rm(rt,0,0)|((imm>>16)&0xfff)|((imm>>12)&0xf0000));
967 void emit_movimm(u_int imm,u_int rt)
970 if(genimm(imm,&armval)) {
971 assem_debug("mov %s,#%d\n",regname[rt],imm);
972 output_w32(0xe3a00000|rd_rn_rm(rt,0,0)|armval);
973 }else if(genimm(~imm,&armval)) {
974 assem_debug("mvn %s,#%d\n",regname[rt],imm);
975 output_w32(0xe3e00000|rd_rn_rm(rt,0,0)|armval);
976 }else if(imm<65536) {
978 assem_debug("mov %s,#%d\n",regname[rt],imm&0xFF00);
979 output_w32(0xe3a00000|rd_rn_imm_shift(rt,0,imm>>8,8));
980 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF);
981 output_w32(0xe2800000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
989 emit_movw(imm&0x0000FFFF,rt);
990 emit_movt(imm&0xFFFF0000,rt);
994 void emit_pcreladdr(u_int rt)
996 assem_debug("add %s,pc,#?\n",regname[rt]);
997 output_w32(0xe2800000|rd_rn_rm(rt,15,0));
1000 void emit_loadreg(int r, int hr)
1004 printf("64bit load in 32bit mode!\n");
1011 int addr=((int)reg)+((r&63)<<REG_SHIFT)+((r&64)>>4);
1012 if((r&63)==HIREG) addr=(int)&hi+((r&64)>>4);
1013 if((r&63)==LOREG) addr=(int)&lo+((r&64)>>4);
1014 if(r==CCREG) addr=(int)&cycle_count;
1015 if(r==CSREG) addr=(int)&Status;
1016 if(r==FSREG) addr=(int)&FCR31;
1017 if(r==INVCP) addr=(int)&invc_ptr;
1018 u_int offset = addr-(u_int)&dynarec_local;
1019 assert(offset<4096);
1020 assem_debug("ldr %s,fp+%d\n",regname[hr],offset);
1021 output_w32(0xe5900000|rd_rn_rm(hr,FP,0)|offset);
1024 void emit_storereg(int r, int hr)
1028 printf("64bit store in 32bit mode!\n");
1032 int addr=((int)reg)+((r&63)<<REG_SHIFT)+((r&64)>>4);
1033 if((r&63)==HIREG) addr=(int)&hi+((r&64)>>4);
1034 if((r&63)==LOREG) addr=(int)&lo+((r&64)>>4);
1035 if(r==CCREG) addr=(int)&cycle_count;
1036 if(r==FSREG) addr=(int)&FCR31;
1037 u_int offset = addr-(u_int)&dynarec_local;
1038 assert(offset<4096);
1039 assem_debug("str %s,fp+%d\n",regname[hr],offset);
1040 output_w32(0xe5800000|rd_rn_rm(hr,FP,0)|offset);
1043 void emit_test(int rs, int rt)
1045 assem_debug("tst %s,%s\n",regname[rs],regname[rt]);
1046 output_w32(0xe1100000|rd_rn_rm(0,rs,rt));
1049 void emit_testimm(int rs,int imm)
1052 assem_debug("tst %s,$%d\n",regname[rs],imm);
1053 genimm_checked(imm,&armval);
1054 output_w32(0xe3100000|rd_rn_rm(0,rs,0)|armval);
1057 void emit_testeqimm(int rs,int imm)
1060 assem_debug("tsteq %s,$%d\n",regname[rs],imm);
1061 genimm_checked(imm,&armval);
1062 output_w32(0x03100000|rd_rn_rm(0,rs,0)|armval);
1065 void emit_not(int rs,int rt)
1067 assem_debug("mvn %s,%s\n",regname[rt],regname[rs]);
1068 output_w32(0xe1e00000|rd_rn_rm(rt,0,rs));
1071 void emit_mvnmi(int rs,int rt)
1073 assem_debug("mvnmi %s,%s\n",regname[rt],regname[rs]);
1074 output_w32(0x41e00000|rd_rn_rm(rt,0,rs));
1077 void emit_and(u_int rs1,u_int rs2,u_int rt)
1079 assem_debug("and %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1080 output_w32(0xe0000000|rd_rn_rm(rt,rs1,rs2));
1083 void emit_or(u_int rs1,u_int rs2,u_int rt)
1085 assem_debug("orr %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1086 output_w32(0xe1800000|rd_rn_rm(rt,rs1,rs2));
1088 void emit_or_and_set_flags(int rs1,int rs2,int rt)
1090 assem_debug("orrs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1091 output_w32(0xe1900000|rd_rn_rm(rt,rs1,rs2));
1094 void emit_orrshl_imm(u_int rs,u_int imm,u_int rt)
1099 assem_debug("orr %s,%s,%s,lsl #%d\n",regname[rt],regname[rt],regname[rs],imm);
1100 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs)|(imm<<7));
1103 void emit_orrshr_imm(u_int rs,u_int imm,u_int rt)
1108 assem_debug("orr %s,%s,%s,lsr #%d\n",regname[rt],regname[rt],regname[rs],imm);
1109 output_w32(0xe1800020|rd_rn_rm(rt,rt,rs)|(imm<<7));
1112 void emit_xor(u_int rs1,u_int rs2,u_int rt)
1114 assem_debug("eor %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1115 output_w32(0xe0200000|rd_rn_rm(rt,rs1,rs2));
1118 void emit_addimm(u_int rs,int imm,u_int rt)
1123 assert(imm>-65536&&imm<65536);
1125 if(genimm(imm,&armval)) {
1126 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rs],imm);
1127 output_w32(0xe2800000|rd_rn_rm(rt,rs,0)|armval);
1128 }else if(genimm(-imm,&armval)) {
1129 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rs],imm);
1130 output_w32(0xe2400000|rd_rn_rm(rt,rs,0)|armval);
1132 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rs],(-imm)&0xFF00);
1133 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rt],(-imm)&0xFF);
1134 output_w32(0xe2400000|rd_rn_imm_shift(rt,rs,(-imm)>>8,8));
1135 output_w32(0xe2400000|rd_rn_imm_shift(rt,rt,(-imm)&0xff,0));
1137 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF00);
1138 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF);
1139 output_w32(0xe2800000|rd_rn_imm_shift(rt,rs,imm>>8,8));
1140 output_w32(0xe2800000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1143 else if(rs!=rt) emit_mov(rs,rt);
1146 void emit_addimm_and_set_flags(int imm,int rt)
1148 assert(imm>-65536&&imm<65536);
1150 if(genimm(imm,&armval)) {
1151 assem_debug("adds %s,%s,#%d\n",regname[rt],regname[rt],imm);
1152 output_w32(0xe2900000|rd_rn_rm(rt,rt,0)|armval);
1153 }else if(genimm(-imm,&armval)) {
1154 assem_debug("subs %s,%s,#%d\n",regname[rt],regname[rt],imm);
1155 output_w32(0xe2500000|rd_rn_rm(rt,rt,0)|armval);
1157 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rt],(-imm)&0xFF00);
1158 assem_debug("subs %s,%s,#%d\n",regname[rt],regname[rt],(-imm)&0xFF);
1159 output_w32(0xe2400000|rd_rn_imm_shift(rt,rt,(-imm)>>8,8));
1160 output_w32(0xe2500000|rd_rn_imm_shift(rt,rt,(-imm)&0xff,0));
1162 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF00);
1163 assem_debug("adds %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF);
1164 output_w32(0xe2800000|rd_rn_imm_shift(rt,rt,imm>>8,8));
1165 output_w32(0xe2900000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1168 void emit_addimm_no_flags(u_int imm,u_int rt)
1170 emit_addimm(rt,imm,rt);
1173 void emit_addnop(u_int r)
1176 assem_debug("add %s,%s,#0 (nop)\n",regname[r],regname[r]);
1177 output_w32(0xe2800000|rd_rn_rm(r,r,0));
1180 void emit_adcimm(u_int rs,int imm,u_int rt)
1183 genimm_checked(imm,&armval);
1184 assem_debug("adc %s,%s,#%d\n",regname[rt],regname[rs],imm);
1185 output_w32(0xe2a00000|rd_rn_rm(rt,rs,0)|armval);
1187 /*void emit_sbcimm(int imm,u_int rt)
1190 genimm_checked(imm,&armval);
1191 assem_debug("sbc %s,%s,#%d\n",regname[rt],regname[rt],imm);
1192 output_w32(0xe2c00000|rd_rn_rm(rt,rt,0)|armval);
1194 void emit_sbbimm(int imm,u_int rt)
1196 assem_debug("sbb $%d,%%%s\n",imm,regname[rt]);
1198 if(imm<128&&imm>=-128) {
1200 output_modrm(3,rt,3);
1206 output_modrm(3,rt,3);
1210 void emit_rscimm(int rs,int imm,u_int rt)
1214 genimm_checked(imm,&armval);
1215 assem_debug("rsc %s,%s,#%d\n",regname[rt],regname[rs],imm);
1216 output_w32(0xe2e00000|rd_rn_rm(rt,rs,0)|armval);
1219 void emit_addimm64_32(int rsh,int rsl,int imm,int rth,int rtl)
1221 // TODO: if(genimm(imm,&armval)) ...
1223 emit_movimm(imm,HOST_TEMPREG);
1224 emit_adds(HOST_TEMPREG,rsl,rtl);
1225 emit_adcimm(rsh,0,rth);
1228 void emit_sbb(int rs1,int rs2)
1230 assem_debug("sbb %%%s,%%%s\n",regname[rs2],regname[rs1]);
1232 output_modrm(3,rs1,rs2);
1235 void emit_andimm(int rs,int imm,int rt)
1240 }else if(genimm(imm,&armval)) {
1241 assem_debug("and %s,%s,#%d\n",regname[rt],regname[rs],imm);
1242 output_w32(0xe2000000|rd_rn_rm(rt,rs,0)|armval);
1243 }else if(genimm(~imm,&armval)) {
1244 assem_debug("bic %s,%s,#%d\n",regname[rt],regname[rs],imm);
1245 output_w32(0xe3c00000|rd_rn_rm(rt,rs,0)|armval);
1246 }else if(imm==65535) {
1248 assem_debug("bic %s,%s,#FF000000\n",regname[rt],regname[rs]);
1249 output_w32(0xe3c00000|rd_rn_rm(rt,rs,0)|0x4FF);
1250 assem_debug("bic %s,%s,#00FF0000\n",regname[rt],regname[rt]);
1251 output_w32(0xe3c00000|rd_rn_rm(rt,rt,0)|0x8FF);
1253 assem_debug("uxth %s,%s\n",regname[rt],regname[rs]);
1254 output_w32(0xe6ff0070|rd_rn_rm(rt,0,rs));
1257 assert(imm>0&&imm<65535);
1259 assem_debug("mov r14,#%d\n",imm&0xFF00);
1260 output_w32(0xe3a00000|rd_rn_imm_shift(HOST_TEMPREG,0,imm>>8,8));
1261 assem_debug("add r14,r14,#%d\n",imm&0xFF);
1262 output_w32(0xe2800000|rd_rn_imm_shift(HOST_TEMPREG,HOST_TEMPREG,imm&0xff,0));
1264 emit_movw(imm,HOST_TEMPREG);
1266 assem_debug("and %s,%s,r14\n",regname[rt],regname[rs]);
1267 output_w32(0xe0000000|rd_rn_rm(rt,rs,HOST_TEMPREG));
1271 void emit_orimm(int rs,int imm,int rt)
1275 if(rs!=rt) emit_mov(rs,rt);
1276 }else if(genimm(imm,&armval)) {
1277 assem_debug("orr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1278 output_w32(0xe3800000|rd_rn_rm(rt,rs,0)|armval);
1280 assert(imm>0&&imm<65536);
1281 assem_debug("orr %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF00);
1282 assem_debug("orr %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF);
1283 output_w32(0xe3800000|rd_rn_imm_shift(rt,rs,imm>>8,8));
1284 output_w32(0xe3800000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1288 void emit_xorimm(int rs,int imm,int rt)
1292 if(rs!=rt) emit_mov(rs,rt);
1293 }else if(genimm(imm,&armval)) {
1294 assem_debug("eor %s,%s,#%d\n",regname[rt],regname[rs],imm);
1295 output_w32(0xe2200000|rd_rn_rm(rt,rs,0)|armval);
1297 assert(imm>0&&imm<65536);
1298 assem_debug("eor %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF00);
1299 assem_debug("eor %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF);
1300 output_w32(0xe2200000|rd_rn_imm_shift(rt,rs,imm>>8,8));
1301 output_w32(0xe2200000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1305 void emit_shlimm(int rs,u_int imm,int rt)
1310 assem_debug("lsl %s,%s,#%d\n",regname[rt],regname[rs],imm);
1311 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|(imm<<7));
1314 void emit_shrimm(int rs,u_int imm,int rt)
1318 assem_debug("lsr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1319 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x20|(imm<<7));
1322 void emit_sarimm(int rs,u_int imm,int rt)
1326 assem_debug("asr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1327 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x40|(imm<<7));
1330 void emit_rorimm(int rs,u_int imm,int rt)
1334 assem_debug("ror %s,%s,#%d\n",regname[rt],regname[rs],imm);
1335 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x60|(imm<<7));
1338 void emit_shldimm(int rs,int rs2,u_int imm,int rt)
1340 assem_debug("shld %%%s,%%%s,%d\n",regname[rt],regname[rs2],imm);
1344 assem_debug("lsl %s,%s,#%d\n",regname[rt],regname[rs],imm);
1345 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|(imm<<7));
1346 assem_debug("orr %s,%s,%s,lsr #%d\n",regname[rt],regname[rt],regname[rs2],32-imm);
1347 output_w32(0xe1800020|rd_rn_rm(rt,rt,rs2)|((32-imm)<<7));
1350 void emit_shrdimm(int rs,int rs2,u_int imm,int rt)
1352 assem_debug("shrd %%%s,%%%s,%d\n",regname[rt],regname[rs2],imm);
1356 assem_debug("lsr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1357 output_w32(0xe1a00020|rd_rn_rm(rt,0,rs)|(imm<<7));
1358 assem_debug("orr %s,%s,%s,lsl #%d\n",regname[rt],regname[rt],regname[rs2],32-imm);
1359 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs2)|((32-imm)<<7));
1362 void emit_signextend16(int rs,int rt)
1365 emit_shlimm(rs,16,rt);
1366 emit_sarimm(rt,16,rt);
1368 assem_debug("sxth %s,%s\n",regname[rt],regname[rs]);
1369 output_w32(0xe6bf0070|rd_rn_rm(rt,0,rs));
1373 void emit_shl(u_int rs,u_int shift,u_int rt)
1379 assem_debug("lsl %s,%s,%s\n",regname[rt],regname[rs],regname[shift]);
1380 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x10|(shift<<8));
1382 void emit_shr(u_int rs,u_int shift,u_int rt)
1387 assem_debug("lsr %s,%s,%s\n",regname[rt],regname[rs],regname[shift]);
1388 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x30|(shift<<8));
1390 void emit_sar(u_int rs,u_int shift,u_int rt)
1395 assem_debug("asr %s,%s,%s\n",regname[rt],regname[rs],regname[shift]);
1396 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x50|(shift<<8));
1398 void emit_shlcl(int r)
1400 assem_debug("shl %%%s,%%cl\n",regname[r]);
1403 void emit_shrcl(int r)
1405 assem_debug("shr %%%s,%%cl\n",regname[r]);
1408 void emit_sarcl(int r)
1410 assem_debug("sar %%%s,%%cl\n",regname[r]);
1414 void emit_shldcl(int r1,int r2)
1416 assem_debug("shld %%%s,%%%s,%%cl\n",regname[r1],regname[r2]);
1419 void emit_shrdcl(int r1,int r2)
1421 assem_debug("shrd %%%s,%%%s,%%cl\n",regname[r1],regname[r2]);
1424 void emit_orrshl(u_int rs,u_int shift,u_int rt)
1429 assem_debug("orr %s,%s,%s,lsl %s\n",regname[rt],regname[rt],regname[rs],regname[shift]);
1430 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs)|0x10|(shift<<8));
1432 void emit_orrshr(u_int rs,u_int shift,u_int rt)
1437 assem_debug("orr %s,%s,%s,lsr %s\n",regname[rt],regname[rt],regname[rs],regname[shift]);
1438 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs)|0x30|(shift<<8));
1441 void emit_cmpimm(int rs,int imm)
1444 if(genimm(imm,&armval)) {
1445 assem_debug("cmp %s,$%d\n",regname[rs],imm);
1446 output_w32(0xe3500000|rd_rn_rm(0,rs,0)|armval);
1447 }else if(genimm(-imm,&armval)) {
1448 assem_debug("cmn %s,$%d\n",regname[rs],imm);
1449 output_w32(0xe3700000|rd_rn_rm(0,rs,0)|armval);
1453 emit_movimm(imm,HOST_TEMPREG);
1455 emit_movw(imm,HOST_TEMPREG);
1457 assem_debug("cmp %s,r14\n",regname[rs]);
1458 output_w32(0xe1500000|rd_rn_rm(0,rs,HOST_TEMPREG));
1462 emit_movimm(-imm,HOST_TEMPREG);
1464 emit_movw(-imm,HOST_TEMPREG);
1466 assem_debug("cmn %s,r14\n",regname[rs]);
1467 output_w32(0xe1700000|rd_rn_rm(0,rs,HOST_TEMPREG));
1471 void emit_cmovne(u_int *addr,int rt)
1473 assem_debug("cmovne %x,%%%s",(int)addr,regname[rt]);
1476 void emit_cmovl(u_int *addr,int rt)
1478 assem_debug("cmovl %x,%%%s",(int)addr,regname[rt]);
1481 void emit_cmovs(u_int *addr,int rt)
1483 assem_debug("cmovs %x,%%%s",(int)addr,regname[rt]);
1486 void emit_cmovne_imm(int imm,int rt)
1488 assem_debug("movne %s,#%d\n",regname[rt],imm);
1490 genimm_checked(imm,&armval);
1491 output_w32(0x13a00000|rd_rn_rm(rt,0,0)|armval);
1493 void emit_cmovl_imm(int imm,int rt)
1495 assem_debug("movlt %s,#%d\n",regname[rt],imm);
1497 genimm_checked(imm,&armval);
1498 output_w32(0xb3a00000|rd_rn_rm(rt,0,0)|armval);
1500 void emit_cmovb_imm(int imm,int rt)
1502 assem_debug("movcc %s,#%d\n",regname[rt],imm);
1504 genimm_checked(imm,&armval);
1505 output_w32(0x33a00000|rd_rn_rm(rt,0,0)|armval);
1507 void emit_cmovs_imm(int imm,int rt)
1509 assem_debug("movmi %s,#%d\n",regname[rt],imm);
1511 genimm_checked(imm,&armval);
1512 output_w32(0x43a00000|rd_rn_rm(rt,0,0)|armval);
1514 void emit_cmove_reg(int rs,int rt)
1516 assem_debug("moveq %s,%s\n",regname[rt],regname[rs]);
1517 output_w32(0x01a00000|rd_rn_rm(rt,0,rs));
1519 void emit_cmovne_reg(int rs,int rt)
1521 assem_debug("movne %s,%s\n",regname[rt],regname[rs]);
1522 output_w32(0x11a00000|rd_rn_rm(rt,0,rs));
1524 void emit_cmovl_reg(int rs,int rt)
1526 assem_debug("movlt %s,%s\n",regname[rt],regname[rs]);
1527 output_w32(0xb1a00000|rd_rn_rm(rt,0,rs));
1529 void emit_cmovs_reg(int rs,int rt)
1531 assem_debug("movmi %s,%s\n",regname[rt],regname[rs]);
1532 output_w32(0x41a00000|rd_rn_rm(rt,0,rs));
1535 void emit_slti32(int rs,int imm,int rt)
1537 if(rs!=rt) emit_zeroreg(rt);
1538 emit_cmpimm(rs,imm);
1539 if(rs==rt) emit_movimm(0,rt);
1540 emit_cmovl_imm(1,rt);
1542 void emit_sltiu32(int rs,int imm,int rt)
1544 if(rs!=rt) emit_zeroreg(rt);
1545 emit_cmpimm(rs,imm);
1546 if(rs==rt) emit_movimm(0,rt);
1547 emit_cmovb_imm(1,rt);
1549 void emit_slti64_32(int rsh,int rsl,int imm,int rt)
1552 emit_slti32(rsl,imm,rt);
1556 emit_cmovne_imm(0,rt);
1557 emit_cmovs_imm(1,rt);
1561 emit_cmpimm(rsh,-1);
1562 emit_cmovne_imm(0,rt);
1563 emit_cmovl_imm(1,rt);
1566 void emit_sltiu64_32(int rsh,int rsl,int imm,int rt)
1569 emit_sltiu32(rsl,imm,rt);
1573 emit_cmovne_imm(0,rt);
1577 emit_cmpimm(rsh,-1);
1578 emit_cmovne_imm(1,rt);
1582 void emit_cmp(int rs,int rt)
1584 assem_debug("cmp %s,%s\n",regname[rs],regname[rt]);
1585 output_w32(0xe1500000|rd_rn_rm(0,rs,rt));
1587 void emit_set_gz32(int rs, int rt)
1589 //assem_debug("set_gz32\n");
1592 emit_cmovl_imm(0,rt);
1594 void emit_set_nz32(int rs, int rt)
1596 //assem_debug("set_nz32\n");
1597 if(rs!=rt) emit_movs(rs,rt);
1598 else emit_test(rs,rs);
1599 emit_cmovne_imm(1,rt);
1601 void emit_set_gz64_32(int rsh, int rsl, int rt)
1603 //assem_debug("set_gz64\n");
1604 emit_set_gz32(rsl,rt);
1606 emit_cmovne_imm(1,rt);
1607 emit_cmovs_imm(0,rt);
1609 void emit_set_nz64_32(int rsh, int rsl, int rt)
1611 //assem_debug("set_nz64\n");
1612 emit_or_and_set_flags(rsh,rsl,rt);
1613 emit_cmovne_imm(1,rt);
1615 void emit_set_if_less32(int rs1, int rs2, int rt)
1617 //assem_debug("set if less (%%%s,%%%s),%%%s\n",regname[rs1],regname[rs2],regname[rt]);
1618 if(rs1!=rt&&rs2!=rt) emit_zeroreg(rt);
1620 if(rs1==rt||rs2==rt) emit_movimm(0,rt);
1621 emit_cmovl_imm(1,rt);
1623 void emit_set_if_carry32(int rs1, int rs2, int rt)
1625 //assem_debug("set if carry (%%%s,%%%s),%%%s\n",regname[rs1],regname[rs2],regname[rt]);
1626 if(rs1!=rt&&rs2!=rt) emit_zeroreg(rt);
1628 if(rs1==rt||rs2==rt) emit_movimm(0,rt);
1629 emit_cmovb_imm(1,rt);
1631 void emit_set_if_less64_32(int u1, int l1, int u2, int l2, int rt)
1633 //assem_debug("set if less64 (%%%s,%%%s,%%%s,%%%s),%%%s\n",regname[u1],regname[l1],regname[u2],regname[l2],regname[rt]);
1638 emit_sbcs(u1,u2,HOST_TEMPREG);
1639 emit_cmovl_imm(1,rt);
1641 void emit_set_if_carry64_32(int u1, int l1, int u2, int l2, int rt)
1643 //assem_debug("set if carry64 (%%%s,%%%s,%%%s,%%%s),%%%s\n",regname[u1],regname[l1],regname[u2],regname[l2],regname[rt]);
1648 emit_sbcs(u1,u2,HOST_TEMPREG);
1649 emit_cmovb_imm(1,rt);
1652 void emit_call(int a)
1654 assem_debug("bl %x (%x+%x)\n",a,(int)out,a-(int)out-8);
1655 u_int offset=genjmp(a);
1656 output_w32(0xeb000000|offset);
1658 void emit_jmp(int a)
1660 assem_debug("b %x (%x+%x)\n",a,(int)out,a-(int)out-8);
1661 u_int offset=genjmp(a);
1662 output_w32(0xea000000|offset);
1664 void emit_jne(int a)
1666 assem_debug("bne %x\n",a);
1667 u_int offset=genjmp(a);
1668 output_w32(0x1a000000|offset);
1670 void emit_jeq(int a)
1672 assem_debug("beq %x\n",a);
1673 u_int offset=genjmp(a);
1674 output_w32(0x0a000000|offset);
1678 assem_debug("bmi %x\n",a);
1679 u_int offset=genjmp(a);
1680 output_w32(0x4a000000|offset);
1682 void emit_jns(int a)
1684 assem_debug("bpl %x\n",a);
1685 u_int offset=genjmp(a);
1686 output_w32(0x5a000000|offset);
1690 assem_debug("blt %x\n",a);
1691 u_int offset=genjmp(a);
1692 output_w32(0xba000000|offset);
1694 void emit_jge(int a)
1696 assem_debug("bge %x\n",a);
1697 u_int offset=genjmp(a);
1698 output_w32(0xaa000000|offset);
1700 void emit_jno(int a)
1702 assem_debug("bvc %x\n",a);
1703 u_int offset=genjmp(a);
1704 output_w32(0x7a000000|offset);
1708 assem_debug("bcs %x\n",a);
1709 u_int offset=genjmp(a);
1710 output_w32(0x2a000000|offset);
1712 void emit_jcc(int a)
1714 assem_debug("bcc %x\n",a);
1715 u_int offset=genjmp(a);
1716 output_w32(0x3a000000|offset);
1719 void emit_pushimm(int imm)
1721 assem_debug("push $%x\n",imm);
1726 assem_debug("pusha\n");
1731 assem_debug("popa\n");
1734 void emit_pushreg(u_int r)
1736 assem_debug("push %%%s\n",regname[r]);
1739 void emit_popreg(u_int r)
1741 assem_debug("pop %%%s\n",regname[r]);
1744 void emit_callreg(u_int r)
1746 assem_debug("call *%%%s\n",regname[r]);
1749 void emit_jmpreg(u_int r)
1751 assem_debug("mov pc,%s\n",regname[r]);
1752 output_w32(0xe1a00000|rd_rn_rm(15,0,r));
1755 void emit_readword_indexed(int offset, int rs, int rt)
1757 assert(offset>-4096&&offset<4096);
1758 assem_debug("ldr %s,%s+%d\n",regname[rt],regname[rs],offset);
1760 output_w32(0xe5900000|rd_rn_rm(rt,rs,0)|offset);
1762 output_w32(0xe5100000|rd_rn_rm(rt,rs,0)|(-offset));
1765 void emit_readword_dualindexedx4(int rs1, int rs2, int rt)
1767 assem_debug("ldr %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
1768 output_w32(0xe7900000|rd_rn_rm(rt,rs1,rs2)|0x100);
1770 void emit_readword_indexed_tlb(int addr, int rs, int map, int rt)
1772 if(map<0) emit_readword_indexed(addr, rs, rt);
1775 emit_readword_dualindexedx4(rs, map, rt);
1778 void emit_readdword_indexed_tlb(int addr, int rs, int map, int rh, int rl)
1781 if(rh>=0) emit_readword_indexed(addr, rs, rh);
1782 emit_readword_indexed(addr+4, rs, rl);
1785 if(rh>=0) emit_readword_indexed_tlb(addr, rs, map, rh);
1786 emit_addimm(map,1,map);
1787 emit_readword_indexed_tlb(addr, rs, map, rl);
1790 void emit_movsbl_indexed(int offset, int rs, int rt)
1792 assert(offset>-256&&offset<256);
1793 assem_debug("ldrsb %s,%s+%d\n",regname[rt],regname[rs],offset);
1795 output_w32(0xe1d000d0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1797 output_w32(0xe15000d0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1800 void emit_movsbl_indexed_tlb(int addr, int rs, int map, int rt)
1802 if(map<0) emit_movsbl_indexed(addr, rs, rt);
1805 emit_shlimm(map,2,map);
1806 assem_debug("ldrsb %s,%s+%s\n",regname[rt],regname[rs],regname[map]);
1807 output_w32(0xe19000d0|rd_rn_rm(rt,rs,map));
1809 assert(addr>-256&&addr<256);
1810 assem_debug("add %s,%s,%s,lsl #2\n",regname[rt],regname[rs],regname[map]);
1811 output_w32(0xe0800000|rd_rn_rm(rt,rs,map)|(2<<7));
1812 emit_movsbl_indexed(addr, rt, rt);
1816 void emit_movswl_indexed(int offset, int rs, int rt)
1818 assert(offset>-256&&offset<256);
1819 assem_debug("ldrsh %s,%s+%d\n",regname[rt],regname[rs],offset);
1821 output_w32(0xe1d000f0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1823 output_w32(0xe15000f0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1826 void emit_movzbl_indexed(int offset, int rs, int rt)
1828 assert(offset>-4096&&offset<4096);
1829 assem_debug("ldrb %s,%s+%d\n",regname[rt],regname[rs],offset);
1831 output_w32(0xe5d00000|rd_rn_rm(rt,rs,0)|offset);
1833 output_w32(0xe5500000|rd_rn_rm(rt,rs,0)|(-offset));
1836 void emit_movzbl_dualindexedx4(int rs1, int rs2, int rt)
1838 assem_debug("ldrb %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
1839 output_w32(0xe7d00000|rd_rn_rm(rt,rs1,rs2)|0x100);
1841 void emit_movzbl_indexed_tlb(int addr, int rs, int map, int rt)
1843 if(map<0) emit_movzbl_indexed(addr, rs, rt);
1846 emit_movzbl_dualindexedx4(rs, map, rt);
1848 emit_addimm(rs,addr,rt);
1849 emit_movzbl_dualindexedx4(rt, map, rt);
1853 void emit_movzwl_indexed(int offset, int rs, int rt)
1855 assert(offset>-256&&offset<256);
1856 assem_debug("ldrh %s,%s+%d\n",regname[rt],regname[rs],offset);
1858 output_w32(0xe1d000b0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1860 output_w32(0xe15000b0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1863 void emit_readword(int addr, int rt)
1865 u_int offset = addr-(u_int)&dynarec_local;
1866 assert(offset<4096);
1867 assem_debug("ldr %s,fp+%d\n",regname[rt],offset);
1868 output_w32(0xe5900000|rd_rn_rm(rt,FP,0)|offset);
1870 void emit_movsbl(int addr, int rt)
1872 u_int offset = addr-(u_int)&dynarec_local;
1874 assem_debug("ldrsb %s,fp+%d\n",regname[rt],offset);
1875 output_w32(0xe1d000d0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
1877 void emit_movswl(int addr, int rt)
1879 u_int offset = addr-(u_int)&dynarec_local;
1881 assem_debug("ldrsh %s,fp+%d\n",regname[rt],offset);
1882 output_w32(0xe1d000f0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
1884 void emit_movzbl(int addr, int rt)
1886 u_int offset = addr-(u_int)&dynarec_local;
1887 assert(offset<4096);
1888 assem_debug("ldrb %s,fp+%d\n",regname[rt],offset);
1889 output_w32(0xe5d00000|rd_rn_rm(rt,FP,0)|offset);
1891 void emit_movzwl(int addr, int rt)
1893 u_int offset = addr-(u_int)&dynarec_local;
1895 assem_debug("ldrh %s,fp+%d\n",regname[rt],offset);
1896 output_w32(0xe1d000b0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
1898 void emit_movzwl_reg(int rs, int rt)
1900 assem_debug("movzwl %%%s,%%%s\n",regname[rs]+1,regname[rt]);
1904 void emit_xchg(int rs, int rt)
1906 assem_debug("xchg %%%s,%%%s\n",regname[rs],regname[rt]);
1909 void emit_writeword_indexed(int rt, int offset, int rs)
1911 assert(offset>-4096&&offset<4096);
1912 assem_debug("str %s,%s+%d\n",regname[rt],regname[rs],offset);
1914 output_w32(0xe5800000|rd_rn_rm(rt,rs,0)|offset);
1916 output_w32(0xe5000000|rd_rn_rm(rt,rs,0)|(-offset));
1919 void emit_writeword_dualindexedx4(int rt, int rs1, int rs2)
1921 assem_debug("str %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
1922 output_w32(0xe7800000|rd_rn_rm(rt,rs1,rs2)|0x100);
1924 void emit_writeword_indexed_tlb(int rt, int addr, int rs, int map, int temp)
1926 if(map<0) emit_writeword_indexed(rt, addr, rs);
1929 emit_writeword_dualindexedx4(rt, rs, map);
1932 void emit_writedword_indexed_tlb(int rh, int rl, int addr, int rs, int map, int temp)
1935 if(rh>=0) emit_writeword_indexed(rh, addr, rs);
1936 emit_writeword_indexed(rl, addr+4, rs);
1939 if(temp!=rs) emit_addimm(map,1,temp);
1940 emit_writeword_indexed_tlb(rh, addr, rs, map, temp);
1941 if(temp!=rs) emit_writeword_indexed_tlb(rl, addr, rs, temp, temp);
1943 emit_addimm(rs,4,rs);
1944 emit_writeword_indexed_tlb(rl, addr, rs, map, temp);
1948 void emit_writehword_indexed(int rt, int offset, int rs)
1950 assert(offset>-256&&offset<256);
1951 assem_debug("strh %s,%s+%d\n",regname[rt],regname[rs],offset);
1953 output_w32(0xe1c000b0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1955 output_w32(0xe14000b0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1958 void emit_writebyte_indexed(int rt, int offset, int rs)
1960 assert(offset>-4096&&offset<4096);
1961 assem_debug("strb %s,%s+%d\n",regname[rt],regname[rs],offset);
1963 output_w32(0xe5c00000|rd_rn_rm(rt,rs,0)|offset);
1965 output_w32(0xe5400000|rd_rn_rm(rt,rs,0)|(-offset));
1968 void emit_writebyte_dualindexedx4(int rt, int rs1, int rs2)
1970 assem_debug("strb %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
1971 output_w32(0xe7c00000|rd_rn_rm(rt,rs1,rs2)|0x100);
1973 void emit_writebyte_indexed_tlb(int rt, int addr, int rs, int map, int temp)
1975 if(map<0) emit_writebyte_indexed(rt, addr, rs);
1978 emit_writebyte_dualindexedx4(rt, rs, map);
1980 emit_addimm(rs,addr,temp);
1981 emit_writebyte_dualindexedx4(rt, temp, map);
1985 void emit_writeword(int rt, int addr)
1987 u_int offset = addr-(u_int)&dynarec_local;
1988 assert(offset<4096);
1989 assem_debug("str %s,fp+%d\n",regname[rt],offset);
1990 output_w32(0xe5800000|rd_rn_rm(rt,FP,0)|offset);
1992 void emit_writehword(int rt, int addr)
1994 u_int offset = addr-(u_int)&dynarec_local;
1996 assem_debug("strh %s,fp+%d\n",regname[rt],offset);
1997 output_w32(0xe1c000b0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
1999 void emit_writebyte(int rt, int addr)
2001 u_int offset = addr-(u_int)&dynarec_local;
2002 assert(offset<4096);
2003 assem_debug("strb %s,fp+%d\n",regname[rt],offset);
2004 output_w32(0xe5c00000|rd_rn_rm(rt,FP,0)|offset);
2006 void emit_writeword_imm(int imm, int addr)
2008 assem_debug("movl $%x,%x\n",imm,addr);
2011 void emit_writebyte_imm(int imm, int addr)
2013 assem_debug("movb $%x,%x\n",imm,addr);
2017 void emit_mul(int rs)
2019 assem_debug("mul %%%s\n",regname[rs]);
2022 void emit_imul(int rs)
2024 assem_debug("imul %%%s\n",regname[rs]);
2027 void emit_umull(u_int rs1, u_int rs2, u_int hi, u_int lo)
2029 assem_debug("umull %s, %s, %s, %s\n",regname[lo],regname[hi],regname[rs1],regname[rs2]);
2034 output_w32(0xe0800090|(hi<<16)|(lo<<12)|(rs2<<8)|rs1);
2036 void emit_smull(u_int rs1, u_int rs2, u_int hi, u_int lo)
2038 assem_debug("smull %s, %s, %s, %s\n",regname[lo],regname[hi],regname[rs1],regname[rs2]);
2043 output_w32(0xe0c00090|(hi<<16)|(lo<<12)|(rs2<<8)|rs1);
2046 void emit_div(int rs)
2048 assem_debug("div %%%s\n",regname[rs]);
2051 void emit_idiv(int rs)
2053 assem_debug("idiv %%%s\n",regname[rs]);
2058 assem_debug("cdq\n");
2062 void emit_clz(int rs,int rt)
2064 assem_debug("clz %s,%s\n",regname[rt],regname[rs]);
2065 output_w32(0xe16f0f10|rd_rn_rm(rt,0,rs));
2068 void emit_subcs(int rs1,int rs2,int rt)
2070 assem_debug("subcs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2071 output_w32(0x20400000|rd_rn_rm(rt,rs1,rs2));
2074 void emit_shrcc_imm(int rs,u_int imm,int rt)
2078 assem_debug("lsrcc %s,%s,#%d\n",regname[rt],regname[rs],imm);
2079 output_w32(0x31a00000|rd_rn_rm(rt,0,rs)|0x20|(imm<<7));
2082 void emit_negmi(int rs, int rt)
2084 assem_debug("rsbmi %s,%s,#0\n",regname[rt],regname[rs]);
2085 output_w32(0x42600000|rd_rn_rm(rt,rs,0));
2088 void emit_negsmi(int rs, int rt)
2090 assem_debug("rsbsmi %s,%s,#0\n",regname[rt],regname[rs]);
2091 output_w32(0x42700000|rd_rn_rm(rt,rs,0));
2094 void emit_orreq(u_int rs1,u_int rs2,u_int rt)
2096 assem_debug("orreq %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2097 output_w32(0x01800000|rd_rn_rm(rt,rs1,rs2));
2100 void emit_orrne(u_int rs1,u_int rs2,u_int rt)
2102 assem_debug("orrne %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2103 output_w32(0x11800000|rd_rn_rm(rt,rs1,rs2));
2106 void emit_bic_lsl(u_int rs1,u_int rs2,u_int shift,u_int rt)
2108 assem_debug("bic %s,%s,%s lsl %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2109 output_w32(0xe1C00000|rd_rn_rm(rt,rs1,rs2)|0x10|(shift<<8));
2112 void emit_biceq_lsl(u_int rs1,u_int rs2,u_int shift,u_int rt)
2114 assem_debug("biceq %s,%s,%s lsl %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2115 output_w32(0x01C00000|rd_rn_rm(rt,rs1,rs2)|0x10|(shift<<8));
2118 void emit_bicne_lsl(u_int rs1,u_int rs2,u_int shift,u_int rt)
2120 assem_debug("bicne %s,%s,%s lsl %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2121 output_w32(0x11C00000|rd_rn_rm(rt,rs1,rs2)|0x10|(shift<<8));
2124 void emit_bic_lsr(u_int rs1,u_int rs2,u_int shift,u_int rt)
2126 assem_debug("bic %s,%s,%s lsr %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2127 output_w32(0xe1C00000|rd_rn_rm(rt,rs1,rs2)|0x30|(shift<<8));
2130 void emit_biceq_lsr(u_int rs1,u_int rs2,u_int shift,u_int rt)
2132 assem_debug("biceq %s,%s,%s lsr %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2133 output_w32(0x01C00000|rd_rn_rm(rt,rs1,rs2)|0x30|(shift<<8));
2136 void emit_bicne_lsr(u_int rs1,u_int rs2,u_int shift,u_int rt)
2138 assem_debug("bicne %s,%s,%s lsr %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2139 output_w32(0x11C00000|rd_rn_rm(rt,rs1,rs2)|0x30|(shift<<8));
2142 void emit_teq(int rs, int rt)
2144 assem_debug("teq %s,%s\n",regname[rs],regname[rt]);
2145 output_w32(0xe1300000|rd_rn_rm(0,rs,rt));
2148 void emit_rsbimm(int rs, int imm, int rt)
2151 genimm_checked(imm,&armval);
2152 assem_debug("rsb %s,%s,#%d\n",regname[rt],regname[rs],imm);
2153 output_w32(0xe2600000|rd_rn_rm(rt,rs,0)|armval);
2156 // Load 2 immediates optimizing for small code size
2157 void emit_mov2imm_compact(int imm1,u_int rt1,int imm2,u_int rt2)
2159 emit_movimm(imm1,rt1);
2161 if(genimm(imm2-imm1,&armval)) {
2162 assem_debug("add %s,%s,#%d\n",regname[rt2],regname[rt1],imm2-imm1);
2163 output_w32(0xe2800000|rd_rn_rm(rt2,rt1,0)|armval);
2164 }else if(genimm(imm1-imm2,&armval)) {
2165 assem_debug("sub %s,%s,#%d\n",regname[rt2],regname[rt1],imm1-imm2);
2166 output_w32(0xe2400000|rd_rn_rm(rt2,rt1,0)|armval);
2168 else emit_movimm(imm2,rt2);
2171 // Conditionally select one of two immediates, optimizing for small code size
2172 // This will only be called if HAVE_CMOV_IMM is defined
2173 void emit_cmov2imm_e_ne_compact(int imm1,int imm2,u_int rt)
2176 if(genimm(imm2-imm1,&armval)) {
2177 emit_movimm(imm1,rt);
2178 assem_debug("addne %s,%s,#%d\n",regname[rt],regname[rt],imm2-imm1);
2179 output_w32(0x12800000|rd_rn_rm(rt,rt,0)|armval);
2180 }else if(genimm(imm1-imm2,&armval)) {
2181 emit_movimm(imm1,rt);
2182 assem_debug("subne %s,%s,#%d\n",regname[rt],regname[rt],imm1-imm2);
2183 output_w32(0x12400000|rd_rn_rm(rt,rt,0)|armval);
2187 emit_movimm(imm1,rt);
2188 add_literal((int)out,imm2);
2189 assem_debug("ldrne %s,pc+? [=%x]\n",regname[rt],imm2);
2190 output_w32(0x15900000|rd_rn_rm(rt,15,0));
2192 emit_movw(imm1&0x0000FFFF,rt);
2193 if((imm1&0xFFFF)!=(imm2&0xFFFF)) {
2194 assem_debug("movwne %s,#%d (0x%x)\n",regname[rt],imm2&0xFFFF,imm2&0xFFFF);
2195 output_w32(0x13000000|rd_rn_rm(rt,0,0)|(imm2&0xfff)|((imm2<<4)&0xf0000));
2197 emit_movt(imm1&0xFFFF0000,rt);
2198 if((imm1&0xFFFF0000)!=(imm2&0xFFFF0000)) {
2199 assem_debug("movtne %s,#%d (0x%x)\n",regname[rt],imm2&0xffff0000,imm2&0xffff0000);
2200 output_w32(0x13400000|rd_rn_rm(rt,0,0)|((imm2>>16)&0xfff)|((imm2>>12)&0xf0000));
2206 // special case for checking invalid_code
2207 void emit_cmpmem_indexedsr12_imm(int addr,int r,int imm)
2212 // special case for checking invalid_code
2213 void emit_cmpmem_indexedsr12_reg(int base,int r,int imm)
2215 assert(imm<128&&imm>=0);
2217 assem_debug("ldrb lr,%s,%s lsr #12\n",regname[base],regname[r]);
2218 output_w32(0xe7d00000|rd_rn_rm(HOST_TEMPREG,base,r)|0x620);
2219 emit_cmpimm(HOST_TEMPREG,imm);
2222 // special case for tlb mapping
2223 void emit_addsr12(int rs1,int rs2,int rt)
2225 assem_debug("add %s,%s,%s lsr #12\n",regname[rt],regname[rs1],regname[rs2]);
2226 output_w32(0xe0800620|rd_rn_rm(rt,rs1,rs2));
2229 void emit_callne(int a)
2231 assem_debug("blne %x\n",a);
2232 u_int offset=genjmp(a);
2233 output_w32(0x1b000000|offset);
2236 // Used to preload hash table entries
2237 void emit_prefetch(void *addr)
2239 assem_debug("prefetch %x\n",(int)addr);
2242 output_modrm(0,5,1);
2243 output_w32((int)addr);
2245 void emit_prefetchreg(int r)
2247 assem_debug("pld %s\n",regname[r]);
2248 output_w32(0xf5d0f000|rd_rn_rm(0,r,0));
2251 // Special case for mini_ht
2252 void emit_ldreq_indexed(int rs, u_int offset, int rt)
2254 assert(offset<4096);
2255 assem_debug("ldreq %s,[%s, #%d]\n",regname[rt],regname[rs],offset);
2256 output_w32(0x05900000|rd_rn_rm(rt,rs,0)|offset);
2259 void emit_flds(int r,int sr)
2261 assem_debug("flds s%d,[%s]\n",sr,regname[r]);
2262 output_w32(0xed900a00|((sr&14)<<11)|((sr&1)<<22)|(r<<16));
2265 void emit_vldr(int r,int vr)
2267 assem_debug("vldr d%d,[%s]\n",vr,regname[r]);
2268 output_w32(0xed900b00|(vr<<12)|(r<<16));
2271 void emit_fsts(int sr,int r)
2273 assem_debug("fsts s%d,[%s]\n",sr,regname[r]);
2274 output_w32(0xed800a00|((sr&14)<<11)|((sr&1)<<22)|(r<<16));
2277 void emit_vstr(int vr,int r)
2279 assem_debug("vstr d%d,[%s]\n",vr,regname[r]);
2280 output_w32(0xed800b00|(vr<<12)|(r<<16));
2283 void emit_ftosizs(int s,int d)
2285 assem_debug("ftosizs s%d,s%d\n",d,s);
2286 output_w32(0xeebd0ac0|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
2289 void emit_ftosizd(int s,int d)
2291 assem_debug("ftosizd s%d,d%d\n",d,s);
2292 output_w32(0xeebd0bc0|((d&14)<<11)|((d&1)<<22)|(s&7));
2295 void emit_fsitos(int s,int d)
2297 assem_debug("fsitos s%d,s%d\n",d,s);
2298 output_w32(0xeeb80ac0|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
2301 void emit_fsitod(int s,int d)
2303 assem_debug("fsitod d%d,s%d\n",d,s);
2304 output_w32(0xeeb80bc0|((d&7)<<12)|((s&14)>>1)|((s&1)<<5));
2307 void emit_fcvtds(int s,int d)
2309 assem_debug("fcvtds d%d,s%d\n",d,s);
2310 output_w32(0xeeb70ac0|((d&7)<<12)|((s&14)>>1)|((s&1)<<5));
2313 void emit_fcvtsd(int s,int d)
2315 assem_debug("fcvtsd s%d,d%d\n",d,s);
2316 output_w32(0xeeb70bc0|((d&14)<<11)|((d&1)<<22)|(s&7));
2319 void emit_fsqrts(int s,int d)
2321 assem_debug("fsqrts d%d,s%d\n",d,s);
2322 output_w32(0xeeb10ac0|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
2325 void emit_fsqrtd(int s,int d)
2327 assem_debug("fsqrtd s%d,d%d\n",d,s);
2328 output_w32(0xeeb10bc0|((d&7)<<12)|(s&7));
2331 void emit_fabss(int s,int d)
2333 assem_debug("fabss d%d,s%d\n",d,s);
2334 output_w32(0xeeb00ac0|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
2337 void emit_fabsd(int s,int d)
2339 assem_debug("fabsd s%d,d%d\n",d,s);
2340 output_w32(0xeeb00bc0|((d&7)<<12)|(s&7));
2343 void emit_fnegs(int s,int d)
2345 assem_debug("fnegs d%d,s%d\n",d,s);
2346 output_w32(0xeeb10a40|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
2349 void emit_fnegd(int s,int d)
2351 assem_debug("fnegd s%d,d%d\n",d,s);
2352 output_w32(0xeeb10b40|((d&7)<<12)|(s&7));
2355 void emit_fadds(int s1,int s2,int d)
2357 assem_debug("fadds s%d,s%d,s%d\n",d,s1,s2);
2358 output_w32(0xee300a00|((d&14)<<11)|((d&1)<<22)|((s1&14)<<15)|((s1&1)<<7)|((s2&14)>>1)|((s2&1)<<5));
2361 void emit_faddd(int s1,int s2,int d)
2363 assem_debug("faddd d%d,d%d,d%d\n",d,s1,s2);
2364 output_w32(0xee300b00|((d&7)<<12)|((s1&7)<<16)|(s2&7));
2367 void emit_fsubs(int s1,int s2,int d)
2369 assem_debug("fsubs s%d,s%d,s%d\n",d,s1,s2);
2370 output_w32(0xee300a40|((d&14)<<11)|((d&1)<<22)|((s1&14)<<15)|((s1&1)<<7)|((s2&14)>>1)|((s2&1)<<5));
2373 void emit_fsubd(int s1,int s2,int d)
2375 assem_debug("fsubd d%d,d%d,d%d\n",d,s1,s2);
2376 output_w32(0xee300b40|((d&7)<<12)|((s1&7)<<16)|(s2&7));
2379 void emit_fmuls(int s1,int s2,int d)
2381 assem_debug("fmuls s%d,s%d,s%d\n",d,s1,s2);
2382 output_w32(0xee200a00|((d&14)<<11)|((d&1)<<22)|((s1&14)<<15)|((s1&1)<<7)|((s2&14)>>1)|((s2&1)<<5));
2385 void emit_fmuld(int s1,int s2,int d)
2387 assem_debug("fmuld d%d,d%d,d%d\n",d,s1,s2);
2388 output_w32(0xee200b00|((d&7)<<12)|((s1&7)<<16)|(s2&7));
2391 void emit_fdivs(int s1,int s2,int d)
2393 assem_debug("fdivs s%d,s%d,s%d\n",d,s1,s2);
2394 output_w32(0xee800a00|((d&14)<<11)|((d&1)<<22)|((s1&14)<<15)|((s1&1)<<7)|((s2&14)>>1)|((s2&1)<<5));
2397 void emit_fdivd(int s1,int s2,int d)
2399 assem_debug("fdivd d%d,d%d,d%d\n",d,s1,s2);
2400 output_w32(0xee800b00|((d&7)<<12)|((s1&7)<<16)|(s2&7));
2403 void emit_fcmps(int x,int y)
2405 assem_debug("fcmps s14, s15\n");
2406 output_w32(0xeeb47a67);
2409 void emit_fcmpd(int x,int y)
2411 assem_debug("fcmpd d6, d7\n");
2412 output_w32(0xeeb46b47);
2417 assem_debug("fmstat\n");
2418 output_w32(0xeef1fa10);
2421 void emit_bicne_imm(int rs,int imm,int rt)
2424 genimm_checked(imm,&armval);
2425 assem_debug("bicne %s,%s,#%d\n",regname[rt],regname[rs],imm);
2426 output_w32(0x13c00000|rd_rn_rm(rt,rs,0)|armval);
2429 void emit_biccs_imm(int rs,int imm,int rt)
2432 genimm_checked(imm,&armval);
2433 assem_debug("biccs %s,%s,#%d\n",regname[rt],regname[rs],imm);
2434 output_w32(0x23c00000|rd_rn_rm(rt,rs,0)|armval);
2437 void emit_bicvc_imm(int rs,int imm,int rt)
2440 genimm_checked(imm,&armval);
2441 assem_debug("bicvc %s,%s,#%d\n",regname[rt],regname[rs],imm);
2442 output_w32(0x73c00000|rd_rn_rm(rt,rs,0)|armval);
2445 void emit_bichi_imm(int rs,int imm,int rt)
2448 genimm_checked(imm,&armval);
2449 assem_debug("bichi %s,%s,#%d\n",regname[rt],regname[rs],imm);
2450 output_w32(0x83c00000|rd_rn_rm(rt,rs,0)|armval);
2453 void emit_orrvs_imm(int rs,int imm,int rt)
2456 genimm_checked(imm,&armval);
2457 assem_debug("orrvs %s,%s,#%d\n",regname[rt],regname[rs],imm);
2458 output_w32(0x63800000|rd_rn_rm(rt,rs,0)|armval);
2461 void emit_orrne_imm(int rs,int imm,int rt)
2464 genimm_checked(imm,&armval);
2465 assem_debug("orrne %s,%s,#%d\n",regname[rt],regname[rs],imm);
2466 output_w32(0x13800000|rd_rn_rm(rt,rs,0)|armval);
2469 void emit_andne_imm(int rs,int imm,int rt)
2472 genimm_checked(imm,&armval);
2473 assem_debug("andne %s,%s,#%d\n",regname[rt],regname[rs],imm);
2474 output_w32(0x12000000|rd_rn_rm(rt,rs,0)|armval);
2477 void emit_jno_unlikely(int a)
2480 assem_debug("addvc pc,pc,#? (%x)\n",/*a-(int)out-8,*/a);
2481 output_w32(0x72800000|rd_rn_rm(15,15,0));
2484 // Save registers before function call
2485 void save_regs(u_int reglist)
2487 reglist&=0x100f; // only save the caller-save registers, r0-r3, r12
2488 if(!reglist) return;
2489 assem_debug("stmia fp,{");
2490 if(reglist&1) assem_debug("r0, ");
2491 if(reglist&2) assem_debug("r1, ");
2492 if(reglist&4) assem_debug("r2, ");
2493 if(reglist&8) assem_debug("r3, ");
2494 if(reglist&0x1000) assem_debug("r12");
2496 output_w32(0xe88b0000|reglist);
2498 // Restore registers after function call
2499 void restore_regs(u_int reglist)
2501 reglist&=0x100f; // only restore the caller-save registers, r0-r3, r12
2502 if(!reglist) return;
2503 assem_debug("ldmia fp,{");
2504 if(reglist&1) assem_debug("r0, ");
2505 if(reglist&2) assem_debug("r1, ");
2506 if(reglist&4) assem_debug("r2, ");
2507 if(reglist&8) assem_debug("r3, ");
2508 if(reglist&0x1000) assem_debug("r12");
2510 output_w32(0xe89b0000|reglist);
2513 // Write back consts using r14 so we don't disturb the other registers
2514 void wb_consts(signed char i_regmap[],uint64_t i_is32,u_int i_dirty,int i)
2517 for(hr=0;hr<HOST_REGS;hr++) {
2518 if(hr!=EXCLUDE_REG&&i_regmap[hr]>=0&&((i_dirty>>hr)&1)) {
2519 if(((regs[i].isconst>>hr)&1)&&i_regmap[hr]>0) {
2520 if(i_regmap[hr]<64 || !((i_is32>>(i_regmap[hr]&63))&1) ) {
2521 int value=constmap[i][hr];
2523 emit_zeroreg(HOST_TEMPREG);
2526 emit_movimm(value,HOST_TEMPREG);
2528 emit_storereg(i_regmap[hr],HOST_TEMPREG);
2530 if((i_is32>>i_regmap[hr])&1) {
2531 if(value!=-1&&value!=0) emit_sarimm(HOST_TEMPREG,31,HOST_TEMPREG);
2532 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
2541 /* Stubs/epilogue */
2543 void literal_pool(int n)
2545 if(!literalcount) return;
2547 if((int)out-literals[0][0]<4096-n) return;
2551 for(i=0;i<literalcount;i++)
2553 ptr=(u_int *)literals[i][0];
2554 u_int offset=(u_int)out-(u_int)ptr-8;
2555 assert(offset<4096);
2556 assert(!(offset&3));
2558 output_w32(literals[i][1]);
2563 void literal_pool_jumpover(int n)
2565 if(!literalcount) return;
2567 if((int)out-literals[0][0]<4096-n) return;
2572 set_jump_target(jaddr,(int)out);
2575 emit_extjump2(int addr, int target, int linker)
2577 u_char *ptr=(u_char *)addr;
2578 assert((ptr[3]&0x0e)==0xa);
2579 emit_loadlp(target,0);
2580 emit_loadlp(addr,1);
2581 assert(addr>=BASE_ADDR&&addr<(BASE_ADDR+(1<<TARGET_SIZE_2)));
2582 //assert((target>=0x80000000&&target<0x80800000)||(target>0xA4000000&&target<0xA4001000));
2584 #ifdef DEBUG_CYCLE_COUNT
2585 emit_readword((int)&last_count,ECX);
2586 emit_add(HOST_CCREG,ECX,HOST_CCREG);
2587 emit_readword((int)&next_interupt,ECX);
2588 emit_writeword(HOST_CCREG,(int)&Count);
2589 emit_sub(HOST_CCREG,ECX,HOST_CCREG);
2590 emit_writeword(ECX,(int)&last_count);
2596 emit_extjump(int addr, int target)
2598 emit_extjump2(addr, target, (int)dyna_linker);
2600 emit_extjump_ds(int addr, int target)
2602 emit_extjump2(addr, target, (int)dyna_linker_ds);
2606 #include "pcsxmem_inline.c"
2611 assem_debug("do_readstub %x\n",start+stubs[n][3]*4);
2613 set_jump_target(stubs[n][1],(int)out);
2614 int type=stubs[n][0];
2617 struct regstat *i_regs=(struct regstat *)stubs[n][5];
2618 u_int reglist=stubs[n][7];
2619 signed char *i_regmap=i_regs->regmap;
2620 int addr=get_reg(i_regmap,AGEN1+(i&1));
2623 if(itype[i]==C1LS||itype[i]==C2LS||itype[i]==LOADLR) {
2624 rth=get_reg(i_regmap,FTEMP|64);
2625 rt=get_reg(i_regmap,FTEMP);
2627 rth=get_reg(i_regmap,rt1[i]|64);
2628 rt=get_reg(i_regmap,rt1[i]);
2632 if(addr<0&&itype[i]!=C1LS&&itype[i]!=C2LS&&itype[i]!=LOADLR) addr=get_reg(i_regmap,-1);
2635 if(type==LOADB_STUB||type==LOADBU_STUB)
2636 ftable=(int)readmemb;
2637 if(type==LOADH_STUB||type==LOADHU_STUB)
2638 ftable=(int)readmemh;
2639 if(type==LOADW_STUB)
2640 ftable=(int)readmem;
2642 if(type==LOADD_STUB)
2643 ftable=(int)readmemd;
2646 emit_writeword(rs,(int)&address);
2649 ds=i_regs!=®s[i];
2650 int real_rs=(itype[i]==LOADLR)?-1:get_reg(i_regmap,rs1[i]);
2651 u_int cmask=ds?-1:(0x100f|~i_regs->wasconst);
2652 if(!ds) load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&0x100f,i);
2653 wb_dirtys(i_regs->regmap_entry,i_regs->was32,i_regs->wasdirty&cmask&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs)));
2654 if(!ds) wb_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&~0x100f,i);
2655 emit_shrimm(rs,16,1);
2656 int cc=get_reg(i_regmap,CCREG);
2658 emit_loadreg(CCREG,2);
2660 emit_movimm(ftable,0);
2661 emit_addimm(cc<0?2:cc,2*stubs[n][6]+2,2);
2663 emit_movimm(start+stubs[n][3]*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3);
2665 //emit_readword((int)&last_count,temp);
2666 //emit_add(cc,temp,cc);
2667 //emit_writeword(cc,(int)&Count);
2669 emit_call((int)&indirect_jump_indexed);
2671 //emit_readword_dualindexedx4(rs,HOST_TEMPREG,15);
2673 // We really shouldn't need to update the count here,
2674 // but not doing so causes random crashes...
2675 emit_readword((int)&Count,HOST_TEMPREG);
2676 emit_readword((int)&next_interupt,2);
2677 emit_addimm(HOST_TEMPREG,-2*stubs[n][6]-2,HOST_TEMPREG);
2678 emit_writeword(2,(int)&last_count);
2679 emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
2681 emit_storereg(CCREG,HOST_TEMPREG);
2685 restore_regs(reglist);
2686 //if((cc=get_reg(regmap,CCREG))>=0) {
2687 // emit_loadreg(CCREG,cc);
2689 if(itype[i]==C1LS||itype[i]==C2LS||(rt>=0&&rt1[i]!=0)) {
2691 if(type==LOADB_STUB)
2692 emit_movsbl((int)&readmem_dword,rt);
2693 if(type==LOADBU_STUB)
2694 emit_movzbl((int)&readmem_dword,rt);
2695 if(type==LOADH_STUB)
2696 emit_movswl((int)&readmem_dword,rt);
2697 if(type==LOADHU_STUB)
2698 emit_movzwl((int)&readmem_dword,rt);
2699 if(type==LOADW_STUB)
2700 emit_readword((int)&readmem_dword,rt);
2701 if(type==LOADD_STUB) {
2702 emit_readword((int)&readmem_dword,rt);
2703 if(rth>=0) emit_readword(((int)&readmem_dword)+4,rth);
2706 emit_jmp(stubs[n][2]); // return address
2709 inline_readstub(int type, int i, u_int addr, signed char regmap[], int target, int adj, u_int reglist)
2711 int rs=get_reg(regmap,target);
2712 int rth=get_reg(regmap,target|64);
2713 int rt=get_reg(regmap,target);
2714 if(rs<0) rs=get_reg(regmap,-1);
2717 if(type==LOADB_STUB||type==LOADBU_STUB)
2718 ftable=(int)readmemb;
2719 if(type==LOADH_STUB||type==LOADHU_STUB)
2720 ftable=(int)readmemh;
2721 if(type==LOADW_STUB)
2722 ftable=(int)readmem;
2724 if(type==LOADD_STUB)
2725 ftable=(int)readmemd;
2729 if(pcsx_direct_read(type,addr,target?rs:-1,rt))
2733 emit_movimm(addr,rs);
2734 emit_writeword(rs,(int)&address);
2737 //emit_shrimm(rs,16,1);
2738 int cc=get_reg(regmap,CCREG);
2740 emit_loadreg(CCREG,2);
2742 //emit_movimm(ftable,0);
2743 emit_movimm(((u_int *)ftable)[addr>>16],0);
2744 //emit_readword((int)&last_count,12);
2745 emit_addimm(cc<0?2:cc,CLOCK_DIVIDER*(adj+1),2);
2747 if((signed int)addr>=(signed int)0xC0000000) {
2748 // Pagefault address
2749 int ds=regmap!=regs[i].regmap;
2750 emit_movimm(start+i*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3);
2754 //emit_writeword(2,(int)&Count);
2755 //emit_call(((u_int *)ftable)[addr>>16]);
2756 emit_call((int)&indirect_jump);
2758 // We really shouldn't need to update the count here,
2759 // but not doing so causes random crashes...
2760 emit_readword((int)&Count,HOST_TEMPREG);
2761 emit_readword((int)&next_interupt,2);
2762 emit_addimm(HOST_TEMPREG,-CLOCK_DIVIDER*(adj+1),HOST_TEMPREG);
2763 emit_writeword(2,(int)&last_count);
2764 emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
2766 emit_storereg(CCREG,HOST_TEMPREG);
2770 restore_regs(reglist);
2772 if(type==LOADB_STUB)
2773 emit_movsbl((int)&readmem_dword,rt);
2774 if(type==LOADBU_STUB)
2775 emit_movzbl((int)&readmem_dword,rt);
2776 if(type==LOADH_STUB)
2777 emit_movswl((int)&readmem_dword,rt);
2778 if(type==LOADHU_STUB)
2779 emit_movzwl((int)&readmem_dword,rt);
2780 if(type==LOADW_STUB)
2781 emit_readword((int)&readmem_dword,rt);
2782 if(type==LOADD_STUB) {
2783 emit_readword((int)&readmem_dword,rt);
2784 if(rth>=0) emit_readword(((int)&readmem_dword)+4,rth);
2791 assem_debug("do_writestub %x\n",start+stubs[n][3]*4);
2793 set_jump_target(stubs[n][1],(int)out);
2794 int type=stubs[n][0];
2797 struct regstat *i_regs=(struct regstat *)stubs[n][5];
2798 u_int reglist=stubs[n][7];
2799 signed char *i_regmap=i_regs->regmap;
2800 int addr=get_reg(i_regmap,AGEN1+(i&1));
2803 if(itype[i]==C1LS||itype[i]==C2LS) {
2804 rth=get_reg(i_regmap,FTEMP|64);
2805 rt=get_reg(i_regmap,r=FTEMP);
2807 rth=get_reg(i_regmap,rs2[i]|64);
2808 rt=get_reg(i_regmap,r=rs2[i]);
2812 if(addr<0) addr=get_reg(i_regmap,-1);
2815 if(type==STOREB_STUB)
2816 ftable=(int)writememb;
2817 if(type==STOREH_STUB)
2818 ftable=(int)writememh;
2819 if(type==STOREW_STUB)
2820 ftable=(int)writemem;
2822 if(type==STORED_STUB)
2823 ftable=(int)writememd;
2826 emit_writeword(rs,(int)&address);
2827 //emit_shrimm(rs,16,rs);
2828 //emit_movmem_indexedx4(ftable,rs,rs);
2829 if(type==STOREB_STUB)
2830 emit_writebyte(rt,(int)&byte);
2831 if(type==STOREH_STUB)
2832 emit_writehword(rt,(int)&hword);
2833 if(type==STOREW_STUB)
2834 emit_writeword(rt,(int)&word);
2835 if(type==STORED_STUB) {
2837 emit_writeword(rt,(int)&dword);
2838 emit_writeword(r?rth:rt,(int)&dword+4);
2840 printf("STORED_STUB\n");
2845 ds=i_regs!=®s[i];
2846 int real_rs=get_reg(i_regmap,rs1[i]);
2847 u_int cmask=ds?-1:(0x100f|~i_regs->wasconst);
2848 if(!ds) load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&0x100f,i);
2849 wb_dirtys(i_regs->regmap_entry,i_regs->was32,i_regs->wasdirty&cmask&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs)));
2850 if(!ds) wb_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&~0x100f,i);
2851 emit_shrimm(rs,16,1);
2852 int cc=get_reg(i_regmap,CCREG);
2854 emit_loadreg(CCREG,2);
2856 emit_movimm(ftable,0);
2857 emit_addimm(cc<0?2:cc,2*stubs[n][6]+2,2);
2859 emit_movimm(start+stubs[n][3]*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3);
2861 //emit_readword((int)&last_count,temp);
2862 //emit_addimm(cc,2*stubs[n][5]+2,cc);
2863 //emit_add(cc,temp,cc);
2864 //emit_writeword(cc,(int)&Count);
2865 emit_call((int)&indirect_jump_indexed);
2867 emit_readword((int)&Count,HOST_TEMPREG);
2868 emit_readword((int)&next_interupt,2);
2869 emit_addimm(HOST_TEMPREG,-2*stubs[n][6]-2,HOST_TEMPREG);
2870 emit_writeword(2,(int)&last_count);
2871 emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
2873 emit_storereg(CCREG,HOST_TEMPREG);
2876 restore_regs(reglist);
2877 //if((cc=get_reg(regmap,CCREG))>=0) {
2878 // emit_loadreg(CCREG,cc);
2880 emit_jmp(stubs[n][2]); // return address
2883 inline_writestub(int type, int i, u_int addr, signed char regmap[], int target, int adj, u_int reglist)
2885 int rs=get_reg(regmap,-1);
2886 int rth=get_reg(regmap,target|64);
2887 int rt=get_reg(regmap,target);
2891 if(pcsx_direct_write(type,addr,rs,rt,regmap))
2895 if(type==STOREB_STUB)
2896 ftable=(int)writememb;
2897 if(type==STOREH_STUB)
2898 ftable=(int)writememh;
2899 if(type==STOREW_STUB)
2900 ftable=(int)writemem;
2902 if(type==STORED_STUB)
2903 ftable=(int)writememd;
2906 emit_writeword(rs,(int)&address);
2907 //emit_shrimm(rs,16,rs);
2908 //emit_movmem_indexedx4(ftable,rs,rs);
2909 if(type==STOREB_STUB)
2910 emit_writebyte(rt,(int)&byte);
2911 if(type==STOREH_STUB)
2912 emit_writehword(rt,(int)&hword);
2913 if(type==STOREW_STUB)
2914 emit_writeword(rt,(int)&word);
2915 if(type==STORED_STUB) {
2917 emit_writeword(rt,(int)&dword);
2918 emit_writeword(target?rth:rt,(int)&dword+4);
2920 printf("STORED_STUB\n");
2925 //emit_shrimm(rs,16,1);
2926 int cc=get_reg(regmap,CCREG);
2928 emit_loadreg(CCREG,2);
2930 //emit_movimm(ftable,0);
2931 emit_movimm(((u_int *)ftable)[addr>>16],0);
2932 //emit_readword((int)&last_count,12);
2933 emit_addimm(cc<0?2:cc,CLOCK_DIVIDER*(adj+1),2);
2935 if((signed int)addr>=(signed int)0xC0000000) {
2936 // Pagefault address
2937 int ds=regmap!=regs[i].regmap;
2938 emit_movimm(start+i*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3);
2942 //emit_writeword(2,(int)&Count);
2943 //emit_call(((u_int *)ftable)[addr>>16]);
2944 emit_call((int)&indirect_jump);
2945 emit_readword((int)&Count,HOST_TEMPREG);
2946 emit_readword((int)&next_interupt,2);
2947 emit_addimm(HOST_TEMPREG,-CLOCK_DIVIDER*(adj+1),HOST_TEMPREG);
2948 emit_writeword(2,(int)&last_count);
2949 emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
2951 emit_storereg(CCREG,HOST_TEMPREG);
2954 restore_regs(reglist);
2957 do_unalignedwritestub(int n)
2959 assem_debug("do_unalignedwritestub %x\n",start+stubs[n][3]*4);
2961 set_jump_target(stubs[n][1],(int)out);
2964 struct regstat *i_regs=(struct regstat *)stubs[n][4];
2965 int addr=stubs[n][5];
2966 u_int reglist=stubs[n][7];
2967 signed char *i_regmap=i_regs->regmap;
2968 int temp2=get_reg(i_regmap,FTEMP);
2971 rt=get_reg(i_regmap,rs2[i]);
2974 assert(opcode[i]==0x2a||opcode[i]==0x2e); // SWL/SWR only implemented
2976 reglist&=~(1<<temp2);
2978 emit_andimm(addr,0xfffffffc,temp2);
2979 emit_writeword(temp2,(int)&address);
2982 ds=i_regs!=®s[i];
2983 real_rs=get_reg(i_regmap,rs1[i]);
2984 u_int cmask=ds?-1:(0x100f|~i_regs->wasconst);
2985 if(!ds) load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&0x100f,i);
2986 wb_dirtys(i_regs->regmap_entry,i_regs->was32,i_regs->wasdirty&cmask&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs)));
2987 if(!ds) wb_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&~0x100f,i);
2988 emit_shrimm(addr,16,1);
2989 int cc=get_reg(i_regmap,CCREG);
2991 emit_loadreg(CCREG,2);
2993 emit_movimm((u_int)readmem,0);
2994 emit_addimm(cc<0?2:cc,2*stubs[n][6]+2,2);
2996 // pagefault address
2997 emit_movimm(start+stubs[n][3]*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3);
2999 emit_call((int)&indirect_jump_indexed);
3000 restore_regs(reglist);
3002 emit_readword((int)&readmem_dword,temp2);
3003 int temp=addr; //hmh
3004 emit_shlimm(addr,3,temp);
3005 emit_andimm(temp,24,temp);
3006 #ifdef BIG_ENDIAN_MIPS
3007 if (opcode[i]==0x2e) // SWR
3009 if (opcode[i]==0x2a) // SWL
3011 emit_xorimm(temp,24,temp);
3012 emit_movimm(-1,HOST_TEMPREG);
3013 if (opcode[i]==0x2a) { // SWL
3014 emit_bic_lsr(temp2,HOST_TEMPREG,temp,temp2);
3015 emit_orrshr(rt,temp,temp2);
3017 emit_bic_lsl(temp2,HOST_TEMPREG,temp,temp2);
3018 emit_orrshl(rt,temp,temp2);
3020 emit_readword((int)&address,addr);
3021 emit_writeword(temp2,(int)&word);
3022 //save_regs(reglist); // don't need to, no state changes
3023 emit_shrimm(addr,16,1);
3024 emit_movimm((u_int)writemem,0);
3025 //emit_call((int)&indirect_jump_indexed);
3027 emit_readword_dualindexedx4(0,1,15);
3028 emit_readword((int)&Count,HOST_TEMPREG);
3029 emit_readword((int)&next_interupt,2);
3030 emit_addimm(HOST_TEMPREG,-2*stubs[n][6]-2,HOST_TEMPREG);
3031 emit_writeword(2,(int)&last_count);
3032 emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
3034 emit_storereg(CCREG,HOST_TEMPREG);
3036 restore_regs(reglist);
3037 emit_jmp(stubs[n][2]); // return address
3040 void printregs(int edi,int esi,int ebp,int esp,int b,int d,int c,int a)
3042 printf("regs: %x %x %x %x %x %x %x (%x)\n",a,b,c,d,ebp,esi,edi,(&edi)[-1]);
3048 u_int reglist=stubs[n][3];
3049 set_jump_target(stubs[n][1],(int)out);
3051 if(stubs[n][4]!=0) emit_mov(stubs[n][4],0);
3052 emit_call((int)&invalidate_addr);
3053 restore_regs(reglist);
3054 emit_jmp(stubs[n][2]); // return address
3057 int do_dirty_stub(int i)
3059 assem_debug("do_dirty_stub %x\n",start+i*4);
3060 u_int addr=(int)start<(int)0xC0000000?(u_int)source:(u_int)start;
3064 // Careful about the code output here, verify_dirty needs to parse it.
3066 emit_loadlp(addr,1);
3067 emit_loadlp((int)copy,2);
3068 emit_loadlp(slen*4,3);
3070 emit_movw(addr&0x0000FFFF,1);
3071 emit_movw(((u_int)copy)&0x0000FFFF,2);
3072 emit_movt(addr&0xFFFF0000,1);
3073 emit_movt(((u_int)copy)&0xFFFF0000,2);
3074 emit_movw(slen*4,3);
3076 emit_movimm(start+i*4,0);
3077 emit_call((int)start<(int)0xC0000000?(int)&verify_code:(int)&verify_code_vm);
3080 if(entry==(int)out) entry=instr_addr[i];
3081 emit_jmp(instr_addr[i]);
3085 void do_dirty_stub_ds()
3087 // Careful about the code output here, verify_dirty needs to parse it.
3089 emit_loadlp((int)start<(int)0xC0000000?(int)source:(int)start,1);
3090 emit_loadlp((int)copy,2);
3091 emit_loadlp(slen*4,3);
3093 emit_movw(((int)start<(int)0xC0000000?(u_int)source:(u_int)start)&0x0000FFFF,1);
3094 emit_movw(((u_int)copy)&0x0000FFFF,2);
3095 emit_movt(((int)start<(int)0xC0000000?(u_int)source:(u_int)start)&0xFFFF0000,1);
3096 emit_movt(((u_int)copy)&0xFFFF0000,2);
3097 emit_movw(slen*4,3);
3099 emit_movimm(start+1,0);
3100 emit_call((int)&verify_code_ds);
3106 assem_debug("do_cop1stub %x\n",start+stubs[n][3]*4);
3107 set_jump_target(stubs[n][1],(int)out);
3109 // int rs=stubs[n][4];
3110 struct regstat *i_regs=(struct regstat *)stubs[n][5];
3113 load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty,i);
3114 //if(i_regs!=®s[i]) printf("oops: regs[i]=%x i_regs=%x",(int)®s[i],(int)i_regs);
3116 //else {printf("fp exception in delay slot\n");}
3117 wb_dirtys(i_regs->regmap_entry,i_regs->was32,i_regs->wasdirty);
3118 if(regs[i].regmap_entry[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
3119 emit_movimm(start+(i-ds)*4,EAX); // Get PC
3120 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
3121 emit_jmp(ds?(int)fp_exception_ds:(int)fp_exception);
3126 int do_tlb_r(int s,int ar,int map,int x,int a,int shift,int c,u_int addr)
3129 if((signed int)addr>=(signed int)0xC0000000) {
3130 // address_generation already loaded the const
3131 emit_readword_dualindexedx4(FP,map,map);
3134 return -1; // No mapping
3138 emit_movimm(((int)memory_map-(int)&dynarec_local)>>2,map);
3139 emit_addsr12(map,s,map);
3140 // Schedule this while we wait on the load
3141 //if(x) emit_xorimm(s,x,ar);
3142 if(shift>=0) emit_shlimm(s,3,shift);
3143 if(~a) emit_andimm(s,a,ar);
3144 emit_readword_dualindexedx4(FP,map,map);
3148 int do_tlb_r_branch(int map, int c, u_int addr, int *jaddr)
3150 if(!c||(signed int)addr>=(signed int)0xC0000000) {
3158 int gen_tlb_addr_r(int ar, int map) {
3160 assem_debug("add %s,%s,%s lsl #2\n",regname[ar],regname[ar],regname[map]);
3161 output_w32(0xe0800100|rd_rn_rm(ar,ar,map));
3165 int do_tlb_w(int s,int ar,int map,int x,int c,u_int addr)
3168 if(addr<0x80800000||addr>=0xC0000000) {
3169 // address_generation already loaded the const
3170 emit_readword_dualindexedx4(FP,map,map);
3173 return -1; // No mapping
3177 emit_movimm(((int)memory_map-(int)&dynarec_local)>>2,map);
3178 emit_addsr12(map,s,map);
3179 // Schedule this while we wait on the load
3180 //if(x) emit_xorimm(s,x,ar);
3181 emit_readword_dualindexedx4(FP,map,map);
3185 int do_tlb_w_branch(int map, int c, u_int addr, int *jaddr)
3187 if(!c||addr<0x80800000||addr>=0xC0000000) {
3188 emit_testimm(map,0x40000000);
3194 int gen_tlb_addr_w(int ar, int map) {
3196 assem_debug("add %s,%s,%s lsl #2\n",regname[ar],regname[ar],regname[map]);
3197 output_w32(0xe0800100|rd_rn_rm(ar,ar,map));
3201 // Generate the address of the memory_map entry, relative to dynarec_local
3202 generate_map_const(u_int addr,int reg) {
3203 //printf("generate_map_const(%x,%s)\n",addr,regname[reg]);
3204 emit_movimm((addr>>12)+(((u_int)memory_map-(u_int)&dynarec_local)>>2),reg);
3209 void shift_assemble_arm(int i,struct regstat *i_regs)
3212 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
3214 signed char s,t,shift;
3215 t=get_reg(i_regs->regmap,rt1[i]);
3216 s=get_reg(i_regs->regmap,rs1[i]);
3217 shift=get_reg(i_regs->regmap,rs2[i]);
3226 if(s!=t) emit_mov(s,t);
3230 emit_andimm(shift,31,HOST_TEMPREG);
3231 if(opcode2[i]==4) // SLLV
3233 emit_shl(s,HOST_TEMPREG,t);
3235 if(opcode2[i]==6) // SRLV
3237 emit_shr(s,HOST_TEMPREG,t);
3239 if(opcode2[i]==7) // SRAV
3241 emit_sar(s,HOST_TEMPREG,t);
3245 } else { // DSLLV/DSRLV/DSRAV
3246 signed char sh,sl,th,tl,shift;
3247 th=get_reg(i_regs->regmap,rt1[i]|64);
3248 tl=get_reg(i_regs->regmap,rt1[i]);
3249 sh=get_reg(i_regs->regmap,rs1[i]|64);
3250 sl=get_reg(i_regs->regmap,rs1[i]);
3251 shift=get_reg(i_regs->regmap,rs2[i]);
3256 if(th>=0) emit_zeroreg(th);
3261 if(sl!=tl) emit_mov(sl,tl);
3262 if(th>=0&&sh!=th) emit_mov(sh,th);
3266 // FIXME: What if shift==tl ?
3268 int temp=get_reg(i_regs->regmap,-1);
3270 if(th<0&&opcode2[i]!=0x14) {th=temp;} // DSLLV doesn't need a temporary register
3273 emit_andimm(shift,31,HOST_TEMPREG);
3274 if(opcode2[i]==0x14) // DSLLV
3276 if(th>=0) emit_shl(sh,HOST_TEMPREG,th);
3277 emit_rsbimm(HOST_TEMPREG,32,HOST_TEMPREG);
3278 emit_orrshr(sl,HOST_TEMPREG,th);
3279 emit_andimm(shift,31,HOST_TEMPREG);
3280 emit_testimm(shift,32);
3281 emit_shl(sl,HOST_TEMPREG,tl);
3282 if(th>=0) emit_cmovne_reg(tl,th);
3283 emit_cmovne_imm(0,tl);
3285 if(opcode2[i]==0x16) // DSRLV
3288 emit_shr(sl,HOST_TEMPREG,tl);
3289 emit_rsbimm(HOST_TEMPREG,32,HOST_TEMPREG);
3290 emit_orrshl(sh,HOST_TEMPREG,tl);
3291 emit_andimm(shift,31,HOST_TEMPREG);
3292 emit_testimm(shift,32);
3293 emit_shr(sh,HOST_TEMPREG,th);
3294 emit_cmovne_reg(th,tl);
3295 if(real_th>=0) emit_cmovne_imm(0,th);
3297 if(opcode2[i]==0x17) // DSRAV
3300 emit_shr(sl,HOST_TEMPREG,tl);
3301 emit_rsbimm(HOST_TEMPREG,32,HOST_TEMPREG);
3304 emit_sarimm(th,31,temp);
3306 emit_orrshl(sh,HOST_TEMPREG,tl);
3307 emit_andimm(shift,31,HOST_TEMPREG);
3308 emit_testimm(shift,32);
3309 emit_sar(sh,HOST_TEMPREG,th);
3310 emit_cmovne_reg(th,tl);
3311 if(real_th>=0) emit_cmovne_reg(temp,th);
3318 #define shift_assemble shift_assemble_arm
3320 void loadlr_assemble_arm(int i,struct regstat *i_regs)
3322 int s,th,tl,temp,temp2,addr,map=-1;
3327 th=get_reg(i_regs->regmap,rt1[i]|64);
3328 tl=get_reg(i_regs->regmap,rt1[i]);
3329 s=get_reg(i_regs->regmap,rs1[i]);
3330 temp=get_reg(i_regs->regmap,-1);
3331 temp2=get_reg(i_regs->regmap,FTEMP);
3332 addr=get_reg(i_regs->regmap,AGEN1+(i&1));
3335 for(hr=0;hr<HOST_REGS;hr++) {
3336 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3339 if(offset||s<0||c) addr=temp2;
3342 c=(i_regs->wasconst>>s)&1;
3343 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3344 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3349 map=get_reg(i_regs->regmap,ROREG);
3350 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3352 emit_shlimm(addr,3,temp);
3353 if (opcode[i]==0x22||opcode[i]==0x26) {
3354 emit_andimm(addr,0xFFFFFFFC,temp2); // LWL/LWR
3356 emit_andimm(addr,0xFFFFFFF8,temp2); // LDL/LDR
3358 emit_cmpimm(addr,RAM_SIZE);
3363 if (opcode[i]==0x22||opcode[i]==0x26) {
3364 emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR
3366 emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR
3373 }else if (opcode[i]==0x22||opcode[i]==0x26) {
3374 a=0xFFFFFFFC; // LWL/LWR
3376 a=0xFFFFFFF8; // LDL/LDR
3378 map=get_reg(i_regs->regmap,TLREG);
3380 map=do_tlb_r(addr,temp2,map,0,a,c?-1:temp,c,constmap[i][s]+offset);
3382 if (opcode[i]==0x22||opcode[i]==0x26) {
3383 emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR
3385 emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR
3388 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
3390 if (opcode[i]==0x22||opcode[i]==0x26) { // LWL/LWR
3392 //emit_readword_indexed((int)rdram-0x80000000,temp2,temp2);
3393 emit_readword_indexed_tlb(0,temp2,map,temp2);
3394 if(jaddr) add_stub(LOADW_STUB,jaddr,(int)out,i,temp2,(int)i_regs,ccadj[i],reglist);
3397 inline_readstub(LOADW_STUB,i,(constmap[i][s]+offset)&0xFFFFFFFC,i_regs->regmap,FTEMP,ccadj[i],reglist);
3400 emit_andimm(temp,24,temp);
3401 #ifdef BIG_ENDIAN_MIPS
3402 if (opcode[i]==0x26) // LWR
3404 if (opcode[i]==0x22) // LWL
3406 emit_xorimm(temp,24,temp);
3407 emit_movimm(-1,HOST_TEMPREG);
3408 if (opcode[i]==0x26) {
3409 emit_shr(temp2,temp,temp2);
3410 emit_bic_lsr(tl,HOST_TEMPREG,temp,tl);
3412 emit_shl(temp2,temp,temp2);
3413 emit_bic_lsl(tl,HOST_TEMPREG,temp,tl);
3415 emit_or(temp2,tl,tl);
3417 //emit_storereg(rt1[i],tl); // DEBUG
3419 if (opcode[i]==0x1A||opcode[i]==0x1B) { // LDL/LDR
3420 // FIXME: little endian
3421 int temp2h=get_reg(i_regs->regmap,FTEMP|64);
3423 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,temp2,temp2h);
3424 //emit_readword_indexed((int)rdram-0x7FFFFFFC,temp2,temp2);
3425 emit_readdword_indexed_tlb(0,temp2,map,temp2h,temp2);
3426 if(jaddr) add_stub(LOADD_STUB,jaddr,(int)out,i,temp2,(int)i_regs,ccadj[i],reglist);
3429 inline_readstub(LOADD_STUB,i,(constmap[i][s]+offset)&0xFFFFFFF8,i_regs->regmap,FTEMP,ccadj[i],reglist);
3433 emit_testimm(temp,32);
3434 emit_andimm(temp,24,temp);
3435 if (opcode[i]==0x1A) { // LDL
3436 emit_rsbimm(temp,32,HOST_TEMPREG);
3437 emit_shl(temp2h,temp,temp2h);
3438 emit_orrshr(temp2,HOST_TEMPREG,temp2h);
3439 emit_movimm(-1,HOST_TEMPREG);
3440 emit_shl(temp2,temp,temp2);
3441 emit_cmove_reg(temp2h,th);
3442 emit_biceq_lsl(tl,HOST_TEMPREG,temp,tl);
3443 emit_bicne_lsl(th,HOST_TEMPREG,temp,th);
3444 emit_orreq(temp2,tl,tl);
3445 emit_orrne(temp2,th,th);
3447 if (opcode[i]==0x1B) { // LDR
3448 emit_xorimm(temp,24,temp);
3449 emit_rsbimm(temp,32,HOST_TEMPREG);
3450 emit_shr(temp2,temp,temp2);
3451 emit_orrshl(temp2h,HOST_TEMPREG,temp2);
3452 emit_movimm(-1,HOST_TEMPREG);
3453 emit_shr(temp2h,temp,temp2h);
3454 emit_cmovne_reg(temp2,tl);
3455 emit_bicne_lsr(th,HOST_TEMPREG,temp,th);
3456 emit_biceq_lsr(tl,HOST_TEMPREG,temp,tl);
3457 emit_orrne(temp2h,th,th);
3458 emit_orreq(temp2h,tl,tl);
3463 #define loadlr_assemble loadlr_assemble_arm
3465 void cop0_assemble(int i,struct regstat *i_regs)
3467 if(opcode2[i]==0) // MFC0
3469 signed char t=get_reg(i_regs->regmap,rt1[i]);
3470 char copr=(source[i]>>11)&0x1f;
3471 //assert(t>=0); // Why does this happen? OOT is weird
3472 if(t>=0&&rt1[i]!=0) {
3474 emit_addimm(FP,(int)&fake_pc-(int)&dynarec_local,0);
3475 emit_movimm((source[i]>>11)&0x1f,1);
3476 emit_writeword(0,(int)&PC);
3477 emit_writebyte(1,(int)&(fake_pc.f.r.nrd));
3479 emit_readword((int)&last_count,ECX);
3480 emit_loadreg(CCREG,HOST_CCREG); // TODO: do proper reg alloc
3481 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3482 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG);
3483 emit_writeword(HOST_CCREG,(int)&Count);
3485 emit_call((int)MFC0);
3486 emit_readword((int)&readmem_dword,t);
3488 emit_readword((int)®_cop0+copr*4,t);
3492 else if(opcode2[i]==4) // MTC0
3494 signed char s=get_reg(i_regs->regmap,rs1[i]);
3495 char copr=(source[i]>>11)&0x1f;
3497 emit_writeword(s,(int)&readmem_dword);
3498 wb_register(rs1[i],i_regs->regmap,i_regs->dirty,i_regs->is32);
3500 emit_addimm(FP,(int)&fake_pc-(int)&dynarec_local,0);
3501 emit_movimm((source[i]>>11)&0x1f,1);
3502 emit_writeword(0,(int)&PC);
3503 emit_writebyte(1,(int)&(fake_pc.f.r.nrd));
3505 if(copr==9||copr==11||copr==12||copr==13) {
3506 emit_readword((int)&last_count,ECX);
3507 emit_loadreg(CCREG,HOST_CCREG); // TODO: do proper reg alloc
3508 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3509 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG);
3510 emit_writeword(HOST_CCREG,(int)&Count);
3512 // What a mess. The status register (12) can enable interrupts,
3513 // so needs a special case to handle a pending interrupt.
3514 // The interrupt must be taken immediately, because a subsequent
3515 // instruction might disable interrupts again.
3516 if(copr==12||copr==13) {
3519 // burn cycles to cause cc_interrupt, which will
3520 // reschedule next_interupt. Relies on CCREG from above.
3521 assem_debug("MTC0 DS %d\n", copr);
3522 emit_writeword(HOST_CCREG,(int)&last_count);
3523 emit_movimm(0,HOST_CCREG);
3524 emit_storereg(CCREG,HOST_CCREG);
3525 emit_movimm(copr,0);
3526 emit_call((int)pcsx_mtc0_ds);
3530 emit_movimm(start+i*4+4,0);
3532 emit_writeword(0,(int)&pcaddr);
3533 emit_writeword(1,(int)&pending_exception);
3535 //else if(copr==12&&is_delayslot) emit_call((int)MTC0_R12);
3538 emit_movimm(copr,0);
3539 emit_call((int)pcsx_mtc0);
3541 emit_call((int)MTC0);
3543 if(copr==9||copr==11||copr==12||copr==13) {
3544 emit_readword((int)&Count,HOST_CCREG);
3545 emit_readword((int)&next_interupt,ECX);
3546 emit_addimm(HOST_CCREG,-CLOCK_DIVIDER*ccadj[i],HOST_CCREG);
3547 emit_sub(HOST_CCREG,ECX,HOST_CCREG);
3548 emit_writeword(ECX,(int)&last_count);
3549 emit_storereg(CCREG,HOST_CCREG);
3551 if(copr==12||copr==13) {
3552 assert(!is_delayslot);
3553 emit_readword((int)&pending_exception,14);
3555 emit_loadreg(rs1[i],s);
3556 if(get_reg(i_regs->regmap,rs1[i]|64)>=0)
3557 emit_loadreg(rs1[i]|64,get_reg(i_regs->regmap,rs1[i]|64));
3558 if(copr==12||copr==13) {
3560 emit_jne((int)&do_interrupt);
3566 assert(opcode2[i]==0x10);
3568 if((source[i]&0x3f)==0x01) // TLBR
3569 emit_call((int)TLBR);
3570 if((source[i]&0x3f)==0x02) // TLBWI
3571 emit_call((int)TLBWI_new);
3572 if((source[i]&0x3f)==0x06) { // TLBWR
3573 // The TLB entry written by TLBWR is dependent on the count,
3574 // so update the cycle count
3575 emit_readword((int)&last_count,ECX);
3576 if(i_regs->regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
3577 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3578 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG);
3579 emit_writeword(HOST_CCREG,(int)&Count);
3580 emit_call((int)TLBWR_new);
3582 if((source[i]&0x3f)==0x08) // TLBP
3583 emit_call((int)TLBP);
3586 if((source[i]&0x3f)==0x10) // RFE
3588 emit_readword((int)&Status,0);
3589 emit_andimm(0,0x3c,1);
3590 emit_andimm(0,~0xf,0);
3591 emit_orrshr_imm(1,2,0);
3592 emit_writeword(0,(int)&Status);
3595 if((source[i]&0x3f)==0x18) // ERET
3598 if(i_regs->regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
3599 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*count,HOST_CCREG); // TODO: Should there be an extra cycle here?
3600 emit_jmp((int)jump_eret);
3606 static void cop2_get_dreg(u_int copr,signed char tl,signed char temp)
3616 emit_readword((int)®_cop2d[copr],tl);
3617 emit_signextend16(tl,tl);
3618 emit_writeword(tl,(int)®_cop2d[copr]); // hmh
3625 emit_readword((int)®_cop2d[copr],tl);
3626 emit_andimm(tl,0xffff,tl);
3627 emit_writeword(tl,(int)®_cop2d[copr]);
3630 emit_readword((int)®_cop2d[14],tl); // SXY2
3631 emit_writeword(tl,(int)®_cop2d[copr]);
3635 emit_readword((int)®_cop2d[9],temp);
3636 emit_testimm(temp,0x8000); // do we need this?
3637 emit_andimm(temp,0xf80,temp);
3638 emit_andne_imm(temp,0,temp);
3639 emit_shrimm(temp,7,tl);
3640 emit_readword((int)®_cop2d[10],temp);
3641 emit_testimm(temp,0x8000);
3642 emit_andimm(temp,0xf80,temp);
3643 emit_andne_imm(temp,0,temp);
3644 emit_orrshr_imm(temp,2,tl);
3645 emit_readword((int)®_cop2d[11],temp);
3646 emit_testimm(temp,0x8000);
3647 emit_andimm(temp,0xf80,temp);
3648 emit_andne_imm(temp,0,temp);
3649 emit_orrshl_imm(temp,3,tl);
3650 emit_writeword(tl,(int)®_cop2d[copr]);
3653 emit_readword((int)®_cop2d[copr],tl);
3658 static void cop2_put_dreg(u_int copr,signed char sl,signed char temp)
3662 emit_readword((int)®_cop2d[13],temp); // SXY1
3663 emit_writeword(sl,(int)®_cop2d[copr]);
3664 emit_writeword(temp,(int)®_cop2d[12]); // SXY0
3665 emit_readword((int)®_cop2d[14],temp); // SXY2
3666 emit_writeword(sl,(int)®_cop2d[14]);
3667 emit_writeword(temp,(int)®_cop2d[13]); // SXY1
3670 emit_andimm(sl,0x001f,temp);
3671 emit_shlimm(temp,7,temp);
3672 emit_writeword(temp,(int)®_cop2d[9]);
3673 emit_andimm(sl,0x03e0,temp);
3674 emit_shlimm(temp,2,temp);
3675 emit_writeword(temp,(int)®_cop2d[10]);
3676 emit_andimm(sl,0x7c00,temp);
3677 emit_shrimm(temp,3,temp);
3678 emit_writeword(temp,(int)®_cop2d[11]);
3679 emit_writeword(sl,(int)®_cop2d[28]);
3683 emit_mvnmi(temp,temp);
3684 emit_clz(temp,temp);
3685 emit_writeword(sl,(int)®_cop2d[30]);
3686 emit_writeword(temp,(int)®_cop2d[31]);
3691 emit_writeword(sl,(int)®_cop2d[copr]);
3696 void cop2_assemble(int i,struct regstat *i_regs)
3698 u_int copr=(source[i]>>11)&0x1f;
3699 signed char temp=get_reg(i_regs->regmap,-1);
3700 if (opcode2[i]==0) { // MFC2
3701 signed char tl=get_reg(i_regs->regmap,rt1[i]);
3702 if(tl>=0&&rt1[i]!=0)
3703 cop2_get_dreg(copr,tl,temp);
3705 else if (opcode2[i]==4) { // MTC2
3706 signed char sl=get_reg(i_regs->regmap,rs1[i]);
3707 cop2_put_dreg(copr,sl,temp);
3709 else if (opcode2[i]==2) // CFC2
3711 signed char tl=get_reg(i_regs->regmap,rt1[i]);
3712 if(tl>=0&&rt1[i]!=0)
3713 emit_readword((int)®_cop2c[copr],tl);
3715 else if (opcode2[i]==6) // CTC2
3717 signed char sl=get_reg(i_regs->regmap,rs1[i]);
3726 emit_signextend16(sl,temp);
3729 //value = value & 0x7ffff000;
3730 //if (value & 0x7f87e000) value |= 0x80000000;
3731 emit_shrimm(sl,12,temp);
3732 emit_shlimm(temp,12,temp);
3733 emit_testimm(temp,0x7f000000);
3734 emit_testeqimm(temp,0x00870000);
3735 emit_testeqimm(temp,0x0000e000);
3736 emit_orrne_imm(temp,0x80000000,temp);
3742 emit_writeword(temp,(int)®_cop2c[copr]);
3747 void c2op_assemble(int i,struct regstat *i_regs)
3749 signed char temp=get_reg(i_regs->regmap,-1);
3750 u_int c2op=source[i]&0x3f;
3752 for(hr=0;hr<HOST_REGS;hr++) {
3753 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3755 if(i==0||itype[i-1]!=C2OP)
3758 if (gte_handlers[c2op]!=NULL) {
3759 int cc=get_reg(i_regs->regmap,CCREG);
3760 emit_movimm(source[i],1); // opcode
3761 if (cc>=0&>e_cycletab[c2op])
3762 emit_addimm(cc,gte_cycletab[c2op]/2,cc); // XXX: could just adjust ccadj?
3763 emit_addimm(FP,(int)&psxRegs.CP2D.r[0]-(int)&dynarec_local,0); // cop2 regs
3764 emit_writeword(1,(int)&psxRegs.code);
3765 emit_call((int)gte_handlers[c2op]);
3768 if(i>=slen-1||itype[i+1]!=C2OP)
3769 restore_regs(reglist);
3772 void cop1_unusable(int i,struct regstat *i_regs)
3774 // XXX: should just just do the exception instead
3778 add_stub(FP_STUB,jaddr,(int)out,i,0,(int)i_regs,is_delayslot,0);
3783 void cop1_assemble(int i,struct regstat *i_regs)
3785 #ifndef DISABLE_COP1
3786 // Check cop1 unusable
3788 signed char rs=get_reg(i_regs->regmap,CSREG);
3790 emit_testimm(rs,0x20000000);
3793 add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3796 if (opcode2[i]==0) { // MFC1
3797 signed char tl=get_reg(i_regs->regmap,rt1[i]);
3799 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],tl);
3800 emit_readword_indexed(0,tl,tl);
3803 else if (opcode2[i]==1) { // DMFC1
3804 signed char tl=get_reg(i_regs->regmap,rt1[i]);
3805 signed char th=get_reg(i_regs->regmap,rt1[i]|64);
3807 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],tl);
3808 if(th>=0) emit_readword_indexed(4,tl,th);
3809 emit_readword_indexed(0,tl,tl);
3812 else if (opcode2[i]==4) { // MTC1
3813 signed char sl=get_reg(i_regs->regmap,rs1[i]);
3814 signed char temp=get_reg(i_regs->regmap,-1);
3815 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
3816 emit_writeword_indexed(sl,0,temp);
3818 else if (opcode2[i]==5) { // DMTC1
3819 signed char sl=get_reg(i_regs->regmap,rs1[i]);
3820 signed char sh=rs1[i]>0?get_reg(i_regs->regmap,rs1[i]|64):sl;
3821 signed char temp=get_reg(i_regs->regmap,-1);
3822 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],temp);
3823 emit_writeword_indexed(sh,4,temp);
3824 emit_writeword_indexed(sl,0,temp);
3826 else if (opcode2[i]==2) // CFC1
3828 signed char tl=get_reg(i_regs->regmap,rt1[i]);
3830 u_int copr=(source[i]>>11)&0x1f;
3831 if(copr==0) emit_readword((int)&FCR0,tl);
3832 if(copr==31) emit_readword((int)&FCR31,tl);
3835 else if (opcode2[i]==6) // CTC1
3837 signed char sl=get_reg(i_regs->regmap,rs1[i]);
3838 u_int copr=(source[i]>>11)&0x1f;
3842 emit_writeword(sl,(int)&FCR31);
3843 // Set the rounding mode
3845 //char temp=get_reg(i_regs->regmap,-1);
3846 //emit_andimm(sl,3,temp);
3847 //emit_fldcw_indexed((int)&rounding_modes,temp);
3851 cop1_unusable(i, i_regs);
3855 void fconv_assemble_arm(int i,struct regstat *i_regs)
3857 #ifndef DISABLE_COP1
3858 signed char temp=get_reg(i_regs->regmap,-1);
3860 // Check cop1 unusable
3862 signed char rs=get_reg(i_regs->regmap,CSREG);
3864 emit_testimm(rs,0x20000000);
3867 add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3871 #if(defined(__VFP_FP__) && !defined(__SOFTFP__))
3872 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x0d) { // trunc_w_s
3873 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
3875 emit_ftosizs(15,15); // float->int, truncate
3876 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f))
3877 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],temp);
3881 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x0d) { // trunc_w_d
3882 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],temp);
3884 emit_ftosizd(7,13); // double->int, truncate
3885 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],temp);
3890 if(opcode2[i]==0x14&&(source[i]&0x3f)==0x20) { // cvt_s_w
3891 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
3893 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f))
3894 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],temp);
3899 if(opcode2[i]==0x14&&(source[i]&0x3f)==0x21) { // cvt_d_w
3900 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
3902 emit_readword((int)®_cop1_double[(source[i]>>6)&0x1f],temp);
3908 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x21) { // cvt_d_s
3909 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
3911 emit_readword((int)®_cop1_double[(source[i]>>6)&0x1f],temp);
3916 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x20) { // cvt_s_d
3917 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],temp);
3919 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],temp);
3929 for(hr=0;hr<HOST_REGS;hr++) {
3930 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3934 if(opcode2[i]==0x14&&(source[i]&0x3f)==0x20) {
3935 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
3936 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
3937 emit_call((int)cvt_s_w);
3939 if(opcode2[i]==0x14&&(source[i]&0x3f)==0x21) {
3940 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
3941 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
3942 emit_call((int)cvt_d_w);
3944 if(opcode2[i]==0x15&&(source[i]&0x3f)==0x20) {
3945 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
3946 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
3947 emit_call((int)cvt_s_l);
3949 if(opcode2[i]==0x15&&(source[i]&0x3f)==0x21) {
3950 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
3951 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
3952 emit_call((int)cvt_d_l);
3955 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x21) {
3956 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
3957 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
3958 emit_call((int)cvt_d_s);
3960 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x24) {
3961 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
3962 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
3963 emit_call((int)cvt_w_s);
3965 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x25) {
3966 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
3967 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
3968 emit_call((int)cvt_l_s);
3971 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x20) {
3972 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
3973 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
3974 emit_call((int)cvt_s_d);
3976 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x24) {
3977 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
3978 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
3979 emit_call((int)cvt_w_d);
3981 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x25) {
3982 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
3983 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
3984 emit_call((int)cvt_l_d);
3987 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x08) {
3988 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
3989 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
3990 emit_call((int)round_l_s);
3992 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x09) {
3993 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
3994 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
3995 emit_call((int)trunc_l_s);
3997 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x0a) {
3998 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
3999 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
4000 emit_call((int)ceil_l_s);
4002 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x0b) {
4003 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
4004 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
4005 emit_call((int)floor_l_s);
4007 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x0c) {
4008 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
4009 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
4010 emit_call((int)round_w_s);
4012 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x0d) {
4013 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
4014 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
4015 emit_call((int)trunc_w_s);
4017 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x0e) {
4018 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
4019 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
4020 emit_call((int)ceil_w_s);
4022 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x0f) {
4023 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
4024 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
4025 emit_call((int)floor_w_s);
4028 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x08) {
4029 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
4030 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
4031 emit_call((int)round_l_d);
4033 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x09) {
4034 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
4035 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
4036 emit_call((int)trunc_l_d);
4038 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x0a) {
4039 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
4040 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
4041 emit_call((int)ceil_l_d);
4043 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x0b) {
4044 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
4045 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
4046 emit_call((int)floor_l_d);
4048 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x0c) {
4049 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
4050 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
4051 emit_call((int)round_w_d);
4053 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x0d) {
4054 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
4055 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
4056 emit_call((int)trunc_w_d);
4058 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x0e) {
4059 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
4060 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
4061 emit_call((int)ceil_w_d);
4063 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x0f) {
4064 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
4065 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
4066 emit_call((int)floor_w_d);
4069 restore_regs(reglist);
4071 cop1_unusable(i, i_regs);
4074 #define fconv_assemble fconv_assemble_arm
4076 void fcomp_assemble(int i,struct regstat *i_regs)
4078 #ifndef DISABLE_COP1
4079 signed char fs=get_reg(i_regs->regmap,FSREG);
4080 signed char temp=get_reg(i_regs->regmap,-1);
4082 // Check cop1 unusable
4084 signed char cs=get_reg(i_regs->regmap,CSREG);
4086 emit_testimm(cs,0x20000000);
4089 add_stub(FP_STUB,jaddr,(int)out,i,cs,(int)i_regs,is_delayslot,0);
4093 if((source[i]&0x3f)==0x30) {
4094 emit_andimm(fs,~0x800000,fs);
4098 if((source[i]&0x3e)==0x38) {
4099 // sf/ngle - these should throw exceptions for NaNs
4100 emit_andimm(fs,~0x800000,fs);
4104 #if(defined(__VFP_FP__) && !defined(__SOFTFP__))
4105 if(opcode2[i]==0x10) {
4106 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
4107 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],HOST_TEMPREG);
4108 emit_orimm(fs,0x800000,fs);
4110 emit_flds(HOST_TEMPREG,15);
4113 if((source[i]&0x3f)==0x31) emit_bicvc_imm(fs,0x800000,fs); // c_un_s
4114 if((source[i]&0x3f)==0x32) emit_bicne_imm(fs,0x800000,fs); // c_eq_s
4115 if((source[i]&0x3f)==0x33) {emit_bicne_imm(fs,0x800000,fs);emit_orrvs_imm(fs,0x800000,fs);} // c_ueq_s
4116 if((source[i]&0x3f)==0x34) emit_biccs_imm(fs,0x800000,fs); // c_olt_s
4117 if((source[i]&0x3f)==0x35) {emit_biccs_imm(fs,0x800000,fs);emit_orrvs_imm(fs,0x800000,fs);} // c_ult_s
4118 if((source[i]&0x3f)==0x36) emit_bichi_imm(fs,0x800000,fs); // c_ole_s
4119 if((source[i]&0x3f)==0x37) {emit_bichi_imm(fs,0x800000,fs);emit_orrvs_imm(fs,0x800000,fs);} // c_ule_s
4120 if((source[i]&0x3f)==0x3a) emit_bicne_imm(fs,0x800000,fs); // c_seq_s
4121 if((source[i]&0x3f)==0x3b) emit_bicne_imm(fs,0x800000,fs); // c_ngl_s
4122 if((source[i]&0x3f)==0x3c) emit_biccs_imm(fs,0x800000,fs); // c_lt_s
4123 if((source[i]&0x3f)==0x3d) emit_biccs_imm(fs,0x800000,fs); // c_nge_s
4124 if((source[i]&0x3f)==0x3e) emit_bichi_imm(fs,0x800000,fs); // c_le_s
4125 if((source[i]&0x3f)==0x3f) emit_bichi_imm(fs,0x800000,fs); // c_ngt_s
4128 if(opcode2[i]==0x11) {
4129 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],temp);
4130 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],HOST_TEMPREG);
4131 emit_orimm(fs,0x800000,fs);
4133 emit_vldr(HOST_TEMPREG,7);
4136 if((source[i]&0x3f)==0x31) emit_bicvc_imm(fs,0x800000,fs); // c_un_d
4137 if((source[i]&0x3f)==0x32) emit_bicne_imm(fs,0x800000,fs); // c_eq_d
4138 if((source[i]&0x3f)==0x33) {emit_bicne_imm(fs,0x800000,fs);emit_orrvs_imm(fs,0x800000,fs);} // c_ueq_d
4139 if((source[i]&0x3f)==0x34) emit_biccs_imm(fs,0x800000,fs); // c_olt_d
4140 if((source[i]&0x3f)==0x35) {emit_biccs_imm(fs,0x800000,fs);emit_orrvs_imm(fs,0x800000,fs);} // c_ult_d
4141 if((source[i]&0x3f)==0x36) emit_bichi_imm(fs,0x800000,fs); // c_ole_d
4142 if((source[i]&0x3f)==0x37) {emit_bichi_imm(fs,0x800000,fs);emit_orrvs_imm(fs,0x800000,fs);} // c_ule_d
4143 if((source[i]&0x3f)==0x3a) emit_bicne_imm(fs,0x800000,fs); // c_seq_d
4144 if((source[i]&0x3f)==0x3b) emit_bicne_imm(fs,0x800000,fs); // c_ngl_d
4145 if((source[i]&0x3f)==0x3c) emit_biccs_imm(fs,0x800000,fs); // c_lt_d
4146 if((source[i]&0x3f)==0x3d) emit_biccs_imm(fs,0x800000,fs); // c_nge_d
4147 if((source[i]&0x3f)==0x3e) emit_bichi_imm(fs,0x800000,fs); // c_le_d
4148 if((source[i]&0x3f)==0x3f) emit_bichi_imm(fs,0x800000,fs); // c_ngt_d
4156 for(hr=0;hr<HOST_REGS;hr++) {
4157 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
4161 if(opcode2[i]==0x10) {
4162 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
4163 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],ARG2_REG);
4164 if((source[i]&0x3f)==0x30) emit_call((int)c_f_s);
4165 if((source[i]&0x3f)==0x31) emit_call((int)c_un_s);
4166 if((source[i]&0x3f)==0x32) emit_call((int)c_eq_s);
4167 if((source[i]&0x3f)==0x33) emit_call((int)c_ueq_s);
4168 if((source[i]&0x3f)==0x34) emit_call((int)c_olt_s);
4169 if((source[i]&0x3f)==0x35) emit_call((int)c_ult_s);
4170 if((source[i]&0x3f)==0x36) emit_call((int)c_ole_s);
4171 if((source[i]&0x3f)==0x37) emit_call((int)c_ule_s);
4172 if((source[i]&0x3f)==0x38) emit_call((int)c_sf_s);
4173 if((source[i]&0x3f)==0x39) emit_call((int)c_ngle_s);
4174 if((source[i]&0x3f)==0x3a) emit_call((int)c_seq_s);
4175 if((source[i]&0x3f)==0x3b) emit_call((int)c_ngl_s);
4176 if((source[i]&0x3f)==0x3c) emit_call((int)c_lt_s);
4177 if((source[i]&0x3f)==0x3d) emit_call((int)c_nge_s);
4178 if((source[i]&0x3f)==0x3e) emit_call((int)c_le_s);
4179 if((source[i]&0x3f)==0x3f) emit_call((int)c_ngt_s);
4181 if(opcode2[i]==0x11) {
4182 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
4183 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],ARG2_REG);
4184 if((source[i]&0x3f)==0x30) emit_call((int)c_f_d);
4185 if((source[i]&0x3f)==0x31) emit_call((int)c_un_d);
4186 if((source[i]&0x3f)==0x32) emit_call((int)c_eq_d);
4187 if((source[i]&0x3f)==0x33) emit_call((int)c_ueq_d);
4188 if((source[i]&0x3f)==0x34) emit_call((int)c_olt_d);
4189 if((source[i]&0x3f)==0x35) emit_call((int)c_ult_d);
4190 if((source[i]&0x3f)==0x36) emit_call((int)c_ole_d);
4191 if((source[i]&0x3f)==0x37) emit_call((int)c_ule_d);
4192 if((source[i]&0x3f)==0x38) emit_call((int)c_sf_d);
4193 if((source[i]&0x3f)==0x39) emit_call((int)c_ngle_d);
4194 if((source[i]&0x3f)==0x3a) emit_call((int)c_seq_d);
4195 if((source[i]&0x3f)==0x3b) emit_call((int)c_ngl_d);
4196 if((source[i]&0x3f)==0x3c) emit_call((int)c_lt_d);
4197 if((source[i]&0x3f)==0x3d) emit_call((int)c_nge_d);
4198 if((source[i]&0x3f)==0x3e) emit_call((int)c_le_d);
4199 if((source[i]&0x3f)==0x3f) emit_call((int)c_ngt_d);
4201 restore_regs(reglist);
4202 emit_loadreg(FSREG,fs);
4204 cop1_unusable(i, i_regs);
4208 void float_assemble(int i,struct regstat *i_regs)
4210 #ifndef DISABLE_COP1
4211 signed char temp=get_reg(i_regs->regmap,-1);
4213 // Check cop1 unusable
4215 signed char cs=get_reg(i_regs->regmap,CSREG);
4217 emit_testimm(cs,0x20000000);
4220 add_stub(FP_STUB,jaddr,(int)out,i,cs,(int)i_regs,is_delayslot,0);
4224 #if(defined(__VFP_FP__) && !defined(__SOFTFP__))
4225 if((source[i]&0x3f)==6) // mov
4227 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f)) {
4228 if(opcode2[i]==0x10) {
4229 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
4230 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],HOST_TEMPREG);
4231 emit_readword_indexed(0,temp,temp);
4232 emit_writeword_indexed(temp,0,HOST_TEMPREG);
4234 if(opcode2[i]==0x11) {
4235 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],temp);
4236 emit_readword((int)®_cop1_double[(source[i]>>6)&0x1f],HOST_TEMPREG);
4238 emit_vstr(7,HOST_TEMPREG);
4244 if((source[i]&0x3f)>3)
4246 if(opcode2[i]==0x10) {
4247 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
4249 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f)) {
4250 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],temp);
4252 if((source[i]&0x3f)==4) // sqrt
4254 if((source[i]&0x3f)==5) // abs
4256 if((source[i]&0x3f)==7) // neg
4260 if(opcode2[i]==0x11) {
4261 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],temp);
4263 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f)) {
4264 emit_readword((int)®_cop1_double[(source[i]>>6)&0x1f],temp);
4266 if((source[i]&0x3f)==4) // sqrt
4268 if((source[i]&0x3f)==5) // abs
4270 if((source[i]&0x3f)==7) // neg
4276 if((source[i]&0x3f)<4)
4278 if(opcode2[i]==0x10) {
4279 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
4281 if(opcode2[i]==0x11) {
4282 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],temp);
4284 if(((source[i]>>11)&0x1f)!=((source[i]>>16)&0x1f)) {
4285 if(opcode2[i]==0x10) {
4286 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],HOST_TEMPREG);
4288 emit_flds(HOST_TEMPREG,13);
4289 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f)) {
4290 if(((source[i]>>16)&0x1f)!=((source[i]>>6)&0x1f)) {
4291 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],temp);
4294 if((source[i]&0x3f)==0) emit_fadds(15,13,15);
4295 if((source[i]&0x3f)==1) emit_fsubs(15,13,15);
4296 if((source[i]&0x3f)==2) emit_fmuls(15,13,15);
4297 if((source[i]&0x3f)==3) emit_fdivs(15,13,15);
4298 if(((source[i]>>16)&0x1f)==((source[i]>>6)&0x1f)) {
4299 emit_fsts(15,HOST_TEMPREG);
4304 else if(opcode2[i]==0x11) {
4305 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],HOST_TEMPREG);
4307 emit_vldr(HOST_TEMPREG,6);
4308 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f)) {
4309 if(((source[i]>>16)&0x1f)!=((source[i]>>6)&0x1f)) {
4310 emit_readword((int)®_cop1_double[(source[i]>>6)&0x1f],temp);
4313 if((source[i]&0x3f)==0) emit_faddd(7,6,7);
4314 if((source[i]&0x3f)==1) emit_fsubd(7,6,7);
4315 if((source[i]&0x3f)==2) emit_fmuld(7,6,7);
4316 if((source[i]&0x3f)==3) emit_fdivd(7,6,7);
4317 if(((source[i]>>16)&0x1f)==((source[i]>>6)&0x1f)) {
4318 emit_vstr(7,HOST_TEMPREG);
4325 if(opcode2[i]==0x10) {
4327 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f)) {
4328 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],temp);
4330 if((source[i]&0x3f)==0) emit_fadds(15,15,15);
4331 if((source[i]&0x3f)==1) emit_fsubs(15,15,15);
4332 if((source[i]&0x3f)==2) emit_fmuls(15,15,15);
4333 if((source[i]&0x3f)==3) emit_fdivs(15,15,15);
4336 else if(opcode2[i]==0x11) {
4338 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f)) {
4339 emit_readword((int)®_cop1_double[(source[i]>>6)&0x1f],temp);
4341 if((source[i]&0x3f)==0) emit_faddd(7,7,7);
4342 if((source[i]&0x3f)==1) emit_fsubd(7,7,7);
4343 if((source[i]&0x3f)==2) emit_fmuld(7,7,7);
4344 if((source[i]&0x3f)==3) emit_fdivd(7,7,7);
4353 for(hr=0;hr<HOST_REGS;hr++) {
4354 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
4356 if(opcode2[i]==0x10) { // Single precision
4358 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
4359 if((source[i]&0x3f)<4) {
4360 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],ARG2_REG);
4361 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG3_REG);
4363 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
4365 switch(source[i]&0x3f)
4367 case 0x00: emit_call((int)add_s);break;
4368 case 0x01: emit_call((int)sub_s);break;
4369 case 0x02: emit_call((int)mul_s);break;
4370 case 0x03: emit_call((int)div_s);break;
4371 case 0x04: emit_call((int)sqrt_s);break;
4372 case 0x05: emit_call((int)abs_s);break;
4373 case 0x06: emit_call((int)mov_s);break;
4374 case 0x07: emit_call((int)neg_s);break;
4376 restore_regs(reglist);
4378 if(opcode2[i]==0x11) { // Double precision
4380 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
4381 if((source[i]&0x3f)<4) {
4382 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],ARG2_REG);
4383 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG3_REG);
4385 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
4387 switch(source[i]&0x3f)
4389 case 0x00: emit_call((int)add_d);break;
4390 case 0x01: emit_call((int)sub_d);break;
4391 case 0x02: emit_call((int)mul_d);break;
4392 case 0x03: emit_call((int)div_d);break;
4393 case 0x04: emit_call((int)sqrt_d);break;
4394 case 0x05: emit_call((int)abs_d);break;
4395 case 0x06: emit_call((int)mov_d);break;
4396 case 0x07: emit_call((int)neg_d);break;
4398 restore_regs(reglist);
4401 cop1_unusable(i, i_regs);
4405 void multdiv_assemble_arm(int i,struct regstat *i_regs)
4412 // case 0x1D: DMULTU
4417 if((opcode2[i]&4)==0) // 32-bit
4419 if(opcode2[i]==0x18) // MULT
4421 signed char m1=get_reg(i_regs->regmap,rs1[i]);
4422 signed char m2=get_reg(i_regs->regmap,rs2[i]);
4423 signed char hi=get_reg(i_regs->regmap,HIREG);
4424 signed char lo=get_reg(i_regs->regmap,LOREG);
4429 emit_smull(m1,m2,hi,lo);
4431 if(opcode2[i]==0x19) // MULTU
4433 signed char m1=get_reg(i_regs->regmap,rs1[i]);
4434 signed char m2=get_reg(i_regs->regmap,rs2[i]);
4435 signed char hi=get_reg(i_regs->regmap,HIREG);
4436 signed char lo=get_reg(i_regs->regmap,LOREG);
4441 emit_umull(m1,m2,hi,lo);
4443 if(opcode2[i]==0x1A) // DIV
4445 signed char d1=get_reg(i_regs->regmap,rs1[i]);
4446 signed char d2=get_reg(i_regs->regmap,rs2[i]);
4449 signed char quotient=get_reg(i_regs->regmap,LOREG);
4450 signed char remainder=get_reg(i_regs->regmap,HIREG);
4451 assert(quotient>=0);
4452 assert(remainder>=0);
4453 emit_movs(d1,remainder);
4454 emit_negmi(remainder,remainder);
4455 emit_movs(d2,HOST_TEMPREG);
4456 emit_jeq((int)out+52); // Division by zero
4457 emit_negmi(HOST_TEMPREG,HOST_TEMPREG);
4458 emit_clz(HOST_TEMPREG,quotient);
4459 emit_shl(HOST_TEMPREG,quotient,HOST_TEMPREG);
4460 emit_orimm(quotient,1<<31,quotient);
4461 emit_shr(quotient,quotient,quotient);
4462 emit_cmp(remainder,HOST_TEMPREG);
4463 emit_subcs(remainder,HOST_TEMPREG,remainder);
4464 emit_adcs(quotient,quotient,quotient);
4465 emit_shrimm(HOST_TEMPREG,1,HOST_TEMPREG);
4466 emit_jcc((int)out-16); // -4
4468 emit_negmi(quotient,quotient);
4470 emit_negmi(remainder,remainder);
4472 if(opcode2[i]==0x1B) // DIVU
4474 signed char d1=get_reg(i_regs->regmap,rs1[i]); // dividend
4475 signed char d2=get_reg(i_regs->regmap,rs2[i]); // divisor
4478 signed char quotient=get_reg(i_regs->regmap,LOREG);
4479 signed char remainder=get_reg(i_regs->regmap,HIREG);
4480 assert(quotient>=0);
4481 assert(remainder>=0);
4483 emit_jeq((int)out+44); // Division by zero
4484 emit_clz(d2,HOST_TEMPREG);
4485 emit_movimm(1<<31,quotient);
4486 emit_shl(d2,HOST_TEMPREG,d2);
4487 emit_mov(d1,remainder);
4488 emit_shr(quotient,HOST_TEMPREG,quotient);
4489 emit_cmp(remainder,d2);
4490 emit_subcs(remainder,d2,remainder);
4491 emit_adcs(quotient,quotient,quotient);
4492 emit_shrcc_imm(d2,1,d2);
4493 emit_jcc((int)out-16); // -4
4498 if(opcode2[i]==0x1C) // DMULT
4500 assert(opcode2[i]!=0x1C);
4501 signed char m1h=get_reg(i_regs->regmap,rs1[i]|64);
4502 signed char m1l=get_reg(i_regs->regmap,rs1[i]);
4503 signed char m2h=get_reg(i_regs->regmap,rs2[i]|64);
4504 signed char m2l=get_reg(i_regs->regmap,rs2[i]);
4513 emit_call((int)&mult64);
4518 signed char hih=get_reg(i_regs->regmap,HIREG|64);
4519 signed char hil=get_reg(i_regs->regmap,HIREG);
4520 if(hih>=0) emit_loadreg(HIREG|64,hih);
4521 if(hil>=0) emit_loadreg(HIREG,hil);
4522 signed char loh=get_reg(i_regs->regmap,LOREG|64);
4523 signed char lol=get_reg(i_regs->regmap,LOREG);
4524 if(loh>=0) emit_loadreg(LOREG|64,loh);
4525 if(lol>=0) emit_loadreg(LOREG,lol);
4527 if(opcode2[i]==0x1D) // DMULTU
4529 signed char m1h=get_reg(i_regs->regmap,rs1[i]|64);
4530 signed char m1l=get_reg(i_regs->regmap,rs1[i]);
4531 signed char m2h=get_reg(i_regs->regmap,rs2[i]|64);
4532 signed char m2l=get_reg(i_regs->regmap,rs2[i]);
4538 if(m1l!=0) emit_mov(m1l,0);
4539 if(m1h==0) emit_readword((int)&dynarec_local,1);
4540 else if(m1h>1) emit_mov(m1h,1);
4541 if(m2l<2) emit_readword((int)&dynarec_local+m2l*4,2);
4542 else if(m2l>2) emit_mov(m2l,2);
4543 if(m2h<3) emit_readword((int)&dynarec_local+m2h*4,3);
4544 else if(m2h>3) emit_mov(m2h,3);
4545 emit_call((int)&multu64);
4546 restore_regs(0x100f);
4547 signed char hih=get_reg(i_regs->regmap,HIREG|64);
4548 signed char hil=get_reg(i_regs->regmap,HIREG);
4549 signed char loh=get_reg(i_regs->regmap,LOREG|64);
4550 signed char lol=get_reg(i_regs->regmap,LOREG);
4551 /*signed char temp=get_reg(i_regs->regmap,-1);
4552 signed char rh=get_reg(i_regs->regmap,HIREG|64);
4553 signed char rl=get_reg(i_regs->regmap,HIREG);
4559 //emit_mov(m1l,EAX);
4561 emit_umull(rl,rh,m1l,m2l);
4562 emit_storereg(LOREG,rl);
4564 //emit_mov(m1h,EAX);
4566 emit_umull(rl,rh,m1h,m2l);
4567 emit_adds(rl,temp,temp);
4568 emit_adcimm(rh,0,rh);
4569 emit_storereg(HIREG,rh);
4570 //emit_mov(m2h,EAX);
4572 emit_umull(rl,rh,m1l,m2h);
4573 emit_adds(rl,temp,temp);
4574 emit_adcimm(rh,0,rh);
4575 emit_storereg(LOREG|64,temp);
4577 //emit_mov(m2h,EAX);
4579 emit_umull(rl,rh,m1h,m2h);
4580 emit_adds(rl,temp,rl);
4581 emit_loadreg(HIREG,temp);
4582 emit_adcimm(rh,0,rh);
4583 emit_adds(rl,temp,rl);
4584 emit_adcimm(rh,0,rh);
4591 emit_call((int)&multu64);
4596 signed char hih=get_reg(i_regs->regmap,HIREG|64);
4597 signed char hil=get_reg(i_regs->regmap,HIREG);
4598 if(hih>=0) emit_loadreg(HIREG|64,hih); // DEBUG
4599 if(hil>=0) emit_loadreg(HIREG,hil); // DEBUG
4601 // Shouldn't be necessary
4602 //char loh=get_reg(i_regs->regmap,LOREG|64);
4603 //char lol=get_reg(i_regs->regmap,LOREG);
4604 //if(loh>=0) emit_loadreg(LOREG|64,loh);
4605 //if(lol>=0) emit_loadreg(LOREG,lol);
4607 if(opcode2[i]==0x1E) // DDIV
4609 signed char d1h=get_reg(i_regs->regmap,rs1[i]|64);
4610 signed char d1l=get_reg(i_regs->regmap,rs1[i]);
4611 signed char d2h=get_reg(i_regs->regmap,rs2[i]|64);
4612 signed char d2l=get_reg(i_regs->regmap,rs2[i]);
4618 if(d1l!=0) emit_mov(d1l,0);
4619 if(d1h==0) emit_readword((int)&dynarec_local,1);
4620 else if(d1h>1) emit_mov(d1h,1);
4621 if(d2l<2) emit_readword((int)&dynarec_local+d2l*4,2);
4622 else if(d2l>2) emit_mov(d2l,2);
4623 if(d2h<3) emit_readword((int)&dynarec_local+d2h*4,3);
4624 else if(d2h>3) emit_mov(d2h,3);
4625 emit_call((int)&div64);
4626 restore_regs(0x100f);
4627 signed char hih=get_reg(i_regs->regmap,HIREG|64);
4628 signed char hil=get_reg(i_regs->regmap,HIREG);
4629 signed char loh=get_reg(i_regs->regmap,LOREG|64);
4630 signed char lol=get_reg(i_regs->regmap,LOREG);
4631 if(hih>=0) emit_loadreg(HIREG|64,hih);
4632 if(hil>=0) emit_loadreg(HIREG,hil);
4633 if(loh>=0) emit_loadreg(LOREG|64,loh);
4634 if(lol>=0) emit_loadreg(LOREG,lol);
4636 if(opcode2[i]==0x1F) // DDIVU
4638 //u_int hr,reglist=0;
4639 //for(hr=0;hr<HOST_REGS;hr++) {
4640 // if(i_regs->regmap[hr]>=0 && (i_regs->regmap[hr]&62)!=HIREG) reglist|=1<<hr;
4642 signed char d1h=get_reg(i_regs->regmap,rs1[i]|64);
4643 signed char d1l=get_reg(i_regs->regmap,rs1[i]);
4644 signed char d2h=get_reg(i_regs->regmap,rs2[i]|64);
4645 signed char d2l=get_reg(i_regs->regmap,rs2[i]);
4651 if(d1l!=0) emit_mov(d1l,0);
4652 if(d1h==0) emit_readword((int)&dynarec_local,1);
4653 else if(d1h>1) emit_mov(d1h,1);
4654 if(d2l<2) emit_readword((int)&dynarec_local+d2l*4,2);
4655 else if(d2l>2) emit_mov(d2l,2);
4656 if(d2h<3) emit_readword((int)&dynarec_local+d2h*4,3);
4657 else if(d2h>3) emit_mov(d2h,3);
4658 emit_call((int)&divu64);
4659 restore_regs(0x100f);
4660 signed char hih=get_reg(i_regs->regmap,HIREG|64);
4661 signed char hil=get_reg(i_regs->regmap,HIREG);
4662 signed char loh=get_reg(i_regs->regmap,LOREG|64);
4663 signed char lol=get_reg(i_regs->regmap,LOREG);
4664 if(hih>=0) emit_loadreg(HIREG|64,hih);
4665 if(hil>=0) emit_loadreg(HIREG,hil);
4666 if(loh>=0) emit_loadreg(LOREG|64,loh);
4667 if(lol>=0) emit_loadreg(LOREG,lol);
4673 // Multiply by zero is zero.
4674 // MIPS does not have a divide by zero exception.
4675 // The result is undefined, we return zero.
4676 signed char hr=get_reg(i_regs->regmap,HIREG);
4677 signed char lr=get_reg(i_regs->regmap,LOREG);
4678 if(hr>=0) emit_zeroreg(hr);
4679 if(lr>=0) emit_zeroreg(lr);
4682 #define multdiv_assemble multdiv_assemble_arm
4684 void do_preload_rhash(int r) {
4685 // Don't need this for ARM. On x86, this puts the value 0xf8 into the
4686 // register. On ARM the hash can be done with a single instruction (below)
4689 void do_preload_rhtbl(int ht) {
4690 emit_addimm(FP,(int)&mini_ht-(int)&dynarec_local,ht);
4693 void do_rhash(int rs,int rh) {
4694 emit_andimm(rs,0xf8,rh);
4697 void do_miniht_load(int ht,int rh) {
4698 assem_debug("ldr %s,[%s,%s]!\n",regname[rh],regname[ht],regname[rh]);
4699 output_w32(0xe7b00000|rd_rn_rm(rh,ht,rh));
4702 void do_miniht_jump(int rs,int rh,int ht) {
4704 emit_ldreq_indexed(ht,4,15);
4705 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
4707 emit_jmp(jump_vaddr_reg[7]);
4709 emit_jmp(jump_vaddr_reg[rs]);
4713 void do_miniht_insert(u_int return_address,int rt,int temp) {
4715 emit_movimm(return_address,rt); // PC into link register
4716 add_to_linker((int)out,return_address,1);
4717 emit_pcreladdr(temp);
4718 emit_writeword(rt,(int)&mini_ht[(return_address&0xFF)>>3][0]);
4719 emit_writeword(temp,(int)&mini_ht[(return_address&0xFF)>>3][1]);
4721 emit_movw(return_address&0x0000FFFF,rt);
4722 add_to_linker((int)out,return_address,1);
4723 emit_pcreladdr(temp);
4724 emit_writeword(temp,(int)&mini_ht[(return_address&0xFF)>>3][1]);
4725 emit_movt(return_address&0xFFFF0000,rt);
4726 emit_writeword(rt,(int)&mini_ht[(return_address&0xFF)>>3][0]);
4730 // Sign-extend to 64 bits and write out upper half of a register
4731 // This is useful where we have a 32-bit value in a register, and want to
4732 // keep it in a 32-bit register, but can't guarantee that it won't be read
4733 // as a 64-bit value later.
4734 void wb_sx(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32_pre,uint64_t is32,uint64_t u,uint64_t uu)
4737 if(is32_pre==is32) return;
4739 for(hr=0;hr<HOST_REGS;hr++) {
4740 if(hr!=EXCLUDE_REG) {
4741 //if(pre[hr]==entry[hr]) {
4742 if((reg=pre[hr])>=0) {
4744 if( ((is32_pre&~is32&~uu)>>reg)&1 ) {
4745 emit_sarimm(hr,31,HOST_TEMPREG);
4746 emit_storereg(reg|64,HOST_TEMPREG);
4756 void wb_valid(signed char pre[],signed char entry[],u_int dirty_pre,u_int dirty,uint64_t is32_pre,uint64_t u,uint64_t uu)
4758 //if(dirty_pre==dirty) return;
4760 for(hr=0;hr<HOST_REGS;hr++) {
4761 if(hr!=EXCLUDE_REG) {
4763 if(((~u)>>(reg&63))&1) {
4764 if(reg==entry[hr]||(reg>0&&entry[hr]<0)) {
4765 if(((dirty_pre&~dirty)>>hr)&1) {
4767 emit_storereg(reg,hr);
4768 if( ((is32_pre&~uu)>>reg)&1 ) {
4769 emit_sarimm(hr,31,HOST_TEMPREG);
4770 emit_storereg(reg|64,HOST_TEMPREG);
4774 emit_storereg(reg,hr);
4778 else // Check if register moved to a different register
4779 if((new_hr=get_reg(entry,reg))>=0) {
4780 if((dirty_pre>>hr)&(~dirty>>new_hr)&1) {
4782 emit_storereg(reg,hr);
4783 if( ((is32_pre&~uu)>>reg)&1 ) {
4784 emit_sarimm(hr,31,HOST_TEMPREG);
4785 emit_storereg(reg|64,HOST_TEMPREG);
4789 emit_storereg(reg,hr);
4799 /* using strd could possibly help but you'd have to allocate registers in pairs
4800 void wb_invalidate_arm(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,uint64_t u,uint64_t uu)
4804 for(hr=HOST_REGS-1;hr>=0;hr--) {
4805 if(hr!=EXCLUDE_REG) {
4806 if(pre[hr]!=entry[hr]) {
4809 if(get_reg(entry,pre[hr])<0) {
4811 if(!((u>>pre[hr])&1)) {
4812 if(hr<10&&(~hr&1)&&(pre[hr+1]<0||wrote==hr+1)) {
4813 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
4814 emit_sarimm(hr,31,hr+1);
4815 emit_strdreg(pre[hr],hr);
4818 emit_storereg(pre[hr],hr);
4820 emit_storereg(pre[hr],hr);
4821 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
4822 emit_sarimm(hr,31,hr);
4823 emit_storereg(pre[hr]|64,hr);
4828 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
4829 emit_storereg(pre[hr],hr);
4839 for(hr=0;hr<HOST_REGS;hr++) {
4840 if(hr!=EXCLUDE_REG) {
4841 if(pre[hr]!=entry[hr]) {
4844 if((nr=get_reg(entry,pre[hr]))>=0) {
4852 #define wb_invalidate wb_invalidate_arm
4855 // Clearing the cache is rather slow on ARM Linux, so mark the areas
4856 // that need to be cleared, and then only clear these areas once.
4857 void do_clear_cache()
4860 for (i=0;i<(1<<(TARGET_SIZE_2-17));i++)
4862 u_int bitmap=needs_clear_cache[i];
4868 start=BASE_ADDR+i*131072+j*4096;
4876 __clear_cache((void *)start,(void *)end);
4882 needs_clear_cache[i]=0;
4887 // CPU-architecture-specific initialization
4889 #ifndef DISABLE_COP1
4890 rounding_modes[0]=0x0<<22; // round
4891 rounding_modes[1]=0x3<<22; // trunc
4892 rounding_modes[2]=0x1<<22; // ceil
4893 rounding_modes[3]=0x2<<22; // floor
4897 // vim:shiftwidth=2:expandtab