1 /* FCE Ultra - NES/Famicom Emulator
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3 * Copyright notice for this file:
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4 * Copyright (C) 2011 CaH4e3
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6 * This program is free software; you can redistribute it and/or modify
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7 * it under the terms of the GNU General Public License as published by
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8 * the Free Software Foundation; either version 2 of the License, or
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9 * (at your option) any later version.
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11 * This program is distributed in the hope that it will be useful,
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12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 * GNU General Public License for more details.
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16 * You should have received a copy of the GNU General Public License
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17 * along with this program; if not, write to the Free Software
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18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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20 * SL12 Protected 3-in-1 mapper hardware (VRC2, MMC3, MMC1)
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21 * the same as 603-5052 board (TODO: add reading registers, merge)
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22 * SL1632 2-in-1 protected board, similar to SL12 (TODO: find difference)
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26 * Garou Densetsu Special (G0904.PCB, Huang-1, GAL dip: W conf.)
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27 * Kart Fighter (008, Huang-1, GAL dip: W conf.)
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28 * Somari (008, C5052-13, GAL dip: P conf., GK2-P/GK2-V maskroms)
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29 * Somari (008, Huang-1, GAL dip: W conf., GK1-P/GK1-V maskroms)
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30 * AV Mei Shao Nv Zhan Shi (aka AV Pretty Girl Fighting) (SL-12 PCB, Hunag-1, GAL dip: unk conf. SL-11A/SL-11B maskroms)
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31 * Samurai Spirits (Full version) (Huang-1, GAL dip: unk conf. GS-2A/GS-4A maskroms)
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32 * Contra Fighter (603-5052 PCB, C5052-3, GAL dip: unk conf. SC603-A/SCB603-B maskroms)
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39 static uint8 vrc2_chr[8], vrc2_prg[2], vrc2_mirr;
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40 static uint8 mmc3_regs[10], mmc3_ctrl, mmc3_mirr;
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41 static uint8 IRQCount,IRQLatch,IRQa;
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42 static uint8 IRQReload;
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43 static uint8 mmc1_regs[4], mmc1_buffer, mmc1_shift;
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45 static SFORMAT StateRegs[]=
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48 {vrc2_chr, 8, "VRCC"},
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49 {vrc2_prg, 2, "VRCP"},
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50 {&vrc2_mirr, 1, "VRCM"},
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51 {mmc3_regs, 10, "M3RG"},
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52 {&mmc3_ctrl, 1, "M3CT"},
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53 {&mmc3_mirr, 1, "M3MR"},
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54 {&IRQReload, 1, "IRQR"},
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55 {&IRQCount, 1, "IRQC"},
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56 {&IRQLatch, 1, "IRQL"},
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58 {mmc1_regs, 4, "M1RG"},
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59 {&mmc1_buffer, 1, "M1BF"},
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60 {&mmc1_shift, 1, "M1MR"},
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64 static void SyncPRG(void)
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68 setprg8(0x8000, vrc2_prg[0]);
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69 setprg8(0xA000, vrc2_prg[1]);
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70 setprg8(0xC000, ~1);
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71 setprg8(0xE000, ~0);
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74 uint32 swap = (mmc3_ctrl >> 5) & 2;
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75 setprg8(0x8000, mmc3_regs[6 + swap]);
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76 setprg8(0xA000, mmc3_regs[7]);
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77 setprg8(0xC000, mmc3_regs[6 + (swap ^ 2)]);
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78 setprg8(0xE000, mmc3_regs[9]);
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83 uint8 bank = mmc1_regs[3] & 0xF;
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84 if(mmc1_regs[0] & 8)
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86 if(mmc1_regs[0] & 4)
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88 setprg16(0x8000, bank);
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89 setprg16(0xC000, 0x0F);
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93 setprg16(0x8000, 0);
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94 setprg16(0xC000, bank);
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98 setprg32(0x8000, bank >> 1);
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104 static void SyncCHR(void)
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106 uint32 base = (mode & 4) << 6;
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109 setchr1(0x0000, base|vrc2_chr[0]);
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110 setchr1(0x0400, base|vrc2_chr[1]);
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111 setchr1(0x0800, base|vrc2_chr[2]);
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112 setchr1(0x0c00, base|vrc2_chr[3]);
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113 setchr1(0x1000, base|vrc2_chr[4]);
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114 setchr1(0x1400, base|vrc2_chr[5]);
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115 setchr1(0x1800, base|vrc2_chr[6]);
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116 setchr1(0x1c00, base|vrc2_chr[7]);
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119 uint32 swap = (mmc3_ctrl & 0x80) << 5;
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120 setchr1(0x0000 ^ swap, base|((mmc3_regs[0])&0xFE));
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121 setchr1(0x0400 ^ swap, base|(mmc3_regs[0]|1));
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122 setchr1(0x0800 ^ swap, base|((mmc3_regs[1])&0xFE));
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123 setchr1(0x0c00 ^ swap, base|(mmc3_regs[1]|1));
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124 setchr1(0x1000 ^ swap, base|mmc3_regs[2]);
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125 setchr1(0x1400 ^ swap, base|mmc3_regs[3]);
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126 setchr1(0x1800 ^ swap, base|mmc3_regs[4]);
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127 setchr1(0x1c00 ^ swap, base|mmc3_regs[5]);
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132 if(mmc1_regs[0]&0x10)
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134 setchr4(0x0000, mmc1_regs[1]);
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135 setchr4(0x1000, mmc1_regs[2]);
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138 setchr8(mmc1_regs[1] >> 1);
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143 static void SyncMIR(void)
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147 setmirror((vrc2_mirr&1)^1);
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151 setmirror((mmc3_mirr&1)^1);
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156 switch(mmc1_regs[0]&3) {
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157 case 0: setmirror(MI_0); break;
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158 case 1: setmirror(MI_1); break;
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159 case 2: setmirror(MI_V); break;
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160 case 3: setmirror(MI_H); break;
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167 static void Sync(void)
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174 static DECLFW(UNLSL12ModeWrite)
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176 // FCEU_printf("%04X:%02X\n",A,V);
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177 if((A & 0x4100) == 0x4100) {
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179 if(A&1) { // hacky hacky, there are two configuration modes on SOMARI HUANG-1 PCBs
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180 // Solder pads with P1/P2 shorted called SOMARI P,
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181 // Solder pads with W1/W2 shorted called SOMARI W
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182 // Both identical 3-in-1 but W wanted MMC1 registers
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183 // to be reset when switch to MMC1 mode P one - doesn't
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184 // There is issue with W version of Somari at starting copyrights
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185 mmc1_regs[0] = 0xc;
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194 static DECLFW(UNLSL12Write)
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196 // FCEU_printf("%04X:%02X\n",A,V);
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199 if((A>=0xB000)&&(A<=0xE003))
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201 int32 ind=((((A&2)|(A>>10))>>1)+2)&7;
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202 int32 sar=((A&1)<<2);
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203 vrc2_chr[ind]=(vrc2_chr[ind]&(0xF0>>sar))|((V&0x0F)<<sar);
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208 case 0x8000: vrc2_prg[0] = V; SyncPRG(); break;
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209 case 0xA000: vrc2_prg[1] = V; SyncPRG(); break;
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210 case 0x9000: vrc2_mirr = V; SyncMIR(); break;
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215 switch(A & 0xE001) {
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217 uint8 old_ctrl = mmc3_ctrl;
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219 if((old_ctrl&0x40) != (mmc3_ctrl&0x40))
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221 if((old_ctrl&0x80) != (mmc3_ctrl&0x80))
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226 mmc3_regs[mmc3_ctrl & 7] = V;
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227 if((mmc3_ctrl & 7) < 6)
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243 X6502_IRQEnd(FCEU_IQEXT);
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256 mmc1_regs[0] |= 0xc;
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257 mmc1_buffer = mmc1_shift = 0;
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262 uint8 n = (A >> 13) - 4;
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263 mmc1_buffer |= (V & 1) << (mmc1_shift++);
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264 if(mmc1_shift == 5)
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266 mmc1_regs[n] = mmc1_buffer;
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267 mmc1_buffer = mmc1_shift = 0;
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281 static void UNLSL12HBIRQ(void)
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283 if((mode & 3) == 1)
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285 int32 count = IRQCount;
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286 if(!count || IRQReload)
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288 IRQCount = IRQLatch;
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296 X6502_IRQBegin(FCEU_IQEXT);
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301 static void StateRestore(int version)
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306 static void UNLSL12Power(void)
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312 vrc2_chr[3] = ~0; // W conf. of Somari wanted CHR3 has to be set to BB bank (or similar), but doesn't do that directly
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330 mmc3_ctrl = mmc3_mirr = IRQCount = IRQLatch = IRQa = 0;
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331 mmc1_regs[0] = 0xc;
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338 SetReadHandler(0x8000,0xFFFF,CartBR);
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339 SetWriteHandler(0x4100,0x7FFF,UNLSL12ModeWrite);
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340 SetWriteHandler(0x8000,0xFFFF,UNLSL12Write);
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343 void UNLSL12_Init(CartInfo *info)
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345 info->Power = UNLSL12Power;
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346 GameHBIRQHook = UNLSL12HBIRQ;
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347 GameStateRestore = StateRestore;
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348 AddExState(&StateRegs, ~0, 0, 0);
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