1 /* FCE Ultra - NES/Famicom Emulator
3 * Copyright notice for this file:
4 * Copyright (C) 2002 Xodnizel
5 * Copyright (C) 2005 CaH4e3
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 // Mapper 090 is simpliest mapper hardware and have not extended nametable control and latched chr banks in 4k mode
26 // Mapper 209 much compicated hardware with decribed above features disabled by default and switchable by command
27 // Mapper 211 the same mapper 209 but with forced nametable control
32 static uint8 IRQMode; // from $c001
33 static uint8 IRQPre; // from $c004
34 static uint8 IRQPreSize; // from $c007
35 static uint8 IRQCount; // from $c005
36 static uint8 IRQXOR; // Loaded from $C006
37 static uint8 IRQa; // $c002, $c003, and $c000
42 static uint8 tkcom[4];
44 static uint8 chrlow[8];
45 static uint8 chrhigh[8];
49 static uint16 names[4];
52 static SFORMAT Tek_StateRegs[]={
53 {&IRQMode, 1, "IRQM"},
55 {&IRQPreSize, 1, "IRQR"},
56 {&IRQCount, 1, "IRQC"},
66 {&names[0], 2|FCEUSTATE_RLSB, "NMS0"},
67 {&names[1], 2|FCEUSTATE_RLSB, "NMS1"},
68 {&names[2], 2|FCEUSTATE_RLSB, "NMS2"},
69 {&names[3], 2|FCEUSTATE_RLSB, "NMS3"},
74 static void mira(void)
76 if((tkcom[0]&0x20&&is209)||is211)
79 if(tkcom[0]&0x40) // Name tables are ROM-only
82 setntamem(CHRptr[0]+(((names[x])&CHRmask1[0])<<10),0,x);
84 else // Name tables can be RAM or ROM.
88 if((tkcom[1]&0x80)==(names[x]&0x80)) // RAM selected.
89 setntamem(NTARAM+((names[x]&0x1)<<10),1,x);
91 setntamem(CHRptr[0]+(((names[x])&CHRmask1[0])<<10),0,x);
99 case 0: setmirror(MI_V); break;
100 case 1: setmirror(MI_H); break;
101 case 2: setmirror(MI_0); break;
102 case 3: setmirror(MI_1); break;
107 static void tekprom(void) // TODO: verify for single, small multi and large multi
109 uint32 bankmode=((tkcom[3]&6)<<5);
112 case 00: if(tkcom[0]&0x80)
113 setprg8(0x6000,(((prgb[3]<<2)+3)&0x3F)|bankmode);
114 setprg32(0x8000,(prgb[3]&7)|((tkcom[3]&7)<<3));
116 case 01: if(tkcom[0]&0x80)
117 setprg8(0x6000,(((prgb[3]<<1)+1)&0x3F)|bankmode);
118 setprg16(0x8000,(prgb[1]&0x0F)|((tkcom[3]&7)<<4));
119 setprg16(0xC000,0x0F|((tkcom[3]&7)<<4));
121 case 03: // bit reversion
124 setprg8(0x6000,(prgb[3]&0x1F)|((tkcom[3]&7)<<5)); // 45in1 multy has different bits, seems board was hacked to support big data banks
125 setprg8(0x8000,(prgb[0]&0x1F)|((tkcom[3]&7)<<5));
126 setprg8(0xa000,(prgb[1]&0x1F)|((tkcom[3]&7)<<5));
127 setprg8(0xc000,(prgb[2]&0x1F)|((tkcom[3]&7)<<5));
128 setprg8(0xe000,0x1F|((tkcom[3]&7)<<5));
129 // setprg8(0xe000,(prgb[3]&0x0F)|((tkcom[3]&6)<<3));
130 // setprg32(0x8000,((prgb[0]&0x0F)>>2)|((tkcom[3]&6)<<3));
132 case 04: if(tkcom[0]&0x80)
133 setprg8(0x6000,(((prgb[3]<<2)+3)&0x3F)|bankmode);
134 setprg32(0x8000,(prgb[3]&0x0F)|((tkcom[3]&6)<<3));
136 case 05: if(tkcom[0]&0x80)
137 setprg8(0x6000,(((prgb[3]<<1)+1)&0x3F)|bankmode);
138 setprg16(0x8000,(prgb[1]&0x1F)|((tkcom[3]&6)<<4));
139 setprg16(0xC000,(prgb[3]&0x1F)|((tkcom[3]&6)<<4));
141 case 07: // bit reversion
142 case 06: if(tkcom[0]&0x80)
143 setprg8(0x6000,(prgb[3]&0x3F)|bankmode);
144 setprg8(0x8000,(prgb[0]&0x3F)|bankmode);
145 setprg8(0xa000,(prgb[1]&0x3F)|bankmode);
146 setprg8(0xc000,(prgb[2]&0x3F)|bankmode);
147 setprg8(0xe000,(prgb[3]&0x3F)|bankmode);
152 static void tekvrom(void)
154 int x, bank=0, mask=0xFFFF;
157 bank=(tkcom[3]&1)|((tkcom[3]&0x18)>>2);
158 switch (tkcom[0]&0x18)
160 case 0x00: bank<<=5; mask=0x1F; break;
161 case 0x08: bank<<=6; mask=0x3F; break;
162 case 0x10: bank<<=7; mask=0x7F; break;
163 case 0x18: bank<<=8; mask=0xFF; break;
166 switch(tkcom[0]&0x18)
169 setchr8(((chrlow[0]|(chrhigh[0]<<8))&mask)|bank);
173 // setchr4(x<<10,((chrlow[x]|(chrhigh[x]<<8))&mask)|bank);
174 setchr4(0x0000,((chrlow[chr[0]]|(chrhigh[chr[0]]<<8))&mask)|bank);
175 setchr4(0x1000,((chrlow[chr[1]]|(chrhigh[chr[1]]<<8))&mask)|bank);
179 setchr2(x<<10,((chrlow[x]|(chrhigh[x]<<8))&mask)|bank);
183 setchr1(x<<10,((chrlow[x]|(chrhigh[x]<<8))&mask)|bank);
188 static DECLFW(M90TekWrite)
192 case 0x5800: mul[0]=V; break;
193 case 0x5801: mul[1]=V; break;
194 case 0x5803: regie=V; break;
198 static DECLFR(M90TekRead)
202 case 0x5800: return (mul[0]*mul[1]);
203 case 0x5801: return((mul[0]*mul[1])>>8);
204 case 0x5803: return (regie);
205 default: return tekker;
210 static DECLFW(M90PRGWrite)
212 // FCEU_printf("bs %04x %02x\n",A,V);
217 static DECLFW(M90CHRlowWrite)
219 // FCEU_printf("bs %04x %02x\n",A,V);
224 static DECLFW(M90CHRhiWrite)
226 // FCEU_printf("bs %04x %02x\n",A,V);
231 static DECLFW(M90NTWrite)
233 // FCEU_printf("bs %04x %02x\n",A,V);
247 static DECLFW(M90IRQWrite)
249 // FCEU_printf("bs %04x %02x\n",A,V);
252 case 00: //FCEU_printf("%s IRQ (C000)\n",V&1?"Enable":"Disable");
253 IRQa=V&1;if(!(V&1)) X6502_IRQEnd(FCEU_IQEXT);break;
254 case 02: //FCEU_printf("Disable IRQ (C002) scanline=%d\n", scanline);
255 IRQa=0;X6502_IRQEnd(FCEU_IQEXT);break;
256 case 03: //FCEU_printf("Enable IRQ (C003) scanline=%d\n", scanline);
259 /*FCEU_printf("IRQ Count method: ");
262 case 00: FCEU_printf("M2 cycles\n");break;
263 case 01: FCEU_printf("PPU A12 toggles\n");break;
264 case 02: FCEU_printf("PPU reads\n");break;
265 case 03: FCEU_printf("Writes to CPU space\n");break;
267 FCEU_printf("Counter prescaler size: %s\n",(IRQMode&4)?"3 bits":"8 bits");
268 FCEU_printf("Counter prescaler size adjust: %s\n",(IRQMode&8)?"Used C007":"Normal Operation");
269 if((IRQMode>>6)==2) FCEU_printf("Counter Down\n");
270 else if((IRQMode>>6)==1) FCEU_printf("Counter Up\n");
271 else FCEU_printf("Counter Stopped\n");*/
273 case 04: //FCEU_printf("Pre Counter Loaded and Xored wiht C006: %d\n",V^IRQXOR);
274 IRQPre=V^IRQXOR;break;
275 case 05: //FCEU_printf("Main Counter Loaded and Xored wiht C006: %d\n",V^IRQXOR);
276 IRQCount=V^IRQXOR;break;
277 case 06: //FCEU_printf("Xor Value: %d\n",V);
279 case 07: //if(!(IRQMode&8)) FCEU_printf("C001 is clear, no effect applied\n");
280 // else if(V==0xFF) FCEU_printf("Prescaler is changed for 12bits\n");
281 // else FCEU_printf("Counter Stopped\n");
286 static DECLFW(M90ModeWrite)
288 // FCEU_printf("bs %04x %02x\n",A,V);
297 case 00: FCEU_printf("Main Control Register:\n");
298 FCEU_printf(" PGR Banking mode: %d\n",V&7);
299 FCEU_printf(" CHR Banking mode: %d\n",(V>>3)&3);
300 FCEU_printf(" 6000-7FFF addresses mapping: %s\n",(V&0x80)?"Yes":"No");
301 FCEU_printf(" Nametable control: %s\n",(V&0x20)?"Enabled":"Disabled");
303 FCEU_printf(" Nametable can be: %s\n",(V&0x40)?"ROM Only":"RAM or ROM");
305 case 01: FCEU_printf("Mirroring mode: ");
308 case 0: FCEU_printf("Vertical\n");break;
309 case 1: FCEU_printf("Horizontal\n");break;
310 case 2: FCEU_printf("Nametable 0 only\n");break;
311 case 3: FCEU_printf("Nametable 1 only\n");break;
313 FCEU_printf("Mirroring flag: %s\n",(V&0x80)?"On":"Off");
315 case 02: if((((tkcom[0])>>5)&3)==1)
316 FCEU_printf("Nametable ROM/RAM select mode: %d\n",V>>7);
319 FCEU_printf("CHR Banking mode: %s\n",(V&0x20)?"Entire CHR ROM":"256Kb Switching mode");
320 if(!(V&0x20)) FCEU_printf("256K CHR bank number: %02x\n",(V&1)|((V&0x18)>>2));
321 FCEU_printf("512K PRG bank number: %d\n",(V&6)>>1);
322 FCEU_printf("CHR Bank mirroring: %s\n",(V&0x80)?"Swapped":"Normal operate");
327 static DECLFW(M90DummyWrite)
329 // FCEU_printf("bs %04x %02x\n",A,V);
332 static void CCL(void)
334 if((IRQMode>>6) == 1) // Count Up
337 if((IRQCount == 0) && IRQa)
339 X6502_IRQBegin(FCEU_IQEXT);
342 else if((IRQMode>>6) == 2) // Count down
345 if((IRQCount == 0xFF) && IRQa)
347 X6502_IRQBegin(FCEU_IQEXT);
352 static void ClockCounter(void)
360 if((IRQMode>>6) == 1) // Count up
363 if((IRQPre & premask) == 0) CCL();
365 else if((IRQMode>>6) == 2) // Count down
368 if((IRQPre & premask) == premask) CCL();
372 void FP_FASTAPASS(1) CPUWrap(int a)
375 if((IRQMode&3)==0) for(x=0;x<a;x++) ClockCounter();
378 static void SLWrap(void)
381 if((IRQMode&3)==1) for(x=0;x<8;x++) ClockCounter();
384 static uint32 lastread;
385 static void FP_FASTAPASS(1) M90PPU(uint32 A)
401 if(h<0x20&&((h&0x0F)==0xF))
406 chr[(h&0x10)>>4]=((h&0x10)>>2);
411 chr[(h&0x10)>>4]=((h&0x10)>>2)|2;
423 static void togglie()
427 FCEU_printf("tekker=%02x\n",tekker);
428 memset(tkcom,0x00,sizeof(tkcom));
429 memset(prgb,0xff,sizeof(prgb));
434 static void M90Restore(int version)
441 static void M90Power(void)
443 SetWriteHandler(0x5000,0x5fff,M90TekWrite);
444 SetWriteHandler(0x8000,0x8ff0,M90PRGWrite);
445 SetWriteHandler(0x9000,0x9fff,M90CHRlowWrite);
446 SetWriteHandler(0xA000,0xAfff,M90CHRhiWrite);
447 SetWriteHandler(0xB000,0xBfff,M90NTWrite);
448 SetWriteHandler(0xC000,0xCfff,M90IRQWrite);
449 SetWriteHandler(0xD000,0xD5ff,M90ModeWrite);
450 SetWriteHandler(0xE000,0xFfff,M90DummyWrite);
452 SetReadHandler(0x5000,0x5fff,M90TekRead);
453 SetReadHandler(0x6000,0xffff,CartBR);
455 mul[0]=mul[1]=regie=0xFF;
457 memset(tkcom,0x00,sizeof(tkcom));
458 memset(prgb,0xff,sizeof(prgb));
459 memset(chrlow,0xff,sizeof(chrlow));
460 memset(chrhigh,0xff,sizeof(chrhigh));
461 memset(names,0x00,sizeof(names));
473 void Mapper90_Init(CartInfo *info)
478 info->Power=M90Power;
481 GameHBIRQHook2=SLWrap;
482 GameStateRestore=M90Restore;
483 AddExState(Tek_StateRegs, ~0, 0, 0);
486 void Mapper209_Init(CartInfo *info)
491 info->Power=M90Power;
494 GameHBIRQHook2=SLWrap;
495 GameStateRestore=M90Restore;
496 AddExState(Tek_StateRegs, ~0, 0, 0);
499 void Mapper211_Init(CartInfo *info)
503 info->Power=M90Power;
506 GameHBIRQHook2=SLWrap;
507 GameStateRestore=M90Restore;
508 AddExState(Tek_StateRegs, ~0, 0, 0);