1 /* FCE Ultra - NES/Famicom Emulator
3 * Copyright notice for this file:
4 * Copyright (C) 2002 Xodnizel
5 * Copyright (C) 2005 CaH4e3
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
28 static uint8 IRQMode; // from $c001
29 static uint8 IRQPre; // from $c004
30 static uint8 IRQPreSize; // from $c007
31 static uint8 IRQCount; // from $c005
32 static uint8 IRQXOR; // Loaded from $C006
33 static uint8 IRQa; // $c002, $c003, and $c000
38 static uint8 tkcom[4];
40 static uint8 chrlow[8];
41 static uint8 chrhigh[8];
43 static uint16 names[4];
46 static SFORMAT Tek_StateRegs[]={
47 {&IRQMode, 1, "IRQMODE"},
48 {&IRQPre, 1, "IRQPRE"},
49 {&IRQPreSize, 1, "IRQPRESIZE"},
50 {&IRQCount, 1, "IRQC"},
51 {&IRQXOR, 1, "IRQXOR"},
59 {&names[0], 2|FCEUSTATE_RLSB, "NMS0"},
60 {&names[1], 2|FCEUSTATE_RLSB, "NMS1"},
61 {&names[2], 2|FCEUSTATE_RLSB, "NMS2"},
62 {&names[3], 2|FCEUSTATE_RLSB, "NMS3"},
67 static void mira(void)
69 if((tkcom[0]&0x20&&is209)||is211)
72 if(tkcom[0]&0x40) // Name tables are ROM-only
75 setntamem(CHRptr[0]+(((names[x])&CHRmask1[0])<<10),0,x);
77 else // Name tables can be RAM or ROM.
81 if((tkcom[1]&0x80)==(names[x]&0x80)) // RAM selected.
82 setntamem(NTARAM+((names[x]&0x1)<<10),1,x);
84 setntamem(CHRptr[0]+(((names[x])&CHRmask1[0])<<10),0,x);
92 case 0: setmirror(MI_V); break;
93 case 1: setmirror(MI_H); break;
94 case 2: setmirror(MI_0); break;
95 case 3: setmirror(MI_1); break;
100 static void tekprom(void)
102 uint32 bankmode=((tkcom[3]&6)<<5);
105 case 00: if(tkcom[0]&0x80)
106 setprg8(0x6000,(((prgb[3]<<2)+3)&0x3F)|bankmode);
107 setprg32(0x8000,0x0F|((tkcom[3]&6)<<3));
109 case 01: if(tkcom[0]&0x80)
110 setprg8(0x6000,(((prgb[3]<<1)+1)&0x3F)|bankmode);
111 setprg16(0x8000,(prgb[1]&0x1F)|((tkcom[3]&6)<<4));
112 setprg16(0xC000,0x1F|((tkcom[3]&6)<<4));
114 case 03: // bit reversion
115 case 02: if(tkcom[0]&0x80)
116 setprg8(0x6000,(prgb[3]&0x3F)|bankmode);
117 setprg8(0x8000,(prgb[0]&0x3F)|bankmode);
118 setprg8(0xa000,(prgb[1]&0x3F)|bankmode);
119 setprg8(0xc000,(prgb[2]&0x3F)|bankmode);
120 setprg8(0xe000,0x3F|bankmode);
122 case 04: if(tkcom[0]&0x80)
123 setprg8(0x6000,(((prgb[3]<<2)+3)&0x3F)|bankmode);
124 setprg32(0x8000,(prgb[3]&0x0F)|((tkcom[3]&6)<<3));
126 case 05: if(tkcom[0]&0x80)
127 setprg8(0x6000,(((prgb[3]<<1)+1)&0x3F)|bankmode);
128 setprg16(0x8000,(prgb[1]&0x1F)|((tkcom[3]&6)<<4));
129 setprg16(0xC000,(prgb[3]&0x1F)|((tkcom[3]&6)<<4));
131 case 07: // bit reversion
132 case 06: if(tkcom[0]&0x80)
133 setprg8(0x6000,(prgb[3]&0x3F)|bankmode);
134 setprg8(0x8000,(prgb[0]&0x3F)|bankmode);
135 setprg8(0xa000,(prgb[1]&0x3F)|bankmode);
136 setprg8(0xc000,(prgb[2]&0x3F)|bankmode);
137 setprg8(0xe000,(prgb[3]&0x3F)|bankmode);
142 static void tekvrom(void)
144 int x, bank=0, mask=0xFFFF;
147 bank=(tkcom[3]&1)|((tkcom[3]&0x18)>>2);
148 switch (tkcom[0]&0x18)
150 case 0x00: bank<<=5; mask=0x1F; break;
151 case 0x08: bank<<=6; mask=0x3F; break;
152 case 0x10: bank<<=7; mask=0x7F; break;
153 case 0x18: bank<<=8; mask=0xFF; break;
156 switch(tkcom[0]&0x18)
159 setchr8(((chrlow[0]|(chrhigh[0]<<8))&mask)|bank);
163 setchr4(x<<10,((chrlow[x]|(chrhigh[x]<<8))&mask)|bank);
167 setchr2(x<<10,((chrlow[x]|(chrhigh[x]<<8))&mask)|bank);
171 setchr1(x<<10,((chrlow[x]|(chrhigh[x]<<8))&mask)|bank);
176 static DECLFW(M90TekWrite)
180 case 0x5800: mul[0]=V; break;
181 case 0x5801: mul[1]=V; break;
182 case 0x5803: regie=V; break;
186 static DECLFR(M90TekRead)
190 case 0x5800: return (mul[0]*mul[1]);
191 case 0x5801: return((mul[0]*mul[1])>>8);
192 case 0x5803: return (regie);
197 static DECLFW(M90PRGWrite)
203 static DECLFW(M90CHRlowWrite)
209 static DECLFW(M90CHRhiWrite)
215 static DECLFW(M90NTWrite)
230 static DECLFW(M90IRQWrite)
234 case 00: //FCEU_printf("%s IRQ (C000)\n",V&1?"Enable":"Disable");
235 IRQa=V&1;if(!(V&1)) X6502_IRQEnd(FCEU_IQEXT);break;
236 case 02: //FCEU_printf("Disable IRQ (C002) scanline=%d\n", scanline);
237 IRQa=0;X6502_IRQEnd(FCEU_IQEXT);break;
238 case 03: //FCEU_printf("Enable IRQ (C003) scanline=%d\n", scanline);
241 /* FCEU_printf("IRQ Count method: ");
244 case 00: FCEU_printf("M2 cycles\n");break;
245 case 01: FCEU_printf("PPU A12 toggles\n");break;
246 case 02: FCEU_printf("PPU reads\n");break;
247 case 03: FCEU_printf("Writes to CPU space\n");break;
249 FCEU_printf("Counter prescaler size: %s\n",(IRQMode&4)?"3 bits":"8 bits");
250 FCEU_printf("Counter prescaler size adjust: %s\n",(IRQMode&8)?"Used C007":"Normal Operation");
251 if((IRQMode>>6)==2) FCEU_printf("Counter Down\n");
252 else if((IRQMode>>6)==1) FCEU_printf("Counter Up\n");
253 else FCEU_printf("Counter Stopped\n");
255 case 04: //FCEU_printf("Pre Counter Loaded and Xored wiht C006: %d\n",V^IRQXOR);
256 IRQPre=V^IRQXOR;break;
257 case 05: //FCEU_printf("Main Counter Loaded and Xored wiht C006: %d\n",V^IRQXOR);
258 IRQCount=V^IRQXOR;break;
259 case 06: //FCEU_printf("Xor Value: %d\n",V);
261 case 07: //if(!(IRQMode&8)) FCEU_printf("C001 is clear, no effect applied\n");
262 // else if(V==0xFF) FCEU_printf("Prescaler is changed for 12bits\n");
263 // else FCEU_printf("Counter Stopped\n");
268 static DECLFW(M90ModeWrite)
278 case 00: FCEU_printf("Main Control Register:\n");
279 FCEU_printf(" PGR Banking mode: %d\n",V&7);
280 FCEU_printf(" CHR Banking mode: %d\n",(V>>3)&3);
281 FCEU_printf(" 6000-7FFF addresses mapping: %s\n",(V&0x80)?"Yes":"No");
282 FCEU_printf(" Nametable control: %s\n",(V&0x20)?"Enabled":"Disabled");
284 FCEU_printf(" Nametable can be: %s\n",(V&0x40)?"ROM Only":"RAM or ROM");
286 case 01: FCEU_printf("Mirroring mode: ");
289 case 0: FCEU_printf("Vertical\n");break;
290 case 1: FCEU_printf("Horizontal\n");break;
291 case 2: FCEU_printf("Nametable 0 only\n");break;
292 case 3: FCEU_printf("Nametable 1 only\n");break;
294 FCEU_printf("Mirroring flag: %s\n",(V&0x80)?"On":"Off");
296 case 02: if((((tkcom[0])>>5)&3)==1)
297 FCEU_printf("Nametable ROM/RAM select mode: %d\n",V>>7);
300 FCEU_printf("CHR Banking mode: %s\n",(V&0x20)?"Entire CHR ROM":"256Kb Switching mode");
301 if(!(V&0x20)) FCEU_printf("256K CHR bank number: %02x\n",(V&1)|((V&0x18)>>2));
302 FCEU_printf("512K PRG bank number: %d\n",(V&6)>>1);
303 FCEU_printf("CHR Bank mirroring: %s\n",(V&0x80)?"Swapped":"Normal operate");
308 static void CCL(void)
310 if((IRQMode>>6) == 1) // Count Up
313 if((IRQCount == 0) && IRQa)
315 X6502_IRQBegin(FCEU_IQEXT);
318 else if((IRQMode>>6) == 2) // Count down
321 if((IRQCount == 0xFF) && IRQa)
323 X6502_IRQBegin(FCEU_IQEXT);
328 static void ClockCounter(void)
336 if((IRQMode>>6) == 1) // Count up
339 if((IRQPre & premask) == 0) CCL();
341 else if((IRQMode>>6) == 2) // Count down
344 if((IRQPre & premask) == premask) CCL();
348 void FP_FASTAPASS(1) CPUWrap(int a)
351 if((IRQMode&3)==0) for(x=0;x<a;x++) ClockCounter();
354 static void SLWrap(void)
357 if((IRQMode&3)==1) for(x=0;x<8;x++) ClockCounter();
360 static uint32 lastread;
361 static void FP_FASTAPASS(1) M90PPU(uint32 A)
374 // if((!lastread)&&(A&0x1000))
376 // lastread=A&0x1000;
381 static void togglie()
389 FCEU_printf("tekker=%04x\n",tekker);
390 memset(tkcom,0x00,sizeof(tkcom));
391 memset(prgb,0xff,sizeof(prgb));
396 static void M90Restore(int version)
403 static void M90Power(void)
405 SetWriteHandler(0x5000,0x5fff,M90TekWrite);
406 SetWriteHandler(0x8000,0x8fff,M90PRGWrite);
407 SetWriteHandler(0x9000,0x9fff,M90CHRlowWrite);
408 SetWriteHandler(0xA000,0xAfff,M90CHRhiWrite);
409 SetWriteHandler(0xB000,0xBfff,M90NTWrite);
410 SetWriteHandler(0xC000,0xCfff,M90IRQWrite);
411 SetWriteHandler(0xD000,0xDfff,M90ModeWrite);
413 SetReadHandler(0x5000,0x5fff,M90TekRead);
414 SetReadHandler(0x6000,0xffff,CartBR);
416 mul[0]=mul[1]=regie=0xFF;
418 memset(tkcom,0x00,sizeof(tkcom));
419 memset(prgb,0xff,sizeof(prgb));
420 memset(chrlow,0xff,sizeof(chrlow));
421 memset(chrhigh,0xff,sizeof(chrhigh));
422 memset(names,0x00,sizeof(names));
434 void Mapper90_Init(CartInfo *info)
439 info->Power=M90Power;
441 GameHBIRQHook2=SLWrap;
443 GameStateRestore=M90Restore;
444 AddExState(Tek_StateRegs, ~0, 0, 0);
447 void Mapper209_Init(CartInfo *info)
452 info->Power=M90Power;
453 GameHBIRQHook2=SLWrap;
454 GameStateRestore=M90Restore;
455 AddExState(Tek_StateRegs, ~0, 0, 0);
458 void Mapper211_Init(CartInfo *info)
462 info->Power=M90Power;
463 GameHBIRQHook2=SLWrap;
464 GameStateRestore=M90Restore;
465 AddExState(Tek_StateRegs, ~0, 0, 0);