1 /* FCE Ultra - NES/Famicom Emulator
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3 * Copyright notice for this file:
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4 * Copyright (C) 2007-2010 CaH4e3
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6 * This program is free software; you can redistribute it and/or modify
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7 * it under the terms of the GNU General Public License as published by
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8 * the Free Software Foundation; either version 2 of the License, or
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9 * (at your option) any later version.
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11 * This program is distributed in the hope that it will be useful,
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12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 * GNU General Public License for more details.
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16 * You should have received a copy of the GNU General Public License
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17 * along with this program; if not, write to the Free Software
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18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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20 * VR02/VT03 Console and OneBus System
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22 * Street Dance (Dance pad) (Unl)
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23 * 101-in-1 Arcade Action II
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24 * DreamGEAR 75-in-1, etc.
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30 // General Purpose Registers
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31 static uint8 cpu410x[16], ppu201x[16], apu40xx[64];
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34 static uint8 IRQCount, IRQa, IRQReload;
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35 #define IRQLatch cpu410x[0x1]
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38 static uint8 inv_hack = 0; // some OneBus Systems have swapped PRG reg commans in MMC3 inplementation,
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39 // trying to autodetect unusual behavior, due not to add a new mapper.
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40 #define mmc3cmd cpu410x[0x5]
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41 #define mirror cpu410x[0x6]
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44 static uint8 pcm_enable = 0, pcm_irq = 0;
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45 static int16 pcm_addr, pcm_size, pcm_latch, pcm_clock = 0xF6;
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47 static writefunc defapuwrite[64];
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48 static readfunc defapuread[64];
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50 static SFORMAT StateRegs[]=
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52 {cpu410x, 16, "REGC"},
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53 {ppu201x, 16, "REGS"},
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54 {apu40xx, 64, "REGA"},
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55 {&IRQReload, 1, "IRQR"},
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56 {&IRQCount, 1, "IRQC"},
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58 {&pcm_enable, 1, "PCME"},
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59 {&pcm_irq, 1, "PCMI"},
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60 {&pcm_addr, 2, "PCMA"},
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61 {&pcm_size, 2, "PCMS"},
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62 {&pcm_latch, 2, "PCML"},
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63 {&pcm_clock, 2, "PCMC"},
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67 static void PSync(void)
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69 uint8 bankmode = cpu410x[0xb] & 7;
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70 uint8 mask = (bankmode == 0x7)?(0xff):(0x3f >> bankmode);
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71 uint32 block = ((cpu410x[0x0] & 0xf0) << 4) + (cpu410x[0xa] & (~mask));
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72 uint32 pswap = (mmc3cmd & 0x40) << 8;
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74 // uint8 bank0 = (cpu410x[0xb] & 0x40)?(~1):(cpu410x[0x7]);
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75 // uint8 bank1 = cpu410x[0x8];
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76 // uint8 bank2 = (cpu410x[0xb] & 0x40)?(cpu410x[0x9]):(~1);
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77 // uint8 bank3 = ~0;
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78 uint8 bank0 = cpu410x[0x7^inv_hack];
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79 uint8 bank1 = cpu410x[0x8^inv_hack];
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80 uint8 bank2 = (cpu410x[0xb] & 0x40)?(cpu410x[0x9]):(~1);
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83 // FCEU_printf(" PRG: %04x [%02x]",0x8000^pswap,block | (bank0 & mask));
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84 setprg8(0x8000^pswap, block | (bank0 & mask));
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85 // FCEU_printf(" %04x [%02x]",0xa000^pswap,block | (bank1 & mask));
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86 setprg8(0xa000, block | (bank1 & mask));
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87 // FCEU_printf(" %04x [%02x]",0xc000^pswap,block | (bank2 & mask));
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88 setprg8(0xc000^pswap, block | (bank2 & mask));
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89 // FCEU_printf(" %04x [%02x]\n",0xe000^pswap,block | (bank3 & mask));
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90 setprg8(0xe000, block | (bank3 & mask));
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93 static void CSync(void)
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95 static const uint8 midx[8] = {0, 1, 2, 0, 3, 4, 5, 0 };
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96 uint8 mask = 0xff >> midx[ppu201x[0xa] & 7];
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97 uint32 block = ((cpu410x[0x0] & 0x0f) << 11) + ((ppu201x[0x8] & 0x70) << 4) + (ppu201x[0xa] & (~mask));
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98 uint32 cswap = (mmc3cmd & 0x80) << 5;
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100 uint8 bank0 = ppu201x[0x6]&(~1);
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101 uint8 bank1 = ppu201x[0x6]|1;
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102 uint8 bank2 = ppu201x[0x7]&(~1);
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103 uint8 bank3 = ppu201x[0x7]|1;
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104 uint8 bank4 = ppu201x[0x2];
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105 uint8 bank5 = ppu201x[0x3];
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106 uint8 bank6 = ppu201x[0x4];
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107 uint8 bank7 = ppu201x[0x5];
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109 setchr1(0x0000^cswap, block | (bank0 & mask));
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110 setchr1(0x0400^cswap, block | (bank1 & mask));
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111 setchr1(0x0800^cswap, block | (bank2 & mask));
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112 setchr1(0x0c00^cswap, block | (bank3 & mask));
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113 setchr1(0x1000^cswap, block | (bank4 & mask));
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114 setchr1(0x1400^cswap, block | (bank5 & mask));
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115 setchr1(0x1800^cswap, block | (bank6 & mask));
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116 setchr1(0x1c00^cswap, block | (bank7 & mask));
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118 setmirror((mirror & 1) ^ 1);
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121 static void Sync(void)
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127 static DECLFW(UNLOneBusWriteCPU410X)
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129 // FCEU_printf("CPU %04x:%04x\n",A,V);
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132 case 0x1: IRQLatch = V & 0xfe; break;
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133 case 0x2: IRQReload = 1; break;
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134 case 0x3: X6502_IRQEnd(FCEU_IQEXT); IRQa = 0; break;
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135 case 0x4: IRQa = 1; break;
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137 cpu410x[A & 0xf] = V;
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142 static DECLFW(UNLOneBusWritePPU201X)
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144 // FCEU_printf("PPU %04x:%04x\n",A,V);
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145 ppu201x[A & 0x0f] = V;
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149 static DECLFW(UNLOneBusWriteMMC3)
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151 // FCEU_printf("MMC %04x:%04x\n",A,V);
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154 case 0x8000: mmc3cmd = (mmc3cmd & 0x38) | (V & 0xc7); Sync(); break;
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157 switch(mmc3cmd & 7)
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159 case 0: ppu201x[0x6] = V; CSync(); break;
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160 case 1: ppu201x[0x7] = V; CSync(); break;
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161 case 2: ppu201x[0x2] = V; CSync(); break;
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162 case 3: ppu201x[0x3] = V; CSync(); break;
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163 case 4: ppu201x[0x4] = V; CSync(); break;
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164 case 5: ppu201x[0x5] = V; CSync(); break;
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165 case 6: cpu410x[0x7] = V; PSync(); break;
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166 case 7: cpu410x[0x8] = V; PSync(); break;
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170 case 0xa000: mirror = V; CSync(); break;
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171 case 0xc000: IRQLatch = V & 0xfe; break;
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172 case 0xc001: IRQReload = 1; break;
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173 case 0xe000: X6502_IRQEnd(FCEU_IQEXT); IRQa = 0; break;
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174 case 0xe001: IRQa = 1; break;
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178 static void UNLOneBusIRQHook(void)
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180 int count = IRQCount;
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181 if(!count || IRQReload)
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183 IRQCount = IRQLatch;
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188 if(count && !IRQCount)
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191 X6502_IRQBegin(FCEU_IQEXT);
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195 static DECLFW(UNLOneBusWriteAPU40XX)
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197 // FCEU_printf("APU %04x:%04x\n",A,V);
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198 apu40xx[A & 0x3f] = V;
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202 if(apu40xx[0x30] & 0x10)
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207 if(apu40xx[0x30] & 0x10)
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209 pcm_size = (V << 4) + 1;
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212 if(apu40xx[0x30] & 0x10)
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214 pcm_enable = V&0x10;
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217 X6502_IRQEnd(FCEU_IQEXT);
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221 pcm_latch = pcm_clock;
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225 defapuwrite[A & 0x3f](A, V);
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228 static DECLFR(UNLOneBusReadAPU40XX)
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230 uint8 result = defapuread[A & 0x3f](A);
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231 // FCEU_printf("read %04x, %02x\n",A,result);
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235 if(apu40xx[0x30] & 0x10)
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237 result = (result & 0x7f) | pcm_irq;
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243 static void UNLOneBusCpuHook(int a)
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250 pcm_latch+=pcm_clock;
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256 X6502_IRQBegin(FCEU_IQEXT);
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260 uint8 raw_pcm = ARead[pcm_addr](pcm_addr) >> 1;
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261 defapuwrite[0x11](0x4011,raw_pcm);
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269 static void UNLOneBusPower(void)
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272 IRQReload = IRQCount = IRQa = 0;
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274 memset(cpu410x, 0x00, sizeof(cpu410x));
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275 memset(ppu201x, 0x00, sizeof(ppu201x));
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276 memset(apu40xx, 0x00, sizeof(apu40xx));
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278 SetupCartCHRMapping(0, PRGptr[0], PRGsize[0], 0);
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280 for(i=0; i<64; i++)
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282 defapuread[i] = GetReadHandler(0x4000|i);
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283 defapuwrite[i] = GetWriteHandler(0x4000|i);
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285 SetReadHandler(0x4000,0x403f,UNLOneBusReadAPU40XX);
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286 SetWriteHandler(0x4000,0x403f,UNLOneBusWriteAPU40XX);
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288 SetReadHandler(0x8000,0xFFFF,CartBR);
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289 SetWriteHandler(0x2010,0x201f,UNLOneBusWritePPU201X);
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290 SetWriteHandler(0x4100,0x410f,UNLOneBusWriteCPU410X);
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291 SetWriteHandler(0x8000,0xffff,UNLOneBusWriteMMC3);
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296 static void UNLOneBusReset(void)
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298 IRQReload = IRQCount = IRQa = 0;
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300 memset(cpu410x, 0x00, sizeof(cpu410x));
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301 memset(ppu201x, 0x00, sizeof(ppu201x));
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302 memset(apu40xx, 0x00, sizeof(apu40xx));
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307 static void StateRestore(int version)
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312 void UNLOneBus_Init(CartInfo *info)
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314 info->Power=UNLOneBusPower;
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315 info->Reset=UNLOneBusReset;
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317 if(((*(uint32*)&(info->MD5)) == 0x305fcdc3) || // PowerJoy Supermax Carts
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318 ((*(uint32*)&(info->MD5)) == 0x6abfce8e) )
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321 GameHBIRQHook=UNLOneBusIRQHook;
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322 MapIRQHook=UNLOneBusCpuHook;
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323 GameStateRestore=StateRestore;
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324 AddExState(&StateRegs, ~0, 0, 0);
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