2 * Copyright (C) 2012-2023 Free Software Foundation, Inc.
4 * This file is part of GNU lightning.
6 * GNU lightning is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU Lesser General Public License as published
8 * by the Free Software Foundation; either version 3, or (at your option)
11 * GNU lightning is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
14 * License for more details.
17 * Paulo Cesar Pereira de Andrade
21 /* FIXME Should need qemu 7.2 -- apparently broken with qemu 7.0 */
22 #define PCREL_BROKEN 1
26 #if __BYTE_ORDER == __LITTLE_ENDIAN
27 struct { jit_uint32_t _:26; jit_uint32_t b : 6; } hc;
28 struct { jit_uint32_t _:21; jit_uint32_t b : 5; } rs;
29 struct { jit_uint32_t _:21; jit_uint32_t b : 5; } fm;
30 struct { jit_uint32_t _:21; jit_uint32_t b : 5; } fr;
31 struct { jit_uint32_t _:18; jit_uint32_t b : 3; } pD;
32 struct { jit_uint32_t _:19; jit_uint32_t b : 2; } pW;
33 struct { jit_uint32_t _:16; jit_uint32_t b : 5; } rt;
34 struct { jit_uint32_t _:16; jit_uint32_t b : 5; } ft;
35 struct { jit_uint32_t _:11; jit_uint32_t b : 5; } rd;
36 struct { jit_uint32_t _:11; jit_uint32_t b : 5; } fs;
37 struct { jit_uint32_t _: 7; jit_uint32_t b : 9; } i9;
38 struct { jit_uint32_t _: 6; jit_uint32_t b : 5; } ic;
39 struct { jit_uint32_t _: 6; jit_uint32_t b : 5; } fd;
40 struct { jit_uint32_t b : 6; } tc;
41 struct { jit_uint32_t b : 5; } cn;
42 struct { jit_uint32_t b : 11; } cc;
43 struct { jit_uint32_t b : 16; } is;
44 struct { jit_uint32_t b : 18; } iD;
45 struct { jit_uint32_t b : 19; } iW;
46 struct { jit_uint32_t b : 26; } ii;
48 struct { jit_uint32_t b : 6; } hc;
49 struct { jit_uint32_t _: 6; jit_uint32_t b : 5; } rs;
50 struct { jit_uint32_t _: 6; jit_uint32_t b : 5; } fm;
51 struct { jit_uint32_t _: 6; jit_uint32_t b : 5; } fr;
52 struct { jit_uint32_t _:11; jit_uint32_t b : 3; } pD;
53 struct { jit_uint32_t _:11; jit_uint32_t b : 2; } pW;
54 struct { jit_uint32_t _:11; jit_uint32_t b : 5; } rt;
55 struct { jit_uint32_t _:11; jit_uint32_t b : 5; } ft;
56 struct { jit_uint32_t _:16; jit_uint32_t b : 5; } rd;
57 struct { jit_uint32_t _:16; jit_uint32_t b : 5; } fs;
58 struct { jit_uint32_t _:16; jit_uint32_t b : 9; } i9;
59 struct { jit_uint32_t _:21; jit_uint32_t b : 5; } ic;
60 struct { jit_uint32_t _:21; jit_uint32_t b : 5; } fd;
61 struct { jit_uint32_t _:26; jit_uint32_t b : 6; } tc;
62 struct { jit_uint32_t _:27; jit_uint32_t b : 5; } cn;
63 struct { jit_uint32_t _:21; jit_uint32_t b : 11; } cc;
64 struct { jit_uint32_t _:16; jit_uint32_t b : 16; } is;
65 struct { jit_uint32_t _:14; jit_uint32_t b : 18; } iD;
66 struct { jit_uint32_t _:13; jit_uint32_t b : 19; } iW;
67 struct { jit_uint32_t _: 6; jit_uint32_t b : 26; } ii;
71 #define jit_mips2_p() (jit_cpu.release >= 2)
72 #define jit_mips6_p() (jit_cpu.release >= 6)
73 #define jit_unaligned_p() (jit_cpu.unaligned)
74 # define _ZERO_REGNO 0
75 # define _T0_REGNO 0x08
76 # define _T1_REGNO 0x09
77 # define _T2_REGNO 0x0a
78 # define _T3_REGNO 0x0b
79 # define _T4_REGNO 0x0c
80 # define _T5_REGNO 0x0d
81 # define _T6_REGNO 0x0e
82 # define _T7_REGNO 0x0f
83 # define _S0_REGNO 0x10
84 # define _S1_REGNO 0x11
85 # define _S2_REGNO 0x12
86 # define _S3_REGNO 0x13
87 # define _S4_REGNO 0x14
88 # define _S5_REGNO 0x15
89 # define _S6_REGNO 0x16
90 # define _S7_REGNO 0x17
91 # define _T8_REGNO 0x18
92 # define _T9_REGNO 0x19
93 # define _SP_REGNO 0x1d
94 # define _BP_REGNO 0x1e
95 # define _RA_REGNO 0x1f
96 # define _F16_REGNO 16
97 # define _F18_REGNO 18
98 # define _F20_REGNO 20
99 # define _F22_REGNO 22
100 # define _F24_REGNO 24
101 # define _F26_REGNO 26
102 # define _F28_REGNO 28
103 # define _F30_REGNO 30
104 # if __WORDSIZE == 32
105 # define ldr(u,v) ldr_i(u,v)
106 # define ldi(u,v) ldi_i(u,v)
107 # define ldxr(u,v,w) ldxr_i(u,v,w)
108 # define ldxi(u,v,w) ldxi_i(u,v,w)
109 # define str(u,v) str_i(u,v)
110 # define sti(u,v) sti_i(u,v)
111 # define stxr(u,v,w) stxr_i(u,v,w)
112 # define stxi(u,v,w) stxi_i(u,v,w)
114 # define ldr(u,v) ldr_l(u,v)
115 # define ldi(u,v) ldi_l(u,v)
116 # define ldxr(u,v,w) ldxr_l(u,v,w)
117 # define ldxi(u,v,w) ldxi_l(u,v,w)
118 # define str(u,v) str_l(u,v)
119 # define sti(u,v) sti_l(u,v)
120 # define stxr(u,v,w) stxr_l(u,v,w)
121 # define stxi(u,v,w) stxi_l(u,v,w)
123 /* can_relative_jump_p(im) => can_sign_extend_short_p(im << 2) */
124 # define can_relative_jump_p(im) ((im) >= -130712 && (im) <= 131068)
125 /* can_compact_jump_p(im) => can_sign_extend_i26_p(im << 2) */
126 # define can_compact_jump_p(im) ((im) >= -268435456 && (im) <= 268435452)
127 # define can_sign_extend_short_p(im) ((im) >= -32768 && (im) <= 32767)
128 # define can_zero_extend_short_p(im) ((im) >= 0 && (im) <= 65535)
129 # define can_sign_extend_i18_p(im) ((im) >= -262144 && (im) <= 262143)
130 # define can_sign_extend_i19_p(im) ((im) >= -524288 && (im) <= 524287)
131 # define can_sign_extend_i26_p(im) ((im) >= -67108864 && (im) <= 67108863)
132 # define is_low_mask(im) (((im) & 1) ? (__builtin_popcountl((im) + 1) <= 1) : 0)
133 # define is_middle_mask(im) ((im) ? (__builtin_popcountl((im) + (1 << __builtin_ctzl(im))) <= 1) : 0)
134 # define is_high_mask(im) ((im) ? (__builtin_popcountl((im) + (1 << __builtin_ctzl(im))) == 0) : 0)
135 # define masked_bits_count(im) __builtin_popcountl(im)
136 # define unmasked_bits_count(im) (__WORDSIZE - masked_bits_count(im))
137 # if __WORDSIZE == 32
138 # define can_sign_extend_int_p(im) 1
139 # define can_zero_extend_int_p(im) 1
141 # define can_sign_extend_int_p(im) \
142 (((im) >= 0 && (im) <= 0x7fffffffL) || \
143 ((im) < 0 && (im) >= -0x80000000L))
144 # define can_zero_extend_int_p(im) ((im) >= 0 && (im) <= 0xffffffff)
146 # define MIPS_SPECIAL 0x00
147 # define MIPS_REGIMM 0x01
149 # define MIPS_SRL 0x02
150 # define MIPS_JAL 0x03
151 # define MIPS_SRA 0x03
152 # define MIPS_BEQ 0x04
153 # define MIPS_BNE 0x05
154 # define MIPS_BLEZ 0x06
155 # define MIPS_BGTZ 0x07
156 # define MIPS_ADDI 0x08
157 # define MIPS_ADDIU 0x09
158 # define MIPS_SLTI 0x0a
159 # define MIPS_SLTIU 0x0b
160 # define MIPS_ANDI 0x0c
161 # define MIPS_ORI 0x0d
162 # define MIPS_XORI 0x0e
163 # define MIPS_LUI 0x0f
164 # define MIPS_COP0 0x10
165 # define MIPS_COP1 0x11
166 # define MIPS_COP2 0x12
167 # define MIPS_COP1X 0x13
168 # define MIPS_BEQL 0x14
169 # define MIPS_BNEL 0x15
170 # define MIPS_BLEZL 0x16
171 # define MIPS_BGTZL 0x17
172 # define MIPS_DADDI 0x18
173 # define MIPS_DADDIU 0x19
174 # define MIPS_LDL 0x1a
175 # define MIPS_LDR 0x1b
176 # define MIPS_SPECIAL2 0x1c
177 # define MIPS_JALX 0x1d
178 # define MIPS_DAUI 0x1d
179 # define MIPS_SPECIAL3 0x1f
180 # define MIPS_LB 0x20
181 # define MIPS_LH 0x21
182 # define MIPS_LWL 0x22
183 # define MIPS_LW 0x23
184 # define MIPS_LBU 0x24
185 # define MIPS_LHU 0x25
186 # define MIPS_LWR 0x26
187 # define MIPS_LWU 0x27
188 # define MIPS_SB 0x28
189 # define MIPS_SH 0x29
190 # define MIPS_SWL 0x2a
191 # define MIPS_SW 0x2b
192 # define MIPS_SDL 0x2c
193 # define MIPS_SDR 0x2d
194 # define MIPS_SWR 0x2e
195 # define MIPS_CACHE 0x2f
196 # define MIPS_LL 0x30
197 # define MIPS_LWC1 0x31
198 # define MIPS_LWC2 0x32
199 # define MIPS_PREF 0x33
200 # define MIPS_LLD 0x34
201 # define MIPS_LDC1 0x35
202 # define MIPS_LDC2 0x36
203 # define MIPS_LD 0x37
204 # define MIPS_SC 0x38
205 # define MIPS_BC_R6 0x32
206 # define MIPS_BALC 0x3a
207 # define MIPS_PCREL 0x3b
208 # define MIPS_SCD 0x3c
209 # define MIPS_SDC1 0x3d
210 # define MIPS_SDC2 0x3e
211 # define MIPS_SWC1 0x39
212 # define MIPS_SWC2 0x3a
213 # define MIPS_SD 0x3f
214 # define MIPS_MF 0x00
215 # define MIPS_DMF 0x01
216 # define MIPS_CF 0x02
217 # define MIPS_MFH 0x03
218 # define MIPS_MT 0x04
219 # define MIPS_DMT 0x05
220 # define MIPS_CT 0x06
221 # define MIPS_MTH 0x07
222 # define MIPS_BC 0x08
223 # define MIPS_BC1EQZ 0x09 /* release 6 */
224 # define MIPS_BC1NEZ 0x0d /* release 6 */
225 # define MIPS_WRPGPR 0x0e
226 # define MIPS_BGZAL 0x11
227 # define MIPS_MFMC0 0x11
228 # define MIPS_BCF 0x00
229 # define MIPS_BLTZ 0x00
230 # define MIPS_BCT 0x01
231 # define MIPS_BGEZ 0x01
232 # define MIPS_BCFL 0x02
233 # define MIPS_BLTZL 0x02
234 # define MIPS_BCTL 0x03
235 # define MIPS_BGEZL 0x03
236 # define MIPS_TGEI 0x08
237 # define MIPS_TGEIU 0x09
238 # define MIPS_TLTI 0x0a
239 # define MIPS_TLTIU 0x0b
240 # define MIPS_TEQI 0x0c
241 # define MIPS_TNEI 0x0e
242 # define MIPS_BLTZAL 0x10
243 # define MIPS_BGEZAL 0x11
244 # define MIPS_BLTZALL 0x12
245 # define MIPS_BGEZALL 0x13
246 # define MIPS_SYNCI 0x1f
247 # define MIPS_WSBH 0x02
248 # define MIPS_DSBH 0x02
249 # define MIPS_DSHD 0x05
250 # define MIPS_SEB 0x10
251 # define MIPS_SEH 0x18
252 # define MIPS_MADD 0x00
253 # define MIPS_SLL 0x00
254 # define MIPS_EXT 0x00
255 # define MIPS_DEXTM 0x01
256 # define MIPS_MADDU 0x01
257 # define MIPS_MOVFT 0x01
258 # define MIPS_TLBR 0x01
259 # define MIPS_MUL 0x02
260 # define MIPS_DEXTU 0x02
261 # define MIPS_TLBWI 0x02
262 # define MIPS_DEXT 0x03
263 # define MIPS_SLLV 0x04
264 # define MIPS_INS 0x04
265 # define MIPS_MSUB 0x04
266 # define MIPS_DINSM 0x05
267 # define MIPS_MSUBU 0x05
268 # define MIPS_SRLV 0x06
269 # define MIPS_DINSU 0x06
270 # define MIPS_TLBWR 0x06
271 # define MIPS_SRAV 0x07
272 # define MIPS_DINS 0x07
273 # define MIPS_JR 0x08
274 # define MIPS_TLBP 0x08
275 # define MIPS_JALR 0x09
276 # define MIPS_MOVZ 0x0a
277 # define MIPS_MOVN 0x0b
278 # define MIPS_SYSCALL 0x0c
279 # define MIPS_BREAK 0x0d
280 # define MIPS_PREFX 0x0f
281 # define MIPS_SYNC 0x0f
282 # define MIPS_MFHI 0x10
283 # define MIPS_MTHI 0x11
284 # define MIPS_MFLO 0x12
285 # define MIPS_MTLO 0x13
286 # define MIPS_DSLLV 0x14
287 # define MIPS_DSRLV 0x16
288 # define MIPS_DSRAV 0x17
289 # define MIPS_MULT 0x18
290 # define MIPS_ERET 0x18
291 # define MIPS_MULTU 0x19
292 # define MIPS_DIV 0x1a
293 # define MIPS_DIVU 0x1b
294 # define MIPS_DMULT 0x1c
295 # define MIPS_DMULTU 0x1d
296 # define MIPS_DDIV 0x1e
297 # define MIPS_DDIVU 0x1f
298 # define MIPS_DERET 0x1f
299 # define MIPS_ADD 0x20
300 # define MIPS_CLZ 0x20
301 # define MIPS_BSHFL 0x20
302 # define MIPS_ADDU 0x21
303 # define MIPS_CLO 0x21
304 # define MIPS_SUB 0x22
305 # define MIPS_SUBU 0x23
306 # define MIPS_AND 0x24
307 # define MIPS_DCLZ 0x24
308 # define MIPS_DBSHFL 0x24
309 # define MIPS_OR 0x25
310 # define MIPS_DCLO 0x25
311 # define MIPS_XOR 0x26
312 # define MIPS_NOR 0x27
313 # define MIPS_SLT 0x2a
314 # define MIPS_SLTU 0x2b
315 # define MIPS_DADD 0x2c
316 # define MIPS_DADDU 0x2d
317 # define MIPS_DSUB 0x2e
318 # define MIPS_DSUBU 0x2f
319 # define MIPS_TGE 0x30
320 # define MIPS_TGEU 0x31
321 # define MIPS_TLT 0x32
322 # define MIPS_TLTU 0x33
323 # define MIPS_TEQ 0x34
324 # define MIPS_TNE 0x36
325 # define MIPS_DSLL 0x38
326 # define MIPS_DSRL 0x3a
327 # define MIPS_DSRA 0x3b
328 # define MIPS_DSLL32 0x3c
329 # define MIPS_DSRL32 0x3e
330 # define MIPS_DSRA32 0x3f
331 # define MIPS_SDBPP 0x3f
332 # define ii(i) *_jit->pc.ui++ = i
333 # define instr(op) _instr(_jit, op)
334 static void _instr(jit_state_t*, jit_int32_t);
335 # define flush() _flush(_jit)
336 static void _flush(jit_state_t*);
337 # define pending() _pending(_jit)
338 static jit_int32_t _pending(jit_state_t*);
339 # define delay(op) _delay(_jit,op)
340 static void _delay(jit_state_t*,jit_int32_t);
341 # define jit_get_reg_for_delay_slot(mask, r0,r1) \
342 _jit_get_reg_for_delay_slot(_jit,mask,r0,r1)
343 static jit_int32_t _jit_get_reg_for_delay_slot(jit_state_t*,jit_int32_t,
344 jit_int32_t, jit_int32_t);
345 # define hrrrit(hc,rs,rt,rd,im,tc) _hrrrit(_jit,hc,rs,rt,rd,im,tc)
347 _hrrrit(jit_state_t*,jit_int32_t,jit_int32_t,jit_int32_t,jit_int32_t,
348 jit_int32_t,jit_int32_t);
349 # define hrrr_t(hc,rs,rt,rd,tc) hrrrit(hc,rs,rt,rd,0,tc)
350 # define rrr_t(rs,rt,rd,tc) hrrr_t(0,rs,rt,rd,tc)
351 # define hrri(hc,rs,rt,im) _hrri(_jit,hc,rs,rt,im)
352 static void _hrri(jit_state_t*,jit_int32_t,jit_int32_t,jit_int32_t,jit_int32_t);
353 # define hrri9(hc,rs,rt,i9,tc) _hrri9(_jit,hc,rs,rt,i9,tc)
354 static void _hrri9(jit_state_t*,jit_int32_t,jit_int32_t,
355 jit_int32_t,jit_int32_t,jit_int32_t);
356 # define hriD(hc,rs,pD,iD) _hriD(_jit,hc,rs,pD,iD)
357 static void _hriD(jit_state_t*,jit_int32_t,jit_int32_t,jit_int32_t,jit_int32_t);
358 # define hriW(hc,rs,pW,iW) _hriW(_jit,hc,rs,pW,iW)
359 static void _hriW(jit_state_t*,jit_int32_t,jit_int32_t,jit_int32_t,jit_int32_t);
360 # define hi(hc,im) _hi(_jit,hc,im)
361 static void _hi(jit_state_t*,jit_int32_t,jit_int32_t);
362 # define NOP(i0) instr(0)
363 # define nop(i0) _nop(_jit,i0)
364 static void _nop(jit_state_t*,jit_int32_t);
365 # define h_ri(hc,rt,im) _hrri(_jit,hc,0,rt,im)
366 # define rrit(rt,rd,im,tc) _hrrrit(_jit,0,0,rt,rd,im,tc)
367 # define AUIPC(rs,im) hrri(MIPS_PCREL,rs,30,im)
368 # define ALUIPC(rs,im) hrri(MIPS_PCREL,rs,31,im)
369 # define ADDIUPC(rs,im) hriW(MIPS_PCREL,rs,0,im)
370 # define LUI(rt,im) h_ri(MIPS_LUI,rt,im)
371 # define AUI(rs,rt) hrri(MIPS_LUI,rs,rt,im) /* mips r6 */
372 # define ADDU(rd,rs,rt) rrr_t(rs,rt,rd,MIPS_ADDU)
373 # define DADDU(rd,rs,rt) rrr_t(rs,rt,rd,MIPS_DADDU)
374 # define ADDIU(rt,rs,im) hrri(MIPS_ADDIU,rs,rt,im)
375 # define DADDIU(rt,rs,im) hrri(MIPS_DADDIU,rs,rt,im)
376 # define SUBU(rd,rs,rt) rrr_t(rs,rt,rd,MIPS_SUBU)
377 # define DSUBU(rd,rs,rt) rrr_t(rs,rt,rd,MIPS_DSUBU)
378 # define MUL(rd,rs,rt) hrrr_t(MIPS_SPECIAL2,rs,rt,rd,MIPS_MUL)
379 # define MULT(rs,rt) rrr_t(rs,rt,_ZERO_REGNO,MIPS_MULT)
380 # define MUL_R6(rd,rs,rt) hrrrit(MIPS_SPECIAL, rs, rt, rd, 2, 24)
381 # define MUH_R6(rd,rs,rt) hrrrit(MIPS_SPECIAL, rs, rt, rd, 3, 24)
382 # define MULTU(rs,rt) rrr_t(rs,rt,_ZERO_REGNO,MIPS_MULTU)
383 # define MULU_R6(rd,rs,rt) hrrrit(MIPS_SPECIAL, rs, rt, rd, 2, 25)
384 # define MUHU_R6(rd,rs,rt) hrrrit(MIPS_SPECIAL, rs, rt, rd, 3, 25)
385 # define DMULT(rs,rt) rrr_t(rs,rt,_ZERO_REGNO,MIPS_DMULT)
386 # define DMUL_R6(rd,rs,rt) hrrrit(MIPS_SPECIAL, rs, rt, rd, 2, 28)
387 # define DMUH_R6(rd,rs,rt) hrrrit(MIPS_SPECIAL, rs, rt, rd, 3, 28)
388 # define DMULTU(rs,rt) rrr_t(rs,rt,_ZERO_REGNO,MIPS_DMULTU)
389 # define DMULU_R6(rd,rs,rt) hrrrit(MIPS_SPECIAL, rs, rt, rd, 2, 29)
390 # define DMUHU_R6(rd,rs,rt) hrrrit(MIPS_SPECIAL, rs, rt, rd, 3, 29)
391 # define DIV(rs,rt) rrr_t(rs,rt,_ZERO_REGNO,MIPS_DIV)
392 # define DIV_R6(rd,rs,rt) hrrrit(MIPS_SPECIAL, rs, rt, rd, 2, 26)
393 # define MOD_R6(rd,rs,rt) hrrrit(MIPS_SPECIAL, rs, rt, rd, 3, 26)
394 # define DIVU(rs,rt) rrr_t(rs,rt,_ZERO_REGNO,MIPS_DIVU)
395 # define DIVU_R6(rd,rs,rt) hrrrit(MIPS_SPECIAL, rs, rt, rd, 2, 27)
396 # define MODU_R6(rd,rs,rt) hrrrit(MIPS_SPECIAL, rs, rt, rd, 3, 27)
397 # define DDIV(rs,rt) rrr_t(rs,rt,_ZERO_REGNO,MIPS_DDIV)
398 # define DDIV_R6(rd,rs,rt) hrrrit(MIPS_SPECIAL, rs, rt, rd, 2, 30)
399 # define DMOD_R6(rd,rs,rt) hrrrit(MIPS_SPECIAL, rs, rt, rd, 3, 30)
400 # define DDIVU(rs,rt) rrr_t(rs,rt,_ZERO_REGNO,MIPS_DDIVU)
401 # define DDIVU_R6(rd,rs,rt) hrrrit(MIPS_SPECIAL, rs, rt, rd, 2, 31)
402 # define DMODU_R6(rd,rs,rt) hrrrit(MIPS_SPECIAL, rs, rt, rd, 3, 31)
403 # define SLLV(rd,rt,rs) rrr_t(rs,rt,rd,MIPS_SLLV)
404 # define SLL(rd,rt,sa) rrit(rt,rd,sa,MIPS_SLL)
405 # define DSLLV(rd,rt,rs) rrr_t(rs,rt,rd,MIPS_DSLLV)
406 # define DSLL(rd,rt,sa) rrit(rt,rd,sa,MIPS_DSLL)
407 # define DSLL32(rd,rt,sa) rrit(rt,rd,sa,MIPS_DSLL32)
408 # define SRAV(rd,rt,rs) rrr_t(rs,rt,rd,MIPS_SRAV)
409 # define SRA(rd,rt,sa) rrit(rt,rd,sa,MIPS_SRA)
410 # define SRLV(rd,rt,rs) rrr_t(rs,rt,rd,MIPS_SRLV)
411 # define SRL(rd,rt,sa) rrit(rt,rd,sa,MIPS_SRL)
412 # define DSRAV(rd,rt,rs) rrr_t(rs,rt,rd,MIPS_DSRAV)
413 # define DSRA(rd,rt,sa) rrit(rt,rd,sa,MIPS_DSRA)
414 # define DSRA32(rd,rt,sa) rrit(rt,rd,sa,MIPS_DSRA32)
415 # define DSRLV(rd,rt,rs) rrr_t(rs,rt,rd,MIPS_DSRLV)
416 # define DSRL(rd,rt,sa) rrit(rt,rd,sa,MIPS_DSRL)
417 # define DSRL32(rd,rt,sa) rrit(rt,rd,sa,MIPS_DSRL32)
418 # define INS(rt,rs,pos,size) hrrrit(MIPS_SPECIAL3,rs,rt,pos+size-1,pos,MIPS_INS)
419 # define DINS(rt,rs,pos,size) hrrrit(MIPS_SPECIAL3,rs,rt,pos+size-1,pos,MIPS_DINS)
420 # define DINSU(rt,rs,pos,size) hrrrit(MIPS_SPECIAL3,rs,rt,pos+size-32-1,pos-32,MIPS_DINSU)
421 # define DINSM(rt,rs,pos,size) hrrrit(MIPS_SPECIAL3,rs,rt,pos+size-32-1,pos,MIPS_DINSM)
422 # define EXT(rt,rs,pos,size) hrrrit(MIPS_SPECIAL3,rs,rt,size-1,pos,MIPS_EXT)
423 # define DEXT(rt,rs,pos,size) hrrrit(MIPS_SPECIAL3,rs,rt,size-1,pos,MIPS_DEXT)
424 # define DEXTU(rt,rs,pos,size) hrrrit(MIPS_SPECIAL3,rs,rt,size-1,pos-32,MIPS_DEXTU)
425 # define DEXTM(rt,rs,pos,size) hrrrit(MIPS_SPECIAL3,rs,rt,size-32-1,pos,MIPS_DEXTM)
426 # define ROTR(rd,rt,sa) hrrrit(MIPS_SPECIAL,1,rt,rd,sa,MIPS_SRL)
427 # define ROTRV(rd,rt,rs) hrrrit(MIPS_SPECIAL,rs,rt,rd,1,MIPS_SRLV)
428 # define DROTR(rd,rt,sa) hrrrit(MIPS_SPECIAL,1,rt,rd,sa,MIPS_DSRL)
429 # define DROTR32(rd,rt,sa) hrrrit(MIPS_SPECIAL,1,rt,rd,sa,MIPS_DSRL32)
430 # define DROTRV(rd,rt,rs) hrrrit(MIPS_SPECIAL,rs,rt,rd,1,MIPS_DSRLV)
431 # define SYNC() rrr_t(_ZERO_REGNO,_ZERO_REGNO,_ZERO_REGNO,MIPS_SYNC)
432 # define MFHI(rd) rrr_t(_ZERO_REGNO,_ZERO_REGNO,rd,MIPS_MFHI)
433 # define MFLO(rd) rrr_t(_ZERO_REGNO,_ZERO_REGNO,rd,MIPS_MFLO)
434 # define MTHI(rs) rrr_t(rs,_ZERO_REGNO,_ZERO_REGNO,MIPS_MTHI)
435 # define MTLO(rs) rrr_t(rs,_ZERO_REGNO,_ZERO_REGNO,MIPS_MTLO)
436 # define AND(rd,rs,rt) rrr_t(rs,rt,rd,MIPS_AND)
437 # define ANDI(rt,rs,im) hrri(MIPS_ANDI,rs,rt,im)
438 # define OR(rd,rs,rt) rrr_t(rs,rt,rd,MIPS_OR)
439 # define ORI(rt,rs,im) hrri(MIPS_ORI,rs,rt,im)
440 # define NOR(rd,rs,rt) rrr_t(rs,rt,rd,MIPS_NOR)
441 # define XOR(rd,rs,rt) rrr_t(rs,rt,rd,MIPS_XOR)
442 # define XORI(rt,rs,im) hrri(MIPS_XORI,rs,rt,im)
443 # define LB(rt,of,rb) hrri(MIPS_LB,rb,rt,of)
444 # define LBU(rt,of,rb) hrri(MIPS_LBU,rb,rt,of)
445 # define LH(rt,of,rb) hrri(MIPS_LH,rb,rt,of)
446 # define LHU(rt,of,rb) hrri(MIPS_LHU,rb,rt,of)
447 # define LW(rt,of,rb) hrri(MIPS_LW,rb,rt,of)
448 # define LWPC(rs,im) hriW(MIPS_PCREL,rs,1,im)
449 # define LWU(rt,of,rb) hrri(MIPS_LWU,rb,rt,of)
450 # define LWUPC(rs,im) hriW(MIPS_PCREL,rs,2,im)
451 # define LWL(rt,of,rb) hrri(MIPS_LWL,rb,rt,of)
452 # define LWR(rt,of,rb) hrri(MIPS_LWR,rb,rt,of)
453 # define LD(rt,of,rb) hrri(MIPS_LD,rb,rt,of)
454 # define LDPC(rs,im) hriD(MIPS_PCREL,rs,6,im)
455 # define LL(rt,of,rb) hrri(MIPS_LL,rb,rt,of)
456 # define LL_R6(rt,of,rb) hrri9(MIPS_SPECIAL3,rb,rt,of,54)
457 # define LLD(rt,of,rb) hrri(MIPS_LLD,rb,rt,of)
458 # define LLD_R6(rt,of,rb) hrri9(MIPS_SPECIAL3,rb,rt,of,55)
459 # define LDL(rt,of,rb) hrri(MIPS_LDL,rb,rt,of)
460 # define LDR(rt,of,rb) hrri(MIPS_LDR,rb,rt,of)
461 # define SB(rt,of,rb) hrri(MIPS_SB,rb,rt,of)
462 # define SH(rt,of,rb) hrri(MIPS_SH,rb,rt,of)
463 # define SW(rt,of,rb) hrri(MIPS_SW,rb,rt,of)
464 # define SWL(rt,of,rb) hrri(MIPS_SWL,rb,rt,of)
465 # define SWR(rt,of,rb) hrri(MIPS_SWR,rb,rt,of)
466 # define SD(rt,of,rb) hrri(MIPS_SD,rb,rt,of)
467 # define SC(rt,of,rb) hrri(MIPS_SC,rb,rt,of)
468 # define SC_R6(rt,of,rb) hrri9(MIPS_SPECIAL3,rb,rt,of,38)
469 # define SCD(rt,of,rb) hrri(MIPS_SCD,rb,rt,of)
470 # define SCD_R6(rt,of,rb) hrri9(MIPS_SPECIAL3,rb,rt,of,39)
471 # define SDL(rt,of,rb) hrri(MIPS_SDL,rb,rt,of)
472 # define SDR(rt,of,rb) hrri(MIPS_SDR,rb,rt,of)
473 # define WSBH(rd,rt) hrrrit(MIPS_SPECIAL3,0,rt,rd,MIPS_WSBH,MIPS_BSHFL)
474 # define SEB(rd,rt) hrrrit(MIPS_SPECIAL3,0,rt,rd,MIPS_SEB,MIPS_BSHFL)
475 # define SEH(rd,rt) hrrrit(MIPS_SPECIAL3,0,rt,rd,MIPS_SEH,MIPS_BSHFL)
476 # define DSBH(rd,rt) hrrrit(MIPS_SPECIAL3,0,rt,rd,MIPS_DSBH,MIPS_DBSHFL)
477 # define DSHD(rd,rt) hrrrit(MIPS_SPECIAL3,0,rt,rd,MIPS_DSHD,MIPS_DBSHFL)
478 # define SLT(rd,rs,rt) rrr_t(rs,rt,rd,MIPS_SLT)
479 # define SLTU(rd,rs,rt) rrr_t(rs,rt,rd,MIPS_SLTU)
480 # define SLTI(rt,rs,im) hrri(MIPS_SLTI,rs,rt,im)
481 # define SLTIU(rt,rs,im) hrri(MIPS_SLTIU,rs,rt,im)
482 # define DAUI(rt,rs,im) hrri(MIPS_DAUI,rs,rt,im)
483 # define DAHI(rs,im) hrri(MIPS_REGIMM,rs,6,im)
484 # define DATI(rs,im) hrri(MIPS_REGIMM,rs,30,im)
485 # define BLTZ(rs,im) hrri(MIPS_REGIMM,rs,MIPS_BLTZ,im)
486 # define BLEZ(rs,im) hrri(MIPS_BLEZ,rs,_ZERO_REGNO,im)
487 # define BEQ(rs,rt,im) hrri(MIPS_BEQ,rs,rt,im)
488 # define BGEZ(rs,im) hrri(MIPS_REGIMM,rs,MIPS_BGEZ,im)
489 # define BGTZ(rs,im) hrri(MIPS_BGTZ,rs,_ZERO_REGNO,im)
490 # define BNE(rs,rt,im) hrri(MIPS_BNE,rs,rt,im)
491 # define BGEZAL(rs,im) hrri(MIPS_REGIMM,rs,MIPS_BGEZAL,im)
492 # define JALR(r0) hrrrit(MIPS_SPECIAL,r0,0,_RA_REGNO,0,MIPS_JALR)
493 # if 1 /* This should work for mips r6 or older */
494 # define JR(r0) hrrrit(MIPS_SPECIAL,r0,0,0,0,MIPS_JALR)
495 # else /* This should generate an illegal instruction in mips r6 */
496 # define JR(r0) hrrrit(MIPS_SPECIAL,r0,0,0,0,MIPS_JR)
498 # define CLO_R6(rd,rs) hrrrit(MIPS_SPECIAL,rs,0,rd,1,0x11)
499 # define DCLO_R6(rd,rs) hrrrit(MIPS_SPECIAL,rs,0,rd,1,0x13)
500 # define CLZ_R6(rd,rs) hrrrit(MIPS_SPECIAL,rs,0,rd,1,0x10)
501 # define DCLZ_R6(rd,rs) hrrrit(MIPS_SPECIAL,rs,0,rd,1,0x12)
502 # define BITSWAP(rd,rt) hrrrit(MIPS_SPECIAL3,0,rt,rd,0,0x20)
503 # define DBITSWAP(rd,rt) hrrrit(MIPS_SPECIAL3,0,rt,rd,0,0x24)
504 # define CLO(rd,rs) hrrrit(MIPS_SPECIAL2,rs,rd,rd,0,MIPS_CLO)
505 # define DCLO(rd,rs) hrrrit(MIPS_SPECIAL2,rs,rd,rd,0,MIPS_DCLO)
506 # define CLZ(rd,rs) hrrrit(MIPS_SPECIAL2,rs,rd,rd,0,MIPS_CLZ)
507 # define DCLZ(rd,rs) hrrrit(MIPS_SPECIAL2,rs,rd,rd,0,MIPS_DCLZ)
508 # define J(i0) hi(MIPS_J,i0)
509 # define JAL(i0) hi(MIPS_JAL,i0)
510 # define BC_R6(i0) hi(MIPS_BC_R6,i0)
511 # define BALC(i0) hi(MIPS_BALC,i0)
512 # define MOVN(rd,rs,rt) hrrrit(0,rs,rt,rd,0,MIPS_MOVN)
513 # define MOVZ(rd,rs,rt) hrrrit(0,rs,rt,rd,0,MIPS_MOVZ)
514 # define SELEQZ(rd,rs,rt) hrrrit(0,rs,rt,rd,0,53)
515 # define SELNEZ(rd,rs,rt) hrrrit(0,rs,rt,rd,0,55)
516 # define comr(r0,r1) xori(r0,r1,-1)
517 # define negr(r0,r1) subr(r0,_ZERO_REGNO,r1)
518 # define clor(r0, r1) _clor(_jit, r0, r1)
519 static void _clor(jit_state_t*, jit_int32_t, jit_int32_t);
520 # define clzr(r0, r1) _clzr(_jit, r0, r1)
521 static void _clzr(jit_state_t*, jit_int32_t, jit_int32_t);
522 # define ctor(r0, r1) _ctor(_jit, r0, r1)
523 static void _ctor(jit_state_t*, jit_int32_t, jit_int32_t);
524 # define ctzr(r0, r1) _ctzr(_jit, r0, r1)
525 static void _ctzr(jit_state_t*, jit_int32_t, jit_int32_t);
526 # define rbitr(r0, r1) _rbitr(_jit, r0, r1)
527 static void _rbitr(jit_state_t*, jit_int32_t, jit_int32_t);
528 # if __WORDSIZE == 32
529 # define addr(rd,rs,rt) ADDU(rd,rs,rt)
530 # define addiu(r0,r1,i0) ADDIU(r0,r1,i0)
531 # define subr(rd,rs,rt) SUBU(rd,rs,rt)
532 # define mult(rs,rt) MULT(rs,rt)
533 # define mul_r6(rd,rs,rt) MUL_R6(rd,rs,rt)
534 # define muh_r6(rd,rs,rt) MUH_R6(rd,rs,rt)
535 # define multu(rs,rt) MULTU(rs,rt)
536 # define mulu_r6(rd,rs,rt) MULU_R6(rd,rs,rt)
537 # define muhu_r6(rd,rs,rt) MUHU_R6(rd,rs,rt)
538 # define div(rs,rt) DIV(rs,rt)
539 # define divu(rs,rt) DIVU(rs,rt)
540 # define div_r6(rd,rs,rt) DIV_R6(rd,rs,rt)
541 # define divu_r6(rd,rs,rt) DIVU_R6(rd,rs,rt)
542 # define mod_r6(rd,rs,rt) MOD_R6(rd,rs,rt)
543 # define modu_r6(rd,rs,rt) MODU_R6(rd,rs,rt)
545 # define addr(rd,rs,rt) DADDU(rd,rs,rt)
546 # define addiu(r0,r1,i0) DADDIU(r0,r1,i0)
547 # define subr(rd,rs,rt) DSUBU(rd,rs,rt)
548 # define mult(rs,rt) DMULT(rs,rt)
549 # define mul_r6(rd,rs,rt) DMUL_R6(rd,rs,rt)
550 # define muh_r6(rd,rs,rt) DMUH_R6(rd,rs,rt)
551 # define multu(rs,rt) DMULTU(rs,rt)
552 # define mulu_r6(rd,rs,rt) DMULU_R6(rd,rs,rt)
553 # define muhu_r6(rd,rs,rt) DMUHU_R6(rd,rs,rt)
554 # define div(rs,rt) DDIV(rs,rt)
555 # define divu(rs,rt) DDIVU(rs,rt)
556 # define div_r6(rd,rs,rt) DDIV_R6(rd,rs,rt)
557 # define divu_r6(rd,rs,rt) DDIVU_R6(rd,rs,rt)
558 # define mod_r6(rd,rs,rt) DMOD_R6(rd,rs,rt)
559 # define modu_r6(rd,rs,rt) DMODU_R6(rd,rs,rt)
561 # define mips_extr(rd,rt,lsb,nb) _mips_extr(_jit,rd,rt,lsb,nb)
562 static void _mips_extr(jit_state_t*,jit_int32_t,jit_int32_t,jit_int32_t,jit_int32_t);
563 # define insr(rd,rt,lsb,nb) _insr(_jit,rd,rt,lsb,nb)
564 static void _insr(jit_state_t*,jit_int32_t,jit_int32_t,jit_int32_t,jit_int32_t);
565 # define addi(r0,r1,i0) _addi(_jit,r0,r1,i0)
566 static void _addi(jit_state_t*,jit_int32_t,jit_int32_t,jit_word_t);
567 #define addcr(r0,r1,r2) _addcr(_jit,r0,r1,r2)
568 static void _addcr(jit_state_t*,jit_int32_t,jit_int32_t,jit_int32_t);
569 #define addci(r0,r1,i0) _addci(_jit,r0,r1,i0)
570 static void _addci(jit_state_t*,jit_int32_t,jit_int32_t,jit_word_t);
571 # define addxr(r0,r1,r2) _addxr(_jit,r0,r1,r2)
572 static void _addxr(jit_state_t*,jit_int32_t,jit_int32_t,jit_int32_t);
573 # define addxi(r0,r1,i0) _addxi(_jit,r0,r1,i0)
574 static void _addxi(jit_state_t*,jit_int32_t,jit_int32_t,jit_word_t);
575 # define subi(r0,r1,i0) _subi(_jit,r0,r1,i0)
576 static void _subi(jit_state_t*,jit_int32_t,jit_int32_t,jit_word_t);
577 # define subcr(r0,r1,r2) _subcr(_jit,r0,r1,r2)
578 static void _subcr(jit_state_t*,jit_int32_t,jit_int32_t,jit_int32_t);
579 # define subci(r0,r1,i0) _subci(_jit,r0,r1,i0)
580 static void _subci(jit_state_t*,jit_int32_t,jit_int32_t,jit_word_t);
581 # define subxr(r0,r1,r2) _subxr(_jit,r0,r1,r2)
582 static void _subxr(jit_state_t*,jit_int32_t,jit_int32_t,jit_int32_t);
583 # define subxi(r0,r1,i0) _subxi(_jit,r0,r1,i0)
584 static void _subxi(jit_state_t*,jit_int32_t,jit_int32_t,jit_word_t);
585 # define rsbi(r0, r1, i0) _rsbi(_jit, r0, r1, i0)
586 static void _rsbi(jit_state_t*,jit_int32_t,jit_int32_t,jit_word_t);
587 # define mulr(r0,r1,r2) _mulr(_jit,r0,r1,r2)
588 static void _mulr(jit_state_t*,jit_int32_t,jit_int32_t,jit_int32_t);
589 # define muli(r0,r1,i0) _muli(_jit,r0,r1,i0)
590 static void _muli(jit_state_t*,jit_int32_t,jit_int32_t,jit_word_t);
591 # define hmulr(r0,r1,r2) _hmulr(_jit,r0,r1,r2)
592 static void _hmulr(jit_state_t*,jit_int32_t,jit_int32_t,jit_int32_t);
593 # define hmuli(r0,r1,i0) _hmuli(_jit,r0,r1,i0)
594 static void _hmuli(jit_state_t*,jit_int32_t,jit_int32_t,jit_word_t);
595 # define hmulr_u(r0,r1,r2) _hmulr_u(_jit,r0,r1,r2)
596 static void _hmulr_u(jit_state_t*,jit_int32_t,jit_int32_t,jit_int32_t);
597 # define hmuli_u(r0,r1,i0) _hmuli_u(_jit,r0,r1,i0)
598 static void _hmuli_u(jit_state_t*,jit_int32_t,jit_int32_t,jit_word_t);
599 # define qmulr(r0,r1,r2,r3) iqmulr(r0,r1,r2,r3,1)
600 # define qmulr_u(r0,r1,r2,r3) iqmulr(r0,r1,r2,r3,0)
601 # define iqmulr(r0,r1,r2,r3,cc) _iqmulr(_jit,r0,r1,r2,r3,cc)
602 static void _iqmulr(jit_state_t*,jit_int32_t,jit_int32_t,
603 jit_int32_t,jit_int32_t,jit_bool_t);
604 # define qmuli(r0,r1,r2,i0) iqmuli(r0,r1,r2,i0,1)
605 # define qmuli_u(r0,r1,r2,i0) iqmuli(r0,r1,r2,i0,0)
606 # define iqmuli(r0,r1,r2,i0,cc) _iqmuli(_jit,r0,r1,r2,i0,cc)
607 static void _iqmuli(jit_state_t*,jit_int32_t,jit_int32_t,
608 jit_int32_t,jit_word_t,jit_bool_t);
609 # define divr(r0,r1,r2) _divr(_jit,r0,r1,r2)
610 static void _divr(jit_state_t*,jit_int32_t,jit_int32_t,jit_int32_t);
611 # define divi(r0,r1,i0) _divi(_jit,r0,r1,i0)
612 static void _divi(jit_state_t*,jit_int32_t,jit_int32_t,jit_word_t);
613 # define divr_u(r0,r1,r2) _divr_u(_jit,r0,r1,r2)
614 static void _divr_u(jit_state_t*,jit_int32_t,jit_int32_t,jit_int32_t);
615 # define divi_u(r0,r1,i0) _divi_u(_jit,r0,r1,i0)
616 static void _divi_u(jit_state_t*,jit_int32_t,jit_int32_t,jit_word_t);
617 # define qdivr(r0,r1,r2,r3) iqdivr(r0,r1,r2,r3,1)
618 # define qdivr_u(r0,r1,r2,r3) iqdivr(r0,r1,r2,r3,0)
619 # define iqdivr(r0,r1,r2,r3,cc) _iqdivr(_jit,r0,r1,r2,r3,cc)
620 static void _iqdivr(jit_state_t*,jit_int32_t,jit_int32_t,
621 jit_int32_t,jit_int32_t,jit_bool_t);
622 # define qdivi(r0,r1,r2,i0) iqdivi(r0,r1,r2,i0,1)
623 # define qdivi_u(r0,r1,r2,i0) iqdivi(r0,r1,r2,i0,0)
624 # define iqdivi(r0,r1,r2,i0,cc) _iqdivi(_jit,r0,r1,r2,i0,cc)
625 static void _iqdivi(jit_state_t*,jit_int32_t,jit_int32_t,
626 jit_int32_t,jit_word_t,jit_bool_t);
627 # define remr(r0,r1,r2) _remr(_jit,r0,r1,r2)
628 static void _remr(jit_state_t*,jit_int32_t,jit_int32_t,jit_int32_t);
629 # define remi(r0,r1,i0) _remi(_jit,r0,r1,i0)
630 static void _remi(jit_state_t*,jit_int32_t,jit_int32_t,jit_word_t);
631 # define remr_u(r0,r1,r2) _remr_u(_jit,r0,r1,r2)
632 static void _remr_u(jit_state_t*,jit_int32_t,jit_int32_t,jit_int32_t);
633 # define remi_u(r0,r1,i0) _remi_u(_jit,r0,r1,i0)
634 static void _remi_u(jit_state_t*,jit_int32_t,jit_int32_t,jit_word_t);
635 # if __WORDSIZE == 32
636 # define lshr(r0,r1,r2) SLLV(r0,r1,r2)
637 # define lshi(r0,r1,i0) SLL(r0,r1,i0)
638 # define rshr(r0,r1,r2) SRAV(r0,r1,r2)
639 # define rshi(r0,r1,i0) SRA(r0,r1,i0)
640 # define rshr_u(r0,r1,r2) SRLV(r0,r1,r2)
641 # define rshi_u(r0,r1,i0) SRL(r0,r1,i0)
643 # define lshr(r0,r1,r2) DSLLV(r0,r1,r2)
644 # define lshi(r0,r1,i0) _lshi(_jit,r0,r1,i0)
645 static void _lshi(jit_state_t*,jit_int32_t,jit_int32_t,jit_word_t);
646 # define rshr(r0,r1,r2) DSRAV(r0,r1,r2)
647 # define rshi(r0,r1,i0) _rshi(_jit,r0,r1,i0)
648 static void _rshi(jit_state_t*,jit_int32_t,jit_int32_t,jit_word_t);
649 # define rshr_u(r0,r1,r2) DSRLV(r0,r1,r2)
650 # define rshi_u(r0,r1,i0) _rshi_u(_jit,r0,r1,i0)
651 static void _rshi_u(jit_state_t*,jit_int32_t,jit_int32_t,jit_word_t);
653 # define qlshr(r0,r1,r2,r3) xlshr(1,r0,r1,r2,r3)
654 # define qlshr_u(r0, r1, r2, r3) xlshr(0, r0, r1, r2, r3)
655 # define xlshr(s,r0,r1,r2,r3) _xlshr(_jit,s,r0,r1,r2,r3)
657 _xlshr(jit_state_t*,jit_bool_t,jit_int32_t,jit_int32_t,jit_int32_t,jit_int32_t);
658 # define qlshi(r0, r1, r2, i0) xlshi(1, r0, r1, r2, i0)
659 # define qlshi_u(r0, r1, r2, i0) xlshi(0, r0, r1, r2, i0)
660 # define xlshi(s, r0, r1, r2, i0) _xlshi(_jit, s, r0, r1, r2, i0)
662 _xlshi(jit_state_t*,jit_bool_t,jit_int32_t,jit_int32_t,jit_int32_t,jit_word_t);
663 # define qrshr(r0, r1, r2, r3) xrshr(1, r0, r1, r2, r3)
664 # define qrshr_u(r0, r1, r2, r3) xrshr(0, r0, r1, r2, r3)
665 # define xrshr(s, r0, r1, r2, r3) _xrshr(_jit, s, r0, r1, r2, r3)
667 _xrshr(jit_state_t*,jit_bool_t,jit_int32_t,jit_int32_t,jit_int32_t,jit_int32_t);
668 # define qrshi(r0, r1, r2, i0) xrshi(1, r0, r1, r2, i0)
669 # define qrshi_u(r0, r1, r2, i0) xrshi(0, r0, r1, r2, i0)
670 # define xrshi(s, r0, r1, r2, i0) _xrshi(_jit, s, r0, r1, r2, i0)
672 _xrshi(jit_state_t*,jit_bool_t,jit_int32_t,jit_int32_t,jit_int32_t,jit_word_t);
673 # define lrotr(r0,r1,r2) _lrotr(_jit,r0,r1,r2)
674 static void _lrotr(jit_state_t*,jit_int32_t,jit_int32_t,jit_int32_t);
675 # define lroti(r0,r1,i0) rroti(r0,r1,__WORDSIZE-i0)
676 # define rrotr(r0,r1,r2) _rrotr(_jit,r0,r1,r2)
677 static void _rrotr(jit_state_t*,jit_int32_t,jit_int32_t,jit_int32_t);
678 # define rroti(r0,r1,i0) _rroti(_jit,r0,r1,i0)
679 static void _rroti(jit_state_t*,jit_int32_t,jit_int32_t,jit_word_t);
680 # define andr(r0,r1,r2) AND(r0,r1,r2)
681 # define andi(r0,r1,i0) _andi(_jit,r0,r1,i0)
682 static void _andi(jit_state_t*,jit_int32_t,jit_int32_t,jit_word_t);
683 # define orr(r0,r1,r2) OR(r0,r1,r2)
684 # define ori(r0,r1,i0) _ori(_jit,r0,r1,i0)
685 static void _ori(jit_state_t*,jit_int32_t,jit_int32_t,jit_word_t);
686 # define xorr(r0,r1,r2) XOR(r0,r1,r2)
687 # define xori(r0,r1,i0) _xori(_jit,r0,r1,i0)
688 static void _xori(jit_state_t*,jit_int32_t,jit_int32_t,jit_word_t);
689 # define movr(r0,r1) _movr(_jit,r0,r1)
690 static void _movr(jit_state_t*,jit_int32_t,jit_int32_t);
691 # define movi(r0,i0) _movi(_jit,r0,i0)
692 static void _movi(jit_state_t*,jit_int32_t,jit_word_t);
693 # define movi_p(r0,i0) _movi_p(_jit,r0,i0)
694 static jit_word_t _movi_p(jit_state_t*,jit_int32_t,jit_word_t);
695 # define movnr(r0, r1, r2) _movnr(_jit, r0, r1, r2)
696 static void _movnr(jit_state_t*, jit_int32_t, jit_int32_t, jit_int32_t);
697 # define movzr(r0, r1, r2) _movzr(_jit, r0, r1, r2)
698 static void _movzr(jit_state_t*, jit_int32_t, jit_int32_t, jit_int32_t);
699 # define casx(r0, r1, r2, r3, i0) _casx(_jit, r0, r1, r2, r3, i0)
700 static void _casx(jit_state_t *_jit,jit_int32_t,jit_int32_t,
701 jit_int32_t,jit_int32_t,jit_word_t);
702 #define casr(r0, r1, r2, r3) casx(r0, r1, r2, r3, 0)
703 #define casi(r0, i0, r1, r2) casx(r0, _NOREG, r1, r2, i0)
704 # define ldr_c(r0,r1) LB(r0,0,r1)
705 # define ldi_c(r0,i0) _ldi_c(_jit,r0,i0)
706 static void _ldi_c(jit_state_t*,jit_int32_t,jit_word_t);
707 # define ldr_uc(r0,r1) LBU(r0,0,r1)
708 # define ldi_uc(r0,i0) _ldi_uc(_jit,r0,i0)
709 static void _ldi_uc(jit_state_t*,jit_int32_t,jit_word_t);
710 # define ldr_s(r0,r1) LH(r0,0,r1)
711 # define ldi_s(r0,i0) _ldi_s(_jit,r0,i0)
712 static void _ldi_s(jit_state_t*,jit_int32_t,jit_word_t);
713 # define ldr_us(r0,r1) LHU(r0,0,r1)
714 # define ldi_us(r0,i0) _ldi_us(_jit,r0,i0)
715 static void _ldi_us(jit_state_t*,jit_int32_t,jit_word_t);
716 # define ldr_i(r0,r1) LW(r0,0,r1)
717 # define ldi_i(r0,i0) _ldi_i(_jit,r0,i0)
718 static void _ldi_i(jit_state_t*,jit_int32_t,jit_word_t);
719 # if __WORDSIZE == 64
720 # define ldr_ui(r0,r1) LWU(r0,0,r1)
721 # define ldi_ui(r0,i0) _ldi_ui(_jit,r0,i0)
722 static void _ldi_ui(jit_state_t*,jit_int32_t,jit_word_t);
723 # define ldr_l(r0,r1) LD(r0,0,r1)
724 # define ldi_l(r0,i0) _ldi_l(_jit,r0,i0)
725 static void _ldi_l(jit_state_t*,jit_int32_t,jit_word_t);
727 # define ldxr_c(r0,r1,r2) _ldxr_c(_jit,r0,r1,r2)
728 static void _ldxr_c(jit_state_t*,jit_int32_t,jit_int32_t,jit_int32_t);
729 # define ldxi_c(r0,r1,i0) _ldxi_c(_jit,r0,r1,i0)
730 static void _ldxi_c(jit_state_t*,jit_int32_t,jit_int32_t,jit_word_t);
731 # define ldxr_uc(r0,r1,r2) _ldxr_uc(_jit,r0,r1,r2)
732 static void _ldxr_uc(jit_state_t*,jit_int32_t,jit_int32_t,jit_int32_t);
733 # define ldxi_uc(r0,r1,i0) _ldxi_uc(_jit,r0,r1,i0)
734 static void _ldxi_uc(jit_state_t*,jit_int32_t,jit_int32_t,jit_word_t);
735 # define ldxr_s(r0,r1,r2) _ldxr_s(_jit,r0,r1,r2)
736 static void _ldxr_s(jit_state_t*,jit_int32_t,jit_int32_t,jit_int32_t);
737 # define ldxi_s(r0,r1,i0) _ldxi_s(_jit,r0,r1,i0)
738 static void _ldxi_s(jit_state_t*,jit_int32_t,jit_int32_t,jit_word_t);
739 # define ldxr_us(r0,r1,r2) _ldxr_us(_jit,r0,r1,r2)
740 static void _ldxr_us(jit_state_t*,jit_int32_t,jit_int32_t,jit_int32_t);
741 # define ldxi_us(r0,r1,i0) _ldxi_us(_jit,r0,r1,i0)
742 static void _ldxi_us(jit_state_t*,jit_int32_t,jit_int32_t,jit_word_t);
743 # define ldxr_i(r0,r1,r2) _ldxr_i(_jit,r0,r1,r2)
744 static void _ldxr_i(jit_state_t*,jit_int32_t,jit_int32_t,jit_int32_t);
745 # define ldxi_i(r0,r1,i0) _ldxi_i(_jit,r0,r1,i0)
746 static void _ldxi_i(jit_state_t*,jit_int32_t,jit_int32_t,jit_word_t);
747 # if __WORDSIZE == 64
748 # define ldxr_ui(r0,r1,r2) _ldxr_ui(_jit,r0,r1,r2)
749 static void _ldxr_ui(jit_state_t*,jit_int32_t,jit_int32_t,jit_int32_t);
750 # define ldxi_ui(r0,r1,i0) _ldxi_ui(_jit,r0,r1,i0)
751 static void _ldxi_ui(jit_state_t*,jit_int32_t,jit_int32_t,jit_word_t);
752 # define ldxr_l(r0,r1,r2) _ldxr_l(_jit,r0,r1,r2)
753 static void _ldxr_l(jit_state_t*,jit_int32_t,jit_int32_t,jit_int32_t);
754 # define ldxi_l(r0,r1,i0) _ldxi_l(_jit,r0,r1,i0)
755 static void _ldxi_l(jit_state_t*,jit_int32_t,jit_int32_t,jit_word_t);
757 # define unldr(r0, r1, i0) _unldr(_jit, r0, r1, i0)
758 static void _unldr(jit_state_t*, jit_int32_t, jit_int32_t, jit_word_t);
759 # define unldi(r0, i0, i1) _unldi(_jit, r0, i0, i1)
760 static void _unldi(jit_state_t*, jit_int32_t, jit_word_t, jit_word_t);
761 # define unldr_u(r0, r1, i0) _unldr_u(_jit, r0, r1, i0)
762 static void _unldr_u(jit_state_t*, jit_int32_t, jit_int32_t, jit_word_t);
763 # define unldi_u(r0, i0, i1) _unldi_u(_jit, r0, i0, i1)
764 static void _unldi_u(jit_state_t*, jit_int32_t, jit_word_t, jit_word_t);
765 # define str_c(r0,r1) SB(r1,0,r0)
766 # define sti_c(i0,r0) _sti_c(_jit,i0,r0)
767 static void _sti_c(jit_state_t*,jit_word_t,jit_int32_t);
768 # define str_s(r0,r1) SH(r1,0,r0)
769 # define sti_s(i0,r0) _sti_s(_jit,i0,r0)
770 static void _sti_s(jit_state_t*,jit_word_t,jit_int32_t);
771 # define str_i(r0,r1) SW(r1,0,r0)
772 # define sti_i(i0,r0) _sti_i(_jit,i0,r0)
773 static void _sti_i(jit_state_t*,jit_word_t,jit_int32_t);
774 # if __WORDSIZE == 64
775 # define str_l(r0,r1) SD(r1,0,r0)
776 # define sti_l(i0,r0) _sti_l(_jit,i0,r0)
777 static void _sti_l(jit_state_t*,jit_word_t,jit_int32_t);
779 # define stxr_c(r0,r1,r2) _stxr_c(_jit,r0,r1,r2)
780 static void _stxr_c(jit_state_t*,jit_int32_t,jit_int32_t,jit_int32_t);
781 # define stxi_c(i0,r0,r1) _stxi_c(_jit,i0,r0,r1)
782 static void _stxi_c(jit_state_t*,jit_word_t,jit_int32_t,jit_int32_t);
783 # define stxr_s(r0,r1,r2) _stxr_s(_jit,r0,r1,r2)
784 static void _stxr_s(jit_state_t*,jit_int32_t,jit_int32_t,jit_int32_t);
785 # define stxi_s(i0,r0,r1) _stxi_s(_jit,i0,r0,r1)
786 static void _stxi_s(jit_state_t*,jit_word_t,jit_int32_t,jit_int32_t);
787 # define stxr_i(r0,r1,r2) _stxr_i(_jit,r0,r1,r2)
788 static void _stxr_i(jit_state_t*,jit_int32_t,jit_int32_t,jit_int32_t);
789 # define stxi_i(i0,r0,r1) _stxi_i(_jit,i0,r0,r1)
790 static void _stxi_i(jit_state_t*,jit_word_t,jit_int32_t,jit_int32_t);
791 # if __WORDSIZE == 64
792 # define stxr_l(r0,r1,r2) _stxr_l(_jit,r0,r1,r2)
793 static void _stxr_l(jit_state_t*,jit_int32_t,jit_int32_t,jit_int32_t);
794 # define stxi_l(i0,r0,r1) _stxi_l(_jit,i0,r0,r1)
795 static void _stxi_l(jit_state_t*,jit_word_t,jit_int32_t,jit_int32_t);
797 # define unstr(r0, r1, i0) _unstr(_jit, r0, r1, i0)
798 static void _unstr(jit_state_t*, jit_int32_t, jit_int32_t, jit_word_t);
799 # define unsti(i0, r0, i1) _unsti(_jit, i0, r0, i1)
800 static void _unsti(jit_state_t*, jit_word_t, jit_int32_t, jit_word_t);
801 # define bswapr_us(r0,r1) _bswapr_us(_jit,r0,r1)
802 static void _bswapr_us(jit_state_t*,jit_int32_t,jit_int32_t);
803 # define bswapr_ui(r0,r1) _bswapr_ui(_jit,r0,r1)
804 static void _bswapr_ui(jit_state_t*,jit_int32_t,jit_int32_t);
805 # if __WORDSIZE == 64
806 # define bswapr_ul(r0,r1) _bswapr_ul(_jit,r0,r1)
807 static void _bswapr_ul(jit_state_t*,jit_int32_t,jit_int32_t);
809 #define extr(r0,r1,i0,i1) fallback_ext(r0,r1,i0,i1)
810 #define extr_u(r0,r1,i0,i1) _extr_u(_jit,r0,r1,i0,i1)
811 static void _extr_u(jit_state_t*,jit_int32_t,jit_int32_t,jit_word_t,jit_word_t);
812 #define depr(r0,r1,i0,i1) _depr(_jit,r0,r1,i0,i1)
813 static void _depr(jit_state_t*,jit_int32_t,jit_int32_t,jit_word_t,jit_word_t);
814 # define extr_c(r0,r1) _extr_c(_jit,r0,r1)
815 static void _extr_c(jit_state_t*,jit_int32_t,jit_int32_t);
816 # define extr_uc(r0,r1) ANDI(r0,r1,0xff)
817 # define extr_s(r0,r1) _extr_s(_jit,r0,r1)
818 static void _extr_s(jit_state_t*,jit_int32_t,jit_int32_t);
819 # define extr_us(r0,r1) ANDI(r0,r1,0xffff)
820 # if __WORDSIZE == 64
821 # define extr_i(r0,r1) SLL(r0,r1,0)
822 # define extr_ui(r0,r1) _extr_ui(_jit,r0,r1)
823 static void _extr_ui(jit_state_t*,jit_int32_t,jit_int32_t);
825 # define ltr(r0,r1,r2) SLT(r0,r1,r2)
826 # define lti(r0,r1,i0) _lti(_jit,r0,r1,i0)
827 static void _lti(jit_state_t*,jit_int32_t,jit_int32_t,jit_word_t);
828 # define ltr_u(r0,r1,r2) SLTU(r0,r1,r2)
829 # define lti_u(r0,r1,i0) _lti_u(_jit,r0,r1,i0)
830 static void _lti_u(jit_state_t*,jit_int32_t,jit_int32_t,jit_word_t);
831 #define ler(r0,r1,r2) _ler(_jit,r0,r1,r2)
832 static void _ler(jit_state_t*,jit_int32_t,jit_int32_t,jit_int32_t);
833 #define lei(r0,r1,i0) _lei(_jit,r0,r1,i0)
834 static void _lei(jit_state_t*,jit_int32_t,jit_int32_t,jit_word_t);
835 #define ler_u(r0,r1,r2) _ler_u(_jit,r0,r1,r2)
836 static void _ler_u(jit_state_t*,jit_int32_t,jit_int32_t,jit_int32_t);
837 #define lei_u(r0,r1,i0) _lei_u(_jit,r0,r1,i0)
838 static void _lei_u(jit_state_t*,jit_int32_t,jit_int32_t,jit_word_t);
839 #define eqr(r0,r1,r2) _eqr(_jit,r0,r1,r2)
840 static void _eqr(jit_state_t*,jit_int32_t,jit_int32_t,jit_int32_t);
841 #define eqi(r0,r1,i0) _eqi(_jit,r0,r1,i0)
842 static void _eqi(jit_state_t*,jit_int32_t,jit_int32_t,jit_word_t);
843 #define ger(r0,r1,r2) _ger(_jit,r0,r1,r2)
844 static void _ger(jit_state_t*,jit_int32_t,jit_int32_t,jit_int32_t);
845 #define gei(r0,r1,i0) _gei(_jit,r0,r1,i0)
846 static void _gei(jit_state_t*,jit_int32_t,jit_int32_t,jit_word_t);
847 #define ger_u(r0,r1,i0) _ger_u(_jit,r0,r1,i0)
848 static void _ger_u(jit_state_t*,jit_int32_t,jit_int32_t,jit_int32_t);
849 #define gei_u(r0,r1,i0) _gei_u(_jit,r0,r1,i0)
850 static void _gei_u(jit_state_t*,jit_int32_t,jit_int32_t,jit_word_t);
851 # define gtr(r0,r1,r2) SLT(r0,r2,r1)
852 #define gti(r0,r1,i0) _gti(_jit,r0,r1,i0)
853 static void _gti(jit_state_t*,jit_int32_t,jit_int32_t,jit_word_t);
854 # define gtr_u(r0,r1,r2) SLTU(r0,r2,r1)
855 # define gti_u(r0,r1,i0) _gti_u(_jit,r0,r1,i0)
856 static void _gti_u(jit_state_t*,jit_int32_t,jit_int32_t,jit_word_t);
857 #define ner(r0,r1,r2) _ner(_jit,r0,r1,r2)
858 static void _ner(jit_state_t*,jit_int32_t,jit_int32_t,jit_int32_t);
859 #define nei(r0,r1,i0) _nei(_jit,r0,r1,i0)
860 static void _nei(jit_state_t*,jit_int32_t,jit_int32_t,jit_word_t);
861 #define bltr(i0,r0,r1) bger(i0,r1,r0)
862 #define bltr_u(i0,r0,r1) bger_u(i0,r1,r0)
863 #define blti(i0,r0,i1) _bgei(_jit,i0,r0,i1,0,1)
864 #define blti_u(i0,r0,i1) _bgei(_jit,i0,r0,i1,1,1)
865 #define bler(i0,r0,r1) _bgtr(_jit,i0,r1,r0,0,1)
866 #define bler_u(i0,r0,r1) _bgtr(_jit,i0,r1,r0,1,1)
867 #define blei(i0,r0,i1) _bgti(_jit,i0,r0,i1,0,1)
868 #define blei_u(i0,r0,i1) _bgti(_jit,i0,r0,i1,1,1)
869 #define beqr(i0,r0,r1) _beqr(_jit,i0,r0,r1)
870 static jit_word_t _beqr(jit_state_t*,jit_word_t,jit_int32_t,jit_int32_t);
871 #define beqi(i0,r0,i1) _beqi(_jit,i0,r0,i1)
872 static jit_word_t _beqi(jit_state_t*,jit_word_t,jit_int32_t,jit_word_t);
873 #define bger(i0,r0,r1) _bger(_jit,i0,r0,r1,0)
874 #define bger_u(i0,r0,r1) _bger(_jit,i0,r0,r1,1)
875 static jit_word_t _bger(jit_state_t*,jit_word_t,jit_int32_t,jit_int32_t,
877 #define bgei(i0,r0,i1) _bgei(_jit,i0,r0,i1,0,0)
878 #define bgei_u(i0,r0,i1) _bgei(_jit,i0,r0,i1,1,0)
879 static jit_word_t _bgei(jit_state_t*,jit_word_t,jit_int32_t,jit_word_t,
880 jit_bool_t,jit_bool_t);
881 #define bgtr(i0,r0,r1) _bgtr(_jit,i0,r0,r1,0,0)
882 #define bgtr_u(i0,r0,r1) _bgtr(_jit,i0,r0,r1,1,0)
883 static jit_word_t _bgtr(jit_state_t*,jit_word_t,jit_int32_t,jit_int32_t,
884 jit_bool_t,jit_bool_t);
885 #define bgti(i0,r0,i1) _bgti(_jit,i0,r0,i1,0,0)
886 #define bgti_u(i0,r0,i1) _bgti(_jit,i0,r0,i1,1,0)
887 static jit_word_t _bgti(jit_state_t*,jit_word_t,jit_int32_t,jit_word_t,
888 jit_bool_t,jit_bool_t);
889 #define bner(i0,r0,r1) _bner(_jit,i0,r0,r1)
890 static jit_word_t _bner(jit_state_t*,jit_word_t,jit_int32_t,jit_int32_t);
891 #define bnei(i0,r0,i1) _bnei(_jit,i0,r0,i1)
892 static jit_word_t _bnei(jit_state_t*,jit_word_t,jit_int32_t,jit_word_t);
893 # define jmpr(r0) _jmpr(_jit,r0)
894 static void _jmpr(jit_state_t*,jit_int32_t);
895 # define jmpi(i0,patch) _jmpi(_jit,i0,patch)
896 static jit_word_t _jmpi(jit_state_t*,jit_word_t,jit_bool_t);
897 # define jmpi_p(i0) _jmpi_p(_jit,i0)
898 static jit_word_t _jmpi_p(jit_state_t*,jit_word_t);
899 # define boaddr(i0,r0,r1) _boaddr(_jit,i0,r0,r1)
900 static jit_word_t _boaddr(jit_state_t*,jit_word_t,jit_int32_t,jit_int32_t);
901 # define boaddi(i0,r0,i1) _boaddi(_jit,i0,r0,i1)
902 static jit_word_t _boaddi(jit_state_t*,jit_word_t,jit_int32_t,jit_word_t);
903 # define boaddr_u(i0,r0,r1) _boaddr_u(_jit,i0,r0,r1)
904 static jit_word_t _boaddr_u(jit_state_t*,jit_word_t,jit_int32_t,jit_int32_t);
905 # define boaddi_u(i0,r0,i1) _boaddi_u(_jit,i0,r0,i1)
906 static jit_word_t _boaddi_u(jit_state_t*,jit_word_t,jit_int32_t,jit_word_t);
907 # define bxaddr(i0,r0,r1) _bxaddr(_jit,i0,r0,r1)
908 static jit_word_t _bxaddr(jit_state_t*,jit_word_t,jit_int32_t,jit_int32_t);
909 # define bxaddi(i0,r0,i1) _bxaddi(_jit,i0,r0,i1)
910 static jit_word_t _bxaddi(jit_state_t*,jit_word_t,jit_int32_t,jit_word_t);
911 # define bxaddr_u(i0,r0,r1) _bxaddr_u(_jit,i0,r0,r1)
912 static jit_word_t _bxaddr_u(jit_state_t*,jit_word_t,jit_int32_t,jit_int32_t);
913 # define bxaddi_u(i0,r0,i1) _bxaddi_u(_jit,i0,r0,i1)
914 static jit_word_t _bxaddi_u(jit_state_t*,jit_word_t,jit_int32_t,jit_word_t);
915 # define bosubr(i0,r0,r1) _bosubr(_jit,i0,r0,r1)
916 static jit_word_t _bosubr(jit_state_t*,jit_word_t,jit_int32_t,jit_int32_t);
917 # define bosubi(i0,r0,i1) _bosubi(_jit,i0,r0,i1)
918 static jit_word_t _bosubi(jit_state_t*,jit_word_t,jit_int32_t,jit_word_t);
919 # define bosubr_u(i0,r0,r1) _bosubr_u(_jit,i0,r0,r1)
920 static jit_word_t _bosubr_u(jit_state_t*,jit_word_t,jit_int32_t,jit_int32_t);
921 # define bosubi_u(i0,r0,i1) _bosubi_u(_jit,i0,r0,i1)
922 static jit_word_t _bosubi_u(jit_state_t*,jit_word_t,jit_int32_t,jit_word_t);
923 # define bxsubr(i0,r0,r1) _bxsubr(_jit,i0,r0,r1)
924 static jit_word_t _bxsubr(jit_state_t*,jit_word_t,jit_int32_t,jit_int32_t);
925 # define bxsubi(i0,r0,i1) _bxsubi(_jit,i0,r0,i1)
926 static jit_word_t _bxsubi(jit_state_t*,jit_word_t,jit_int32_t,jit_word_t);
927 # define bxsubr_u(i0,r0,r1) _bxsubr_u(_jit,i0,r0,r1)
928 static jit_word_t _bxsubr_u(jit_state_t*,jit_word_t,jit_int32_t,jit_int32_t);
929 # define bxsubi_u(i0,r0,i1) _bxsubi_u(_jit,i0,r0,i1)
930 static jit_word_t _bxsubi_u(jit_state_t*,jit_word_t,jit_int32_t,jit_word_t);
931 # define bmsr(i0,r0,r1) _bmsr(_jit,i0,r0,r1)
932 static jit_word_t _bmsr(jit_state_t*,jit_word_t,jit_int32_t,jit_int32_t);
933 # define bmsi(i0,r0,i1) _bmsi(_jit,i0,r0,i1)
934 static jit_word_t _bmsi(jit_state_t*,jit_word_t,jit_int32_t,jit_word_t);
935 # define bmcr(i0,r0,r1) _bmcr(_jit,i0,r0,r1)
936 static jit_word_t _bmcr(jit_state_t*,jit_word_t,jit_int32_t,jit_int32_t);
937 # define bmci(i0,r0,i1) _bmci(_jit,i0,r0,i1)
938 static jit_word_t _bmci(jit_state_t*,jit_word_t,jit_int32_t,jit_word_t);
939 # define callr(r0) _callr(_jit,r0)
940 static void _callr(jit_state_t*,jit_int32_t);
941 # define calli(i0,i1) _calli(_jit,i0,i1)
942 static jit_word_t _calli(jit_state_t*,jit_word_t,jit_bool_t);
943 # define calli_p(i0) _calli_p(_jit,i0)
944 static jit_word_t _calli_p(jit_state_t*,jit_word_t);
945 # define prolog(node) _prolog(_jit,node)
946 static void _prolog(jit_state_t*,jit_node_t*);
947 # define epilog(node) _epilog(_jit,node)
948 static void _epilog(jit_state_t*,jit_node_t*);
949 # define vastart(r0) _vastart(_jit, r0)
950 static void _vastart(jit_state_t*, jit_int32_t);
951 # define vaarg(r0, r1) _vaarg(_jit, r0, r1)
952 static void _vaarg(jit_state_t*, jit_int32_t, jit_int32_t);
953 #define patch_abs(instr,label) _patch_abs(_jit,instr,label)
954 static void _patch_abs(jit_state_t*,jit_word_t,jit_word_t);
955 #define patch_at(jump,label) _patch_at(_jit,jump,label)
956 static void _patch_at(jit_state_t*,jit_word_t,jit_word_t);
957 /* definitions used by jit_get_reg_for_delay_slot() */
958 #include "jit_mips-fpu.c"
963 _instr(jit_state_t *_jit, jit_int32_t op)
965 if (_jitc->inst.pend)
968 _jitc->inst.pend = 1;
973 _flush(jit_state_t *_jit)
975 if (_jitc->inst.pend) {
977 _jitc->inst.pend = 0;
982 _pending(jit_state_t *_jit)
985 if (_jitc->inst.pend) {
987 _jitc->inst.pend = 0;
995 _delay(jit_state_t *_jit, jit_int32_t op)
997 assert(_jitc->inst.pend);
999 _jitc->inst.pend = 0;
1004 _jit_get_reg_for_delay_slot(jit_state_t *_jit, jit_int32_t mask,
1005 jit_int32_t reg0, jit_int32_t reg1)
1008 jit_int32_t reg, r0, r1, r2/*, xreg*/, regs[3];
1009 /* If will emit a pending instruction */
1010 if (_jitc->inst.pend)
1011 i.op = _jitc->inst.op;
1012 /* Else if at least one instruction emited, check it */
1013 else if (_jit->pc.uc > _jit->code.ptr)
1014 i.op = _jit->pc.ui[-1];
1018 regs[0] = regs[1] = regs[2]/* = xreg*/ = -1;
1020 case MIPS_SPECIAL: /* 00 */
1022 case MIPS_SLLV: /* 04 */
1023 case MIPS_SRLV: /* 06 */
1024 case MIPS_SRAV: /* 07 */
1025 case MIPS_DSLLV: /* 14 */
1026 case MIPS_DSRLV: /* 16 */
1027 case MIPS_DSRAV: /* 17 */
1028 case MIPS_ADDU: /* 21 */
1029 case MIPS_SUBU: /* 23 */
1030 case MIPS_AND: /* 24 */
1031 case MIPS_OR: /* 25 */
1032 case MIPS_XOR: /* 26 */
1033 case MIPS_NOR: /* 27 */
1034 case MIPS_SLT: /* 2a */
1035 case MIPS_SLTU: /* 2b */
1036 case MIPS_DADDU: /* 2d */
1037 case MIPS_DSUBU: /* 2f */
1038 if (mask & jit_class_gpr) {
1045 case MIPS_MULT: /* 18 */
1047 case MIPS_MULTU: /* 19 */
1049 case MIPS_DIV: /* 1a */
1051 case MIPS_DIVU: /* 1b */
1053 case MIPS_DMULT: /* 1c */
1055 case MIPS_DMULTU: /* 1d */
1057 case MIPS_DDIV: /* 1e */
1059 case MIPS_DDIVU: /* 1f */
1060 if (jit_mips6_p()) {
1061 assert(i.ic.b == 2 || i.ic.b == 3);
1062 if (mask & jit_class_gpr) {
1069 assert(i.rd.b == 0);
1070 if (mask & jit_class_gpr) {
1078 case MIPS_MFHI: /* 10 */
1080 case MIPS_MTHI: /* 11 */
1082 case MIPS_MFLO: /* 12 */
1084 case MIPS_MTLO: /* 13 */
1085 if (mask & jit_class_gpr) {
1086 if (jit_mips6_p()) {
1087 assert(i.ic.b == 1);
1091 assert(!i.rs.b && !i.rt.b);
1098 case MIPS_JR: /* 08 */
1099 assert(!jit_mips6_p());
1100 case MIPS_JALR: /* 09 */
1101 /* check for proper/known encondig */
1103 if (mask & jit_class_gpr) {
1109 case MIPS_SLL: /* 00 */
1110 /* If cannot have a shift in delay slot */
1111 if (!jit_cpu.sll_delay)
1113 case MIPS_SRL: /* 02 */
1114 case MIPS_SRA: /* 03 */
1115 case MIPS_DSLL: /* 38 */
1116 case MIPS_DSRL: /* 3a */
1117 case MIPS_DSRA: /* 3b */
1118 case MIPS_DSLL32: /* 3c */
1119 case MIPS_DSRA32: /* 3f */
1120 case MIPS_DSRL32: /* 3e */
1121 /* shift (or rotate if i.rs.b == 1) */
1122 assert(i.rs.b == 0 || i.rs.b == 1);
1123 if (mask & jit_class_gpr) {
1129 case MIPS_SYNC: /* 0f */
1130 assert(i.rs.b == 0 && i.rt.b == 0 && i.rd.b == 0);
1131 if (mask & jit_class_gpr)
1132 regs[0] = regs[1] = regs[2] = 0;
1134 case MIPS_MOVZ: /* 0a */
1135 case MIPS_MOVN: /* 0b */
1136 assert(!jit_mips6_p() && i.ic.b == 0);
1137 if (mask & jit_class_gpr) {
1147 assert(jit_mips6_p() && i.ic.b == 0);
1148 if (mask & jit_class_gpr) {
1158 case MIPS_REGIMM: /* 01 */
1164 assert(jit_mips6_p());
1165 case MIPS_BLTZ: /* 00 */
1166 case MIPS_BGEZ: /* 01 */
1167 case MIPS_BGEZAL: /* 11 */
1172 if (mask & jit_class_gpr) {
1174 regs[1] = regs[2] = 0;
1177 case MIPS_BC_R6: /* 32 */
1178 case MIPS_BALC: /* 3a */
1179 assert(jit_mips6_p());
1180 case MIPS_J: /* 02 */
1181 case MIPS_JAL: /* 03 */
1182 if (mask & jit_class_gpr)
1183 regs[0] = regs[1] = regs[2] = 0;
1185 case MIPS_LUI: /* 0f */
1186 assert(jit_mips6_p() || i.rs.b == 0);
1187 if (mask & jit_class_gpr) {
1189 regs[1] = i.rs.b; /* AUI if non zero */
1193 case MIPS_SPECIAL2: /* 1c */
1195 case MIPS_CLZ: /* 20 */
1196 case MIPS_CLO: /* 21 */
1197 case MIPS_DCLZ: /* 24 */
1198 case MIPS_DCLO: /* 25 */
1199 assert(!jit_mips6_p() && i.rt.b == i.rd.b && i.ic.b == 0);
1200 if (mask & jit_class_gpr) {
1206 case MIPS_MUL: /* 02 */
1207 assert(jit_mips2_p() && i.ic.b == 0);
1208 if (mask & jit_class_gpr) {
1218 case MIPS_SPECIAL3: /* 1f */
1220 case MIPS_EXT: /* 00 */
1221 case MIPS_DEXTM: /* 01 */
1222 case MIPS_DEXTU: /* 02 */
1223 case MIPS_DEXT: /* 03 */
1224 case MIPS_INS: /* 04 */
1225 case MIPS_DINSM: /* 05 */
1226 case MIPS_DINSU: /* 06 */
1227 case MIPS_DINS: /* 07 */
1228 if (mask & jit_class_gpr) {
1235 case MIPS_BSHFL: /* 20 */
1237 case MIPS_DBSHFL: /* 24 */
1240 case MIPS_WSBH: /* 02 */
1241 case MIPS_DSHD: /* 05 */
1242 case MIPS_SEB: /* 10 */
1243 case MIPS_SEH: /* 18 */
1244 if (mask & jit_class_gpr) {
1250 /* BITSWAP DBITSWAP */
1252 assert(jit_mips6_p() && i.rt.b == 0);
1253 if (mask & jit_class_gpr) {
1271 assert(jit_mips6_p());
1272 if (mask & jit_class_gpr) {
1282 case MIPS_COP1: /* 11 */
1284 case MIPS_ADD_fmt: /* 00 */
1286 case MIPS_MF: /* 00 */
1287 case MIPS_DMF: /* 01 */
1288 case MIPS_MFH: /* 03 */
1289 case MIPS_MT: /* 04 */
1290 case MIPS_DMT: /* 05 */
1291 case MIPS_MTH: /* 07 */
1292 assert(i.ic.b == 0);
1293 /* If these cop1 instructions in delay slot
1295 if (!jit_cpu.cop1_delay)
1297 if (mask & jit_class_gpr) {
1299 regs[1] = regs[2] = 0;
1308 case MIPS_MADDF: /* 18 */
1309 case MIPS_MSUBF: /* 19 */
1310 assert(jit_mips6_p());
1311 case MIPS_SUB_fmt: /* 01 */
1312 case MIPS_MUL_fmt: /* 02 */
1313 case MIPS_DIV_fmt: /* 03 */
1316 assert(i.rs.b == MIPS_fmt_S ||
1318 i.rs.b == MIPS_fmt_D);
1319 if (mask & jit_class_gpr)
1320 regs[0] = regs[1] = regs[2] = 0;
1327 case MIPS_SQRT_fmt: /* 04 */
1328 case MIPS_ABS_fmt: /* 05 */
1329 case MIPS_MOV_fmt: /* 06 */
1330 case MIPS_NEG_fmt: /* 07 */
1331 assert((i.rs.b == MIPS_fmt_S || i.rs.b == MIPS_fmt_D) &&
1333 if (mask & jit_class_gpr)
1334 regs[0] = regs[1] = regs[2] = 0;
1340 case MIPS_CVT_fmt_S: /* 20 */
1341 case MIPS_CVT_fmt_D: /* 21 */
1342 case MIPS_CVT_fmt_W: /* 24 */
1343 case MIPS_CVT_fmt_L: /* 25 */
1345 case MIPS_fmt_S:/* 10 */
1346 case MIPS_fmt_D:/* 11 */
1347 case MIPS_fmt_W:/* 14 */
1348 case MIPS_fmt_L:/* 15 */
1353 assert(i.rt.b == 0);
1354 if (mask & jit_class_gpr)
1355 regs[0] = regs[1] = regs[2] = 0;
1361 case MIPS_cond_F: /* 30 */
1362 case MIPS_cond_UN: /* 31 */
1363 case MIPS_cond_EQ: /* 32 */
1364 case MIPS_cond_UEQ: /* 33 */
1365 case MIPS_cond_OLT: /* 34 */
1366 case MIPS_cond_ULT: /* 35 */
1367 case MIPS_cond_OLE: /* 36 */
1368 case MIPS_cond_ULE: /* 37 */
1369 case MIPS_cond_SF: /* 38 */
1370 case MIPS_cond_NGLE: /* 39 */
1371 case MIPS_cond_SEQ: /* 3a */
1372 case MIPS_cond_NGL: /* 3b */
1373 case MIPS_cond_LT: /* 3c */
1374 case MIPS_cond_NGE: /* 3d */
1375 case MIPS_cond_LE: /* 3e */
1376 case MIPS_cond_UGT: /* 3f */
1377 assert(!jit_mips6_p() &&
1379 (i.fm.b == MIPS_fmt_S ||
1381 i.fm.b == MIPS_fmt_D));
1382 if (mask & jit_class_gpr)
1383 regs[0] = regs[1] = regs[2] = 0;
1391 case MIPS_cmp_AF: /* 00 */
1392 case MIPS_cmp_UN: /* 01 */
1393 case MIPS_cmp_EQ: /* 02 */
1394 case MIPS_cmp_UEQ: /* 03 */
1395 case MIPS_cmp_LT: /* 04 */
1396 case MIPS_cmp_ULT: /* 05 */
1397 case MIPS_cmp_LE: /* 06 */
1398 case MIPS_cmp_ULE: /* 07 */
1399 case MIPS_cmp_SAF: /* 08 */
1400 case MIPS_cmp_SUN: /* 09 */
1401 case MIPS_cmp_SEQ: /* 0a */
1402 case MIPS_cmp_SUEQ:/* 0b */
1403 case MIPS_cmp_SLT: /* 0c */
1404 case MIPS_cmp_SULT:/* 0d */
1405 case MIPS_cmp_SLE: /* 0e */
1406 case MIPS_cmp_SULE:/* 0f */
1407 assert(jit_mips6_p() &&
1409 (i.rs.b == MIPS_condn_S ||
1411 i.rs.b == MIPS_condn_D));
1412 if (mask & jit_class_gpr)
1413 regs[0] = regs[1] = regs[2] = 0;
1424 case MIPS_BC: /* 08 */
1425 assert(!jit_mips6_p() &&
1427 (i.rs.b == MIPS_BCF ||
1429 i.rs.b == MIPS_BCT));
1430 if (mask & jit_class_gpr)
1431 regs[0] = regs[1] = regs[2] = 0;
1437 case MIPS_BC1EQZ:/* 09 */
1438 case MIPS_BC1NEZ:/* 0a */
1439 assert(jit_mips6_p());
1440 if (mask & jit_class_gpr)
1441 regs[0] = regs[1] = regs[2] = 0;
1451 case MIPS_COP1X: /* 13 */
1453 case MIPS_MADD_fmt_S:
1454 case MIPS_MADD_fmt_D:
1455 case MIPS_MSUB_fmt_S:
1456 case MIPS_MSUB_fmt_D:
1457 case MIPS_NMADD_fmt_S:
1458 case MIPS_NMADD_fmt_D:
1459 case MIPS_NMSUB_fmt_S:
1460 case MIPS_NMSUB_fmt_D:
1461 assert(!jit_mips6_p());
1462 if (mask & jit_class_gpr)
1463 regs[0] = regs[1] = regs[2] = 0;
1468 /* FIXME No need to compute and check it.
1469 * If asking for a tmeporary fpr, code will
1471 /* xreg = i.fr.b; */
1478 case MIPS_DAUI: /* JALX */ /* 1d */
1479 /* Do not generate JALX. No microMIPS64 or MIPS16e support */
1480 assert(jit_mips6_p() && i.rs.b != 0);
1481 case MIPS_ADDIU: /* 09 */
1482 case MIPS_SLTI: /* 0a */
1483 case MIPS_SLTIU: /* 0b */
1484 case MIPS_ANDI: /* 0c */
1485 case MIPS_ORI: /* 0d */
1486 case MIPS_XORI: /* 0e */
1487 case MIPS_DADDIU: /* 18 */
1488 case MIPS_LDL: /* 1a */
1489 case MIPS_LDR: /* 1b */
1490 case MIPS_LB: /* 20 */
1491 case MIPS_LH: /* 21 */
1492 case MIPS_LW: /* 23 */
1493 case MIPS_LBU: /* 24 */
1494 case MIPS_LHU: /* 25 */
1495 case MIPS_LWU: /* 27 */
1496 case MIPS_SB: /* 28 */
1497 case MIPS_SH: // 29 */
1498 case MIPS_SW: /* 2b */
1499 case MIPS_LD: /* 37 */
1500 case MIPS_SD: /* 3f */
1501 if (mask & jit_class_gpr) {
1507 case MIPS_LWL: /* 22 */
1508 case MIPS_LWR: /* 26 */
1509 if (!jit_cpu.lwl_lwr_delay)
1511 case MIPS_SWL: /* 2a */
1512 case MIPS_SWR: /* 2e */
1513 case MIPS_SDL: /* 2c */
1514 case MIPS_SDR: /* 2d */
1515 assert(!(jit_mips6_p()));
1516 if (mask & jit_class_gpr) {
1522 case MIPS_LL: /* 30 */
1523 case MIPS_LLD: /* 34 */
1524 case MIPS_SC: /* 38 */
1525 case MIPS_SCD: /* 3c */
1526 assert(!jit_mips6_p() && i.ic.b == 0);
1527 if (mask & jit_class_gpr) {
1533 case MIPS_BLEZ: /* 06 */
1534 case MIPS_BGTZ: /* 07 */
1535 assert(i.rt.b == 0);
1536 if (mask & jit_class_gpr) {
1538 regs[1] = regs[2] = 0;
1541 case MIPS_LWC1: /* 31 */
1542 case MIPS_LDC1: /* 35 */
1543 case MIPS_SWC1: /* 39 */
1544 case MIPS_SDC1: /* 3d */
1545 /* If these cop1 instructions in delay wont not work */
1546 if (!jit_cpu.cop1_delay)
1548 if (mask & jit_class_gpr) {
1556 case MIPS_BEQ: /* 04 */
1557 case MIPS_BNE: /* 05 */
1558 assert(i.rt.b == 0);
1559 if (mask & jit_class_gpr) {
1567 case MIPS_PCREL: /* 0x3b */
1568 assert(jit_mips6_p());
1570 case 0x1e: /* AUIPC */
1571 case 0x1f: /* ALUIPC */
1574 assert(i.pD.b == 1 ||/* LDPC */
1575 i.pW.b == 0 ||/* ADDIUPC */
1576 i.pW.b == 1 ||/* LWPC */
1577 i.pW.b == 2); /* LWUPC */
1580 if (mask & jit_class_gpr) {
1582 regs[1] = regs[2] = 0;
1589 /* If cannot move instruction do delay slot */
1590 if (_jitc->inst.pend &&
1591 (((mask & jit_class_fpr) || reg0) &&
1592 (reg0 == regs[0] || reg0 == regs[1] || reg0 == regs[2])) ||
1593 (((mask & jit_class_fpr) || reg1) &&
1594 (reg1 == regs[0] || reg1 == regs[1] || reg1 == regs[2]))) {
1597 /* Get a temporary register */
1599 reg = jit_get_reg(mask|jit_class_nospill);
1600 /* Make sure will not use a register in use by delay slot */
1601 if (_jitc->inst.pend) {
1602 if (rn(reg) == regs[0] ||
1603 rn(reg) == regs[1] || rn(reg) == regs[2]) {
1605 reg = jit_get_reg(mask|jit_class_nospill);
1606 if (rn(reg) == regs[0] ||
1607 rn(reg) == regs[1] || rn(reg) == regs[2]) {
1609 reg = jit_get_reg(mask|jit_class_nospill);
1610 if (rn(reg) == regs[0] ||
1611 rn(reg) == regs[1] || rn(reg) == regs[2]) {
1613 reg = jit_get_reg(mask|jit_class_nospill);
1621 if (reg == JIT_NOREG) {
1622 /* Cannot get a register to optimize delay slot */
1624 /* Must find a free register */
1625 if (!(mask & jit_class_chk))
1628 assert(reg != JIT_NOREG || (mask & jit_class_chk));
1633 _hrrrit(jit_state_t *_jit,jit_int32_t hc,
1634 jit_int32_t rs, jit_int32_t rt, jit_int32_t rd,
1635 jit_int32_t ic, jit_int32_t tc)
1648 _hrri(jit_state_t *_jit, jit_int32_t hc,
1649 jit_int32_t rs, jit_int32_t rt, jit_int32_t im)
1661 _hrri9(jit_state_t *_jit, jit_int32_t hc,
1662 jit_int32_t rs, jit_int32_t rt, jit_int32_t i9, jit_int32_t tc)
1675 _hriD(jit_state_t *_jit, jit_int32_t hc,
1676 jit_int32_t rs, jit_int32_t pD, jit_int32_t iD)
1687 _hriW(jit_state_t *_jit, jit_int32_t hc,
1688 jit_int32_t rs, jit_int32_t pW, jit_int32_t iW)
1699 _hi(jit_state_t *_jit, jit_int32_t hc, jit_int32_t im)
1708 _nop(jit_state_t *_jit, jit_int32_t i0)
1710 for (; i0 > 0; i0 -= 4)
1716 _mips_extr(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1,
1717 jit_int32_t pos, jit_int32_t size)
1721 if (__WORDSIZE == 32)
1722 EXT(r0, r1, pos, size);
1724 DEXTU(r0, r1, pos, size);
1726 DEXTM(r0, r1, pos, size);
1728 DEXT(r0, r1, pos, size);
1732 _insr(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1,
1733 jit_int32_t pos, jit_int32_t size)
1737 if (__WORDSIZE == 32)
1738 INS(r0, r1, pos, size);
1740 DINSU(r0, r1, pos, size);
1742 DINSM(r0, r1, pos, size);
1744 DINS(r0, r1, pos, size);
1748 _clor(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1)
1750 #if __WORDSIZE == 32
1753 else if (jit_mips2_p())
1756 fallback_clo(r0, r1);
1758 assert(jit_mips2_p());
1767 _clzr(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1)
1769 #if __WORDSIZE == 32
1772 else if (jit_mips2_p())
1775 fallback_clz(r0, r1);
1777 assert(jit_mips2_p());
1786 _ctor(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1)
1788 if (jit_mips6_p()) {
1799 _ctzr(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1)
1801 if (jit_mips6_p()) {
1808 t0 = jit_get_reg(jit_class_gpr);
1809 t1 = jit_get_reg(jit_class_gpr);
1812 andr(rn(t0), rn(t0), r1);
1814 xori(rn(t1), r0, __WORDSIZE - 1);
1815 movnr(r0, rn(t1), rn(t0));
1823 _rbitr(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1)
1825 if (jit_mips6_p()) {
1826 #if __WORDSIZE == 32
1835 fallback_rbit(r0, r1);
1839 _addi(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_word_t i0)
1844 else if (can_sign_extend_short_p(i0))
1847 if (jit_mips6_p()) {
1850 # if __BYTE_ORDER == __LITTLE_ENDIAN
1852 jit_word_t aui : 16;
1853 # if __WORDSIZE == 64
1854 jit_word_t ahi : 16;
1855 jit_word_t ati : 16;
1858 # if __WORDSIZE == 64
1859 jit_word_t ati : 16;
1860 jit_word_t ahi : 16;
1862 jit_word_t aui : 16;
1869 if (r0 == r1 && ((jit_word_t)bits.b.aui << 16) == i0)
1870 /* FIXME It should not be required r0 == r1 per
1871 * documentation, but this is now it works in qemu
1872 * for DAUI. Assume AUI has the same restriction. */
1873 DAUI(r1, r0, bits.b.aui & 0xffff);
1874 #if __WORDSIZE == 64
1875 else if (r0 == r1 && ((jit_word_t)bits.b.ahi << 32) == i0)
1876 DAHI(r0, bits.b.ahi & 0xffff);
1877 else if (r0 == r1 && ((jit_word_t)bits.b.ati << 48) == i0)
1878 DATI(r0, bits.b.ati & 0xffff);
1885 reg = jit_get_reg(jit_class_gpr);
1887 addr(r0, r1, rn(reg));
1894 _addcr(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_int32_t r2)
1898 if (jit_carry == _NOREG)
1899 jit_carry = jit_get_reg(jit_class_gpr);
1901 t0 = jit_get_reg(jit_class_gpr);
1902 addr(rn(t0), r1, r2);
1903 SLTU(rn(jit_carry), rn(t0), r1);
1909 SLTU(rn(jit_carry), r0, r1);
1914 _addci(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_word_t i0)
1918 if (jit_carry == _NOREG)
1919 jit_carry = jit_get_reg(jit_class_gpr);
1920 t0 = jit_get_reg(jit_class_gpr);
1922 if (can_sign_extend_short_p(i0))
1923 addiu(rn(t0), r1, i0);
1926 addr(rn(t0), r1, rn(t0));
1928 SLTU(rn(jit_carry), rn(t0), r1);
1932 if (can_sign_extend_short_p(i0))
1936 addr(r0, r1, rn(t0));
1938 SLTU(rn(jit_carry), r0, r1);
1944 _addxr(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_int32_t r2)
1948 assert(jit_carry != _NOREG);
1949 t0 = jit_get_reg(jit_class_gpr);
1950 movr(rn(t0), rn(jit_carry));
1952 addcr(r0, r0, rn(t0));
1957 _addxi(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_word_t i0)
1961 assert(jit_carry != _NOREG);
1962 t0 = jit_get_reg(jit_class_gpr);
1963 movr(rn(t0), rn(jit_carry));
1965 addcr(r0, r0, rn(t0));
1970 _subi(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_word_t i0)
1975 else if (can_sign_extend_short_p(i0) && (i0 & 0xffff) != 0x8000)
1978 reg = jit_get_reg(jit_class_gpr);
1980 subr(r0, r1, rn(reg));
1986 _subcr(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_int32_t r2)
1990 if (jit_carry == _NOREG)
1991 jit_carry = jit_get_reg(jit_class_gpr);
1993 t0 = jit_get_reg(jit_class_gpr);
1994 subr(rn(t0), r1, r2);
1995 SLTU(rn(jit_carry), r1, rn(t0));
2001 SLTU(rn(jit_carry), r1, r0);
2006 _subci(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_word_t i0)
2010 if (jit_carry == _NOREG)
2011 jit_carry = jit_get_reg(jit_class_gpr);
2012 t0 = jit_get_reg(jit_class_gpr);
2014 if (can_sign_extend_short_p(i0) && (i0 & 0xffff) != 0x8000)
2015 addiu(rn(t0), r1, -i0);
2018 subr(rn(t0), r1, rn(t0));
2020 SLTU(rn(jit_carry), r1, rn(t0));
2024 if (can_sign_extend_short_p(i0) && (i0 & 0xffff) != 0x8000)
2028 subr(r0, r1, rn(t0));
2030 SLTU(rn(jit_carry), r1, r0);
2036 _subxr(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_int32_t r2)
2040 assert(jit_carry != _NOREG);
2041 t0 = jit_get_reg(jit_class_gpr);
2042 movr(rn(t0), rn(jit_carry));
2044 subcr(r0, r0, rn(t0));
2049 _subxi(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_word_t i0)
2053 assert(jit_carry != _NOREG);
2054 t0 = jit_get_reg(jit_class_gpr);
2055 movr(rn(t0), rn(jit_carry));
2057 subcr(r0, r0, rn(t0));
2062 _rsbi(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_word_t i0)
2069 _mulr(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_int32_t r2)
2074 if (jit_mips2_p() && __WORDSIZE == 32)
2084 _muli(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_word_t i0)
2088 reg = jit_get_reg(jit_class_gpr);
2090 mulr(r0, r1, rn(reg));
2095 _hmulr(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_int32_t r2)
2106 _hmuli(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_word_t i0)
2109 reg = jit_get_reg(jit_class_gpr);
2111 hmulr(r0, r1, rn(reg));
2116 _hmulr_u(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_int32_t r2)
2119 muhu_r6(r0, r1, r2);
2127 _hmuli_u(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_word_t i0)
2130 reg = jit_get_reg(jit_class_gpr);
2132 hmulr_u(r0, r1, rn(reg));
2137 _iqmulr(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1,
2138 jit_int32_t r2, jit_int32_t r3, jit_bool_t sign)
2141 if (jit_mips6_p()) {
2142 if (r0 == r2 || r0 == r3) {
2143 t0 = jit_get_reg(jit_class_gpr);
2145 mul_r6(rn(t0), r2, r3);
2147 mulu_r6(rn(t0), r2, r3);
2153 mulu_r6(r0, r2, r3);
2158 muhu_r6(r1, r2, r3);
2159 if (r0 == r2 || r0 == r3) {
2175 _iqmuli(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1,
2176 jit_int32_t r2, jit_word_t i0, jit_bool_t sign)
2179 reg = jit_get_reg(jit_class_gpr);
2181 iqmulr(r0, r1, r2, rn(reg), sign);
2186 _divr(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_int32_t r2)
2197 _divi(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_word_t i0)
2200 reg = jit_get_reg(jit_class_gpr);
2202 divr(r0, r1, rn(reg));
2207 _divr_u(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_int32_t r2)
2210 divu_r6(r0, r1, r2);
2218 _divi_u(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_word_t i0)
2221 reg = jit_get_reg(jit_class_gpr);
2223 divr_u(r0, r1, rn(reg));
2228 _iqdivr(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1,
2229 jit_int32_t r2, jit_int32_t r3, jit_bool_t sign)
2232 if (jit_mips6_p()) {
2233 if (r0 == r2 || r0 == r3)
2234 t0 = jit_get_reg(jit_class_gpr);
2241 div_r6(rn(t0), r2, r3);
2246 divu_r6(r0, r2, r3);
2248 divu_r6(rn(t0), r2, r3);
2249 modu_r6(r1, r2, r3);
2267 _iqdivi(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1,
2268 jit_int32_t r2, jit_word_t i0, jit_bool_t sign)
2271 reg = jit_get_reg(jit_class_gpr);
2273 iqdivr(r0, r1, r2, rn(reg), sign);
2278 _remr(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_int32_t r2)
2289 _remi(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_word_t i0)
2292 reg = jit_get_reg(jit_class_gpr);
2294 remr(r0, r1, rn(reg));
2299 _remr_u(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_int32_t r2)
2302 modu_r6(r0, r1, r2);
2310 _remi_u(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_word_t i0)
2313 reg = jit_get_reg(jit_class_gpr);
2315 remr_u(r0, r1, rn(reg));
2319 #if __WORDSIZE == 64
2321 _lshi(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_word_t i0)
2323 assert(i0 >= 0 && i0 <= 63);
2327 DSLL32(r0, r1, i0 - 32);
2331 _rshi(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_word_t i0)
2333 assert(i0 >= 0 && i0 <= 63);
2337 DSRA32(r0, r1, i0 - 32);
2341 _rshi_u(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_word_t i0)
2343 assert(i0 >= 0 && i0 <= 63);
2347 DSRL32(r0, r1, i0 - 32);
2352 _xlshr(jit_state_t *_jit, jit_bool_t sign,
2353 jit_int32_t r0, jit_int32_t r1, jit_int32_t r2, jit_int32_t r3)
2355 jit_int32_t t0, s0, t2, s2, t3, s3;
2356 s0 = jit_get_reg(jit_class_gpr);
2358 if (r0 == r2 || r1 == r2) {
2359 s2 = jit_get_reg(jit_class_gpr);
2365 if (r0 == r3 || r1 == r3) {
2366 s3 = jit_get_reg(jit_class_gpr);
2372 rsbi(t0, t3, __WORDSIZE);
2379 rshi(t0, t2, __WORDSIZE - 1);
2388 nei(t0, t3, __WORDSIZE);
2399 _xlshi(jit_state_t *_jit, jit_bool_t sign,
2400 jit_int32_t r0, jit_int32_t r1, jit_int32_t r2, jit_word_t i0)
2405 rshi(r1, r2, __WORDSIZE - 1);
2409 else if (i0 == __WORDSIZE) {
2414 assert((jit_uword_t)i0 <= __WORDSIZE);
2416 rshi(r1, r2, __WORDSIZE - i0);
2418 rshi_u(r1, r2, __WORDSIZE - i0);
2424 _xrshr(jit_state_t *_jit, jit_bool_t sign,
2425 jit_int32_t r0, jit_int32_t r1, jit_int32_t r2, jit_int32_t r3)
2427 jit_int32_t t0, s0, t2, s2, t3, s3;
2428 s0 = jit_get_reg(jit_class_gpr);
2430 if (r0 == r2 || r1 == r2) {
2431 s2 = jit_get_reg(jit_class_gpr);
2437 if (r0 == r3 || r1 == r3) {
2438 s3 = jit_get_reg(jit_class_gpr);
2447 eqi(t0, t3, __WORDSIZE);
2452 nei(t0, t3, __WORDSIZE);
2457 rsbi(t0, t3, __WORDSIZE);
2471 _xrshi(jit_state_t *_jit, jit_bool_t sign,
2472 jit_int32_t r0, jit_int32_t r1, jit_int32_t r2, jit_word_t i0)
2478 else if (i0 == __WORDSIZE) {
2481 rshi(r0, r2, __WORDSIZE - 1);
2486 assert((jit_uword_t)i0 <= __WORDSIZE);
2487 lshi(r1, r2, __WORDSIZE - i0);
2496 _lrotr(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_int32_t r2)
2499 if (jit_mips2_p()) {
2500 if (r0 != r1 && r0 != r2) {
2501 rsbi(r0, r2, __WORDSIZE);
2505 reg = jit_get_reg(jit_class_gpr);
2506 rsbi(rn(reg), r2, __WORDSIZE);
2507 rrotr(r0, r1, rn(reg));
2512 fallback_lrotr(r0, r1, r2);
2516 _rrotr(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_int32_t r2)
2518 if (jit_mips2_p()) {
2519 #if __WORDSIZE == 32
2526 fallback_rrotr(r0, r1, r2);
2530 _rroti(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_word_t i0)
2532 assert(i0 >= 0 && i0 <= __WORDSIZE - 1);
2533 if (jit_mips2_p()) {
2534 #if __WORDSIZE == 32
2540 DROTR32(r0, r1, i0 - 32);
2544 fallback_rroti(r0, r1, i0);
2548 _andi(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_word_t i0)
2551 if (can_zero_extend_short_p(i0))
2553 else if (is_low_mask(i0)) {
2555 mips_extr(r0, r1, 0, masked_bits_count(i0));
2557 lshi(r0, r1, unmasked_bits_count(i0));
2558 rshi_u(r0, r0, unmasked_bits_count(i0));
2560 } else if (is_high_mask(i0)) {
2561 if (jit_mips2_p() && r0 == r1)
2562 insr(r0, _ZERO_REGNO, 0, unmasked_bits_count(i0));
2564 rshi(r0, r1, unmasked_bits_count(i0));
2565 lshi(r0, r0, unmasked_bits_count(i0));
2567 } else if (jit_mips2_p() && is_middle_mask(i0)) {
2568 mips_extr(r0, r1, __builtin_ctzl(i0), masked_bits_count(i0));
2569 lshi(r0, r0, __builtin_ctzl(i0));
2570 } else if (jit_mips2_p() && is_middle_mask(~i0)) {
2573 insr(r0, _ZERO_REGNO, __builtin_ctzl(~i0), masked_bits_count(~i0));
2575 reg = jit_get_reg(jit_class_gpr);
2577 AND(r0, r1, rn(reg));
2583 _ori(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_word_t i0)
2586 if (can_zero_extend_short_p(i0))
2589 reg = jit_get_reg(jit_class_gpr);
2591 OR(r0, r1, rn(reg));
2597 _xori(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_word_t i0)
2600 if (can_zero_extend_short_p(i0))
2603 reg = jit_get_reg(jit_class_gpr);
2605 XOR(r0, r1, rn(reg));
2611 _movr(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1)
2614 orr(r0, r1, _ZERO_REGNO);
2618 _movi(jit_state_t *_jit, jit_int32_t r0, jit_word_t i0)
2621 OR(r0, _ZERO_REGNO, _ZERO_REGNO);
2622 else if (can_sign_extend_short_p(i0))
2623 addiu(r0, _ZERO_REGNO, i0);
2624 else if (can_zero_extend_short_p(i0))
2625 ORI(r0, _ZERO_REGNO, i0);
2627 /* Check if loading some constant reachable address */
2628 if (jit_mips6_p()) {
2630 w = i0 - (_jit->pc.w + (_jitc->inst.pend ? 4 : 0));
2634 if (can_sign_extend_i19_p(d)) {
2640 if (can_sign_extend_int_p(w)) {
2641 jit_int32_t lo = (jit_int32_t)w << 16 >> 16;
2642 jit_int32_t hi = w - lo;
2643 AUIPC(r0, hi >> 16);
2649 if (can_sign_extend_int_p(i0))
2651 else if (can_zero_extend_int_p(i0)) {
2652 if (i0 & 0xffff0000) {
2653 ORI(r0, _ZERO_REGNO, i0 >> 16);
2657 # if __WORDSIZE == 64
2659 movi(r0, (jit_uword_t)i0 >> 32);
2660 if (i0 & 0xffff0000) {
2662 ORI(r0, r0, i0 >> 16);
2676 _movi_p(jit_state_t *_jit, jit_int32_t r0, jit_word_t i0)
2681 # if __WORDSIZE == 32
2686 ORI(r0, r0, i0 >> 32);
2688 ORI(r0, r0, i0 >> 16);
2697 _movnr(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_int32_t r2)
2700 if (jit_mips6_p()) {
2701 reg = jit_get_reg(jit_class_gpr);
2702 SELNEZ(rn(reg), r1, r2);
2704 OR(r0, r0, rn(reg));
2712 _movzr(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_int32_t r2)
2715 if (jit_mips6_p()) {
2716 reg = jit_get_reg(jit_class_gpr);
2717 SELEQZ(rn(reg), r1, r2);
2719 OR(r0, r0, rn(reg));
2727 _casx(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1,
2728 jit_int32_t r2, jit_int32_t r3, jit_word_t i0)
2730 jit_int32_t r1_reg, iscasi;
2731 jit_word_t retry, done, jump0, jump1;
2732 if ((iscasi = (r1 == _NOREG))) {
2733 r1_reg = jit_get_reg(jit_class_gpr);
2741 # if __WORDSIZE == 32
2742 if (jit_mips6_p()) LL_R6(r0, 0, r1);
2745 if (jit_mips6_p()) LLD_R6(r0, 0, r1);
2746 else LLD(r0, 0, r1);
2750 BNE(r0, r2, 1); /* bne done r0 r2 */
2751 movi(r0, 0); /* set to 0 in delay slot */
2753 movr(r0, r3); /* after jump and delay slot */
2754 /* store new value */
2755 # if __WORDSIZE == 32
2756 if (jit_mips6_p()) SC_R6(r0, 0, r1);
2759 if (jit_mips6_p()) SCD_R6(r0, 0, r1);
2760 else SCD(r0, 0, r1);
2764 BEQ(r0, _ZERO_REGNO, 0); /* beqi retry r0 0 */
2765 movi(r0, 1); /* set to 1 in delay slot */
2771 patch_at(jump0, done);
2772 patch_at(jump1, retry);
2774 jit_unget_reg(r1_reg);
2778 _ldi_c(jit_state_t *_jit, jit_int32_t r0, jit_word_t i0)
2781 if (can_sign_extend_short_p(i0))
2782 LB(r0, i0, _ZERO_REGNO);
2784 reg = jit_get_reg(jit_class_gpr);
2792 _ldi_uc(jit_state_t *_jit, jit_int32_t r0, jit_word_t i0)
2795 if (can_sign_extend_short_p(i0))
2796 LBU(r0, i0, _ZERO_REGNO);
2798 reg = jit_get_reg(jit_class_gpr);
2800 ldr_uc(r0, rn(reg));
2806 _ldi_s(jit_state_t *_jit, jit_int32_t r0, jit_word_t i0)
2809 if (can_sign_extend_short_p(i0))
2810 LH(r0, i0, _ZERO_REGNO);
2812 reg = jit_get_reg(jit_class_gpr);
2820 _ldi_us(jit_state_t *_jit, jit_int32_t r0, jit_word_t i0)
2823 if (can_sign_extend_short_p(i0))
2824 LHU(r0, i0, _ZERO_REGNO);
2826 reg = jit_get_reg(jit_class_gpr);
2828 ldr_us(r0, rn(reg));
2834 _ldi_i(jit_state_t *_jit, jit_int32_t r0, jit_word_t i0)
2838 if (jit_mips6_p()) {
2841 w = (i0 - (_jit->pc.w + (_jitc->inst.pend ? 4 : 0))) >> 2;
2842 if (can_sign_extend_i19_p(w)) {
2848 if (can_sign_extend_short_p(i0))
2849 LW(r0, i0, _ZERO_REGNO);
2851 reg = jit_get_reg(jit_class_gpr);
2861 #if __WORDSIZE == 64
2863 _ldi_ui(jit_state_t *_jit, jit_int32_t r0, jit_word_t i0)
2867 if (jit_mips6_p()) {
2870 w = (i0 - (_jit->pc.w + (_jitc->inst.pend ? 4 : 0))) >> 2;
2871 if (can_sign_extend_i19_p(w)) {
2877 if (can_sign_extend_short_p(i0))
2878 LWU(r0, i0, _ZERO_REGNO);
2880 reg = jit_get_reg(jit_class_gpr);
2882 ldr_ui(r0, rn(reg));
2891 _ldi_l(jit_state_t *_jit, jit_int32_t r0, jit_word_t i0)
2895 if (jit_mips6_p()) {
2897 w = (i0 - (_jit->pc.w + (_jitc->inst.pend ? 4 : 0))) >> 3;
2898 if (can_sign_extend_i18_p(w)) {
2903 if (can_sign_extend_short_p(i0))
2904 LD(r0, i0, _ZERO_REGNO);
2906 reg = jit_get_reg(jit_class_gpr);
2916 _ldxr_c(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1 ,jit_int32_t r2)
2923 _ldxi_c(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_word_t i0)
2925 if (can_sign_extend_short_p(i0))
2934 _ldxr_uc(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1 ,jit_int32_t r2)
2941 _ldxi_uc(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_word_t i0)
2943 if (can_sign_extend_short_p(i0))
2952 _ldxr_s(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1 ,jit_int32_t r2)
2959 _ldxi_s(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_word_t i0)
2961 if (can_sign_extend_short_p(i0))
2970 _ldxr_us(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1 ,jit_int32_t r2)
2977 _ldxi_us(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_word_t i0)
2979 if (can_sign_extend_short_p(i0))
2988 _ldxr_i(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1 ,jit_int32_t r2)
2995 _ldxi_i(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_word_t i0)
2997 if (can_sign_extend_short_p(i0))
3005 #if __WORDSIZE == 64
3007 _ldxr_ui(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1 ,jit_int32_t r2)
3014 _ldxi_ui(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_word_t i0)
3016 if (can_sign_extend_short_p(i0))
3025 _ldxr_l(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1 ,jit_int32_t r2)
3032 _ldxi_l(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_word_t i0)
3034 if (can_sign_extend_short_p(i0))
3043 #if __WORDSIZE == 32
3044 # define LOAD_LEFT LWL
3045 # define LOAD_RIGHT LWR
3047 # define LOAD_LEFT LDL
3048 # define LOAD_RIGHT LDR
3051 _unldr(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_word_t i0)
3054 if (jit_unaligned_p()) {
3055 assert(i0 >= 1 && i0 <= sizeof(jit_word_t));
3060 t0 = jit_get_reg(jit_class_gpr);
3066 #if __BYTE_ORDER == __LITTLE_ENDIAN
3067 LOAD_LEFT(r0, sizeof(jit_word_t) - 1, r2);
3068 LOAD_RIGHT(r0, 0, r2);
3070 LOAD_LEFT(r0, 0, r2);
3071 LOAD_RIGHT(r0, sizeof(jit_word_t) - 1, r2);
3077 #if __BYTE_ORDER == __LITTLE_ENDIAN
3080 rshi(r0, r0, __WORDSIZE - 16);
3084 #if __BYTE_ORDER == __LITTLE_ENDIAN
3085 lshi(r0, r0, __WORDSIZE - 24);
3087 rshi(r0, r0, __WORDSIZE - 24);
3089 #if __WORDSIZE == 32
3093 # if __BYTE_ORDER == __LITTLE_ENDIAN
3096 rshi(r0, r0, __WORDSIZE - 32);
3100 #if __WORDSIZE == 64
3102 # if __BYTE_ORDER == __LITTLE_ENDIAN
3103 lshi(r0, r0, __WORDSIZE - 40);
3105 rshi(r0, r0, __WORDSIZE - 40);
3108 # if __BYTE_ORDER == __LITTLE_ENDIAN
3109 lshi(r0, r0, __WORDSIZE - 48);
3111 rshi(r0, r0, __WORDSIZE - 48);
3114 # if __BYTE_ORDER == __LITTLE_ENDIAN
3115 lshi(r0, r0, __WORDSIZE - 56);
3117 rshi(r0, r0, __WORDSIZE - 56);
3126 generic_unldr(r0, r1, i0);
3130 _unldi(jit_state_t *_jit, jit_int32_t r0, jit_word_t i0, jit_word_t i1)
3133 if (jit_unaligned_p()) {
3134 t0 = jit_get_reg(jit_class_gpr);
3136 unldr(r0, rn(t0), i1);
3140 generic_unldi(r0, i0, i1);
3144 _unldr_u(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_word_t i0)
3147 if (jit_unaligned_p()) {
3148 assert(i0 >= 1 && i0 <= sizeof(jit_word_t));
3153 t0 = jit_get_reg(jit_class_gpr);
3159 #if __BYTE_ORDER == __LITTLE_ENDIAN
3160 LOAD_LEFT(r0, sizeof(jit_word_t) - 1, r2);
3161 LOAD_RIGHT(r0, 0, r2);
3163 LOAD_LEFT(r0, 0, r2);
3164 LOAD_RIGHT(r0, sizeof(jit_word_t) - 1, r2);
3170 #if __BYTE_ORDER == __LITTLE_ENDIAN
3173 rshi_u(r0, r0, __WORDSIZE - 16);
3177 #if __BYTE_ORDER == __LITTLE_ENDIAN
3178 lshi(r0, r0, __WORDSIZE - 24);
3180 rshi_u(r0, r0, __WORDSIZE - 24);
3182 #if __WORDSIZE == 32
3186 # if __BYTE_ORDER == __LITTLE_ENDIAN
3189 rshi_u(r0, r0, __WORDSIZE - 32);
3193 #if __WORDSIZE == 64
3195 # if __BYTE_ORDER == __LITTLE_ENDIAN
3196 lshi(r0, r0, __WORDSIZE - 40);
3198 rshi_u(r0, r0, __WORDSIZE - 40);
3201 # if __BYTE_ORDER == __LITTLE_ENDIAN
3202 lshi(r0, r0, __WORDSIZE - 48);
3204 rshi_u(r0, r0, __WORDSIZE - 48);
3207 # if __BYTE_ORDER == __LITTLE_ENDIAN
3208 lshi(r0, r0, __WORDSIZE - 56);
3210 rshi_u(r0, r0, __WORDSIZE - 56);
3219 generic_unldr_u(r0, r1, i0);
3225 _unldi_u(jit_state_t *_jit, jit_int32_t r0, jit_word_t i0, jit_word_t i1)
3228 if (jit_unaligned_p()) {
3229 t0 = jit_get_reg(jit_class_gpr);
3231 unldr_u(r0, rn(t0), i1);
3235 generic_unldi_u(r0, i0, i1);
3239 _sti_c(jit_state_t *_jit, jit_word_t i0, jit_int32_t r0)
3242 if (can_sign_extend_short_p(i0))
3243 SB(r0, i0, _ZERO_REGNO);
3245 reg = jit_get_reg(jit_class_gpr);
3253 _sti_s(jit_state_t *_jit, jit_word_t i0, jit_int32_t r0)
3256 if (can_sign_extend_short_p(i0))
3257 SH(r0, i0, _ZERO_REGNO);
3259 reg = jit_get_reg(jit_class_gpr);
3267 _sti_i(jit_state_t *_jit, jit_word_t i0, jit_int32_t r0)
3270 if (can_sign_extend_short_p(i0))
3271 SW(r0, i0, _ZERO_REGNO);
3273 reg = jit_get_reg(jit_class_gpr);
3280 #if __WORDSIZE == 64
3282 _sti_l(jit_state_t *_jit, jit_word_t i0, jit_int32_t r0)
3285 if (can_sign_extend_short_p(i0))
3286 SD(r0, i0, _ZERO_REGNO);
3288 reg = jit_get_reg(jit_class_gpr);
3297 _stxr_c(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_int32_t r2)
3300 reg = jit_get_reg(jit_class_gpr);
3301 addr(rn(reg), r0, r1);
3307 _stxi_c(jit_state_t *_jit, jit_word_t i0, jit_int32_t r0, jit_int32_t r1)
3310 if (can_sign_extend_short_p(i0))
3313 reg = jit_get_reg(jit_class_gpr);
3314 addi(rn(reg), r0, i0);
3321 _stxr_s(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1 ,jit_int32_t r2)
3324 reg = jit_get_reg(jit_class_gpr);
3325 addr(rn(reg), r0, r1);
3331 _stxi_s(jit_state_t *_jit, jit_word_t i0, jit_int32_t r0, jit_int32_t r1)
3334 if (can_sign_extend_short_p(i0))
3337 reg = jit_get_reg(jit_class_gpr);
3338 addi(rn(reg), r0, i0);
3345 _stxr_i(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1 ,jit_int32_t r2)
3348 reg = jit_get_reg(jit_class_gpr);
3349 addr(rn(reg), r0, r1);
3355 _stxi_i(jit_state_t *_jit, jit_word_t i0, jit_int32_t r0, jit_int32_t r1)
3358 if (can_sign_extend_short_p(i0))
3361 reg = jit_get_reg(jit_class_gpr);
3362 addi(rn(reg), r0, i0);
3368 #if __WORDSIZE == 64
3370 _stxr_l(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1 ,jit_int32_t r2)
3373 reg = jit_get_reg(jit_class_gpr);
3374 addr(rn(reg), r0, r1);
3380 _stxi_l(jit_state_t *_jit, jit_word_t i0, jit_int32_t r0, jit_int32_t r1)
3383 if (can_sign_extend_short_p(i0))
3386 reg = jit_get_reg(jit_class_gpr);
3387 addi(rn(reg), r0, i0);
3395 _unstr(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_word_t i0)
3397 assert(i0 > 0 && i0 <= sizeof(jit_word_t));
3398 if (jit_unaligned_p()) {
3401 #if __BYTE_ORDER == __LITTLE_ENDIAN
3409 #if __WORDSIZE == 64
3411 # if __BYTE_ORDER == __LITTLE_ENDIAN
3421 /* FIXME Cost of loading memory contents, creating masks,
3422 * and'ing, and or'ing values to use SW* or SD* might
3423 * larger than using fallback. */
3424 /* FIXME Probably not, and would be without branches. */
3425 fallback_unstr(r0, r1, i0);
3430 generic_unstr(r0, r1, i0);
3434 _unsti(jit_state_t *_jit, jit_word_t i0, jit_int32_t r0, jit_word_t i1)
3437 if (jit_unaligned_p()) {
3438 if (i1 == 4 || i1 == 8) {
3439 reg = jit_get_reg(jit_class_gpr);
3441 unstr(rn(reg), r0, i1);
3445 fallback_unsti(i0, r0, i1);
3448 generic_unsti(i0, r0, i1);
3452 _bswapr_us(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1)
3454 if (jit_mips2_p()) {
3458 generic_bswapr_us(_jit, r0, r1);
3463 _bswapr_ui(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1)
3465 if (jit_mips2_p()) {
3466 if (__WORDSIZE == 64) {
3470 mips_extr(r0, r0, 0, 32);
3476 generic_bswapr_ui(_jit, r0, r1);
3480 #if __WORDSIZE == 64
3482 _bswapr_ul(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1)
3484 if (jit_mips2_p()) {
3489 generic_bswapr_ul(_jit, r0, r1);
3494 _extr_u(jit_state_t *_jit,
3495 jit_int32_t r0, jit_int32_t r1, jit_word_t i0, jit_word_t i1)
3497 assert(i0 >= 0 && i1 >= 1 && i0 + i1 <= __WORDSIZE);
3498 if (jit_mips2_p()) {
3499 if (i1 == __WORDSIZE)
3502 # if __BYTE_ORDER == __BIG_ENDIAN
3503 i0 = __WORDSIZE - (i0 + i1);
3505 #if __WORDSIZE == 32
3506 EXT(r0, r1, i0, i1);
3508 if (i0 < 32 && i1 <= 32)
3509 DEXT(r0, r1, i0, i1);
3510 else if (i0 < 32 && i1 > 32)
3511 DEXTM(r0, r1, i0, i1);
3513 assert(i0 >= 32 && i1 <= 32);
3514 DEXTU(r0, r1, i0, i1);
3520 fallback_ext_u(r0, r1, i0, i1);
3524 _depr(jit_state_t *_jit,
3525 jit_int32_t r0, jit_int32_t r1, jit_word_t i0, jit_word_t i1)
3527 assert(i0 >= 0 && i1 >= 1 && i0 + i1 <= __WORDSIZE);
3528 if (jit_mips2_p()) {
3529 if (i1 == __WORDSIZE)
3532 # if __BYTE_ORDER == __BIG_ENDIAN
3533 i0 = __WORDSIZE - (i0 + i1);
3535 #if __WORDSIZE == 32
3536 INS(r0, r1, i0, i1);
3538 if (i0 < 32 && i1 <= 32 && (i0 + i1) <= 32)
3539 DINS(r0, r1, i0, i1);
3540 else if (i0 < 32 && i1 >= 2 && (i0 + i1) > 32)
3541 DINSM(r0, r1, i0, i1);
3543 assert(i0 >= 32 && i1 >= 1 && i1 <= 32 && (i0 + i1) > 32);
3544 DINSU(r0, r1, i0, i1);
3550 fallback_dep(r0, r1, i0, i1);
3554 _extr_c(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1)
3559 lshi(r0, r1, __WORDSIZE - 8);
3560 rshi(r0, r0, __WORDSIZE - 8);
3565 _extr_s(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1)
3570 lshi(r0, r1, __WORDSIZE - 16);
3571 rshi(r0, r0, __WORDSIZE - 16);
3575 # if __WORDSIZE == 64
3577 _extr_ui(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1)
3580 DEXT(r0, r1, 0, 32);
3589 _lti(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_word_t i0)
3593 if (can_sign_extend_short_p(i0))
3596 reg = jit_get_reg(jit_class_gpr);
3598 ltr(r0, r1, rn(reg));
3604 _lti_u(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_word_t i0)
3608 if (can_sign_extend_short_p(i0))
3611 reg = jit_get_reg(jit_class_gpr);
3613 ltr_u(r0, r1, rn(reg));
3619 _ler(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_int32_t r2)
3626 _lei(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_word_t i0)
3630 if (can_sign_extend_short_p(i0 + 1))
3631 SLTI(r0, r1, i0 + 1);
3633 reg = jit_get_reg(jit_class_gpr);
3635 ler(r0, r1, rn(reg));
3641 _ler_u(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_int32_t r2)
3648 _lei_u(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_word_t i0)
3652 if (can_sign_extend_short_p(i0 + 1))
3653 SLTIU(r0, r1, i0 + 1);
3655 reg = jit_get_reg(jit_class_gpr);
3657 ler_u(r0, r1, rn(reg));
3663 _eqr(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_int32_t r2)
3670 _eqi(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_word_t i0)
3681 _ger(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_int32_t r2)
3688 _gei(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_word_t i0)
3692 if (can_sign_extend_short_p(i0)) {
3696 reg = jit_get_reg(jit_class_gpr);
3698 ger(r0, r1, rn(reg));
3704 _ger_u(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_int32_t r2)
3711 _gei_u(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_word_t i0)
3715 if (can_sign_extend_short_p(i0)) {
3719 reg = jit_get_reg(jit_class_gpr);
3721 ger_u(r0, r1, rn(reg));
3727 _gti(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_word_t i0)
3732 SLT(r0, _ZERO_REGNO, r1);
3734 reg = jit_get_reg(jit_class_gpr);
3736 SLT(r0, rn(reg), r1);
3742 _gti_u(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_word_t i0)
3747 SLTU(r0, _ZERO_REGNO, r1);
3749 reg = jit_get_reg(jit_class_gpr);
3751 SLTU(r0, rn(reg), r1);
3757 _ner(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_int32_t r2)
3760 SLTU(r0, _ZERO_REGNO, r0);
3764 _nei(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_word_t i0)
3768 SLTU(r0, _ZERO_REGNO, r0);
3771 SLTU(r0, _ZERO_REGNO, r1);
3775 _beqr(jit_state_t *_jit, jit_word_t i0, jit_int32_t r0, jit_int32_t r1)
3778 jit_int32_t op, reg;
3779 /* Just to not move incorrectly instruction to delay slot */
3780 reg = jit_get_reg_for_delay_slot(jit_class_gpr|jit_class_chk, r0, r1);
3782 /* implicit flush() */
3784 BEQ(r0, r1, ((i0 - w) >> 2) - 1);
3786 if (reg != JIT_NOREG)
3792 _beqi(jit_state_t *_jit, jit_word_t i0, jit_int32_t r0, jit_word_t i1)
3795 jit_int32_t op, reg;
3797 w = beqr(i0, r0, _ZERO_REGNO);
3799 reg = jit_get_reg_for_delay_slot(jit_class_gpr, r0, _ZERO_REGNO);
3804 BEQ(r0, rn(reg), ((i0 - w) >> 2) - 1);
3812 _bger(jit_state_t *_jit, jit_word_t i0, jit_int32_t r0, jit_int32_t r1,
3816 jit_int32_t op, reg;
3817 reg = jit_get_reg_for_delay_slot(jit_class_gpr, r0, r1);
3820 SLTU(rn(reg), r0, r1);
3822 SLT(rn(reg), r0, r1);
3825 BEQ(rn(reg), _ZERO_REGNO, ((i0 - w) >> 2) - 1);
3832 _bgei(jit_state_t *_jit, jit_word_t i0, jit_int32_t r0, jit_word_t i1,
3833 jit_bool_t sltiu, jit_bool_t bne)
3838 jit_int32_t op, t0, mask;
3839 zero_p = !sltiu && i1 == 0;
3840 /* Even if zero_p allocate one as a mean to avoid incorrect delay slot */
3841 mask = jit_class_gpr;
3843 mask |= jit_class_chk;
3844 t0 = jit_get_reg_for_delay_slot(mask, r0, _ZERO_REGNO);
3845 if (can_sign_extend_short_p(i1)) {
3849 SLTIU(rn(t0), r0, i1);
3851 SLTI(rn(t0), r0, i1);
3855 d = ((i0 - w) >> 2) - 1;
3858 BNE(rn(t0), _ZERO_REGNO, d);
3864 BEQ(rn(t0), _ZERO_REGNO, d);
3873 SLTU(rn(t0), r0, rn(t0));
3875 SLT(rn(t0), r0, rn(t0));
3879 BNE(rn(t0), _ZERO_REGNO, ((i0 - w) >> 2) - 1);
3881 BEQ(rn(t0), _ZERO_REGNO, ((i0 - w) >> 2) - 1);
3884 if (t0 != JIT_NOREG)
3890 _bgtr(jit_state_t *_jit, jit_word_t i0, jit_int32_t r0, jit_int32_t r1,
3891 jit_bool_t sltu, jit_bool_t inv)
3894 jit_int32_t op, reg;
3895 reg = jit_get_reg_for_delay_slot(jit_class_gpr, r0, r1);
3898 SLTU(rn(reg), r1, r0);
3900 SLT(rn(reg), r1, r0);
3904 BEQ(rn(reg), _ZERO_REGNO, ((i0 - w) >> 2) - 1);
3906 BNE(rn(reg), _ZERO_REGNO, ((i0 - w) >> 2) - 1);
3913 _bgti(jit_state_t *_jit, jit_word_t i0, jit_int32_t r0, jit_word_t i1,
3914 jit_bool_t sltiu, jit_bool_t inv)
3917 jit_int32_t op, t0, mask;
3918 mask = jit_class_gpr;
3920 mask |= jit_class_chk;
3921 /* Allocate even if i0 == 0 as a way to avoid incorrect delay slot */
3922 t0 = jit_get_reg_for_delay_slot(mask, r0, _ZERO_REGNO);
3925 /* implicit flush() */
3929 BEQ(r0, _ZERO_REGNO, ((i0 - w) >> 2) - 1);
3931 BLEZ(r0, ((i0 - w) >> 2) - 1);
3935 BNE(r0, _ZERO_REGNO, ((i0 - w) >> 2) - 1);
3937 BGTZ(r0, ((i0 - w) >> 2) - 1);
3944 SLTU(rn(t0), rn(t0), r0);
3946 SLT(rn(t0), rn(t0), r0);
3950 BEQ(rn(t0), _ZERO_REGNO, ((i0 - w) >> 2) - 1);
3952 BNE(rn(t0), _ZERO_REGNO, ((i0 - w) >> 2) - 1);
3955 if (t0 != JIT_NOREG)
3961 _bner(jit_state_t *_jit, jit_word_t i0, jit_int32_t r0, jit_int32_t r1)
3964 jit_int32_t op, reg;
3965 /* Just to not move incorrectly instruction to delay slot */
3966 reg = jit_get_reg_for_delay_slot(jit_class_gpr|jit_class_chk, r0, r1);
3968 /* implicit flush() */
3970 BNE(r0, r1, ((i0 - w) >> 2) - 1);
3972 if (reg != JIT_NOREG)
3978 _bnei(jit_state_t *_jit, jit_word_t i0, jit_int32_t r0, jit_word_t i1)
3981 jit_int32_t op, reg;
3983 w = bner(i0, r0, _ZERO_REGNO);
3985 reg = jit_get_reg_for_delay_slot(jit_class_gpr, r0, _ZERO_REGNO);
3990 BNE(r0, rn(reg), ((i0 - w) >> 2) - 1);
3998 _jmpr(jit_state_t *_jit, jit_int32_t r0)
4001 /* make sure delay slot does not use r0 */
4002 t0 = jit_get_reg_for_delay_slot(jit_class_gpr|jit_class_chk,
4007 if (t0 != JIT_NOREG)
4012 _jmpi(jit_state_t *_jit, jit_word_t i0, jit_bool_t patch)
4017 if (jit_mips6_p() && !(i0 & 3)) {
4018 disp = ((i0 - (_jit->pc.w + (_jitc->inst.pend ? 4 : 0))) >> 2) - 1;
4019 if (patch || can_sign_extend_i26_p(disp)) {
4022 /* Compact branch instructions do not have a delay slot */
4024 goto done_without_delay;
4028 /* try to get a pending instruction before the jump */
4029 t0 = jit_get_reg_for_delay_slot(jit_class_gpr, _ZERO_REGNO, _ZERO_REGNO);
4031 /* implicit flush() */
4033 if (jit_mips2_p()) {
4034 disp = ((i0 - w) >> 2) - 1;
4035 if (patch || can_sign_extend_short_p(disp)) {
4036 BEQ(_ZERO_REGNO, _ZERO_REGNO, disp);
4040 if (((w + sizeof(jit_int32_t)) & 0xf0000000) == (i0 & 0xf0000000))
4041 J((i0 & ~0xf0000000) >> 2);
4044 w = movi_p(rn(t0), i0);
4059 _jmpi_p(jit_state_t *_jit, jit_word_t i0)
4063 /* Get a register without side effects in delay slot */
4064 t0 = jit_get_reg_for_delay_slot(jit_class_gpr, _ZERO_REGNO, _ZERO_REGNO);
4065 /* Check for a instruction that can be executed in the delay slot */
4067 /* implicit flush() */
4070 flush(); /* movi_p will be patched */
4078 _boaddr(jit_state_t *_jit, jit_word_t i0, jit_int32_t r0, jit_int32_t r1)
4085 /* t1 = r0 + r1; overflow = r1 < 0 ? r0 < t1 : t1 < r0 */
4086 t0 = jit_get_reg(jit_class_gpr|jit_class_nospill);
4087 t1 = jit_get_reg(jit_class_gpr|jit_class_nospill);
4088 t2 = jit_get_reg(jit_class_gpr|jit_class_nospill);
4089 SLT(rn(t0), r1, _ZERO_REGNO); /* t0 = r1 < 0 */
4090 addr(rn(t1), r0, r1); /* t1 = r0 + r1 */
4091 SLT(rn(t2), rn(t1), r0); /* t2 = t1 < r0 */
4092 SLT(rn(t1), r0, rn(t1)); /* t1 = r0 < t1 */
4093 movzr(rn(t1), rn(t2), rn(t0)); /* if (r0 == 0) t1 = t2 */
4094 /* cannot optimize delay slot */
4097 BNE(rn(t1), _ZERO_REGNO, ((i0 - w) >> 2) - 1);
4109 _boaddi(jit_state_t *_jit, jit_word_t i0, jit_int32_t r0, jit_word_t i1)
4116 if (can_sign_extend_short_p(i1)) {
4117 t0 = jit_get_reg(jit_class_gpr|jit_class_nospill);
4118 t1 = jit_get_reg(jit_class_gpr|jit_class_nospill);
4119 t2 = jit_get_reg(jit_class_gpr|jit_class_nospill);
4120 SLTI(rn(t0), _ZERO_REGNO, i1);
4121 addiu(rn(t1), r0, i1);
4122 SLT(rn(t2), r0, rn(t1));
4123 SLT(rn(t1), rn(t1), r0);
4124 movzr(rn(t1), rn(t2), rn(t0));
4125 /* cannot optimize delay slot */
4128 BNE(rn(t1), _ZERO_REGNO, ((i0 - w) >> 2) - 1);
4137 t0 = jit_get_reg(jit_class_gpr);
4139 w = boaddr(i0, r0, rn(t0));
4146 _boaddr_u(jit_state_t *_jit, jit_word_t i0, jit_int32_t r0, jit_int32_t r1)
4152 t0 = jit_get_reg(jit_class_gpr|jit_class_nospill);
4153 t1 = jit_get_reg(jit_class_gpr|jit_class_nospill);
4154 addr(rn(t0), r0, r1);
4155 SLTU(rn(t1), rn(t0), r0);
4157 /* cannot optimize delay slot */
4159 BNE(_ZERO_REGNO, rn(t1), ((i0 - w) >> 2) - 1);
4169 _boaddi_u(jit_state_t *_jit, jit_word_t i0, jit_int32_t r0, jit_word_t i1)
4175 if (can_sign_extend_short_p(i0)) {
4176 t0 = jit_get_reg(jit_class_gpr|jit_class_nospill);
4177 t1 = jit_get_reg(jit_class_gpr|jit_class_nospill);
4178 addiu(rn(t0), r0, i1);
4179 SLTU(rn(t1), rn(t0), r0);
4181 /* cannot optimize delay slot */
4183 BNE(_ZERO_REGNO, rn(t1), ((i0 - w) >> 2) - 1);
4191 t0 = jit_get_reg(jit_class_gpr|jit_class_nospill);
4193 w = boaddr_u(i0, r0, rn(t0));
4200 _bxaddr(jit_state_t *_jit, jit_word_t i0, jit_int32_t r0, jit_int32_t r1)
4207 /* t1 = r0 + r1; overflow = r1 < 0 ? r0 < t1 : t1 < r0 */
4208 t0 = jit_get_reg(jit_class_gpr|jit_class_nospill);
4209 t1 = jit_get_reg(jit_class_gpr|jit_class_nospill);
4210 t2 = jit_get_reg(jit_class_gpr|jit_class_nospill);
4211 SLT(rn(t0), r1, _ZERO_REGNO); /* t0 = r1 < 0 */
4212 addr(rn(t1), r0, r1); /* t1 = r0 + r1 */
4213 SLT(rn(t2), rn(t1), r0); /* t2 = t1 < r0 */
4214 SLT(rn(t1), r0, rn(t1)); /* t1 = r0 < t1 */
4215 movzr(rn(t1), rn(t2), rn(t0)); /* if (r0 == 0) t1 = t2 */
4216 /* cannot optimize delay slot */
4219 BEQ(rn(t1), _ZERO_REGNO, ((i0 - w) >> 2) - 1);
4231 _bxaddi(jit_state_t *_jit, jit_word_t i0, jit_int32_t r0, jit_word_t i1)
4238 if (can_sign_extend_short_p(i1)) {
4239 t0 = jit_get_reg(jit_class_gpr|jit_class_nospill);
4240 t1 = jit_get_reg(jit_class_gpr|jit_class_nospill);
4241 t2 = jit_get_reg(jit_class_gpr|jit_class_nospill);
4242 SLTI(rn(t0), _ZERO_REGNO, i1);
4243 addiu(rn(t1), r0, i1);
4244 SLT(rn(t2), r0, rn(t1));
4245 SLT(rn(t1), rn(t1), r0);
4246 movzr(rn(t1), rn(t2), rn(t0));
4247 /* cannot optimize delay slot */
4250 BEQ(rn(t1), _ZERO_REGNO, ((i0 - w) >> 2) - 1);
4259 t0 = jit_get_reg(jit_class_gpr|jit_class_nospill);
4261 w = bxaddr(i0, r0, rn(t0));
4268 _bxaddr_u(jit_state_t *_jit, jit_word_t i0, jit_int32_t r0, jit_int32_t r1)
4274 t0 = jit_get_reg(jit_class_gpr|jit_class_nospill);
4275 t1 = jit_get_reg(jit_class_gpr|jit_class_nospill);
4276 addr(rn(t0), r0, r1);
4277 SLTU(rn(t1), rn(t0), r0);
4278 /* cannot optimize delay slot */
4281 BEQ(_ZERO_REGNO, rn(t1), ((i0 - w) >> 2) - 1);
4291 _bxaddi_u(jit_state_t *_jit, jit_word_t i0, jit_int32_t r0, jit_word_t i1)
4297 if (can_sign_extend_short_p(i0)) {
4298 t0 = jit_get_reg(jit_class_gpr|jit_class_nospill);
4299 t1 = jit_get_reg(jit_class_gpr|jit_class_nospill);
4300 addiu(rn(t0), r0, i1);
4301 SLTU(rn(t1), rn(t0), r0);
4302 /* cannot optimize delay slot */
4305 BEQ(_ZERO_REGNO, rn(t1), ((i0 - w) >> 2) - 1);
4313 t0 = jit_get_reg(jit_class_gpr|jit_class_nospill);
4315 w = bxaddr_u(i0, r0, rn(t0));
4322 _bosubr(jit_state_t *_jit, jit_word_t i0, jit_int32_t r0, jit_int32_t r1)
4329 /* t1 = r0 - r1; overflow = 0 < r1 ? r0 < t1 : t1 < r0 */
4330 t0 = jit_get_reg(jit_class_gpr|jit_class_nospill);
4331 t1 = jit_get_reg(jit_class_gpr|jit_class_nospill);
4332 t2 = jit_get_reg(jit_class_gpr|jit_class_nospill);
4333 SLT(rn(t0), _ZERO_REGNO, r1); /* t0 = 0 < r1 */
4334 subr(rn(t1), r0, r1); /* t1 = r0 - r1 */
4335 SLT(rn(t2), rn(t1), r0); /* t2 = t1 < r0 */
4336 SLT(rn(t1), r0, rn(t1)); /* t1 = r0 < t1 */
4337 movzr(rn(t1), rn(t2), rn(t0)); /* if (r0 == 0) t1 = t2 */
4340 BNE(rn(t1), _ZERO_REGNO, ((i0 - w) >> 2) - 1);
4352 _bosubi(jit_state_t *_jit, jit_word_t i0, jit_int32_t r0, jit_word_t i1)
4359 if (can_sign_extend_short_p(i1) && (i1 & 0xffff) != 0x8000) {
4360 t0 = jit_get_reg(jit_class_gpr|jit_class_nospill);
4361 t1 = jit_get_reg(jit_class_gpr|jit_class_nospill);
4362 t2 = jit_get_reg(jit_class_gpr|jit_class_nospill);
4363 SLTI(rn(t0), _ZERO_REGNO, i1);
4364 addiu(rn(t1), r0, -i1);
4365 SLT(rn(t2), rn(t1), r0);
4366 SLT(rn(t1), r0, rn(t1));
4367 movzr(rn(t1), rn(t2), rn(t0));
4370 BNE(rn(t1), _ZERO_REGNO, ((i0 - w) >> 2) - 1);
4379 t0 = jit_get_reg(jit_class_gpr|jit_class_nospill);
4381 w = bosubr(i0, r0, rn(t0));
4388 _bosubr_u(jit_state_t *_jit, jit_word_t i0, jit_int32_t r0, jit_int32_t r1)
4394 t0 = jit_get_reg(jit_class_gpr|jit_class_nospill);
4395 t1 = jit_get_reg(jit_class_gpr|jit_class_nospill);
4396 subr(rn(t0), r0, r1);
4397 SLTU(rn(t1), r0, rn(t0));
4398 /* cannot optimize delay slot */
4401 BNE(_ZERO_REGNO, rn(t1), ((i0 - w) >> 2) - 1);
4411 _bosubi_u(jit_state_t *_jit, jit_word_t i0, jit_int32_t r0, jit_word_t i1)
4417 if (can_sign_extend_short_p(i0) && (i0 & 0xffff) != 0x8000) {
4418 t0 = jit_get_reg(jit_class_gpr|jit_class_nospill);
4419 t1 = jit_get_reg(jit_class_gpr|jit_class_nospill);
4420 addiu(rn(t0), r0, -i1);
4421 SLTU(rn(t1), r0, rn(t0));
4422 /* cannot optimize delay slot */
4425 BNE(_ZERO_REGNO, rn(t1), ((i0 - w) >> 2) - 1);
4433 t0 = jit_get_reg(jit_class_gpr|jit_class_nospill);
4435 w = bosubr_u(i0, r0, rn(t0));
4442 _bxsubr(jit_state_t *_jit, jit_word_t i0, jit_int32_t r0, jit_int32_t r1)
4449 /* t1 = r0 - r1; overflow = 0 < r1 ? r0 < t1 : t1 < r0 */
4450 t0 = jit_get_reg(jit_class_gpr|jit_class_nospill);
4451 t1 = jit_get_reg(jit_class_gpr|jit_class_nospill);
4452 t2 = jit_get_reg(jit_class_gpr|jit_class_nospill);
4453 SLT(rn(t0), _ZERO_REGNO, r1); /* t0 = 0 < r1 */
4454 subr(rn(t1), r0, r1); /* t1 = r0 - r1 */
4455 SLT(rn(t2), rn(t1), r0); /* t2 = t1 < r0 */
4456 SLT(rn(t1), r0, rn(t1)); /* t1 = r0 < t1 */
4457 movzr(rn(t1), rn(t2), rn(t0)); /* if (t0 == 0) t1 = t2 */
4458 /* cannot optimize delay slot */
4461 BEQ(rn(t1), _ZERO_REGNO, ((i0 - w) >> 2) - 1);
4473 _bxsubi(jit_state_t *_jit, jit_word_t i0, jit_int32_t r0, jit_word_t i1)
4480 if (can_sign_extend_short_p(i1) && (i1 & 0xffff) != 0x8000) {
4481 t0 = jit_get_reg(jit_class_gpr|jit_class_nospill);
4482 t1 = jit_get_reg(jit_class_gpr|jit_class_nospill);
4483 t2 = jit_get_reg(jit_class_gpr|jit_class_nospill);
4484 SLTI(rn(t0), _ZERO_REGNO, i1);
4485 addiu(rn(t1), r0, -i1);
4486 SLT(rn(t2), rn(t1), r0);
4487 SLT(rn(t1), r0, rn(t1));
4488 movzr(rn(t1), rn(t2), rn(t0));
4489 /* cannot optimize delay slot */
4492 BEQ(rn(t1), _ZERO_REGNO, ((i0 - w) >> 2) - 1);
4501 t0 = jit_get_reg(jit_class_gpr|jit_class_nospill);
4503 w = bxsubr(i0, r0, rn(t0));
4510 _bxsubr_u(jit_state_t *_jit, jit_word_t i0, jit_int32_t r0, jit_int32_t r1)
4516 t0 = jit_get_reg(jit_class_gpr|jit_class_nospill);
4517 t1 = jit_get_reg(jit_class_gpr|jit_class_nospill);
4518 subr(rn(t0), r0, r1);
4519 SLTU(rn(t1), r0, rn(t0));
4520 /* cannot optimize delay slot */
4523 BEQ(_ZERO_REGNO, rn(t1), ((i0 - w) >> 2) - 1);
4533 _bxsubi_u(jit_state_t *_jit, jit_word_t i0, jit_int32_t r0, jit_word_t i1)
4539 if (can_sign_extend_short_p(i0) && (i0 & 0xffff) != 0x8000) {
4540 t0 = jit_get_reg(jit_class_gpr|jit_class_nospill);
4541 t1 = jit_get_reg(jit_class_gpr|jit_class_nospill);
4542 addiu(rn(t0), r0, -i1);
4543 SLTU(rn(t1), r0, rn(t0));
4544 /* cannot optimize delay slot */
4547 BEQ(_ZERO_REGNO, rn(t1), ((i0 - w) >> 2) - 1);
4555 t0 = jit_get_reg(jit_class_gpr|jit_class_nospill);
4557 w = bxsubr_u(i0, r0, rn(t0));
4564 _bmsr(jit_state_t *_jit, jit_word_t i0, jit_int32_t r0, jit_int32_t r1)
4568 t0 = jit_get_reg_for_delay_slot(jit_class_gpr, r0, r1);
4570 AND(rn(t0), r0, r1);
4573 BNE(_ZERO_REGNO, rn(t0), ((i0 - w) >> 2) - 1);
4580 _bmsi(jit_state_t *_jit, jit_word_t i0, jit_int32_t r0, jit_word_t i1)
4584 t0 = jit_get_reg_for_delay_slot(jit_class_gpr, r0, _ZERO_REGNO);
4586 andi(rn(t0), r0, i1);
4589 BNE(_ZERO_REGNO, rn(t0), ((i0 - w) >> 2) - 1);
4596 _bmcr(jit_state_t *_jit, jit_word_t i0, jit_int32_t r0, jit_int32_t r1)
4600 t0 = jit_get_reg_for_delay_slot(jit_class_gpr, r0, r1);
4602 AND(rn(t0), r0, r1);
4605 BEQ(_ZERO_REGNO, rn(t0), ((i0 - w) >> 2) - 1);
4612 _bmci(jit_state_t *_jit, jit_word_t i0, jit_int32_t r0, jit_word_t i1)
4616 t0 = jit_get_reg_for_delay_slot(jit_class_gpr, r0, _ZERO_REGNO);
4618 andi(rn(t0), r0, i1);
4621 BEQ(_ZERO_REGNO, rn(t0), ((i0 - w) >> 2) - 1);
4628 _callr(jit_state_t *_jit, jit_int32_t r0)
4631 if (r0 != _T9_REGNO) {
4634 movr(_T9_REGNO, r0);
4638 /* make sure delay slot does not use r0 */
4639 t0 = jit_get_reg_for_delay_slot(jit_class_gpr|jit_class_chk,
4644 if (t0 != JIT_NOREG)
4650 _calli(jit_state_t *_jit, jit_word_t i0, jit_bool_t patch)
4656 if (jit_mips6_p() && !(i0 & 3)) {
4657 disp = ((i0 - (w + (_jitc->inst.pend ? 4 : 0))) >> 2) - 1;
4658 if (patch || can_sign_extend_i26_p(disp)) {
4661 /* Compact branch instructions do not have a delay slot */
4667 if (jit_mips2_p()) {
4668 disp = ((i0 - (w + _jitc->inst.pend ? 4 : 0)) >> 2) - 1;
4669 if (patch || can_sign_extend_short_p(disp)) {
4671 BGEZAL(_ZERO_REGNO, disp); /* Renamed to BAL in mips release 6 */
4678 if (((w + sizeof(jit_int32_t)) & 0xf0000000) == (i0 & 0xf0000000)) {
4679 if (can_sign_extend_short_p(i0)) {
4680 JAL((i0 & ~0xf0000000) >> 2);
4682 addiu(_T9_REGNO, _ZERO_REGNO, i0);
4684 else if (can_zero_extend_short_p(i0)) {
4685 JAL((i0 & ~0xf0000000) >> 2);
4687 ORI(_T9_REGNO, _ZERO_REGNO, i0);
4689 else if (can_sign_extend_int_p(i0)) {
4691 LUI(_T9_REGNO, i0 >> 16);
4692 JAL((i0 & ~0xf0000000) >> 2);
4694 ORI(_T9_REGNO, _T9_REGNO, i0);
4697 JAL((i0 & ~0xf0000000) >> 2);
4699 LUI(_T9_REGNO, i0 >> 16);
4707 /* make sure delay slot does not use _T9_REGNO */
4708 t0 = jit_get_reg_for_delay_slot(jit_class_gpr|jit_class_chk,
4709 _T9_REGNO, _ZERO_REGNO);
4710 /* try to get an instruction before the call */
4712 movi(_T9_REGNO, i0);
4715 if (t0 != JIT_NOREG)
4723 _calli_p(jit_state_t *_jit, jit_word_t i0)
4727 /* make sure delay slot does not use _T9_REGNO */
4728 t0 = jit_get_reg_for_delay_slot(jit_class_gpr|jit_class_chk,
4729 _T9_REGNO, _ZERO_REGNO);
4731 /* implicit flush() */
4733 movi_p(_T9_REGNO, i0);
4736 if (t0 != JIT_NOREG)
4742 _prolog(jit_state_t *_jit, jit_node_t *node)
4744 jit_int32_t reg, offs;
4745 if (_jitc->function->define_frame || _jitc->function->assume_frame) {
4746 jit_int32_t frame = -_jitc->function->frame;
4748 assert(_jitc->function->self.aoff >= frame);
4749 if (_jitc->function->assume_frame)
4751 _jitc->function->self.aoff = frame;
4753 if (_jitc->function->allocar)
4754 _jitc->function->self.aoff &= -8;
4756 _jitc->function->stack = ((_jitc->function->self.alen -
4757 /* align stack at 16 bytes */
4758 _jitc->function->self.aoff) + 15) & -16;
4760 _jitc->function->stack = ((/* first 16 bytes must be allocated */
4761 (_jitc->function->self.alen > 16 ?
4762 _jitc->function->self.alen : 16) -
4763 /* align stack at 8 bytes */
4764 _jitc->function->self.aoff) + 7) & -8;
4768 if (_jitc->function->stack)
4769 _jitc->function->need_stack = 1;
4770 if (!_jitc->function->need_frame && !_jitc->function->need_stack) {
4771 /* check if any callee save register needs to be saved */
4772 for (reg = 0; reg < _jitc->reglen; ++reg)
4773 if (jit_regset_tstbit(&_jitc->function->regset, reg) &&
4774 (_rvs[reg].spec & jit_class_sav)) {
4775 _jitc->function->need_stack = 1;
4780 /* Need always a frame due to the need to always allocate 16 bytes */
4784 if (_jitc->function->need_frame || _jitc->function->need_stack)
4785 subi(_SP_REGNO, _SP_REGNO, jit_framesize());
4786 if (_jitc->function->need_frame) {
4787 stxi(0, _SP_REGNO, _RA_REGNO);
4788 stxi(STACK_SLOT, _SP_REGNO, _BP_REGNO);
4790 /* callee save registers */
4791 for (reg = 0, offs = STACK_SLOT << 1; reg < jit_size(iregs); reg++) {
4792 if (jit_regset_tstbit(&_jitc->function->regset, iregs[reg])) {
4793 stxi(offs, _SP_REGNO, rn(iregs[reg]));
4797 for (reg = 0; reg < jit_size(fregs); reg++) {
4798 if (jit_regset_tstbit(&_jitc->function->regset, fregs[reg])) {
4799 stxi_d(offs, _SP_REGNO, rn(fregs[reg]));
4800 offs += sizeof(jit_float64_t);
4804 if (_jitc->function->need_frame)
4805 movr(_BP_REGNO, _SP_REGNO);
4808 if (_jitc->function->stack)
4809 subi(_SP_REGNO, _SP_REGNO, _jitc->function->stack);
4810 if (_jitc->function->allocar) {
4811 reg = jit_get_reg(jit_class_gpr);
4812 movi(rn(reg), _jitc->function->self.aoff);
4813 stxi_i(_jitc->function->aoffoff, _BP_REGNO, rn(reg));
4817 if (_jitc->function->self.call & jit_call_varargs) {
4818 for (reg = _jitc->function->vagp; jit_arg_reg_p(reg); ++reg) {
4819 offs = jit_framesize() - ((NUM_WORD_ARGS - reg) * STACK_SLOT);
4821 SD(rn(_A0 - reg), offs, _BP_REGNO);
4823 offs += 16 + WORD_ADJUST;
4824 stxi(offs, _BP_REGNO, rn(_A0 - reg));
4831 _epilog(jit_state_t *_jit, jit_node_t *node)
4833 jit_int32_t reg, offs;
4834 if (_jitc->function->assume_frame)
4837 if (_jitc->function->need_frame) {
4838 movr(_SP_REGNO, _BP_REGNO);
4839 ldxi(_RA_REGNO, _SP_REGNO, 0);
4840 ldxi(_BP_REGNO, _SP_REGNO, STACK_SLOT);
4843 /* callee save registers */
4844 for (reg = 0, offs = STACK_SLOT << 1; reg < jit_size(iregs); reg++) {
4845 if (jit_regset_tstbit(&_jitc->function->regset, iregs[reg])) {
4846 ldxi(rn(iregs[reg]), _SP_REGNO, offs);
4847 offs += sizeof(jit_word_t);
4850 for (reg = 0; reg < jit_size(fregs); reg++) {
4851 if (jit_regset_tstbit(&_jitc->function->regset, fregs[reg])) {
4852 ldxi_d(rn(fregs[reg]), _SP_REGNO, offs);
4853 offs += sizeof(jit_float64_t);
4858 if (_jitc->function->need_frame || _jitc->function->need_stack)
4859 addi(_SP_REGNO, _SP_REGNO, jit_framesize());
4866 _vastart(jit_state_t *_jit, jit_int32_t r0)
4868 assert(_jitc->function->self.call & jit_call_varargs);
4870 /* Initialize va_list to the first stack argument. */
4871 if (jit_arg_reg_p(_jitc->function->vagp))
4874 ((NUM_WORD_ARGS - _jitc->function->vagp) * STACK_SLOT));
4877 addi(r0, _BP_REGNO, jit_selfsize());
4881 _vaarg(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1)
4883 /* Load argument. */
4885 ldxi(r0, r1, WORD_ADJUST);
4890 /* Update va_list. */
4891 addi(r1, r1, STACK_SLOT);
4895 _patch_abs(jit_state_t *_jit, jit_word_t instr, jit_word_t label)
4904 #if __WORDSIZE == 32
4906 assert(i.hc.b == MIPS_LUI);
4907 i.is.b = label >> 16;
4910 assert(i.hc.b == MIPS_ORI);
4915 assert(i.hc.b == MIPS_LUI);
4916 i.is.b = label >> 48;
4919 assert(i.hc.b == MIPS_ORI);
4920 i.is.b = label >> 32;
4924 assert(i.hc.b == MIPS_ORI);
4925 i.is.b = label >> 16;
4929 assert(i.hc.b == MIPS_ORI);
4936 _patch_at(jit_state_t *_jit, jit_word_t instr, jit_word_t label)
4947 /* 16 bit immediate opcodes */
4950 case MIPS_BLTZ: case MIPS_BLTZL:
4951 case MIPS_BLTZAL: case MIPS_BLTZALL:
4952 case MIPS_BGEZ: case MIPS_BGEZAL:
4953 case MIPS_BGEZALL: case MIPS_BGEZL:
4954 case MIPS_TEQI: case MIPS_TGEI:
4955 case MIPS_TGEIU: case MIPS_TLTI:
4956 case MIPS_TLTIU: case MIPS_TNEI:
4957 i.is.b = ((label - instr) >> 2) - 1;
4961 assert(!"unhandled branch opcode");
4966 case MIPS_COP1: case MIPS_COP2:
4967 if (jit_mips6_p()) {
4969 case MIPS_BC1EQZ: case MIPS_BC1NEZ:
4970 assert(jit_mips6_p());
4971 i.is.b = ((label - instr) >> 2) - 1;
4975 assert(!"unhandled branch opcode");
4980 assert(i.rs.b == MIPS_BC);
4982 case MIPS_BCF: case MIPS_BCFL:
4983 case MIPS_BCT: case MIPS_BCTL:
4984 assert(!jit_mips6_p());
4985 i.is.b = ((label - instr) >> 2) - 1;
4989 assert(!"unhandled branch opcode");
4995 case MIPS_BLEZ: case MIPS_BLEZL:
4996 case MIPS_BEQ: case MIPS_BEQL:
4997 case MIPS_BGTZ: case MIPS_BGTZL:
4998 case MIPS_BNE: case MIPS_BNEL:
4999 i.is.b = ((label - instr) >> 2) - 1;
5004 patch_abs(instr, label);
5007 case MIPS_J: case MIPS_JAL:
5009 assert(((instr + sizeof(jit_int32_t)) & 0xf0000000) ==
5010 (label & 0xf0000000));
5011 i.ii.b = (label & ~0xf0000000) >> 2;
5015 case MIPS_BALC: case MIPS_BC_R6:
5016 assert(jit_mips6_p());
5017 i.ii.b = ((label - instr) >> 2) - 1;
5022 assert(!"unhandled branch opcode");