1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
3 * Copyright (C) 2009-2011 Ari64 *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
22 #include <stdint.h> //include for uint64_t
26 #include "emu_if.h" //emulator interface
29 //#define assem_debug printf
30 //#define inv_debug printf
31 #define assem_debug(...)
32 #define inv_debug(...)
35 #include "assem_x86.h"
38 #include "assem_x64.h"
41 #include "assem_arm.h"
45 #define MAX_OUTPUT_BLOCK_SIZE 262144
47 int cycle_multiplier; // 100 for 1.0
48 #define CLOCK_ADJUST(x) (((x) * cycle_multiplier + 50) / 100)
52 signed char regmap_entry[HOST_REGS];
53 signed char regmap[HOST_REGS];
62 u_int loadedconst; // host regs that have constants loaded
63 u_int waswritten; // MIPS regs that were used as store base before
64 uint64_t constmap[HOST_REGS];
72 struct ll_entry *next;
78 char insn[MAXBLOCK][10];
79 u_char itype[MAXBLOCK];
80 u_char opcode[MAXBLOCK];
81 u_char opcode2[MAXBLOCK];
89 u_char dep1[MAXBLOCK];
90 u_char dep2[MAXBLOCK];
92 static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
93 static uint64_t gte_rt[MAXBLOCK];
94 static uint64_t gte_unneeded[MAXBLOCK];
95 static u_int smrv[32]; // speculated MIPS register values
96 static u_int smrv_strong; // mask or regs that are likely to have correct values
97 static u_int smrv_weak; // same, but somewhat less likely
98 static u_int smrv_strong_next; // same, but after current insn executes
99 static u_int smrv_weak_next;
102 char likely[MAXBLOCK];
103 char is_ds[MAXBLOCK];
105 uint64_t unneeded_reg[MAXBLOCK];
106 uint64_t unneeded_reg_upper[MAXBLOCK];
107 uint64_t branch_unneeded_reg[MAXBLOCK];
108 uint64_t branch_unneeded_reg_upper[MAXBLOCK];
109 uint64_t p32[MAXBLOCK];
110 uint64_t pr32[MAXBLOCK];
111 signed char regmap_pre[MAXBLOCK][HOST_REGS];
112 signed char regmap[MAXBLOCK][HOST_REGS];
113 signed char regmap_entry[MAXBLOCK][HOST_REGS];
114 uint64_t constmap[MAXBLOCK][HOST_REGS];
115 struct regstat regs[MAXBLOCK];
116 struct regstat branch_regs[MAXBLOCK];
117 signed char minimum_free_regs[MAXBLOCK];
118 u_int needed_reg[MAXBLOCK];
119 uint64_t requires_32bit[MAXBLOCK];
120 u_int wont_dirty[MAXBLOCK];
121 u_int will_dirty[MAXBLOCK];
124 u_int instr_addr[MAXBLOCK];
125 u_int link_addr[MAXBLOCK][3];
127 u_int stubs[MAXBLOCK*3][8];
129 u_int literals[1024][2];
134 struct ll_entry *jump_in[4096];
135 struct ll_entry *jump_out[4096];
136 struct ll_entry *jump_dirty[4096];
137 u_int hash_table[65536][4] __attribute__((aligned(16)));
138 char shadow[1048576] __attribute__((aligned(16)));
144 static const u_int using_tlb=0;
146 int new_dynarec_did_compile;
147 int new_dynarec_hacks;
148 u_int stop_after_jal;
149 extern u_char restore_candidate[512];
150 extern int cycle_count;
152 /* registers that may be allocated */
154 #define HIREG 32 // hi
155 #define LOREG 33 // lo
156 #define FSREG 34 // FPU status (FCSR)
157 #define CSREG 35 // Coprocessor status
158 #define CCREG 36 // Cycle count
159 #define INVCP 37 // Pointer to invalid_code
160 #define MMREG 38 // Pointer to memory_map
161 #define ROREG 39 // ram offset (if rdram!=0x80000000)
163 #define FTEMP 40 // FPU temporary register
164 #define PTEMP 41 // Prefetch temporary register
165 #define TLREG 42 // TLB mapping offset
166 #define RHASH 43 // Return address hash
167 #define RHTBL 44 // Return address hash table address
168 #define RTEMP 45 // JR/JALR address register
170 #define AGEN1 46 // Address generation temporary register
171 #define AGEN2 47 // Address generation temporary register
172 #define MGEN1 48 // Maptable address generation temporary register
173 #define MGEN2 49 // Maptable address generation temporary register
174 #define BTREG 50 // Branch target temporary register
176 /* instruction types */
177 #define NOP 0 // No operation
178 #define LOAD 1 // Load
179 #define STORE 2 // Store
180 #define LOADLR 3 // Unaligned load
181 #define STORELR 4 // Unaligned store
182 #define MOV 5 // Move
183 #define ALU 6 // Arithmetic/logic
184 #define MULTDIV 7 // Multiply/divide
185 #define SHIFT 8 // Shift by register
186 #define SHIFTIMM 9// Shift by immediate
187 #define IMM16 10 // 16-bit immediate
188 #define RJUMP 11 // Unconditional jump to register
189 #define UJUMP 12 // Unconditional jump
190 #define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
191 #define SJUMP 14 // Conditional branch (regimm format)
192 #define COP0 15 // Coprocessor 0
193 #define COP1 16 // Coprocessor 1
194 #define C1LS 17 // Coprocessor 1 load/store
195 #define FJUMP 18 // Conditional branch (floating point)
196 #define FLOAT 19 // Floating point unit
197 #define FCONV 20 // Convert integer to float
198 #define FCOMP 21 // Floating point compare (sets FSREG)
199 #define SYSCALL 22// SYSCALL
200 #define OTHER 23 // Other
201 #define SPAN 24 // Branch/delay slot spans 2 pages
202 #define NI 25 // Not implemented
203 #define HLECALL 26// PCSX fake opcodes for HLE
204 #define COP2 27 // Coprocessor 2 move
205 #define C2LS 28 // Coprocessor 2 load/store
206 #define C2OP 29 // Coprocessor 2 operation
207 #define INTCALL 30// Call interpreter to handle rare corner cases
216 #define LOADBU_STUB 7
217 #define LOADHU_STUB 8
218 #define STOREB_STUB 9
219 #define STOREH_STUB 10
220 #define STOREW_STUB 11
221 #define STORED_STUB 12
222 #define STORELR_STUB 13
223 #define INVCODE_STUB 14
231 int new_recompile_block(int addr);
232 void *get_addr_ht(u_int vaddr);
233 void invalidate_block(u_int block);
234 void invalidate_addr(u_int addr);
235 void remove_hash(int vaddr);
238 void dyna_linker_ds();
240 void verify_code_vm();
241 void verify_code_ds();
244 void fp_exception_ds();
246 void jump_syscall_hle();
250 void new_dyna_leave();
255 void read_nomem_new();
256 void read_nomemb_new();
257 void read_nomemh_new();
258 void read_nomemd_new();
259 void write_nomem_new();
260 void write_nomemb_new();
261 void write_nomemh_new();
262 void write_nomemd_new();
263 void write_rdram_new();
264 void write_rdramb_new();
265 void write_rdramh_new();
266 void write_rdramd_new();
267 extern u_int memory_map[1048576];
269 // Needed by assembler
270 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
271 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
272 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
273 void load_all_regs(signed char i_regmap[]);
274 void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
275 void load_regs_entry(int t);
276 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
280 //#define DEBUG_CYCLE_COUNT 1
282 static void tlb_hacks()
286 if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
290 switch (ROM_HEADER->Country_code&0xFF)
302 // Unknown country code
306 u_int rom_addr=(u_int)rom;
308 // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
309 // in the lower 4G of memory to use this hack. Copy it if necessary.
310 if((void *)rom>(void *)0xffffffff) {
311 munmap(ROM_COPY, 67108864);
312 if(mmap(ROM_COPY, 12582912,
313 PROT_READ | PROT_WRITE,
314 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
315 -1, 0) <= 0) {printf("mmap() failed\n");}
316 memcpy(ROM_COPY,rom,12582912);
317 rom_addr=(u_int)ROM_COPY;
321 for(n=0x7F000;n<0x80000;n++) {
322 memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
329 static u_int get_page(u_int vaddr)
332 u_int page=(vaddr^0x80000000)>>12;
334 u_int page=vaddr&~0xe0000000;
335 if (page < 0x1000000)
336 page &= ~0x0e00000; // RAM mirrors
340 if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
342 if(page>2048) page=2048+(page&2047);
346 static u_int get_vpage(u_int vaddr)
348 u_int vpage=(vaddr^0x80000000)>>12;
350 if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
352 if(vpage>2048) vpage=2048+(vpage&2047);
356 // Get address from virtual address
357 // This is called from the recompiled JR/JALR instructions
358 void *get_addr(u_int vaddr)
360 u_int page=get_page(vaddr);
361 u_int vpage=get_vpage(vaddr);
362 struct ll_entry *head;
363 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
366 if(head->vaddr==vaddr&&head->reg32==0) {
367 //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
368 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
371 ht_bin[1]=(int)head->addr;
377 head=jump_dirty[vpage];
379 if(head->vaddr==vaddr&&head->reg32==0) {
380 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
381 // Don't restore blocks which are about to expire from the cache
382 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
383 if(verify_dirty(head->addr)) {
384 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
385 invalid_code[vaddr>>12]=0;
386 inv_code_start=inv_code_end=~0;
388 memory_map[vaddr>>12]|=0x40000000;
392 if(tlb_LUT_r[vaddr>>12]) {
393 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
394 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
397 restore_candidate[vpage>>3]|=1<<(vpage&7);
399 else restore_candidate[page>>3]|=1<<(page&7);
400 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
401 if(ht_bin[0]==vaddr) {
402 ht_bin[1]=(int)head->addr; // Replace existing entry
408 ht_bin[1]=(int)head->addr;
416 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
417 int r=new_recompile_block(vaddr);
418 if(r==0) return get_addr(vaddr);
419 // Execute in unmapped page, generate pagefault execption
421 Cause=(vaddr<<31)|0x8;
422 EPC=(vaddr&1)?vaddr-5:vaddr;
424 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
425 EntryHi=BadVAddr&0xFFFFE000;
426 return get_addr_ht(0x80000000);
428 // Look up address in hash table first
429 void *get_addr_ht(u_int vaddr)
431 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
432 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
433 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
434 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
435 return get_addr(vaddr);
438 void *get_addr_32(u_int vaddr,u_int flags)
441 return get_addr(vaddr);
443 //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
444 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
445 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
446 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
447 u_int page=get_page(vaddr);
448 u_int vpage=get_vpage(vaddr);
449 struct ll_entry *head;
452 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
453 //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
455 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
457 ht_bin[1]=(int)head->addr;
459 }else if(ht_bin[2]==-1) {
460 ht_bin[3]=(int)head->addr;
463 //ht_bin[3]=ht_bin[1];
464 //ht_bin[2]=ht_bin[0];
465 //ht_bin[1]=(int)head->addr;
472 head=jump_dirty[vpage];
474 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
475 //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
476 // Don't restore blocks which are about to expire from the cache
477 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
478 if(verify_dirty(head->addr)) {
479 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
480 invalid_code[vaddr>>12]=0;
481 inv_code_start=inv_code_end=~0;
482 memory_map[vaddr>>12]|=0x40000000;
485 if(tlb_LUT_r[vaddr>>12]) {
486 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
487 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
490 restore_candidate[vpage>>3]|=1<<(vpage&7);
492 else restore_candidate[page>>3]|=1<<(page&7);
494 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
496 ht_bin[1]=(int)head->addr;
498 }else if(ht_bin[2]==-1) {
499 ht_bin[3]=(int)head->addr;
502 //ht_bin[3]=ht_bin[1];
503 //ht_bin[2]=ht_bin[0];
504 //ht_bin[1]=(int)head->addr;
512 //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
513 int r=new_recompile_block(vaddr);
514 if(r==0) return get_addr(vaddr);
515 // Execute in unmapped page, generate pagefault execption
517 Cause=(vaddr<<31)|0x8;
518 EPC=(vaddr&1)?vaddr-5:vaddr;
520 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
521 EntryHi=BadVAddr&0xFFFFE000;
522 return get_addr_ht(0x80000000);
526 void clear_all_regs(signed char regmap[])
529 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
532 signed char get_reg(signed char regmap[],int r)
535 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map[hr]==r) return hr;
539 // Find a register that is available for two consecutive cycles
540 signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
543 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map1[hr]==r&®map2[hr]==r) return hr;
547 int count_free_regs(signed char regmap[])
551 for(hr=0;hr<HOST_REGS;hr++)
553 if(hr!=EXCLUDE_REG) {
554 if(regmap[hr]<0) count++;
560 void dirty_reg(struct regstat *cur,signed char reg)
564 for (hr=0;hr<HOST_REGS;hr++) {
565 if((cur->regmap[hr]&63)==reg) {
571 // If we dirty the lower half of a 64 bit register which is now being
572 // sign-extended, we need to dump the upper half.
573 // Note: Do this only after completion of the instruction, because
574 // some instructions may need to read the full 64-bit value even if
575 // overwriting it (eg SLTI, DSRA32).
576 static void flush_dirty_uppers(struct regstat *cur)
579 for (hr=0;hr<HOST_REGS;hr++) {
580 if((cur->dirty>>hr)&1) {
583 if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
588 void set_const(struct regstat *cur,signed char reg,uint64_t value)
592 for (hr=0;hr<HOST_REGS;hr++) {
593 if(cur->regmap[hr]==reg) {
595 cur->constmap[hr]=value;
597 else if((cur->regmap[hr]^64)==reg) {
599 cur->constmap[hr]=value>>32;
604 void clear_const(struct regstat *cur,signed char reg)
608 for (hr=0;hr<HOST_REGS;hr++) {
609 if((cur->regmap[hr]&63)==reg) {
610 cur->isconst&=~(1<<hr);
615 int is_const(struct regstat *cur,signed char reg)
620 for (hr=0;hr<HOST_REGS;hr++) {
621 if((cur->regmap[hr]&63)==reg) {
622 return (cur->isconst>>hr)&1;
627 uint64_t get_const(struct regstat *cur,signed char reg)
631 for (hr=0;hr<HOST_REGS;hr++) {
632 if(cur->regmap[hr]==reg) {
633 return cur->constmap[hr];
636 printf("Unknown constant in r%d\n",reg);
640 // Least soon needed registers
641 // Look at the next ten instructions and see which registers
642 // will be used. Try not to reallocate these.
643 void lsn(u_char hsn[], int i, int *preferred_reg)
653 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
655 // Don't go past an unconditonal jump
662 if(rs1[i+j]) hsn[rs1[i+j]]=j;
663 if(rs2[i+j]) hsn[rs2[i+j]]=j;
664 if(rt1[i+j]) hsn[rt1[i+j]]=j;
665 if(rt2[i+j]) hsn[rt2[i+j]]=j;
666 if(itype[i+j]==STORE || itype[i+j]==STORELR) {
667 // Stores can allocate zero
671 // On some architectures stores need invc_ptr
672 #if defined(HOST_IMM8)
673 if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
677 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
685 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
687 // Follow first branch
688 int t=(ba[i+b]-start)>>2;
689 j=7-b;if(t+j>=slen) j=slen-t-1;
692 if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
693 if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
694 //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
695 //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
698 // TODO: preferred register based on backward branch
700 // Delay slot should preferably not overwrite branch conditions or cycle count
701 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
702 if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
703 if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
709 // Coprocessor load/store needs FTEMP, even if not declared
710 if(itype[i]==C1LS||itype[i]==C2LS) {
713 // Load L/R also uses FTEMP as a temporary register
714 if(itype[i]==LOADLR) {
717 // Also SWL/SWR/SDL/SDR
718 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
721 // Don't remove the TLB registers either
722 if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
725 // Don't remove the miniht registers
726 if(itype[i]==UJUMP||itype[i]==RJUMP)
733 // We only want to allocate registers if we're going to use them again soon
734 int needed_again(int r, int i)
740 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
742 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
743 return 0; // Don't need any registers if exiting the block
751 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
753 // Don't go past an unconditonal jump
757 if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
764 if(rs1[i+j]==r) rn=j;
765 if(rs2[i+j]==r) rn=j;
766 if((unneeded_reg[i+j]>>r)&1) rn=10;
767 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
775 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
777 // Follow first branch
779 int t=(ba[i+b]-start)>>2;
780 j=7-b;if(t+j>=slen) j=slen-t-1;
783 if(!((unneeded_reg[t+j]>>r)&1)) {
784 if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
785 if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
795 // Try to match register allocations at the end of a loop with those
797 int loop_reg(int i, int r, int hr)
806 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
808 // Don't go past an unconditonal jump
815 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
820 if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
821 if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
822 if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
824 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
826 int t=(ba[i+k]-start)>>2;
827 int reg=get_reg(regs[t].regmap_entry,r);
828 if(reg>=0) return reg;
829 //reg=get_reg(regs[t+1].regmap_entry,r);
830 //if(reg>=0) return reg;
838 // Allocate every register, preserving source/target regs
839 void alloc_all(struct regstat *cur,int i)
843 for(hr=0;hr<HOST_REGS;hr++) {
844 if(hr!=EXCLUDE_REG) {
845 if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
846 ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
849 cur->dirty&=~(1<<hr);
852 if((cur->regmap[hr]&63)==0)
855 cur->dirty&=~(1<<hr);
862 void div64(int64_t dividend,int64_t divisor)
866 //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
867 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
869 void divu64(uint64_t dividend,uint64_t divisor)
873 //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
874 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
877 void mult64(uint64_t m1,uint64_t m2)
879 unsigned long long int op1, op2, op3, op4;
880 unsigned long long int result1, result2, result3, result4;
881 unsigned long long int temp1, temp2, temp3, temp4;
897 op1 = op2 & 0xFFFFFFFF;
898 op2 = (op2 >> 32) & 0xFFFFFFFF;
899 op3 = op4 & 0xFFFFFFFF;
900 op4 = (op4 >> 32) & 0xFFFFFFFF;
903 temp2 = (temp1 >> 32) + op1 * op4;
905 temp4 = (temp3 >> 32) + op2 * op4;
907 result1 = temp1 & 0xFFFFFFFF;
908 result2 = temp2 + (temp3 & 0xFFFFFFFF);
909 result3 = (result2 >> 32) + temp4;
910 result4 = (result3 >> 32);
912 lo = result1 | (result2 << 32);
913 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
922 void multu64(uint64_t m1,uint64_t m2)
924 unsigned long long int op1, op2, op3, op4;
925 unsigned long long int result1, result2, result3, result4;
926 unsigned long long int temp1, temp2, temp3, temp4;
928 op1 = m1 & 0xFFFFFFFF;
929 op2 = (m1 >> 32) & 0xFFFFFFFF;
930 op3 = m2 & 0xFFFFFFFF;
931 op4 = (m2 >> 32) & 0xFFFFFFFF;
934 temp2 = (temp1 >> 32) + op1 * op4;
936 temp4 = (temp3 >> 32) + op2 * op4;
938 result1 = temp1 & 0xFFFFFFFF;
939 result2 = temp2 + (temp3 & 0xFFFFFFFF);
940 result3 = (result2 >> 32) + temp4;
941 result4 = (result3 >> 32);
943 lo = result1 | (result2 << 32);
944 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
946 //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
947 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
950 uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
958 else original=loaded;
961 uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
964 original>>=64-(bits^56);
965 original<<=64-(bits^56);
969 else original=loaded;
975 #include "assem_x86.c"
978 #include "assem_x64.c"
981 #include "assem_arm.c"
984 // Add virtual address mapping to linked list
985 void ll_add(struct ll_entry **head,int vaddr,void *addr)
987 struct ll_entry *new_entry;
988 new_entry=malloc(sizeof(struct ll_entry));
989 assert(new_entry!=NULL);
990 new_entry->vaddr=vaddr;
992 new_entry->addr=addr;
993 new_entry->next=*head;
997 // Add virtual address mapping for 32-bit compiled block
998 void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
1000 ll_add(head,vaddr,addr);
1002 (*head)->reg32=reg32;
1006 // Check if an address is already compiled
1007 // but don't return addresses which are about to expire from the cache
1008 void *check_addr(u_int vaddr)
1010 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
1011 if(ht_bin[0]==vaddr) {
1012 if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1013 if(isclean(ht_bin[1])) return (void *)ht_bin[1];
1015 if(ht_bin[2]==vaddr) {
1016 if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1017 if(isclean(ht_bin[3])) return (void *)ht_bin[3];
1019 u_int page=get_page(vaddr);
1020 struct ll_entry *head;
1023 if(head->vaddr==vaddr&&head->reg32==0) {
1024 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1025 // Update existing entry with current address
1026 if(ht_bin[0]==vaddr) {
1027 ht_bin[1]=(int)head->addr;
1030 if(ht_bin[2]==vaddr) {
1031 ht_bin[3]=(int)head->addr;
1034 // Insert into hash table with low priority.
1035 // Don't evict existing entries, as they are probably
1036 // addresses that are being accessed frequently.
1038 ht_bin[1]=(int)head->addr;
1040 }else if(ht_bin[2]==-1) {
1041 ht_bin[3]=(int)head->addr;
1052 void remove_hash(int vaddr)
1054 //printf("remove hash: %x\n",vaddr);
1055 int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1056 if(ht_bin[2]==vaddr) {
1057 ht_bin[2]=ht_bin[3]=-1;
1059 if(ht_bin[0]==vaddr) {
1060 ht_bin[0]=ht_bin[2];
1061 ht_bin[1]=ht_bin[3];
1062 ht_bin[2]=ht_bin[3]=-1;
1066 void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1068 struct ll_entry *next;
1070 if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1071 ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1073 inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1074 remove_hash((*head)->vaddr);
1081 head=&((*head)->next);
1086 // Remove all entries from linked list
1087 void ll_clear(struct ll_entry **head)
1089 struct ll_entry *cur;
1090 struct ll_entry *next;
1101 // Dereference the pointers and remove if it matches
1102 void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1105 int ptr=get_pointer(head->addr);
1106 inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1107 if(((ptr>>shift)==(addr>>shift)) ||
1108 (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1110 inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1111 u_int host_addr=(u_int)kill_pointer(head->addr);
1113 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1120 // This is called when we write to a compiled block (see do_invstub)
1121 void invalidate_page(u_int page)
1123 struct ll_entry *head;
1124 struct ll_entry *next;
1128 inv_debug("INVALIDATE: %x\n",head->vaddr);
1129 remove_hash(head->vaddr);
1134 head=jump_out[page];
1137 inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
1138 u_int host_addr=(u_int)kill_pointer(head->addr);
1140 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1148 static void invalidate_block_range(u_int block, u_int first, u_int last)
1150 u_int page=get_page(block<<12);
1151 //printf("first=%d last=%d\n",first,last);
1152 invalidate_page(page);
1153 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1154 assert(last<page+5);
1155 // Invalidate the adjacent pages if a block crosses a 4K boundary
1157 invalidate_page(first);
1160 for(first=page+1;first<last;first++) {
1161 invalidate_page(first);
1167 // Don't trap writes
1168 invalid_code[block]=1;
1170 // If there is a valid TLB entry for this page, remove write protect
1171 if(tlb_LUT_w[block]) {
1172 assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1173 // CHECK: Is this right?
1174 memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1175 u_int real_block=tlb_LUT_w[block]>>12;
1176 invalid_code[real_block]=1;
1177 if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1179 else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
1183 memset(mini_ht,-1,sizeof(mini_ht));
1187 void invalidate_block(u_int block)
1189 u_int page=get_page(block<<12);
1190 u_int vpage=get_vpage(block<<12);
1191 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1192 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1195 struct ll_entry *head;
1196 head=jump_dirty[vpage];
1197 //printf("page=%d vpage=%d\n",page,vpage);
1200 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1201 get_bounds((int)head->addr,&start,&end);
1202 //printf("start: %x end: %x\n",start,end);
1203 if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) {
1204 if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1205 if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1206 if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1210 if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1211 if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1212 if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1213 if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1220 invalidate_block_range(block,first,last);
1223 void invalidate_addr(u_int addr)
1227 // this check is done by the caller
1228 //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
1229 u_int page=get_page(addr);
1230 if(page<2048) { // RAM
1231 struct ll_entry *head;
1232 u_int addr_min=~0, addr_max=0;
1233 int mask=RAM_SIZE-1;
1235 inv_code_start=addr&~0xfff;
1236 inv_code_end=addr|0xfff;
1239 // must check previous page too because of spans..
1241 inv_code_start-=0x1000;
1243 for(;pg1<=page;pg1++) {
1244 for(head=jump_dirty[pg1];head!=NULL;head=head->next) {
1246 get_bounds((int)head->addr,&start,&end);
1247 if((start&mask)<=(addr&mask)&&(addr&mask)<(end&mask)) {
1248 if(start<addr_min) addr_min=start;
1249 if(end>addr_max) addr_max=end;
1251 else if(addr<start) {
1252 if(start<inv_code_end)
1253 inv_code_end=start-1;
1256 if(end>inv_code_start)
1262 inv_debug("INV ADDR: %08x hit %08x-%08x\n", addr, addr_min, addr_max);
1263 inv_code_start=inv_code_end=~0;
1264 invalidate_block_range(addr>>12,(addr_min&mask)>>12,(addr_max&mask)>>12);
1268 inv_debug("INV ADDR: %08x miss, inv %08x-%08x, sk %d\n", addr, inv_code_start, inv_code_end, 0);//rhits);
1271 if(page!=0) // FIXME: don't know what's up with page 0 (Klonoa)
1275 invalidate_block(addr>>12);
1278 // This is called when loading a save state.
1279 // Anything could have changed, so invalidate everything.
1280 void invalidate_all_pages()
1283 for(page=0;page<4096;page++)
1284 invalidate_page(page);
1285 for(page=0;page<1048576;page++)
1286 if(!invalid_code[page]) {
1287 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1288 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1291 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1294 memset(mini_ht,-1,sizeof(mini_ht));
1298 for(page=0;page<0x100000;page++) {
1299 if(tlb_LUT_r[page]) {
1300 memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1301 if(!tlb_LUT_w[page]||!invalid_code[page])
1302 memory_map[page]|=0x40000000; // Write protect
1304 else memory_map[page]=-1;
1305 if(page==0x80000) page=0xC0000;
1311 // Add an entry to jump_out after making a link
1312 void add_link(u_int vaddr,void *src)
1314 u_int page=get_page(vaddr);
1315 inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1316 int *ptr=(int *)(src+4);
1317 assert((*ptr&0x0fff0000)==0x059f0000);
1318 ll_add(jump_out+page,vaddr,src);
1319 //int ptr=get_pointer(src);
1320 //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1323 // If a code block was found to be unmodified (bit was set in
1324 // restore_candidate) and it remains unmodified (bit is clear
1325 // in invalid_code) then move the entries for that 4K page from
1326 // the dirty list to the clean list.
1327 void clean_blocks(u_int page)
1329 struct ll_entry *head;
1330 inv_debug("INV: clean_blocks page=%d\n",page);
1331 head=jump_dirty[page];
1333 if(!invalid_code[head->vaddr>>12]) {
1334 // Don't restore blocks which are about to expire from the cache
1335 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1337 if(verify_dirty((int)head->addr)) {
1338 //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1341 get_bounds((int)head->addr,&start,&end);
1342 if(start-(u_int)rdram<RAM_SIZE) {
1343 for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1344 inv|=invalid_code[i];
1348 if((signed int)head->vaddr>=(signed int)0xC0000000) {
1349 u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1350 //printf("addr=%x start=%x end=%x\n",addr,start,end);
1351 if(addr<start||addr>=end) inv=1;
1354 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
1358 void * clean_addr=(void *)get_clean_addr((int)head->addr);
1359 if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1362 if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
1364 inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1365 //printf("page=%x, addr=%x\n",page,head->vaddr);
1366 //assert(head->vaddr>>12==(page|0x80000));
1367 ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1368 int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1370 if(ht_bin[0]==head->vaddr) {
1371 ht_bin[1]=(int)clean_addr; // Replace existing entry
1373 if(ht_bin[2]==head->vaddr) {
1374 ht_bin[3]=(int)clean_addr; // Replace existing entry
1387 void mov_alloc(struct regstat *current,int i)
1389 // Note: Don't need to actually alloc the source registers
1390 if((~current->is32>>rs1[i])&1) {
1391 //alloc_reg64(current,i,rs1[i]);
1392 alloc_reg64(current,i,rt1[i]);
1393 current->is32&=~(1LL<<rt1[i]);
1395 //alloc_reg(current,i,rs1[i]);
1396 alloc_reg(current,i,rt1[i]);
1397 current->is32|=(1LL<<rt1[i]);
1399 clear_const(current,rs1[i]);
1400 clear_const(current,rt1[i]);
1401 dirty_reg(current,rt1[i]);
1404 void shiftimm_alloc(struct regstat *current,int i)
1406 if(opcode2[i]<=0x3) // SLL/SRL/SRA
1409 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1411 alloc_reg(current,i,rt1[i]);
1412 current->is32|=1LL<<rt1[i];
1413 dirty_reg(current,rt1[i]);
1414 if(is_const(current,rs1[i])) {
1415 int v=get_const(current,rs1[i]);
1416 if(opcode2[i]==0x00) set_const(current,rt1[i],v<<imm[i]);
1417 if(opcode2[i]==0x02) set_const(current,rt1[i],(u_int)v>>imm[i]);
1418 if(opcode2[i]==0x03) set_const(current,rt1[i],v>>imm[i]);
1420 else clear_const(current,rt1[i]);
1425 clear_const(current,rs1[i]);
1426 clear_const(current,rt1[i]);
1429 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1432 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1433 alloc_reg64(current,i,rt1[i]);
1434 current->is32&=~(1LL<<rt1[i]);
1435 dirty_reg(current,rt1[i]);
1438 if(opcode2[i]==0x3c) // DSLL32
1441 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1442 alloc_reg64(current,i,rt1[i]);
1443 current->is32&=~(1LL<<rt1[i]);
1444 dirty_reg(current,rt1[i]);
1447 if(opcode2[i]==0x3e) // DSRL32
1450 alloc_reg64(current,i,rs1[i]);
1452 alloc_reg64(current,i,rt1[i]);
1453 current->is32&=~(1LL<<rt1[i]);
1455 alloc_reg(current,i,rt1[i]);
1456 current->is32|=1LL<<rt1[i];
1458 dirty_reg(current,rt1[i]);
1461 if(opcode2[i]==0x3f) // DSRA32
1464 alloc_reg64(current,i,rs1[i]);
1465 alloc_reg(current,i,rt1[i]);
1466 current->is32|=1LL<<rt1[i];
1467 dirty_reg(current,rt1[i]);
1472 void shift_alloc(struct regstat *current,int i)
1475 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1477 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1478 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1479 alloc_reg(current,i,rt1[i]);
1480 if(rt1[i]==rs2[i]) {
1481 alloc_reg_temp(current,i,-1);
1482 minimum_free_regs[i]=1;
1484 current->is32|=1LL<<rt1[i];
1485 } else { // DSLLV/DSRLV/DSRAV
1486 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1487 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1488 alloc_reg64(current,i,rt1[i]);
1489 current->is32&=~(1LL<<rt1[i]);
1490 if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1492 alloc_reg_temp(current,i,-1);
1493 minimum_free_regs[i]=1;
1496 clear_const(current,rs1[i]);
1497 clear_const(current,rs2[i]);
1498 clear_const(current,rt1[i]);
1499 dirty_reg(current,rt1[i]);
1503 void alu_alloc(struct regstat *current,int i)
1505 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1507 if(rs1[i]&&rs2[i]) {
1508 alloc_reg(current,i,rs1[i]);
1509 alloc_reg(current,i,rs2[i]);
1512 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1513 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1515 alloc_reg(current,i,rt1[i]);
1517 current->is32|=1LL<<rt1[i];
1519 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1521 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1523 alloc_reg64(current,i,rs1[i]);
1524 alloc_reg64(current,i,rs2[i]);
1525 alloc_reg(current,i,rt1[i]);
1527 alloc_reg(current,i,rs1[i]);
1528 alloc_reg(current,i,rs2[i]);
1529 alloc_reg(current,i,rt1[i]);
1532 current->is32|=1LL<<rt1[i];
1534 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1536 if(rs1[i]&&rs2[i]) {
1537 alloc_reg(current,i,rs1[i]);
1538 alloc_reg(current,i,rs2[i]);
1542 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1543 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1545 alloc_reg(current,i,rt1[i]);
1546 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1548 if(!((current->uu>>rt1[i])&1)) {
1549 alloc_reg64(current,i,rt1[i]);
1551 if(get_reg(current->regmap,rt1[i]|64)>=0) {
1552 if(rs1[i]&&rs2[i]) {
1553 alloc_reg64(current,i,rs1[i]);
1554 alloc_reg64(current,i,rs2[i]);
1558 // Is is really worth it to keep 64-bit values in registers?
1560 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1561 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1565 current->is32&=~(1LL<<rt1[i]);
1567 current->is32|=1LL<<rt1[i];
1571 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1573 if(rs1[i]&&rs2[i]) {
1574 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1575 alloc_reg64(current,i,rs1[i]);
1576 alloc_reg64(current,i,rs2[i]);
1577 alloc_reg64(current,i,rt1[i]);
1579 alloc_reg(current,i,rs1[i]);
1580 alloc_reg(current,i,rs2[i]);
1581 alloc_reg(current,i,rt1[i]);
1585 alloc_reg(current,i,rt1[i]);
1586 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1587 // DADD used as move, or zeroing
1588 // If we have a 64-bit source, then make the target 64 bits too
1589 if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1590 if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1591 alloc_reg64(current,i,rt1[i]);
1592 } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1593 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1594 alloc_reg64(current,i,rt1[i]);
1596 if(opcode2[i]>=0x2e&&rs2[i]) {
1597 // DSUB used as negation - 64-bit result
1598 // If we have a 32-bit register, extend it to 64 bits
1599 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1600 alloc_reg64(current,i,rt1[i]);
1604 if(rs1[i]&&rs2[i]) {
1605 current->is32&=~(1LL<<rt1[i]);
1607 current->is32&=~(1LL<<rt1[i]);
1608 if((current->is32>>rs1[i])&1)
1609 current->is32|=1LL<<rt1[i];
1611 current->is32&=~(1LL<<rt1[i]);
1612 if((current->is32>>rs2[i])&1)
1613 current->is32|=1LL<<rt1[i];
1615 current->is32|=1LL<<rt1[i];
1619 clear_const(current,rs1[i]);
1620 clear_const(current,rs2[i]);
1621 clear_const(current,rt1[i]);
1622 dirty_reg(current,rt1[i]);
1625 void imm16_alloc(struct regstat *current,int i)
1627 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1629 if(rt1[i]) alloc_reg(current,i,rt1[i]);
1630 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1631 current->is32&=~(1LL<<rt1[i]);
1632 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1633 // TODO: Could preserve the 32-bit flag if the immediate is zero
1634 alloc_reg64(current,i,rt1[i]);
1635 alloc_reg64(current,i,rs1[i]);
1637 clear_const(current,rs1[i]);
1638 clear_const(current,rt1[i]);
1640 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1641 if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1642 current->is32|=1LL<<rt1[i];
1643 clear_const(current,rs1[i]);
1644 clear_const(current,rt1[i]);
1646 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1647 if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1648 if(rs1[i]!=rt1[i]) {
1649 if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1650 alloc_reg64(current,i,rt1[i]);
1651 current->is32&=~(1LL<<rt1[i]);
1654 else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1655 if(is_const(current,rs1[i])) {
1656 int v=get_const(current,rs1[i]);
1657 if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1658 if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1659 if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1661 else clear_const(current,rt1[i]);
1663 else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1664 if(is_const(current,rs1[i])) {
1665 int v=get_const(current,rs1[i]);
1666 set_const(current,rt1[i],v+imm[i]);
1668 else clear_const(current,rt1[i]);
1669 current->is32|=1LL<<rt1[i];
1672 set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1673 current->is32|=1LL<<rt1[i];
1675 dirty_reg(current,rt1[i]);
1678 void load_alloc(struct regstat *current,int i)
1680 clear_const(current,rt1[i]);
1681 //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1682 if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1683 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1684 if(rt1[i]&&!((current->u>>rt1[i])&1)) {
1685 alloc_reg(current,i,rt1[i]);
1686 assert(get_reg(current->regmap,rt1[i])>=0);
1687 if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1689 current->is32&=~(1LL<<rt1[i]);
1690 alloc_reg64(current,i,rt1[i]);
1692 else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1694 current->is32&=~(1LL<<rt1[i]);
1695 alloc_reg64(current,i,rt1[i]);
1696 alloc_all(current,i);
1697 alloc_reg64(current,i,FTEMP);
1698 minimum_free_regs[i]=HOST_REGS;
1700 else current->is32|=1LL<<rt1[i];
1701 dirty_reg(current,rt1[i]);
1702 // If using TLB, need a register for pointer to the mapping table
1703 if(using_tlb) alloc_reg(current,i,TLREG);
1704 // LWL/LWR need a temporary register for the old value
1705 if(opcode[i]==0x22||opcode[i]==0x26)
1707 alloc_reg(current,i,FTEMP);
1708 alloc_reg_temp(current,i,-1);
1709 minimum_free_regs[i]=1;
1714 // Load to r0 or unneeded register (dummy load)
1715 // but we still need a register to calculate the address
1716 if(opcode[i]==0x22||opcode[i]==0x26)
1718 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1720 // If using TLB, need a register for pointer to the mapping table
1721 if(using_tlb) alloc_reg(current,i,TLREG);
1722 alloc_reg_temp(current,i,-1);
1723 minimum_free_regs[i]=1;
1724 if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1726 alloc_all(current,i);
1727 alloc_reg64(current,i,FTEMP);
1728 minimum_free_regs[i]=HOST_REGS;
1733 void store_alloc(struct regstat *current,int i)
1735 clear_const(current,rs2[i]);
1736 if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1737 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1738 alloc_reg(current,i,rs2[i]);
1739 if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1740 alloc_reg64(current,i,rs2[i]);
1741 if(rs2[i]) alloc_reg(current,i,FTEMP);
1743 // If using TLB, need a register for pointer to the mapping table
1744 if(using_tlb) alloc_reg(current,i,TLREG);
1745 #if defined(HOST_IMM8)
1746 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1747 else alloc_reg(current,i,INVCP);
1749 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
1750 alloc_reg(current,i,FTEMP);
1752 // We need a temporary register for address generation
1753 alloc_reg_temp(current,i,-1);
1754 minimum_free_regs[i]=1;
1757 void c1ls_alloc(struct regstat *current,int i)
1759 //clear_const(current,rs1[i]); // FIXME
1760 clear_const(current,rt1[i]);
1761 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1762 alloc_reg(current,i,CSREG); // Status
1763 alloc_reg(current,i,FTEMP);
1764 if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1765 alloc_reg64(current,i,FTEMP);
1767 // If using TLB, need a register for pointer to the mapping table
1768 if(using_tlb) alloc_reg(current,i,TLREG);
1769 #if defined(HOST_IMM8)
1770 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1771 else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1772 alloc_reg(current,i,INVCP);
1774 // We need a temporary register for address generation
1775 alloc_reg_temp(current,i,-1);
1778 void c2ls_alloc(struct regstat *current,int i)
1780 clear_const(current,rt1[i]);
1781 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1782 alloc_reg(current,i,FTEMP);
1783 // If using TLB, need a register for pointer to the mapping table
1784 if(using_tlb) alloc_reg(current,i,TLREG);
1785 #if defined(HOST_IMM8)
1786 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1787 else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1788 alloc_reg(current,i,INVCP);
1790 // We need a temporary register for address generation
1791 alloc_reg_temp(current,i,-1);
1792 minimum_free_regs[i]=1;
1795 #ifndef multdiv_alloc
1796 void multdiv_alloc(struct regstat *current,int i)
1803 // case 0x1D: DMULTU
1806 clear_const(current,rs1[i]);
1807 clear_const(current,rs2[i]);
1810 if((opcode2[i]&4)==0) // 32-bit
1812 current->u&=~(1LL<<HIREG);
1813 current->u&=~(1LL<<LOREG);
1814 alloc_reg(current,i,HIREG);
1815 alloc_reg(current,i,LOREG);
1816 alloc_reg(current,i,rs1[i]);
1817 alloc_reg(current,i,rs2[i]);
1818 current->is32|=1LL<<HIREG;
1819 current->is32|=1LL<<LOREG;
1820 dirty_reg(current,HIREG);
1821 dirty_reg(current,LOREG);
1825 current->u&=~(1LL<<HIREG);
1826 current->u&=~(1LL<<LOREG);
1827 current->uu&=~(1LL<<HIREG);
1828 current->uu&=~(1LL<<LOREG);
1829 alloc_reg64(current,i,HIREG);
1830 //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1831 alloc_reg64(current,i,rs1[i]);
1832 alloc_reg64(current,i,rs2[i]);
1833 alloc_all(current,i);
1834 current->is32&=~(1LL<<HIREG);
1835 current->is32&=~(1LL<<LOREG);
1836 dirty_reg(current,HIREG);
1837 dirty_reg(current,LOREG);
1838 minimum_free_regs[i]=HOST_REGS;
1843 // Multiply by zero is zero.
1844 // MIPS does not have a divide by zero exception.
1845 // The result is undefined, we return zero.
1846 alloc_reg(current,i,HIREG);
1847 alloc_reg(current,i,LOREG);
1848 current->is32|=1LL<<HIREG;
1849 current->is32|=1LL<<LOREG;
1850 dirty_reg(current,HIREG);
1851 dirty_reg(current,LOREG);
1856 void cop0_alloc(struct regstat *current,int i)
1858 if(opcode2[i]==0) // MFC0
1861 clear_const(current,rt1[i]);
1862 alloc_all(current,i);
1863 alloc_reg(current,i,rt1[i]);
1864 current->is32|=1LL<<rt1[i];
1865 dirty_reg(current,rt1[i]);
1868 else if(opcode2[i]==4) // MTC0
1871 clear_const(current,rs1[i]);
1872 alloc_reg(current,i,rs1[i]);
1873 alloc_all(current,i);
1876 alloc_all(current,i); // FIXME: Keep r0
1878 alloc_reg(current,i,0);
1883 // TLBR/TLBWI/TLBWR/TLBP/ERET
1884 assert(opcode2[i]==0x10);
1885 alloc_all(current,i);
1887 minimum_free_regs[i]=HOST_REGS;
1890 void cop1_alloc(struct regstat *current,int i)
1892 alloc_reg(current,i,CSREG); // Load status
1893 if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1896 clear_const(current,rt1[i]);
1898 alloc_reg64(current,i,rt1[i]); // DMFC1
1899 current->is32&=~(1LL<<rt1[i]);
1901 alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1902 current->is32|=1LL<<rt1[i];
1904 dirty_reg(current,rt1[i]);
1906 alloc_reg_temp(current,i,-1);
1908 else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1911 clear_const(current,rs1[i]);
1913 alloc_reg64(current,i,rs1[i]); // DMTC1
1915 alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1916 alloc_reg_temp(current,i,-1);
1920 alloc_reg(current,i,0);
1921 alloc_reg_temp(current,i,-1);
1924 minimum_free_regs[i]=1;
1926 void fconv_alloc(struct regstat *current,int i)
1928 alloc_reg(current,i,CSREG); // Load status
1929 alloc_reg_temp(current,i,-1);
1930 minimum_free_regs[i]=1;
1932 void float_alloc(struct regstat *current,int i)
1934 alloc_reg(current,i,CSREG); // Load status
1935 alloc_reg_temp(current,i,-1);
1936 minimum_free_regs[i]=1;
1938 void c2op_alloc(struct regstat *current,int i)
1940 alloc_reg_temp(current,i,-1);
1942 void fcomp_alloc(struct regstat *current,int i)
1944 alloc_reg(current,i,CSREG); // Load status
1945 alloc_reg(current,i,FSREG); // Load flags
1946 dirty_reg(current,FSREG); // Flag will be modified
1947 alloc_reg_temp(current,i,-1);
1948 minimum_free_regs[i]=1;
1951 void syscall_alloc(struct regstat *current,int i)
1953 alloc_cc(current,i);
1954 dirty_reg(current,CCREG);
1955 alloc_all(current,i);
1956 minimum_free_regs[i]=HOST_REGS;
1960 void delayslot_alloc(struct regstat *current,int i)
1971 assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1);
1972 printf("Disabled speculative precompilation\n");
1976 imm16_alloc(current,i);
1980 load_alloc(current,i);
1984 store_alloc(current,i);
1987 alu_alloc(current,i);
1990 shift_alloc(current,i);
1993 multdiv_alloc(current,i);
1996 shiftimm_alloc(current,i);
1999 mov_alloc(current,i);
2002 cop0_alloc(current,i);
2006 cop1_alloc(current,i);
2009 c1ls_alloc(current,i);
2012 c2ls_alloc(current,i);
2015 fconv_alloc(current,i);
2018 float_alloc(current,i);
2021 fcomp_alloc(current,i);
2024 c2op_alloc(current,i);
2029 // Special case where a branch and delay slot span two pages in virtual memory
2030 static void pagespan_alloc(struct regstat *current,int i)
2033 current->wasconst=0;
2035 minimum_free_regs[i]=HOST_REGS;
2036 alloc_all(current,i);
2037 alloc_cc(current,i);
2038 dirty_reg(current,CCREG);
2039 if(opcode[i]==3) // JAL
2041 alloc_reg(current,i,31);
2042 dirty_reg(current,31);
2044 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
2046 alloc_reg(current,i,rs1[i]);
2048 alloc_reg(current,i,rt1[i]);
2049 dirty_reg(current,rt1[i]);
2052 if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
2054 if(rs1[i]) alloc_reg(current,i,rs1[i]);
2055 if(rs2[i]) alloc_reg(current,i,rs2[i]);
2056 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
2058 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2059 if(rs2[i]) alloc_reg64(current,i,rs2[i]);
2063 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
2065 if(rs1[i]) alloc_reg(current,i,rs1[i]);
2066 if(!((current->is32>>rs1[i])&1))
2068 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2072 if(opcode[i]==0x11) // BC1
2074 alloc_reg(current,i,FSREG);
2075 alloc_reg(current,i,CSREG);
2080 add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
2082 stubs[stubcount][0]=type;
2083 stubs[stubcount][1]=addr;
2084 stubs[stubcount][2]=retaddr;
2085 stubs[stubcount][3]=a;
2086 stubs[stubcount][4]=b;
2087 stubs[stubcount][5]=c;
2088 stubs[stubcount][6]=d;
2089 stubs[stubcount][7]=e;
2093 // Write out a single register
2094 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
2097 for(hr=0;hr<HOST_REGS;hr++) {
2098 if(hr!=EXCLUDE_REG) {
2099 if((regmap[hr]&63)==r) {
2102 emit_storereg(r,hr);
2104 if((is32>>regmap[hr])&1) {
2105 emit_sarimm(hr,31,hr);
2106 emit_storereg(r|64,hr);
2110 emit_storereg(r|64,hr);
2120 //if(!tracedebug) return 0;
2123 for(i=0;i<2097152;i++) {
2124 unsigned int temp=sum;
2127 sum^=((u_int *)rdram)[i];
2136 sum^=((u_int *)reg)[i];
2144 printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2146 #ifndef DISABLE_COP1
2149 printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2159 void memdebug(int i)
2161 //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2162 //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2165 //if(Count>=-2084597794) {
2166 if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2168 printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2169 //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2170 //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2173 printf("TRACE: %x\n",(&i)[-1]);
2177 printf("TRACE: %x \n",(&j)[10]);
2178 printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2182 //printf("TRACE: %x\n",(&i)[-1]);
2185 void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2187 printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2190 void alu_assemble(int i,struct regstat *i_regs)
2192 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2194 signed char s1,s2,t;
2195 t=get_reg(i_regs->regmap,rt1[i]);
2197 s1=get_reg(i_regs->regmap,rs1[i]);
2198 s2=get_reg(i_regs->regmap,rs2[i]);
2199 if(rs1[i]&&rs2[i]) {
2202 if(opcode2[i]&2) emit_sub(s1,s2,t);
2203 else emit_add(s1,s2,t);
2206 if(s1>=0) emit_mov(s1,t);
2207 else emit_loadreg(rs1[i],t);
2211 if(opcode2[i]&2) emit_neg(s2,t);
2212 else emit_mov(s2,t);
2215 emit_loadreg(rs2[i],t);
2216 if(opcode2[i]&2) emit_neg(t,t);
2219 else emit_zeroreg(t);
2223 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2225 signed char s1l,s2l,s1h,s2h,tl,th;
2226 tl=get_reg(i_regs->regmap,rt1[i]);
2227 th=get_reg(i_regs->regmap,rt1[i]|64);
2229 s1l=get_reg(i_regs->regmap,rs1[i]);
2230 s2l=get_reg(i_regs->regmap,rs2[i]);
2231 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2232 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2233 if(rs1[i]&&rs2[i]) {
2236 if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2237 else emit_adds(s1l,s2l,tl);
2239 #ifdef INVERTED_CARRY
2240 if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2242 if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2244 else emit_add(s1h,s2h,th);
2248 if(s1l>=0) emit_mov(s1l,tl);
2249 else emit_loadreg(rs1[i],tl);
2251 if(s1h>=0) emit_mov(s1h,th);
2252 else emit_loadreg(rs1[i]|64,th);
2257 if(opcode2[i]&2) emit_negs(s2l,tl);
2258 else emit_mov(s2l,tl);
2261 emit_loadreg(rs2[i],tl);
2262 if(opcode2[i]&2) emit_negs(tl,tl);
2265 #ifdef INVERTED_CARRY
2266 if(s2h>=0) emit_mov(s2h,th);
2267 else emit_loadreg(rs2[i]|64,th);
2269 emit_adcimm(-1,th); // x86 has inverted carry flag
2274 if(s2h>=0) emit_rscimm(s2h,0,th);
2276 emit_loadreg(rs2[i]|64,th);
2277 emit_rscimm(th,0,th);
2280 if(s2h>=0) emit_mov(s2h,th);
2281 else emit_loadreg(rs2[i]|64,th);
2288 if(th>=0) emit_zeroreg(th);
2293 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2295 signed char s1l,s1h,s2l,s2h,t;
2296 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2298 t=get_reg(i_regs->regmap,rt1[i]);
2301 s1l=get_reg(i_regs->regmap,rs1[i]);
2302 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2303 s2l=get_reg(i_regs->regmap,rs2[i]);
2304 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2305 if(rs2[i]==0) // rx<r0
2308 if(opcode2[i]==0x2a) // SLT
2309 emit_shrimm(s1h,31,t);
2310 else // SLTU (unsigned can not be less than zero)
2313 else if(rs1[i]==0) // r0<rx
2316 if(opcode2[i]==0x2a) // SLT
2317 emit_set_gz64_32(s2h,s2l,t);
2318 else // SLTU (set if not zero)
2319 emit_set_nz64_32(s2h,s2l,t);
2322 assert(s1l>=0);assert(s1h>=0);
2323 assert(s2l>=0);assert(s2h>=0);
2324 if(opcode2[i]==0x2a) // SLT
2325 emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2327 emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2331 t=get_reg(i_regs->regmap,rt1[i]);
2334 s1l=get_reg(i_regs->regmap,rs1[i]);
2335 s2l=get_reg(i_regs->regmap,rs2[i]);
2336 if(rs2[i]==0) // rx<r0
2339 if(opcode2[i]==0x2a) // SLT
2340 emit_shrimm(s1l,31,t);
2341 else // SLTU (unsigned can not be less than zero)
2344 else if(rs1[i]==0) // r0<rx
2347 if(opcode2[i]==0x2a) // SLT
2348 emit_set_gz32(s2l,t);
2349 else // SLTU (set if not zero)
2350 emit_set_nz32(s2l,t);
2353 assert(s1l>=0);assert(s2l>=0);
2354 if(opcode2[i]==0x2a) // SLT
2355 emit_set_if_less32(s1l,s2l,t);
2357 emit_set_if_carry32(s1l,s2l,t);
2363 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2365 signed char s1l,s1h,s2l,s2h,th,tl;
2366 tl=get_reg(i_regs->regmap,rt1[i]);
2367 th=get_reg(i_regs->regmap,rt1[i]|64);
2368 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2372 s1l=get_reg(i_regs->regmap,rs1[i]);
2373 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2374 s2l=get_reg(i_regs->regmap,rs2[i]);
2375 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2376 if(rs1[i]&&rs2[i]) {
2377 assert(s1l>=0);assert(s1h>=0);
2378 assert(s2l>=0);assert(s2h>=0);
2379 if(opcode2[i]==0x24) { // AND
2380 emit_and(s1l,s2l,tl);
2381 emit_and(s1h,s2h,th);
2383 if(opcode2[i]==0x25) { // OR
2384 emit_or(s1l,s2l,tl);
2385 emit_or(s1h,s2h,th);
2387 if(opcode2[i]==0x26) { // XOR
2388 emit_xor(s1l,s2l,tl);
2389 emit_xor(s1h,s2h,th);
2391 if(opcode2[i]==0x27) { // NOR
2392 emit_or(s1l,s2l,tl);
2393 emit_or(s1h,s2h,th);
2400 if(opcode2[i]==0x24) { // AND
2404 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2406 if(s1l>=0) emit_mov(s1l,tl);
2407 else emit_loadreg(rs1[i],tl);
2408 if(s1h>=0) emit_mov(s1h,th);
2409 else emit_loadreg(rs1[i]|64,th);
2413 if(s2l>=0) emit_mov(s2l,tl);
2414 else emit_loadreg(rs2[i],tl);
2415 if(s2h>=0) emit_mov(s2h,th);
2416 else emit_loadreg(rs2[i]|64,th);
2423 if(opcode2[i]==0x27) { // NOR
2425 if(s1l>=0) emit_not(s1l,tl);
2427 emit_loadreg(rs1[i],tl);
2430 if(s1h>=0) emit_not(s1h,th);
2432 emit_loadreg(rs1[i]|64,th);
2438 if(s2l>=0) emit_not(s2l,tl);
2440 emit_loadreg(rs2[i],tl);
2443 if(s2h>=0) emit_not(s2h,th);
2445 emit_loadreg(rs2[i]|64,th);
2461 s1l=get_reg(i_regs->regmap,rs1[i]);
2462 s2l=get_reg(i_regs->regmap,rs2[i]);
2463 if(rs1[i]&&rs2[i]) {
2466 if(opcode2[i]==0x24) { // AND
2467 emit_and(s1l,s2l,tl);
2469 if(opcode2[i]==0x25) { // OR
2470 emit_or(s1l,s2l,tl);
2472 if(opcode2[i]==0x26) { // XOR
2473 emit_xor(s1l,s2l,tl);
2475 if(opcode2[i]==0x27) { // NOR
2476 emit_or(s1l,s2l,tl);
2482 if(opcode2[i]==0x24) { // AND
2485 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2487 if(s1l>=0) emit_mov(s1l,tl);
2488 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2492 if(s2l>=0) emit_mov(s2l,tl);
2493 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2495 else emit_zeroreg(tl);
2497 if(opcode2[i]==0x27) { // NOR
2499 if(s1l>=0) emit_not(s1l,tl);
2501 emit_loadreg(rs1[i],tl);
2507 if(s2l>=0) emit_not(s2l,tl);
2509 emit_loadreg(rs2[i],tl);
2513 else emit_movimm(-1,tl);
2522 void imm16_assemble(int i,struct regstat *i_regs)
2524 if (opcode[i]==0x0f) { // LUI
2527 t=get_reg(i_regs->regmap,rt1[i]);
2530 if(!((i_regs->isconst>>t)&1))
2531 emit_movimm(imm[i]<<16,t);
2535 if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2538 t=get_reg(i_regs->regmap,rt1[i]);
2539 s=get_reg(i_regs->regmap,rs1[i]);
2544 if(!((i_regs->isconst>>t)&1)) {
2546 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2547 emit_addimm(t,imm[i],t);
2549 if(!((i_regs->wasconst>>s)&1))
2550 emit_addimm(s,imm[i],t);
2552 emit_movimm(constmap[i][s]+imm[i],t);
2558 if(!((i_regs->isconst>>t)&1))
2559 emit_movimm(imm[i],t);
2564 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2566 signed char sh,sl,th,tl;
2567 th=get_reg(i_regs->regmap,rt1[i]|64);
2568 tl=get_reg(i_regs->regmap,rt1[i]);
2569 sh=get_reg(i_regs->regmap,rs1[i]|64);
2570 sl=get_reg(i_regs->regmap,rs1[i]);
2576 emit_addimm64_32(sh,sl,imm[i],th,tl);
2579 emit_addimm(sl,imm[i],tl);
2582 emit_movimm(imm[i],tl);
2583 if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2588 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2590 //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2591 signed char sh,sl,t;
2592 t=get_reg(i_regs->regmap,rt1[i]);
2593 sh=get_reg(i_regs->regmap,rs1[i]|64);
2594 sl=get_reg(i_regs->regmap,rs1[i]);
2598 if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2599 if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2600 if(opcode[i]==0x0a) { // SLTI
2602 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2603 emit_slti32(t,imm[i],t);
2605 emit_slti32(sl,imm[i],t);
2610 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2611 emit_sltiu32(t,imm[i],t);
2613 emit_sltiu32(sl,imm[i],t);
2618 if(opcode[i]==0x0a) // SLTI
2619 emit_slti64_32(sh,sl,imm[i],t);
2621 emit_sltiu64_32(sh,sl,imm[i],t);
2624 // SLTI(U) with r0 is just stupid,
2625 // nonetheless examples can be found
2626 if(opcode[i]==0x0a) // SLTI
2627 if(0<imm[i]) emit_movimm(1,t);
2628 else emit_zeroreg(t);
2631 if(imm[i]) emit_movimm(1,t);
2632 else emit_zeroreg(t);
2638 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2640 signed char sh,sl,th,tl;
2641 th=get_reg(i_regs->regmap,rt1[i]|64);
2642 tl=get_reg(i_regs->regmap,rt1[i]);
2643 sh=get_reg(i_regs->regmap,rs1[i]|64);
2644 sl=get_reg(i_regs->regmap,rs1[i]);
2645 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2646 if(opcode[i]==0x0c) //ANDI
2650 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2651 emit_andimm(tl,imm[i],tl);
2653 if(!((i_regs->wasconst>>sl)&1))
2654 emit_andimm(sl,imm[i],tl);
2656 emit_movimm(constmap[i][sl]&imm[i],tl);
2661 if(th>=0) emit_zeroreg(th);
2667 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2671 emit_loadreg(rs1[i]|64,th);
2676 if(opcode[i]==0x0d) //ORI
2678 emit_orimm(tl,imm[i],tl);
2680 if(!((i_regs->wasconst>>sl)&1))
2681 emit_orimm(sl,imm[i],tl);
2683 emit_movimm(constmap[i][sl]|imm[i],tl);
2685 if(opcode[i]==0x0e) //XORI
2687 emit_xorimm(tl,imm[i],tl);
2689 if(!((i_regs->wasconst>>sl)&1))
2690 emit_xorimm(sl,imm[i],tl);
2692 emit_movimm(constmap[i][sl]^imm[i],tl);
2696 emit_movimm(imm[i],tl);
2697 if(th>=0) emit_zeroreg(th);
2705 void shiftimm_assemble(int i,struct regstat *i_regs)
2707 if(opcode2[i]<=0x3) // SLL/SRL/SRA
2711 t=get_reg(i_regs->regmap,rt1[i]);
2712 s=get_reg(i_regs->regmap,rs1[i]);
2714 if(t>=0&&!((i_regs->isconst>>t)&1)){
2721 if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2723 if(opcode2[i]==0) // SLL
2725 emit_shlimm(s<0?t:s,imm[i],t);
2727 if(opcode2[i]==2) // SRL
2729 emit_shrimm(s<0?t:s,imm[i],t);
2731 if(opcode2[i]==3) // SRA
2733 emit_sarimm(s<0?t:s,imm[i],t);
2737 if(s>=0 && s!=t) emit_mov(s,t);
2741 //emit_storereg(rt1[i],t); //DEBUG
2744 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2747 signed char sh,sl,th,tl;
2748 th=get_reg(i_regs->regmap,rt1[i]|64);
2749 tl=get_reg(i_regs->regmap,rt1[i]);
2750 sh=get_reg(i_regs->regmap,rs1[i]|64);
2751 sl=get_reg(i_regs->regmap,rs1[i]);
2756 if(th>=0) emit_zeroreg(th);
2763 if(opcode2[i]==0x38) // DSLL
2765 if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2766 emit_shlimm(sl,imm[i],tl);
2768 if(opcode2[i]==0x3a) // DSRL
2770 emit_shrdimm(sl,sh,imm[i],tl);
2771 if(th>=0) emit_shrimm(sh,imm[i],th);
2773 if(opcode2[i]==0x3b) // DSRA
2775 emit_shrdimm(sl,sh,imm[i],tl);
2776 if(th>=0) emit_sarimm(sh,imm[i],th);
2780 if(sl!=tl) emit_mov(sl,tl);
2781 if(th>=0&&sh!=th) emit_mov(sh,th);
2787 if(opcode2[i]==0x3c) // DSLL32
2790 signed char sl,tl,th;
2791 tl=get_reg(i_regs->regmap,rt1[i]);
2792 th=get_reg(i_regs->regmap,rt1[i]|64);
2793 sl=get_reg(i_regs->regmap,rs1[i]);
2802 emit_shlimm(th,imm[i]&31,th);
2807 if(opcode2[i]==0x3e) // DSRL32
2810 signed char sh,tl,th;
2811 tl=get_reg(i_regs->regmap,rt1[i]);
2812 th=get_reg(i_regs->regmap,rt1[i]|64);
2813 sh=get_reg(i_regs->regmap,rs1[i]|64);
2817 if(th>=0) emit_zeroreg(th);
2820 emit_shrimm(tl,imm[i]&31,tl);
2825 if(opcode2[i]==0x3f) // DSRA32
2829 tl=get_reg(i_regs->regmap,rt1[i]);
2830 sh=get_reg(i_regs->regmap,rs1[i]|64);
2836 emit_sarimm(tl,imm[i]&31,tl);
2843 #ifndef shift_assemble
2844 void shift_assemble(int i,struct regstat *i_regs)
2846 printf("Need shift_assemble for this architecture.\n");
2851 void load_assemble(int i,struct regstat *i_regs)
2853 int s,th,tl,addr,map=-1;
2856 int memtarget=0,c=0;
2857 int fastload_reg_override=0;
2859 th=get_reg(i_regs->regmap,rt1[i]|64);
2860 tl=get_reg(i_regs->regmap,rt1[i]);
2861 s=get_reg(i_regs->regmap,rs1[i]);
2863 for(hr=0;hr<HOST_REGS;hr++) {
2864 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2866 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2868 c=(i_regs->wasconst>>s)&1;
2870 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2871 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2874 //printf("load_assemble: c=%d\n",c);
2875 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2876 // FIXME: Even if the load is a NOP, we should check for pagefaults...
2878 if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2880 // could be FIFO, must perform the read
2882 assem_debug("(forced read)\n");
2883 tl=get_reg(i_regs->regmap,-1);
2887 if(offset||s<0||c) addr=tl;
2889 //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2891 //printf("load_assemble: c=%d\n",c);
2892 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2893 assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2895 if(th>=0) reglist&=~(1<<th);
2899 map=get_reg(i_regs->regmap,ROREG);
2900 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2902 //#define R29_HACK 1
2904 // Strmnnrmn's speed hack
2905 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2908 jaddr=emit_fastpath_cmp_jump(i,addr,&fastload_reg_override);
2913 if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2914 if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2915 map=get_reg(i_regs->regmap,TLREG);
2918 map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2919 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2921 int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2922 if (opcode[i]==0x20) { // LB
2925 #ifdef HOST_IMM_ADDR32
2927 emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2931 //emit_xorimm(addr,3,tl);
2932 //gen_tlb_addr_r(tl,map);
2933 //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2935 #ifdef BIG_ENDIAN_MIPS
2936 if(!c) emit_xorimm(addr,3,tl);
2937 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2941 if(fastload_reg_override) a=fastload_reg_override;
2943 emit_movsbl_indexed_tlb(x,a,map,tl);
2947 add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2950 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2952 if (opcode[i]==0x21) { // LH
2955 #ifdef HOST_IMM_ADDR32
2957 emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2962 #ifdef BIG_ENDIAN_MIPS
2963 if(!c) emit_xorimm(addr,2,tl);
2964 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2968 if(fastload_reg_override) a=fastload_reg_override;
2970 //emit_movswl_indexed_tlb(x,tl,map,tl);
2973 gen_tlb_addr_r(a,map);
2974 emit_movswl_indexed(x,a,tl);
2977 emit_movswl_indexed(x,a,tl);
2979 emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
2985 add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2988 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2990 if (opcode[i]==0x23) { // LW
2994 if(fastload_reg_override) a=fastload_reg_override;
2995 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2996 #ifdef HOST_IMM_ADDR32
2998 emit_readword_tlb(constmap[i][s]+offset,map,tl);
3001 emit_readword_indexed_tlb(0,a,map,tl);
3004 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3007 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3009 if (opcode[i]==0x24) { // LBU
3012 #ifdef HOST_IMM_ADDR32
3014 emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
3018 //emit_xorimm(addr,3,tl);
3019 //gen_tlb_addr_r(tl,map);
3020 //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
3022 #ifdef BIG_ENDIAN_MIPS
3023 if(!c) emit_xorimm(addr,3,tl);
3024 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3028 if(fastload_reg_override) a=fastload_reg_override;
3030 emit_movzbl_indexed_tlb(x,a,map,tl);
3034 add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3037 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3039 if (opcode[i]==0x25) { // LHU
3042 #ifdef HOST_IMM_ADDR32
3044 emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
3049 #ifdef BIG_ENDIAN_MIPS
3050 if(!c) emit_xorimm(addr,2,tl);
3051 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3055 if(fastload_reg_override) a=fastload_reg_override;
3057 //emit_movzwl_indexed_tlb(x,tl,map,tl);
3060 gen_tlb_addr_r(a,map);
3061 emit_movzwl_indexed(x,a,tl);
3064 emit_movzwl_indexed(x,a,tl);
3066 emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
3072 add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3075 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3077 if (opcode[i]==0x27) { // LWU
3082 if(fastload_reg_override) a=fastload_reg_override;
3083 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
3084 #ifdef HOST_IMM_ADDR32
3086 emit_readword_tlb(constmap[i][s]+offset,map,tl);
3089 emit_readword_indexed_tlb(0,a,map,tl);
3092 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3095 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3099 if (opcode[i]==0x37) { // LD
3103 if(fastload_reg_override) a=fastload_reg_override;
3104 //gen_tlb_addr_r(tl,map);
3105 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
3106 //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
3107 #ifdef HOST_IMM_ADDR32
3109 emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3112 emit_readdword_indexed_tlb(0,a,map,th,tl);
3115 add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3118 inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3121 //emit_storereg(rt1[i],tl); // DEBUG
3122 //if(opcode[i]==0x23)
3123 //if(opcode[i]==0x24)
3124 //if(opcode[i]==0x23||opcode[i]==0x24)
3125 /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
3129 emit_readword((int)&last_count,ECX);
3131 if(get_reg(i_regs->regmap,CCREG)<0)
3132 emit_loadreg(CCREG,HOST_CCREG);
3133 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3134 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3135 emit_writeword(HOST_CCREG,(int)&Count);
3138 if(get_reg(i_regs->regmap,CCREG)<0)
3139 emit_loadreg(CCREG,0);
3141 emit_mov(HOST_CCREG,0);
3143 emit_addimm(0,2*ccadj[i],0);
3144 emit_writeword(0,(int)&Count);
3146 emit_call((int)memdebug);
3148 restore_regs(0x100f);
3152 #ifndef loadlr_assemble
3153 void loadlr_assemble(int i,struct regstat *i_regs)
3155 printf("Need loadlr_assemble for this architecture.\n");
3160 void store_assemble(int i,struct regstat *i_regs)
3165 int jaddr=0,jaddr2,type;
3166 int memtarget=0,c=0;
3167 int agr=AGEN1+(i&1);
3168 int faststore_reg_override=0;
3170 th=get_reg(i_regs->regmap,rs2[i]|64);
3171 tl=get_reg(i_regs->regmap,rs2[i]);
3172 s=get_reg(i_regs->regmap,rs1[i]);
3173 temp=get_reg(i_regs->regmap,agr);
3174 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3177 c=(i_regs->wasconst>>s)&1;
3179 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3180 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3185 for(hr=0;hr<HOST_REGS;hr++) {
3186 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3188 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3189 if(offset||s<0||c) addr=temp;
3195 // Strmnnrmn's speed hack
3196 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3198 emit_cmpimm(addr,RAM_SIZE);
3199 #ifdef DESTRUCTIVE_SHIFT
3200 if(s==addr) emit_mov(s,temp);
3204 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3208 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3209 // Hint to branch predictor that the branch is unlikely to be taken
3211 emit_jno_unlikely(0);
3217 jaddr=emit_fastpath_cmp_jump(i,addr,&faststore_reg_override);
3222 if (opcode[i]==0x28) x=3; // SB
3223 if (opcode[i]==0x29) x=2; // SH
3224 map=get_reg(i_regs->regmap,TLREG);
3227 map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3228 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3231 if (opcode[i]==0x28) { // SB
3234 #ifdef BIG_ENDIAN_MIPS
3235 if(!c) emit_xorimm(addr,3,temp);
3236 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3240 if(faststore_reg_override) a=faststore_reg_override;
3241 //gen_tlb_addr_w(temp,map);
3242 //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3243 emit_writebyte_indexed_tlb(tl,x,a,map,a);
3247 if (opcode[i]==0x29) { // SH
3250 #ifdef BIG_ENDIAN_MIPS
3251 if(!c) emit_xorimm(addr,2,temp);
3252 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3256 if(faststore_reg_override) a=faststore_reg_override;
3258 //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3261 gen_tlb_addr_w(a,map);
3262 emit_writehword_indexed(tl,x,a);
3264 emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a);
3268 if (opcode[i]==0x2B) { // SW
3271 if(faststore_reg_override) a=faststore_reg_override;
3272 //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3273 emit_writeword_indexed_tlb(tl,0,a,map,temp);
3277 if (opcode[i]==0x3F) { // SD
3280 if(faststore_reg_override) a=faststore_reg_override;
3283 //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3284 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3285 emit_writedword_indexed_tlb(th,tl,0,a,map,temp);
3288 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3289 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3290 emit_writedword_indexed_tlb(tl,tl,0,a,map,temp);
3297 // PCSX store handlers don't check invcode again
3299 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3303 if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
3305 #ifdef DESTRUCTIVE_SHIFT
3306 // The x86 shift operation is 'destructive'; it overwrites the
3307 // source register, so we need to make a copy first and use that.
3310 #if defined(HOST_IMM8)
3311 int ir=get_reg(i_regs->regmap,INVCP);
3313 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3315 emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3317 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3318 emit_callne(invalidate_addr_reg[addr]);
3322 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3327 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3328 } else if(c&&!memtarget) {
3329 inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3331 //if(opcode[i]==0x2B || opcode[i]==0x3F)
3332 //if(opcode[i]==0x2B || opcode[i]==0x28)
3333 //if(opcode[i]==0x2B || opcode[i]==0x29)
3334 //if(opcode[i]==0x2B)
3335 /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3343 emit_readword((int)&last_count,ECX);
3345 if(get_reg(i_regs->regmap,CCREG)<0)
3346 emit_loadreg(CCREG,HOST_CCREG);
3347 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3348 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3349 emit_writeword(HOST_CCREG,(int)&Count);
3352 if(get_reg(i_regs->regmap,CCREG)<0)
3353 emit_loadreg(CCREG,0);
3355 emit_mov(HOST_CCREG,0);
3357 emit_addimm(0,2*ccadj[i],0);
3358 emit_writeword(0,(int)&Count);
3360 emit_call((int)memdebug);
3365 restore_regs(0x100f);
3370 void storelr_assemble(int i,struct regstat *i_regs)
3377 int case1,case2,case3;
3378 int done0,done1,done2;
3379 int memtarget=0,c=0;
3380 int agr=AGEN1+(i&1);
3382 th=get_reg(i_regs->regmap,rs2[i]|64);
3383 tl=get_reg(i_regs->regmap,rs2[i]);
3384 s=get_reg(i_regs->regmap,rs1[i]);
3385 temp=get_reg(i_regs->regmap,agr);
3386 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3389 c=(i_regs->isconst>>s)&1;
3391 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3392 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3396 for(hr=0;hr<HOST_REGS;hr++) {
3397 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3402 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3403 if(!offset&&s!=temp) emit_mov(s,temp);
3409 if(!memtarget||!rs1[i]) {
3415 int map=get_reg(i_regs->regmap,ROREG);
3416 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3417 gen_tlb_addr_w(temp,map);
3419 if((u_int)rdram!=0x80000000)
3420 emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3423 int map=get_reg(i_regs->regmap,TLREG);
3426 map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3427 if(!c&&!offset&&s>=0) emit_mov(s,temp);
3428 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3429 if(!jaddr&&!memtarget) {
3433 gen_tlb_addr_w(temp,map);
3436 if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3437 temp2=get_reg(i_regs->regmap,FTEMP);
3438 if(!rs2[i]) temp2=th=tl;
3441 #ifndef BIG_ENDIAN_MIPS
3442 emit_xorimm(temp,3,temp);
3444 emit_testimm(temp,2);
3447 emit_testimm(temp,1);
3451 if (opcode[i]==0x2A) { // SWL
3452 emit_writeword_indexed(tl,0,temp);
3454 if (opcode[i]==0x2E) { // SWR
3455 emit_writebyte_indexed(tl,3,temp);
3457 if (opcode[i]==0x2C) { // SDL
3458 emit_writeword_indexed(th,0,temp);
3459 if(rs2[i]) emit_mov(tl,temp2);
3461 if (opcode[i]==0x2D) { // SDR
3462 emit_writebyte_indexed(tl,3,temp);
3463 if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3468 set_jump_target(case1,(int)out);
3469 if (opcode[i]==0x2A) { // SWL
3470 // Write 3 msb into three least significant bytes
3471 if(rs2[i]) emit_rorimm(tl,8,tl);
3472 emit_writehword_indexed(tl,-1,temp);
3473 if(rs2[i]) emit_rorimm(tl,16,tl);
3474 emit_writebyte_indexed(tl,1,temp);
3475 if(rs2[i]) emit_rorimm(tl,8,tl);
3477 if (opcode[i]==0x2E) { // SWR
3478 // Write two lsb into two most significant bytes
3479 emit_writehword_indexed(tl,1,temp);
3481 if (opcode[i]==0x2C) { // SDL
3482 if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3483 // Write 3 msb into three least significant bytes
3484 if(rs2[i]) emit_rorimm(th,8,th);
3485 emit_writehword_indexed(th,-1,temp);
3486 if(rs2[i]) emit_rorimm(th,16,th);
3487 emit_writebyte_indexed(th,1,temp);
3488 if(rs2[i]) emit_rorimm(th,8,th);
3490 if (opcode[i]==0x2D) { // SDR
3491 if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3492 // Write two lsb into two most significant bytes
3493 emit_writehword_indexed(tl,1,temp);
3498 set_jump_target(case2,(int)out);
3499 emit_testimm(temp,1);
3502 if (opcode[i]==0x2A) { // SWL
3503 // Write two msb into two least significant bytes
3504 if(rs2[i]) emit_rorimm(tl,16,tl);
3505 emit_writehword_indexed(tl,-2,temp);
3506 if(rs2[i]) emit_rorimm(tl,16,tl);
3508 if (opcode[i]==0x2E) { // SWR
3509 // Write 3 lsb into three most significant bytes
3510 emit_writebyte_indexed(tl,-1,temp);
3511 if(rs2[i]) emit_rorimm(tl,8,tl);
3512 emit_writehword_indexed(tl,0,temp);
3513 if(rs2[i]) emit_rorimm(tl,24,tl);
3515 if (opcode[i]==0x2C) { // SDL
3516 if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3517 // Write two msb into two least significant bytes
3518 if(rs2[i]) emit_rorimm(th,16,th);
3519 emit_writehword_indexed(th,-2,temp);
3520 if(rs2[i]) emit_rorimm(th,16,th);
3522 if (opcode[i]==0x2D) { // SDR
3523 if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3524 // Write 3 lsb into three most significant bytes
3525 emit_writebyte_indexed(tl,-1,temp);
3526 if(rs2[i]) emit_rorimm(tl,8,tl);
3527 emit_writehword_indexed(tl,0,temp);
3528 if(rs2[i]) emit_rorimm(tl,24,tl);
3533 set_jump_target(case3,(int)out);
3534 if (opcode[i]==0x2A) { // SWL
3535 // Write msb into least significant byte
3536 if(rs2[i]) emit_rorimm(tl,24,tl);
3537 emit_writebyte_indexed(tl,-3,temp);
3538 if(rs2[i]) emit_rorimm(tl,8,tl);
3540 if (opcode[i]==0x2E) { // SWR
3541 // Write entire word
3542 emit_writeword_indexed(tl,-3,temp);
3544 if (opcode[i]==0x2C) { // SDL
3545 if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3546 // Write msb into least significant byte
3547 if(rs2[i]) emit_rorimm(th,24,th);
3548 emit_writebyte_indexed(th,-3,temp);
3549 if(rs2[i]) emit_rorimm(th,8,th);
3551 if (opcode[i]==0x2D) { // SDR
3552 if(rs2[i]) emit_mov(th,temp2);
3553 // Write entire word
3554 emit_writeword_indexed(tl,-3,temp);
3556 set_jump_target(done0,(int)out);
3557 set_jump_target(done1,(int)out);
3558 set_jump_target(done2,(int)out);
3559 if (opcode[i]==0x2C) { // SDL
3560 emit_testimm(temp,4);
3563 emit_andimm(temp,~3,temp);
3564 emit_writeword_indexed(temp2,4,temp);
3565 set_jump_target(done0,(int)out);
3567 if (opcode[i]==0x2D) { // SDR
3568 emit_testimm(temp,4);
3571 emit_andimm(temp,~3,temp);
3572 emit_writeword_indexed(temp2,-4,temp);
3573 set_jump_target(done0,(int)out);
3576 add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
3577 if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
3579 int map=get_reg(i_regs->regmap,ROREG);
3580 if(map<0) map=HOST_TEMPREG;
3581 gen_orig_addr_w(temp,map);
3583 emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
3585 #if defined(HOST_IMM8)
3586 int ir=get_reg(i_regs->regmap,INVCP);
3588 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3590 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3592 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3593 emit_callne(invalidate_addr_reg[temp]);
3597 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3602 //save_regs(0x100f);
3603 emit_readword((int)&last_count,ECX);
3604 if(get_reg(i_regs->regmap,CCREG)<0)
3605 emit_loadreg(CCREG,HOST_CCREG);
3606 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3607 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3608 emit_writeword(HOST_CCREG,(int)&Count);
3609 emit_call((int)memdebug);
3611 //restore_regs(0x100f);
3615 void c1ls_assemble(int i,struct regstat *i_regs)
3617 #ifndef DISABLE_COP1
3623 int jaddr,jaddr2=0,jaddr3,type;
3624 int agr=AGEN1+(i&1);
3626 th=get_reg(i_regs->regmap,FTEMP|64);
3627 tl=get_reg(i_regs->regmap,FTEMP);
3628 s=get_reg(i_regs->regmap,rs1[i]);
3629 temp=get_reg(i_regs->regmap,agr);
3630 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3635 for(hr=0;hr<HOST_REGS;hr++) {
3636 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3638 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3639 if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3641 // Loads use a temporary register which we need to save
3644 if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3648 //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3649 //else c=(i_regs->wasconst>>s)&1;
3650 if(s>=0) c=(i_regs->wasconst>>s)&1;
3651 // Check cop1 unusable
3653 signed char rs=get_reg(i_regs->regmap,CSREG);
3655 emit_testimm(rs,0x20000000);
3658 add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3661 if (opcode[i]==0x39) { // SWC1 (get float address)
3662 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],tl);
3664 if (opcode[i]==0x3D) { // SDC1 (get double address)
3665 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],tl);
3667 // Generate address + offset
3670 emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3674 map=get_reg(i_regs->regmap,TLREG);
3677 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3678 map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
3680 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3681 map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
3684 if (opcode[i]==0x39) { // SWC1 (read float)
3685 emit_readword_indexed(0,tl,tl);
3687 if (opcode[i]==0x3D) { // SDC1 (read double)
3688 emit_readword_indexed(4,tl,th);
3689 emit_readword_indexed(0,tl,tl);
3691 if (opcode[i]==0x31) { // LWC1 (get target address)
3692 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],temp);
3694 if (opcode[i]==0x35) { // LDC1 (get target address)
3695 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],temp);
3702 else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80000000+RAM_SIZE) {
3704 emit_jmp(0); // inline_readstub/inline_writestub? Very rare case
3706 #ifdef DESTRUCTIVE_SHIFT
3707 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3708 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3712 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3713 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3715 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3716 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3719 if (opcode[i]==0x31) { // LWC1
3720 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3721 //gen_tlb_addr_r(ar,map);
3722 //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3723 #ifdef HOST_IMM_ADDR32
3724 if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3727 emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3730 if (opcode[i]==0x35) { // LDC1
3732 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3733 //gen_tlb_addr_r(ar,map);
3734 //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3735 //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3736 #ifdef HOST_IMM_ADDR32
3737 if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3740 emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3743 if (opcode[i]==0x39) { // SWC1
3744 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3745 emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3748 if (opcode[i]==0x3D) { // SDC1
3750 //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3751 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3752 emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3755 if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
3756 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3757 #ifndef DESTRUCTIVE_SHIFT
3758 temp=offset||c||s<0?ar:s;
3760 #if defined(HOST_IMM8)
3761 int ir=get_reg(i_regs->regmap,INVCP);
3763 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3765 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3767 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3768 emit_callne(invalidate_addr_reg[temp]);
3772 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3776 if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3777 if (opcode[i]==0x31) { // LWC1 (write float)
3778 emit_writeword_indexed(tl,0,temp);
3780 if (opcode[i]==0x35) { // LDC1 (write double)
3781 emit_writeword_indexed(th,4,temp);
3782 emit_writeword_indexed(tl,0,temp);
3784 //if(opcode[i]==0x39)
3785 /*if(opcode[i]==0x39||opcode[i]==0x31)
3788 emit_readword((int)&last_count,ECX);
3789 if(get_reg(i_regs->regmap,CCREG)<0)
3790 emit_loadreg(CCREG,HOST_CCREG);
3791 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3792 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3793 emit_writeword(HOST_CCREG,(int)&Count);
3794 emit_call((int)memdebug);
3798 cop1_unusable(i, i_regs);
3802 void c2ls_assemble(int i,struct regstat *i_regs)
3807 int memtarget=0,c=0;
3808 int jaddr2=0,jaddr3,type;
3809 int agr=AGEN1+(i&1);
3810 int fastio_reg_override=0;
3812 u_int copr=(source[i]>>16)&0x1f;
3813 s=get_reg(i_regs->regmap,rs1[i]);
3814 tl=get_reg(i_regs->regmap,FTEMP);
3820 for(hr=0;hr<HOST_REGS;hr++) {
3821 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3823 if(i_regs->regmap[HOST_CCREG]==CCREG)
3824 reglist&=~(1<<HOST_CCREG);
3827 if (opcode[i]==0x3a) { // SWC2
3828 ar=get_reg(i_regs->regmap,agr);
3829 if(ar<0) ar=get_reg(i_regs->regmap,-1);
3834 if(s>=0) c=(i_regs->wasconst>>s)&1;
3835 memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
3836 if (!offset&&!c&&s>=0) ar=s;
3839 if (opcode[i]==0x3a) { // SWC2
3840 cop2_get_dreg(copr,tl,HOST_TEMPREG);
3848 emit_jmp(0); // inline_readstub/inline_writestub?
3852 jaddr2=emit_fastpath_cmp_jump(i,ar,&fastio_reg_override);
3854 if (opcode[i]==0x32) { // LWC2
3855 #ifdef HOST_IMM_ADDR32
3856 if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
3860 if(fastio_reg_override) a=fastio_reg_override;
3861 emit_readword_indexed(0,a,tl);
3863 if (opcode[i]==0x3a) { // SWC2
3864 #ifdef DESTRUCTIVE_SHIFT
3865 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3868 if(fastio_reg_override) a=fastio_reg_override;
3869 emit_writeword_indexed(tl,0,a);
3873 add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist);
3874 if(opcode[i]==0x3a) // SWC2
3875 if(!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
3876 #if defined(HOST_IMM8)
3877 int ir=get_reg(i_regs->regmap,INVCP);
3879 emit_cmpmem_indexedsr12_reg(ir,ar,1);
3881 emit_cmpmem_indexedsr12_imm((int)invalid_code,ar,1);
3883 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3884 emit_callne(invalidate_addr_reg[ar]);
3888 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),ar,0,0,0);
3891 if (opcode[i]==0x32) { // LWC2
3892 cop2_put_dreg(copr,tl,HOST_TEMPREG);
3896 #ifndef multdiv_assemble
3897 void multdiv_assemble(int i,struct regstat *i_regs)
3899 printf("Need multdiv_assemble for this architecture.\n");
3904 void mov_assemble(int i,struct regstat *i_regs)
3906 //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3907 //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
3909 signed char sh,sl,th,tl;
3910 th=get_reg(i_regs->regmap,rt1[i]|64);
3911 tl=get_reg(i_regs->regmap,rt1[i]);
3914 sh=get_reg(i_regs->regmap,rs1[i]|64);
3915 sl=get_reg(i_regs->regmap,rs1[i]);
3916 if(sl>=0) emit_mov(sl,tl);
3917 else emit_loadreg(rs1[i],tl);
3919 if(sh>=0) emit_mov(sh,th);
3920 else emit_loadreg(rs1[i]|64,th);
3926 #ifndef fconv_assemble
3927 void fconv_assemble(int i,struct regstat *i_regs)
3929 printf("Need fconv_assemble for this architecture.\n");
3935 void float_assemble(int i,struct regstat *i_regs)
3937 printf("Need float_assemble for this architecture.\n");
3942 void syscall_assemble(int i,struct regstat *i_regs)
3944 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3945 assert(ccreg==HOST_CCREG);
3946 assert(!is_delayslot);
3947 emit_movimm(start+i*4,EAX); // Get PC
3948 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
3949 emit_jmp((int)jump_syscall_hle); // XXX
3952 void hlecall_assemble(int i,struct regstat *i_regs)
3954 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3955 assert(ccreg==HOST_CCREG);
3956 assert(!is_delayslot);
3957 emit_movimm(start+i*4+4,0); // Get PC
3958 emit_movimm((int)psxHLEt[source[i]&7],1);
3959 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // XXX
3960 emit_jmp((int)jump_hlecall);
3963 void intcall_assemble(int i,struct regstat *i_regs)
3965 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3966 assert(ccreg==HOST_CCREG);
3967 assert(!is_delayslot);
3968 emit_movimm(start+i*4,0); // Get PC
3969 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG);
3970 emit_jmp((int)jump_intcall);
3973 void ds_assemble(int i,struct regstat *i_regs)
3975 speculate_register_values(i);
3979 alu_assemble(i,i_regs);break;
3981 imm16_assemble(i,i_regs);break;
3983 shift_assemble(i,i_regs);break;
3985 shiftimm_assemble(i,i_regs);break;
3987 load_assemble(i,i_regs);break;
3989 loadlr_assemble(i,i_regs);break;
3991 store_assemble(i,i_regs);break;
3993 storelr_assemble(i,i_regs);break;
3995 cop0_assemble(i,i_regs);break;
3997 cop1_assemble(i,i_regs);break;
3999 c1ls_assemble(i,i_regs);break;
4001 cop2_assemble(i,i_regs);break;
4003 c2ls_assemble(i,i_regs);break;
4005 c2op_assemble(i,i_regs);break;
4007 fconv_assemble(i,i_regs);break;
4009 float_assemble(i,i_regs);break;
4011 fcomp_assemble(i,i_regs);break;
4013 multdiv_assemble(i,i_regs);break;
4015 mov_assemble(i,i_regs);break;
4025 printf("Jump in the delay slot. This is probably a bug.\n");
4030 // Is the branch target a valid internal jump?
4031 int internal_branch(uint64_t i_is32,int addr)
4033 if(addr&1) return 0; // Indirect (register) jump
4034 if(addr>=start && addr<start+slen*4-4)
4036 int t=(addr-start)>>2;
4037 // Delay slots are not valid branch targets
4038 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4039 // 64 -> 32 bit transition requires a recompile
4040 /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
4042 if(requires_32bit[t]&~i_is32) printf("optimizable: no\n");
4043 else printf("optimizable: yes\n");
4045 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4047 if(requires_32bit[t]&~i_is32) return 0;
4055 #ifndef wb_invalidate
4056 void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
4057 uint64_t u,uint64_t uu)
4060 for(hr=0;hr<HOST_REGS;hr++) {
4061 if(hr!=EXCLUDE_REG) {
4062 if(pre[hr]!=entry[hr]) {
4065 if(get_reg(entry,pre[hr])<0) {
4067 if(!((u>>pre[hr])&1)) {
4068 emit_storereg(pre[hr],hr);
4069 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
4070 emit_sarimm(hr,31,hr);
4071 emit_storereg(pre[hr]|64,hr);
4075 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
4076 emit_storereg(pre[hr],hr);
4085 // Move from one register to another (no writeback)
4086 for(hr=0;hr<HOST_REGS;hr++) {
4087 if(hr!=EXCLUDE_REG) {
4088 if(pre[hr]!=entry[hr]) {
4089 if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
4091 if((nr=get_reg(entry,pre[hr]))>=0) {
4101 // Load the specified registers
4102 // This only loads the registers given as arguments because
4103 // we don't want to load things that will be overwritten
4104 void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
4108 for(hr=0;hr<HOST_REGS;hr++) {
4109 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4110 if(entry[hr]!=regmap[hr]) {
4111 if(regmap[hr]==rs1||regmap[hr]==rs2)
4118 emit_loadreg(regmap[hr],hr);
4125 for(hr=0;hr<HOST_REGS;hr++) {
4126 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4127 if(entry[hr]!=regmap[hr]) {
4128 if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
4130 assert(regmap[hr]!=64);
4131 if((is32>>(regmap[hr]&63))&1) {
4132 int lr=get_reg(regmap,regmap[hr]-64);
4134 emit_sarimm(lr,31,hr);
4136 emit_loadreg(regmap[hr],hr);
4140 emit_loadreg(regmap[hr],hr);
4148 // Load registers prior to the start of a loop
4149 // so that they are not loaded within the loop
4150 static void loop_preload(signed char pre[],signed char entry[])
4153 for(hr=0;hr<HOST_REGS;hr++) {
4154 if(hr!=EXCLUDE_REG) {
4155 if(pre[hr]!=entry[hr]) {
4157 if(get_reg(pre,entry[hr])<0) {
4158 assem_debug("loop preload:\n");
4159 //printf("loop preload: %d\n",hr);
4163 else if(entry[hr]<TEMPREG)
4165 emit_loadreg(entry[hr],hr);
4167 else if(entry[hr]-64<TEMPREG)
4169 emit_loadreg(entry[hr],hr);
4178 // Generate address for load/store instruction
4179 // goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
4180 void address_generation(int i,struct regstat *i_regs,signed char entry[])
4182 if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS||itype[i]==C2LS) {
4184 int agr=AGEN1+(i&1);
4185 int mgr=MGEN1+(i&1);
4186 if(itype[i]==LOAD) {
4187 ra=get_reg(i_regs->regmap,rt1[i]);
4188 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4191 if(itype[i]==LOADLR) {
4192 ra=get_reg(i_regs->regmap,FTEMP);
4194 if(itype[i]==STORE||itype[i]==STORELR) {
4195 ra=get_reg(i_regs->regmap,agr);
4196 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4198 if(itype[i]==C1LS||itype[i]==C2LS) {
4199 if ((opcode[i]&0x3b)==0x31||(opcode[i]&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
4200 ra=get_reg(i_regs->regmap,FTEMP);
4201 else { // SWC1/SDC1/SWC2/SDC2
4202 ra=get_reg(i_regs->regmap,agr);
4203 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4206 int rs=get_reg(i_regs->regmap,rs1[i]);
4207 int rm=get_reg(i_regs->regmap,TLREG);
4210 int c=(i_regs->wasconst>>rs)&1;
4212 // Using r0 as a base address
4214 if(!entry||entry[rm]!=mgr) {
4215 generate_map_const(offset,rm);
4216 } // else did it in the previous cycle
4218 if(!entry||entry[ra]!=agr) {
4219 if (opcode[i]==0x22||opcode[i]==0x26) {
4220 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4221 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4222 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4224 emit_movimm(offset,ra);
4226 } // else did it in the previous cycle
4229 if(!entry||entry[ra]!=rs1[i])
4230 emit_loadreg(rs1[i],ra);
4231 //if(!entry||entry[ra]!=rs1[i])
4232 // printf("poor load scheduling!\n");
4237 if(!entry||entry[rm]!=mgr) {
4238 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a) {
4239 // Stores to memory go thru the mapper to detect self-modifying
4240 // code, loads don't.
4241 if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
4242 (unsigned int)(constmap[i][rs]+offset)<0x80000000+RAM_SIZE )
4243 generate_map_const(constmap[i][rs]+offset,rm);
4245 if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
4246 generate_map_const(constmap[i][rs]+offset,rm);
4251 if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
4252 if(!entry||entry[ra]!=agr) {
4253 if (opcode[i]==0x22||opcode[i]==0x26) {
4254 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4255 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4256 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4258 #ifdef HOST_IMM_ADDR32
4259 if((itype[i]!=LOAD&&(opcode[i]&0x3b)!=0x31&&(opcode[i]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4260 (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
4262 emit_movimm(constmap[i][rs]+offset,ra);
4263 regs[i].loadedconst|=1<<ra;
4265 } // else did it in the previous cycle
4266 } // else load_consts already did it
4268 if(offset&&!c&&rs1[i]) {
4270 emit_addimm(rs,offset,ra);
4272 emit_addimm(ra,offset,ra);
4277 // Preload constants for next instruction
4278 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
4280 #if !defined(HOST_IMM_ADDR32) && !defined(DISABLE_TLB)
4282 agr=MGEN1+((i+1)&1);
4283 ra=get_reg(i_regs->regmap,agr);
4285 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4286 int offset=imm[i+1];
4287 int c=(regs[i+1].wasconst>>rs)&1;
4289 if(itype[i+1]==STORE||itype[i+1]==STORELR
4290 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1, SWC2/SDC2
4291 // Stores to memory go thru the mapper to detect self-modifying
4292 // code, loads don't.
4293 if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
4294 (unsigned int)(constmap[i+1][rs]+offset)<0x80000000+RAM_SIZE )
4295 generate_map_const(constmap[i+1][rs]+offset,ra);
4297 if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
4298 generate_map_const(constmap[i+1][rs]+offset,ra);
4301 /*else if(rs1[i]==0) {
4302 generate_map_const(offset,ra);
4307 agr=AGEN1+((i+1)&1);
4308 ra=get_reg(i_regs->regmap,agr);
4310 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4311 int offset=imm[i+1];
4312 int c=(regs[i+1].wasconst>>rs)&1;
4313 if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
4314 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4315 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4316 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4317 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4319 #ifdef HOST_IMM_ADDR32
4320 if((itype[i+1]!=LOAD&&(opcode[i+1]&0x3b)!=0x31&&(opcode[i+1]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4321 (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000))
4323 emit_movimm(constmap[i+1][rs]+offset,ra);
4324 regs[i+1].loadedconst|=1<<ra;
4327 else if(rs1[i+1]==0) {
4328 // Using r0 as a base address
4329 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4330 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4331 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4332 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4334 emit_movimm(offset,ra);
4341 int get_final_value(int hr, int i, int *value)
4343 int reg=regs[i].regmap[hr];
4345 if(regs[i+1].regmap[hr]!=reg) break;
4346 if(!((regs[i+1].isconst>>hr)&1)) break;
4351 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
4352 *value=constmap[i][hr];
4356 if(itype[i+1]==UJUMP||itype[i+1]==RJUMP||itype[i+1]==CJUMP||itype[i+1]==SJUMP) {
4357 // Load in delay slot, out-of-order execution
4358 if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
4360 #ifdef HOST_IMM_ADDR32
4361 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+2])<(signed int)0xC0000000) return 0;
4363 // Precompute load address
4364 *value=constmap[i][hr]+imm[i+2];
4368 if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)
4370 #ifdef HOST_IMM_ADDR32
4371 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+1])<(signed int)0xC0000000) return 0;
4373 // Precompute load address
4374 *value=constmap[i][hr]+imm[i+1];
4375 //printf("c=%x imm=%x\n",(int)constmap[i][hr],imm[i+1]);
4380 *value=constmap[i][hr];
4381 //printf("c=%x\n",(int)constmap[i][hr]);
4382 if(i==slen-1) return 1;
4384 return !((unneeded_reg[i+1]>>reg)&1);
4386 return !((unneeded_reg_upper[i+1]>>reg)&1);
4390 // Load registers with known constants
4391 void load_consts(signed char pre[],signed char regmap[],int is32,int i)
4394 // propagate loaded constant flags
4396 regs[i].loadedconst=0;
4398 for(hr=0;hr<HOST_REGS;hr++) {
4399 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((regs[i-1].isconst>>hr)&1)&&pre[hr]==regmap[hr]
4400 &®map[hr]==regs[i-1].regmap[hr]&&((regs[i-1].loadedconst>>hr)&1))
4402 regs[i].loadedconst|=1<<hr;
4407 for(hr=0;hr<HOST_REGS;hr++) {
4408 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4409 //if(entry[hr]!=regmap[hr]) {
4410 if(!((regs[i].loadedconst>>hr)&1)) {
4411 if(((regs[i].isconst>>hr)&1)&®map[hr]<64&®map[hr]>0) {
4412 int value,similar=0;
4413 if(get_final_value(hr,i,&value)) {
4414 // see if some other register has similar value
4415 for(hr2=0;hr2<HOST_REGS;hr2++) {
4416 if(hr2!=EXCLUDE_REG&&((regs[i].loadedconst>>hr2)&1)) {
4417 if(is_similar_value(value,constmap[i][hr2])) {
4425 if(get_final_value(hr2,i,&value2)) // is this needed?
4426 emit_movimm_from(value2,hr2,value,hr);
4428 emit_movimm(value,hr);
4434 emit_movimm(value,hr);
4437 regs[i].loadedconst|=1<<hr;
4443 for(hr=0;hr<HOST_REGS;hr++) {
4444 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4445 //if(entry[hr]!=regmap[hr]) {
4446 if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4447 if(((regs[i].isconst>>hr)&1)&®map[hr]>64) {
4448 if((is32>>(regmap[hr]&63))&1) {
4449 int lr=get_reg(regmap,regmap[hr]-64);
4451 emit_sarimm(lr,31,hr);
4456 if(get_final_value(hr,i,&value)) {
4461 emit_movimm(value,hr);
4470 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i)
4474 for(hr=0;hr<HOST_REGS;hr++) {
4475 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) {
4476 if(((regs[i].isconst>>hr)&1)&®map[hr]<64&®map[hr]>0) {
4477 int value=constmap[i][hr];
4482 emit_movimm(value,hr);
4488 for(hr=0;hr<HOST_REGS;hr++) {
4489 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) {
4490 if(((regs[i].isconst>>hr)&1)&®map[hr]>64) {
4491 if((is32>>(regmap[hr]&63))&1) {
4492 int lr=get_reg(regmap,regmap[hr]-64);
4494 emit_sarimm(lr,31,hr);
4498 int value=constmap[i][hr];
4503 emit_movimm(value,hr);
4511 // Write out all dirty registers (except cycle count)
4512 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty)
4515 for(hr=0;hr<HOST_REGS;hr++) {
4516 if(hr!=EXCLUDE_REG) {
4517 if(i_regmap[hr]>0) {
4518 if(i_regmap[hr]!=CCREG) {
4519 if((i_dirty>>hr)&1) {
4520 if(i_regmap[hr]<64) {
4521 emit_storereg(i_regmap[hr],hr);
4523 if( ((i_is32>>i_regmap[hr])&1) ) {
4524 #ifdef DESTRUCTIVE_WRITEBACK
4525 emit_sarimm(hr,31,hr);
4526 emit_storereg(i_regmap[hr]|64,hr);
4528 emit_sarimm(hr,31,HOST_TEMPREG);
4529 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4534 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4535 emit_storereg(i_regmap[hr],hr);
4544 // Write out dirty registers that we need to reload (pair with load_needed_regs)
4545 // This writes the registers not written by store_regs_bt
4546 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4549 int t=(addr-start)>>2;
4550 for(hr=0;hr<HOST_REGS;hr++) {
4551 if(hr!=EXCLUDE_REG) {
4552 if(i_regmap[hr]>0) {
4553 if(i_regmap[hr]!=CCREG) {
4554 if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1) && !(((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4555 if((i_dirty>>hr)&1) {
4556 if(i_regmap[hr]<64) {
4557 emit_storereg(i_regmap[hr],hr);
4559 if( ((i_is32>>i_regmap[hr])&1) ) {
4560 #ifdef DESTRUCTIVE_WRITEBACK
4561 emit_sarimm(hr,31,hr);
4562 emit_storereg(i_regmap[hr]|64,hr);
4564 emit_sarimm(hr,31,HOST_TEMPREG);
4565 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4570 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4571 emit_storereg(i_regmap[hr],hr);
4582 // Load all registers (except cycle count)
4583 void load_all_regs(signed char i_regmap[])
4586 for(hr=0;hr<HOST_REGS;hr++) {
4587 if(hr!=EXCLUDE_REG) {
4588 if(i_regmap[hr]==0) {
4592 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4594 emit_loadreg(i_regmap[hr],hr);
4600 // Load all current registers also needed by next instruction
4601 void load_needed_regs(signed char i_regmap[],signed char next_regmap[])
4604 for(hr=0;hr<HOST_REGS;hr++) {
4605 if(hr!=EXCLUDE_REG) {
4606 if(get_reg(next_regmap,i_regmap[hr])>=0) {
4607 if(i_regmap[hr]==0) {
4611 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4613 emit_loadreg(i_regmap[hr],hr);
4620 // Load all regs, storing cycle count if necessary
4621 void load_regs_entry(int t)
4624 if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_ADJUST(1),HOST_CCREG);
4625 else if(ccadj[t]) emit_addimm(HOST_CCREG,-CLOCK_ADJUST(ccadj[t]),HOST_CCREG);
4626 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4627 emit_storereg(CCREG,HOST_CCREG);
4630 for(hr=0;hr<HOST_REGS;hr++) {
4631 if(regs[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) {
4632 if(regs[t].regmap_entry[hr]==0) {
4635 else if(regs[t].regmap_entry[hr]!=CCREG)
4637 emit_loadreg(regs[t].regmap_entry[hr],hr);
4642 for(hr=0;hr<HOST_REGS;hr++) {
4643 if(regs[t].regmap_entry[hr]>=64&®s[t].regmap_entry[hr]<TEMPREG+64) {
4644 assert(regs[t].regmap_entry[hr]!=64);
4645 if((regs[t].was32>>(regs[t].regmap_entry[hr]&63))&1) {
4646 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4648 emit_loadreg(regs[t].regmap_entry[hr],hr);
4652 emit_sarimm(lr,31,hr);
4657 emit_loadreg(regs[t].regmap_entry[hr],hr);
4663 // Store dirty registers prior to branch
4664 void store_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4666 if(internal_branch(i_is32,addr))
4668 int t=(addr-start)>>2;
4670 for(hr=0;hr<HOST_REGS;hr++) {
4671 if(hr!=EXCLUDE_REG) {
4672 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4673 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4674 if((i_dirty>>hr)&1) {
4675 if(i_regmap[hr]<64) {
4676 if(!((unneeded_reg[t]>>i_regmap[hr])&1)) {
4677 emit_storereg(i_regmap[hr],hr);
4678 if( ((i_is32>>i_regmap[hr])&1) && !((unneeded_reg_upper[t]>>i_regmap[hr])&1) ) {
4679 #ifdef DESTRUCTIVE_WRITEBACK
4680 emit_sarimm(hr,31,hr);
4681 emit_storereg(i_regmap[hr]|64,hr);
4683 emit_sarimm(hr,31,HOST_TEMPREG);
4684 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4689 if( !((i_is32>>(i_regmap[hr]&63))&1) && !((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1) ) {
4690 emit_storereg(i_regmap[hr],hr);
4701 // Branch out of this block, write out all dirty regs
4702 wb_dirtys(i_regmap,i_is32,i_dirty);
4706 // Load all needed registers for branch target
4707 void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4709 //if(addr>=start && addr<(start+slen*4))
4710 if(internal_branch(i_is32,addr))
4712 int t=(addr-start)>>2;
4714 // Store the cycle count before loading something else
4715 if(i_regmap[HOST_CCREG]!=CCREG) {
4716 assert(i_regmap[HOST_CCREG]==-1);
4718 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4719 emit_storereg(CCREG,HOST_CCREG);
4722 for(hr=0;hr<HOST_REGS;hr++) {
4723 if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) {
4724 #ifdef DESTRUCTIVE_WRITEBACK
4725 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || ( !((regs[t].dirty>>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4727 if(i_regmap[hr]!=regs[t].regmap_entry[hr] ) {
4729 if(regs[t].regmap_entry[hr]==0) {
4732 else if(regs[t].regmap_entry[hr]!=CCREG)
4734 emit_loadreg(regs[t].regmap_entry[hr],hr);
4740 for(hr=0;hr<HOST_REGS;hr++) {
4741 if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=64&®s[t].regmap_entry[hr]<TEMPREG+64) {
4742 if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4743 assert(regs[t].regmap_entry[hr]!=64);
4744 if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4745 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4747 emit_loadreg(regs[t].regmap_entry[hr],hr);
4751 emit_sarimm(lr,31,hr);
4756 emit_loadreg(regs[t].regmap_entry[hr],hr);
4759 else if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4760 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4762 emit_sarimm(lr,31,hr);
4769 int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4771 if(addr>=start && addr<start+slen*4-4)
4773 int t=(addr-start)>>2;
4775 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4776 for(hr=0;hr<HOST_REGS;hr++)
4780 if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4782 if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
4789 if(i_regmap[hr]<TEMPREG)
4791 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4794 else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
4796 if(!((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1))
4801 else // Same register but is it 32-bit or dirty?
4804 if(!((regs[t].dirty>>hr)&1))
4808 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4810 //printf("%x: dirty no match\n",addr);
4815 if((((regs[t].was32^i_is32)&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)
4817 //printf("%x: is32 no match\n",addr);
4823 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4825 if(requires_32bit[t]&~i_is32) return 0;
4827 // Delay slots are not valid branch targets
4828 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4829 // Delay slots require additional processing, so do not match
4830 if(is_ds[t]) return 0;
4835 for(hr=0;hr<HOST_REGS;hr++)
4841 if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4855 // Used when a branch jumps into the delay slot of another branch
4856 void ds_assemble_entry(int i)
4858 int t=(ba[i]-start)>>2;
4859 if(!instr_addr[t]) instr_addr[t]=(u_int)out;
4860 assem_debug("Assemble delay slot at %x\n",ba[i]);
4861 assem_debug("<->\n");
4862 if(regs[t].regmap_entry[HOST_CCREG]==CCREG&®s[t].regmap[HOST_CCREG]!=CCREG)
4863 wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty,regs[t].was32);
4864 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,rs1[t],rs2[t]);
4865 address_generation(t,®s[t],regs[t].regmap_entry);
4866 if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39||(opcode[t]&0x3b)==0x3a)
4867 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,INVCP,INVCP);
4872 alu_assemble(t,®s[t]);break;
4874 imm16_assemble(t,®s[t]);break;
4876 shift_assemble(t,®s[t]);break;
4878 shiftimm_assemble(t,®s[t]);break;
4880 load_assemble(t,®s[t]);break;
4882 loadlr_assemble(t,®s[t]);break;
4884 store_assemble(t,®s[t]);break;
4886 storelr_assemble(t,®s[t]);break;
4888 cop0_assemble(t,®s[t]);break;
4890 cop1_assemble(t,®s[t]);break;
4892 c1ls_assemble(t,®s[t]);break;
4894 cop2_assemble(t,®s[t]);break;
4896 c2ls_assemble(t,®s[t]);break;
4898 c2op_assemble(t,®s[t]);break;
4900 fconv_assemble(t,®s[t]);break;
4902 float_assemble(t,®s[t]);break;
4904 fcomp_assemble(t,®s[t]);break;
4906 multdiv_assemble(t,®s[t]);break;
4908 mov_assemble(t,®s[t]);break;
4918 printf("Jump in the delay slot. This is probably a bug.\n");
4920 store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4921 load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4922 if(internal_branch(regs[t].is32,ba[i]+4))
4923 assem_debug("branch: internal\n");
4925 assem_debug("branch: external\n");
4926 assert(internal_branch(regs[t].is32,ba[i]+4));
4927 add_to_linker((int)out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4));
4931 void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
4940 //if(ba[i]>=start && ba[i]<(start+slen*4))
4941 if(internal_branch(branch_regs[i].is32,ba[i]))
4943 int t=(ba[i]-start)>>2;
4944 if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
4952 if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4954 if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
4956 //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4957 emit_andimm(HOST_CCREG,3,HOST_CCREG);
4961 else if(*adj==0||invert) {
4962 emit_addimm_and_set_flags(CLOCK_ADJUST(count+2),HOST_CCREG);
4968 emit_cmpimm(HOST_CCREG,-CLOCK_ADJUST(count+2));
4972 add_stub(CC_STUB,jaddr,idle?idle:(int)out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
4975 void do_ccstub(int n)
4978 assem_debug("do_ccstub %x\n",start+stubs[n][4]*4);
4979 set_jump_target(stubs[n][1],(int)out);
4981 if(stubs[n][6]==NULLDS) {
4982 // Delay slot instruction is nullified ("likely" branch)
4983 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
4985 else if(stubs[n][6]!=TAKEN) {
4986 wb_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty);
4989 if(internal_branch(branch_regs[i].is32,ba[i]))
4990 wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4994 // Save PC as return address
4995 emit_movimm(stubs[n][5],EAX);
4996 emit_writeword(EAX,(int)&pcaddr);
5000 // Return address depends on which way the branch goes
5001 if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
5003 int s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5004 int s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5005 int s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5006 int s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5016 if((branch_regs[i].is32>>rs1[i])&(branch_regs[i].is32>>rs2[i])&1) {
5020 #ifdef DESTRUCTIVE_WRITEBACK
5022 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1)
5023 emit_loadreg(rs1[i],s1l);
5026 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1)
5027 emit_loadreg(rs2[i],s1l);
5030 if((branch_regs[i].dirty>>s2l)&(branch_regs[i].is32>>rs2[i])&1)
5031 emit_loadreg(rs2[i],s2l);
5034 int addr=-1,alt=-1,ntaddr=-1;
5037 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5038 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5039 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5047 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5048 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5049 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5055 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
5059 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5060 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5061 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5067 assert(hr<HOST_REGS);
5069 if((opcode[i]&0x2f)==4) // BEQ
5071 #ifdef HAVE_CMOV_IMM
5073 if(s2l>=0) emit_cmp(s1l,s2l);
5074 else emit_test(s1l,s1l);
5075 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
5080 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5082 if(s2h>=0) emit_cmp(s1h,s2h);
5083 else emit_test(s1h,s1h);
5084 emit_cmovne_reg(alt,addr);
5086 if(s2l>=0) emit_cmp(s1l,s2l);
5087 else emit_test(s1l,s1l);
5088 emit_cmovne_reg(alt,addr);
5091 if((opcode[i]&0x2f)==5) // BNE
5093 #ifdef HAVE_CMOV_IMM
5095 if(s2l>=0) emit_cmp(s1l,s2l);
5096 else emit_test(s1l,s1l);
5097 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
5102 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
5104 if(s2h>=0) emit_cmp(s1h,s2h);
5105 else emit_test(s1h,s1h);
5106 emit_cmovne_reg(alt,addr);
5108 if(s2l>=0) emit_cmp(s1l,s2l);
5109 else emit_test(s1l,s1l);
5110 emit_cmovne_reg(alt,addr);
5113 if((opcode[i]&0x2f)==6) // BLEZ
5115 //emit_movimm(ba[i],alt);
5116 //emit_movimm(start+i*4+8,addr);
5117 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5119 if(s1h>=0) emit_mov(addr,ntaddr);
5120 emit_cmovl_reg(alt,addr);
5123 emit_cmovne_reg(ntaddr,addr);
5124 emit_cmovs_reg(alt,addr);
5127 if((opcode[i]&0x2f)==7) // BGTZ
5129 //emit_movimm(ba[i],addr);
5130 //emit_movimm(start+i*4+8,ntaddr);
5131 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
5133 if(s1h>=0) emit_mov(addr,alt);
5134 emit_cmovl_reg(ntaddr,addr);
5137 emit_cmovne_reg(alt,addr);
5138 emit_cmovs_reg(ntaddr,addr);
5141 if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ
5143 //emit_movimm(ba[i],alt);
5144 //emit_movimm(start+i*4+8,addr);
5145 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5146 if(s1h>=0) emit_test(s1h,s1h);
5147 else emit_test(s1l,s1l);
5148 emit_cmovs_reg(alt,addr);
5150 if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ
5152 //emit_movimm(ba[i],addr);
5153 //emit_movimm(start+i*4+8,alt);
5154 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5155 if(s1h>=0) emit_test(s1h,s1h);
5156 else emit_test(s1l,s1l);
5157 emit_cmovs_reg(alt,addr);
5159 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
5160 if(source[i]&0x10000) // BC1T
5162 //emit_movimm(ba[i],alt);
5163 //emit_movimm(start+i*4+8,addr);
5164 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5165 emit_testimm(s1l,0x800000);
5166 emit_cmovne_reg(alt,addr);
5170 //emit_movimm(ba[i],addr);
5171 //emit_movimm(start+i*4+8,alt);
5172 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5173 emit_testimm(s1l,0x800000);
5174 emit_cmovne_reg(alt,addr);
5177 emit_writeword(addr,(int)&pcaddr);
5182 int r=get_reg(branch_regs[i].regmap,rs1[i]);
5183 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5184 r=get_reg(branch_regs[i].regmap,RTEMP);
5186 emit_writeword(r,(int)&pcaddr);
5188 else {printf("Unknown branch type in do_ccstub\n");exit(1);}
5190 // Update cycle count
5191 assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
5192 if(stubs[n][3]) emit_addimm(HOST_CCREG,CLOCK_ADJUST((int)stubs[n][3]),HOST_CCREG);
5193 emit_call((int)cc_interrupt);
5194 if(stubs[n][3]) emit_addimm(HOST_CCREG,-CLOCK_ADJUST((int)stubs[n][3]),HOST_CCREG);
5195 if(stubs[n][6]==TAKEN) {
5196 if(internal_branch(branch_regs[i].is32,ba[i]))
5197 load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
5198 else if(itype[i]==RJUMP) {
5199 if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
5200 emit_readword((int)&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
5202 emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i]));
5204 }else if(stubs[n][6]==NOTTAKEN) {
5205 if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5206 else load_all_regs(branch_regs[i].regmap);
5207 }else if(stubs[n][6]==NULLDS) {
5208 // Delay slot instruction is nullified ("likely" branch)
5209 if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
5210 else load_all_regs(regs[i].regmap);
5212 load_all_regs(branch_regs[i].regmap);
5214 emit_jmp(stubs[n][2]); // return address
5216 /* This works but uses a lot of memory...
5217 emit_readword((int)&last_count,ECX);
5218 emit_add(HOST_CCREG,ECX,EAX);
5219 emit_writeword(EAX,(int)&Count);
5220 emit_call((int)gen_interupt);
5221 emit_readword((int)&Count,HOST_CCREG);
5222 emit_readword((int)&next_interupt,EAX);
5223 emit_readword((int)&pending_exception,EBX);
5224 emit_writeword(EAX,(int)&last_count);
5225 emit_sub(HOST_CCREG,EAX,HOST_CCREG);
5227 int jne_instr=(int)out;
5229 if(stubs[n][3]) emit_addimm(HOST_CCREG,-2*stubs[n][3],HOST_CCREG);
5230 load_all_regs(branch_regs[i].regmap);
5231 emit_jmp(stubs[n][2]); // return address
5232 set_jump_target(jne_instr,(int)out);
5233 emit_readword((int)&pcaddr,EAX);
5234 // Call get_addr_ht instead of doing the hash table here.
5235 // This code is executed infrequently and takes up a lot of space
5236 // so smaller is better.
5237 emit_storereg(CCREG,HOST_CCREG);
5239 emit_call((int)get_addr_ht);
5240 emit_loadreg(CCREG,HOST_CCREG);
5241 emit_addimm(ESP,4,ESP);
5245 add_to_linker(int addr,int target,int ext)
5247 link_addr[linkcount][0]=addr;
5248 link_addr[linkcount][1]=target;
5249 link_addr[linkcount][2]=ext;
5253 static void ujump_assemble_write_ra(int i)
5256 unsigned int return_address;
5257 rt=get_reg(branch_regs[i].regmap,31);
5258 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5260 return_address=start+i*4+8;
5263 if(internal_branch(branch_regs[i].is32,return_address)&&rt1[i+1]!=31) {
5264 int temp=-1; // note: must be ds-safe
5268 if(temp>=0) do_miniht_insert(return_address,rt,temp);
5269 else emit_movimm(return_address,rt);
5277 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5280 emit_movimm(return_address,rt); // PC into link register
5282 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5288 void ujump_assemble(int i,struct regstat *i_regs)
5290 signed char *i_regmap=i_regs->regmap;
5292 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5293 address_generation(i+1,i_regs,regs[i].regmap_entry);
5295 int temp=get_reg(branch_regs[i].regmap,PTEMP);
5296 if(rt1[i]==31&&temp>=0)
5298 int return_address=start+i*4+8;
5299 if(get_reg(branch_regs[i].regmap,31)>0)
5300 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5303 if(rt1[i]==31&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
5304 ujump_assemble_write_ra(i); // writeback ra for DS
5307 ds_assemble(i+1,i_regs);
5308 uint64_t bc_unneeded=branch_regs[i].u;
5309 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5310 bc_unneeded|=1|(1LL<<rt1[i]);
5311 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5312 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5313 bc_unneeded,bc_unneeded_upper);
5314 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5315 if(!ra_done&&rt1[i]==31)
5316 ujump_assemble_write_ra(i);
5318 cc=get_reg(branch_regs[i].regmap,CCREG);
5319 assert(cc==HOST_CCREG);
5320 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5322 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5324 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5325 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5326 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5327 if(internal_branch(branch_regs[i].is32,ba[i]))
5328 assem_debug("branch: internal\n");
5330 assem_debug("branch: external\n");
5331 if(internal_branch(branch_regs[i].is32,ba[i])&&is_ds[(ba[i]-start)>>2]) {
5332 ds_assemble_entry(i);
5335 add_to_linker((int)out,ba[i],internal_branch(branch_regs[i].is32,ba[i]));
5340 static void rjump_assemble_write_ra(int i)
5342 int rt,return_address;
5343 assert(rt1[i+1]!=rt1[i]);
5344 assert(rt2[i+1]!=rt1[i]);
5345 rt=get_reg(branch_regs[i].regmap,rt1[i]);
5346 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5348 return_address=start+i*4+8;
5352 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5355 emit_movimm(return_address,rt); // PC into link register
5357 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5361 void rjump_assemble(int i,struct regstat *i_regs)
5363 signed char *i_regmap=i_regs->regmap;
5367 rs=get_reg(branch_regs[i].regmap,rs1[i]);
5369 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5370 // Delay slot abuse, make a copy of the branch address register
5371 temp=get_reg(branch_regs[i].regmap,RTEMP);
5373 assert(regs[i].regmap[temp]==RTEMP);
5377 address_generation(i+1,i_regs,regs[i].regmap_entry);
5381 if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5382 int return_address=start+i*4+8;
5383 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5389 int rh=get_reg(regs[i].regmap,RHASH);
5390 if(rh>=0) do_preload_rhash(rh);
5393 if(rt1[i]!=0&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
5394 rjump_assemble_write_ra(i);
5397 ds_assemble(i+1,i_regs);
5398 uint64_t bc_unneeded=branch_regs[i].u;
5399 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5400 bc_unneeded|=1|(1LL<<rt1[i]);
5401 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5402 bc_unneeded&=~(1LL<<rs1[i]);
5403 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5404 bc_unneeded,bc_unneeded_upper);
5405 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
5406 if(!ra_done&&rt1[i]!=0)
5407 rjump_assemble_write_ra(i);
5408 cc=get_reg(branch_regs[i].regmap,CCREG);
5409 assert(cc==HOST_CCREG);
5411 int rh=get_reg(branch_regs[i].regmap,RHASH);
5412 int ht=get_reg(branch_regs[i].regmap,RHTBL);
5414 if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5415 do_preload_rhtbl(ht);
5419 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5420 #ifdef DESTRUCTIVE_WRITEBACK
5421 if((branch_regs[i].dirty>>rs)&(branch_regs[i].is32>>rs1[i])&1) {
5422 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
5423 emit_loadreg(rs1[i],rs);
5428 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5432 do_miniht_load(ht,rh);
5435 //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5436 //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5438 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
5439 add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
5441 if(itype[i+1]==COP0&&(source[i+1]&0x3f)==0x10)
5442 // special case for RFE
5447 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5450 do_miniht_jump(rs,rh,ht);
5455 //if(rs!=EAX) emit_mov(rs,EAX);
5456 //emit_jmp((int)jump_vaddr_eax);
5457 emit_jmp(jump_vaddr_reg[rs]);
5462 emit_shrimm(rs,16,rs);
5463 emit_xor(temp,rs,rs);
5464 emit_movzwl_reg(rs,rs);
5465 emit_shlimm(rs,4,rs);
5466 emit_cmpmem_indexed((int)hash_table,rs,temp);
5467 emit_jne((int)out+14);
5468 emit_readword_indexed((int)hash_table+4,rs,rs);
5470 emit_cmpmem_indexed((int)hash_table+8,rs,temp);
5471 emit_addimm_no_flags(8,rs);
5472 emit_jeq((int)out-17);
5473 // No hit on hash table, call compiler
5476 #ifdef DEBUG_CYCLE_COUNT
5477 emit_readword((int)&last_count,ECX);
5478 emit_add(HOST_CCREG,ECX,HOST_CCREG);
5479 emit_readword((int)&next_interupt,ECX);
5480 emit_writeword(HOST_CCREG,(int)&Count);
5481 emit_sub(HOST_CCREG,ECX,HOST_CCREG);
5482 emit_writeword(ECX,(int)&last_count);
5485 emit_storereg(CCREG,HOST_CCREG);
5486 emit_call((int)get_addr);
5487 emit_loadreg(CCREG,HOST_CCREG);
5488 emit_addimm(ESP,4,ESP);
5490 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5491 if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5495 void cjump_assemble(int i,struct regstat *i_regs)
5497 signed char *i_regmap=i_regs->regmap;
5500 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5501 assem_debug("match=%d\n",match);
5502 int s1h,s1l,s2h,s2l;
5503 int prev_cop1_usable=cop1_usable;
5504 int unconditional=0,nop=0;
5507 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5508 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5509 if(!match) invert=1;
5510 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5511 if(i>(ba[i]-start)>>2) invert=1;
5515 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5516 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5517 s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5518 s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5521 s1l=get_reg(i_regmap,rs1[i]);
5522 s1h=get_reg(i_regmap,rs1[i]|64);
5523 s2l=get_reg(i_regmap,rs2[i]);
5524 s2h=get_reg(i_regmap,rs2[i]|64);
5526 if(rs1[i]==0&&rs2[i]==0)
5528 if(opcode[i]&1) nop=1;
5529 else unconditional=1;
5530 //assert(opcode[i]!=5);
5531 //assert(opcode[i]!=7);
5532 //assert(opcode[i]!=0x15);
5533 //assert(opcode[i]!=0x17);
5539 only32=(regs[i].was32>>rs2[i])&1;
5544 only32=(regs[i].was32>>rs1[i])&1;
5547 only32=(regs[i].was32>>rs1[i])&(regs[i].was32>>rs2[i])&1;
5551 // Out of order execution (delay slot first)
5553 address_generation(i+1,i_regs,regs[i].regmap_entry);
5554 ds_assemble(i+1,i_regs);
5556 uint64_t bc_unneeded=branch_regs[i].u;
5557 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5558 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5559 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5561 bc_unneeded_upper|=1;
5562 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5563 bc_unneeded,bc_unneeded_upper);
5564 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
5565 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5566 cc=get_reg(branch_regs[i].regmap,CCREG);
5567 assert(cc==HOST_CCREG);
5569 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5570 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5571 //assem_debug("cycle count (adj)\n");
5573 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5574 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5575 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5576 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5578 assem_debug("branch: internal\n");
5580 assem_debug("branch: external\n");
5581 if(internal&&is_ds[(ba[i]-start)>>2]) {
5582 ds_assemble_entry(i);
5585 add_to_linker((int)out,ba[i],internal);
5588 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5589 if(((u_int)out)&7) emit_addnop(0);
5594 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5597 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5600 int taken=0,nottaken=0,nottaken1=0;
5601 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5602 if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5606 if(opcode[i]==4) // BEQ
5608 if(s2h>=0) emit_cmp(s1h,s2h);
5609 else emit_test(s1h,s1h);
5613 if(opcode[i]==5) // BNE
5615 if(s2h>=0) emit_cmp(s1h,s2h);
5616 else emit_test(s1h,s1h);
5617 if(invert) taken=(int)out;
5618 else add_to_linker((int)out,ba[i],internal);
5621 if(opcode[i]==6) // BLEZ
5624 if(invert) taken=(int)out;
5625 else add_to_linker((int)out,ba[i],internal);
5630 if(opcode[i]==7) // BGTZ
5635 if(invert) taken=(int)out;
5636 else add_to_linker((int)out,ba[i],internal);
5641 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5643 if(opcode[i]==4) // BEQ
5645 if(s2l>=0) emit_cmp(s1l,s2l);
5646 else emit_test(s1l,s1l);
5651 add_to_linker((int)out,ba[i],internal);
5655 if(opcode[i]==5) // BNE
5657 if(s2l>=0) emit_cmp(s1l,s2l);
5658 else emit_test(s1l,s1l);
5663 add_to_linker((int)out,ba[i],internal);
5667 if(opcode[i]==6) // BLEZ
5674 add_to_linker((int)out,ba[i],internal);
5678 if(opcode[i]==7) // BGTZ
5685 add_to_linker((int)out,ba[i],internal);
5690 if(taken) set_jump_target(taken,(int)out);
5691 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5692 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5694 emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
5695 add_to_linker((int)out,ba[i],internal);
5698 add_to_linker((int)out,ba[i],internal*2);
5704 if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
5705 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5706 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5708 assem_debug("branch: internal\n");
5710 assem_debug("branch: external\n");
5711 if(internal&&is_ds[(ba[i]-start)>>2]) {
5712 ds_assemble_entry(i);
5715 add_to_linker((int)out,ba[i],internal);
5719 set_jump_target(nottaken,(int)out);
5722 if(nottaken1) set_jump_target(nottaken1,(int)out);
5724 if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
5726 } // (!unconditional)
5730 // In-order execution (branch first)
5731 //if(likely[i]) printf("IOL\n");
5734 int taken=0,nottaken=0,nottaken1=0;
5735 if(!unconditional&&!nop) {
5739 if((opcode[i]&0x2f)==4) // BEQ
5741 if(s2h>=0) emit_cmp(s1h,s2h);
5742 else emit_test(s1h,s1h);
5746 if((opcode[i]&0x2f)==5) // BNE
5748 if(s2h>=0) emit_cmp(s1h,s2h);
5749 else emit_test(s1h,s1h);
5753 if((opcode[i]&0x2f)==6) // BLEZ
5761 if((opcode[i]&0x2f)==7) // BGTZ
5771 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5773 if((opcode[i]&0x2f)==4) // BEQ
5775 if(s2l>=0) emit_cmp(s1l,s2l);
5776 else emit_test(s1l,s1l);
5780 if((opcode[i]&0x2f)==5) // BNE
5782 if(s2l>=0) emit_cmp(s1l,s2l);
5783 else emit_test(s1l,s1l);
5787 if((opcode[i]&0x2f)==6) // BLEZ
5793 if((opcode[i]&0x2f)==7) // BGTZ
5799 } // if(!unconditional)
5801 uint64_t ds_unneeded=branch_regs[i].u;
5802 uint64_t ds_unneeded_upper=branch_regs[i].uu;
5803 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5804 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5805 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5807 ds_unneeded_upper|=1;
5810 if(taken) set_jump_target(taken,(int)out);
5811 assem_debug("1:\n");
5812 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5813 ds_unneeded,ds_unneeded_upper);
5815 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5816 address_generation(i+1,&branch_regs[i],0);
5817 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5818 ds_assemble(i+1,&branch_regs[i]);
5819 cc=get_reg(branch_regs[i].regmap,CCREG);
5821 emit_loadreg(CCREG,cc=HOST_CCREG);
5822 // CHECK: Is the following instruction (fall thru) allocated ok?
5824 assert(cc==HOST_CCREG);
5825 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5826 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5827 assem_debug("cycle count (adj)\n");
5828 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5829 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5831 assem_debug("branch: internal\n");
5833 assem_debug("branch: external\n");
5834 if(internal&&is_ds[(ba[i]-start)>>2]) {
5835 ds_assemble_entry(i);
5838 add_to_linker((int)out,ba[i],internal);
5843 cop1_usable=prev_cop1_usable;
5844 if(!unconditional) {
5845 if(nottaken1) set_jump_target(nottaken1,(int)out);
5846 set_jump_target(nottaken,(int)out);
5847 assem_debug("2:\n");
5849 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5850 ds_unneeded,ds_unneeded_upper);
5851 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5852 address_generation(i+1,&branch_regs[i],0);
5853 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5854 ds_assemble(i+1,&branch_regs[i]);
5856 cc=get_reg(branch_regs[i].regmap,CCREG);
5857 if(cc==-1&&!likely[i]) {
5858 // Cycle count isn't in a register, temporarily load it then write it out
5859 emit_loadreg(CCREG,HOST_CCREG);
5860 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
5863 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5864 emit_storereg(CCREG,HOST_CCREG);
5867 cc=get_reg(i_regmap,CCREG);
5868 assert(cc==HOST_CCREG);
5869 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5872 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5878 void sjump_assemble(int i,struct regstat *i_regs)
5880 signed char *i_regmap=i_regs->regmap;
5883 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5884 assem_debug("smatch=%d\n",match);
5886 int prev_cop1_usable=cop1_usable;
5887 int unconditional=0,nevertaken=0;
5890 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5891 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5892 if(!match) invert=1;
5893 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5894 if(i>(ba[i]-start)>>2) invert=1;
5897 //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
5898 //assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
5901 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5902 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5905 s1l=get_reg(i_regmap,rs1[i]);
5906 s1h=get_reg(i_regmap,rs1[i]|64);
5910 if(opcode2[i]&1) unconditional=1;
5912 // These are never taken (r0 is never less than zero)
5913 //assert(opcode2[i]!=0);
5914 //assert(opcode2[i]!=2);
5915 //assert(opcode2[i]!=0x10);
5916 //assert(opcode2[i]!=0x12);
5919 only32=(regs[i].was32>>rs1[i])&1;
5923 // Out of order execution (delay slot first)
5925 address_generation(i+1,i_regs,regs[i].regmap_entry);
5926 ds_assemble(i+1,i_regs);
5928 uint64_t bc_unneeded=branch_regs[i].u;
5929 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5930 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5931 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5933 bc_unneeded_upper|=1;
5934 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5935 bc_unneeded,bc_unneeded_upper);
5936 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5937 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5939 int rt,return_address;
5940 rt=get_reg(branch_regs[i].regmap,31);
5941 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5943 // Save the PC even if the branch is not taken
5944 return_address=start+i*4+8;
5945 emit_movimm(return_address,rt); // PC into link register
5947 if(!nevertaken) emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5951 cc=get_reg(branch_regs[i].regmap,CCREG);
5952 assert(cc==HOST_CCREG);
5954 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5955 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5956 assem_debug("cycle count (adj)\n");
5958 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5959 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5960 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5961 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5963 assem_debug("branch: internal\n");
5965 assem_debug("branch: external\n");
5966 if(internal&&is_ds[(ba[i]-start)>>2]) {
5967 ds_assemble_entry(i);
5970 add_to_linker((int)out,ba[i],internal);
5973 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5974 if(((u_int)out)&7) emit_addnop(0);
5978 else if(nevertaken) {
5979 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5982 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5986 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5987 if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5991 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
5998 add_to_linker((int)out,ba[i],internal);
6002 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
6009 add_to_linker((int)out,ba[i],internal);
6017 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
6024 add_to_linker((int)out,ba[i],internal);
6028 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
6035 add_to_linker((int)out,ba[i],internal);
6042 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6043 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
6045 emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
6046 add_to_linker((int)out,ba[i],internal);
6049 add_to_linker((int)out,ba[i],internal*2);
6055 if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
6056 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6057 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6059 assem_debug("branch: internal\n");
6061 assem_debug("branch: external\n");
6062 if(internal&&is_ds[(ba[i]-start)>>2]) {
6063 ds_assemble_entry(i);
6066 add_to_linker((int)out,ba[i],internal);
6070 set_jump_target(nottaken,(int)out);
6074 if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
6076 } // (!unconditional)
6080 // In-order execution (branch first)
6084 int rt,return_address;
6085 rt=get_reg(branch_regs[i].regmap,31);
6087 // Save the PC even if the branch is not taken
6088 return_address=start+i*4+8;
6089 emit_movimm(return_address,rt); // PC into link register
6091 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
6095 if(!unconditional) {
6096 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6100 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
6106 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
6116 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
6122 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
6129 } // if(!unconditional)
6131 uint64_t ds_unneeded=branch_regs[i].u;
6132 uint64_t ds_unneeded_upper=branch_regs[i].uu;
6133 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6134 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6135 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6137 ds_unneeded_upper|=1;
6140 //assem_debug("1:\n");
6141 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6142 ds_unneeded,ds_unneeded_upper);
6144 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6145 address_generation(i+1,&branch_regs[i],0);
6146 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6147 ds_assemble(i+1,&branch_regs[i]);
6148 cc=get_reg(branch_regs[i].regmap,CCREG);
6150 emit_loadreg(CCREG,cc=HOST_CCREG);
6151 // CHECK: Is the following instruction (fall thru) allocated ok?
6153 assert(cc==HOST_CCREG);
6154 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6155 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6156 assem_debug("cycle count (adj)\n");
6157 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6158 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6160 assem_debug("branch: internal\n");
6162 assem_debug("branch: external\n");
6163 if(internal&&is_ds[(ba[i]-start)>>2]) {
6164 ds_assemble_entry(i);
6167 add_to_linker((int)out,ba[i],internal);
6172 cop1_usable=prev_cop1_usable;
6173 if(!unconditional) {
6174 set_jump_target(nottaken,(int)out);
6175 assem_debug("1:\n");
6177 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6178 ds_unneeded,ds_unneeded_upper);
6179 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6180 address_generation(i+1,&branch_regs[i],0);
6181 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6182 ds_assemble(i+1,&branch_regs[i]);
6184 cc=get_reg(branch_regs[i].regmap,CCREG);
6185 if(cc==-1&&!likely[i]) {
6186 // Cycle count isn't in a register, temporarily load it then write it out
6187 emit_loadreg(CCREG,HOST_CCREG);
6188 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
6191 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6192 emit_storereg(CCREG,HOST_CCREG);
6195 cc=get_reg(i_regmap,CCREG);
6196 assert(cc==HOST_CCREG);
6197 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
6200 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6206 void fjump_assemble(int i,struct regstat *i_regs)
6208 signed char *i_regmap=i_regs->regmap;
6211 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6212 assem_debug("fmatch=%d\n",match);
6216 int internal=internal_branch(branch_regs[i].is32,ba[i]);
6217 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
6218 if(!match) invert=1;
6219 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6220 if(i>(ba[i]-start)>>2) invert=1;
6224 fs=get_reg(branch_regs[i].regmap,FSREG);
6225 address_generation(i+1,i_regs,regs[i].regmap_entry); // Is this okay?
6228 fs=get_reg(i_regmap,FSREG);
6231 // Check cop1 unusable
6233 cs=get_reg(i_regmap,CSREG);
6235 emit_testimm(cs,0x20000000);
6238 add_stub(FP_STUB,eaddr,(int)out,i,cs,(int)i_regs,0,0);
6243 // Out of order execution (delay slot first)
6245 ds_assemble(i+1,i_regs);
6247 uint64_t bc_unneeded=branch_regs[i].u;
6248 uint64_t bc_unneeded_upper=branch_regs[i].uu;
6249 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6250 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
6252 bc_unneeded_upper|=1;
6253 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6254 bc_unneeded,bc_unneeded_upper);
6255 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
6256 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6257 cc=get_reg(branch_regs[i].regmap,CCREG);
6258 assert(cc==HOST_CCREG);
6259 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
6260 assem_debug("cycle count (adj)\n");
6263 if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6266 emit_testimm(fs,0x800000);
6267 if(source[i]&0x10000) // BC1T
6273 add_to_linker((int)out,ba[i],internal);
6282 add_to_linker((int)out,ba[i],internal);
6290 if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
6291 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6292 else if(match) emit_addnop(13);
6294 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6295 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6297 assem_debug("branch: internal\n");
6299 assem_debug("branch: external\n");
6300 if(internal&&is_ds[(ba[i]-start)>>2]) {
6301 ds_assemble_entry(i);
6304 add_to_linker((int)out,ba[i],internal);
6307 set_jump_target(nottaken,(int)out);
6311 if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
6313 } // (!unconditional)
6317 // In-order execution (branch first)
6321 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6324 emit_testimm(fs,0x800000);
6325 if(source[i]&0x10000) // BC1T
6336 } // if(!unconditional)
6338 uint64_t ds_unneeded=branch_regs[i].u;
6339 uint64_t ds_unneeded_upper=branch_regs[i].uu;
6340 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6341 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6342 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6344 ds_unneeded_upper|=1;
6346 //assem_debug("1:\n");
6347 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6348 ds_unneeded,ds_unneeded_upper);
6350 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6351 address_generation(i+1,&branch_regs[i],0);
6352 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6353 ds_assemble(i+1,&branch_regs[i]);
6354 cc=get_reg(branch_regs[i].regmap,CCREG);
6356 emit_loadreg(CCREG,cc=HOST_CCREG);
6357 // CHECK: Is the following instruction (fall thru) allocated ok?
6359 assert(cc==HOST_CCREG);
6360 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6361 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6362 assem_debug("cycle count (adj)\n");
6363 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6364 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6366 assem_debug("branch: internal\n");
6368 assem_debug("branch: external\n");
6369 if(internal&&is_ds[(ba[i]-start)>>2]) {
6370 ds_assemble_entry(i);
6373 add_to_linker((int)out,ba[i],internal);
6378 if(1) { // <- FIXME (don't need this)
6379 set_jump_target(nottaken,(int)out);
6380 assem_debug("1:\n");
6382 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6383 ds_unneeded,ds_unneeded_upper);
6384 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6385 address_generation(i+1,&branch_regs[i],0);
6386 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6387 ds_assemble(i+1,&branch_regs[i]);
6389 cc=get_reg(branch_regs[i].regmap,CCREG);
6390 if(cc==-1&&!likely[i]) {
6391 // Cycle count isn't in a register, temporarily load it then write it out
6392 emit_loadreg(CCREG,HOST_CCREG);
6393 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
6396 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6397 emit_storereg(CCREG,HOST_CCREG);
6400 cc=get_reg(i_regmap,CCREG);
6401 assert(cc==HOST_CCREG);
6402 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
6405 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6411 static void pagespan_assemble(int i,struct regstat *i_regs)
6413 int s1l=get_reg(i_regs->regmap,rs1[i]);
6414 int s1h=get_reg(i_regs->regmap,rs1[i]|64);
6415 int s2l=get_reg(i_regs->regmap,rs2[i]);
6416 int s2h=get_reg(i_regs->regmap,rs2[i]|64);
6417 void *nt_branch=NULL;
6420 int unconditional=0;
6430 if((i_regs->is32>>rs1[i])&(i_regs->is32>>rs2[i])&1) {
6434 int addr,alt,ntaddr;
6435 if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
6439 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
6440 (i_regs->regmap[hr]&63)!=rs1[i] &&
6441 (i_regs->regmap[hr]&63)!=rs2[i] )
6450 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6451 (i_regs->regmap[hr]&63)!=rs1[i] &&
6452 (i_regs->regmap[hr]&63)!=rs2[i] )
6458 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
6462 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6463 (i_regs->regmap[hr]&63)!=rs1[i] &&
6464 (i_regs->regmap[hr]&63)!=rs2[i] )
6471 assert(hr<HOST_REGS);
6472 if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
6473 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
6475 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
6476 if(opcode[i]==2) // J
6480 if(opcode[i]==3) // JAL
6483 int rt=get_reg(i_regs->regmap,31);
6484 emit_movimm(start+i*4+8,rt);
6487 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
6490 if(opcode2[i]==9) // JALR
6492 int rt=get_reg(i_regs->regmap,rt1[i]);
6493 emit_movimm(start+i*4+8,rt);
6496 if((opcode[i]&0x3f)==4) // BEQ
6503 #ifdef HAVE_CMOV_IMM
6505 if(s2l>=0) emit_cmp(s1l,s2l);
6506 else emit_test(s1l,s1l);
6507 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
6513 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6515 if(s2h>=0) emit_cmp(s1h,s2h);
6516 else emit_test(s1h,s1h);
6517 emit_cmovne_reg(alt,addr);
6519 if(s2l>=0) emit_cmp(s1l,s2l);
6520 else emit_test(s1l,s1l);
6521 emit_cmovne_reg(alt,addr);
6524 if((opcode[i]&0x3f)==5) // BNE
6526 #ifdef HAVE_CMOV_IMM
6528 if(s2l>=0) emit_cmp(s1l,s2l);
6529 else emit_test(s1l,s1l);
6530 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
6536 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
6538 if(s2h>=0) emit_cmp(s1h,s2h);
6539 else emit_test(s1h,s1h);
6540 emit_cmovne_reg(alt,addr);
6542 if(s2l>=0) emit_cmp(s1l,s2l);
6543 else emit_test(s1l,s1l);
6544 emit_cmovne_reg(alt,addr);
6547 if((opcode[i]&0x3f)==0x14) // BEQL
6550 if(s2h>=0) emit_cmp(s1h,s2h);
6551 else emit_test(s1h,s1h);
6555 if(s2l>=0) emit_cmp(s1l,s2l);
6556 else emit_test(s1l,s1l);
6557 if(nottaken) set_jump_target(nottaken,(int)out);
6561 if((opcode[i]&0x3f)==0x15) // BNEL
6564 if(s2h>=0) emit_cmp(s1h,s2h);
6565 else emit_test(s1h,s1h);
6569 if(s2l>=0) emit_cmp(s1l,s2l);
6570 else emit_test(s1l,s1l);
6573 if(taken) set_jump_target(taken,(int)out);
6575 if((opcode[i]&0x3f)==6) // BLEZ
6577 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6579 if(s1h>=0) emit_mov(addr,ntaddr);
6580 emit_cmovl_reg(alt,addr);
6583 emit_cmovne_reg(ntaddr,addr);
6584 emit_cmovs_reg(alt,addr);
6587 if((opcode[i]&0x3f)==7) // BGTZ
6589 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
6591 if(s1h>=0) emit_mov(addr,alt);
6592 emit_cmovl_reg(ntaddr,addr);
6595 emit_cmovne_reg(alt,addr);
6596 emit_cmovs_reg(ntaddr,addr);
6599 if((opcode[i]&0x3f)==0x16) // BLEZL
6601 assert((opcode[i]&0x3f)!=0x16);
6603 if((opcode[i]&0x3f)==0x17) // BGTZL
6605 assert((opcode[i]&0x3f)!=0x17);
6607 assert(opcode[i]!=1); // BLTZ/BGEZ
6609 //FIXME: Check CSREG
6610 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
6611 if((source[i]&0x30000)==0) // BC1F
6613 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6614 emit_testimm(s1l,0x800000);
6615 emit_cmovne_reg(alt,addr);
6617 if((source[i]&0x30000)==0x10000) // BC1T
6619 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6620 emit_testimm(s1l,0x800000);
6621 emit_cmovne_reg(alt,addr);
6623 if((source[i]&0x30000)==0x20000) // BC1FL
6625 emit_testimm(s1l,0x800000);
6629 if((source[i]&0x30000)==0x30000) // BC1TL
6631 emit_testimm(s1l,0x800000);
6637 assert(i_regs->regmap[HOST_CCREG]==CCREG);
6638 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6639 if(likely[i]||unconditional)
6641 emit_movimm(ba[i],HOST_BTREG);
6643 else if(addr!=HOST_BTREG)
6645 emit_mov(addr,HOST_BTREG);
6647 void *branch_addr=out;
6649 int target_addr=start+i*4+5;
6651 void *compiled_target_addr=check_addr(target_addr);
6652 emit_extjump_ds((int)branch_addr,target_addr);
6653 if(compiled_target_addr) {
6654 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6655 add_link(target_addr,stub);
6657 else set_jump_target((int)branch_addr,(int)stub);
6660 set_jump_target((int)nottaken,(int)out);
6661 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6662 void *branch_addr=out;
6664 int target_addr=start+i*4+8;
6666 void *compiled_target_addr=check_addr(target_addr);
6667 emit_extjump_ds((int)branch_addr,target_addr);
6668 if(compiled_target_addr) {
6669 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6670 add_link(target_addr,stub);
6672 else set_jump_target((int)branch_addr,(int)stub);
6676 // Assemble the delay slot for the above
6677 static void pagespan_ds()
6679 assem_debug("initial delay slot:\n");
6680 u_int vaddr=start+1;
6681 u_int page=get_page(vaddr);
6682 u_int vpage=get_vpage(vaddr);
6683 ll_add(jump_dirty+vpage,vaddr,(void *)out);
6685 ll_add(jump_in+page,vaddr,(void *)out);
6686 assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6687 if(regs[0].regmap[HOST_CCREG]!=CCREG)
6688 wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty,regs[0].was32);
6689 if(regs[0].regmap[HOST_BTREG]!=BTREG)
6690 emit_writeword(HOST_BTREG,(int)&branch_target);
6691 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,rs1[0],rs2[0]);
6692 address_generation(0,®s[0],regs[0].regmap_entry);
6693 if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39||(opcode[0]&0x3b)==0x3a)
6694 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,INVCP,INVCP);
6699 alu_assemble(0,®s[0]);break;
6701 imm16_assemble(0,®s[0]);break;
6703 shift_assemble(0,®s[0]);break;
6705 shiftimm_assemble(0,®s[0]);break;
6707 load_assemble(0,®s[0]);break;
6709 loadlr_assemble(0,®s[0]);break;
6711 store_assemble(0,®s[0]);break;
6713 storelr_assemble(0,®s[0]);break;
6715 cop0_assemble(0,®s[0]);break;
6717 cop1_assemble(0,®s[0]);break;
6719 c1ls_assemble(0,®s[0]);break;
6721 cop2_assemble(0,®s[0]);break;
6723 c2ls_assemble(0,®s[0]);break;
6725 c2op_assemble(0,®s[0]);break;
6727 fconv_assemble(0,®s[0]);break;
6729 float_assemble(0,®s[0]);break;
6731 fcomp_assemble(0,®s[0]);break;
6733 multdiv_assemble(0,®s[0]);break;
6735 mov_assemble(0,®s[0]);break;
6745 printf("Jump in the delay slot. This is probably a bug.\n");
6747 int btaddr=get_reg(regs[0].regmap,BTREG);
6749 btaddr=get_reg(regs[0].regmap,-1);
6750 emit_readword((int)&branch_target,btaddr);
6752 assert(btaddr!=HOST_CCREG);
6753 if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6755 emit_movimm(start+4,HOST_TEMPREG);
6756 emit_cmp(btaddr,HOST_TEMPREG);
6758 emit_cmpimm(btaddr,start+4);
6760 int branch=(int)out;
6762 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,-1);
6763 emit_jmp(jump_vaddr_reg[btaddr]);
6764 set_jump_target(branch,(int)out);
6765 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6766 load_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6769 // Basic liveness analysis for MIPS registers
6770 void unneeded_registers(int istart,int iend,int r)
6773 uint64_t u,uu,gte_u,b,bu,gte_bu;
6774 uint64_t temp_u,temp_uu,temp_gte_u=0;
6776 uint64_t gte_u_unknown=0;
6777 if(new_dynarec_hacks&NDHACK_GTE_UNNEEDED)
6781 gte_u=gte_u_unknown;
6783 u=unneeded_reg[iend+1];
6784 uu=unneeded_reg_upper[iend+1];
6786 gte_u=gte_unneeded[iend+1];
6789 for (i=iend;i>=istart;i--)
6791 //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
6792 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6794 // If subroutine call, flag return address as a possible branch target
6795 if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
6797 if(ba[i]<start || ba[i]>=(start+slen*4))
6799 // Branch out of this block, flush all regs
6802 gte_u=gte_u_unknown;
6804 if(itype[i]==UJUMP&&rt1[i]==31)
6806 uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
6808 if(itype[i]==RJUMP&&rs1[i]==31)
6810 uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9
6812 if(start>0x80000400&&start<0x80000000+RAM_SIZE) {
6813 if(itype[i]==UJUMP&&rt1[i]==31)
6815 //uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi
6816 uu=u=0x300FF0F; // Discard at, v0-v1, t0-t9
6818 if(itype[i]==RJUMP&&rs1[i]==31)
6820 //uu=u=0x30300FFF3LL; // Discard at, a0-a3, t0-t9, lo, hi
6821 uu=u=0x300FFF3; // Discard at, a0-a3, t0-t9
6824 branch_unneeded_reg[i]=u;
6825 branch_unneeded_reg_upper[i]=uu;
6826 // Merge in delay slot
6827 tdep=(~uu>>rt1[i+1])&1;
6828 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6829 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6830 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6831 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6832 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6835 gte_u&=~gte_rs[i+1];
6836 // If branch is "likely" (and conditional)
6837 // then we skip the delay slot on the fall-thru path
6840 u&=unneeded_reg[i+2];
6841 uu&=unneeded_reg_upper[i+2];
6842 gte_u&=gte_unneeded[i+2];
6848 gte_u=gte_u_unknown;
6854 // Internal branch, flag target
6855 bt[(ba[i]-start)>>2]=1;
6856 if(ba[i]<=start+i*4) {
6858 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6860 // Unconditional branch
6864 // Conditional branch (not taken case)
6865 temp_u=unneeded_reg[i+2];
6866 temp_uu=unneeded_reg_upper[i+2];
6867 temp_gte_u&=gte_unneeded[i+2];
6869 // Merge in delay slot
6870 tdep=(~temp_uu>>rt1[i+1])&1;
6871 temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6872 temp_uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6873 temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6874 temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6875 temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6876 temp_u|=1;temp_uu|=1;
6877 temp_gte_u|=gte_rt[i+1];
6878 temp_gte_u&=~gte_rs[i+1];
6879 // If branch is "likely" (and conditional)
6880 // then we skip the delay slot on the fall-thru path
6883 temp_u&=unneeded_reg[i+2];
6884 temp_uu&=unneeded_reg_upper[i+2];
6885 temp_gte_u&=gte_unneeded[i+2];
6891 temp_gte_u=gte_u_unknown;
6894 tdep=(~temp_uu>>rt1[i])&1;
6895 temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6896 temp_uu|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6897 temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6898 temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
6899 temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i]));
6900 temp_u|=1;temp_uu|=1;
6901 temp_gte_u|=gte_rt[i];
6902 temp_gte_u&=~gte_rs[i];
6903 unneeded_reg[i]=temp_u;
6904 unneeded_reg_upper[i]=temp_uu;
6905 gte_unneeded[i]=temp_gte_u;
6906 // Only go three levels deep. This recursion can take an
6907 // excessive amount of time if there are a lot of nested loops.
6909 unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6911 unneeded_reg[(ba[i]-start)>>2]=1;
6912 unneeded_reg_upper[(ba[i]-start)>>2]=1;
6913 gte_unneeded[(ba[i]-start)>>2]=gte_u_unknown;
6916 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6918 // Unconditional branch
6919 u=unneeded_reg[(ba[i]-start)>>2];
6920 uu=unneeded_reg_upper[(ba[i]-start)>>2];
6921 gte_u=gte_unneeded[(ba[i]-start)>>2];
6922 branch_unneeded_reg[i]=u;
6923 branch_unneeded_reg_upper[i]=uu;
6926 //branch_unneeded_reg[i]=u;
6927 //branch_unneeded_reg_upper[i]=uu;
6928 // Merge in delay slot
6929 tdep=(~uu>>rt1[i+1])&1;
6930 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6931 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6932 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6933 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6934 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6937 gte_u&=~gte_rs[i+1];
6939 // Conditional branch
6940 b=unneeded_reg[(ba[i]-start)>>2];
6941 bu=unneeded_reg_upper[(ba[i]-start)>>2];
6942 gte_bu=gte_unneeded[(ba[i]-start)>>2];
6943 branch_unneeded_reg[i]=b;
6944 branch_unneeded_reg_upper[i]=bu;
6947 //branch_unneeded_reg[i]=b;
6948 //branch_unneeded_reg_upper[i]=bu;
6949 // Branch delay slot
6950 tdep=(~uu>>rt1[i+1])&1;
6951 b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6952 bu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6953 b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6954 bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6955 bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6957 gte_bu|=gte_rt[i+1];
6958 gte_bu&=~gte_rs[i+1];
6959 // If branch is "likely" then we skip the
6960 // delay slot on the fall-thru path
6966 u&=unneeded_reg[i+2];
6967 uu&=unneeded_reg_upper[i+2];
6968 gte_u&=gte_unneeded[i+2];
6980 branch_unneeded_reg[i]&=unneeded_reg[i+2];
6981 branch_unneeded_reg_upper[i]&=unneeded_reg_upper[i+2];
6982 //branch_unneeded_reg[i]=1;
6983 //branch_unneeded_reg_upper[i]=1;
6985 branch_unneeded_reg[i]=1;
6986 branch_unneeded_reg_upper[i]=1;
6992 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
6994 // SYSCALL instruction (software interrupt)
6998 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7000 // ERET instruction (return from interrupt)
7005 tdep=(~uu>>rt1[i])&1;
7006 // Written registers are unneeded
7012 // Accessed registers are needed
7018 if(gte_rs[i]&&rt1[i]&&(unneeded_reg[i+1]&(1ll<<rt1[i])))
7019 gte_u|=gte_rs[i]; // MFC2/CFC2 to dead register, unneeded
7020 // Source-target dependencies
7021 uu&=~(tdep<<dep1[i]);
7022 uu&=~(tdep<<dep2[i]);
7023 // R0 is always unneeded
7027 unneeded_reg_upper[i]=uu;
7028 gte_unneeded[i]=gte_u;
7030 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
7033 for(r=1;r<=CCREG;r++) {
7034 if((unneeded_reg[i]>>r)&1) {
7035 if(r==HIREG) printf(" HI");
7036 else if(r==LOREG) printf(" LO");
7037 else printf(" r%d",r);
7041 for(r=1;r<=CCREG;r++) {
7042 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
7043 if(r==HIREG) printf(" HI");
7044 else if(r==LOREG) printf(" LO");
7045 else printf(" r%d",r);
7051 for (i=iend;i>=istart;i--)
7053 unneeded_reg_upper[i]=branch_unneeded_reg_upper[i]=-1LL;
7058 // Identify registers which are likely to contain 32-bit values
7059 // This is used to predict whether any branches will jump to a
7060 // location with 64-bit values in registers.
7061 static void provisional_32bit()
7065 uint64_t lastbranch=1;
7070 if(itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) {
7071 if(i>1) is32=lastbranch;
7077 if(itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP) {
7079 if(i>2) is32=lastbranch;
7083 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
7085 if(rs1[i-2]==0||rs2[i-2]==0)
7088 is32|=1LL<<rs1[i-2];
7091 is32|=1LL<<rs2[i-2];
7096 // If something jumps here with 64-bit values
7097 // then promote those registers to 64 bits
7100 uint64_t temp_is32=is32;
7103 if(ba[j]==start+i*4)
7104 //temp_is32&=branch_regs[j].is32;
7109 if(ba[j]==start+i*4)
7120 if(type==UJUMP||type==RJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
7121 // Branches don't write registers, consider the delay slot instead.
7132 if(opcode[i]==0x27||opcode[i]==0x37|| // LWU/LD
7133 opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
7142 if(op==0x1a||op==0x1b) is32&=~(1LL<<rt); // LDR/LDL
7143 if(op==0x22) is32|=1LL<<rt; // LWL
7146 if (op==0x08||op==0x09|| // ADDI/ADDIU
7147 op==0x0a||op==0x0b|| // SLTI/SLTIU
7153 if(op==0x18||op==0x19) { // DADDI/DADDIU
7156 // is32|=((is32>>s1)&1LL)<<rt;
7158 if(op==0x0d||op==0x0e) { // ORI/XORI
7159 uint64_t sr=((is32>>s1)&1LL);
7175 if(op2>=0x20&&op2<=0x23) { // ADD/ADDU/SUB/SUBU
7178 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
7181 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
7182 uint64_t sr=((is32>>s1)&(is32>>s2)&1LL);
7186 else if(op2>=0x2c&&op2<=0x2d) { // DADD/DADDU
7191 uint64_t sr=((is32>>s1)&1LL);
7196 uint64_t sr=((is32>>s2)&1LL);
7204 else if(op2>=0x2e&&op2<=0x2f) { // DSUB/DSUBU
7209 uint64_t sr=((is32>>s1)&1LL);
7219 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
7220 is32&=~((1LL<<HIREG)|(1LL<<LOREG));
7223 is32|=(1LL<<HIREG)|(1LL<<LOREG);
7228 uint64_t sr=((is32>>s1)&1LL);
7234 if(op2>=0x14&&op2<=0x17) is32&=~(1LL<<rt); // DSLLV/DSRLV/DSRAV
7235 else is32|=1LL<<rt; // SLLV/SRLV/SRAV
7239 // DSLL/DSRL/DSRA/DSLL32/DSRL32 but not DSRA32 have 64-bit result
7240 if(op2>=0x38&&op2<0x3f) is32&=~(1LL<<rt);
7243 if(op2==0) is32|=1LL<<rt; // MFC0
7247 if(op2==0) is32|=1LL<<rt; // MFC1
7248 if(op2==1) is32&=~(1LL<<rt); // DMFC1
7249 if(op2==2) is32|=1LL<<rt; // CFC1
7271 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
7273 if(rt1[i-1]==31) // JAL/JALR
7275 // Subroutine call will return here, don't alloc any registers
7280 // Internal branch will jump here, match registers to caller
7288 // Identify registers which may be assumed to contain 32-bit values
7289 // and where optimizations will rely on this.
7290 // This is used to determine whether backward branches can safely
7291 // jump to a location with 64-bit values in registers.
7292 static void provisional_r32()
7297 for (i=slen-1;i>=0;i--)
7300 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7302 if(ba[i]<start || ba[i]>=(start+slen*4))
7304 // Branch out of this block, don't need anything
7310 // Need whatever matches the target
7311 // (and doesn't get overwritten by the delay slot instruction)
7313 int t=(ba[i]-start)>>2;
7314 if(ba[i]>start+i*4) {
7316 //if(!(requires_32bit[t]&~regs[i].was32))
7317 // r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7318 if(!(pr32[t]&~regs[i].was32))
7319 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7322 if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
7323 r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7326 // Conditional branch may need registers for following instructions
7327 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
7330 //r32|=requires_32bit[i+2];
7333 // Mark this address as a branch target since it may be called
7334 // upon return from interrupt
7338 // Merge in delay slot
7340 // These are overwritten unless the branch is "likely"
7341 // and the delay slot is nullified if not taken
7342 r32&=~(1LL<<rt1[i+1]);
7343 r32&=~(1LL<<rt2[i+1]);
7345 // Assume these are needed (delay slot)
7348 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
7352 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
7354 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
7356 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
7358 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
7360 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
7363 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7365 // SYSCALL instruction (software interrupt)
7368 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7370 // ERET instruction (return from interrupt)
7374 r32&=~(1LL<<rt1[i]);
7375 r32&=~(1LL<<rt2[i]);
7378 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
7382 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
7384 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
7386 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
7388 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
7390 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
7392 //requires_32bit[i]=r32;
7395 // Dirty registers which are 32-bit, require 32-bit input
7396 // as they will be written as 32-bit values
7397 for(hr=0;hr<HOST_REGS;hr++)
7399 if(regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64) {
7400 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
7401 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
7402 pr32[i]|=1LL<<regs[i].regmap_entry[hr];
7403 //requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
7410 // Write back dirty registers as soon as we will no longer modify them,
7411 // so that we don't end up with lots of writes at the branches.
7412 void clean_registers(int istart,int iend,int wr)
7416 u_int will_dirty_i,will_dirty_next,temp_will_dirty;
7417 u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
7419 will_dirty_i=will_dirty_next=0;
7420 wont_dirty_i=wont_dirty_next=0;
7422 will_dirty_i=will_dirty_next=will_dirty[iend+1];
7423 wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
7425 for (i=iend;i>=istart;i--)
7427 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7429 if(ba[i]<start || ba[i]>=(start+slen*4))
7431 // Branch out of this block, flush all regs
7432 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7434 // Unconditional branch
7437 // Merge in delay slot (will dirty)
7438 for(r=0;r<HOST_REGS;r++) {
7439 if(r!=EXCLUDE_REG) {
7440 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7441 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7442 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7443 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7444 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7445 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7446 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7447 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7448 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7449 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7450 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7451 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7452 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7453 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7459 // Conditional branch
7461 wont_dirty_i=wont_dirty_next;
7462 // Merge in delay slot (will dirty)
7463 for(r=0;r<HOST_REGS;r++) {
7464 if(r!=EXCLUDE_REG) {
7466 // Might not dirty if likely branch is not taken
7467 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7468 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7469 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7470 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7471 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7472 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
7473 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7474 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7475 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7476 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7477 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7478 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7479 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7480 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7485 // Merge in delay slot (wont dirty)
7486 for(r=0;r<HOST_REGS;r++) {
7487 if(r!=EXCLUDE_REG) {
7488 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7489 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7490 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7491 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7492 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7493 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7494 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7495 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7496 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7497 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7501 #ifndef DESTRUCTIVE_WRITEBACK
7502 branch_regs[i].dirty&=wont_dirty_i;
7504 branch_regs[i].dirty|=will_dirty_i;
7510 if(ba[i]<=start+i*4) {
7512 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7514 // Unconditional branch
7517 // Merge in delay slot (will dirty)
7518 for(r=0;r<HOST_REGS;r++) {
7519 if(r!=EXCLUDE_REG) {
7520 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7521 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7522 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7523 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7524 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7525 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7526 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7527 if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7528 if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7529 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7530 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7531 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7532 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7533 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7537 // Conditional branch (not taken case)
7538 temp_will_dirty=will_dirty_next;
7539 temp_wont_dirty=wont_dirty_next;
7540 // Merge in delay slot (will dirty)
7541 for(r=0;r<HOST_REGS;r++) {
7542 if(r!=EXCLUDE_REG) {
7544 // Will not dirty if likely branch is not taken
7545 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7546 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7547 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7548 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7549 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7550 if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
7551 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7552 //if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7553 //if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7554 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7555 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7556 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7557 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7558 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7563 // Merge in delay slot (wont dirty)
7564 for(r=0;r<HOST_REGS;r++) {
7565 if(r!=EXCLUDE_REG) {
7566 if((regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7567 if((regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7568 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7569 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7570 if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7571 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7572 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7573 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7574 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7575 if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7578 // Deal with changed mappings
7580 for(r=0;r<HOST_REGS;r++) {
7581 if(r!=EXCLUDE_REG) {
7582 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
7583 temp_will_dirty&=~(1<<r);
7584 temp_wont_dirty&=~(1<<r);
7585 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7586 temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7587 temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7589 temp_will_dirty|=1<<r;
7590 temp_wont_dirty|=1<<r;
7597 will_dirty[i]=temp_will_dirty;
7598 wont_dirty[i]=temp_wont_dirty;
7599 clean_registers((ba[i]-start)>>2,i-1,0);
7601 // Limit recursion. It can take an excessive amount
7602 // of time if there are a lot of nested loops.
7603 will_dirty[(ba[i]-start)>>2]=0;
7604 wont_dirty[(ba[i]-start)>>2]=-1;
7609 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7611 // Unconditional branch
7614 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7615 for(r=0;r<HOST_REGS;r++) {
7616 if(r!=EXCLUDE_REG) {
7617 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7618 will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
7619 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7621 if(branch_regs[i].regmap[r]>=0) {
7622 will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7623 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7628 // Merge in delay slot
7629 for(r=0;r<HOST_REGS;r++) {
7630 if(r!=EXCLUDE_REG) {
7631 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7632 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7633 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7634 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7635 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7636 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7637 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7638 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7639 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7640 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7641 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7642 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7643 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7644 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7648 // Conditional branch
7649 will_dirty_i=will_dirty_next;
7650 wont_dirty_i=wont_dirty_next;
7651 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7652 for(r=0;r<HOST_REGS;r++) {
7653 if(r!=EXCLUDE_REG) {
7654 signed char target_reg=branch_regs[i].regmap[r];
7655 if(target_reg==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7656 will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7657 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7659 else if(target_reg>=0) {
7660 will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
7661 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
7663 // Treat delay slot as part of branch too
7664 /*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7665 will_dirty[i+1]&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7666 wont_dirty[i+1]|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7670 will_dirty[i+1]&=~(1<<r);
7675 // Merge in delay slot
7676 for(r=0;r<HOST_REGS;r++) {
7677 if(r!=EXCLUDE_REG) {
7679 // Might not dirty if likely branch is not taken
7680 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7681 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7682 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7683 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7684 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7685 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7686 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7687 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7688 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7689 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7690 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7691 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7692 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7693 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7698 // Merge in delay slot (won't dirty)
7699 for(r=0;r<HOST_REGS;r++) {
7700 if(r!=EXCLUDE_REG) {
7701 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7702 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7703 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7704 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7705 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7706 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7707 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7708 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7709 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7710 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7714 #ifndef DESTRUCTIVE_WRITEBACK
7715 branch_regs[i].dirty&=wont_dirty_i;
7717 branch_regs[i].dirty|=will_dirty_i;
7722 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7724 // SYSCALL instruction (software interrupt)
7728 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7730 // ERET instruction (return from interrupt)
7734 will_dirty_next=will_dirty_i;
7735 wont_dirty_next=wont_dirty_i;
7736 for(r=0;r<HOST_REGS;r++) {
7737 if(r!=EXCLUDE_REG) {
7738 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7739 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7740 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7741 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7742 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7743 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7744 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7745 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7747 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
7749 // Don't store a register immediately after writing it,
7750 // may prevent dual-issue.
7751 if((regs[i].regmap[r]&63)==rt1[i-1]) wont_dirty_i|=1<<r;
7752 if((regs[i].regmap[r]&63)==rt2[i-1]) wont_dirty_i|=1<<r;
7758 will_dirty[i]=will_dirty_i;
7759 wont_dirty[i]=wont_dirty_i;
7760 // Mark registers that won't be dirtied as not dirty
7762 /*printf("wr (%d,%d) %x will:",istart,iend,start+i*4);
7763 for(r=0;r<HOST_REGS;r++) {
7764 if((will_dirty_i>>r)&1) {
7770 //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=FJUMP)) {
7771 regs[i].dirty|=will_dirty_i;
7772 #ifndef DESTRUCTIVE_WRITEBACK
7773 regs[i].dirty&=wont_dirty_i;
7774 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7776 if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
7777 for(r=0;r<HOST_REGS;r++) {
7778 if(r!=EXCLUDE_REG) {
7779 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
7780 regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
7781 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7789 for(r=0;r<HOST_REGS;r++) {
7790 if(r!=EXCLUDE_REG) {
7791 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
7792 regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
7793 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7801 // Deal with changed mappings
7802 temp_will_dirty=will_dirty_i;
7803 temp_wont_dirty=wont_dirty_i;
7804 for(r=0;r<HOST_REGS;r++) {
7805 if(r!=EXCLUDE_REG) {
7807 if(regs[i].regmap[r]==regmap_pre[i][r]) {
7809 #ifndef DESTRUCTIVE_WRITEBACK
7810 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7812 regs[i].wasdirty|=will_dirty_i&(1<<r);
7815 else if(regmap_pre[i][r]>=0&&(nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
7816 // Register moved to a different register
7817 will_dirty_i&=~(1<<r);
7818 wont_dirty_i&=~(1<<r);
7819 will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
7820 wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
7822 #ifndef DESTRUCTIVE_WRITEBACK
7823 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7825 regs[i].wasdirty|=will_dirty_i&(1<<r);
7829 will_dirty_i&=~(1<<r);
7830 wont_dirty_i&=~(1<<r);
7831 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7832 will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7833 wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7836 /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);/*assert(!((will_dirty>>r)&1));*/
7846 void disassemble_inst(int i)
7848 if (bt[i]) printf("*"); else printf(" ");
7851 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7853 printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
7855 printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
7857 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7859 if (opcode[i]==0x9&&rt1[i]!=31)
7860 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i]);
7862 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7865 printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break;
7867 if(opcode[i]==0xf) //LUI
7868 printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],rt1[i],imm[i]&0xffff);
7870 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7874 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7878 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rs2[i],rs1[i],imm[i]);
7882 printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i],rs2[i]);
7885 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rs1[i],rs2[i]);
7888 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7891 if((opcode2[i]&0x1d)==0x10)
7892 printf (" %x: %s r%d\n",start+i*4,insn[i],rt1[i]);
7893 else if((opcode2[i]&0x1d)==0x11)
7894 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7896 printf (" %x: %s\n",start+i*4,insn[i]);
7900 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC0
7901 else if(opcode2[i]==4)
7902 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC0
7903 else printf (" %x: %s\n",start+i*4,insn[i]);
7907 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC1
7908 else if(opcode2[i]>3)
7909 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC1
7910 else printf (" %x: %s\n",start+i*4,insn[i]);
7914 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC2
7915 else if(opcode2[i]>3)
7916 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC2
7917 else printf (" %x: %s\n",start+i*4,insn[i]);
7920 printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7923 printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7926 printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
7929 //printf (" %s %8x\n",insn[i],source[i]);
7930 printf (" %x: %s\n",start+i*4,insn[i]);
7934 static void disassemble_inst(int i) {}
7937 // clear the state completely, instead of just marking
7938 // things invalid like invalidate_all_pages() does
7939 void new_dynarec_clear_full()
7942 out=(u_char *)BASE_ADDR;
7943 memset(invalid_code,1,sizeof(invalid_code));
7944 memset(hash_table,0xff,sizeof(hash_table));
7945 memset(mini_ht,-1,sizeof(mini_ht));
7946 memset(restore_candidate,0,sizeof(restore_candidate));
7947 memset(shadow,0,sizeof(shadow));
7949 expirep=16384; // Expiry pointer, +2 blocks
7950 pending_exception=0;
7953 inv_code_start=inv_code_end=~0;
7957 for(n=0;n<524288;n++) // 0 .. 0x7FFFFFFF
7959 for(n=524288;n<526336;n++) // 0x80000000 .. 0x807FFFFF
7960 memory_map[n]=((u_int)rdram-0x80000000)>>2;
7961 for(n=526336;n<1048576;n++) // 0x80800000 .. 0xFFFFFFFF
7964 for(n=0;n<4096;n++) ll_clear(jump_in+n);
7965 for(n=0;n<4096;n++) ll_clear(jump_out+n);
7966 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7969 void new_dynarec_init()
7971 printf("Init new dynarec\n");
7972 out=(u_char *)BASE_ADDR;
7973 if (mmap (out, 1<<TARGET_SIZE_2,
7974 PROT_READ | PROT_WRITE | PROT_EXEC,
7975 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
7976 -1, 0) <= 0) {printf("mmap() failed\n");}
7978 rdword=&readmem_dword;
7979 fake_pc.f.r.rs=&readmem_dword;
7980 fake_pc.f.r.rt=&readmem_dword;
7981 fake_pc.f.r.rd=&readmem_dword;
7984 cycle_multiplier=200;
7985 new_dynarec_clear_full();
7987 // Copy this into local area so we don't have to put it in every literal pool
7988 invc_ptr=invalid_code;
7991 for(n=0;n<0x8000;n++) { // 0 .. 0x7FFFFFFF
7992 writemem[n] = write_nomem_new;
7993 writememb[n] = write_nomemb_new;
7994 writememh[n] = write_nomemh_new;
7996 writememd[n] = write_nomemd_new;
7998 readmem[n] = read_nomem_new;
7999 readmemb[n] = read_nomemb_new;
8000 readmemh[n] = read_nomemh_new;
8002 readmemd[n] = read_nomemd_new;
8005 for(n=0x8000;n<0x8080;n++) { // 0x80000000 .. 0x807FFFFF
8006 writemem[n] = write_rdram_new;
8007 writememb[n] = write_rdramb_new;
8008 writememh[n] = write_rdramh_new;
8010 writememd[n] = write_rdramd_new;
8013 for(n=0xC000;n<0x10000;n++) { // 0xC0000000 .. 0xFFFFFFFF
8014 writemem[n] = write_nomem_new;
8015 writememb[n] = write_nomemb_new;
8016 writememh[n] = write_nomemh_new;
8018 writememd[n] = write_nomemd_new;
8020 readmem[n] = read_nomem_new;
8021 readmemb[n] = read_nomemb_new;
8022 readmemh[n] = read_nomemh_new;
8024 readmemd[n] = read_nomemd_new;
8032 void new_dynarec_cleanup()
8035 if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0) {printf("munmap() failed\n");}
8036 for(n=0;n<4096;n++) ll_clear(jump_in+n);
8037 for(n=0;n<4096;n++) ll_clear(jump_out+n);
8038 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
8040 if (munmap (ROM_COPY, 67108864) < 0) {printf("munmap() failed\n");}
8044 int new_recompile_block(int addr)
8047 if(addr==0x800cd050) {
8049 for(block=0x80000;block<0x80800;block++) invalidate_block(block);
8051 for(n=0;n<=2048;n++) ll_clear(jump_dirty+n);
8054 //if(Count==365117028) tracedebug=1;
8055 assem_debug("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
8056 //printf("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
8057 //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
8059 //printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
8060 //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
8061 /*if(Count>=312978186) {
8065 start = (u_int)addr&~3;
8066 //assert(((u_int)addr&1)==0);
8067 new_dynarec_did_compile=1;
8069 if (Config.HLE && start == 0x80001000) // hlecall
8071 // XXX: is this enough? Maybe check hleSoftCall?
8072 u_int beginning=(u_int)out;
8073 u_int page=get_page(start);
8074 invalid_code[start>>12]=0;
8075 emit_movimm(start,0);
8076 emit_writeword(0,(int)&pcaddr);
8077 emit_jmp((int)new_dyna_leave);
8080 __clear_cache((void *)beginning,out);
8082 ll_add(jump_in+page,start,(void *)beginning);
8085 else if ((u_int)addr < 0x00200000 ||
8086 (0xa0000000 <= addr && addr < 0xa0200000)) {
8087 // used for BIOS calls mostly?
8088 source = (u_int *)((u_int)rdram+(start&0x1fffff));
8089 pagelimit = (addr&0xa0000000)|0x00200000;
8091 else if (!Config.HLE && (
8092 /* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
8093 (0xbfc00000 <= addr && addr < 0xbfc80000))) {
8095 source = (u_int *)((u_int)psxR+(start&0x7ffff));
8096 pagelimit = (addr&0xfff00000)|0x80000;
8101 if ((int)addr >= 0xa4000000 && (int)addr < 0xa4001000) {
8102 source = (u_int *)((u_int)SP_DMEM+start-0xa4000000);
8103 pagelimit = 0xa4001000;
8107 if ((int)addr >= 0x80000000 && (int)addr < 0x80000000+RAM_SIZE) {
8108 source = (u_int *)((u_int)rdram+start-0x80000000);
8109 pagelimit = 0x80000000+RAM_SIZE;
8112 else if ((signed int)addr >= (signed int)0xC0000000) {
8113 //printf("addr=%x mm=%x\n",(u_int)addr,(memory_map[start>>12]<<2));
8114 //if(tlb_LUT_r[start>>12])
8115 //source = (u_int *)(((int)rdram)+(tlb_LUT_r[start>>12]&0xFFFFF000)+(((int)addr)&0xFFF)-0x80000000);
8116 if((signed int)memory_map[start>>12]>=0) {
8117 source = (u_int *)((u_int)(start+(memory_map[start>>12]<<2)));
8118 pagelimit=(start+4096)&0xFFFFF000;
8119 int map=memory_map[start>>12];
8122 //printf("start: %x next: %x\n",map,memory_map[pagelimit>>12]);
8123 if((map&0xBFFFFFFF)==(memory_map[pagelimit>>12]&0xBFFFFFFF)) pagelimit+=4096;
8125 assem_debug("pagelimit=%x\n",pagelimit);
8126 assem_debug("mapping=%x (%x)\n",memory_map[start>>12],(memory_map[start>>12]<<2)+start);
8129 assem_debug("Compile at unmapped memory address: %x \n", (int)addr);
8130 //assem_debug("start: %x next: %x\n",memory_map[start>>12],memory_map[(start+4096)>>12]);
8131 return -1; // Caller will invoke exception handler
8133 //printf("source= %x\n",(int)source);
8137 printf("Compile at bogus memory address: %x \n", (int)addr);
8141 /* Pass 1: disassemble */
8142 /* Pass 2: register dependencies, branch targets */
8143 /* Pass 3: register allocation */
8144 /* Pass 4: branch dependencies */
8145 /* Pass 5: pre-alloc */
8146 /* Pass 6: optimize clean/dirty state */
8147 /* Pass 7: flag 32-bit registers */
8148 /* Pass 8: assembly */
8149 /* Pass 9: linker */
8150 /* Pass 10: garbage collection / free memory */
8154 unsigned int type,op,op2;
8156 //printf("addr = %x source = %x %x\n", addr,source,source[0]);
8158 /* Pass 1 disassembly */
8160 for(i=0;!done;i++) {
8161 bt[i]=0;likely[i]=0;ooo[i]=0;op2=0;
8162 minimum_free_regs[i]=0;
8163 opcode[i]=op=source[i]>>26;
8166 case 0x00: strcpy(insn[i],"special"); type=NI;
8170 case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
8171 case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
8172 case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
8173 case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
8174 case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
8175 case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
8176 case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
8177 case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
8178 case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
8179 case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
8180 case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
8181 case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
8182 case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
8183 case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
8184 case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
8185 case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
8186 case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
8187 case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
8188 case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
8189 case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
8190 case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
8191 case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
8192 case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
8193 case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
8194 case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
8195 case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
8196 case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
8197 case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
8198 case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
8199 case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
8200 case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
8201 case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
8202 case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
8203 case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
8204 case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
8206 case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
8207 case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
8208 case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
8209 case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
8210 case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
8211 case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
8212 case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
8213 case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
8214 case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
8215 case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
8216 case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
8217 case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
8218 case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
8219 case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
8220 case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
8221 case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
8222 case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
8226 case 0x01: strcpy(insn[i],"regimm"); type=NI;
8227 op2=(source[i]>>16)&0x1f;
8230 case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
8231 case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
8232 case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
8233 case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
8234 case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
8235 case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
8236 case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
8237 case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
8238 case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
8239 case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
8240 case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
8241 case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
8242 case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
8243 case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
8246 case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
8247 case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
8248 case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
8249 case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
8250 case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
8251 case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
8252 case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
8253 case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
8254 case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
8255 case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
8256 case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
8257 case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
8258 case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
8259 case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
8260 case 0x10: strcpy(insn[i],"cop0"); type=NI;
8261 op2=(source[i]>>21)&0x1f;
8264 case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
8265 case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
8266 case 0x10: strcpy(insn[i],"tlb"); type=NI;
8267 switch(source[i]&0x3f)
8269 case 0x01: strcpy(insn[i],"TLBR"); type=COP0; break;
8270 case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break;
8271 case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break;
8272 case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break;
8274 case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
8276 case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
8281 case 0x11: strcpy(insn[i],"cop1"); type=NI;
8282 op2=(source[i]>>21)&0x1f;
8285 case 0x00: strcpy(insn[i],"MFC1"); type=COP1; break;
8286 case 0x01: strcpy(insn[i],"DMFC1"); type=COP1; break;
8287 case 0x02: strcpy(insn[i],"CFC1"); type=COP1; break;
8288 case 0x04: strcpy(insn[i],"MTC1"); type=COP1; break;
8289 case 0x05: strcpy(insn[i],"DMTC1"); type=COP1; break;
8290 case 0x06: strcpy(insn[i],"CTC1"); type=COP1; break;
8291 case 0x08: strcpy(insn[i],"BC1"); type=FJUMP;
8292 switch((source[i]>>16)&0x3)
8294 case 0x00: strcpy(insn[i],"BC1F"); break;
8295 case 0x01: strcpy(insn[i],"BC1T"); break;
8296 case 0x02: strcpy(insn[i],"BC1FL"); break;
8297 case 0x03: strcpy(insn[i],"BC1TL"); break;
8300 case 0x10: strcpy(insn[i],"C1.S"); type=NI;
8301 switch(source[i]&0x3f)
8303 case 0x00: strcpy(insn[i],"ADD.S"); type=FLOAT; break;
8304 case 0x01: strcpy(insn[i],"SUB.S"); type=FLOAT; break;
8305 case 0x02: strcpy(insn[i],"MUL.S"); type=FLOAT; break;
8306 case 0x03: strcpy(insn[i],"DIV.S"); type=FLOAT; break;
8307 case 0x04: strcpy(insn[i],"SQRT.S"); type=FLOAT; break;
8308 case 0x05: strcpy(insn[i],"ABS.S"); type=FLOAT; break;
8309 case 0x06: strcpy(insn[i],"MOV.S"); type=FLOAT; break;
8310 case 0x07: strcpy(insn[i],"NEG.S"); type=FLOAT; break;
8311 case 0x08: strcpy(insn[i],"ROUND.L.S"); type=FCONV; break;
8312 case 0x09: strcpy(insn[i],"TRUNC.L.S"); type=FCONV; break;
8313 case 0x0A: strcpy(insn[i],"CEIL.L.S"); type=FCONV; break;
8314 case 0x0B: strcpy(insn[i],"FLOOR.L.S"); type=FCONV; break;
8315 case 0x0C: strcpy(insn[i],"ROUND.W.S"); type=FCONV; break;
8316 case 0x0D: strcpy(insn[i],"TRUNC.W.S"); type=FCONV; break;
8317 case 0x0E: strcpy(insn[i],"CEIL.W.S"); type=FCONV; break;
8318 case 0x0F: strcpy(insn[i],"FLOOR.W.S"); type=FCONV; break;
8319 case 0x21: strcpy(insn[i],"CVT.D.S"); type=FCONV; break;
8320 case 0x24: strcpy(insn[i],"CVT.W.S"); type=FCONV; break;
8321 case 0x25: strcpy(insn[i],"CVT.L.S"); type=FCONV; break;
8322 case 0x30: strcpy(insn[i],"C.F.S"); type=FCOMP; break;
8323 case 0x31: strcpy(insn[i],"C.UN.S"); type=FCOMP; break;
8324 case 0x32: strcpy(insn[i],"C.EQ.S"); type=FCOMP; break;
8325 case 0x33: strcpy(insn[i],"C.UEQ.S"); type=FCOMP; break;
8326 case 0x34: strcpy(insn[i],"C.OLT.S"); type=FCOMP; break;
8327 case 0x35: strcpy(insn[i],"C.ULT.S"); type=FCOMP; break;
8328 case 0x36: strcpy(insn[i],"C.OLE.S"); type=FCOMP; break;
8329 case 0x37: strcpy(insn[i],"C.ULE.S"); type=FCOMP; break;
8330 case 0x38: strcpy(insn[i],"C.SF.S"); type=FCOMP; break;
8331 case 0x39: strcpy(insn[i],"C.NGLE.S"); type=FCOMP; break;
8332 case 0x3A: strcpy(insn[i],"C.SEQ.S"); type=FCOMP; break;
8333 case 0x3B: strcpy(insn[i],"C.NGL.S"); type=FCOMP; break;
8334 case 0x3C: strcpy(insn[i],"C.LT.S"); type=FCOMP; break;
8335 case 0x3D: strcpy(insn[i],"C.NGE.S"); type=FCOMP; break;
8336 case 0x3E: strcpy(insn[i],"C.LE.S"); type=FCOMP; break;
8337 case 0x3F: strcpy(insn[i],"C.NGT.S"); type=FCOMP; break;
8340 case 0x11: strcpy(insn[i],"C1.D"); type=NI;
8341 switch(source[i]&0x3f)
8343 case 0x00: strcpy(insn[i],"ADD.D"); type=FLOAT; break;
8344 case 0x01: strcpy(insn[i],"SUB.D"); type=FLOAT; break;
8345 case 0x02: strcpy(insn[i],"MUL.D"); type=FLOAT; break;
8346 case 0x03: strcpy(insn[i],"DIV.D"); type=FLOAT; break;
8347 case 0x04: strcpy(insn[i],"SQRT.D"); type=FLOAT; break;
8348 case 0x05: strcpy(insn[i],"ABS.D"); type=FLOAT; break;
8349 case 0x06: strcpy(insn[i],"MOV.D"); type=FLOAT; break;
8350 case 0x07: strcpy(insn[i],"NEG.D"); type=FLOAT; break;
8351 case 0x08: strcpy(insn[i],"ROUND.L.D"); type=FCONV; break;
8352 case 0x09: strcpy(insn[i],"TRUNC.L.D"); type=FCONV; break;
8353 case 0x0A: strcpy(insn[i],"CEIL.L.D"); type=FCONV; break;
8354 case 0x0B: strcpy(insn[i],"FLOOR.L.D"); type=FCONV; break;
8355 case 0x0C: strcpy(insn[i],"ROUND.W.D"); type=FCONV; break;
8356 case 0x0D: strcpy(insn[i],"TRUNC.W.D"); type=FCONV; break;
8357 case 0x0E: strcpy(insn[i],"CEIL.W.D"); type=FCONV; break;
8358 case 0x0F: strcpy(insn[i],"FLOOR.W.D"); type=FCONV; break;
8359 case 0x20: strcpy(insn[i],"CVT.S.D"); type=FCONV; break;
8360 case 0x24: strcpy(insn[i],"CVT.W.D"); type=FCONV; break;
8361 case 0x25: strcpy(insn[i],"CVT.L.D"); type=FCONV; break;
8362 case 0x30: strcpy(insn[i],"C.F.D"); type=FCOMP; break;
8363 case 0x31: strcpy(insn[i],"C.UN.D"); type=FCOMP; break;
8364 case 0x32: strcpy(insn[i],"C.EQ.D"); type=FCOMP; break;
8365 case 0x33: strcpy(insn[i],"C.UEQ.D"); type=FCOMP; break;
8366 case 0x34: strcpy(insn[i],"C.OLT.D"); type=FCOMP; break;
8367 case 0x35: strcpy(insn[i],"C.ULT.D"); type=FCOMP; break;
8368 case 0x36: strcpy(insn[i],"C.OLE.D"); type=FCOMP; break;
8369 case 0x37: strcpy(insn[i],"C.ULE.D"); type=FCOMP; break;
8370 case 0x38: strcpy(insn[i],"C.SF.D"); type=FCOMP; break;
8371 case 0x39: strcpy(insn[i],"C.NGLE.D"); type=FCOMP; break;
8372 case 0x3A: strcpy(insn[i],"C.SEQ.D"); type=FCOMP; break;
8373 case 0x3B: strcpy(insn[i],"C.NGL.D"); type=FCOMP; break;
8374 case 0x3C: strcpy(insn[i],"C.LT.D"); type=FCOMP; break;
8375 case 0x3D: strcpy(insn[i],"C.NGE.D"); type=FCOMP; break;
8376 case 0x3E: strcpy(insn[i],"C.LE.D"); type=FCOMP; break;
8377 case 0x3F: strcpy(insn[i],"C.NGT.D"); type=FCOMP; break;
8380 case 0x14: strcpy(insn[i],"C1.W"); type=NI;
8381 switch(source[i]&0x3f)
8383 case 0x20: strcpy(insn[i],"CVT.S.W"); type=FCONV; break;
8384 case 0x21: strcpy(insn[i],"CVT.D.W"); type=FCONV; break;
8387 case 0x15: strcpy(insn[i],"C1.L"); type=NI;
8388 switch(source[i]&0x3f)
8390 case 0x20: strcpy(insn[i],"CVT.S.L"); type=FCONV; break;
8391 case 0x21: strcpy(insn[i],"CVT.D.L"); type=FCONV; break;
8397 case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
8398 case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
8399 case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
8400 case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
8401 case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
8402 case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
8403 case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
8404 case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
8406 case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
8407 case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
8408 case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
8409 case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
8410 case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
8411 case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
8412 case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
8414 case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
8416 case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
8417 case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
8418 case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
8419 case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
8421 case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
8422 case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
8424 case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
8425 case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
8426 case 0x30: strcpy(insn[i],"LL"); type=NI; break;
8427 case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
8429 case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
8430 case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
8431 case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
8433 case 0x38: strcpy(insn[i],"SC"); type=NI; break;
8434 case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
8436 case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
8437 case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
8438 case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
8441 case 0x12: strcpy(insn[i],"COP2"); type=NI;
8442 op2=(source[i]>>21)&0x1f;
8444 if (source[i]&0x3f) { // use this hack to support old savestates with patched gte insns
8445 if (gte_handlers[source[i]&0x3f]!=NULL) {
8446 if (gte_regnames[source[i]&0x3f]!=NULL)
8447 strcpy(insn[i],gte_regnames[source[i]&0x3f]);
8449 snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
8455 case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
8456 case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
8457 case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
8458 case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
8461 case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
8462 case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
8463 case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
8465 default: strcpy(insn[i],"???"); type=NI;
8466 printf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
8471 /* Get registers/immediates */
8477 gte_rs[i]=gte_rt[i]=0;
8480 rs1[i]=(source[i]>>21)&0x1f;
8482 rt1[i]=(source[i]>>16)&0x1f;
8484 imm[i]=(short)source[i];
8488 rs1[i]=(source[i]>>21)&0x1f;
8489 rs2[i]=(source[i]>>16)&0x1f;
8492 imm[i]=(short)source[i];
8493 if(op==0x2c||op==0x2d||op==0x3f) us1[i]=rs2[i]; // 64-bit SDL/SDR/SD
8496 // LWL/LWR only load part of the register,
8497 // therefore the target register must be treated as a source too
8498 rs1[i]=(source[i]>>21)&0x1f;
8499 rs2[i]=(source[i]>>16)&0x1f;
8500 rt1[i]=(source[i]>>16)&0x1f;
8502 imm[i]=(short)source[i];
8503 if(op==0x1a||op==0x1b) us1[i]=rs2[i]; // LDR/LDL
8504 if(op==0x26) dep1[i]=rt1[i]; // LWR
8507 if (op==0x0f) rs1[i]=0; // LUI instruction has no source register
8508 else rs1[i]=(source[i]>>21)&0x1f;
8510 rt1[i]=(source[i]>>16)&0x1f;
8512 if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
8513 imm[i]=(unsigned short)source[i];
8515 imm[i]=(short)source[i];
8517 if(op==0x18||op==0x19) us1[i]=rs1[i]; // DADDI/DADDIU
8518 if(op==0x0a||op==0x0b) us1[i]=rs1[i]; // SLTI/SLTIU
8519 if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI
8526 // The JAL instruction writes to r31.
8533 rs1[i]=(source[i]>>21)&0x1f;
8537 // The JALR instruction writes to rd.
8539 rt1[i]=(source[i]>>11)&0x1f;
8544 rs1[i]=(source[i]>>21)&0x1f;
8545 rs2[i]=(source[i]>>16)&0x1f;
8548 if(op&2) { // BGTZ/BLEZ
8556 rs1[i]=(source[i]>>21)&0x1f;
8561 if(op2&0x10) { // BxxAL
8563 // NOTE: If the branch is not taken, r31 is still overwritten
8565 likely[i]=(op2&2)>>1;
8572 likely[i]=((source[i])>>17)&1;
8575 rs1[i]=(source[i]>>21)&0x1f; // source
8576 rs2[i]=(source[i]>>16)&0x1f; // subtract amount
8577 rt1[i]=(source[i]>>11)&0x1f; // destination
8579 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
8580 us1[i]=rs1[i];us2[i]=rs2[i];
8582 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
8583 dep1[i]=rs1[i];dep2[i]=rs2[i];
8585 else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB
8586 dep1[i]=rs1[i];dep2[i]=rs2[i];
8590 rs1[i]=(source[i]>>21)&0x1f; // source
8591 rs2[i]=(source[i]>>16)&0x1f; // divisor
8594 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
8595 us1[i]=rs1[i];us2[i]=rs2[i];
8603 if(op2==0x10) rs1[i]=HIREG; // MFHI
8604 if(op2==0x11) rt1[i]=HIREG; // MTHI
8605 if(op2==0x12) rs1[i]=LOREG; // MFLO
8606 if(op2==0x13) rt1[i]=LOREG; // MTLO
8607 if((op2&0x1d)==0x10) rt1[i]=(source[i]>>11)&0x1f; // MFxx
8608 if((op2&0x1d)==0x11) rs1[i]=(source[i]>>21)&0x1f; // MTxx
8612 rs1[i]=(source[i]>>16)&0x1f; // target of shift
8613 rs2[i]=(source[i]>>21)&0x1f; // shift amount
8614 rt1[i]=(source[i]>>11)&0x1f; // destination
8616 // DSLLV/DSRLV/DSRAV are 64-bit
8617 if(op2>=0x14&&op2<=0x17) us1[i]=rs1[i];
8620 rs1[i]=(source[i]>>16)&0x1f;
8622 rt1[i]=(source[i]>>11)&0x1f;
8624 imm[i]=(source[i]>>6)&0x1f;
8625 // DSxx32 instructions
8626 if(op2>=0x3c) imm[i]|=0x20;
8627 // DSLL/DSRL/DSRA/DSRA32/DSRL32 but not DSLL32 require 64-bit source
8628 if(op2>=0x38&&op2!=0x3c) us1[i]=rs1[i];
8635 if(op2==0) rt1[i]=(source[i]>>16)&0x1F; // MFC0
8636 if(op2==4) rs1[i]=(source[i]>>16)&0x1F; // MTC0
8637 if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status
8638 if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET
8645 if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
8646 if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
8647 if(op2==5) us1[i]=rs1[i]; // DMTC1
8655 if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC2/CFC2
8656 if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC2/CTC2
8658 int gr=(source[i]>>11)&0x1F;
8661 case 0x00: gte_rs[i]=1ll<<gr; break; // MFC2
8662 case 0x04: gte_rt[i]=1ll<<gr; break; // MTC2
8663 case 0x02: gte_rs[i]=1ll<<(gr+32); break; // CFC2
8664 case 0x06: gte_rt[i]=1ll<<(gr+32); break; // CTC2
8668 rs1[i]=(source[i]>>21)&0x1F;
8672 imm[i]=(short)source[i];
8675 rs1[i]=(source[i]>>21)&0x1F;
8679 imm[i]=(short)source[i];
8680 if(op==0x32) gte_rt[i]=1ll<<((source[i]>>16)&0x1F); // LWC2
8681 else gte_rs[i]=1ll<<((source[i]>>16)&0x1F); // SWC2
8688 gte_rs[i]=gte_reg_reads[source[i]&0x3f];
8689 gte_rt[i]=gte_reg_writes[source[i]&0x3f];
8690 gte_rt[i]|=1ll<<63; // every op changes flags
8719 /* Calculate branch target addresses */
8721 ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
8722 else if(type==CJUMP&&rs1[i]==rs2[i]&&(op&1))
8723 ba[i]=start+i*4+8; // Ignore never taken branch
8724 else if(type==SJUMP&&rs1[i]==0&&!(op2&1))
8725 ba[i]=start+i*4+8; // Ignore never taken branch
8726 else if(type==CJUMP||type==SJUMP||type==FJUMP)
8727 ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
8730 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
8732 // branch in delay slot?
8733 if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
8734 // don't handle first branch and call interpreter if it's hit
8735 printf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr);
8738 // basic load delay detection
8739 else if((type==LOAD||type==LOADLR||type==COP0||type==COP2||type==C2LS)&&rt1[i]!=0) {
8740 int t=(ba[i-1]-start)/4;
8741 if(0 <= t && t < i &&(rt1[i]==rs1[t]||rt1[i]==rs2[t])&&itype[t]!=CJUMP&&itype[t]!=SJUMP) {
8742 // jump target wants DS result - potential load delay effect
8743 printf("load delay @%08x (%08x)\n", addr + i*4, addr);
8745 bt[t+1]=1; // expected return from interpreter
8747 else if(i>=2&&rt1[i-2]==2&&rt1[i]==2&&rs1[i]!=2&&rs2[i]!=2&&rs1[i-1]!=2&&rs2[i-1]!=2&&
8748 !(i>=3&&(itype[i-3]==RJUMP||itype[i-3]==UJUMP||itype[i-3]==CJUMP||itype[i-3]==SJUMP))) {
8749 // v0 overwrite like this is a sign of trouble, bail out
8750 printf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr);
8756 rs2[i-1]=rt1[i-1]=rt2[i-1]=0;
8760 i--; // don't compile the DS
8764 /* Is this the end of the block? */
8765 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
8766 if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
8770 if(stop_after_jal) done=1;
8772 if((source[i+1]&0xfc00003f)==0x0d) done=1;
8774 // Don't recompile stuff that's already compiled
8775 if(check_addr(start+i*4+4)) done=1;
8776 // Don't get too close to the limit
8777 if(i>MAXBLOCK/2) done=1;
8779 if(itype[i]==SYSCALL&&stop_after_jal) done=1;
8780 if(itype[i]==HLECALL||itype[i]==INTCALL) done=2;
8782 // Does the block continue due to a branch?
8785 if(ba[j]==start+i*4) done=j=0; // Branch into delay slot
8786 if(ba[j]==start+i*4+4) done=j=0;
8787 if(ba[j]==start+i*4+8) done=j=0;
8790 //assert(i<MAXBLOCK-1);
8791 if(start+i*4==pagelimit-4) done=1;
8792 assert(start+i*4<pagelimit);
8793 if (i==MAXBLOCK-1) done=1;
8794 // Stop if we're compiling junk
8795 if(itype[i]==NI&&opcode[i]==0x11) {
8796 done=stop_after_jal=1;
8797 printf("Disabled speculative precompilation\n");
8801 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP||itype[i-1]==FJUMP) {
8802 if(start+i*4==pagelimit) {
8808 /* Pass 2 - Register dependencies and branch targets */
8810 unneeded_registers(0,slen-1,0);
8812 /* Pass 3 - Register allocation */
8814 struct regstat current; // Current register allocations/status
8817 current.u=unneeded_reg[0];
8818 current.uu=unneeded_reg_upper[0];
8819 clear_all_regs(current.regmap);
8820 alloc_reg(¤t,0,CCREG);
8821 dirty_reg(¤t,CCREG);
8824 current.waswritten=0;
8830 provisional_32bit();
8833 // First instruction is delay slot
8838 unneeded_reg_upper[0]=1;
8839 current.regmap[HOST_BTREG]=BTREG;
8847 for(hr=0;hr<HOST_REGS;hr++)
8849 // Is this really necessary?
8850 if(current.regmap[hr]==0) current.regmap[hr]=-1;
8853 current.waswritten=0;
8857 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
8859 if(rs1[i-2]==0||rs2[i-2]==0)
8862 current.is32|=1LL<<rs1[i-2];
8863 int hr=get_reg(current.regmap,rs1[i-2]|64);
8864 if(hr>=0) current.regmap[hr]=-1;
8867 current.is32|=1LL<<rs2[i-2];
8868 int hr=get_reg(current.regmap,rs2[i-2]|64);
8869 if(hr>=0) current.regmap[hr]=-1;
8875 // If something jumps here with 64-bit values
8876 // then promote those registers to 64 bits
8879 uint64_t temp_is32=current.is32;
8882 if(ba[j]==start+i*4)
8883 temp_is32&=branch_regs[j].is32;
8887 if(ba[j]==start+i*4)
8891 if(temp_is32!=current.is32) {
8892 //printf("dumping 32-bit regs (%x)\n",start+i*4);
8893 #ifndef DESTRUCTIVE_WRITEBACK
8896 for(hr=0;hr<HOST_REGS;hr++)
8898 int r=current.regmap[hr];
8901 if((current.dirty>>hr)&((current.is32&~temp_is32)>>r)&1) {
8903 //printf("restore %d\n",r);
8907 current.is32=temp_is32;
8914 memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
8915 regs[i].wasconst=current.isconst;
8916 regs[i].was32=current.is32;
8917 regs[i].wasdirty=current.dirty;
8918 regs[i].loadedconst=0;
8919 #if defined(DESTRUCTIVE_WRITEBACK) && !defined(FORCE32)
8920 // To change a dirty register from 32 to 64 bits, we must write
8921 // it out during the previous cycle (for branches, 2 cycles)
8922 if(i<slen-1&&bt[i+1]&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP)
8924 uint64_t temp_is32=current.is32;
8927 if(ba[j]==start+i*4+4)
8928 temp_is32&=branch_regs[j].is32;
8932 if(ba[j]==start+i*4+4)
8936 if(temp_is32!=current.is32) {
8937 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8938 for(hr=0;hr<HOST_REGS;hr++)
8940 int r=current.regmap[hr];
8943 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8944 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP)
8946 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63))
8948 //printf("dump %d/r%d\n",hr,r);
8949 current.regmap[hr]=-1;
8950 if(get_reg(current.regmap,r|64)>=0)
8951 current.regmap[get_reg(current.regmap,r|64)]=-1;
8959 else if(i<slen-2&&bt[i+2]&&(source[i-1]>>16)!=0x1000&&(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP))
8961 uint64_t temp_is32=current.is32;
8964 if(ba[j]==start+i*4+8)
8965 temp_is32&=branch_regs[j].is32;
8969 if(ba[j]==start+i*4+8)
8973 if(temp_is32!=current.is32) {
8974 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8975 for(hr=0;hr<HOST_REGS;hr++)
8977 int r=current.regmap[hr];
8980 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8981 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63)&&rs1[i+1]!=(r&63)&&rs2[i+1]!=(r&63))
8983 //printf("dump %d/r%d\n",hr,r);
8984 current.regmap[hr]=-1;
8985 if(get_reg(current.regmap,r|64)>=0)
8986 current.regmap[get_reg(current.regmap,r|64)]=-1;
8994 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
8996 current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
8997 current.uu=unneeded_reg_upper[i+1]&~((1LL<<us1[i])|(1LL<<us2[i]));
8998 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9007 current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
9008 current.uu=branch_unneeded_reg_upper[i]&~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
9009 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
9010 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
9011 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9014 } else { printf("oops, branch at end of block with no delay slot\n");exit(1); }
9018 ds=0; // Skip delay slot, already allocated as part of branch
9019 // ...but we need to alloc it in case something jumps here
9021 current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
9022 current.uu=branch_unneeded_reg_upper[i-1]&unneeded_reg_upper[i+1];
9024 current.u=branch_unneeded_reg[i-1];
9025 current.uu=branch_unneeded_reg_upper[i-1];
9027 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
9028 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9029 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9032 struct regstat temp;
9033 memcpy(&temp,¤t,sizeof(current));
9034 temp.wasdirty=temp.dirty;
9035 temp.was32=temp.is32;
9036 // TODO: Take into account unconditional branches, as below
9037 delayslot_alloc(&temp,i);
9038 memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
9039 regs[i].wasdirty=temp.wasdirty;
9040 regs[i].was32=temp.was32;
9041 regs[i].dirty=temp.dirty;
9042 regs[i].is32=temp.is32;
9046 // Create entry (branch target) regmap
9047 for(hr=0;hr<HOST_REGS;hr++)
9049 int r=temp.regmap[hr];
9051 if(r!=regmap_pre[i][hr]) {
9052 regs[i].regmap_entry[hr]=-1;
9057 if((current.u>>r)&1) {
9058 regs[i].regmap_entry[hr]=-1;
9059 regs[i].regmap[hr]=-1;
9060 //Don't clear regs in the delay slot as the branch might need them
9061 //current.regmap[hr]=-1;
9063 regs[i].regmap_entry[hr]=r;
9066 if((current.uu>>(r&63))&1) {
9067 regs[i].regmap_entry[hr]=-1;
9068 regs[i].regmap[hr]=-1;
9069 //Don't clear regs in the delay slot as the branch might need them
9070 //current.regmap[hr]=-1;
9072 regs[i].regmap_entry[hr]=r;
9076 // First instruction expects CCREG to be allocated
9077 if(i==0&&hr==HOST_CCREG)
9078 regs[i].regmap_entry[hr]=CCREG;
9080 regs[i].regmap_entry[hr]=-1;
9084 else { // Not delay slot
9087 //current.isconst=0; // DEBUG
9088 //current.wasconst=0; // DEBUG
9089 //regs[i].wasconst=0; // DEBUG
9090 clear_const(¤t,rt1[i]);
9091 alloc_cc(¤t,i);
9092 dirty_reg(¤t,CCREG);
9094 alloc_reg(¤t,i,31);
9095 dirty_reg(¤t,31);
9096 //assert(rs1[i+1]!=31&&rs2[i+1]!=31);
9097 //assert(rt1[i+1]!=rt1[i]);
9099 alloc_reg(¤t,i,PTEMP);
9101 //current.is32|=1LL<<rt1[i];
9104 delayslot_alloc(¤t,i+1);
9105 //current.isconst=0; // DEBUG
9107 //printf("i=%d, isconst=%x\n",i,current.isconst);
9110 //current.isconst=0;
9111 //current.wasconst=0;
9112 //regs[i].wasconst=0;
9113 clear_const(¤t,rs1[i]);
9114 clear_const(¤t,rt1[i]);
9115 alloc_cc(¤t,i);
9116 dirty_reg(¤t,CCREG);
9117 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
9118 alloc_reg(¤t,i,rs1[i]);
9120 alloc_reg(¤t,i,rt1[i]);
9121 dirty_reg(¤t,rt1[i]);
9122 assert(rs1[i+1]!=rt1[i]&&rs2[i+1]!=rt1[i]);
9123 assert(rt1[i+1]!=rt1[i]);
9125 alloc_reg(¤t,i,PTEMP);
9129 if(rs1[i]==31) { // JALR
9130 alloc_reg(¤t,i,RHASH);
9131 #ifndef HOST_IMM_ADDR32
9132 alloc_reg(¤t,i,RHTBL);
9136 delayslot_alloc(¤t,i+1);
9138 // The delay slot overwrites our source register,
9139 // allocate a temporary register to hold the old value.
9143 delayslot_alloc(¤t,i+1);
9145 alloc_reg(¤t,i,RTEMP);
9147 //current.isconst=0; // DEBUG
9152 //current.isconst=0;
9153 //current.wasconst=0;
9154 //regs[i].wasconst=0;
9155 clear_const(¤t,rs1[i]);
9156 clear_const(¤t,rs2[i]);
9157 if((opcode[i]&0x3E)==4) // BEQ/BNE
9159 alloc_cc(¤t,i);
9160 dirty_reg(¤t,CCREG);
9161 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
9162 if(rs2[i]) alloc_reg(¤t,i,rs2[i]);
9163 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9165 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
9166 if(rs2[i]) alloc_reg64(¤t,i,rs2[i]);
9168 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
9169 (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) {
9170 // The delay slot overwrites one of our conditions.
9171 // Allocate the branch condition registers instead.
9175 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
9176 if(rs2[i]) alloc_reg(¤t,i,rs2[i]);
9177 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9179 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
9180 if(rs2[i]) alloc_reg64(¤t,i,rs2[i]);
9186 delayslot_alloc(¤t,i+1);
9190 if((opcode[i]&0x3E)==6) // BLEZ/BGTZ
9192 alloc_cc(¤t,i);
9193 dirty_reg(¤t,CCREG);
9194 alloc_reg(¤t,i,rs1[i]);
9195 if(!(current.is32>>rs1[i]&1))
9197 alloc_reg64(¤t,i,rs1[i]);
9199 if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
9200 // The delay slot overwrites one of our conditions.
9201 // Allocate the branch condition registers instead.
9205 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
9206 if(!((current.is32>>rs1[i])&1))
9208 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
9214 delayslot_alloc(¤t,i+1);
9218 // Don't alloc the delay slot yet because we might not execute it
9219 if((opcode[i]&0x3E)==0x14) // BEQL/BNEL
9224 alloc_cc(¤t,i);
9225 dirty_reg(¤t,CCREG);
9226 alloc_reg(¤t,i,rs1[i]);
9227 alloc_reg(¤t,i,rs2[i]);
9228 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9230 alloc_reg64(¤t,i,rs1[i]);
9231 alloc_reg64(¤t,i,rs2[i]);
9235 if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL
9240 alloc_cc(¤t,i);
9241 dirty_reg(¤t,CCREG);
9242 alloc_reg(¤t,i,rs1[i]);
9243 if(!(current.is32>>rs1[i]&1))
9245 alloc_reg64(¤t,i,rs1[i]);
9249 //current.isconst=0;
9252 //current.isconst=0;
9253 //current.wasconst=0;
9254 //regs[i].wasconst=0;
9255 clear_const(¤t,rs1[i]);
9256 clear_const(¤t,rt1[i]);
9257 //if((opcode2[i]&0x1E)==0x0) // BLTZ/BGEZ
9258 if((opcode2[i]&0x0E)==0x0) // BLTZ/BGEZ
9260 alloc_cc(¤t,i);
9261 dirty_reg(¤t,CCREG);
9262 alloc_reg(¤t,i,rs1[i]);
9263 if(!(current.is32>>rs1[i]&1))
9265 alloc_reg64(¤t,i,rs1[i]);
9267 if (rt1[i]==31) { // BLTZAL/BGEZAL
9268 alloc_reg(¤t,i,31);
9269 dirty_reg(¤t,31);
9270 //#ifdef REG_PREFETCH
9271 //alloc_reg(¤t,i,PTEMP);
9273 //current.is32|=1LL<<rt1[i];
9275 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) // The delay slot overwrites the branch condition.
9276 ||(rt1[i]==31&&(rs1[i+1]==31||rs2[i+1]==31||rt1[i+1]==31||rt2[i+1]==31))) { // DS touches $ra
9277 // Allocate the branch condition registers instead.
9281 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
9282 if(!((current.is32>>rs1[i])&1))
9284 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
9290 delayslot_alloc(¤t,i+1);
9294 // Don't alloc the delay slot yet because we might not execute it
9295 if((opcode2[i]&0x1E)==0x2) // BLTZL/BGEZL
9300 alloc_cc(¤t,i);
9301 dirty_reg(¤t,CCREG);
9302 alloc_reg(¤t,i,rs1[i]);
9303 if(!(current.is32>>rs1[i]&1))
9305 alloc_reg64(¤t,i,rs1[i]);
9309 //current.isconst=0;
9315 if(likely[i]==0) // BC1F/BC1T
9317 // TODO: Theoretically we can run out of registers here on x86.
9318 // The delay slot can allocate up to six, and we need to check
9319 // CSREG before executing the delay slot. Possibly we can drop
9320 // the cycle count and then reload it after checking that the
9321 // FPU is in a usable state, or don't do out-of-order execution.
9322 alloc_cc(¤t,i);
9323 dirty_reg(¤t,CCREG);
9324 alloc_reg(¤t,i,FSREG);
9325 alloc_reg(¤t,i,CSREG);
9326 if(itype[i+1]==FCOMP) {
9327 // The delay slot overwrites the branch condition.
9328 // Allocate the branch condition registers instead.
9329 alloc_cc(¤t,i);
9330 dirty_reg(¤t,CCREG);
9331 alloc_reg(¤t,i,CSREG);
9332 alloc_reg(¤t,i,FSREG);
9336 delayslot_alloc(¤t,i+1);
9337 alloc_reg(¤t,i+1,CSREG);
9341 // Don't alloc the delay slot yet because we might not execute it
9342 if(likely[i]) // BC1FL/BC1TL
9344 alloc_cc(¤t,i);
9345 dirty_reg(¤t,CCREG);
9346 alloc_reg(¤t,i,CSREG);
9347 alloc_reg(¤t,i,FSREG);
9353 imm16_alloc(¤t,i);
9357 load_alloc(¤t,i);
9361 store_alloc(¤t,i);
9364 alu_alloc(¤t,i);
9367 shift_alloc(¤t,i);
9370 multdiv_alloc(¤t,i);
9373 shiftimm_alloc(¤t,i);
9376 mov_alloc(¤t,i);
9379 cop0_alloc(¤t,i);
9383 cop1_alloc(¤t,i);
9386 c1ls_alloc(¤t,i);
9389 c2ls_alloc(¤t,i);
9392 c2op_alloc(¤t,i);
9395 fconv_alloc(¤t,i);
9398 float_alloc(¤t,i);
9401 fcomp_alloc(¤t,i);
9406 syscall_alloc(¤t,i);
9409 pagespan_alloc(¤t,i);
9413 // Drop the upper half of registers that have become 32-bit
9414 current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i]));
9415 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
9416 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9417 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9420 current.uu|=current.is32&((1LL<<rt1[i+1])|(1LL<<rt2[i+1]));
9421 current.uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
9422 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
9423 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9427 // Create entry (branch target) regmap
9428 for(hr=0;hr<HOST_REGS;hr++)
9431 r=current.regmap[hr];
9433 if(r!=regmap_pre[i][hr]) {
9434 // TODO: delay slot (?)
9435 or=get_reg(regmap_pre[i],r); // Get old mapping for this register
9436 if(or<0||(r&63)>=TEMPREG){
9437 regs[i].regmap_entry[hr]=-1;
9441 // Just move it to a different register
9442 regs[i].regmap_entry[hr]=r;
9443 // If it was dirty before, it's still dirty
9444 if((regs[i].wasdirty>>or)&1) dirty_reg(¤t,r&63);
9451 regs[i].regmap_entry[hr]=0;
9455 if((current.u>>r)&1) {
9456 regs[i].regmap_entry[hr]=-1;
9457 //regs[i].regmap[hr]=-1;
9458 current.regmap[hr]=-1;
9460 regs[i].regmap_entry[hr]=r;
9463 if((current.uu>>(r&63))&1) {
9464 regs[i].regmap_entry[hr]=-1;
9465 //regs[i].regmap[hr]=-1;
9466 current.regmap[hr]=-1;
9468 regs[i].regmap_entry[hr]=r;
9472 // Branches expect CCREG to be allocated at the target
9473 if(regmap_pre[i][hr]==CCREG)
9474 regs[i].regmap_entry[hr]=CCREG;
9476 regs[i].regmap_entry[hr]=-1;
9479 memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
9482 if(i>0&&(itype[i-1]==STORE||itype[i-1]==STORELR||(itype[i-1]==C2LS&&opcode[i-1]==0x3a))&&(u_int)imm[i-1]<0x800)
9483 current.waswritten|=1<<rs1[i-1];
9484 current.waswritten&=~(1<<rt1[i]);
9485 current.waswritten&=~(1<<rt2[i]);
9486 if((itype[i]==STORE||itype[i]==STORELR||(itype[i]==C2LS&&opcode[i]==0x3a))&&(u_int)imm[i]>=0x800)
9487 current.waswritten&=~(1<<rs1[i]);
9489 /* Branch post-alloc */
9492 current.was32=current.is32;
9493 current.wasdirty=current.dirty;
9494 switch(itype[i-1]) {
9496 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9497 branch_regs[i-1].isconst=0;
9498 branch_regs[i-1].wasconst=0;
9499 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9500 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9501 alloc_cc(&branch_regs[i-1],i-1);
9502 dirty_reg(&branch_regs[i-1],CCREG);
9503 if(rt1[i-1]==31) { // JAL
9504 alloc_reg(&branch_regs[i-1],i-1,31);
9505 dirty_reg(&branch_regs[i-1],31);
9506 branch_regs[i-1].is32|=1LL<<31;
9508 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9509 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9512 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9513 branch_regs[i-1].isconst=0;
9514 branch_regs[i-1].wasconst=0;
9515 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9516 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9517 alloc_cc(&branch_regs[i-1],i-1);
9518 dirty_reg(&branch_regs[i-1],CCREG);
9519 alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]);
9520 if(rt1[i-1]!=0) { // JALR
9521 alloc_reg(&branch_regs[i-1],i-1,rt1[i-1]);
9522 dirty_reg(&branch_regs[i-1],rt1[i-1]);
9523 branch_regs[i-1].is32|=1LL<<rt1[i-1];
9526 if(rs1[i-1]==31) { // JALR
9527 alloc_reg(&branch_regs[i-1],i-1,RHASH);
9528 #ifndef HOST_IMM_ADDR32
9529 alloc_reg(&branch_regs[i-1],i-1,RHTBL);
9533 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9534 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9537 if((opcode[i-1]&0x3E)==4) // BEQ/BNE
9539 alloc_cc(¤t,i-1);
9540 dirty_reg(¤t,CCREG);
9541 if((rs1[i-1]&&(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]))||
9542 (rs2[i-1]&&(rs2[i-1]==rt1[i]||rs2[i-1]==rt2[i]))) {
9543 // The delay slot overwrote one of our conditions
9544 // Delay slot goes after the test (in order)
9545 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9546 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9547 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9550 delayslot_alloc(¤t,i);
9555 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9556 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9557 // Alloc the branch condition registers
9558 if(rs1[i-1]) alloc_reg(¤t,i-1,rs1[i-1]);
9559 if(rs2[i-1]) alloc_reg(¤t,i-1,rs2[i-1]);
9560 if(!((current.is32>>rs1[i-1])&(current.is32>>rs2[i-1])&1))
9562 if(rs1[i-1]) alloc_reg64(¤t,i-1,rs1[i-1]);
9563 if(rs2[i-1]) alloc_reg64(¤t,i-1,rs2[i-1]);
9566 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9567 branch_regs[i-1].isconst=0;
9568 branch_regs[i-1].wasconst=0;
9569 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9570 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9573 if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ
9575 alloc_cc(¤t,i-1);
9576 dirty_reg(¤t,CCREG);
9577 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9578 // The delay slot overwrote the branch condition
9579 // Delay slot goes after the test (in order)
9580 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9581 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9582 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9585 delayslot_alloc(¤t,i);
9590 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9591 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9592 // Alloc the branch condition register
9593 alloc_reg(¤t,i-1,rs1[i-1]);
9594 if(!(current.is32>>rs1[i-1]&1))
9596 alloc_reg64(¤t,i-1,rs1[i-1]);
9599 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9600 branch_regs[i-1].isconst=0;
9601 branch_regs[i-1].wasconst=0;
9602 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9603 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9606 // Alloc the delay slot in case the branch is taken
9607 if((opcode[i-1]&0x3E)==0x14) // BEQL/BNEL
9609 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9610 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9611 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9612 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9613 alloc_cc(&branch_regs[i-1],i);
9614 dirty_reg(&branch_regs[i-1],CCREG);
9615 delayslot_alloc(&branch_regs[i-1],i);
9616 branch_regs[i-1].isconst=0;
9617 alloc_reg(¤t,i,CCREG); // Not taken path
9618 dirty_reg(¤t,CCREG);
9619 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9622 if((opcode[i-1]&0x3E)==0x16) // BLEZL/BGTZL
9624 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9625 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9626 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9627 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9628 alloc_cc(&branch_regs[i-1],i);
9629 dirty_reg(&branch_regs[i-1],CCREG);
9630 delayslot_alloc(&branch_regs[i-1],i);
9631 branch_regs[i-1].isconst=0;
9632 alloc_reg(¤t,i,CCREG); // Not taken path
9633 dirty_reg(¤t,CCREG);
9634 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9638 //if((opcode2[i-1]&0x1E)==0) // BLTZ/BGEZ
9639 if((opcode2[i-1]&0x0E)==0) // BLTZ/BGEZ
9641 alloc_cc(¤t,i-1);
9642 dirty_reg(¤t,CCREG);
9643 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9644 // The delay slot overwrote the branch condition
9645 // Delay slot goes after the test (in order)
9646 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9647 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9648 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9651 delayslot_alloc(¤t,i);
9656 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9657 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9658 // Alloc the branch condition register
9659 alloc_reg(¤t,i-1,rs1[i-1]);
9660 if(!(current.is32>>rs1[i-1]&1))
9662 alloc_reg64(¤t,i-1,rs1[i-1]);
9665 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9666 branch_regs[i-1].isconst=0;
9667 branch_regs[i-1].wasconst=0;
9668 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9669 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9672 // Alloc the delay slot in case the branch is taken
9673 if((opcode2[i-1]&0x1E)==2) // BLTZL/BGEZL
9675 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9676 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9677 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9678 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9679 alloc_cc(&branch_regs[i-1],i);
9680 dirty_reg(&branch_regs[i-1],CCREG);
9681 delayslot_alloc(&branch_regs[i-1],i);
9682 branch_regs[i-1].isconst=0;
9683 alloc_reg(¤t,i,CCREG); // Not taken path
9684 dirty_reg(¤t,CCREG);
9685 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9687 // FIXME: BLTZAL/BGEZAL
9688 if(opcode2[i-1]&0x10) { // BxxZAL
9689 alloc_reg(&branch_regs[i-1],i-1,31);
9690 dirty_reg(&branch_regs[i-1],31);
9691 branch_regs[i-1].is32|=1LL<<31;
9695 if(likely[i-1]==0) // BC1F/BC1T
9697 alloc_cc(¤t,i-1);
9698 dirty_reg(¤t,CCREG);
9699 if(itype[i]==FCOMP) {
9700 // The delay slot overwrote the branch condition
9701 // Delay slot goes after the test (in order)
9702 delayslot_alloc(¤t,i);
9707 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9708 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9709 // Alloc the branch condition register
9710 alloc_reg(¤t,i-1,FSREG);
9712 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9713 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9717 // Alloc the delay slot in case the branch is taken
9718 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9719 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9720 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9721 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9722 alloc_cc(&branch_regs[i-1],i);
9723 dirty_reg(&branch_regs[i-1],CCREG);
9724 delayslot_alloc(&branch_regs[i-1],i);
9725 branch_regs[i-1].isconst=0;
9726 alloc_reg(¤t,i,CCREG); // Not taken path
9727 dirty_reg(¤t,CCREG);
9728 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9733 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
9735 if(rt1[i-1]==31) // JAL/JALR
9737 // Subroutine call will return here, don't alloc any registers
9740 clear_all_regs(current.regmap);
9741 alloc_reg(¤t,i,CCREG);
9742 dirty_reg(¤t,CCREG);
9746 // Internal branch will jump here, match registers to caller
9747 current.is32=0x3FFFFFFFFLL;
9749 clear_all_regs(current.regmap);
9750 alloc_reg(¤t,i,CCREG);
9751 dirty_reg(¤t,CCREG);
9754 if(ba[j]==start+i*4+4) {
9755 memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
9756 current.is32=branch_regs[j].is32;
9757 current.dirty=branch_regs[j].dirty;
9762 if(ba[j]==start+i*4+4) {
9763 for(hr=0;hr<HOST_REGS;hr++) {
9764 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
9765 current.regmap[hr]=-1;
9767 current.is32&=branch_regs[j].is32;
9768 current.dirty&=branch_regs[j].dirty;
9777 // Count cycles in between branches
9779 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP||itype[i]==SYSCALL||itype[i]==HLECALL))
9784 else if(itype[i]==C2OP&>e_cycletab[source[i]&0x3f]>2)
9786 // GTE runs in parallel until accessed, divide by 2 for a rough guess
9787 cc+=gte_cycletab[source[i]&0x3f]/2;
9789 else if(/*itype[i]==LOAD||*/itype[i]==STORE||itype[i]==C1LS) // load causes weird timing issues
9791 cc+=2; // 2 cycle penalty (after CLOCK_DIVIDER)
9793 else if(itype[i]==C2LS)
9803 flush_dirty_uppers(¤t);
9805 regs[i].is32=current.is32;
9806 regs[i].dirty=current.dirty;
9807 regs[i].isconst=current.isconst;
9808 memcpy(constmap[i],current.constmap,sizeof(current.constmap));
9810 for(hr=0;hr<HOST_REGS;hr++) {
9811 if(hr!=EXCLUDE_REG&®s[i].regmap[hr]>=0) {
9812 if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
9813 regs[i].wasconst&=~(1<<hr);
9817 if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
9818 regs[i].waswritten=current.waswritten;
9821 /* Pass 4 - Cull unused host registers */
9825 for (i=slen-1;i>=0;i--)
9828 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9830 if(ba[i]<start || ba[i]>=(start+slen*4))
9832 // Branch out of this block, don't need anything
9838 // Need whatever matches the target
9840 int t=(ba[i]-start)>>2;
9841 for(hr=0;hr<HOST_REGS;hr++)
9843 if(regs[i].regmap_entry[hr]>=0) {
9844 if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
9848 // Conditional branch may need registers for following instructions
9849 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9852 nr|=needed_reg[i+2];
9853 for(hr=0;hr<HOST_REGS;hr++)
9855 if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
9856 //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
9860 // Don't need stuff which is overwritten
9861 //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9862 //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9863 // Merge in delay slot
9864 for(hr=0;hr<HOST_REGS;hr++)
9867 // These are overwritten unless the branch is "likely"
9868 // and the delay slot is nullified if not taken
9869 if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9870 if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9872 if(us1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9873 if(us2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9874 if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9875 if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9876 if(us1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9877 if(us2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9878 if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9879 if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9880 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1)) {
9881 if(dep1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9882 if(dep2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9884 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1)) {
9885 if(dep1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9886 if(dep2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9888 if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) {
9889 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9890 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9894 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
9896 // SYSCALL instruction (software interrupt)
9899 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
9901 // ERET instruction (return from interrupt)
9907 for(hr=0;hr<HOST_REGS;hr++) {
9908 if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
9909 if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
9910 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9911 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9915 for(hr=0;hr<HOST_REGS;hr++)
9917 // Overwritten registers are not needed
9918 if(rt1[i]&&rt1[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9919 if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9920 if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9921 // Source registers are needed
9922 if(us1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9923 if(us2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9924 if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr;
9925 if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr;
9926 if(us1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9927 if(us2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9928 if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9929 if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9930 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1)) {
9931 if(dep1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9932 if(dep1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9934 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1)) {
9935 if(dep2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9936 if(dep2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9938 if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) {
9939 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9940 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9942 // Don't store a register immediately after writing it,
9943 // may prevent dual-issue.
9944 // But do so if this is a branch target, otherwise we
9945 // might have to load the register before the branch.
9946 if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) {
9947 if((regmap_pre[i][hr]>0&®map_pre[i][hr]<64&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1)) ||
9948 (regmap_pre[i][hr]>64&&!((unneeded_reg_upper[i]>>(regmap_pre[i][hr]&63))&1)) ) {
9949 if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9950 if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9952 if((regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1)) ||
9953 (regs[i].regmap_entry[hr]>64&&!((unneeded_reg_upper[i]>>(regs[i].regmap_entry[hr]&63))&1)) ) {
9954 if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9955 if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9959 // Cycle count is needed at branches. Assume it is needed at the target too.
9960 if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==FJUMP||itype[i]==SPAN) {
9961 if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9962 if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9967 // Deallocate unneeded registers
9968 for(hr=0;hr<HOST_REGS;hr++)
9971 if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
9972 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9973 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9974 (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG)
9976 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9979 regs[i].regmap[hr]=-1;
9980 regs[i].isconst&=~(1<<hr);
9982 regmap_pre[i+2][hr]=-1;
9983 regs[i+2].wasconst&=~(1<<hr);
9988 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9990 int d1=0,d2=0,map=0,temp=0;
9991 if(get_reg(regs[i].regmap,rt1[i+1]|64)>=0||get_reg(branch_regs[i].regmap,rt1[i+1]|64)>=0)
9997 if(itype[i+1]==LOAD || itype[i+1]==LOADLR ||
9998 itype[i+1]==STORE || itype[i+1]==STORELR ||
9999 itype[i+1]==C1LS || itype[i+1]==C2LS)
10002 if(itype[i+1]==STORE || itype[i+1]==STORELR ||
10003 (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
10006 if(itype[i+1]==LOADLR || itype[i+1]==STORELR ||
10007 itype[i+1]==C1LS || itype[i+1]==C2LS)
10009 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
10010 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
10011 (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] &&
10012 (regs[i].regmap[hr]^64)!=us1[i+1] && (regs[i].regmap[hr]^64)!=us2[i+1] &&
10013 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
10014 regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] &&
10015 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
10016 regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
10017 regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
10018 regs[i].regmap[hr]!=map )
10020 regs[i].regmap[hr]=-1;
10021 regs[i].isconst&=~(1<<hr);
10022 if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] &&
10023 (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] &&
10024 (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] &&
10025 (branch_regs[i].regmap[hr]^64)!=us1[i+1] && (branch_regs[i].regmap[hr]^64)!=us2[i+1] &&
10026 (branch_regs[i].regmap[hr]^64)!=d1 && (branch_regs[i].regmap[hr]^64)!=d2 &&
10027 branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] &&
10028 (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
10029 branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
10030 branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
10031 branch_regs[i].regmap[hr]!=map)
10033 branch_regs[i].regmap[hr]=-1;
10034 branch_regs[i].regmap_entry[hr]=-1;
10035 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10037 if(!likely[i]&&i<slen-2) {
10038 regmap_pre[i+2][hr]=-1;
10039 regs[i+2].wasconst&=~(1<<hr);
10050 int d1=0,d2=0,map=-1,temp=-1;
10051 if(get_reg(regs[i].regmap,rt1[i]|64)>=0)
10057 if(itype[i]==LOAD || itype[i]==LOADLR ||
10058 itype[i]==STORE || itype[i]==STORELR ||
10059 itype[i]==C1LS || itype[i]==C2LS)
10061 } else if(itype[i]==STORE || itype[i]==STORELR ||
10062 (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
10065 if(itype[i]==LOADLR || itype[i]==STORELR ||
10066 itype[i]==C1LS || itype[i]==C2LS)
10068 if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
10069 (regs[i].regmap[hr]^64)!=us1[i] && (regs[i].regmap[hr]^64)!=us2[i] &&
10070 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
10071 regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] &&
10072 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map &&
10073 (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG))
10075 if(i<slen-1&&!is_ds[i]) {
10076 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]!=-1)
10077 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
10078 if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
10080 printf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
10081 assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
10083 regmap_pre[i+1][hr]=-1;
10084 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
10085 regs[i+1].wasconst&=~(1<<hr);
10087 regs[i].regmap[hr]=-1;
10088 regs[i].isconst&=~(1<<hr);
10096 /* Pass 5 - Pre-allocate registers */
10098 // If a register is allocated during a loop, try to allocate it for the
10099 // entire loop, if possible. This avoids loading/storing registers
10100 // inside of the loop.
10102 signed char f_regmap[HOST_REGS];
10103 clear_all_regs(f_regmap);
10104 for(i=0;i<slen-1;i++)
10106 if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10108 if(ba[i]>=start && ba[i]<(start+i*4))
10109 if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
10110 ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
10111 ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
10112 ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
10113 ||itype[i+1]==FCOMP||itype[i+1]==FCONV
10114 ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
10116 int t=(ba[i]-start)>>2;
10117 if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots
10118 if(t<2||(itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||rt1[t-2]!=31) // call/ret assumes no registers allocated
10119 for(hr=0;hr<HOST_REGS;hr++)
10121 if(regs[i].regmap[hr]>64) {
10122 if(!((regs[i].dirty>>hr)&1))
10123 f_regmap[hr]=regs[i].regmap[hr];
10124 else f_regmap[hr]=-1;
10126 else if(regs[i].regmap[hr]>=0) {
10127 if(f_regmap[hr]!=regs[i].regmap[hr]) {
10128 // dealloc old register
10130 for(n=0;n<HOST_REGS;n++)
10132 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
10134 // and alloc new one
10135 f_regmap[hr]=regs[i].regmap[hr];
10138 if(branch_regs[i].regmap[hr]>64) {
10139 if(!((branch_regs[i].dirty>>hr)&1))
10140 f_regmap[hr]=branch_regs[i].regmap[hr];
10141 else f_regmap[hr]=-1;
10143 else if(branch_regs[i].regmap[hr]>=0) {
10144 if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
10145 // dealloc old register
10147 for(n=0;n<HOST_REGS;n++)
10149 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
10151 // and alloc new one
10152 f_regmap[hr]=branch_regs[i].regmap[hr];
10156 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
10157 f_regmap[hr]=branch_regs[i].regmap[hr];
10159 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
10160 f_regmap[hr]=branch_regs[i].regmap[hr];
10162 // Avoid dirty->clean transition
10163 #ifdef DESTRUCTIVE_WRITEBACK
10164 if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
10166 // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
10167 // case above, however it's always a good idea. We can't hoist the
10168 // load if the register was already allocated, so there's no point
10169 // wasting time analyzing most of these cases. It only "succeeds"
10170 // when the mapping was different and the load can be replaced with
10171 // a mov, which is of negligible benefit. So such cases are
10173 if(f_regmap[hr]>0) {
10174 if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
10175 int r=f_regmap[hr];
10178 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
10179 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
10180 if(r>63&&((unneeded_reg_upper[j]>>(r&63))&1)) break;
10182 // NB This can exclude the case where the upper-half
10183 // register is lower numbered than the lower-half
10184 // register. Not sure if it's worth fixing...
10185 if(get_reg(regs[j].regmap,r&63)<0) break;
10186 if(get_reg(regs[j].regmap_entry,r&63)<0) break;
10187 if(regs[j].is32&(1LL<<(r&63))) break;
10189 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
10190 //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
10192 if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
10193 if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
10195 if(get_reg(regs[i].regmap,r&63)<0) break;
10196 if(get_reg(branch_regs[i].regmap,r&63)<0) break;
10199 while(k>1&®s[k-1].regmap[hr]==-1) {
10200 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10201 //printf("no free regs for store %x\n",start+(k-1)*4);
10204 if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
10205 //printf("no-match due to different register\n");
10208 if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP||itype[k-2]==FJUMP) {
10209 //printf("no-match due to branch\n");
10212 // call/ret fast path assumes no registers allocated
10213 if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)&&rt1[k-3]==31) {
10217 // NB This can exclude the case where the upper-half
10218 // register is lower numbered than the lower-half
10219 // register. Not sure if it's worth fixing...
10220 if(get_reg(regs[k-1].regmap,r&63)<0) break;
10221 if(regs[k-1].is32&(1LL<<(r&63))) break;
10226 if((regs[k].is32&(1LL<<f_regmap[hr]))!=
10227 (regs[i+2].was32&(1LL<<f_regmap[hr]))) {
10228 //printf("bad match after branch\n");
10232 if(regs[k-1].regmap[hr]==f_regmap[hr]&®map_pre[k][hr]==f_regmap[hr]) {
10233 //printf("Extend r%d, %x ->\n",hr,start+k*4);
10235 regs[k].regmap_entry[hr]=f_regmap[hr];
10236 regs[k].regmap[hr]=f_regmap[hr];
10237 regmap_pre[k+1][hr]=f_regmap[hr];
10238 regs[k].wasdirty&=~(1<<hr);
10239 regs[k].dirty&=~(1<<hr);
10240 regs[k].wasdirty|=(1<<hr)®s[k-1].dirty;
10241 regs[k].dirty|=(1<<hr)®s[k].wasdirty;
10242 regs[k].wasconst&=~(1<<hr);
10243 regs[k].isconst&=~(1<<hr);
10248 //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
10251 assert(regs[i-1].regmap[hr]==f_regmap[hr]);
10252 if(regs[i-1].regmap[hr]==f_regmap[hr]&®map_pre[i][hr]==f_regmap[hr]) {
10253 //printf("OK fill %x (r%d)\n",start+i*4,hr);
10254 regs[i].regmap_entry[hr]=f_regmap[hr];
10255 regs[i].regmap[hr]=f_regmap[hr];
10256 regs[i].wasdirty&=~(1<<hr);
10257 regs[i].dirty&=~(1<<hr);
10258 regs[i].wasdirty|=(1<<hr)®s[i-1].dirty;
10259 regs[i].dirty|=(1<<hr)®s[i-1].dirty;
10260 regs[i].wasconst&=~(1<<hr);
10261 regs[i].isconst&=~(1<<hr);
10262 branch_regs[i].regmap_entry[hr]=f_regmap[hr];
10263 branch_regs[i].wasdirty&=~(1<<hr);
10264 branch_regs[i].wasdirty|=(1<<hr)®s[i].dirty;
10265 branch_regs[i].regmap[hr]=f_regmap[hr];
10266 branch_regs[i].dirty&=~(1<<hr);
10267 branch_regs[i].dirty|=(1<<hr)®s[i].dirty;
10268 branch_regs[i].wasconst&=~(1<<hr);
10269 branch_regs[i].isconst&=~(1<<hr);
10270 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
10271 regmap_pre[i+2][hr]=f_regmap[hr];
10272 regs[i+2].wasdirty&=~(1<<hr);
10273 regs[i+2].wasdirty|=(1<<hr)®s[i].dirty;
10274 assert((branch_regs[i].is32&(1LL<<f_regmap[hr]))==
10275 (regs[i+2].was32&(1LL<<f_regmap[hr])));
10280 // Alloc register clean at beginning of loop,
10281 // but may dirty it in pass 6
10282 regs[k].regmap_entry[hr]=f_regmap[hr];
10283 regs[k].regmap[hr]=f_regmap[hr];
10284 regs[k].dirty&=~(1<<hr);
10285 regs[k].wasconst&=~(1<<hr);
10286 regs[k].isconst&=~(1<<hr);
10287 if(itype[k]==UJUMP||itype[k]==RJUMP||itype[k]==CJUMP||itype[k]==SJUMP||itype[k]==FJUMP) {
10288 branch_regs[k].regmap_entry[hr]=f_regmap[hr];
10289 branch_regs[k].regmap[hr]=f_regmap[hr];
10290 branch_regs[k].dirty&=~(1<<hr);
10291 branch_regs[k].wasconst&=~(1<<hr);
10292 branch_regs[k].isconst&=~(1<<hr);
10293 if(itype[k]!=RJUMP&&itype[k]!=UJUMP&&(source[k]>>16)!=0x1000) {
10294 regmap_pre[k+2][hr]=f_regmap[hr];
10295 regs[k+2].wasdirty&=~(1<<hr);
10296 assert((branch_regs[k].is32&(1LL<<f_regmap[hr]))==
10297 (regs[k+2].was32&(1LL<<f_regmap[hr])));
10302 regmap_pre[k+1][hr]=f_regmap[hr];
10303 regs[k+1].wasdirty&=~(1<<hr);
10306 if(regs[j].regmap[hr]==f_regmap[hr])
10307 regs[j].regmap_entry[hr]=f_regmap[hr];
10311 if(regs[j].regmap[hr]>=0)
10313 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
10314 //printf("no-match due to different register\n");
10317 if((regs[j+1].is32&(1LL<<f_regmap[hr]))!=(regs[j].is32&(1LL<<f_regmap[hr]))) {
10318 //printf("32/64 mismatch %x %d\n",start+j*4,hr);
10321 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10323 // Stop on unconditional branch
10326 if(itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP)
10329 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
10332 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
10335 if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
10336 //printf("no-match due to different register (branch)\n");
10340 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10341 //printf("No free regs for store %x\n",start+j*4);
10344 if(f_regmap[hr]>=64) {
10345 if(regs[j].is32&(1LL<<(f_regmap[hr]&63))) {
10350 if(get_reg(regs[j].regmap,f_regmap[hr]&63)<0) {
10361 // Non branch or undetermined branch target
10362 for(hr=0;hr<HOST_REGS;hr++)
10364 if(hr!=EXCLUDE_REG) {
10365 if(regs[i].regmap[hr]>64) {
10366 if(!((regs[i].dirty>>hr)&1))
10367 f_regmap[hr]=regs[i].regmap[hr];
10369 else if(regs[i].regmap[hr]>=0) {
10370 if(f_regmap[hr]!=regs[i].regmap[hr]) {
10371 // dealloc old register
10373 for(n=0;n<HOST_REGS;n++)
10375 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
10377 // and alloc new one
10378 f_regmap[hr]=regs[i].regmap[hr];
10383 // Try to restore cycle count at branch targets
10385 for(j=i;j<slen-1;j++) {
10386 if(regs[j].regmap[HOST_CCREG]!=-1) break;
10387 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10388 //printf("no free regs for store %x\n",start+j*4);
10392 if(regs[j].regmap[HOST_CCREG]==CCREG) {
10394 //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
10396 regs[k].regmap_entry[HOST_CCREG]=CCREG;
10397 regs[k].regmap[HOST_CCREG]=CCREG;
10398 regmap_pre[k+1][HOST_CCREG]=CCREG;
10399 regs[k+1].wasdirty|=1<<HOST_CCREG;
10400 regs[k].dirty|=1<<HOST_CCREG;
10401 regs[k].wasconst&=~(1<<HOST_CCREG);
10402 regs[k].isconst&=~(1<<HOST_CCREG);
10405 regs[j].regmap_entry[HOST_CCREG]=CCREG;
10407 // Work backwards from the branch target
10408 if(j>i&&f_regmap[HOST_CCREG]==CCREG)
10410 //printf("Extend backwards\n");
10413 while(regs[k-1].regmap[HOST_CCREG]==-1) {
10414 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10415 //printf("no free regs for store %x\n",start+(k-1)*4);
10420 if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
10421 //printf("Extend CC, %x ->\n",start+k*4);
10423 regs[k].regmap_entry[HOST_CCREG]=CCREG;
10424 regs[k].regmap[HOST_CCREG]=CCREG;
10425 regmap_pre[k+1][HOST_CCREG]=CCREG;
10426 regs[k+1].wasdirty|=1<<HOST_CCREG;
10427 regs[k].dirty|=1<<HOST_CCREG;
10428 regs[k].wasconst&=~(1<<HOST_CCREG);
10429 regs[k].isconst&=~(1<<HOST_CCREG);
10434 //printf("Fail Extend CC, %x ->\n",start+k*4);
10438 if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&&
10439 itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&&
10440 itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1&&itype[i]!=FLOAT&&
10441 itype[i]!=FCONV&&itype[i]!=FCOMP)
10443 memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
10448 // Cache memory offset or tlb map pointer if a register is available
10449 #ifndef HOST_IMM_ADDR32
10454 int earliest_available[HOST_REGS];
10455 int loop_start[HOST_REGS];
10456 int score[HOST_REGS];
10457 int end[HOST_REGS];
10458 int reg=using_tlb?MMREG:ROREG;
10461 for(hr=0;hr<HOST_REGS;hr++) {
10462 score[hr]=0;earliest_available[hr]=0;
10463 loop_start[hr]=MAXBLOCK;
10465 for(i=0;i<slen-1;i++)
10467 // Can't do anything if no registers are available
10468 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i]) {
10469 for(hr=0;hr<HOST_REGS;hr++) {
10470 score[hr]=0;earliest_available[hr]=i+1;
10471 loop_start[hr]=MAXBLOCK;
10474 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10476 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1]) {
10477 for(hr=0;hr<HOST_REGS;hr++) {
10478 score[hr]=0;earliest_available[hr]=i+1;
10479 loop_start[hr]=MAXBLOCK;
10483 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1]) {
10484 for(hr=0;hr<HOST_REGS;hr++) {
10485 score[hr]=0;earliest_available[hr]=i+1;
10486 loop_start[hr]=MAXBLOCK;
10491 // Mark unavailable registers
10492 for(hr=0;hr<HOST_REGS;hr++) {
10493 if(regs[i].regmap[hr]>=0) {
10494 score[hr]=0;earliest_available[hr]=i+1;
10495 loop_start[hr]=MAXBLOCK;
10497 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10498 if(branch_regs[i].regmap[hr]>=0) {
10499 score[hr]=0;earliest_available[hr]=i+2;
10500 loop_start[hr]=MAXBLOCK;
10504 // No register allocations after unconditional jumps
10505 if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
10507 for(hr=0;hr<HOST_REGS;hr++) {
10508 score[hr]=0;earliest_available[hr]=i+2;
10509 loop_start[hr]=MAXBLOCK;
10511 i++; // Skip delay slot too
10512 //printf("skip delay slot: %x\n",start+i*4);
10516 if(itype[i]==LOAD||itype[i]==LOADLR||
10517 itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS) {
10518 for(hr=0;hr<HOST_REGS;hr++) {
10519 if(hr!=EXCLUDE_REG) {
10521 for(j=i;j<slen-1;j++) {
10522 if(regs[j].regmap[hr]>=0) break;
10523 if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10524 if(branch_regs[j].regmap[hr]>=0) break;
10526 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1]) break;
10528 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1]) break;
10531 else if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) break;
10532 if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10533 int t=(ba[j]-start)>>2;
10534 if(t<j&&t>=earliest_available[hr]) {
10535 if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) { // call/ret assumes no registers allocated
10536 // Score a point for hoisting loop invariant
10537 if(t<loop_start[hr]) loop_start[hr]=t;
10538 //printf("set loop_start: i=%x j=%x (%x)\n",start+i*4,start+j*4,start+t*4);
10544 if(regs[t].regmap[hr]==reg) {
10545 // Score a point if the branch target matches this register
10550 if(itype[j+1]==LOAD||itype[j+1]==LOADLR||
10551 itype[j+1]==STORE||itype[j+1]==STORELR||itype[j+1]==C1LS) {
10556 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10558 // Stop on unconditional branch
10562 if(itype[j]==LOAD||itype[j]==LOADLR||
10563 itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS) {
10570 // Find highest score and allocate that register
10572 for(hr=0;hr<HOST_REGS;hr++) {
10573 if(hr!=EXCLUDE_REG) {
10574 if(score[hr]>score[maxscore]) {
10576 //printf("highest score: %d %d (%x->%x)\n",score[hr],hr,start+i*4,start+end[hr]*4);
10580 if(score[maxscore]>1)
10582 if(i<loop_start[maxscore]) loop_start[maxscore]=i;
10583 for(j=loop_start[maxscore];j<slen&&j<=end[maxscore];j++) {
10584 //if(regs[j].regmap[maxscore]>=0) {printf("oops: %x %x was %d=%d\n",loop_start[maxscore]*4+start,j*4+start,maxscore,regs[j].regmap[maxscore]);}
10585 assert(regs[j].regmap[maxscore]<0);
10586 if(j>loop_start[maxscore]) regs[j].regmap_entry[maxscore]=reg;
10587 regs[j].regmap[maxscore]=reg;
10588 regs[j].dirty&=~(1<<maxscore);
10589 regs[j].wasconst&=~(1<<maxscore);
10590 regs[j].isconst&=~(1<<maxscore);
10591 if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10592 branch_regs[j].regmap[maxscore]=reg;
10593 branch_regs[j].wasdirty&=~(1<<maxscore);
10594 branch_regs[j].dirty&=~(1<<maxscore);
10595 branch_regs[j].wasconst&=~(1<<maxscore);
10596 branch_regs[j].isconst&=~(1<<maxscore);
10597 if(itype[j]!=RJUMP&&itype[j]!=UJUMP&&(source[j]>>16)!=0x1000) {
10598 regmap_pre[j+2][maxscore]=reg;
10599 regs[j+2].wasdirty&=~(1<<maxscore);
10601 // loop optimization (loop_preload)
10602 int t=(ba[j]-start)>>2;
10603 if(t==loop_start[maxscore]) {
10604 if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) // call/ret assumes no registers allocated
10605 regs[t].regmap_entry[maxscore]=reg;
10610 if(j<1||(itype[j-1]!=RJUMP&&itype[j-1]!=UJUMP&&itype[j-1]!=CJUMP&&itype[j-1]!=SJUMP&&itype[j-1]!=FJUMP)) {
10611 regmap_pre[j+1][maxscore]=reg;
10612 regs[j+1].wasdirty&=~(1<<maxscore);
10617 if(itype[j-1]==RJUMP||itype[j-1]==UJUMP||itype[j-1]==CJUMP||itype[j-1]==SJUMP||itype[j-1]==FJUMP) i++; // skip delay slot
10618 for(hr=0;hr<HOST_REGS;hr++) {
10619 score[hr]=0;earliest_available[hr]=i+i;
10620 loop_start[hr]=MAXBLOCK;
10628 // This allocates registers (if possible) one instruction prior
10629 // to use, which can avoid a load-use penalty on certain CPUs.
10630 for(i=0;i<slen-1;i++)
10632 if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP))
10636 if(itype[i]==ALU||itype[i]==MOV||itype[i]==LOAD||itype[i]==SHIFTIMM||itype[i]==IMM16
10637 ||((itype[i]==COP1||itype[i]==COP2)&&opcode2[i]<3))
10640 if((hr=get_reg(regs[i+1].regmap,rs1[i+1]))>=0)
10642 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10644 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10645 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10646 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10647 regs[i].isconst&=~(1<<hr);
10648 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10649 constmap[i][hr]=constmap[i+1][hr];
10650 regs[i+1].wasdirty&=~(1<<hr);
10651 regs[i].dirty&=~(1<<hr);
10656 if((hr=get_reg(regs[i+1].regmap,rs2[i+1]))>=0)
10658 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10660 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10661 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10662 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10663 regs[i].isconst&=~(1<<hr);
10664 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10665 constmap[i][hr]=constmap[i+1][hr];
10666 regs[i+1].wasdirty&=~(1<<hr);
10667 regs[i].dirty&=~(1<<hr);
10671 // Preload target address for load instruction (non-constant)
10672 if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10673 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10675 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10677 regs[i].regmap[hr]=rs1[i+1];
10678 regmap_pre[i+1][hr]=rs1[i+1];
10679 regs[i+1].regmap_entry[hr]=rs1[i+1];
10680 regs[i].isconst&=~(1<<hr);
10681 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10682 constmap[i][hr]=constmap[i+1][hr];
10683 regs[i+1].wasdirty&=~(1<<hr);
10684 regs[i].dirty&=~(1<<hr);
10688 // Load source into target register
10689 if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10690 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10692 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10694 regs[i].regmap[hr]=rs1[i+1];
10695 regmap_pre[i+1][hr]=rs1[i+1];
10696 regs[i+1].regmap_entry[hr]=rs1[i+1];
10697 regs[i].isconst&=~(1<<hr);
10698 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10699 constmap[i][hr]=constmap[i+1][hr];
10700 regs[i+1].wasdirty&=~(1<<hr);
10701 regs[i].dirty&=~(1<<hr);
10705 // Preload map address
10706 #ifndef HOST_IMM_ADDR32
10707 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
10708 hr=get_reg(regs[i+1].regmap,TLREG);
10710 int sr=get_reg(regs[i+1].regmap,rs1[i+1]);
10711 if(sr>=0&&((regs[i+1].wasconst>>sr)&1)) {
10713 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10715 regs[i].regmap[hr]=MGEN1+((i+1)&1);
10716 regmap_pre[i+1][hr]=MGEN1+((i+1)&1);
10717 regs[i+1].regmap_entry[hr]=MGEN1+((i+1)&1);
10718 regs[i].isconst&=~(1<<hr);
10719 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10720 constmap[i][hr]=constmap[i+1][hr];
10721 regs[i+1].wasdirty&=~(1<<hr);
10722 regs[i].dirty&=~(1<<hr);
10724 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10726 // move it to another register
10727 regs[i+1].regmap[hr]=-1;
10728 regmap_pre[i+2][hr]=-1;
10729 regs[i+1].regmap[nr]=TLREG;
10730 regmap_pre[i+2][nr]=TLREG;
10731 regs[i].regmap[nr]=MGEN1+((i+1)&1);
10732 regmap_pre[i+1][nr]=MGEN1+((i+1)&1);
10733 regs[i+1].regmap_entry[nr]=MGEN1+((i+1)&1);
10734 regs[i].isconst&=~(1<<nr);
10735 regs[i+1].isconst&=~(1<<nr);
10736 regs[i].dirty&=~(1<<nr);
10737 regs[i+1].wasdirty&=~(1<<nr);
10738 regs[i+1].dirty&=~(1<<nr);
10739 regs[i+2].wasdirty&=~(1<<nr);
10745 // Address for store instruction (non-constant)
10746 if(itype[i+1]==STORE||itype[i+1]==STORELR
10747 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
10748 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10749 hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
10750 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10751 else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
10753 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10755 regs[i].regmap[hr]=rs1[i+1];
10756 regmap_pre[i+1][hr]=rs1[i+1];
10757 regs[i+1].regmap_entry[hr]=rs1[i+1];
10758 regs[i].isconst&=~(1<<hr);
10759 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10760 constmap[i][hr]=constmap[i+1][hr];
10761 regs[i+1].wasdirty&=~(1<<hr);
10762 regs[i].dirty&=~(1<<hr);
10766 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
10767 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10769 hr=get_reg(regs[i+1].regmap,FTEMP);
10771 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10773 regs[i].regmap[hr]=rs1[i+1];
10774 regmap_pre[i+1][hr]=rs1[i+1];
10775 regs[i+1].regmap_entry[hr]=rs1[i+1];
10776 regs[i].isconst&=~(1<<hr);
10777 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10778 constmap[i][hr]=constmap[i+1][hr];
10779 regs[i+1].wasdirty&=~(1<<hr);
10780 regs[i].dirty&=~(1<<hr);
10782 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10784 // move it to another register
10785 regs[i+1].regmap[hr]=-1;
10786 regmap_pre[i+2][hr]=-1;
10787 regs[i+1].regmap[nr]=FTEMP;
10788 regmap_pre[i+2][nr]=FTEMP;
10789 regs[i].regmap[nr]=rs1[i+1];
10790 regmap_pre[i+1][nr]=rs1[i+1];
10791 regs[i+1].regmap_entry[nr]=rs1[i+1];
10792 regs[i].isconst&=~(1<<nr);
10793 regs[i+1].isconst&=~(1<<nr);
10794 regs[i].dirty&=~(1<<nr);
10795 regs[i+1].wasdirty&=~(1<<nr);
10796 regs[i+1].dirty&=~(1<<nr);
10797 regs[i+2].wasdirty&=~(1<<nr);
10801 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS||||itype[i+1]==C2LS*/) {
10802 if(itype[i+1]==LOAD)
10803 hr=get_reg(regs[i+1].regmap,rt1[i+1]);
10804 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
10805 hr=get_reg(regs[i+1].regmap,FTEMP);
10806 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
10807 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
10808 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10810 if(hr>=0&®s[i].regmap[hr]<0) {
10811 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
10812 if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
10813 regs[i].regmap[hr]=AGEN1+((i+1)&1);
10814 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
10815 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
10816 regs[i].isconst&=~(1<<hr);
10817 regs[i+1].wasdirty&=~(1<<hr);
10818 regs[i].dirty&=~(1<<hr);
10827 /* Pass 6 - Optimize clean/dirty state */
10828 clean_registers(0,slen-1,1);
10830 /* Pass 7 - Identify 32-bit registers */
10836 for (i=slen-1;i>=0;i--)
10839 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10841 if(ba[i]<start || ba[i]>=(start+slen*4))
10843 // Branch out of this block, don't need anything
10849 // Need whatever matches the target
10850 // (and doesn't get overwritten by the delay slot instruction)
10852 int t=(ba[i]-start)>>2;
10853 if(ba[i]>start+i*4) {
10855 if(!(requires_32bit[t]&~regs[i].was32))
10856 r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10859 //if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
10860 // r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10861 if(!(pr32[t]&~regs[i].was32))
10862 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10865 // Conditional branch may need registers for following instructions
10866 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10869 r32|=requires_32bit[i+2];
10870 r32&=regs[i].was32;
10871 // Mark this address as a branch target since it may be called
10872 // upon return from interrupt
10876 // Merge in delay slot
10878 // These are overwritten unless the branch is "likely"
10879 // and the delay slot is nullified if not taken
10880 r32&=~(1LL<<rt1[i+1]);
10881 r32&=~(1LL<<rt2[i+1]);
10883 // Assume these are needed (delay slot)
10886 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
10890 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
10892 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
10894 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
10896 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
10898 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
10901 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
10903 // SYSCALL instruction (software interrupt)
10906 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
10908 // ERET instruction (return from interrupt)
10912 r32&=~(1LL<<rt1[i]);
10913 r32&=~(1LL<<rt2[i]);
10916 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
10920 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
10922 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
10924 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
10926 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
10928 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
10930 requires_32bit[i]=r32;
10932 // Dirty registers which are 32-bit, require 32-bit input
10933 // as they will be written as 32-bit values
10934 for(hr=0;hr<HOST_REGS;hr++)
10936 if(regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64) {
10937 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
10938 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
10939 requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
10943 //requires_32bit[i]=is32[i]&~unneeded_reg_upper[i]; // DEBUG
10946 for (i=slen-1;i>=0;i--)
10948 if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10950 // Conditional branch
10951 if((source[i]>>16)!=0x1000&&i<slen-2) {
10952 // Mark this address as a branch target since it may be called
10953 // upon return from interrupt
10960 if(itype[slen-1]==SPAN) {
10961 bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
10965 /* Debug/disassembly */
10966 for(i=0;i<slen;i++)
10970 for(r=1;r<=CCREG;r++) {
10971 if((unneeded_reg[i]>>r)&1) {
10972 if(r==HIREG) printf(" HI");
10973 else if(r==LOREG) printf(" LO");
10974 else printf(" r%d",r);
10979 for(r=1;r<=CCREG;r++) {
10980 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
10981 if(r==HIREG) printf(" HI");
10982 else if(r==LOREG) printf(" LO");
10983 else printf(" r%d",r);
10987 for(r=0;r<=CCREG;r++) {
10988 //if(((is32[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10989 if((regs[i].was32>>r)&1) {
10990 if(r==CCREG) printf(" CC");
10991 else if(r==HIREG) printf(" HI");
10992 else if(r==LOREG) printf(" LO");
10993 else printf(" r%d",r);
10998 #if defined(__i386__) || defined(__x86_64__)
10999 printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
11002 printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
11005 if(needed_reg[i]&1) printf("eax ");
11006 if((needed_reg[i]>>1)&1) printf("ecx ");
11007 if((needed_reg[i]>>2)&1) printf("edx ");
11008 if((needed_reg[i]>>3)&1) printf("ebx ");
11009 if((needed_reg[i]>>5)&1) printf("ebp ");
11010 if((needed_reg[i]>>6)&1) printf("esi ");
11011 if((needed_reg[i]>>7)&1) printf("edi ");
11013 for(r=0;r<=CCREG;r++) {
11014 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
11015 if((requires_32bit[i]>>r)&1) {
11016 if(r==CCREG) printf(" CC");
11017 else if(r==HIREG) printf(" HI");
11018 else if(r==LOREG) printf(" LO");
11019 else printf(" r%d",r);
11024 for(r=0;r<=CCREG;r++) {
11025 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
11026 if((pr32[i]>>r)&1) {
11027 if(r==CCREG) printf(" CC");
11028 else if(r==HIREG) printf(" HI");
11029 else if(r==LOREG) printf(" LO");
11030 else printf(" r%d",r);
11033 if(pr32[i]!=requires_32bit[i]) printf(" OOPS");
11035 #if defined(__i386__) || defined(__x86_64__)
11036 printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
11038 if(regs[i].wasdirty&1) printf("eax ");
11039 if((regs[i].wasdirty>>1)&1) printf("ecx ");
11040 if((regs[i].wasdirty>>2)&1) printf("edx ");
11041 if((regs[i].wasdirty>>3)&1) printf("ebx ");
11042 if((regs[i].wasdirty>>5)&1) printf("ebp ");
11043 if((regs[i].wasdirty>>6)&1) printf("esi ");
11044 if((regs[i].wasdirty>>7)&1) printf("edi ");
11047 printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
11049 if(regs[i].wasdirty&1) printf("r0 ");
11050 if((regs[i].wasdirty>>1)&1) printf("r1 ");
11051 if((regs[i].wasdirty>>2)&1) printf("r2 ");
11052 if((regs[i].wasdirty>>3)&1) printf("r3 ");
11053 if((regs[i].wasdirty>>4)&1) printf("r4 ");
11054 if((regs[i].wasdirty>>5)&1) printf("r5 ");
11055 if((regs[i].wasdirty>>6)&1) printf("r6 ");
11056 if((regs[i].wasdirty>>7)&1) printf("r7 ");
11057 if((regs[i].wasdirty>>8)&1) printf("r8 ");
11058 if((regs[i].wasdirty>>9)&1) printf("r9 ");
11059 if((regs[i].wasdirty>>10)&1) printf("r10 ");
11060 if((regs[i].wasdirty>>12)&1) printf("r12 ");
11063 disassemble_inst(i);
11064 //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
11065 #if defined(__i386__) || defined(__x86_64__)
11066 printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
11067 if(regs[i].dirty&1) printf("eax ");
11068 if((regs[i].dirty>>1)&1) printf("ecx ");
11069 if((regs[i].dirty>>2)&1) printf("edx ");
11070 if((regs[i].dirty>>3)&1) printf("ebx ");
11071 if((regs[i].dirty>>5)&1) printf("ebp ");
11072 if((regs[i].dirty>>6)&1) printf("esi ");
11073 if((regs[i].dirty>>7)&1) printf("edi ");
11076 printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
11077 if(regs[i].dirty&1) printf("r0 ");
11078 if((regs[i].dirty>>1)&1) printf("r1 ");
11079 if((regs[i].dirty>>2)&1) printf("r2 ");
11080 if((regs[i].dirty>>3)&1) printf("r3 ");
11081 if((regs[i].dirty>>4)&1) printf("r4 ");
11082 if((regs[i].dirty>>5)&1) printf("r5 ");
11083 if((regs[i].dirty>>6)&1) printf("r6 ");
11084 if((regs[i].dirty>>7)&1) printf("r7 ");
11085 if((regs[i].dirty>>8)&1) printf("r8 ");
11086 if((regs[i].dirty>>9)&1) printf("r9 ");
11087 if((regs[i].dirty>>10)&1) printf("r10 ");
11088 if((regs[i].dirty>>12)&1) printf("r12 ");
11091 if(regs[i].isconst) {
11092 printf("constants: ");
11093 #if defined(__i386__) || defined(__x86_64__)
11094 if(regs[i].isconst&1) printf("eax=%x ",(int)constmap[i][0]);
11095 if((regs[i].isconst>>1)&1) printf("ecx=%x ",(int)constmap[i][1]);
11096 if((regs[i].isconst>>2)&1) printf("edx=%x ",(int)constmap[i][2]);
11097 if((regs[i].isconst>>3)&1) printf("ebx=%x ",(int)constmap[i][3]);
11098 if((regs[i].isconst>>5)&1) printf("ebp=%x ",(int)constmap[i][5]);
11099 if((regs[i].isconst>>6)&1) printf("esi=%x ",(int)constmap[i][6]);
11100 if((regs[i].isconst>>7)&1) printf("edi=%x ",(int)constmap[i][7]);
11103 if(regs[i].isconst&1) printf("r0=%x ",(int)constmap[i][0]);
11104 if((regs[i].isconst>>1)&1) printf("r1=%x ",(int)constmap[i][1]);
11105 if((regs[i].isconst>>2)&1) printf("r2=%x ",(int)constmap[i][2]);
11106 if((regs[i].isconst>>3)&1) printf("r3=%x ",(int)constmap[i][3]);
11107 if((regs[i].isconst>>4)&1) printf("r4=%x ",(int)constmap[i][4]);
11108 if((regs[i].isconst>>5)&1) printf("r5=%x ",(int)constmap[i][5]);
11109 if((regs[i].isconst>>6)&1) printf("r6=%x ",(int)constmap[i][6]);
11110 if((regs[i].isconst>>7)&1) printf("r7=%x ",(int)constmap[i][7]);
11111 if((regs[i].isconst>>8)&1) printf("r8=%x ",(int)constmap[i][8]);
11112 if((regs[i].isconst>>9)&1) printf("r9=%x ",(int)constmap[i][9]);
11113 if((regs[i].isconst>>10)&1) printf("r10=%x ",(int)constmap[i][10]);
11114 if((regs[i].isconst>>12)&1) printf("r12=%x ",(int)constmap[i][12]);
11120 for(r=0;r<=CCREG;r++) {
11121 if((regs[i].is32>>r)&1) {
11122 if(r==CCREG) printf(" CC");
11123 else if(r==HIREG) printf(" HI");
11124 else if(r==LOREG) printf(" LO");
11125 else printf(" r%d",r);
11131 for(r=0;r<=CCREG;r++) {
11132 if((p32[i]>>r)&1) {
11133 if(r==CCREG) printf(" CC");
11134 else if(r==HIREG) printf(" HI");
11135 else if(r==LOREG) printf(" LO");
11136 else printf(" r%d",r);
11139 if(p32[i]!=regs[i].is32) printf(" NO MATCH\n");
11140 else printf("\n");*/
11141 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
11142 #if defined(__i386__) || defined(__x86_64__)
11143 printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
11144 if(branch_regs[i].dirty&1) printf("eax ");
11145 if((branch_regs[i].dirty>>1)&1) printf("ecx ");
11146 if((branch_regs[i].dirty>>2)&1) printf("edx ");
11147 if((branch_regs[i].dirty>>3)&1) printf("ebx ");
11148 if((branch_regs[i].dirty>>5)&1) printf("ebp ");
11149 if((branch_regs[i].dirty>>6)&1) printf("esi ");
11150 if((branch_regs[i].dirty>>7)&1) printf("edi ");
11153 printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
11154 if(branch_regs[i].dirty&1) printf("r0 ");
11155 if((branch_regs[i].dirty>>1)&1) printf("r1 ");
11156 if((branch_regs[i].dirty>>2)&1) printf("r2 ");
11157 if((branch_regs[i].dirty>>3)&1) printf("r3 ");
11158 if((branch_regs[i].dirty>>4)&1) printf("r4 ");
11159 if((branch_regs[i].dirty>>5)&1) printf("r5 ");
11160 if((branch_regs[i].dirty>>6)&1) printf("r6 ");
11161 if((branch_regs[i].dirty>>7)&1) printf("r7 ");
11162 if((branch_regs[i].dirty>>8)&1) printf("r8 ");
11163 if((branch_regs[i].dirty>>9)&1) printf("r9 ");
11164 if((branch_regs[i].dirty>>10)&1) printf("r10 ");
11165 if((branch_regs[i].dirty>>12)&1) printf("r12 ");
11169 for(r=0;r<=CCREG;r++) {
11170 if((branch_regs[i].is32>>r)&1) {
11171 if(r==CCREG) printf(" CC");
11172 else if(r==HIREG) printf(" HI");
11173 else if(r==LOREG) printf(" LO");
11174 else printf(" r%d",r);
11183 /* Pass 8 - Assembly */
11184 linkcount=0;stubcount=0;
11185 ds=0;is_delayslot=0;
11187 uint64_t is32_pre=0;
11189 u_int beginning=(u_int)out;
11190 if((u_int)addr&1) {
11194 u_int instr_addr0_override=0;
11197 if (start == 0x80030000) {
11198 // nasty hack for fastbios thing
11199 // override block entry to this code
11200 instr_addr0_override=(u_int)out;
11201 emit_movimm(start,0);
11202 // abuse io address var as a flag that we
11203 // have already returned here once
11204 emit_readword((int)&address,1);
11205 emit_writeword(0,(int)&pcaddr);
11206 emit_writeword(0,(int)&address);
11208 emit_jne((int)new_dyna_leave);
11211 for(i=0;i<slen;i++)
11213 //if(ds) printf("ds: ");
11214 disassemble_inst(i);
11216 ds=0; // Skip delay slot
11217 if(bt[i]) assem_debug("OOPS - branch into delay slot\n");
11220 speculate_register_values(i);
11221 #ifndef DESTRUCTIVE_WRITEBACK
11222 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
11224 wb_sx(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,is32_pre,regs[i].was32,
11225 unneeded_reg[i],unneeded_reg_upper[i]);
11226 wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre,
11227 unneeded_reg[i],unneeded_reg_upper[i]);
11229 if((itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)&&!likely[i]) {
11230 is32_pre=branch_regs[i].is32;
11231 dirty_pre=branch_regs[i].dirty;
11233 is32_pre=regs[i].is32;
11234 dirty_pre=regs[i].dirty;
11238 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
11240 wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32,
11241 unneeded_reg[i],unneeded_reg_upper[i]);
11242 loop_preload(regmap_pre[i],regs[i].regmap_entry);
11244 // branch target entry point
11245 instr_addr[i]=(u_int)out;
11246 assem_debug("<->\n");
11248 if(regs[i].regmap_entry[HOST_CCREG]==CCREG&®s[i].regmap[HOST_CCREG]!=CCREG)
11249 wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32);
11250 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
11251 address_generation(i,®s[i],regs[i].regmap_entry);
11252 load_consts(regmap_pre[i],regs[i].regmap,regs[i].was32,i);
11253 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
11255 // Load the delay slot registers if necessary
11256 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i]&&(rs1[i+1]!=rt1[i]||rt1[i]==0))
11257 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
11258 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i]&&(rs2[i+1]!=rt1[i]||rt1[i]==0))
11259 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
11260 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a)
11261 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
11265 // Preload registers for following instruction
11266 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
11267 if(rs1[i+1]!=rt1[i]&&rs1[i+1]!=rt2[i])
11268 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
11269 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
11270 if(rs2[i+1]!=rt1[i]&&rs2[i+1]!=rt2[i])
11271 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
11273 // TODO: if(is_ooo(i)) address_generation(i+1);
11274 if(itype[i]==CJUMP||itype[i]==FJUMP)
11275 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
11276 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a)
11277 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
11278 if(bt[i]) cop1_usable=0;
11282 alu_assemble(i,®s[i]);break;
11284 imm16_assemble(i,®s[i]);break;
11286 shift_assemble(i,®s[i]);break;
11288 shiftimm_assemble(i,®s[i]);break;
11290 load_assemble(i,®s[i]);break;
11292 loadlr_assemble(i,®s[i]);break;
11294 store_assemble(i,®s[i]);break;
11296 storelr_assemble(i,®s[i]);break;
11298 cop0_assemble(i,®s[i]);break;
11300 cop1_assemble(i,®s[i]);break;
11302 c1ls_assemble(i,®s[i]);break;
11304 cop2_assemble(i,®s[i]);break;
11306 c2ls_assemble(i,®s[i]);break;
11308 c2op_assemble(i,®s[i]);break;
11310 fconv_assemble(i,®s[i]);break;
11312 float_assemble(i,®s[i]);break;
11314 fcomp_assemble(i,®s[i]);break;
11316 multdiv_assemble(i,®s[i]);break;
11318 mov_assemble(i,®s[i]);break;
11320 syscall_assemble(i,®s[i]);break;
11322 hlecall_assemble(i,®s[i]);break;
11324 intcall_assemble(i,®s[i]);break;
11326 ujump_assemble(i,®s[i]);ds=1;break;
11328 rjump_assemble(i,®s[i]);ds=1;break;
11330 cjump_assemble(i,®s[i]);ds=1;break;
11332 sjump_assemble(i,®s[i]);ds=1;break;
11334 fjump_assemble(i,®s[i]);ds=1;break;
11336 pagespan_assemble(i,®s[i]);break;
11338 if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
11339 literal_pool(1024);
11341 literal_pool_jumpover(256);
11344 //assert(itype[i-2]==UJUMP||itype[i-2]==RJUMP||(source[i-2]>>16)==0x1000);
11345 // If the block did not end with an unconditional branch,
11346 // add a jump to the next instruction.
11348 if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) {
11349 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
11351 if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP&&itype[i-2]!=FJUMP) {
11352 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
11353 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
11354 emit_loadreg(CCREG,HOST_CCREG);
11355 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG);
11357 else if(!likely[i-2])
11359 store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].is32,branch_regs[i-2].dirty,start+i*4);
11360 assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
11364 store_regs_bt(regs[i-2].regmap,regs[i-2].is32,regs[i-2].dirty,start+i*4);
11365 assert(regs[i-2].regmap[HOST_CCREG]==CCREG);
11367 add_to_linker((int)out,start+i*4,0);
11374 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
11375 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
11376 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
11377 emit_loadreg(CCREG,HOST_CCREG);
11378 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG);
11379 add_to_linker((int)out,start+i*4,0);
11383 // TODO: delay slot stubs?
11385 for(i=0;i<stubcount;i++)
11387 switch(stubs[i][0])
11395 do_readstub(i);break;
11400 do_writestub(i);break;
11402 do_ccstub(i);break;
11404 do_invstub(i);break;
11406 do_cop1stub(i);break;
11408 do_unalignedwritestub(i);break;
11412 if (instr_addr0_override)
11413 instr_addr[0] = instr_addr0_override;
11415 /* Pass 9 - Linker */
11416 for(i=0;i<linkcount;i++)
11418 assem_debug("%8x -> %8x\n",link_addr[i][0],link_addr[i][1]);
11420 if(!link_addr[i][2])
11423 void *addr=check_addr(link_addr[i][1]);
11424 emit_extjump(link_addr[i][0],link_addr[i][1]);
11426 set_jump_target(link_addr[i][0],(int)addr);
11427 add_link(link_addr[i][1],stub);
11429 else set_jump_target(link_addr[i][0],(int)stub);
11434 int target=(link_addr[i][1]-start)>>2;
11435 assert(target>=0&&target<slen);
11436 assert(instr_addr[target]);
11437 //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11438 //set_jump_target_fillslot(link_addr[i][0],instr_addr[target],link_addr[i][2]>>1);
11440 set_jump_target(link_addr[i][0],instr_addr[target]);
11444 // External Branch Targets (jump_in)
11445 if(copy+slen*4>(void *)shadow+sizeof(shadow)) copy=shadow;
11446 for(i=0;i<slen;i++)
11450 if(instr_addr[i]) // TODO - delay slots (=null)
11452 u_int vaddr=start+i*4;
11453 u_int page=get_page(vaddr);
11454 u_int vpage=get_vpage(vaddr);
11456 //if(!(is32[i]&(~unneeded_reg_upper[i])&~(1LL<<CCREG)))
11458 if(!requires_32bit[i])
11463 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
11464 assem_debug("jump_in: %x\n",start+i*4);
11465 ll_add(jump_dirty+vpage,vaddr,(void *)out);
11466 int entry_point=do_dirty_stub(i);
11467 ll_add(jump_in+page,vaddr,(void *)entry_point);
11468 // If there was an existing entry in the hash table,
11469 // replace it with the new address.
11470 // Don't add new entries. We'll insert the
11471 // ones that actually get used in check_addr().
11472 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
11473 if(ht_bin[0]==vaddr) {
11474 ht_bin[1]=entry_point;
11476 if(ht_bin[2]==vaddr) {
11477 ht_bin[3]=entry_point;
11482 u_int r=requires_32bit[i]|!!(requires_32bit[i]>>32);
11483 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
11484 assem_debug("jump_in: %x (restricted - %x)\n",start+i*4,r);
11485 //int entry_point=(int)out;
11486 ////assem_debug("entry_point: %x\n",entry_point);
11487 //load_regs_entry(i);
11488 //if(entry_point==(int)out)
11489 // entry_point=instr_addr[i];
11491 // emit_jmp(instr_addr[i]);
11492 //ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11493 ll_add_32(jump_dirty+vpage,vaddr,r,(void *)out);
11494 int entry_point=do_dirty_stub(i);
11495 ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11500 // Write out the literal pool if necessary
11502 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11504 if(((u_int)out)&7) emit_addnop(13);
11506 assert((u_int)out-beginning<MAX_OUTPUT_BLOCK_SIZE);
11507 //printf("shadow buffer: %x-%x\n",(int)copy,(int)copy+slen*4);
11508 memcpy(copy,source,slen*4);
11512 __clear_cache((void *)beginning,out);
11515 // If we're within 256K of the end of the buffer,
11516 // start over from the beginning. (Is 256K enough?)
11517 if((int)out>BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR;
11519 // Trap writes to any of the pages we compiled
11520 for(i=start>>12;i<=(start+slen*4)>>12;i++) {
11522 #ifndef DISABLE_TLB
11523 memory_map[i]|=0x40000000;
11524 if((signed int)start>=(signed int)0xC0000000) {
11526 j=(((u_int)i<<12)+(memory_map[i]<<2)-(u_int)rdram+(u_int)0x80000000)>>12;
11528 memory_map[j]|=0x40000000;
11529 //printf("write protect physical page: %x (virtual %x)\n",j<<12,start);
11533 inv_code_start=inv_code_end=~0;
11535 // for PCSX we need to mark all mirrors too
11536 if(get_page(start)<(RAM_SIZE>>12))
11537 for(i=start>>12;i<=(start+slen*4)>>12;i++)
11538 invalid_code[((u_int)0x00000000>>12)|(i&0x1ff)]=
11539 invalid_code[((u_int)0x80000000>>12)|(i&0x1ff)]=
11540 invalid_code[((u_int)0xa0000000>>12)|(i&0x1ff)]=0;
11543 /* Pass 10 - Free memory by expiring oldest blocks */
11545 int end=((((int)out-BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535;
11546 while(expirep!=end)
11548 int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
11549 int base=BASE_ADDR+((expirep>>13)<<shift); // Base address of this block
11550 inv_debug("EXP: Phase %d\n",expirep);
11551 switch((expirep>>11)&3)
11554 // Clear jump_in and jump_dirty
11555 ll_remove_matching_addrs(jump_in+(expirep&2047),base,shift);
11556 ll_remove_matching_addrs(jump_dirty+(expirep&2047),base,shift);
11557 ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base,shift);
11558 ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base,shift);
11562 ll_kill_pointers(jump_out[expirep&2047],base,shift);
11563 ll_kill_pointers(jump_out[(expirep&2047)+2048],base,shift);
11566 // Clear hash table
11567 for(i=0;i<32;i++) {
11568 int *ht_bin=hash_table[((expirep&2047)<<5)+i];
11569 if((ht_bin[3]>>shift)==(base>>shift) ||
11570 ((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11571 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[2],ht_bin[3]);
11572 ht_bin[2]=ht_bin[3]=-1;
11574 if((ht_bin[1]>>shift)==(base>>shift) ||
11575 ((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11576 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[0],ht_bin[1]);
11577 ht_bin[0]=ht_bin[2];
11578 ht_bin[1]=ht_bin[3];
11579 ht_bin[2]=ht_bin[3]=-1;
11586 if((expirep&2047)==0)
11589 ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);
11590 ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base,shift);
11593 expirep=(expirep+1)&65535;
11598 // vim:shiftwidth=2:expandtab