1 /***************************************************************************
2 * Copyright (C) 2010 by Blade_Arma *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. *
18 ***************************************************************************/
21 * Internal PSX counters.
24 #include "psxcounters.h"
28 /******************************************************************************/
32 Rc0Gate = 0x0001, // 0 not implemented
33 Rc1Gate = 0x0001, // 0 not implemented
34 Rc2Disable = 0x0001, // 0 partially implemented
35 RcUnknown1 = 0x0002, // 1 ?
36 RcUnknown2 = 0x0004, // 2 ?
37 RcCountToTarget = 0x0008, // 3
38 RcIrqOnTarget = 0x0010, // 4
39 RcIrqOnOverflow = 0x0020, // 5
40 RcIrqRegenerate = 0x0040, // 6
41 RcUnknown7 = 0x0080, // 7 ?
42 Rc0PixelClock = 0x0100, // 8 fake implementation
43 Rc1HSyncClock = 0x0100, // 8
44 Rc2Unknown8 = 0x0100, // 8 ?
45 Rc0Unknown9 = 0x0200, // 9 ?
46 Rc1Unknown9 = 0x0200, // 9 ?
47 Rc2OneEighthClock = 0x0200, // 9
48 RcUnknown10 = 0x0400, // 10 ?
49 RcCountEqTarget = 0x0800, // 11
50 RcOverflow = 0x1000, // 12
51 RcUnknown13 = 0x2000, // 13 ? (always zero)
52 RcUnknown14 = 0x4000, // 14 ? (always zero)
53 RcUnknown15 = 0x8000, // 15 ? (always zero)
56 #define CounterQuantity ( 4 )
57 //static const u32 CounterQuantity = 4;
59 static const u32 CountToOverflow = 0;
60 static const u32 CountToTarget = 1;
62 static const u32 FrameRate[] = { 60, 50 };
63 static const u32 HSyncTotal[] = { 263, 314 }; // actually one more on odd lines for PAL
64 #define VBlankStart 240
66 #define VERBOSE_LEVEL 0
68 /******************************************************************************/
70 Rcnt rcnts[ CounterQuantity ];
73 u32 frame_counter = 0;
74 static u32 hsync_steps = 0;
76 u32 psxNextCounter = 0, psxNextsCounter = 0;
78 /******************************************************************************/
81 void setIrq( u32 irq )
83 psxHu32ref(0x1070) |= SWAPu32(irq);
87 void verboseLog( u32 level, const char *str, ... )
90 if( level <= VERBOSE_LEVEL )
96 vsprintf( buf, str, va );
105 /******************************************************************************/
108 void _psxRcntWcount( u32 index, u32 value )
112 verboseLog( 1, "[RCNT %i] wcount > 0xffff: %x\n", index, value );
116 rcnts[index].cycleStart = psxRegs.cycle;
117 rcnts[index].cycleStart -= value * rcnts[index].rate;
120 if( value < rcnts[index].target )
122 rcnts[index].cycle = rcnts[index].target * rcnts[index].rate;
123 rcnts[index].counterState = CountToTarget;
127 rcnts[index].cycle = 0x10000 * rcnts[index].rate;
128 rcnts[index].counterState = CountToOverflow;
133 u32 _psxRcntRcount( u32 index )
137 count = psxRegs.cycle;
138 count -= rcnts[index].cycleStart;
139 if (rcnts[index].rate > 1)
140 count /= rcnts[index].rate;
142 if( count > 0x10000 )
144 verboseLog( 1, "[RCNT %i] rcount > 0x10000: %x\n", index, count );
152 void _psxRcntWmode( u32 index, u32 value )
154 rcnts[index].mode = value;
159 if( value & Rc0PixelClock )
161 rcnts[index].rate = 5;
165 rcnts[index].rate = 1;
169 if( value & Rc1HSyncClock )
171 rcnts[index].rate = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType]));
175 rcnts[index].rate = 1;
179 if( value & Rc2OneEighthClock )
181 rcnts[index].rate = 8;
185 rcnts[index].rate = 1;
188 // TODO: wcount must work.
189 if( value & Rc2Disable )
191 rcnts[index].rate = 0xffffffff;
197 /******************************************************************************/
205 psxNextsCounter = psxRegs.cycle;
206 psxNextCounter = 0x7fffffff;
208 for( i = 0; i < CounterQuantity; ++i )
210 countToUpdate = rcnts[i].cycle - (psxNextsCounter - rcnts[i].cycleStart);
212 if( countToUpdate < 0 )
218 if( countToUpdate < (s32)psxNextCounter )
220 psxNextCounter = countToUpdate;
224 psxRegs.interrupt |= (1 << PSXINT_RCNT);
225 new_dyna_set_event(PSXINT_RCNT, psxNextCounter);
228 /******************************************************************************/
231 void psxRcntReset( u32 index )
235 rcnts[index].mode |= RcUnknown10;
237 if( rcnts[index].counterState == CountToTarget )
239 rcycles = psxRegs.cycle - rcnts[index].cycleStart;
240 if( rcnts[index].mode & RcCountToTarget )
242 rcycles -= rcnts[index].target * rcnts[index].rate;
243 rcnts[index].cycleStart = psxRegs.cycle - rcycles;
247 rcnts[index].cycle = 0x10000 * rcnts[index].rate;
248 rcnts[index].counterState = CountToOverflow;
251 if( rcnts[index].mode & RcIrqOnTarget )
253 if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) )
255 verboseLog( 3, "[RCNT %i] irq\n", index );
256 setIrq( rcnts[index].irq );
257 rcnts[index].irqState = 1;
261 rcnts[index].mode |= RcCountEqTarget;
263 if( rcycles < 0x10000 * rcnts[index].rate )
267 if( rcnts[index].counterState == CountToOverflow )
269 rcycles = psxRegs.cycle - rcnts[index].cycleStart;
270 rcycles -= 0x10000 * rcnts[index].rate;
272 rcnts[index].cycleStart = psxRegs.cycle - rcycles;
274 if( rcycles < rcnts[index].target * rcnts[index].rate )
276 rcnts[index].cycle = rcnts[index].target * rcnts[index].rate;
277 rcnts[index].counterState = CountToTarget;
280 if( rcnts[index].mode & RcIrqOnOverflow )
282 if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) )
284 verboseLog( 3, "[RCNT %i] irq\n", index );
285 setIrq( rcnts[index].irq );
286 rcnts[index].irqState = 1;
290 rcnts[index].mode |= RcOverflow;
294 static void scheduleRcntBase(void)
296 // Schedule next call, in hsyncs
297 if (hSyncCount < VBlankStart)
298 hsync_steps = VBlankStart - hSyncCount;
300 hsync_steps = HSyncTotal[Config.PsxType] - hSyncCount;
302 if (hSyncCount + hsync_steps == HSyncTotal[Config.PsxType])
304 rcnts[3].cycle = Config.PsxType ? PSXCLK / 50 : PSXCLK / 60;
308 // clk / 50 / 314 ~= 2157.25
309 // clk / 60 / 263 ~= 2146.31
310 u32 mult = Config.PsxType ? 8836089 : 8791293;
311 rcnts[3].cycle = hsync_steps * mult >> 12;
319 cycle = psxRegs.cycle;
322 while( cycle - rcnts[0].cycleStart >= rcnts[0].cycle )
328 while( cycle - rcnts[1].cycleStart >= rcnts[1].cycle )
334 while( cycle - rcnts[2].cycleStart >= rcnts[2].cycle )
340 if( cycle - rcnts[3].cycleStart >= rcnts[3].cycle )
342 hSyncCount += hsync_steps;
345 if( hSyncCount == VBlankStart )
347 HW_GPU_STATUS &= SWAP32(~PSXGPU_LCF);
356 SPU_async( cycle, 1 );
361 if( hSyncCount >= HSyncTotal[Config.PsxType] )
363 rcnts[3].cycleStart += Config.PsxType ? PSXCLK / 50 : PSXCLK / 60;
368 if ((HW_GPU_STATUS & SWAP32(PSXGPU_ILACE_BITS)) == SWAP32(PSXGPU_ILACE_BITS))
369 HW_GPU_STATUS |= SWAP32(frame_counter << 31);
370 GPU_vBlank(0, SWAP32(HW_GPU_STATUS) >> 31);
383 /******************************************************************************/
385 void psxRcntWcount( u32 index, u32 value )
387 verboseLog( 2, "[RCNT %i] wcount: %x\n", index, value );
389 _psxRcntWcount( index, value );
393 void psxRcntWmode( u32 index, u32 value )
395 verboseLog( 1, "[RCNT %i] wmode: %x\n", index, value );
397 _psxRcntWmode( index, value );
398 _psxRcntWcount( index, 0 );
400 rcnts[index].irqState = 0;
404 void psxRcntWtarget( u32 index, u32 value )
406 verboseLog( 1, "[RCNT %i] wtarget: %x\n", index, value );
408 rcnts[index].target = value;
410 _psxRcntWcount( index, _psxRcntRcount( index ) );
414 /******************************************************************************/
416 u32 psxRcntRcount( u32 index )
420 count = _psxRcntRcount( index );
422 verboseLog( 2, "[RCNT %i] rcount: %x\n", index, count );
427 u32 psxRcntRmode( u32 index )
431 mode = rcnts[index].mode;
432 rcnts[index].mode &= 0xe7ff;
434 verboseLog( 2, "[RCNT %i] rmode: %x\n", index, mode );
439 u32 psxRcntRtarget( u32 index )
441 verboseLog( 2, "[RCNT %i] rtarget: %x\n", index, rcnts[index].target );
443 return rcnts[index].target;
446 /******************************************************************************/
466 rcnts[3].mode = RcCountToTarget;
467 rcnts[3].target = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType]));
469 for( i = 0; i < CounterQuantity; ++i )
471 _psxRcntWcount( i, 0 );
480 /******************************************************************************/
482 s32 psxRcntFreeze( void *f, s32 Mode )
484 u32 spuSyncCount = 0;
488 gzfreeze( &rcnts, sizeof(Rcnt) * CounterQuantity );
489 gzfreeze( &hSyncCount, sizeof(hSyncCount) );
490 gzfreeze( &spuSyncCount, sizeof(spuSyncCount) );
491 gzfreeze( &psxNextCounter, sizeof(psxNextCounter) );
492 gzfreeze( &psxNextsCounter, sizeof(psxNextsCounter) );
496 // don't trust things from a savestate
498 for( i = 0; i < CounterQuantity; ++i )
500 _psxRcntWmode( i, rcnts[i].mode );
501 count = (psxRegs.cycle - rcnts[i].cycleStart) / rcnts[i].rate;
502 _psxRcntWcount( i, count );
511 /******************************************************************************/
512 // vim:ts=4:shiftwidth=4:expandtab