1 /***************************************************************************
2 * Copyright (C) 2010 by Blade_Arma *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. *
18 ***************************************************************************/
21 * Internal PSX counters.
24 #include "psxcounters.h"
28 /******************************************************************************/
32 Rc0Gate = 0x0001, // 0 not implemented
33 Rc1Gate = 0x0001, // 0 not implemented
34 Rc2Disable = 0x0001, // 0 partially implemented
35 RcUnknown1 = 0x0002, // 1 ?
36 RcUnknown2 = 0x0004, // 2 ?
37 RcCountToTarget = 0x0008, // 3
38 RcIrqOnTarget = 0x0010, // 4
39 RcIrqOnOverflow = 0x0020, // 5
40 RcIrqRegenerate = 0x0040, // 6
41 RcUnknown7 = 0x0080, // 7 ?
42 Rc0PixelClock = 0x0100, // 8 fake implementation
43 Rc1HSyncClock = 0x0100, // 8
44 Rc2Unknown8 = 0x0100, // 8 ?
45 Rc0Unknown9 = 0x0200, // 9 ?
46 Rc1Unknown9 = 0x0200, // 9 ?
47 Rc2OneEighthClock = 0x0200, // 9
48 RcUnknown10 = 0x0400, // 10 ?
49 RcCountEqTarget = 0x0800, // 11
50 RcOverflow = 0x1000, // 12
51 RcUnknown13 = 0x2000, // 13 ? (always zero)
52 RcUnknown14 = 0x4000, // 14 ? (always zero)
53 RcUnknown15 = 0x8000, // 15 ? (always zero)
56 #define CounterQuantity ( 4 )
57 //static const u32 CounterQuantity = 4;
59 static const u32 CountToOverflow = 0;
60 static const u32 CountToTarget = 1;
62 static const u32 FrameRate[] = { 60, 50 };
63 static const u32 HSyncTotal[] = { 263, 314 }; // actually one more on odd lines for PAL
64 #define VBlankStart 240
66 #define VERBOSE_LEVEL 0
68 static const s32 VerboseLevel = VERBOSE_LEVEL;
71 /******************************************************************************/
74 Rcnt rcnts[ CounterQuantity ];
78 u32 frame_counter = 0;
79 static u32 hsync_steps = 0;
80 static u32 base_cycle = 0;
82 u32 psxNextCounter = 0, psxNextsCounter = 0;
84 /******************************************************************************/
87 void setIrq( u32 irq )
89 psxHu32ref(0x1070) |= SWAPu32(irq);
93 void verboseLog( u32 level, const char *str, ... )
96 if( level <= VerboseLevel )
102 vsprintf( buf, str, va );
111 /******************************************************************************/
114 void _psxRcntWcount( u32 index, u32 value )
118 verboseLog( 1, "[RCNT %i] wcount > 0xffff: %x\n", index, value );
122 rcnts[index].cycleStart = psxRegs.cycle;
123 rcnts[index].cycleStart -= value * rcnts[index].rate;
126 if( value < rcnts[index].target )
128 rcnts[index].cycle = rcnts[index].target * rcnts[index].rate;
129 rcnts[index].counterState = CountToTarget;
133 rcnts[index].cycle = 0x10000 * rcnts[index].rate;
134 rcnts[index].counterState = CountToOverflow;
139 u32 _psxRcntRcount( u32 index )
143 count = psxRegs.cycle;
144 count -= rcnts[index].cycleStart;
145 if (rcnts[index].rate > 1)
146 count /= rcnts[index].rate;
148 if( count > 0x10000 )
150 verboseLog( 1, "[RCNT %i] rcount > 0x10000: %x\n", index, count );
158 void _psxRcntWmode( u32 index, u32 value )
160 rcnts[index].mode = value;
165 if( value & Rc0PixelClock )
167 rcnts[index].rate = 5;
171 rcnts[index].rate = 1;
175 if( value & Rc1HSyncClock )
177 rcnts[index].rate = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType]));
181 rcnts[index].rate = 1;
185 if( value & Rc2OneEighthClock )
187 rcnts[index].rate = 8;
191 rcnts[index].rate = 1;
194 // TODO: wcount must work.
195 if( value & Rc2Disable )
197 rcnts[index].rate = 0xffffffff;
203 /******************************************************************************/
211 psxNextsCounter = psxRegs.cycle;
212 psxNextCounter = 0x7fffffff;
214 for( i = 0; i < CounterQuantity; ++i )
216 countToUpdate = rcnts[i].cycle - (psxNextsCounter - rcnts[i].cycleStart);
218 if( countToUpdate < 0 )
224 if( countToUpdate < (s32)psxNextCounter )
226 psxNextCounter = countToUpdate;
230 psxRegs.interrupt |= (1 << PSXINT_RCNT);
231 new_dyna_set_event(PSXINT_RCNT, psxNextCounter);
234 /******************************************************************************/
237 void psxRcntReset( u32 index )
241 rcnts[index].mode |= RcUnknown10;
243 if( rcnts[index].counterState == CountToTarget )
245 rcycles = psxRegs.cycle - rcnts[index].cycleStart;
246 if( rcnts[index].mode & RcCountToTarget )
248 rcycles -= rcnts[index].target * rcnts[index].rate;
249 rcnts[index].cycleStart = psxRegs.cycle - rcycles;
253 rcnts[index].cycle = 0x10000 * rcnts[index].rate;
254 rcnts[index].counterState = CountToOverflow;
257 if( rcnts[index].mode & RcIrqOnTarget )
259 if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) )
261 verboseLog( 3, "[RCNT %i] irq\n", index );
262 setIrq( rcnts[index].irq );
263 rcnts[index].irqState = 1;
267 rcnts[index].mode |= RcCountEqTarget;
269 if( rcycles < 0x10000 * rcnts[index].rate )
273 if( rcnts[index].counterState == CountToOverflow )
275 rcycles = psxRegs.cycle - rcnts[index].cycleStart;
276 rcycles -= 0x10000 * rcnts[index].rate;
278 rcnts[index].cycleStart = psxRegs.cycle - rcycles;
280 if( rcycles < rcnts[index].target * rcnts[index].rate )
282 rcnts[index].cycle = rcnts[index].target * rcnts[index].rate;
283 rcnts[index].counterState = CountToTarget;
286 if( rcnts[index].mode & RcIrqOnOverflow )
288 if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) )
290 verboseLog( 3, "[RCNT %i] irq\n", index );
291 setIrq( rcnts[index].irq );
292 rcnts[index].irqState = 1;
296 rcnts[index].mode |= RcOverflow;
304 cycle = psxRegs.cycle;
307 if( cycle - rcnts[0].cycleStart >= rcnts[0].cycle )
313 if( cycle - rcnts[1].cycleStart >= rcnts[1].cycle )
319 if( cycle - rcnts[2].cycleStart >= rcnts[2].cycle )
325 if( cycle - rcnts[3].cycleStart >= rcnts[3].cycle )
327 u32 leftover_cycles = cycle - rcnts[3].cycleStart - rcnts[3].cycle;
330 hSyncCount += hsync_steps;
333 if( hSyncCount == VBlankStart )
335 HW_GPU_STATUS &= ~PSXGPU_LCF;
344 SPU_async( cycle, 1 );
348 // Update lace. (with InuYasha fix)
349 if( hSyncCount >= (Config.VSyncWA ? HSyncTotal[Config.PsxType] / BIAS : HSyncTotal[Config.PsxType]) )
355 if( (HW_GPU_STATUS & PSXGPU_ILACE_BITS) == PSXGPU_ILACE_BITS )
356 HW_GPU_STATUS |= frame_counter << 31;
357 GPU_vBlank( 0, HW_GPU_STATUS >> 31 );
360 // Schedule next call, in hsyncs
361 hsync_steps = HSyncTotal[Config.PsxType] - hSyncCount;
362 next_vsync = VBlankStart - hSyncCount; // ok to overflow
363 if( next_vsync && next_vsync < hsync_steps )
364 hsync_steps = next_vsync;
366 rcnts[3].cycleStart = cycle - leftover_cycles;
368 // 20.12 precision, clk / 50 / 313 ~= 2164.14
369 base_cycle += hsync_steps * 8864320;
371 // clk / 60 / 263 ~= 2146.31
372 base_cycle += hsync_steps * 8791293;
373 rcnts[3].cycle = base_cycle >> 12;
384 /******************************************************************************/
386 void psxRcntWcount( u32 index, u32 value )
388 verboseLog( 2, "[RCNT %i] wcount: %x\n", index, value );
390 _psxRcntWcount( index, value );
394 void psxRcntWmode( u32 index, u32 value )
396 verboseLog( 1, "[RCNT %i] wmode: %x\n", index, value );
398 _psxRcntWmode( index, value );
399 _psxRcntWcount( index, 0 );
401 rcnts[index].irqState = 0;
405 void psxRcntWtarget( u32 index, u32 value )
407 verboseLog( 1, "[RCNT %i] wtarget: %x\n", index, value );
409 rcnts[index].target = value;
411 _psxRcntWcount( index, _psxRcntRcount( index ) );
415 /******************************************************************************/
417 u32 psxRcntRcount( u32 index )
421 count = _psxRcntRcount( index );
423 // Parasite Eve 2 fix.
428 if( rcnts[index].counterState == CountToTarget )
435 verboseLog( 2, "[RCNT %i] rcount: %x\n", index, count );
440 u32 psxRcntRmode( u32 index )
444 mode = rcnts[index].mode;
445 rcnts[index].mode &= 0xe7ff;
447 verboseLog( 2, "[RCNT %i] rmode: %x\n", index, mode );
452 u32 psxRcntRtarget( u32 index )
454 verboseLog( 2, "[RCNT %i] rtarget: %x\n", index, rcnts[index].target );
456 return rcnts[index].target;
459 /******************************************************************************/
479 rcnts[3].mode = RcCountToTarget;
480 rcnts[3].target = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType]));
482 for( i = 0; i < CounterQuantity; ++i )
484 _psxRcntWcount( i, 0 );
493 /******************************************************************************/
495 s32 psxRcntFreeze( void *f, s32 Mode )
497 u32 spuSyncCount = 0;
501 gzfreeze( &rcnts, sizeof(Rcnt) * CounterQuantity );
502 gzfreeze( &hSyncCount, sizeof(hSyncCount) );
503 gzfreeze( &spuSyncCount, sizeof(spuSyncCount) );
504 gzfreeze( &psxNextCounter, sizeof(psxNextCounter) );
505 gzfreeze( &psxNextsCounter, sizeof(psxNextsCounter) );
509 // don't trust things from a savestate
510 for( i = 0; i < CounterQuantity; ++i )
512 _psxRcntWmode( i, rcnts[i].mode );
513 count = (psxRegs.cycle - rcnts[i].cycleStart) / rcnts[i].rate;
514 _psxRcntWcount( i, count );
516 hsync_steps = (psxRegs.cycle - rcnts[3].cycleStart) / rcnts[3].target;
525 /******************************************************************************/