1 /***************************************************************************
2 * Copyright (C) 2007 Ryan Schultz, PCSX-df Team, PCSX team *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. *
18 ***************************************************************************/
21 * Functions for PSX hardware control.
25 #include "psxevents.h"
31 //#define PSXHW_LOG printf
36 static u32 (*psxHwReadGpuSRptr)(void) = psxHwReadGpuSR;
39 memset(psxH, 0, 0x10000);
41 mdecInit(); // initialize mdec decoder
44 HW_GPU_STATUS = SWAP32(0x14802000);
45 psxHwReadGpuSRptr = Config.hacks.gpu_busy_hack
46 ? psxHwReadGpuSRbusyHack : psxHwReadGpuSR;
49 void psxHwWriteIstat(u32 value)
51 u32 stat = psxHu16(0x1070) & value;
52 psxHu16ref(0x1070) = SWAPu16(stat);
54 psxRegs.CP0.n.Cause &= ~0x400;
55 if (stat & psxHu16(0x1074))
56 psxRegs.CP0.n.Cause |= 0x400;
59 void psxHwWriteImask(u32 value)
61 u32 stat = psxHu16(0x1070);
62 psxHu16ref(0x1074) = SWAPu16(value);
64 //if ((psxRegs.CP0.n.SR & 0x401) == 0x401)
65 // log_unhandled("irq on unmask @%08x\n", psxRegs.pc);
66 set_event(PSXINT_NEWDRC_CHECK, 1);
68 psxRegs.CP0.n.Cause &= ~0x400;
70 psxRegs.CP0.n.Cause |= 0x400;
73 void psxHwWriteDmaIcr32(u32 value)
75 u32 tmp = value & 0x00ff803f;
76 tmp |= (SWAPu32(HW_DMA_ICR) & ~value) & 0x7f000000;
77 if ((tmp & HW_DMA_ICR_GLOBAL_ENABLE && tmp & 0x7f000000)
78 || tmp & HW_DMA_ICR_BUS_ERROR) {
79 if (!(SWAPu32(HW_DMA_ICR) & HW_DMA_ICR_IRQ_SENT))
80 psxHu32ref(0x1070) |= SWAP32(8);
81 tmp |= HW_DMA_ICR_IRQ_SENT;
83 HW_DMA_ICR = SWAPu32(tmp);
86 void psxHwWriteGpuSR(u32 value)
88 GPU_writeStatus(value);
92 u32 psxHwReadGpuSR(void)
96 // meh2, syncing for img bit, might want to avoid it..
98 v = SWAP32(HW_GPU_STATUS);
100 // XXX: because of large timeslices can't use hSyncCount, using rough
101 // approximization instead. Perhaps better use hcounter code here or something.
102 if (hSyncCount < 240 && (v & PSXGPU_ILACE_BITS) != PSXGPU_ILACE_BITS)
103 v |= PSXGPU_LCF & (psxRegs.cycle << 20);
107 // a hack due to poor timing of gpu idle bit
108 // to get rid of this, GPU draw times, DMAs, cpu timing has to fall within
109 // certain timing window or else games like "ToHeart" softlock
110 u32 psxHwReadGpuSRbusyHack(void)
112 u32 v = psxHwReadGpuSR();
119 u8 psxHwRead8(u32 add) {
122 switch (add & 0x1fffffff) {
123 case 0x1f801040: hard = sioRead8(); break;
124 case 0x1f801800: hard = cdrRead0(); break;
125 case 0x1f801801: hard = cdrRead1(); break;
126 case 0x1f801802: hard = cdrRead2(); break;
127 case 0x1f801803: hard = cdrRead3(); break;
129 case 0x1f801041: case 0x1f801042: case 0x1f801043:
130 case 0x1f801044: case 0x1f801045:
131 case 0x1f801046: case 0x1f801047:
132 case 0x1f801048: case 0x1f801049:
133 case 0x1f80104a: case 0x1f80104b:
134 case 0x1f80104c: case 0x1f80104d:
135 case 0x1f80104e: case 0x1f80104f:
136 case 0x1f801050: case 0x1f801051:
137 case 0x1f801054: case 0x1f801055:
138 case 0x1f801058: case 0x1f801059:
139 case 0x1f80105a: case 0x1f80105b:
140 case 0x1f80105c: case 0x1f80105d:
141 case 0x1f801100: case 0x1f801101:
142 case 0x1f801104: case 0x1f801105:
143 case 0x1f801108: case 0x1f801109:
144 case 0x1f801110: case 0x1f801111:
145 case 0x1f801114: case 0x1f801115:
146 case 0x1f801118: case 0x1f801119:
147 case 0x1f801120: case 0x1f801121:
148 case 0x1f801124: case 0x1f801125:
149 case 0x1f801128: case 0x1f801129:
150 case 0x1f801810: case 0x1f801811:
151 case 0x1f801812: case 0x1f801813:
152 case 0x1f801814: case 0x1f801815:
153 case 0x1f801816: case 0x1f801817:
154 case 0x1f801820: case 0x1f801821:
155 case 0x1f801822: case 0x1f801823:
156 case 0x1f801824: case 0x1f801825:
157 case 0x1f801826: case 0x1f801827:
158 log_unhandled("unhandled r8 %08x @%08x\n", add, psxRegs.pc);
161 if (0x1f801c00 <= add && add < 0x1f802000) {
162 u16 val = SPU_readRegister(add & ~1, psxRegs.cycle);
163 hard = (add & 1) ? val >> 8 : val;
168 PSXHW_LOG("*Unkwnown 8bit read at address %x\n", add);
174 PSXHW_LOG("*Known 8bit read at address %x value %x\n", add, hard);
179 u16 psxHwRead16(u32 add) {
182 switch (add & 0x1fffffff) {
184 case 0x1f801070: PSXHW_LOG("IREG 16bit read %x\n", psxHu16(0x1070));
185 return psxHu16(0x1070);
186 case 0x1f801074: PSXHW_LOG("IMASK 16bit read %x\n", psxHu16(0x1074));
187 return psxHu16(0x1074);
191 hard|= sioRead8() << 8;
192 PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
195 hard = sioReadStat16();
196 PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
199 hard = sioReadMode16();
200 PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
203 hard = sioReadCtrl16();
204 PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
207 hard = sioReadBaud16();
208 PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
211 /* Fixes Armored Core misdetecting the Link cable being detected.
212 * We want to turn that thing off and force it to do local multiplayer instead.
213 * Thanks Sony for the fix, they fixed it in their PS Classic fork.
219 hard = psxRcntRcount0();
221 PSXHW_LOG("T0 count read16: %x\n", hard);
225 hard = psxRcntRmode(0);
227 PSXHW_LOG("T0 mode read16: %x\n", hard);
231 hard = psxRcntRtarget(0);
233 PSXHW_LOG("T0 target read16: %x\n", hard);
237 hard = psxRcntRcount1();
239 PSXHW_LOG("T1 count read16: %x\n", hard);
243 hard = psxRcntRmode(1);
245 PSXHW_LOG("T1 mode read16: %x\n", hard);
249 hard = psxRcntRtarget(1);
251 PSXHW_LOG("T1 target read16: %x\n", hard);
255 hard = psxRcntRcount2();
257 PSXHW_LOG("T2 count read16: %x\n", hard);
261 hard = psxRcntRmode(2);
263 PSXHW_LOG("T2 mode read16: %x\n", hard);
267 hard = psxRcntRtarget(2);
269 PSXHW_LOG("T2 target read16: %x\n", hard);
273 //case 0x1f802030: hard = //int_2000????
274 //case 0x1f802040: hard =//dip switches...??
293 log_unhandled("unhandled r16 %08x @%08x\n", add, psxRegs.pc);
296 if (0x1f801c00 <= add && add < 0x1f802000)
297 return SPU_readRegister(add, psxRegs.cycle);
300 PSXHW_LOG("*Unkwnown 16bit read at address %x\n", add);
306 PSXHW_LOG("*Known 16bit read at address %x value %x\n", add, hard);
311 u32 psxHwRead32(u32 add) {
314 switch (add & 0x1fffffff) {
317 hard |= sioRead8() << 8;
318 hard |= sioRead8() << 16;
319 hard |= sioRead8() << 24;
320 PAD_LOG("sio read32 ;ret = %x\n", hard);
323 hard = sioReadStat16();
324 PAD_LOG("sio read32 %x; ret = %x\n", add&0xf, hard);
328 PSXHW_LOG("RAM size read %x\n", psxHu32(0x1060));
329 return psxHu32(0x1060);
330 case 0x1f801070: PSXHW_LOG("IREG 32bit read %x\n", psxHu32(0x1070));
331 return psxHu32(0x1070);
332 case 0x1f801074: PSXHW_LOG("IMASK 32bit read %x\n", psxHu32(0x1074));
333 return psxHu32(0x1074);
337 hard = GPU_readData();
339 PSXHW_LOG("GPU DATA 32bit read %x\n", hard);
343 hard = psxHwReadGpuSRptr();
345 PSXHW_LOG("GPU STATUS 32bit read %x\n", hard);
349 case 0x1f801820: hard = mdecRead0(); break;
350 case 0x1f801824: hard = mdecRead1(); break;
354 PSXHW_LOG("DMA2 MADR 32bit read %x\n", psxHu32(0x10a0));
355 return SWAPu32(HW_DMA2_MADR);
357 PSXHW_LOG("DMA2 BCR 32bit read %x\n", psxHu32(0x10a4));
358 return SWAPu32(HW_DMA2_BCR);
360 PSXHW_LOG("DMA2 CHCR 32bit read %x\n", psxHu32(0x10a8));
361 return SWAPu32(HW_DMA2_CHCR);
366 PSXHW_LOG("DMA3 MADR 32bit read %x\n", psxHu32(0x10b0));
367 return SWAPu32(HW_DMA3_MADR);
369 PSXHW_LOG("DMA3 BCR 32bit read %x\n", psxHu32(0x10b4));
370 return SWAPu32(HW_DMA3_BCR);
372 PSXHW_LOG("DMA3 CHCR 32bit read %x\n", psxHu32(0x10b8));
373 return SWAPu32(HW_DMA3_CHCR);
378 PSXHW_LOG("DMA PCR 32bit read %x\n", psxHu32(0x10f0));
379 return SWAPu32(HW_DMA_PCR); // dma rest channel
381 PSXHW_LOG("DMA ICR 32bit read %x\n", psxHu32(0x10f4));
382 return SWAPu32(HW_DMA_ICR); // interrupt enabler?*/
385 // time for rootcounters :)
387 hard = psxRcntRcount0();
389 PSXHW_LOG("T0 count read32: %x\n", hard);
393 hard = psxRcntRmode(0);
395 PSXHW_LOG("T0 mode read32: %x\n", hard);
399 hard = psxRcntRtarget(0);
401 PSXHW_LOG("T0 target read32: %x\n", hard);
405 hard = psxRcntRcount1();
407 PSXHW_LOG("T1 count read32: %x\n", hard);
411 hard = psxRcntRmode(1);
413 PSXHW_LOG("T1 mode read32: %x\n", hard);
417 hard = psxRcntRtarget(1);
419 PSXHW_LOG("T1 target read32: %x\n", hard);
423 hard = psxRcntRcount2();
425 PSXHW_LOG("T2 count read32: %x\n", hard);
429 hard = psxRcntRmode(2);
431 PSXHW_LOG("T2 mode read32: %x\n", hard);
435 hard = psxRcntRtarget(2);
437 PSXHW_LOG("T2 target read32: %x\n", hard);
448 log_unhandled("unhandled r32 %08x @%08x\n", add, psxRegs.pc);
451 if (0x1f801c00 <= add && add < 0x1f802000) {
452 hard = SPU_readRegister(add, psxRegs.cycle);
453 hard |= SPU_readRegister(add + 2, psxRegs.cycle) << 16;
458 PSXHW_LOG("*Unkwnown 32bit read at address %x\n", add);
463 PSXHW_LOG("*Known 32bit read at address %x\n", add);
468 void psxHwWrite8(u32 add, u8 value) {
469 switch (add & 0x1fffffff) {
470 case 0x1f801040: sioWrite8(value); break;
\r
471 case 0x1f801800: cdrWrite0(value); break;
472 case 0x1f801801: cdrWrite1(value); break;
473 case 0x1f801802: cdrWrite2(value); break;
474 case 0x1f801803: cdrWrite3(value); break;
476 case 0x1f801041: case 0x1f801042: case 0x1f801043:
477 case 0x1f801044: case 0x1f801045:
478 case 0x1f801046: case 0x1f801047:
479 case 0x1f801048: case 0x1f801049:
480 case 0x1f80104a: case 0x1f80104b:
481 case 0x1f80104c: case 0x1f80104d:
482 case 0x1f80104e: case 0x1f80104f:
483 case 0x1f801050: case 0x1f801051:
484 case 0x1f801054: case 0x1f801055:
485 case 0x1f801058: case 0x1f801059:
486 case 0x1f80105a: case 0x1f80105b:
487 case 0x1f80105c: case 0x1f80105d:
488 case 0x1f801100: case 0x1f801101:
489 case 0x1f801104: case 0x1f801105:
490 case 0x1f801108: case 0x1f801109:
491 case 0x1f801110: case 0x1f801111:
492 case 0x1f801114: case 0x1f801115:
493 case 0x1f801118: case 0x1f801119:
494 case 0x1f801120: case 0x1f801121:
495 case 0x1f801124: case 0x1f801125:
496 case 0x1f801128: case 0x1f801129:
497 case 0x1f801810: case 0x1f801811:
498 case 0x1f801812: case 0x1f801813:
499 case 0x1f801814: case 0x1f801815:
500 case 0x1f801816: case 0x1f801817:
501 case 0x1f801820: case 0x1f801821:
502 case 0x1f801822: case 0x1f801823:
503 case 0x1f801824: case 0x1f801825:
504 case 0x1f801826: case 0x1f801827:
505 log_unhandled("unhandled w8 %08x @%08x\n", add, psxRegs.pc);
508 if (0x1f801c00 <= add && add < 0x1f802000) {
509 log_unhandled("spu w8 %02x @%08x\n", value, psxRegs.pc);
511 SPU_writeRegister(add, value, psxRegs.cycle);
517 PSXHW_LOG("*Unknown 8bit write at address %x value %x\n", add, value);
523 PSXHW_LOG("*Known 8bit write at address %x value %x\n", add, value);
527 void psxHwWrite16(u32 add, u16 value) {
528 switch (add & 0x1fffffff) {
530 sioWrite8((unsigned char)value);
531 sioWrite8((unsigned char)(value>>8));
532 PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
535 sioWriteStat16(value);
536 PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
539 sioWriteMode16(value);
540 PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
542 case 0x1f80104a: // control register
543 sioWriteCtrl16(value);
544 PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
546 case 0x1f80104e: // baudrate register
547 sioWriteBaud16(value);
548 PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
552 PSXHW_LOG("IREG 16bit write %x\n", value);
554 psxHwWriteIstat(value);
559 PSXHW_LOG("IMASK 16bit write %x\n", value);
561 psxHwWriteImask(value);
566 PSXHW_LOG("COUNTER 0 COUNT 16bit write %x\n", value);
568 psxRcntWcount(0, value); return;
571 PSXHW_LOG("COUNTER 0 MODE 16bit write %x\n", value);
573 psxRcntWmode(0, value); return;
576 PSXHW_LOG("COUNTER 0 TARGET 16bit write %x\n", value);
578 psxRcntWtarget(0, value); return;
582 PSXHW_LOG("COUNTER 1 COUNT 16bit write %x\n", value);
584 psxRcntWcount(1, value); return;
587 PSXHW_LOG("COUNTER 1 MODE 16bit write %x\n", value);
589 psxRcntWmode(1, value); return;
592 PSXHW_LOG("COUNTER 1 TARGET 16bit write %x\n", value);
594 psxRcntWtarget(1, value); return;
598 PSXHW_LOG("COUNTER 2 COUNT 16bit write %x\n", value);
600 psxRcntWcount(2, value); return;
603 PSXHW_LOG("COUNTER 2 MODE 16bit write %x\n", value);
605 psxRcntWmode(2, value); return;
608 PSXHW_LOG("COUNTER 2 TARGET 16bit write %x\n", value);
610 psxRcntWtarget(2, value); return;
630 log_unhandled("unhandled w16 %08x @%08x\n", add, psxRegs.pc);
633 if (0x1f801c00 <= add && add < 0x1f802000) {
634 SPU_writeRegister(add, value, psxRegs.cycle);
638 psxHu16ref(add) = SWAPu16(value);
640 PSXHW_LOG("*Unknown 16bit write at address %x value %x\n", add, value);
644 psxHu16ref(add) = SWAPu16(value);
646 PSXHW_LOG("*Known 16bit write at address %x value %x\n", add, value);
650 #define DmaExec(n) { \
651 if (value & SWAPu32(HW_DMA##n##_CHCR) & 0x01000000) \
652 log_unhandled("dma" #n " %08x -> %08x\n", HW_DMA##n##_CHCR, value); \
653 HW_DMA##n##_CHCR = SWAPu32(value); \
655 if (SWAPu32(HW_DMA##n##_CHCR) & 0x01000000 && SWAPu32(HW_DMA_PCR) & (8 << (n * 4))) { \
656 psxDma##n(SWAPu32(HW_DMA##n##_MADR), SWAPu32(HW_DMA##n##_BCR), SWAPu32(HW_DMA##n##_CHCR)); \
660 void psxHwWrite32(u32 add, u32 value) {
661 switch (add & 0x1fffffff) {
663 sioWrite8((unsigned char)value);
664 sioWrite8((unsigned char)((value&0xff) >> 8));
665 sioWrite8((unsigned char)((value&0xff) >> 16));
666 sioWrite8((unsigned char)((value&0xff) >> 24));
667 PAD_LOG("sio write32 %x\n", value);
671 PSXHW_LOG("RAM size write %x\n", value);
672 psxHu32ref(add) = SWAPu32(value);
678 PSXHW_LOG("IREG 32bit write %x\n", value);
680 psxHwWriteIstat(value);
684 PSXHW_LOG("IMASK 32bit write %x\n", value);
686 psxHwWriteImask(value);
691 PSXHW_LOG("DMA0 MADR 32bit write %x\n", value);
692 HW_DMA0_MADR = SWAPu32(value); return; // DMA0 madr
694 PSXHW_LOG("DMA0 BCR 32bit write %x\n", value);
695 HW_DMA0_BCR = SWAPu32(value); return; // DMA0 bcr
699 PSXHW_LOG("DMA0 CHCR 32bit write %x\n", value);
701 DmaExec(0); // DMA0 chcr (MDEC in DMA)
706 PSXHW_LOG("DMA1 MADR 32bit write %x\n", value);
707 HW_DMA1_MADR = SWAPu32(value); return; // DMA1 madr
709 PSXHW_LOG("DMA1 BCR 32bit write %x\n", value);
710 HW_DMA1_BCR = SWAPu32(value); return; // DMA1 bcr
714 PSXHW_LOG("DMA1 CHCR 32bit write %x\n", value);
716 DmaExec(1); // DMA1 chcr (MDEC out DMA)
721 PSXHW_LOG("DMA2 MADR 32bit write %x\n", value);
722 HW_DMA2_MADR = SWAPu32(value); return; // DMA2 madr
724 PSXHW_LOG("DMA2 BCR 32bit write %x\n", value);
725 HW_DMA2_BCR = SWAPu32(value); return; // DMA2 bcr
729 PSXHW_LOG("DMA2 CHCR 32bit write %x\n", value);
731 DmaExec(2); // DMA2 chcr (GPU DMA)
736 PSXHW_LOG("DMA3 MADR 32bit write %x\n", value);
737 HW_DMA3_MADR = SWAPu32(value); return; // DMA3 madr
739 PSXHW_LOG("DMA3 BCR 32bit write %x\n", value);
740 HW_DMA3_BCR = SWAPu32(value); return; // DMA3 bcr
744 PSXHW_LOG("DMA3 CHCR 32bit write %x\n", value);
746 DmaExec(3); // DMA3 chcr (CDROM DMA)
752 PSXHW_LOG("DMA4 MADR 32bit write %x\n", value);
753 HW_DMA4_MADR = SWAPu32(value); return; // DMA4 madr
755 PSXHW_LOG("DMA4 BCR 32bit write %x\n", value);
756 HW_DMA4_BCR = SWAPu32(value); return; // DMA4 bcr
760 PSXHW_LOG("DMA4 CHCR 32bit write %x\n", value);
762 DmaExec(4); // DMA4 chcr (SPU DMA)
766 case 0x1f8010d0: break; //DMA5write_madr();
767 case 0x1f8010d4: break; //DMA5write_bcr();
768 case 0x1f8010d8: break; //DMA5write_chcr(); // Not needed
773 PSXHW_LOG("DMA6 MADR 32bit write %x\n", value);
774 HW_DMA6_MADR = SWAPu32(value); return; // DMA6 bcr
776 PSXHW_LOG("DMA6 BCR 32bit write %x\n", value);
777 HW_DMA6_BCR = SWAPu32(value); return; // DMA6 bcr
781 PSXHW_LOG("DMA6 CHCR 32bit write %x\n", value);
783 DmaExec(6); // DMA6 chcr (OT clear)
788 PSXHW_LOG("DMA PCR 32bit write %x\n", value);
789 HW_DMA_PCR = SWAPu32(value);
795 PSXHW_LOG("DMA ICR 32bit write %x\n", value);
797 psxHwWriteDmaIcr32(value);
802 PSXHW_LOG("GPU DATA 32bit write %x\n", value);
804 GPU_writeData(value); return;
807 PSXHW_LOG("GPU STATUS 32bit write %x\n", value);
809 psxHwWriteGpuSR(value);
813 mdecWrite0(value); break;
815 mdecWrite1(value); break;
819 PSXHW_LOG("COUNTER 0 COUNT 32bit write %x\n", value);
821 psxRcntWcount(0, value & 0xffff); return;
824 PSXHW_LOG("COUNTER 0 MODE 32bit write %x\n", value);
826 psxRcntWmode(0, value); return;
829 PSXHW_LOG("COUNTER 0 TARGET 32bit write %x\n", value);
831 psxRcntWtarget(0, value & 0xffff); return; // HW_DMA_ICR&= SWAP32((~value)&0xff000000);
835 PSXHW_LOG("COUNTER 1 COUNT 32bit write %x\n", value);
837 psxRcntWcount(1, value & 0xffff); return;
840 PSXHW_LOG("COUNTER 1 MODE 32bit write %x\n", value);
842 psxRcntWmode(1, value); return;
845 PSXHW_LOG("COUNTER 1 TARGET 32bit write %x\n", value);
847 psxRcntWtarget(1, value & 0xffff); return;
851 PSXHW_LOG("COUNTER 2 COUNT 32bit write %x\n", value);
853 psxRcntWcount(2, value & 0xffff); return;
856 PSXHW_LOG("COUNTER 2 MODE 32bit write %x\n", value);
858 psxRcntWmode(2, value); return;
861 PSXHW_LOG("COUNTER 2 TARGET 32bit write %x\n", value);
863 psxRcntWtarget(2, value & 0xffff); return;
873 log_unhandled("unhandled w32 %08x @%08x\n", add, psxRegs.pc);
876 // Dukes of Hazard 2 - car engine noise
877 if (0x1f801c00 <= add && add < 0x1f802000) {
878 SPU_writeRegister(add, value&0xffff, psxRegs.cycle);
879 SPU_writeRegister(add + 2, value>>16, psxRegs.cycle);
883 psxHu32ref(add) = SWAPu32(value);
885 PSXHW_LOG("*Unknown 32bit write at address %x value %x\n", add, value);
889 psxHu32ref(add) = SWAPu32(value);
891 PSXHW_LOG("*Known 32bit write at address %x value %x\n", add, value);
895 int psxHwFreeze(void *f, int Mode) {