libpcsxcore/psxhw.c

   1 /***************************************************************************
   2  *   Copyright (C) 2007 Ryan Schultz, PCSX-df Team, PCSX team              *
   3  *                                                                         *
   4  *   This program is free software; you can redistribute it and/or modify  *
   5  *   it under the terms of the GNU General Public License as published by  *
   6  *   the Free Software Foundation; either version 2 of the License, or     *
   7  *   (at your option) any later version.                                   *
   8  *                                                                         *
   9  *   This program is distributed in the hope that it will be useful,       *
  10  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  11  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  12  *   GNU General Public License for more details.                          *
  13  *                                                                         *
  14  *   You should have received a copy of the GNU General Public License     *
  15  *   along with this program; if not, write to the                         *
  16  *   Free Software Foundation, Inc.,                                       *
  17  *   51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA.           *
  18  ***************************************************************************/
  19
  20 /*
  21 * Functions for PSX hardware control.
  22 */
  23
  24 #include "psxhw.h"
  25 #include "psxevents.h"
  26 #include "mdec.h"
  27 #include "cdrom.h"
  28 #include "gpu.h"
  29 #include "../include/compiler_features.h"
  30
  31 void psxHwReset() {
  32         memset(psxH, 0, 0x10000);
  33
  34         mdecInit(); // initialize mdec decoder
  35         cdrReset();
  36         psxRcntInit();
  37         HW_GPU_STATUS = SWAP32(0x10802000);
  38 }
  39
  40 void psxHwWriteIstat(u32 value)
  41 {
  42         u32 stat = psxHu16(0x1070) & value;
  43         psxHu16ref(0x1070) = SWAPu16(stat);
  44
  45         psxRegs.CP0.n.Cause &= ~0x400;
  46         if (stat & psxHu16(0x1074))
  47                 psxRegs.CP0.n.Cause |= 0x400;
  48 }
  49
  50 void psxHwWriteImask(u32 value)
  51 {
  52         u32 stat = psxHu16(0x1070);
  53         psxHu16ref(0x1074) = SWAPu16(value);
  54         if (stat & value) {
  55                 //if ((psxRegs.CP0.n.SR & 0x401) == 0x401)
  56                 //      log_unhandled("irq on unmask @%08x\n", psxRegs.pc);
  57                 set_event(PSXINT_NEWDRC_CHECK, 1);
  58         }
  59         psxRegs.CP0.n.Cause &= ~0x400;
  60         if (stat & value)
  61                 psxRegs.CP0.n.Cause |= 0x400;
  62 }
  63
  64 #define make_dma_func(n, abort_func) \
  65 void psxHwWriteChcr##n(u32 value) \
  66 { \
  67         u32 old = SWAPu32(HW_DMA##n##_CHCR); \
  68         if (n == 6) { value &= 0x51000002; value |= 2; } \
  69         else        { value &= 0x71770703; } \
  70         if (value == old) \
  71                 return; \
  72         if (old & 0x01000000) \
  73                 log_unhandled("%u dma" #n " %08x -> %08x\n", psxRegs.cycle, old, value); \
  74         HW_DMA##n##_CHCR = SWAPu32(value); \
  75         if ((value ^ old) & 0x01000000) { \
  76                 if (!(value & 0x01000000)) \
  77                         abort_func; \
  78                 else if (HW_DMA_PCR & SWAPu32(8u << (n * 4))) \
  79                         psxDma##n(SWAPu32(HW_DMA##n##_MADR), SWAPu32(HW_DMA##n##_BCR), value); \
  80         } \
  81 }
  82
  83 make_dma_func(0,)
  84 make_dma_func(1,)
  85 make_dma_func(2, psxAbortDma2())
  86 make_dma_func(3,)
  87 make_dma_func(4,)
  88 make_dma_func(6,)
  89
  90 void psxHwWriteDmaPcr32(u32 value)
  91 {
  92         // todo: can this also pause/stop live dma?
  93         u32 on = (SWAPu32(HW_DMA_PCR) ^ value) & value & 0x08888888;
  94         u32 chcr;
  95         HW_DMA_PCR = SWAPu32(value);
  96         if (likely(!on))
  97                 return;
  98         #define DO(n) \
  99         chcr = SWAPu32(HW_DMA##n##_CHCR); \
 100         if ((on & (8u << 4*n)) && (chcr & 0x01000000)) \
 101                 psxDma##n(SWAPu32(HW_DMA##n##_MADR), SWAPu32(HW_DMA##n##_BCR), chcr)
 102         DO(0);
 103         DO(1);
 104         // breaks Kyuutenkai. Probably needs better timing or
 105         // proper gpu side dma enable handling
 106         //DO(2);
 107         if ((on & (8u << 4*2)) && (SWAPu32(HW_DMA2_CHCR) & 0x01000000))
 108                 log_unhandled("dma2 pcr write ignored\n");
 109         DO(3);
 110         DO(4);
 111         DO(6);
 112         #undef DO
 113 }
 114
 115 void psxHwWriteDmaIcr32(u32 value)
 116 {
 117         u32 tmp = value & 0x00ff803f;
 118         tmp |= (SWAPu32(HW_DMA_ICR) & ~value) & 0x7f000000;
 119         if ((tmp & HW_DMA_ICR_GLOBAL_ENABLE && tmp & 0x7f000000)
 120             || tmp & HW_DMA_ICR_BUS_ERROR) {
 121                 if (!(SWAPu32(HW_DMA_ICR) & HW_DMA_ICR_IRQ_SENT))
 122                         psxHu32ref(0x1070) |= SWAP32(8);
 123                 tmp |= HW_DMA_ICR_IRQ_SENT;
 124         }
 125         HW_DMA_ICR = SWAPu32(tmp);
 126 }
 127
 128 void psxHwWriteGpuSR(u32 value)
 129 {
 130         u32 old_sr = HW_GPU_STATUS, new_sr;
 131         GPU_writeStatus(value);
 132         gpuSyncPluginSR();
 133         new_sr = HW_GPU_STATUS;
 134         // "The Next Tetris" seems to rely on the field order after enable
 135         if ((old_sr ^ new_sr) & new_sr & SWAP32(PSXGPU_ILACE))
 136                 frame_counter |= 1;
 137 }
 138
 139 u32 psxHwReadGpuSR(void)
 140 {
 141         u32 v, c = psxRegs.cycle;
 142
 143         // meh2, syncing for img bit, might want to avoid it..
 144         gpuSyncPluginSR();
 145         v = SWAP32(HW_GPU_STATUS);
 146         v |= ((s32)(psxRegs.gpuIdleAfter - c) >> 31) & PSXGPU_nBUSY;
 147
 148         // XXX: because of large timeslices can't use hSyncCount, using rough
 149         // approximization instead. Perhaps better use hcounter code here or something.
 150         if (hSyncCount < 240 && (v & PSXGPU_ILACE_BITS) != PSXGPU_ILACE_BITS)
 151                 v |= PSXGPU_LCF & (c << 20);
 152         return v;
 153 }
 154
 155 u32 sio1ReadStat16(void)
 156 {
 157         // Armored Core, F1 Link cable misdetection
 158         return 0xa0;
 159 }
 160
 161 u8 psxHwRead8(u32 add) {
 162         u8 hard;
 163
 164         switch (add & 0xffff) {
 165         case 0x1040: hard = sioRead8(); break;
 166         case 0x1800: hard = cdrRead0(); break;
 167         case 0x1801: hard = cdrRead1(); break;
 168         case 0x1802: hard = cdrRead2(); break;
 169         case 0x1803: hard = cdrRead3(); break;
 170
 171         case 0x1041: case 0x1042: case 0x1043:
 172         case 0x1044: case 0x1045:
 173         case 0x1046: case 0x1047:
 174         case 0x1048: case 0x1049:
 175         case 0x104a: case 0x104b:
 176         case 0x104c: case 0x104d:
 177         case 0x104e: case 0x104f:
 178         case 0x1050: case 0x1051:
 179         case 0x1054: case 0x1055:
 180         case 0x1058: case 0x1059:
 181         case 0x105a: case 0x105b:
 182         case 0x105c: case 0x105d:
 183         case 0x1100: case 0x1101:
 184         case 0x1104: case 0x1105:
 185         case 0x1108: case 0x1109:
 186         case 0x1110: case 0x1111:
 187         case 0x1114: case 0x1115:
 188         case 0x1118: case 0x1119:
 189         case 0x1120: case 0x1121:
 190         case 0x1124: case 0x1125:
 191         case 0x1128: case 0x1129:
 192         case 0x1810: case 0x1811:
 193         case 0x1812: case 0x1813:
 194         case 0x1814: case 0x1815:
 195         case 0x1816: case 0x1817:
 196         case 0x1820: case 0x1821:
 197         case 0x1822: case 0x1823:
 198         case 0x1824: case 0x1825:
 199         case 0x1826: case 0x1827:
 200                 log_unhandled("unhandled r8  %08x @%08x\n", add, psxRegs.pc);
 201                 // falthrough
 202         default:
 203                 if (0x1f801c00 <= add && add < 0x1f802000) {
 204                         u16 val = SPU_readRegister(add & ~1, psxRegs.cycle);
 205                         hard = (add & 1) ? val >> 8 : val;
 206                         break;
 207                 }
 208                 hard = psxHu8(add);
 209         }
 210
 211         //printf("r8  %08x       %02x @%08x\n", add, hard, psxRegs.pc);
 212         return hard;
 213 }
 214
 215 u16 psxHwRead16(u32 add) {
 216         unsigned short hard;
 217
 218         switch (add & 0xffff) {
 219         case 0x1040: hard = sioRead8(); break;
 220         case 0x1044: hard = sioReadStat16(); break;
 221         case 0x1048: hard = sioReadMode16(); break;
 222         case 0x104a: hard = sioReadCtrl16(); break;
 223         case 0x104e: hard = sioReadBaud16(); break;
 224         case 0x1054: hard = sio1ReadStat16(); break;
 225         case 0x1100: hard = psxRcntRcount0(); break;
 226         case 0x1104: hard = psxRcntRmode(0); break;
 227         case 0x1108: hard = psxRcntRtarget(0); break;
 228         case 0x1110: hard = psxRcntRcount1(); break;
 229         case 0x1114: hard = psxRcntRmode(1); break;
 230         case 0x1118: hard = psxRcntRtarget(1); break;
 231         case 0x1120: hard = psxRcntRcount2(); break;
 232         case 0x1124: hard = psxRcntRmode(2); break;
 233         case 0x1128: hard = psxRcntRtarget(2); break;
 234
 235         case 0x1042:
 236         case 0x1046:
 237         case 0x104c:
 238         case 0x1050:
 239         case 0x1058:
 240         case 0x105a:
 241         case 0x105c:
 242         case 0x1800:
 243         case 0x1802:
 244         case 0x1810:
 245         case 0x1812:
 246         case 0x1814:
 247         case 0x1816:
 248         case 0x1820:
 249         case 0x1822:
 250         case 0x1824:
 251         case 0x1826:
 252                 log_unhandled("unhandled r16 %08x @%08x\n", add, psxRegs.pc);
 253                 // falthrough
 254         default:
 255                 if (0x1f801c00 <= add && add < 0x1f802000) {
 256                         hard = SPU_readRegister(add, psxRegs.cycle);
 257                         break;
 258                 }
 259                 hard = psxHu16(add);
 260         }
 261
 262         //printf("r16 %08x     %04x @%08x\n", add, hard, psxRegs.pc);
 263         return hard;
 264 }
 265
 266 u32 psxHwRead32(u32 add) {
 267         u32 hard;
 268
 269         switch (add & 0xffff) {
 270         case 0x1040: hard = sioRead8(); break;
 271         case 0x1044: hard = sioReadStat16(); break;
 272         case 0x1100: hard = psxRcntRcount0(); break;
 273         case 0x1104: hard = psxRcntRmode(0); break;
 274         case 0x1108: hard = psxRcntRtarget(0); break;
 275         case 0x1110: hard = psxRcntRcount1(); break;
 276         case 0x1114: hard = psxRcntRmode(1); break;
 277         case 0x1118: hard = psxRcntRtarget(1); break;
 278         case 0x1120: hard = psxRcntRcount2(); break;
 279         case 0x1124: hard = psxRcntRmode(2); break;
 280         case 0x1128: hard = psxRcntRtarget(2); break;
 281         case 0x1810: hard = GPU_readData(); break;
 282         case 0x1814: hard = psxHwReadGpuSR(); break;
 283         case 0x1820: hard = mdecRead0(); break;
 284         case 0x1824: hard = mdecRead1(); break;
 285
 286         case 0x1048:
 287         case 0x104c:
 288         case 0x1050:
 289         case 0x1054:
 290         case 0x1058:
 291         case 0x105c:
 292         case 0x1800:
 293                 log_unhandled("unhandled r32 %08x @%08x\n", add, psxRegs.pc);
 294                 // falthrough
 295         default:
 296                 if (0x1f801c00 <= add && add < 0x1f802000) {
 297                         hard = SPU_readRegister(add, psxRegs.cycle);
 298                         hard |= SPU_readRegister(add + 2, psxRegs.cycle) << 16;
 299                         break;
 300                 }
 301                 hard = psxHu32(add);
 302         }
 303         //printf("r32 %08x %08x @%08x\n", add, hard, psxRegs.pc);
 304         return hard;
 305 }
 306
 307 void psxHwWrite8(u32 add, u32 value) {
 308         switch (add & 0xffff) {
 309         case 0x1040: sioWrite8(value); return;
 310         case 0x10f6:
 311                 // nocash documents it as forced w32, but still games use this?
 312                 break;
 313         case 0x1800: cdrWrite0(value); return;
 314         case 0x1801: cdrWrite1(value); return;
 315         case 0x1802: cdrWrite2(value); return;
 316         case 0x1803: cdrWrite3(value); return;
 317         case 0x2041: break; // "POST (external 7 segment display)"
 318
 319         default:
 320                 if (0x1f801c00 <= add && add < 0x1f802000) {
 321                         log_unhandled("spu w8 %02x @%08x\n", value, psxRegs.pc);
 322                         if (!(add & 1))
 323                                 SPU_writeRegister(add, value, psxRegs.cycle);
 324                         return;
 325                 }
 326                 else
 327                         log_unhandled("unhandled w8  %08x %08x @%08x\n",
 328                                 add, value, psxRegs.pc);
 329         }
 330         psxHu8(add) = value;
 331 }
 332
 333 void psxHwWrite16(u32 add, u32 value) {
 334         switch (add & 0xffff) {
 335         case 0x1040: sioWrite8(value); return;
 336         case 0x1044: sioWriteStat16(value); return;
 337         case 0x1048: sioWriteMode16(value); return;
 338         case 0x104a: sioWriteCtrl16(value); return;
 339         case 0x104e: sioWriteBaud16(value); return;
 340         case 0x1070: psxHwWriteIstat(value); return;
 341         case 0x1074: psxHwWriteImask(value); return;
 342         case 0x1100: psxRcntWcount(0, value); return;
 343         case 0x1104: psxRcntWmode(0, value); return;
 344         case 0x1108: psxRcntWtarget(0, value); return;
 345         case 0x1110: psxRcntWcount(1, value); return;
 346         case 0x1114: psxRcntWmode(1, value); return;
 347         case 0x1118: psxRcntWtarget(1, value); return;
 348         case 0x1120: psxRcntWcount(2, value); return;
 349         case 0x1124: psxRcntWmode(2, value); return;
 350         case 0x1128: psxRcntWtarget(2, value); return;
 351
 352         // forced write32:
 353         case 0x1088: // DMA0 chcr (MDEC in DMA)
 354         case 0x108c: psxHwWriteChcr0(value); return;
 355         case 0x1098: // DMA1 chcr (MDEC out DMA)
 356         case 0x109c: psxHwWriteChcr1(value); return;
 357         case 0x10a8: // DMA2 chcr (GPU DMA)
 358         case 0x10ac: psxHwWriteChcr2(value); return;
 359         case 0x10b8: // DMA3 chcr (CDROM DMA)
 360         case 0x10bc: psxHwWriteChcr3(value); return;
 361         case 0x10c8: // DMA4 chcr (SPU DMA)
 362         case 0x10cc: psxHwWriteChcr4(value); return;
 363         case 0x10e8: // DMA6 chcr (OT clear)
 364         case 0x10ec: psxHwWriteChcr6(value); return;
 365         case 0x10f0: psxHwWriteDmaPcr32(value); return;
 366         case 0x10f4: psxHwWriteDmaIcr32(value); return;
 367
 368         // forced write32 with no immediate effect:
 369         case 0x1014:
 370         case 0x1060:
 371         case 0x1080:
 372         case 0x1090:
 373         case 0x10a0:
 374         case 0x10b0:
 375         case 0x10c0:
 376         case 0x10d0:
 377         case 0x10e0:
 378                 psxHu32ref(add) = SWAPu32(value);
 379                 return;
 380
 381         case 0x1800:
 382         case 0x1802:
 383         case 0x1810:
 384         case 0x1812:
 385         case 0x1814:
 386         case 0x1816:
 387         case 0x1820:
 388         case 0x1822:
 389         case 0x1824:
 390         case 0x1826:
 391                 log_unhandled("unhandled w16 %08x @%08x\n", add, psxRegs.pc);
 392                 break;
 393
 394         default:
 395                 if (0x1f801c00 <= add && add < 0x1f802000) {
 396                         SPU_writeRegister(add, value, psxRegs.cycle);
 397                         return;
 398                 }
 399                 else if (0x1f801000 <= add && add < 0x1f801800)
 400                         log_unhandled("unhandled w16 %08x %08x @%08x\n",
 401                                 add, value, psxRegs.pc);
 402         }
 403         psxHu16ref(add) = SWAPu16(value);
 404 }
 405
 406 void psxHwWrite32(u32 add, u32 value) {
 407         switch (add & 0xffff) {
 408         case 0x1040: sioWrite8(value); return;
 409         case 0x1070: psxHwWriteIstat(value); return;
 410         case 0x1074: psxHwWriteImask(value); return;
 411         case 0x1088: // DMA0 chcr (MDEC in DMA)
 412         case 0x108c: psxHwWriteChcr0(value); return;
 413         case 0x1098: // DMA1 chcr (MDEC out DMA)
 414         case 0x109c: psxHwWriteChcr1(value); return;
 415         case 0x10a8: // DMA2 chcr (GPU DMA)
 416         case 0x10ac: psxHwWriteChcr2(value); return;
 417         case 0x10b8: // DMA3 chcr (CDROM DMA)
 418         case 0x10bc: psxHwWriteChcr3(value); return;
 419         case 0x10c8: // DMA4 chcr (SPU DMA)
 420         case 0x10cc: psxHwWriteChcr4(value); return;
 421         case 0x10e8: // DMA6 chcr (OT clear)
 422         case 0x10ec: psxHwWriteChcr6(value); return;
 423         case 0x10f0: psxHwWriteDmaPcr32(value); return;
 424         case 0x10f4: psxHwWriteDmaIcr32(value); return;
 425
 426         case 0x1810: GPU_writeData(value); return;
 427         case 0x1814: psxHwWriteGpuSR(value); return;
 428         case 0x1820: mdecWrite0(value); break;
 429         case 0x1824: mdecWrite1(value); break;
 430
 431         case 0x1100: psxRcntWcount(0, value & 0xffff); return;
 432         case 0x1104: psxRcntWmode(0, value); return;
 433         case 0x1108: psxRcntWtarget(0, value & 0xffff); return;
 434         case 0x1110: psxRcntWcount(1, value & 0xffff); return;
 435         case 0x1114: psxRcntWmode(1, value); return;
 436         case 0x1118: psxRcntWtarget(1, value & 0xffff); return;
 437         case 0x1120: psxRcntWcount(2, value & 0xffff); return;
 438         case 0x1124: psxRcntWmode(2, value); return;
 439         case 0x1128: psxRcntWtarget(2, value & 0xffff); return;
 440
 441         case 0x1044:
 442         case 0x1048:
 443         case 0x104c:
 444         case 0x1050:
 445         case 0x1054:
 446         case 0x1058:
 447         case 0x105c:
 448         case 0x1800:
 449                 log_unhandled("unhandled w32 %08x %08x @%08x\n", add, value, psxRegs.pc);
 450                 break;
 451
 452         default:
 453                 if (0x1f801c00 <= add && add < 0x1f802000) {
 454                         SPU_writeRegister(add, value&0xffff, psxRegs.cycle);
 455                         SPU_writeRegister(add + 2, value>>16, psxRegs.cycle);
 456                         return;
 457                 }
 458         }
 459         psxHu32ref(add) = SWAPu32(value);
 460 }
 461
 462 int psxHwFreeze(void *f, int Mode) {
 463         return 0;
 464 }