2 * include/asm-arm/arch-mmsp2/mmsp2-regs.h
4 * Copyright (C) 2004,2005 DIGNSYS Inc. (www.dignsys.com)
5 * Kane Ahn < hbahn@dignsys.com >
6 * hhsong < hhsong@dignsys.com >
12 static const char * const regnames[0x10000] = {
15 * BANK C (Static) Memory Control Register
17 [0x3a00] = "MEMCFG", /* BANK C configuration */
18 [0x3a02] = "MEMTIME0", /* BANK C Timing #0 */
19 [0x3a04] = "MEMTIME1", /* BANK C Timing #1 */
20 [0x3a06] = "MEMTIME2", /* BANK C Timing #2 */
21 [0x3a08] = "MEMTIME3", /* BANK C Timing #3 */
22 [0x3a0a] = "MEMTIME4", /* BANK C Timing #4 */
23 [0x3a0e] = "MEMWAITCTRL", /* BANK C Wait Control */
24 [0x3a10] = "MEMPAGE", /* BANK C Page Control */
25 [0x3a12] = "MEMIDETIME", /* BANK C IDE Timing Control */
27 [0x3a14] = "MEMPCMCIAM", /* BANK C PCMCIA Timing */
28 [0x3a16] = "MEMPCMCIAA", /* PCMCIA Attribute Timing */
29 [0x3a18] = "MEMPCMCIAI", /* PCMCIA I/O Timing */
30 [0x3a1a] = "MEMPCMCIAWAIT", /* PCMCIA Wait Timing */
32 [0x3a1c] = "MEMEIDEWAIT", /* IDE Wait Timing */
34 [0x3a20] = "MEMDTIMEOUT", /* DMA Timeout */
35 [0x3a22] = "MEMDMACTRL", /* DMA Control */
36 [0x3a24] = "MEMDMAPOL", /* DMA Polarity */
37 [0x3a26] = "MEMDMATIME0", /* DMA Timing #0 */
38 [0x3a28] = "MEMDMATIME1", /* DMA Timing #1 */
39 [0x3a2a] = "MEMDMATIME2", /* DMA Timing #2 */
40 [0x3a2c] = "MEMDMATIME3", /* DMA Timing #3 */
41 [0x3a2e] = "MEMDMATIME4", /* DMA Timing #4 */
42 [0x3a30] = "MEMDMATIME5", /* DMA Timing #5 */
43 [0x3a32] = "MEMDMATIME6", /* DMA Timing #6 */
44 [0x3a34] = "MEMDMATIME7", /* DMA Timing #7 */
45 [0x3a36] = "MEMDMATIME8", /* DMA Timing #8 */
46 [0x3a38] = "MEMDMASTRB", /* DMA Strobe Control */
48 [0x3a3a] = "MEMNANDCTRL", /* NAND FLASH Control */
49 [0x3a3c] = "MEMNANDTIME", /* NAND FLASH Timing */
50 [0x3a3e] = "MEMNANDECC0", /* NAND FLASH ECC0 */
51 [0x3a40] = "MEMNANDECC1", /* NAND FLASH ECC1 */
52 [0x3a42] = "MEMNANDECC2", /* NAND FLASH ECC2 */
53 [0x3a44] = "MEMNANDCNT", /* NAND FLASH Data Counter */
55 /* Bank A Memory (SDRAM) Control Register */
56 [0x3800] = "MEMCFGX", /* SDRAM Configuration */
57 [0x3802] = "MEMTIMEX0", /* SDRAM Timing #0 */
58 [0x3804] = "MEMTIMEX1", /* SDRAM Timing #1 */
59 [0x3806] = "MEMACTPWDX", /* Active Power Down Ctrl */
60 [0x3808] = "MEMREFX", /* Refresh Ctrl */
64 * Clocks and Power Manager
66 [0x0900] = "PWMODE", /* Power Mode */
67 [0x0902] = "CLKCHGST", /* Clock Change Status */
68 [0x0904] = "SYSCLKEN", /* System Clock Enable */
69 [0x0908] = "COMCLKEN", /* Communication Device Clk En */
70 [0x090a] = "VGCLKEN", /* Video & Graphic Device Clk En */
71 [0x090c] = "ASCLKEN", /* Audio & Storage Device Clk En */
72 [0x0910] = "FPLLSETV", /* FCLK PLL Setting Value Write */
73 [0x0912] = "FPLLVSET", /* FCLK PLL Value Setting */
74 [0x0914] = "UPLLSETV", /* UCLK PLL Setting Value Write */
75 [0x0916] = "UPLLVSET", /* UCLK PLL Value Setting */
76 [0x0918] = "APLLSETV", /* ACLK PLL Setting Value Write */
77 [0x091a] = "APLLVSET", /* ACLK PLL Value Setting */
78 [0x091c] = "SYSCSET", /* System CLK PLL Divide Value */
79 [0x091e] = "ESYSCSET", /* External System Clk Time Set */
80 [0x0920] = "UIRMCSET", /* USB/IRDA/MMC Clk Gen */
81 [0x0922] = "AUDICSET", /* Audio Ctrl Clk Gen */
82 [0x092e] = "SPDICSET", /* SPDIF Ctrl Clk Gen */
83 [0x0924] = "DISPCSET", /* Display Clk Gen */
84 [0x0926] = "IMAGCSET", /* Image Pixel Clk Gen */
85 [0x0928] = "URT0CSET", /* UART 0/1 Clk Gen */
86 [0x092a] = "UAR1CSET", /* UART 2/3 Clk Gen */
87 [0x092c] = "A940TMODE", /* ARM940T CPU Power Manage Mode */
95 [0x080c] = "IPRIORITY",
97 [0x0814] = "INTOFFSET",
112 [0x1208] = "UTRSTAT0",
113 [0x120a] = "UERRSTAT0",
114 [0x120c] = "UFIFOSTAT0",
115 [0x120e] = "UMODEMSTAT0",
119 [0x1216] = "UTIMEOUTREG0",
125 [0x1228] = "UTRSTAT1",
126 [0x122a] = "UERRSTAT1",
127 [0x122c] = "UFIFOSTAT1",
128 [0x122e] = "UMODEMSTAT1",
132 [0x1236] = "UTIMEOUTREG1",
138 [0x1248] = "UTRSTAT2",
139 [0x124a] = "UERRSTAT2",
140 [0x124c] = "UFIFOSTAT2",
141 [0x124e] = "UMODEMSTAT2",
145 [0x1256] = "UTIMEOUTREG2",
151 [0x1268] = "UTRSTAT3",
152 [0x126a] = "UERRSTAT3",
153 [0x126c] = "UFIFOSTAT3",
154 [0x126e] = "UMODEMSTAT3",
158 [0x1276] = "UTIMEOUTREG3",
160 [0x1280] = "UINTSTAT",
161 [0x1282] = "UPORTCON",
167 [0x0a04] = "TMATCH0",
168 [0x0a08] = "TMATCH1",
169 [0x0a0c] = "TMATCH2",
170 [0x0a10] = "TMATCH3",
171 [0x0a14] = "TCONTROL",
172 [0x0a16] = "TSTATUS",
176 * Real Time Clock (RTC)
178 [0x0c00] = "RTCTSET",
179 [0x0c04] = "RTCTCNT",
180 [0x0c08] = "RTCSTCNT",
181 [0x0c0a] = "TICKSET",
185 [0x0c14] = "RSTCTRL",
187 [0x0c18] = "BOOTCTRL",
188 [0x0c1a] = "LOCKTIME",
189 [0x0c1c] = "RSTTIME",
190 [0x0c1e] = "EXTCTRL",
191 [0x0c20] = "STOPTSET",
192 [0x0c22] = "RTCCTRL",
199 [0x0d02] = "IICSTAT",
206 [0x0E00] = "AC_CTL", /* Control Register */
207 [0x0E02] = "AC_CONFIG", /* Config Register */
208 [0x0E04] = "AC_STA_EN", /* Status Enable Register */
209 [0x0E06] = "AC_GSR", /* Global Status Register */
210 [0x0E08] = "AC_ST_MCH", /* State Machine */
211 [0x0E0C] = "AC_ADDR", /* Codec Address Register */
212 [0x0E0E] = "AC_DATA", /* Codec Read Data Register */
213 [0x0E10] = "AC_CAR", /* Codec Access Register */
214 [0x0F00] = "AC_REG_BASE", /* AC97 Codec Register Base */
217 [0x1400] = "FUNC_ADDR_REG",
218 [0x1402] = "PWR_REG",
219 [0x1404] = "EP_INT_REG",
220 [0x140C] = "USB_INT_REG",
221 [0x140E] = "EP_INT_EN_REG",
222 [0x1416] = "USB_INT_EN_REG",
223 [0x1418] = "FRAME_NUM1_REG",
224 [0x141A] = "FRAME_NUM2_REG",
225 [0x141C] = "INDEX_REG",
226 [0x1440] = "EP0_FIFO_REG",
227 [0x1442] = "EP1_FIFO_REG",
228 [0x1444] = "EP2_FIFO_REG",
229 [0x1446] = "EP3_FIFO_REG",
230 [0x1448] = "EP4_FIFO_REG",
231 [0x1460] = "EP1_DMA_CON",
232 [0x1464] = "EP1_DMA_FIFO",
233 [0x1466] = "EP1_DMA_TTC_L",
234 [0x1468] = "EP1_DMA_TTC_M",
235 [0x146A] = "EP1_DMA_TTC_H",
236 [0x146C] = "EP2_DMA_CON",
237 [0x1470] = "EP2_DMA_FIFO",
238 [0x1472] = "EP2_DMA_TTC_L",
239 [0x1474] = "EP2_DMA_TTC_M",
240 [0x1476] = "EP2_DMA_TTC_H",
241 [0x1480] = "EP3_DMA_CON",
242 [0x1484] = "EP3_DMA_FIFO",
243 [0x1486] = "EP3_DMA_TTC_L",
244 [0x1488] = "EP3_DMA_TTC_M",
245 [0x148A] = "EP3_DMA_TTC_H",
246 [0x148C] = "EP4_DMA_CON",
247 [0x1490] = "EP4_DMA_FIFO",
248 [0x1492] = "EP4_DMA_TTC_L",
249 [0x1494] = "EP4_DMA_TTC_M",
250 [0x1496] = "EP4_DMA_TTC_H",
251 [0x1420] = "MAXP_REG",
252 [0x1426] = "OUT_MAXP_REG",
253 [0x1422] = "EP0_CSR",
254 [0x1422] = "IN_CSR1_REG",
255 [0x1424] = "IN_CSR2_REG",
256 [0x1428] = "OUT_CSR1_REG",
257 [0x142A] = "OUT_CSR2_REG",
258 [0x142C] = "OUT_FIFO_CNT1_REG",
259 [0x142E] = "OUT_FIFO_CNT2_REG",
262 [0x4600] = "TPC_ADCCON",
263 [0x4604] = "TPC_ADCDAT",
264 [0x4640] = "TPC_CNTL",
265 [0x4644] = "TPC_INTR",
266 [0x4648] = "TPC_COMP_TP",
267 [0x464c] = "TPC_COMP_U1",
268 [0x4650] = "TPC_COMP_U2",
269 [0x4654] = "TPC_CLK_CNTL",
270 [0x4658] = "TPC_CH_SEL",
271 [0x465c] = "TPC_TIME_PARM1",
272 [0x4660] = "TPC_TIME_PARM2",
273 [0x4664] = "TPC_TIME_PARM3",
274 [0x4668] = "TPC_X_VALUE",
275 [0x466c] = "TPC_Y_VALUE",
276 [0x4670] = "TPC_AZ_VALUE",
277 [0x4674] = "TPC_U1_VALUE",
278 [0x4678] = "TPC_U2_VALUE",
280 /* Dual CPU Interface: mmsp20_type.h */
281 [0x3B40] = "DINT920",
282 [0x3B42] = "DINT940",
283 [0x3B44] = "DPEND920",
284 [0x3B46] = "DPEND940",
285 [0x3B48] = "DCTRL940",
287 /* FDC: mmsp20_type.h */
288 [0x1838] = "DFDC_CNTL",
289 [0x183A] = "DFDC_FRAME_SIZE",
290 [0x183C] = "DFDC_LUMA_OFFSET",
291 [0x183E] = "DFDC_CB_OFFSET",
292 [0x1840] = "DFDC_CR_OFFSET",
293 [0x1842] = "DFDC_DST_BASE_L",
294 [0x1844] = "DFDC_DST_BASE_H",
295 [0x1846] = "DFDC_STATUS",
296 [0x1848] = "DFDC_DERING",
297 [0x184A] = "DFDC_OCC_CNTL",
301 * General Purpose I/O (GPIO)
303 [0x1020] = "GPIOAALTFNLOW",
304 [0x1022] = "GPIOBALTFNLOW",
305 [0x1024] = "GPIOCALTFNLOW",
306 [0x1026] = "GPIODALTFNLOW",
307 [0x1028] = "GPIOEALTFNLOW",
308 [0x102a] = "GPIOFALTFNLOW",
309 [0x102c] = "GPIOGALTFNLOW",
310 [0x102e] = "GPIOHALTFNLOW",
311 [0x1030] = "GPIOIALTFNLOW",
312 [0x1032] = "GPIOJALTFNLOW",
313 [0x1034] = "GPIOKALTFNLOW",
314 [0x1036] = "GPIOLALTFNLOW",
315 [0x1038] = "GPIOMALTFNLOW",
316 [0x103a] = "GPIONALTFNLOW",
317 [0x103c] = "GPIOOALTFNLOW",
319 [0x1040] = "GPIOAALTFNHI",
320 [0x1042] = "GPIOBALTFNHI",
321 [0x1044] = "GPIOCALTFNHI",
322 [0x1046] = "GPIODALTFNHI",
323 [0x1048] = "GPIOEALTFNHI",
324 [0x104a] = "GPIOFALTFNHI",
325 [0x104c] = "GPIOGALTFNHI",
326 [0x104e] = "GPIOHALTFNHI",
327 [0x1050] = "GPIOIALTFNHI",
328 [0x1052] = "GPIOJALTFNHI",
329 [0x1054] = "GPIOKALTFNHI",
330 [0x1056] = "GPIOLALTFNHI",
331 [0x1058] = "GPIOMALTFNHI",
332 [0x105a] = "GPIONALTFNHI",
333 [0x105c] = "GPIOOALTFNHI",
335 [0x1180] = "GPIOAPINLVL",
336 [0x1182] = "GPIOBPINLVL",
337 [0x1184] = "GPIOCPINLVL",
338 [0x1186] = "GPIODPINLVL",
339 [0x1188] = "GPIOEPINLVL",
340 [0x118a] = "GPIOFPINLVL",
341 [0x118c] = "GPIOGPINLVL",
342 [0x118e] = "GPIOHPINLVL",
343 [0x1190] = "GPIOIPINLVL",
344 [0x1192] = "GPIOJPINLVL",
345 [0x1194] = "GPIOKPINLVL",
346 [0x1196] = "GPIOLPINLVL",
347 [0x1198] = "GPIOMPINLVL",
348 [0x119a] = "GPIONPINLVL",
349 [0x119c] = "GPIOOPINLVL",
352 [0x2800] = "DPC_CNTL",
353 [0x2802] = "DPC_FPICNTL",
354 [0x2804] = "DPC_FPIPOL1",
355 [0x2806] = "DPC_FPIPOL2",
356 [0x280a] = "DPC_FPIATV1",
357 [0x280c] = "DPC_FPIATV2",
358 [0x280e] = "DPC_FPIATV3",
359 [0x2816] = "DPC_X_MAX",
360 [0x2818] = "DPC_Y_MAX",
361 [0x281a] = "DPC_HS_WIDTH",
362 [0x281c] = "DPC_HS_STR",
363 [0x281e] = "DPC_HS_END",
364 [0x2820] = "DPC_V_SYNC",
365 [0x2822] = "DPC_V_END",
370 [0x2830] = "DPC_CLKV2",
371 [0x2832] = "DPC_POL",
372 [0x2834] = "DPC_CISSYNC",
373 [0x283a] = "DPC_Y_BLANK",
374 [0x283c] = "DPC_C_BLANK",
375 [0x283e] = "DPC_YP_CSYNC",
376 [0x2840] = "DPC_YN_CSYNC",
377 [0x2842] = "DPC_CP_CSYNC",
378 [0x2844] = "DPC_CN_CSYNC",
379 [0x2846] = "DPC_INTR",
380 [0x2848] = "DPC_CLKCNTL",
383 [0X2880] = "MLC_OVLAY_CNTR",
384 [0X2882] = "MLC_YUV_EFECT",
385 [0X2884] = "MLC_YUV_CNTL",
386 [0X2886] = "MLC_YUVA_TP_HSC",
387 [0X2888] = "MLC_YUVA_BT_HSC",
388 [0X2898] = "MLC_VLA_ENDX",
389 [0X288a] = "MLC_VLA_TP_VSCL",
390 [0X288c] = "MLC_VLA_TP_VSCH",
391 [0X2892] = "MLC_YUVA_TP_PXW",
392 [0X2894] = "MLC_YUVA_BT_PXW",
393 [0X28da] = "MLC_STL_CNTL",
394 [0X28dc] = "MLC_STL_MIXMUX",
395 [0X28de] = "MLC_STL_ALPHAL",
396 [0X28e0] = "MLC_STL_ALPHAH",
397 [0X28e2] = "MLC_STL1_STX",
398 [0X28e4] = "MLC_STL1_ENDX",
399 [0X28e6] = "MLC_STL1_STY",
400 [0X28e8] = "MLC_STL1_ENDY",
401 [0X28ea] = "MLC_STL2_STX",
402 [0X28ec] = "MLC_STL2_ENDX",
403 [0X28ee] = "MLC_STL2_STY",
404 [0X28f0] = "MLC_STL2_ENDY",
405 [0X28f2] = "MLC_STL3_STX",
406 [0X28f4] = "MLC_STL3_ENDX",
407 [0X28f6] = "MLC_STL3_STY",
408 [0X28f8] = "MLC_STL3_ENDY",
409 [0X28fa] = "MLC_STL4_STX",
410 [0X28fc] = "MLC_STL4_ENDX",
411 [0X28fe] = "MLC_STL4_STY",
412 [0X2900] = "MLC_STL4_ENDY",
413 [0X2902] = "MLC_STL_CKEY_GB",
414 [0X2904] = "MLC_STL_CKEY_R",
415 [0X2906] = "MLC_STL_HSC",
416 [0X2908] = "MLC_STL_VSCL",
417 [0X290a] = "MLC_STL_VSCH",
418 [0X290c] = "MLC_STL_HW",
419 [0X290e] = "MLC_STL_OADRL",
420 [0X2910] = "MLC_STL_OADRH",
421 [0X2912] = "MLC_STL_EADRL",
422 [0X2914] = "MLC_STL_EADRH",
423 [0X291e] = "MLC_HWC_CNTL",
424 [0X2920] = "MLC_HWC_STX",
425 [0X2922] = "MLC_HWC_STY",
426 [0X2924] = "MLC_HWC_FGR",
427 [0X2926] = "MLC_HWC_FB",
428 [0X2928] = "MLC_HWC_BGR",
429 [0X292a] = "MLC_HWC_BB",
430 [0X292c] = "MLC_HWC_OADRL",
431 [0X292e] = "MLC_HWC_OADRH",
432 [0X2930] = "MLC_HWC_EADRL",
433 [0X2932] = "MLC_HWC_EADRH",
434 [0X2958] = "MLC_STL_PALLT_A",
435 [0X295a] = "MLC_STL_PALLT_D",
439 #endif /* _MMSP2_H */