1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
3 * Copyright (C) 2009-2010 Ari64 *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
22 #include <stdint.h> //include for uint64_t
25 #include "emu_if.h" //emulator interface
30 #include "assem_x86.h"
33 #include "assem_x64.h"
36 #include "assem_arm.h"
40 #define MAX_OUTPUT_BLOCK_SIZE 262144
41 #define CLOCK_DIVIDER 2
45 signed char regmap_entry[HOST_REGS];
46 signed char regmap[HOST_REGS];
55 uint64_t constmap[HOST_REGS];
63 struct ll_entry *next;
69 char insn[MAXBLOCK][10];
70 u_char itype[MAXBLOCK];
71 u_char opcode[MAXBLOCK];
72 u_char opcode2[MAXBLOCK];
80 u_char dep1[MAXBLOCK];
81 u_char dep2[MAXBLOCK];
85 char likely[MAXBLOCK];
87 uint64_t unneeded_reg[MAXBLOCK];
88 uint64_t unneeded_reg_upper[MAXBLOCK];
89 uint64_t branch_unneeded_reg[MAXBLOCK];
90 uint64_t branch_unneeded_reg_upper[MAXBLOCK];
91 uint64_t p32[MAXBLOCK];
92 uint64_t pr32[MAXBLOCK];
93 signed char regmap_pre[MAXBLOCK][HOST_REGS];
94 signed char regmap[MAXBLOCK][HOST_REGS];
95 signed char regmap_entry[MAXBLOCK][HOST_REGS];
96 uint64_t constmap[MAXBLOCK][HOST_REGS];
97 uint64_t known_value[HOST_REGS];
99 struct regstat regs[MAXBLOCK];
100 struct regstat branch_regs[MAXBLOCK];
101 u_int needed_reg[MAXBLOCK];
102 uint64_t requires_32bit[MAXBLOCK];
103 u_int wont_dirty[MAXBLOCK];
104 u_int will_dirty[MAXBLOCK];
107 u_int instr_addr[MAXBLOCK];
108 u_int link_addr[MAXBLOCK][3];
110 u_int stubs[MAXBLOCK*3][8];
112 u_int literals[1024][2];
117 struct ll_entry *jump_in[4096];
118 struct ll_entry *jump_out[4096];
119 struct ll_entry *jump_dirty[4096];
120 u_int hash_table[65536][4] __attribute__((aligned(16)));
121 char shadow[1048576] __attribute__((aligned(16)));
125 u_int stop_after_jal;
126 extern u_char restore_candidate[512];
127 extern int cycle_count;
129 /* registers that may be allocated */
131 #define HIREG 32 // hi
132 #define LOREG 33 // lo
133 #define FSREG 34 // FPU status (FCSR)
134 #define CSREG 35 // Coprocessor status
135 #define CCREG 36 // Cycle count
136 #define INVCP 37 // Pointer to invalid_code
138 #define FTEMP 38 // FPU/LDL/LDR temporary register
139 #define PTEMP 39 // Prefetch temporary register
140 #define TLREG 40 // TLB mapping offset
141 #define RHASH 41 // Return address hash
142 #define RHTBL 42 // Return address hash table address
143 #define RTEMP 43 // JR/JALR address register
145 #define AGEN1 44 // Address generation temporary register
146 #define AGEN2 45 // Address generation temporary register
147 #define MGEN1 46 // Maptable address generation temporary register
148 #define MGEN2 47 // Maptable address generation temporary register
149 #define BTREG 48 // Branch target temporary register
151 /* instruction types */
152 #define NOP 0 // No operation
153 #define LOAD 1 // Load
154 #define STORE 2 // Store
155 #define LOADLR 3 // Unaligned load
156 #define STORELR 4 // Unaligned store
157 #define MOV 5 // Move
158 #define ALU 6 // Arithmetic/logic
159 #define MULTDIV 7 // Multiply/divide
160 #define SHIFT 8 // Shift by register
161 #define SHIFTIMM 9// Shift by immediate
162 #define IMM16 10 // 16-bit immediate
163 #define RJUMP 11 // Unconditional jump to register
164 #define UJUMP 12 // Unconditional jump
165 #define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
166 #define SJUMP 14 // Conditional branch (regimm format)
167 #define COP0 15 // Coprocessor 0
168 #define COP1 16 // Coprocessor 1
169 #define C1LS 17 // Coprocessor 1 load/store
170 #define FJUMP 18 // Conditional branch (floating point)
171 #define FLOAT 19 // Floating point unit
172 #define FCONV 20 // Convert integer to float
173 #define FCOMP 21 // Floating point compare (sets FSREG)
174 #define SYSCALL 22// SYSCALL
175 #define OTHER 23 // Other
176 #define SPAN 24 // Branch/delay slot spans 2 pages
177 #define NI 25 // Not implemented
178 #define HLECALL 26// PCSX fake opcodes for HLE
179 #define COP2 27 // Coprocessor 2 move
180 #define C2LS 28 // Coprocessor 2 load/store
181 #define C2OP 29 // Coprocessor 2 operation
190 #define LOADBU_STUB 7
191 #define LOADHU_STUB 8
192 #define STOREB_STUB 9
193 #define STOREH_STUB 10
194 #define STOREW_STUB 11
195 #define STORED_STUB 12
196 #define STORELR_STUB 13
197 #define INVCODE_STUB 14
205 int new_recompile_block(int addr);
206 void *get_addr_ht(u_int vaddr);
207 void invalidate_block(u_int block);
208 void invalidate_addr(u_int addr);
209 void remove_hash(int vaddr);
212 void dyna_linker_ds();
214 void verify_code_vm();
215 void verify_code_ds();
218 void fp_exception_ds();
220 void jump_syscall_hle();
223 void new_dyna_leave();
228 void read_nomem_new();
229 void read_nomemb_new();
230 void read_nomemh_new();
231 void read_nomemd_new();
232 void write_nomem_new();
233 void write_nomemb_new();
234 void write_nomemh_new();
235 void write_nomemd_new();
236 void write_rdram_new();
237 void write_rdramb_new();
238 void write_rdramh_new();
239 void write_rdramd_new();
240 extern u_int memory_map[1048576];
242 // Needed by assembler
243 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
244 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
245 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
246 void load_all_regs(signed char i_regmap[]);
247 void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
248 void load_regs_entry(int t);
249 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
253 //#define DEBUG_CYCLE_COUNT 1
256 //#define assem_debug printf
257 //#define inv_debug printf
258 #define assem_debug nullf
259 #define inv_debug nullf
261 static void tlb_hacks()
265 if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
269 switch (ROM_HEADER->Country_code&0xFF)
281 // Unknown country code
285 u_int rom_addr=(u_int)rom;
287 // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
288 // in the lower 4G of memory to use this hack. Copy it if necessary.
289 if((void *)rom>(void *)0xffffffff) {
290 munmap(ROM_COPY, 67108864);
291 if(mmap(ROM_COPY, 12582912,
292 PROT_READ | PROT_WRITE,
293 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
294 -1, 0) <= 0) {printf("mmap() failed\n");}
295 memcpy(ROM_COPY,rom,12582912);
296 rom_addr=(u_int)ROM_COPY;
300 for(n=0x7F000;n<0x80000;n++) {
301 memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
308 static u_int get_page(u_int vaddr)
310 u_int page=(vaddr^0x80000000)>>12;
312 if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
314 if(page>2048) page=2048+(page&2047);
318 static u_int get_vpage(u_int vaddr)
320 u_int vpage=(vaddr^0x80000000)>>12;
322 if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
324 if(vpage>2048) vpage=2048+(vpage&2047);
328 // Get address from virtual address
329 // This is called from the recompiled JR/JALR instructions
330 void *get_addr(u_int vaddr)
332 u_int page=get_page(vaddr);
333 u_int vpage=get_vpage(vaddr);
334 struct ll_entry *head;
335 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
338 if(head->vaddr==vaddr&&head->reg32==0) {
339 //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
340 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
343 ht_bin[1]=(int)head->addr;
349 head=jump_dirty[vpage];
351 if(head->vaddr==vaddr&&head->reg32==0) {
352 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
353 // Don't restore blocks which are about to expire from the cache
354 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
355 if(verify_dirty(head->addr)) {
356 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
357 invalid_code[vaddr>>12]=0;
358 memory_map[vaddr>>12]|=0x40000000;
361 if(tlb_LUT_r[vaddr>>12]) {
362 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
363 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
366 restore_candidate[vpage>>3]|=1<<(vpage&7);
368 else restore_candidate[page>>3]|=1<<(page&7);
369 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
370 if(ht_bin[0]==vaddr) {
371 ht_bin[1]=(int)head->addr; // Replace existing entry
377 ht_bin[1]=(int)head->addr;
385 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
386 int r=new_recompile_block(vaddr);
387 if(r==0) return get_addr(vaddr);
388 // Execute in unmapped page, generate pagefault execption
390 Cause=(vaddr<<31)|0x8;
391 EPC=(vaddr&1)?vaddr-5:vaddr;
393 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
394 EntryHi=BadVAddr&0xFFFFE000;
395 return get_addr_ht(0x80000000);
397 // Look up address in hash table first
398 void *get_addr_ht(u_int vaddr)
400 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
401 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
402 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
403 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
404 return get_addr(vaddr);
407 void *get_addr_32(u_int vaddr,u_int flags)
410 return get_addr(vaddr);
412 //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
413 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
414 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
415 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
416 u_int page=get_page(vaddr);
417 u_int vpage=get_vpage(vaddr);
418 struct ll_entry *head;
421 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
422 //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
424 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
426 ht_bin[1]=(int)head->addr;
428 }else if(ht_bin[2]==-1) {
429 ht_bin[3]=(int)head->addr;
432 //ht_bin[3]=ht_bin[1];
433 //ht_bin[2]=ht_bin[0];
434 //ht_bin[1]=(int)head->addr;
441 head=jump_dirty[vpage];
443 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
444 //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
445 // Don't restore blocks which are about to expire from the cache
446 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
447 if(verify_dirty(head->addr)) {
448 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
449 invalid_code[vaddr>>12]=0;
450 memory_map[vaddr>>12]|=0x40000000;
453 if(tlb_LUT_r[vaddr>>12]) {
454 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
455 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
458 restore_candidate[vpage>>3]|=1<<(vpage&7);
460 else restore_candidate[page>>3]|=1<<(page&7);
462 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
464 ht_bin[1]=(int)head->addr;
466 }else if(ht_bin[2]==-1) {
467 ht_bin[3]=(int)head->addr;
470 //ht_bin[3]=ht_bin[1];
471 //ht_bin[2]=ht_bin[0];
472 //ht_bin[1]=(int)head->addr;
480 //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
481 int r=new_recompile_block(vaddr);
482 if(r==0) return get_addr(vaddr);
483 // Execute in unmapped page, generate pagefault execption
485 Cause=(vaddr<<31)|0x8;
486 EPC=(vaddr&1)?vaddr-5:vaddr;
488 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
489 EntryHi=BadVAddr&0xFFFFE000;
490 return get_addr_ht(0x80000000);
493 void clear_all_regs(signed char regmap[])
496 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
499 signed char get_reg(signed char regmap[],int r)
502 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map[hr]==r) return hr;
506 // Find a register that is available for two consecutive cycles
507 signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
510 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map1[hr]==r&®map2[hr]==r) return hr;
514 int count_free_regs(signed char regmap[])
518 for(hr=0;hr<HOST_REGS;hr++)
520 if(hr!=EXCLUDE_REG) {
521 if(regmap[hr]<0) count++;
527 void dirty_reg(struct regstat *cur,signed char reg)
531 for (hr=0;hr<HOST_REGS;hr++) {
532 if((cur->regmap[hr]&63)==reg) {
538 // If we dirty the lower half of a 64 bit register which is now being
539 // sign-extended, we need to dump the upper half.
540 // Note: Do this only after completion of the instruction, because
541 // some instructions may need to read the full 64-bit value even if
542 // overwriting it (eg SLTI, DSRA32).
543 static void flush_dirty_uppers(struct regstat *cur)
546 for (hr=0;hr<HOST_REGS;hr++) {
547 if((cur->dirty>>hr)&1) {
550 if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
555 void set_const(struct regstat *cur,signed char reg,uint64_t value)
559 for (hr=0;hr<HOST_REGS;hr++) {
560 if(cur->regmap[hr]==reg) {
562 cur->constmap[hr]=value;
564 else if((cur->regmap[hr]^64)==reg) {
566 cur->constmap[hr]=value>>32;
571 void clear_const(struct regstat *cur,signed char reg)
575 for (hr=0;hr<HOST_REGS;hr++) {
576 if((cur->regmap[hr]&63)==reg) {
577 cur->isconst&=~(1<<hr);
582 int is_const(struct regstat *cur,signed char reg)
586 for (hr=0;hr<HOST_REGS;hr++) {
587 if((cur->regmap[hr]&63)==reg) {
588 return (cur->isconst>>hr)&1;
593 uint64_t get_const(struct regstat *cur,signed char reg)
597 for (hr=0;hr<HOST_REGS;hr++) {
598 if(cur->regmap[hr]==reg) {
599 return cur->constmap[hr];
602 printf("Unknown constant in r%d\n",reg);
606 // Least soon needed registers
607 // Look at the next ten instructions and see which registers
608 // will be used. Try not to reallocate these.
609 void lsn(u_char hsn[], int i, int *preferred_reg)
619 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
621 // Don't go past an unconditonal jump
628 if(rs1[i+j]) hsn[rs1[i+j]]=j;
629 if(rs2[i+j]) hsn[rs2[i+j]]=j;
630 if(rt1[i+j]) hsn[rt1[i+j]]=j;
631 if(rt2[i+j]) hsn[rt2[i+j]]=j;
632 if(itype[i+j]==STORE || itype[i+j]==STORELR) {
633 // Stores can allocate zero
637 // On some architectures stores need invc_ptr
638 #if defined(HOST_IMM8)
639 if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
643 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
651 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
653 // Follow first branch
654 int t=(ba[i+b]-start)>>2;
655 j=7-b;if(t+j>=slen) j=slen-t-1;
658 if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
659 if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
660 //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
661 //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
664 // TODO: preferred register based on backward branch
666 // Delay slot should preferably not overwrite branch conditions or cycle count
667 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
668 if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
669 if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
675 // Coprocessor load/store needs FTEMP, even if not declared
676 if(itype[i]==C1LS||itype[i]==C2LS) {
679 // Load L/R also uses FTEMP as a temporary register
680 if(itype[i]==LOADLR) {
683 // Also 64-bit SDL/SDR
684 if(opcode[i]==0x2c||opcode[i]==0x2d) {
687 // Don't remove the TLB registers either
688 if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
691 // Don't remove the miniht registers
692 if(itype[i]==UJUMP||itype[i]==RJUMP)
699 // We only want to allocate registers if we're going to use them again soon
700 int needed_again(int r, int i)
706 u_char hsn[MAXREG+1];
709 memset(hsn,10,sizeof(hsn));
710 lsn(hsn,i,&preferred_reg);
712 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
714 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
715 return 0; // Don't need any registers if exiting the block
723 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
725 // Don't go past an unconditonal jump
729 if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||((source[i+j]&0xfc00003f)==0x0d))
736 if(rs1[i+j]==r) rn=j;
737 if(rs2[i+j]==r) rn=j;
738 if((unneeded_reg[i+j]>>r)&1) rn=10;
739 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
747 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
749 // Follow first branch
751 int t=(ba[i+b]-start)>>2;
752 j=7-b;if(t+j>=slen) j=slen-t-1;
755 if(!((unneeded_reg[t+j]>>r)&1)) {
756 if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
757 if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
763 for(hr=0;hr<HOST_REGS;hr++) {
764 if(hr!=EXCLUDE_REG) {
765 if(rn<hsn[hr]) return 1;
771 // Try to match register allocations at the end of a loop with those
773 int loop_reg(int i, int r, int hr)
782 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
784 // Don't go past an unconditonal jump
791 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
796 if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
797 if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
798 if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
800 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
802 int t=(ba[i+k]-start)>>2;
803 int reg=get_reg(regs[t].regmap_entry,r);
804 if(reg>=0) return reg;
805 //reg=get_reg(regs[t+1].regmap_entry,r);
806 //if(reg>=0) return reg;
814 // Allocate every register, preserving source/target regs
815 void alloc_all(struct regstat *cur,int i)
819 for(hr=0;hr<HOST_REGS;hr++) {
820 if(hr!=EXCLUDE_REG) {
821 if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
822 ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
825 cur->dirty&=~(1<<hr);
828 if((cur->regmap[hr]&63)==0)
831 cur->dirty&=~(1<<hr);
838 void div64(int64_t dividend,int64_t divisor)
842 //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
843 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
845 void divu64(uint64_t dividend,uint64_t divisor)
849 //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
850 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
853 void mult64(uint64_t m1,uint64_t m2)
855 unsigned long long int op1, op2, op3, op4;
856 unsigned long long int result1, result2, result3, result4;
857 unsigned long long int temp1, temp2, temp3, temp4;
873 op1 = op2 & 0xFFFFFFFF;
874 op2 = (op2 >> 32) & 0xFFFFFFFF;
875 op3 = op4 & 0xFFFFFFFF;
876 op4 = (op4 >> 32) & 0xFFFFFFFF;
879 temp2 = (temp1 >> 32) + op1 * op4;
881 temp4 = (temp3 >> 32) + op2 * op4;
883 result1 = temp1 & 0xFFFFFFFF;
884 result2 = temp2 + (temp3 & 0xFFFFFFFF);
885 result3 = (result2 >> 32) + temp4;
886 result4 = (result3 >> 32);
888 lo = result1 | (result2 << 32);
889 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
898 void multu64(uint64_t m1,uint64_t m2)
900 unsigned long long int op1, op2, op3, op4;
901 unsigned long long int result1, result2, result3, result4;
902 unsigned long long int temp1, temp2, temp3, temp4;
904 op1 = m1 & 0xFFFFFFFF;
905 op2 = (m1 >> 32) & 0xFFFFFFFF;
906 op3 = m2 & 0xFFFFFFFF;
907 op4 = (m2 >> 32) & 0xFFFFFFFF;
910 temp2 = (temp1 >> 32) + op1 * op4;
912 temp4 = (temp3 >> 32) + op2 * op4;
914 result1 = temp1 & 0xFFFFFFFF;
915 result2 = temp2 + (temp3 & 0xFFFFFFFF);
916 result3 = (result2 >> 32) + temp4;
917 result4 = (result3 >> 32);
919 lo = result1 | (result2 << 32);
920 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
922 //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
923 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
926 uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
934 else original=loaded;
937 uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
940 original>>=64-(bits^56);
941 original<<=64-(bits^56);
945 else original=loaded;
950 #include "assem_x86.c"
953 #include "assem_x64.c"
956 #include "assem_arm.c"
959 // Add virtual address mapping to linked list
960 void ll_add(struct ll_entry **head,int vaddr,void *addr)
962 struct ll_entry *new_entry;
963 new_entry=malloc(sizeof(struct ll_entry));
964 assert(new_entry!=NULL);
965 new_entry->vaddr=vaddr;
967 new_entry->addr=addr;
968 new_entry->next=*head;
972 // Add virtual address mapping for 32-bit compiled block
973 void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
975 ll_add(head,vaddr,addr);
977 (*head)->reg32=reg32;
981 // Check if an address is already compiled
982 // but don't return addresses which are about to expire from the cache
983 void *check_addr(u_int vaddr)
985 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
986 if(ht_bin[0]==vaddr) {
987 if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
988 if(isclean(ht_bin[1])) return (void *)ht_bin[1];
990 if(ht_bin[2]==vaddr) {
991 if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
992 if(isclean(ht_bin[3])) return (void *)ht_bin[3];
994 u_int page=get_page(vaddr);
995 struct ll_entry *head;
998 if(head->vaddr==vaddr&&head->reg32==0) {
999 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1000 // Update existing entry with current address
1001 if(ht_bin[0]==vaddr) {
1002 ht_bin[1]=(int)head->addr;
1005 if(ht_bin[2]==vaddr) {
1006 ht_bin[3]=(int)head->addr;
1009 // Insert into hash table with low priority.
1010 // Don't evict existing entries, as they are probably
1011 // addresses that are being accessed frequently.
1013 ht_bin[1]=(int)head->addr;
1015 }else if(ht_bin[2]==-1) {
1016 ht_bin[3]=(int)head->addr;
1027 void remove_hash(int vaddr)
1029 //printf("remove hash: %x\n",vaddr);
1030 int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1031 if(ht_bin[2]==vaddr) {
1032 ht_bin[2]=ht_bin[3]=-1;
1034 if(ht_bin[0]==vaddr) {
1035 ht_bin[0]=ht_bin[2];
1036 ht_bin[1]=ht_bin[3];
1037 ht_bin[2]=ht_bin[3]=-1;
1041 void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1043 struct ll_entry *next;
1045 if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1046 ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1048 inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1049 remove_hash((*head)->vaddr);
1056 head=&((*head)->next);
1061 // Remove all entries from linked list
1062 void ll_clear(struct ll_entry **head)
1064 struct ll_entry *cur;
1065 struct ll_entry *next;
1076 // Dereference the pointers and remove if it matches
1077 void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1080 int ptr=get_pointer(head->addr);
1081 inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1082 if(((ptr>>shift)==(addr>>shift)) ||
1083 (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1085 inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1086 kill_pointer(head->addr);
1092 // This is called when we write to a compiled block (see do_invstub)
1093 int invalidate_page(u_int page)
1096 struct ll_entry *head;
1097 struct ll_entry *next;
1101 inv_debug("INVALIDATE: %x\n",head->vaddr);
1102 remove_hash(head->vaddr);
1107 head=jump_out[page];
1110 inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
1111 kill_pointer(head->addr);
1119 void invalidate_block(u_int block)
1122 u_int page=get_page(block<<12);
1123 u_int vpage=get_vpage(block<<12);
1124 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1125 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1128 struct ll_entry *head;
1129 head=jump_dirty[vpage];
1130 //printf("page=%d vpage=%d\n",page,vpage);
1133 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1134 get_bounds((int)head->addr,&start,&end);
1135 //printf("start: %x end: %x\n",start,end);
1136 if(page<2048&&start>=0x80000000&&end<0x80800000) {
1137 if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1138 if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1139 if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1143 if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1144 if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1145 if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1146 if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1153 //printf("first=%d last=%d\n",first,last);
1154 modified=invalidate_page(page);
1155 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1156 assert(last<page+5);
1157 // Invalidate the adjacent pages if a block crosses a 4K boundary
1159 invalidate_page(first);
1162 for(first=page+1;first<last;first++) {
1163 invalidate_page(first);
1166 // Don't trap writes
1167 invalid_code[block]=1;
1169 // If there is a valid TLB entry for this page, remove write protect
1170 if(tlb_LUT_w[block]) {
1171 assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1172 // CHECK: Is this right?
1173 memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1174 u_int real_block=tlb_LUT_w[block]>>12;
1175 invalid_code[real_block]=1;
1176 if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1178 else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
1182 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1185 memset(mini_ht,-1,sizeof(mini_ht));
1188 void invalidate_addr(u_int addr)
1190 invalidate_block(addr>>12);
1192 void invalidate_all_pages()
1195 for(page=0;page<4096;page++)
1196 invalidate_page(page);
1197 for(page=0;page<1048576;page++)
1198 if(!invalid_code[page]) {
1199 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1200 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1203 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1206 memset(mini_ht,-1,sizeof(mini_ht));
1210 for(page=0;page<0x100000;page++) {
1211 if(tlb_LUT_r[page]) {
1212 memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1213 if(!tlb_LUT_w[page]||!invalid_code[page])
1214 memory_map[page]|=0x40000000; // Write protect
1216 else memory_map[page]=-1;
1217 if(page==0x80000) page=0xC0000;
1223 // Add an entry to jump_out after making a link
1224 void add_link(u_int vaddr,void *src)
1226 u_int page=get_page(vaddr);
1227 inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1228 ll_add(jump_out+page,vaddr,src);
1229 //int ptr=get_pointer(src);
1230 //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1233 // If a code block was found to be unmodified (bit was set in
1234 // restore_candidate) and it remains unmodified (bit is clear
1235 // in invalid_code) then move the entries for that 4K page from
1236 // the dirty list to the clean list.
1237 void clean_blocks(u_int page)
1239 struct ll_entry *head;
1240 inv_debug("INV: clean_blocks page=%d\n",page);
1241 head=jump_dirty[page];
1243 if(!invalid_code[head->vaddr>>12]) {
1244 // Don't restore blocks which are about to expire from the cache
1245 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1247 if(verify_dirty((int)head->addr)) {
1248 //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1251 get_bounds((int)head->addr,&start,&end);
1252 if(start-(u_int)rdram<0x800000) {
1253 for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1254 inv|=invalid_code[i];
1257 if((signed int)head->vaddr>=(signed int)0xC0000000) {
1258 u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1259 //printf("addr=%x start=%x end=%x\n",addr,start,end);
1260 if(addr<start||addr>=end) inv=1;
1262 else if((signed int)head->vaddr>=(signed int)0x80800000) {
1266 void * clean_addr=(void *)get_clean_addr((int)head->addr);
1267 if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1270 if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
1272 inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1273 //printf("page=%x, addr=%x\n",page,head->vaddr);
1274 //assert(head->vaddr>>12==(page|0x80000));
1275 ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1276 int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1278 if(ht_bin[0]==head->vaddr) {
1279 ht_bin[1]=(int)clean_addr; // Replace existing entry
1281 if(ht_bin[2]==head->vaddr) {
1282 ht_bin[3]=(int)clean_addr; // Replace existing entry
1295 void mov_alloc(struct regstat *current,int i)
1297 // Note: Don't need to actually alloc the source registers
1298 if((~current->is32>>rs1[i])&1) {
1299 //alloc_reg64(current,i,rs1[i]);
1300 alloc_reg64(current,i,rt1[i]);
1301 current->is32&=~(1LL<<rt1[i]);
1303 //alloc_reg(current,i,rs1[i]);
1304 alloc_reg(current,i,rt1[i]);
1305 current->is32|=(1LL<<rt1[i]);
1307 clear_const(current,rs1[i]);
1308 clear_const(current,rt1[i]);
1309 dirty_reg(current,rt1[i]);
1312 void shiftimm_alloc(struct regstat *current,int i)
1314 clear_const(current,rs1[i]);
1315 clear_const(current,rt1[i]);
1316 if(opcode2[i]<=0x3) // SLL/SRL/SRA
1319 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1321 alloc_reg(current,i,rt1[i]);
1322 current->is32|=1LL<<rt1[i];
1323 dirty_reg(current,rt1[i]);
1326 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1329 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1330 alloc_reg64(current,i,rt1[i]);
1331 current->is32&=~(1LL<<rt1[i]);
1332 dirty_reg(current,rt1[i]);
1335 if(opcode2[i]==0x3c) // DSLL32
1338 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1339 alloc_reg64(current,i,rt1[i]);
1340 current->is32&=~(1LL<<rt1[i]);
1341 dirty_reg(current,rt1[i]);
1344 if(opcode2[i]==0x3e) // DSRL32
1347 alloc_reg64(current,i,rs1[i]);
1349 alloc_reg64(current,i,rt1[i]);
1350 current->is32&=~(1LL<<rt1[i]);
1352 alloc_reg(current,i,rt1[i]);
1353 current->is32|=1LL<<rt1[i];
1355 dirty_reg(current,rt1[i]);
1358 if(opcode2[i]==0x3f) // DSRA32
1361 alloc_reg64(current,i,rs1[i]);
1362 alloc_reg(current,i,rt1[i]);
1363 current->is32|=1LL<<rt1[i];
1364 dirty_reg(current,rt1[i]);
1369 void shift_alloc(struct regstat *current,int i)
1372 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1374 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1375 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1376 alloc_reg(current,i,rt1[i]);
1377 if(rt1[i]==rs2[i]) alloc_reg_temp(current,i,-1);
1378 current->is32|=1LL<<rt1[i];
1379 } else { // DSLLV/DSRLV/DSRAV
1380 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1381 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1382 alloc_reg64(current,i,rt1[i]);
1383 current->is32&=~(1LL<<rt1[i]);
1384 if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1385 alloc_reg_temp(current,i,-1);
1387 clear_const(current,rs1[i]);
1388 clear_const(current,rs2[i]);
1389 clear_const(current,rt1[i]);
1390 dirty_reg(current,rt1[i]);
1394 void alu_alloc(struct regstat *current,int i)
1396 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1398 if(rs1[i]&&rs2[i]) {
1399 alloc_reg(current,i,rs1[i]);
1400 alloc_reg(current,i,rs2[i]);
1403 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1404 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1406 alloc_reg(current,i,rt1[i]);
1408 current->is32|=1LL<<rt1[i];
1410 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1412 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1414 alloc_reg64(current,i,rs1[i]);
1415 alloc_reg64(current,i,rs2[i]);
1416 alloc_reg(current,i,rt1[i]);
1418 alloc_reg(current,i,rs1[i]);
1419 alloc_reg(current,i,rs2[i]);
1420 alloc_reg(current,i,rt1[i]);
1423 current->is32|=1LL<<rt1[i];
1425 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1427 if(rs1[i]&&rs2[i]) {
1428 alloc_reg(current,i,rs1[i]);
1429 alloc_reg(current,i,rs2[i]);
1433 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1434 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1436 alloc_reg(current,i,rt1[i]);
1437 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1439 if(!((current->uu>>rt1[i])&1)) {
1440 alloc_reg64(current,i,rt1[i]);
1442 if(get_reg(current->regmap,rt1[i]|64)>=0) {
1443 if(rs1[i]&&rs2[i]) {
1444 alloc_reg64(current,i,rs1[i]);
1445 alloc_reg64(current,i,rs2[i]);
1449 // Is is really worth it to keep 64-bit values in registers?
1451 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1452 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1456 current->is32&=~(1LL<<rt1[i]);
1458 current->is32|=1LL<<rt1[i];
1462 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1464 if(rs1[i]&&rs2[i]) {
1465 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1466 alloc_reg64(current,i,rs1[i]);
1467 alloc_reg64(current,i,rs2[i]);
1468 alloc_reg64(current,i,rt1[i]);
1470 alloc_reg(current,i,rs1[i]);
1471 alloc_reg(current,i,rs2[i]);
1472 alloc_reg(current,i,rt1[i]);
1476 alloc_reg(current,i,rt1[i]);
1477 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1478 // DADD used as move, or zeroing
1479 // If we have a 64-bit source, then make the target 64 bits too
1480 if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1481 if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1482 alloc_reg64(current,i,rt1[i]);
1483 } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1484 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1485 alloc_reg64(current,i,rt1[i]);
1487 if(opcode2[i]>=0x2e&&rs2[i]) {
1488 // DSUB used as negation - 64-bit result
1489 // If we have a 32-bit register, extend it to 64 bits
1490 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1491 alloc_reg64(current,i,rt1[i]);
1495 if(rs1[i]&&rs2[i]) {
1496 current->is32&=~(1LL<<rt1[i]);
1498 current->is32&=~(1LL<<rt1[i]);
1499 if((current->is32>>rs1[i])&1)
1500 current->is32|=1LL<<rt1[i];
1502 current->is32&=~(1LL<<rt1[i]);
1503 if((current->is32>>rs2[i])&1)
1504 current->is32|=1LL<<rt1[i];
1506 current->is32|=1LL<<rt1[i];
1510 clear_const(current,rs1[i]);
1511 clear_const(current,rs2[i]);
1512 clear_const(current,rt1[i]);
1513 dirty_reg(current,rt1[i]);
1516 void imm16_alloc(struct regstat *current,int i)
1518 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1520 if(rt1[i]) alloc_reg(current,i,rt1[i]);
1521 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1522 current->is32&=~(1LL<<rt1[i]);
1523 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1524 // TODO: Could preserve the 32-bit flag if the immediate is zero
1525 alloc_reg64(current,i,rt1[i]);
1526 alloc_reg64(current,i,rs1[i]);
1528 clear_const(current,rs1[i]);
1529 clear_const(current,rt1[i]);
1531 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1532 if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1533 current->is32|=1LL<<rt1[i];
1534 clear_const(current,rs1[i]);
1535 clear_const(current,rt1[i]);
1537 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1538 if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1539 if(rs1[i]!=rt1[i]) {
1540 if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1541 alloc_reg64(current,i,rt1[i]);
1542 current->is32&=~(1LL<<rt1[i]);
1545 else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1546 if(is_const(current,rs1[i])) {
1547 int v=get_const(current,rs1[i]);
1548 if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1549 if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1550 if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1552 else clear_const(current,rt1[i]);
1554 else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1555 if(is_const(current,rs1[i])) {
1556 int v=get_const(current,rs1[i]);
1557 set_const(current,rt1[i],v+imm[i]);
1559 else clear_const(current,rt1[i]);
1560 current->is32|=1LL<<rt1[i];
1563 set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1564 current->is32|=1LL<<rt1[i];
1566 dirty_reg(current,rt1[i]);
1569 void load_alloc(struct regstat *current,int i)
1571 clear_const(current,rt1[i]);
1572 //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1573 if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1574 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1576 alloc_reg(current,i,rt1[i]);
1577 if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1579 current->is32&=~(1LL<<rt1[i]);
1580 alloc_reg64(current,i,rt1[i]);
1582 else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1584 current->is32&=~(1LL<<rt1[i]);
1585 alloc_reg64(current,i,rt1[i]);
1586 alloc_all(current,i);
1587 alloc_reg64(current,i,FTEMP);
1589 else current->is32|=1LL<<rt1[i];
1590 dirty_reg(current,rt1[i]);
1591 // If using TLB, need a register for pointer to the mapping table
1592 if(using_tlb) alloc_reg(current,i,TLREG);
1593 // LWL/LWR need a temporary register for the old value
1594 if(opcode[i]==0x22||opcode[i]==0x26)
1596 alloc_reg(current,i,FTEMP);
1597 alloc_reg_temp(current,i,-1);
1602 // Load to r0 (dummy load)
1603 // but we still need a register to calculate the address
1604 alloc_reg_temp(current,i,-1);
1608 void store_alloc(struct regstat *current,int i)
1610 clear_const(current,rs2[i]);
1611 if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1612 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1613 alloc_reg(current,i,rs2[i]);
1614 if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1615 alloc_reg64(current,i,rs2[i]);
1616 if(rs2[i]) alloc_reg(current,i,FTEMP);
1618 // If using TLB, need a register for pointer to the mapping table
1619 if(using_tlb) alloc_reg(current,i,TLREG);
1620 #if defined(HOST_IMM8)
1621 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1622 else alloc_reg(current,i,INVCP);
1624 if(opcode[i]==0x2c||opcode[i]==0x2d) { // 64-bit SDL/SDR
1625 alloc_reg(current,i,FTEMP);
1627 // We need a temporary register for address generation
1628 alloc_reg_temp(current,i,-1);
1631 void c1ls_alloc(struct regstat *current,int i)
1633 //clear_const(current,rs1[i]); // FIXME
1634 clear_const(current,rt1[i]);
1635 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1636 alloc_reg(current,i,CSREG); // Status
1637 alloc_reg(current,i,FTEMP);
1638 if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1639 alloc_reg64(current,i,FTEMP);
1641 // If using TLB, need a register for pointer to the mapping table
1642 if(using_tlb) alloc_reg(current,i,TLREG);
1643 #if defined(HOST_IMM8)
1644 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1645 else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1646 alloc_reg(current,i,INVCP);
1648 // We need a temporary register for address generation
1649 alloc_reg_temp(current,i,-1);
1652 void c2ls_alloc(struct regstat *current,int i)
1654 clear_const(current,rt1[i]);
1655 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1656 alloc_reg(current,i,FTEMP);
1657 // If using TLB, need a register for pointer to the mapping table
1658 if(using_tlb) alloc_reg(current,i,TLREG);
1659 #if defined(HOST_IMM8)
1660 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1661 else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1662 alloc_reg(current,i,INVCP);
1664 // We need a temporary register for address generation
1665 alloc_reg_temp(current,i,-1);
1668 #ifndef multdiv_alloc
1669 void multdiv_alloc(struct regstat *current,int i)
1676 // case 0x1D: DMULTU
1679 clear_const(current,rs1[i]);
1680 clear_const(current,rs2[i]);
1683 if((opcode2[i]&4)==0) // 32-bit
1685 current->u&=~(1LL<<HIREG);
1686 current->u&=~(1LL<<LOREG);
1687 alloc_reg(current,i,HIREG);
1688 alloc_reg(current,i,LOREG);
1689 alloc_reg(current,i,rs1[i]);
1690 alloc_reg(current,i,rs2[i]);
1691 current->is32|=1LL<<HIREG;
1692 current->is32|=1LL<<LOREG;
1693 dirty_reg(current,HIREG);
1694 dirty_reg(current,LOREG);
1698 current->u&=~(1LL<<HIREG);
1699 current->u&=~(1LL<<LOREG);
1700 current->uu&=~(1LL<<HIREG);
1701 current->uu&=~(1LL<<LOREG);
1702 alloc_reg64(current,i,HIREG);
1703 //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1704 alloc_reg64(current,i,rs1[i]);
1705 alloc_reg64(current,i,rs2[i]);
1706 alloc_all(current,i);
1707 current->is32&=~(1LL<<HIREG);
1708 current->is32&=~(1LL<<LOREG);
1709 dirty_reg(current,HIREG);
1710 dirty_reg(current,LOREG);
1715 // Multiply by zero is zero.
1716 // MIPS does not have a divide by zero exception.
1717 // The result is undefined, we return zero.
1718 alloc_reg(current,i,HIREG);
1719 alloc_reg(current,i,LOREG);
1720 current->is32|=1LL<<HIREG;
1721 current->is32|=1LL<<LOREG;
1722 dirty_reg(current,HIREG);
1723 dirty_reg(current,LOREG);
1728 void cop0_alloc(struct regstat *current,int i)
1730 if(opcode2[i]==0) // MFC0
1733 clear_const(current,rt1[i]);
1734 alloc_all(current,i);
1735 alloc_reg(current,i,rt1[i]);
1736 current->is32|=1LL<<rt1[i];
1737 dirty_reg(current,rt1[i]);
1740 else if(opcode2[i]==4) // MTC0
1743 clear_const(current,rs1[i]);
1744 alloc_reg(current,i,rs1[i]);
1745 alloc_all(current,i);
1748 alloc_all(current,i); // FIXME: Keep r0
1750 alloc_reg(current,i,0);
1755 // TLBR/TLBWI/TLBWR/TLBP/ERET
1756 assert(opcode2[i]==0x10);
1757 alloc_all(current,i);
1761 void cop1_alloc(struct regstat *current,int i)
1763 alloc_reg(current,i,CSREG); // Load status
1764 if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1767 clear_const(current,rt1[i]);
1769 alloc_reg64(current,i,rt1[i]); // DMFC1
1770 current->is32&=~(1LL<<rt1[i]);
1772 alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1773 current->is32|=1LL<<rt1[i];
1775 dirty_reg(current,rt1[i]);
1776 alloc_reg_temp(current,i,-1);
1778 else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1781 clear_const(current,rs1[i]);
1783 alloc_reg64(current,i,rs1[i]); // DMTC1
1785 alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1786 alloc_reg_temp(current,i,-1);
1790 alloc_reg(current,i,0);
1791 alloc_reg_temp(current,i,-1);
1795 void fconv_alloc(struct regstat *current,int i)
1797 alloc_reg(current,i,CSREG); // Load status
1798 alloc_reg_temp(current,i,-1);
1800 void float_alloc(struct regstat *current,int i)
1802 alloc_reg(current,i,CSREG); // Load status
1803 alloc_reg_temp(current,i,-1);
1805 void c2op_alloc(struct regstat *current,int i)
1807 alloc_reg_temp(current,i,-1);
1809 void fcomp_alloc(struct regstat *current,int i)
1811 alloc_reg(current,i,CSREG); // Load status
1812 alloc_reg(current,i,FSREG); // Load flags
1813 dirty_reg(current,FSREG); // Flag will be modified
1814 alloc_reg_temp(current,i,-1);
1817 void syscall_alloc(struct regstat *current,int i)
1819 alloc_cc(current,i);
1820 dirty_reg(current,CCREG);
1821 alloc_all(current,i);
1825 void delayslot_alloc(struct regstat *current,int i)
1836 assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1);
1837 printf("Disabled speculative precompilation\n");
1841 imm16_alloc(current,i);
1845 load_alloc(current,i);
1849 store_alloc(current,i);
1852 alu_alloc(current,i);
1855 shift_alloc(current,i);
1858 multdiv_alloc(current,i);
1861 shiftimm_alloc(current,i);
1864 mov_alloc(current,i);
1867 cop0_alloc(current,i);
1871 cop1_alloc(current,i);
1874 c1ls_alloc(current,i);
1877 c2ls_alloc(current,i);
1880 fconv_alloc(current,i);
1883 float_alloc(current,i);
1886 fcomp_alloc(current,i);
1889 c2op_alloc(current,i);
1894 // Special case where a branch and delay slot span two pages in virtual memory
1895 static void pagespan_alloc(struct regstat *current,int i)
1898 current->wasconst=0;
1900 alloc_all(current,i);
1901 alloc_cc(current,i);
1902 dirty_reg(current,CCREG);
1903 if(opcode[i]==3) // JAL
1905 alloc_reg(current,i,31);
1906 dirty_reg(current,31);
1908 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
1910 alloc_reg(current,i,rs1[i]);
1912 alloc_reg(current,i,31);
1913 dirty_reg(current,31);
1916 if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
1918 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1919 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1920 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1922 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1923 if(rs2[i]) alloc_reg64(current,i,rs2[i]);
1927 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
1929 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1930 if(!((current->is32>>rs1[i])&1))
1932 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1936 if(opcode[i]==0x11) // BC1
1938 alloc_reg(current,i,FSREG);
1939 alloc_reg(current,i,CSREG);
1944 add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
1946 stubs[stubcount][0]=type;
1947 stubs[stubcount][1]=addr;
1948 stubs[stubcount][2]=retaddr;
1949 stubs[stubcount][3]=a;
1950 stubs[stubcount][4]=b;
1951 stubs[stubcount][5]=c;
1952 stubs[stubcount][6]=d;
1953 stubs[stubcount][7]=e;
1957 // Write out a single register
1958 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
1961 for(hr=0;hr<HOST_REGS;hr++) {
1962 if(hr!=EXCLUDE_REG) {
1963 if((regmap[hr]&63)==r) {
1966 emit_storereg(r,hr);
1968 if((is32>>regmap[hr])&1) {
1969 emit_sarimm(hr,31,hr);
1970 emit_storereg(r|64,hr);
1974 emit_storereg(r|64,hr);
1984 //if(!tracedebug) return 0;
1987 for(i=0;i<2097152;i++) {
1988 unsigned int temp=sum;
1991 sum^=((u_int *)rdram)[i];
2000 sum^=((u_int *)reg)[i];
2008 printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2010 #ifndef DISABLE_COP1
2013 printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2023 void memdebug(int i)
2025 //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2026 //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2029 //if(Count>=-2084597794) {
2030 if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2032 printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2033 //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2034 //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2037 printf("TRACE: %x\n",(&i)[-1]);
2041 printf("TRACE: %x \n",(&j)[10]);
2042 printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2046 //printf("TRACE: %x\n",(&i)[-1]);
2049 void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2051 printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2054 void alu_assemble(int i,struct regstat *i_regs)
2056 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2058 signed char s1,s2,t;
2059 t=get_reg(i_regs->regmap,rt1[i]);
2061 s1=get_reg(i_regs->regmap,rs1[i]);
2062 s2=get_reg(i_regs->regmap,rs2[i]);
2063 if(rs1[i]&&rs2[i]) {
2066 if(opcode2[i]&2) emit_sub(s1,s2,t);
2067 else emit_add(s1,s2,t);
2070 if(s1>=0) emit_mov(s1,t);
2071 else emit_loadreg(rs1[i],t);
2075 if(opcode2[i]&2) emit_neg(s2,t);
2076 else emit_mov(s2,t);
2079 emit_loadreg(rs2[i],t);
2080 if(opcode2[i]&2) emit_neg(t,t);
2083 else emit_zeroreg(t);
2087 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2089 signed char s1l,s2l,s1h,s2h,tl,th;
2090 tl=get_reg(i_regs->regmap,rt1[i]);
2091 th=get_reg(i_regs->regmap,rt1[i]|64);
2093 s1l=get_reg(i_regs->regmap,rs1[i]);
2094 s2l=get_reg(i_regs->regmap,rs2[i]);
2095 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2096 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2097 if(rs1[i]&&rs2[i]) {
2100 if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2101 else emit_adds(s1l,s2l,tl);
2103 #ifdef INVERTED_CARRY
2104 if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2106 if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2108 else emit_add(s1h,s2h,th);
2112 if(s1l>=0) emit_mov(s1l,tl);
2113 else emit_loadreg(rs1[i],tl);
2115 if(s1h>=0) emit_mov(s1h,th);
2116 else emit_loadreg(rs1[i]|64,th);
2121 if(opcode2[i]&2) emit_negs(s2l,tl);
2122 else emit_mov(s2l,tl);
2125 emit_loadreg(rs2[i],tl);
2126 if(opcode2[i]&2) emit_negs(tl,tl);
2129 #ifdef INVERTED_CARRY
2130 if(s2h>=0) emit_mov(s2h,th);
2131 else emit_loadreg(rs2[i]|64,th);
2133 emit_adcimm(-1,th); // x86 has inverted carry flag
2138 if(s2h>=0) emit_rscimm(s2h,0,th);
2140 emit_loadreg(rs2[i]|64,th);
2141 emit_rscimm(th,0,th);
2144 if(s2h>=0) emit_mov(s2h,th);
2145 else emit_loadreg(rs2[i]|64,th);
2152 if(th>=0) emit_zeroreg(th);
2157 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2159 signed char s1l,s1h,s2l,s2h,t;
2160 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2162 t=get_reg(i_regs->regmap,rt1[i]);
2165 s1l=get_reg(i_regs->regmap,rs1[i]);
2166 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2167 s2l=get_reg(i_regs->regmap,rs2[i]);
2168 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2169 if(rs2[i]==0) // rx<r0
2172 if(opcode2[i]==0x2a) // SLT
2173 emit_shrimm(s1h,31,t);
2174 else // SLTU (unsigned can not be less than zero)
2177 else if(rs1[i]==0) // r0<rx
2180 if(opcode2[i]==0x2a) // SLT
2181 emit_set_gz64_32(s2h,s2l,t);
2182 else // SLTU (set if not zero)
2183 emit_set_nz64_32(s2h,s2l,t);
2186 assert(s1l>=0);assert(s1h>=0);
2187 assert(s2l>=0);assert(s2h>=0);
2188 if(opcode2[i]==0x2a) // SLT
2189 emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2191 emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2195 t=get_reg(i_regs->regmap,rt1[i]);
2198 s1l=get_reg(i_regs->regmap,rs1[i]);
2199 s2l=get_reg(i_regs->regmap,rs2[i]);
2200 if(rs2[i]==0) // rx<r0
2203 if(opcode2[i]==0x2a) // SLT
2204 emit_shrimm(s1l,31,t);
2205 else // SLTU (unsigned can not be less than zero)
2208 else if(rs1[i]==0) // r0<rx
2211 if(opcode2[i]==0x2a) // SLT
2212 emit_set_gz32(s2l,t);
2213 else // SLTU (set if not zero)
2214 emit_set_nz32(s2l,t);
2217 assert(s1l>=0);assert(s2l>=0);
2218 if(opcode2[i]==0x2a) // SLT
2219 emit_set_if_less32(s1l,s2l,t);
2221 emit_set_if_carry32(s1l,s2l,t);
2227 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2229 signed char s1l,s1h,s2l,s2h,th,tl;
2230 tl=get_reg(i_regs->regmap,rt1[i]);
2231 th=get_reg(i_regs->regmap,rt1[i]|64);
2232 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2236 s1l=get_reg(i_regs->regmap,rs1[i]);
2237 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2238 s2l=get_reg(i_regs->regmap,rs2[i]);
2239 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2240 if(rs1[i]&&rs2[i]) {
2241 assert(s1l>=0);assert(s1h>=0);
2242 assert(s2l>=0);assert(s2h>=0);
2243 if(opcode2[i]==0x24) { // AND
2244 emit_and(s1l,s2l,tl);
2245 emit_and(s1h,s2h,th);
2247 if(opcode2[i]==0x25) { // OR
2248 emit_or(s1l,s2l,tl);
2249 emit_or(s1h,s2h,th);
2251 if(opcode2[i]==0x26) { // XOR
2252 emit_xor(s1l,s2l,tl);
2253 emit_xor(s1h,s2h,th);
2255 if(opcode2[i]==0x27) { // NOR
2256 emit_or(s1l,s2l,tl);
2257 emit_or(s1h,s2h,th);
2264 if(opcode2[i]==0x24) { // AND
2268 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2270 if(s1l>=0) emit_mov(s1l,tl);
2271 else emit_loadreg(rs1[i],tl);
2272 if(s1h>=0) emit_mov(s1h,th);
2273 else emit_loadreg(rs1[i]|64,th);
2277 if(s2l>=0) emit_mov(s2l,tl);
2278 else emit_loadreg(rs2[i],tl);
2279 if(s2h>=0) emit_mov(s2h,th);
2280 else emit_loadreg(rs2[i]|64,th);
2287 if(opcode2[i]==0x27) { // NOR
2289 if(s1l>=0) emit_not(s1l,tl);
2291 emit_loadreg(rs1[i],tl);
2294 if(s1h>=0) emit_not(s1h,th);
2296 emit_loadreg(rs1[i]|64,th);
2302 if(s2l>=0) emit_not(s2l,tl);
2304 emit_loadreg(rs2[i],tl);
2307 if(s2h>=0) emit_not(s2h,th);
2309 emit_loadreg(rs2[i]|64,th);
2325 s1l=get_reg(i_regs->regmap,rs1[i]);
2326 s2l=get_reg(i_regs->regmap,rs2[i]);
2327 if(rs1[i]&&rs2[i]) {
2330 if(opcode2[i]==0x24) { // AND
2331 emit_and(s1l,s2l,tl);
2333 if(opcode2[i]==0x25) { // OR
2334 emit_or(s1l,s2l,tl);
2336 if(opcode2[i]==0x26) { // XOR
2337 emit_xor(s1l,s2l,tl);
2339 if(opcode2[i]==0x27) { // NOR
2340 emit_or(s1l,s2l,tl);
2346 if(opcode2[i]==0x24) { // AND
2349 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2351 if(s1l>=0) emit_mov(s1l,tl);
2352 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2356 if(s2l>=0) emit_mov(s2l,tl);
2357 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2359 else emit_zeroreg(tl);
2361 if(opcode2[i]==0x27) { // NOR
2363 if(s1l>=0) emit_not(s1l,tl);
2365 emit_loadreg(rs1[i],tl);
2371 if(s2l>=0) emit_not(s2l,tl);
2373 emit_loadreg(rs2[i],tl);
2377 else emit_movimm(-1,tl);
2386 void imm16_assemble(int i,struct regstat *i_regs)
2388 if (opcode[i]==0x0f) { // LUI
2391 t=get_reg(i_regs->regmap,rt1[i]);
2394 if(!((i_regs->isconst>>t)&1))
2395 emit_movimm(imm[i]<<16,t);
2399 if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2402 t=get_reg(i_regs->regmap,rt1[i]);
2403 s=get_reg(i_regs->regmap,rs1[i]);
2408 if(!((i_regs->isconst>>t)&1)) {
2410 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2411 emit_addimm(t,imm[i],t);
2413 if(!((i_regs->wasconst>>s)&1))
2414 emit_addimm(s,imm[i],t);
2416 emit_movimm(constmap[i][s]+imm[i],t);
2422 if(!((i_regs->isconst>>t)&1))
2423 emit_movimm(imm[i],t);
2428 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2430 signed char sh,sl,th,tl;
2431 th=get_reg(i_regs->regmap,rt1[i]|64);
2432 tl=get_reg(i_regs->regmap,rt1[i]);
2433 sh=get_reg(i_regs->regmap,rs1[i]|64);
2434 sl=get_reg(i_regs->regmap,rs1[i]);
2440 emit_addimm64_32(sh,sl,imm[i],th,tl);
2443 emit_addimm(sl,imm[i],tl);
2446 emit_movimm(imm[i],tl);
2447 if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2452 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2454 //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2455 signed char sh,sl,t;
2456 t=get_reg(i_regs->regmap,rt1[i]);
2457 sh=get_reg(i_regs->regmap,rs1[i]|64);
2458 sl=get_reg(i_regs->regmap,rs1[i]);
2462 if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2463 if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2464 if(opcode[i]==0x0a) { // SLTI
2466 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2467 emit_slti32(t,imm[i],t);
2469 emit_slti32(sl,imm[i],t);
2474 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2475 emit_sltiu32(t,imm[i],t);
2477 emit_sltiu32(sl,imm[i],t);
2482 if(opcode[i]==0x0a) // SLTI
2483 emit_slti64_32(sh,sl,imm[i],t);
2485 emit_sltiu64_32(sh,sl,imm[i],t);
2488 // SLTI(U) with r0 is just stupid,
2489 // nonetheless examples can be found
2490 if(opcode[i]==0x0a) // SLTI
2491 if(0<imm[i]) emit_movimm(1,t);
2492 else emit_zeroreg(t);
2495 if(imm[i]) emit_movimm(1,t);
2496 else emit_zeroreg(t);
2502 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2504 signed char sh,sl,th,tl;
2505 th=get_reg(i_regs->regmap,rt1[i]|64);
2506 tl=get_reg(i_regs->regmap,rt1[i]);
2507 sh=get_reg(i_regs->regmap,rs1[i]|64);
2508 sl=get_reg(i_regs->regmap,rs1[i]);
2509 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2510 if(opcode[i]==0x0c) //ANDI
2514 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2515 emit_andimm(tl,imm[i],tl);
2517 if(!((i_regs->wasconst>>sl)&1))
2518 emit_andimm(sl,imm[i],tl);
2520 emit_movimm(constmap[i][sl]&imm[i],tl);
2525 if(th>=0) emit_zeroreg(th);
2531 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2535 emit_loadreg(rs1[i]|64,th);
2540 if(opcode[i]==0x0d) //ORI
2542 emit_orimm(tl,imm[i],tl);
2544 if(!((i_regs->wasconst>>sl)&1))
2545 emit_orimm(sl,imm[i],tl);
2547 emit_movimm(constmap[i][sl]|imm[i],tl);
2549 if(opcode[i]==0x0e) //XORI
2551 emit_xorimm(tl,imm[i],tl);
2553 if(!((i_regs->wasconst>>sl)&1))
2554 emit_xorimm(sl,imm[i],tl);
2556 emit_movimm(constmap[i][sl]^imm[i],tl);
2560 emit_movimm(imm[i],tl);
2561 if(th>=0) emit_zeroreg(th);
2569 void shiftimm_assemble(int i,struct regstat *i_regs)
2571 if(opcode2[i]<=0x3) // SLL/SRL/SRA
2575 t=get_reg(i_regs->regmap,rt1[i]);
2576 s=get_reg(i_regs->regmap,rs1[i]);
2585 if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2587 if(opcode2[i]==0) // SLL
2589 emit_shlimm(s<0?t:s,imm[i],t);
2591 if(opcode2[i]==2) // SRL
2593 emit_shrimm(s<0?t:s,imm[i],t);
2595 if(opcode2[i]==3) // SRA
2597 emit_sarimm(s<0?t:s,imm[i],t);
2601 if(s>=0 && s!=t) emit_mov(s,t);
2605 //emit_storereg(rt1[i],t); //DEBUG
2608 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2611 signed char sh,sl,th,tl;
2612 th=get_reg(i_regs->regmap,rt1[i]|64);
2613 tl=get_reg(i_regs->regmap,rt1[i]);
2614 sh=get_reg(i_regs->regmap,rs1[i]|64);
2615 sl=get_reg(i_regs->regmap,rs1[i]);
2620 if(th>=0) emit_zeroreg(th);
2627 if(opcode2[i]==0x38) // DSLL
2629 if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2630 emit_shlimm(sl,imm[i],tl);
2632 if(opcode2[i]==0x3a) // DSRL
2634 emit_shrdimm(sl,sh,imm[i],tl);
2635 if(th>=0) emit_shrimm(sh,imm[i],th);
2637 if(opcode2[i]==0x3b) // DSRA
2639 emit_shrdimm(sl,sh,imm[i],tl);
2640 if(th>=0) emit_sarimm(sh,imm[i],th);
2644 if(sl!=tl) emit_mov(sl,tl);
2645 if(th>=0&&sh!=th) emit_mov(sh,th);
2651 if(opcode2[i]==0x3c) // DSLL32
2654 signed char sl,tl,th;
2655 tl=get_reg(i_regs->regmap,rt1[i]);
2656 th=get_reg(i_regs->regmap,rt1[i]|64);
2657 sl=get_reg(i_regs->regmap,rs1[i]);
2666 emit_shlimm(th,imm[i]&31,th);
2671 if(opcode2[i]==0x3e) // DSRL32
2674 signed char sh,tl,th;
2675 tl=get_reg(i_regs->regmap,rt1[i]);
2676 th=get_reg(i_regs->regmap,rt1[i]|64);
2677 sh=get_reg(i_regs->regmap,rs1[i]|64);
2681 if(th>=0) emit_zeroreg(th);
2684 emit_shrimm(tl,imm[i]&31,tl);
2689 if(opcode2[i]==0x3f) // DSRA32
2693 tl=get_reg(i_regs->regmap,rt1[i]);
2694 sh=get_reg(i_regs->regmap,rs1[i]|64);
2700 emit_sarimm(tl,imm[i]&31,tl);
2707 #ifndef shift_assemble
2708 void shift_assemble(int i,struct regstat *i_regs)
2710 printf("Need shift_assemble for this architecture.\n");
2715 void load_assemble(int i,struct regstat *i_regs)
2717 int s,th,tl,addr,map=-1;
2722 th=get_reg(i_regs->regmap,rt1[i]|64);
2723 tl=get_reg(i_regs->regmap,rt1[i]);
2724 s=get_reg(i_regs->regmap,rs1[i]);
2726 for(hr=0;hr<HOST_REGS;hr++) {
2727 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2729 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2731 c=(i_regs->wasconst>>s)&1;
2732 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80800000;
2733 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2735 if(offset||s<0||c) addr=tl;
2737 //printf("load_assemble: c=%d\n",c);
2738 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2739 // FIXME: Even if the load is a NOP, we should check for pagefaults...
2744 if(th>=0) reglist&=~(1<<th);
2747 //#define R29_HACK 1
2749 // Strmnnrmn's speed hack
2750 if(rs1[i]!=29||start<0x80001000||start>=0x80800000)
2753 emit_cmpimm(addr,0x800000);
2755 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2756 // Hint to branch predictor that the branch is unlikely to be taken
2758 emit_jno_unlikely(0);
2766 if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2767 if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2768 map=get_reg(i_regs->regmap,TLREG);
2770 map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2771 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2773 if (opcode[i]==0x20) { // LB
2775 #ifdef HOST_IMM_ADDR32
2777 emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2781 //emit_xorimm(addr,3,tl);
2782 //gen_tlb_addr_r(tl,map);
2783 //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2785 #ifdef BIG_ENDIAN_MIPS
2786 if(!c) emit_xorimm(addr,3,tl);
2787 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2789 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2790 else if (tl!=addr) emit_mov(addr,tl);
2792 emit_movsbl_indexed_tlb(x,tl,map,tl);
2795 add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2798 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2800 if (opcode[i]==0x21) { // LH
2802 #ifdef HOST_IMM_ADDR32
2804 emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2809 #ifdef BIG_ENDIAN_MIPS
2810 if(!c) emit_xorimm(addr,2,tl);
2811 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2813 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2814 else if (tl!=addr) emit_mov(addr,tl);
2817 //emit_movswl_indexed_tlb(x,tl,map,tl);
2820 gen_tlb_addr_r(tl,map);
2821 emit_movswl_indexed(x,tl,tl);
2823 emit_movswl_indexed((int)rdram-0x80000000+x,tl,tl);
2826 add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2829 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2831 if (opcode[i]==0x23) { // LW
2833 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2834 #ifdef HOST_IMM_ADDR32
2836 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2839 emit_readword_indexed_tlb(0,addr,map,tl);
2841 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2844 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2846 if (opcode[i]==0x24) { // LBU
2848 #ifdef HOST_IMM_ADDR32
2850 emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
2854 //emit_xorimm(addr,3,tl);
2855 //gen_tlb_addr_r(tl,map);
2856 //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
2858 #ifdef BIG_ENDIAN_MIPS
2859 if(!c) emit_xorimm(addr,3,tl);
2860 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2862 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2863 else if (tl!=addr) emit_mov(addr,tl);
2865 emit_movzbl_indexed_tlb(x,tl,map,tl);
2868 add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2871 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2873 if (opcode[i]==0x25) { // LHU
2875 #ifdef HOST_IMM_ADDR32
2877 emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
2882 #ifdef BIG_ENDIAN_MIPS
2883 if(!c) emit_xorimm(addr,2,tl);
2884 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2886 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2887 else if (tl!=addr) emit_mov(addr,tl);
2890 //emit_movzwl_indexed_tlb(x,tl,map,tl);
2893 gen_tlb_addr_r(tl,map);
2894 emit_movzwl_indexed(x,tl,tl);
2896 emit_movzwl_indexed((int)rdram-0x80000000+x,tl,tl);
2898 add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2902 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2904 if (opcode[i]==0x27) { // LWU
2907 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2908 #ifdef HOST_IMM_ADDR32
2910 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2913 emit_readword_indexed_tlb(0,addr,map,tl);
2915 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2918 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2922 if (opcode[i]==0x37) { // LD
2924 //gen_tlb_addr_r(tl,map);
2925 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
2926 //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
2927 #ifdef HOST_IMM_ADDR32
2929 emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
2932 emit_readdword_indexed_tlb(0,addr,map,th,tl);
2934 add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2937 inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2939 //emit_storereg(rt1[i],tl); // DEBUG
2941 //if(opcode[i]==0x23)
2942 //if(opcode[i]==0x24)
2943 //if(opcode[i]==0x23||opcode[i]==0x24)
2944 /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
2948 emit_readword((int)&last_count,ECX);
2950 if(get_reg(i_regs->regmap,CCREG)<0)
2951 emit_loadreg(CCREG,HOST_CCREG);
2952 emit_add(HOST_CCREG,ECX,HOST_CCREG);
2953 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
2954 emit_writeword(HOST_CCREG,(int)&Count);
2957 if(get_reg(i_regs->regmap,CCREG)<0)
2958 emit_loadreg(CCREG,0);
2960 emit_mov(HOST_CCREG,0);
2962 emit_addimm(0,2*ccadj[i],0);
2963 emit_writeword(0,(int)&Count);
2965 emit_call((int)memdebug);
2967 restore_regs(0x100f);
2971 #ifndef loadlr_assemble
2972 void loadlr_assemble(int i,struct regstat *i_regs)
2974 printf("Need loadlr_assemble for this architecture.\n");
2979 void store_assemble(int i,struct regstat *i_regs)
2984 int jaddr=0,jaddr2,type;
2985 int memtarget=0,c=0;
2986 int agr=AGEN1+(i&1);
2988 th=get_reg(i_regs->regmap,rs2[i]|64);
2989 tl=get_reg(i_regs->regmap,rs2[i]);
2990 s=get_reg(i_regs->regmap,rs1[i]);
2991 temp=get_reg(i_regs->regmap,agr);
2992 if(temp<0) temp=get_reg(i_regs->regmap,-1);
2995 c=(i_regs->wasconst>>s)&1;
2996 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80800000;
2997 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3001 for(hr=0;hr<HOST_REGS;hr++) {
3002 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3004 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3005 if(offset||s<0||c) addr=temp;
3010 // Strmnnrmn's speed hack
3012 if(rs1[i]!=29||start<0x80001000||start>=0x80800000)
3014 emit_cmpimm(addr,0x800000);
3015 #ifdef DESTRUCTIVE_SHIFT
3016 if(s==addr) emit_mov(s,temp);
3019 if(rs1[i]!=29||start<0x80001000||start>=0x80800000)
3023 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3024 // Hint to branch predictor that the branch is unlikely to be taken
3026 emit_jno_unlikely(0);
3034 if (opcode[i]==0x28) x=3; // SB
3035 if (opcode[i]==0x29) x=2; // SH
3036 map=get_reg(i_regs->regmap,TLREG);
3038 map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3039 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3042 if (opcode[i]==0x28) { // SB
3045 #ifdef BIG_ENDIAN_MIPS
3046 if(!c) emit_xorimm(addr,3,temp);
3047 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3049 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
3050 else if (addr!=temp) emit_mov(addr,temp);
3052 //gen_tlb_addr_w(temp,map);
3053 //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3054 emit_writebyte_indexed_tlb(tl,x,temp,map,temp);
3058 if (opcode[i]==0x29) { // SH
3061 #ifdef BIG_ENDIAN_MIPS
3062 if(!c) emit_xorimm(addr,2,temp);
3063 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3065 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
3066 else if (addr!=temp) emit_mov(addr,temp);
3069 //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3072 gen_tlb_addr_w(temp,map);
3073 emit_writehword_indexed(tl,x,temp);
3075 emit_writehword_indexed(tl,(int)rdram-0x80000000+x,temp);
3079 if (opcode[i]==0x2B) { // SW
3081 //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3082 emit_writeword_indexed_tlb(tl,0,addr,map,temp);
3085 if (opcode[i]==0x3F) { // SD
3089 //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3090 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3091 emit_writedword_indexed_tlb(th,tl,0,addr,map,temp);
3094 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3095 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3096 emit_writedword_indexed_tlb(tl,tl,0,addr,map,temp);
3101 if(!using_tlb&&(!c||memtarget))
3102 // addr could be a temp, make sure it survives STORE*_STUB
3105 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3106 } else if(!memtarget) {
3107 inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3111 #ifdef DESTRUCTIVE_SHIFT
3112 // The x86 shift operation is 'destructive'; it overwrites the
3113 // source register, so we need to make a copy first and use that.
3116 #if defined(HOST_IMM8)
3117 int ir=get_reg(i_regs->regmap,INVCP);
3119 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3121 emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3125 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3128 //if(opcode[i]==0x2B || opcode[i]==0x3F)
3129 //if(opcode[i]==0x2B || opcode[i]==0x28)
3130 //if(opcode[i]==0x2B || opcode[i]==0x29)
3131 //if(opcode[i]==0x2B)
3132 /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3136 emit_readword((int)&last_count,ECX);
3138 if(get_reg(i_regs->regmap,CCREG)<0)
3139 emit_loadreg(CCREG,HOST_CCREG);
3140 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3141 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3142 emit_writeword(HOST_CCREG,(int)&Count);
3145 if(get_reg(i_regs->regmap,CCREG)<0)
3146 emit_loadreg(CCREG,0);
3148 emit_mov(HOST_CCREG,0);
3150 emit_addimm(0,2*ccadj[i],0);
3151 emit_writeword(0,(int)&Count);
3153 emit_call((int)memdebug);
3155 restore_regs(0x100f);
3159 void storelr_assemble(int i,struct regstat *i_regs)
3166 int case1,case2,case3;
3167 int done0,done1,done2;
3170 th=get_reg(i_regs->regmap,rs2[i]|64);
3171 tl=get_reg(i_regs->regmap,rs2[i]);
3172 s=get_reg(i_regs->regmap,rs1[i]);
3173 temp=get_reg(i_regs->regmap,-1);
3176 c=(i_regs->isconst>>s)&1;
3177 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80800000;
3178 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3181 for(hr=0;hr<HOST_REGS;hr++) {
3182 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3188 emit_cmpimm(s<0||offset?temp:s,0x800000);
3189 if(!offset&&s!=temp) emit_mov(s,temp);
3195 if(!memtarget||!rs1[i]) {
3200 if((u_int)rdram!=0x80000000)
3201 emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3203 int map=get_reg(i_regs->regmap,TLREG);
3205 map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3206 if(!c&&!offset&&s>=0) emit_mov(s,temp);
3207 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3208 if(!jaddr&&!memtarget) {
3212 gen_tlb_addr_w(temp,map);
3215 if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3216 temp2=get_reg(i_regs->regmap,FTEMP);
3217 if(!rs2[i]) temp2=th=tl;
3220 #ifndef BIG_ENDIAN_MIPS
3221 emit_xorimm(temp,3,temp);
3223 emit_testimm(temp,2);
3226 emit_testimm(temp,1);
3230 if (opcode[i]==0x2A) { // SWL
3231 emit_writeword_indexed(tl,0,temp);
3233 if (opcode[i]==0x2E) { // SWR
3234 emit_writebyte_indexed(tl,3,temp);
3236 if (opcode[i]==0x2C) { // SDL
3237 emit_writeword_indexed(th,0,temp);
3238 if(rs2[i]) emit_mov(tl,temp2);
3240 if (opcode[i]==0x2D) { // SDR
3241 emit_writebyte_indexed(tl,3,temp);
3242 if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3247 set_jump_target(case1,(int)out);
3248 if (opcode[i]==0x2A) { // SWL
3249 // Write 3 msb into three least significant bytes
3250 if(rs2[i]) emit_rorimm(tl,8,tl);
3251 emit_writehword_indexed(tl,-1,temp);
3252 if(rs2[i]) emit_rorimm(tl,16,tl);
3253 emit_writebyte_indexed(tl,1,temp);
3254 if(rs2[i]) emit_rorimm(tl,8,tl);
3256 if (opcode[i]==0x2E) { // SWR
3257 // Write two lsb into two most significant bytes
3258 emit_writehword_indexed(tl,1,temp);
3260 if (opcode[i]==0x2C) { // SDL
3261 if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3262 // Write 3 msb into three least significant bytes
3263 if(rs2[i]) emit_rorimm(th,8,th);
3264 emit_writehword_indexed(th,-1,temp);
3265 if(rs2[i]) emit_rorimm(th,16,th);
3266 emit_writebyte_indexed(th,1,temp);
3267 if(rs2[i]) emit_rorimm(th,8,th);
3269 if (opcode[i]==0x2D) { // SDR
3270 if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3271 // Write two lsb into two most significant bytes
3272 emit_writehword_indexed(tl,1,temp);
3277 set_jump_target(case2,(int)out);
3278 emit_testimm(temp,1);
3281 if (opcode[i]==0x2A) { // SWL
3282 // Write two msb into two least significant bytes
3283 if(rs2[i]) emit_rorimm(tl,16,tl);
3284 emit_writehword_indexed(tl,-2,temp);
3285 if(rs2[i]) emit_rorimm(tl,16,tl);
3287 if (opcode[i]==0x2E) { // SWR
3288 // Write 3 lsb into three most significant bytes
3289 emit_writebyte_indexed(tl,-1,temp);
3290 if(rs2[i]) emit_rorimm(tl,8,tl);
3291 emit_writehword_indexed(tl,0,temp);
3292 if(rs2[i]) emit_rorimm(tl,24,tl);
3294 if (opcode[i]==0x2C) { // SDL
3295 if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3296 // Write two msb into two least significant bytes
3297 if(rs2[i]) emit_rorimm(th,16,th);
3298 emit_writehword_indexed(th,-2,temp);
3299 if(rs2[i]) emit_rorimm(th,16,th);
3301 if (opcode[i]==0x2D) { // SDR
3302 if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3303 // Write 3 lsb into three most significant bytes
3304 emit_writebyte_indexed(tl,-1,temp);
3305 if(rs2[i]) emit_rorimm(tl,8,tl);
3306 emit_writehword_indexed(tl,0,temp);
3307 if(rs2[i]) emit_rorimm(tl,24,tl);
3312 set_jump_target(case3,(int)out);
3313 if (opcode[i]==0x2A) { // SWL
3314 // Write msb into least significant byte
3315 if(rs2[i]) emit_rorimm(tl,24,tl);
3316 emit_writebyte_indexed(tl,-3,temp);
3317 if(rs2[i]) emit_rorimm(tl,8,tl);
3319 if (opcode[i]==0x2E) { // SWR
3320 // Write entire word
3321 emit_writeword_indexed(tl,-3,temp);
3323 if (opcode[i]==0x2C) { // SDL
3324 if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3325 // Write msb into least significant byte
3326 if(rs2[i]) emit_rorimm(th,24,th);
3327 emit_writebyte_indexed(th,-3,temp);
3328 if(rs2[i]) emit_rorimm(th,8,th);
3330 if (opcode[i]==0x2D) { // SDR
3331 if(rs2[i]) emit_mov(th,temp2);
3332 // Write entire word
3333 emit_writeword_indexed(tl,-3,temp);
3335 set_jump_target(done0,(int)out);
3336 set_jump_target(done1,(int)out);
3337 set_jump_target(done2,(int)out);
3338 if (opcode[i]==0x2C) { // SDL
3339 emit_testimm(temp,4);
3342 emit_andimm(temp,~3,temp);
3343 emit_writeword_indexed(temp2,4,temp);
3344 set_jump_target(done0,(int)out);
3346 if (opcode[i]==0x2D) { // SDR
3347 emit_testimm(temp,4);
3350 emit_andimm(temp,~3,temp);
3351 emit_writeword_indexed(temp2,-4,temp);
3352 set_jump_target(done0,(int)out);
3355 add_stub(STORELR_STUB,jaddr,(int)out,0,(int)i_regs,rs2[i],ccadj[i],reglist);
3358 emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
3359 #if defined(HOST_IMM8)
3360 int ir=get_reg(i_regs->regmap,INVCP);
3362 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3364 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3368 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3372 //save_regs(0x100f);
3373 emit_readword((int)&last_count,ECX);
3374 if(get_reg(i_regs->regmap,CCREG)<0)
3375 emit_loadreg(CCREG,HOST_CCREG);
3376 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3377 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3378 emit_writeword(HOST_CCREG,(int)&Count);
3379 emit_call((int)memdebug);
3381 //restore_regs(0x100f);
3385 void c1ls_assemble(int i,struct regstat *i_regs)
3387 #ifndef DISABLE_COP1
3393 int jaddr,jaddr2=0,jaddr3,type;
3394 int agr=AGEN1+(i&1);
3396 th=get_reg(i_regs->regmap,FTEMP|64);
3397 tl=get_reg(i_regs->regmap,FTEMP);
3398 s=get_reg(i_regs->regmap,rs1[i]);
3399 temp=get_reg(i_regs->regmap,agr);
3400 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3405 for(hr=0;hr<HOST_REGS;hr++) {
3406 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3408 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3409 if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3411 // Loads use a temporary register which we need to save
3414 if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3418 //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3419 //else c=(i_regs->wasconst>>s)&1;
3420 if(s>=0) c=(i_regs->wasconst>>s)&1;
3421 // Check cop1 unusable
3423 signed char rs=get_reg(i_regs->regmap,CSREG);
3425 emit_testimm(rs,0x20000000);
3428 add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3431 if (opcode[i]==0x39) { // SWC1 (get float address)
3432 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],tl);
3434 if (opcode[i]==0x3D) { // SDC1 (get double address)
3435 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],tl);
3437 // Generate address + offset
3440 emit_cmpimm(offset||c||s<0?ar:s,0x800000);
3444 map=get_reg(i_regs->regmap,TLREG);
3446 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3447 map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
3449 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3450 map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
3453 if (opcode[i]==0x39) { // SWC1 (read float)
3454 emit_readword_indexed(0,tl,tl);
3456 if (opcode[i]==0x3D) { // SDC1 (read double)
3457 emit_readword_indexed(4,tl,th);
3458 emit_readword_indexed(0,tl,tl);
3460 if (opcode[i]==0x31) { // LWC1 (get target address)
3461 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],temp);
3463 if (opcode[i]==0x35) { // LDC1 (get target address)
3464 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],temp);
3471 else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80800000) {
3473 emit_jmp(0); // inline_readstub/inline_writestub? Very rare case
3475 #ifdef DESTRUCTIVE_SHIFT
3476 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3477 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3481 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3482 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3484 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3485 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3488 if (opcode[i]==0x31) { // LWC1
3489 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3490 //gen_tlb_addr_r(ar,map);
3491 //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3492 #ifdef HOST_IMM_ADDR32
3493 if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3496 emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3499 if (opcode[i]==0x35) { // LDC1
3501 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3502 //gen_tlb_addr_r(ar,map);
3503 //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3504 //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3505 #ifdef HOST_IMM_ADDR32
3506 if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3509 emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3512 if (opcode[i]==0x39) { // SWC1
3513 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3514 emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3517 if (opcode[i]==0x3D) { // SDC1
3519 //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3520 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3521 emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3525 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3526 #ifndef DESTRUCTIVE_SHIFT
3527 temp=offset||c||s<0?ar:s;
3529 #if defined(HOST_IMM8)
3530 int ir=get_reg(i_regs->regmap,INVCP);
3532 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3534 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3538 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3541 if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3542 if (opcode[i]==0x31) { // LWC1 (write float)
3543 emit_writeword_indexed(tl,0,temp);
3545 if (opcode[i]==0x35) { // LDC1 (write double)
3546 emit_writeword_indexed(th,4,temp);
3547 emit_writeword_indexed(tl,0,temp);
3549 //if(opcode[i]==0x39)
3550 /*if(opcode[i]==0x39||opcode[i]==0x31)
3553 emit_readword((int)&last_count,ECX);
3554 if(get_reg(i_regs->regmap,CCREG)<0)
3555 emit_loadreg(CCREG,HOST_CCREG);
3556 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3557 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3558 emit_writeword(HOST_CCREG,(int)&Count);
3559 emit_call((int)memdebug);
3563 cop1_unusable(i, i_regs);
3567 void c2ls_assemble(int i,struct regstat *i_regs)
3573 int jaddr,jaddr2=0,jaddr3,type;
3574 int agr=AGEN1+(i&1);
3576 u_int copr=(source[i]>>16)&0x1f;
3577 s=get_reg(i_regs->regmap,rs1[i]);
3578 tl=get_reg(i_regs->regmap,FTEMP);
3584 for(hr=0;hr<HOST_REGS;hr++) {
3585 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3587 if(i_regs->regmap[HOST_CCREG]==CCREG)
3588 reglist&=~(1<<HOST_CCREG);
3591 if (opcode[i]==0x3a) { // SWC2
3592 ar=get_reg(i_regs->regmap,agr);
3593 if(ar<0) ar=get_reg(i_regs->regmap,-1);
3598 if (!offset&&!c&&s>=0) ar=s;
3601 if (opcode[i]==0x3a) { // SWC2
3602 cop2_get_dreg(copr,tl,HOST_TEMPREG);
3604 if(s>=0) c=(i_regs->wasconst>>s)&1;
3606 emit_cmpimm(offset||c||s<0?ar:s,0x800000);
3610 else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80800000) {
3612 emit_jmp(0); // inline_readstub/inline_writestub? Very rare case
3614 if (opcode[i]==0x32) { // LWC2
3615 #ifdef HOST_IMM_ADDR32
3616 if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
3619 emit_readword_indexed(0,ar,tl);
3622 if (opcode[i]==0x3a) { // SWC2
3623 #ifdef DESTRUCTIVE_SHIFT
3624 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3626 emit_writeword_indexed(tl,0,ar);
3630 add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist);
3631 if (opcode[i]==0x3a) { // SWC2
3632 #if defined(HOST_IMM8)
3633 int ir=get_reg(i_regs->regmap,INVCP);
3635 emit_cmpmem_indexedsr12_reg(ir,ar,1);
3637 emit_cmpmem_indexedsr12_imm((int)invalid_code,ar,1);
3641 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),ar,0,0,0);
3643 if (opcode[i]==0x32) { // LWC2
3644 cop2_put_dreg(copr,tl,HOST_TEMPREG);
3648 #ifndef multdiv_assemble
3649 void multdiv_assemble(int i,struct regstat *i_regs)
3651 printf("Need multdiv_assemble for this architecture.\n");
3656 void mov_assemble(int i,struct regstat *i_regs)
3658 //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3659 //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
3662 signed char sh,sl,th,tl;
3663 th=get_reg(i_regs->regmap,rt1[i]|64);
3664 tl=get_reg(i_regs->regmap,rt1[i]);
3667 sh=get_reg(i_regs->regmap,rs1[i]|64);
3668 sl=get_reg(i_regs->regmap,rs1[i]);
3669 if(sl>=0) emit_mov(sl,tl);
3670 else emit_loadreg(rs1[i],tl);
3672 if(sh>=0) emit_mov(sh,th);
3673 else emit_loadreg(rs1[i]|64,th);
3679 #ifndef fconv_assemble
3680 void fconv_assemble(int i,struct regstat *i_regs)
3682 printf("Need fconv_assemble for this architecture.\n");
3688 void float_assemble(int i,struct regstat *i_regs)
3690 printf("Need float_assemble for this architecture.\n");
3695 void syscall_assemble(int i,struct regstat *i_regs)
3697 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3698 assert(ccreg==HOST_CCREG);
3699 assert(!is_delayslot);
3700 emit_movimm(start+i*4,EAX); // Get PC
3701 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
3702 emit_jmp((int)jump_syscall_hle); // XXX
3705 void hlecall_assemble(int i,struct regstat *i_regs)
3707 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3708 assert(ccreg==HOST_CCREG);
3709 assert(!is_delayslot);
3710 emit_movimm(start+i*4+4,0); // Get PC
3711 emit_movimm((int)psxHLEt[source[i]&7],1);
3712 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // XXX
3713 emit_jmp((int)jump_hlecall);
3716 void ds_assemble(int i,struct regstat *i_regs)
3721 alu_assemble(i,i_regs);break;
3723 imm16_assemble(i,i_regs);break;
3725 shift_assemble(i,i_regs);break;
3727 shiftimm_assemble(i,i_regs);break;
3729 load_assemble(i,i_regs);break;
3731 loadlr_assemble(i,i_regs);break;
3733 store_assemble(i,i_regs);break;
3735 storelr_assemble(i,i_regs);break;
3737 cop0_assemble(i,i_regs);break;
3739 cop1_assemble(i,i_regs);break;
3741 c1ls_assemble(i,i_regs);break;
3743 cop2_assemble(i,i_regs);break;
3745 c2ls_assemble(i,i_regs);break;
3747 c2op_assemble(i,i_regs);break;
3749 fconv_assemble(i,i_regs);break;
3751 float_assemble(i,i_regs);break;
3753 fcomp_assemble(i,i_regs);break;
3755 multdiv_assemble(i,i_regs);break;
3757 mov_assemble(i,i_regs);break;
3766 printf("Jump in the delay slot. This is probably a bug.\n");
3771 // Is the branch target a valid internal jump?
3772 int internal_branch(uint64_t i_is32,int addr)
3774 if(addr&1) return 0; // Indirect (register) jump
3775 if(addr>=start && addr<start+slen*4-4)
3777 int t=(addr-start)>>2;
3778 // Delay slots are not valid branch targets
3779 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
3780 // 64 -> 32 bit transition requires a recompile
3781 /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
3783 if(requires_32bit[t]&~i_is32) printf("optimizable: no\n");
3784 else printf("optimizable: yes\n");
3786 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
3787 if(requires_32bit[t]&~i_is32) return 0;
3793 #ifndef wb_invalidate
3794 void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
3795 uint64_t u,uint64_t uu)
3798 for(hr=0;hr<HOST_REGS;hr++) {
3799 if(hr!=EXCLUDE_REG) {
3800 if(pre[hr]!=entry[hr]) {
3803 if(get_reg(entry,pre[hr])<0) {
3805 if(!((u>>pre[hr])&1)) {
3806 emit_storereg(pre[hr],hr);
3807 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
3808 emit_sarimm(hr,31,hr);
3809 emit_storereg(pre[hr]|64,hr);
3813 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
3814 emit_storereg(pre[hr],hr);
3823 // Move from one register to another (no writeback)
3824 for(hr=0;hr<HOST_REGS;hr++) {
3825 if(hr!=EXCLUDE_REG) {
3826 if(pre[hr]!=entry[hr]) {
3827 if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
3829 if((nr=get_reg(entry,pre[hr]))>=0) {
3839 // Load the specified registers
3840 // This only loads the registers given as arguments because
3841 // we don't want to load things that will be overwritten
3842 void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
3846 for(hr=0;hr<HOST_REGS;hr++) {
3847 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
3848 if(entry[hr]!=regmap[hr]) {
3849 if(regmap[hr]==rs1||regmap[hr]==rs2)
3856 emit_loadreg(regmap[hr],hr);
3863 for(hr=0;hr<HOST_REGS;hr++) {
3864 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
3865 if(entry[hr]!=regmap[hr]) {
3866 if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
3868 assert(regmap[hr]!=64);
3869 if((is32>>(regmap[hr]&63))&1) {
3870 int lr=get_reg(regmap,regmap[hr]-64);
3872 emit_sarimm(lr,31,hr);
3874 emit_loadreg(regmap[hr],hr);
3878 emit_loadreg(regmap[hr],hr);
3886 // Load registers prior to the start of a loop
3887 // so that they are not loaded within the loop
3888 static void loop_preload(signed char pre[],signed char entry[])
3891 for(hr=0;hr<HOST_REGS;hr++) {
3892 if(hr!=EXCLUDE_REG) {
3893 if(pre[hr]!=entry[hr]) {
3895 if(get_reg(pre,entry[hr])<0) {
3896 assem_debug("loop preload:\n");
3897 //printf("loop preload: %d\n",hr);
3901 else if(entry[hr]<TEMPREG)
3903 emit_loadreg(entry[hr],hr);
3905 else if(entry[hr]-64<TEMPREG)
3907 emit_loadreg(entry[hr],hr);
3916 // Generate address for load/store instruction
3917 // goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
3918 void address_generation(int i,struct regstat *i_regs,signed char entry[])
3920 if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS||itype[i]==C2LS) {
3922 int agr=AGEN1+(i&1);
3923 int mgr=MGEN1+(i&1);
3924 if(itype[i]==LOAD) {
3925 ra=get_reg(i_regs->regmap,rt1[i]);
3926 //if(rt1[i]) assert(ra>=0);
3928 if(itype[i]==LOADLR) {
3929 ra=get_reg(i_regs->regmap,FTEMP);
3931 if(itype[i]==STORE||itype[i]==STORELR) {
3932 ra=get_reg(i_regs->regmap,agr);
3933 if(ra<0) ra=get_reg(i_regs->regmap,-1);
3935 if(itype[i]==C1LS||itype[i]==C2LS) {
3936 if ((opcode[i]&0x3b)==0x31||(opcode[i]&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
3937 ra=get_reg(i_regs->regmap,FTEMP);
3939 ra=get_reg(i_regs->regmap,agr);
3940 if(ra<0) ra=get_reg(i_regs->regmap,-1);
3943 int rs=get_reg(i_regs->regmap,rs1[i]);
3944 int rm=get_reg(i_regs->regmap,TLREG);
3947 int c=(i_regs->wasconst>>rs)&1;
3949 // Using r0 as a base address
3951 if(!entry||entry[rm]!=mgr) {
3952 generate_map_const(offset,rm);
3953 } // else did it in the previous cycle
3955 if(!entry||entry[ra]!=agr) {
3956 if (opcode[i]==0x22||opcode[i]==0x26) {
3957 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
3958 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
3959 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
3961 emit_movimm(offset,ra);
3963 } // else did it in the previous cycle
3966 if(!entry||entry[ra]!=rs1[i])
3967 emit_loadreg(rs1[i],ra);
3968 //if(!entry||entry[ra]!=rs1[i])
3969 // printf("poor load scheduling!\n");
3973 if(!entry||entry[rm]!=mgr) {
3974 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a) {
3975 // Stores to memory go thru the mapper to detect self-modifying
3976 // code, loads don't.
3977 if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
3978 (unsigned int)(constmap[i][rs]+offset)<0x80800000 )
3979 generate_map_const(constmap[i][rs]+offset,rm);
3981 if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
3982 generate_map_const(constmap[i][rs]+offset,rm);
3986 if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
3987 if(!entry||entry[ra]!=agr) {
3988 if (opcode[i]==0x22||opcode[i]==0x26) {
3989 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
3990 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
3991 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
3993 #ifdef HOST_IMM_ADDR32
3994 if((itype[i]!=LOAD&&(opcode[i]&0x3b)!=0x31&&(opcode[i]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
3995 (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
3997 emit_movimm(constmap[i][rs]+offset,ra);
3999 } // else did it in the previous cycle
4000 } // else load_consts already did it
4002 if(offset&&!c&&rs1[i]) {
4004 emit_addimm(rs,offset,ra);
4006 emit_addimm(ra,offset,ra);
4011 // Preload constants for next instruction
4012 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
4014 #ifndef HOST_IMM_ADDR32
4016 agr=MGEN1+((i+1)&1);
4017 ra=get_reg(i_regs->regmap,agr);
4019 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4020 int offset=imm[i+1];
4021 int c=(regs[i+1].wasconst>>rs)&1;
4023 if(itype[i+1]==STORE||itype[i+1]==STORELR
4024 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1, SWC2/SDC2
4025 // Stores to memory go thru the mapper to detect self-modifying
4026 // code, loads don't.
4027 if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
4028 (unsigned int)(constmap[i+1][rs]+offset)<0x80800000 )
4029 generate_map_const(constmap[i+1][rs]+offset,ra);
4031 if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
4032 generate_map_const(constmap[i+1][rs]+offset,ra);
4035 /*else if(rs1[i]==0) {
4036 generate_map_const(offset,ra);
4041 agr=AGEN1+((i+1)&1);
4042 ra=get_reg(i_regs->regmap,agr);
4044 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4045 int offset=imm[i+1];
4046 int c=(regs[i+1].wasconst>>rs)&1;
4047 if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
4048 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4049 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4050 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4051 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4053 #ifdef HOST_IMM_ADDR32
4054 if((itype[i+1]!=LOAD&&(opcode[i+1]&0x3b)!=0x31&&(opcode[i+1]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4055 (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000))
4057 emit_movimm(constmap[i+1][rs]+offset,ra);
4060 else if(rs1[i+1]==0) {
4061 // Using r0 as a base address
4062 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4063 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4064 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4065 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4067 emit_movimm(offset,ra);
4074 int get_final_value(int hr, int i, int *value)
4076 int reg=regs[i].regmap[hr];
4078 if(regs[i+1].regmap[hr]!=reg) break;
4079 if(!((regs[i+1].isconst>>hr)&1)) break;
4084 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
4085 *value=constmap[i][hr];
4089 if(itype[i+1]==UJUMP||itype[i+1]==RJUMP||itype[i+1]==CJUMP||itype[i+1]==SJUMP) {
4090 // Load in delay slot, out-of-order execution
4091 if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
4093 #ifdef HOST_IMM_ADDR32
4094 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+2])<(signed int)0xC0000000) return 0;
4096 // Precompute load address
4097 *value=constmap[i][hr]+imm[i+2];
4101 if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)
4103 #ifdef HOST_IMM_ADDR32
4104 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+1])<(signed int)0xC0000000) return 0;
4106 // Precompute load address
4107 *value=constmap[i][hr]+imm[i+1];
4108 //printf("c=%x imm=%x\n",(int)constmap[i][hr],imm[i+1]);
4113 *value=constmap[i][hr];
4114 //printf("c=%x\n",(int)constmap[i][hr]);
4115 if(i==slen-1) return 1;
4117 return !((unneeded_reg[i+1]>>reg)&1);
4119 return !((unneeded_reg_upper[i+1]>>reg)&1);
4123 // Load registers with known constants
4124 void load_consts(signed char pre[],signed char regmap[],int is32,int i)
4128 for(hr=0;hr<HOST_REGS;hr++) {
4129 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4130 //if(entry[hr]!=regmap[hr]) {
4131 if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4132 if(((regs[i].isconst>>hr)&1)&®map[hr]<64&®map[hr]>0) {
4134 if(get_final_value(hr,i,&value)) {
4139 emit_movimm(value,hr);
4147 for(hr=0;hr<HOST_REGS;hr++) {
4148 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4149 //if(entry[hr]!=regmap[hr]) {
4150 if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4151 if(((regs[i].isconst>>hr)&1)&®map[hr]>64) {
4152 if((is32>>(regmap[hr]&63))&1) {
4153 int lr=get_reg(regmap,regmap[hr]-64);
4155 emit_sarimm(lr,31,hr);
4160 if(get_final_value(hr,i,&value)) {
4165 emit_movimm(value,hr);
4174 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i)
4178 for(hr=0;hr<HOST_REGS;hr++) {
4179 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) {
4180 if(((regs[i].isconst>>hr)&1)&®map[hr]<64&®map[hr]>0) {
4181 int value=constmap[i][hr];
4186 emit_movimm(value,hr);
4192 for(hr=0;hr<HOST_REGS;hr++) {
4193 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) {
4194 if(((regs[i].isconst>>hr)&1)&®map[hr]>64) {
4195 if((is32>>(regmap[hr]&63))&1) {
4196 int lr=get_reg(regmap,regmap[hr]-64);
4198 emit_sarimm(lr,31,hr);
4202 int value=constmap[i][hr];
4207 emit_movimm(value,hr);
4215 // Write out all dirty registers (except cycle count)
4216 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty)
4219 for(hr=0;hr<HOST_REGS;hr++) {
4220 if(hr!=EXCLUDE_REG) {
4221 if(i_regmap[hr]>0) {
4222 if(i_regmap[hr]!=CCREG) {
4223 if((i_dirty>>hr)&1) {
4224 if(i_regmap[hr]<64) {
4225 emit_storereg(i_regmap[hr],hr);
4227 if( ((i_is32>>i_regmap[hr])&1) ) {
4228 #ifdef DESTRUCTIVE_WRITEBACK
4229 emit_sarimm(hr,31,hr);
4230 emit_storereg(i_regmap[hr]|64,hr);
4232 emit_sarimm(hr,31,HOST_TEMPREG);
4233 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4238 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4239 emit_storereg(i_regmap[hr],hr);
4248 // Write out dirty registers that we need to reload (pair with load_needed_regs)
4249 // This writes the registers not written by store_regs_bt
4250 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4253 int t=(addr-start)>>2;
4254 for(hr=0;hr<HOST_REGS;hr++) {
4255 if(hr!=EXCLUDE_REG) {
4256 if(i_regmap[hr]>0) {
4257 if(i_regmap[hr]!=CCREG) {
4258 if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1) && !(((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4259 if((i_dirty>>hr)&1) {
4260 if(i_regmap[hr]<64) {
4261 emit_storereg(i_regmap[hr],hr);
4263 if( ((i_is32>>i_regmap[hr])&1) ) {
4264 #ifdef DESTRUCTIVE_WRITEBACK
4265 emit_sarimm(hr,31,hr);
4266 emit_storereg(i_regmap[hr]|64,hr);
4268 emit_sarimm(hr,31,HOST_TEMPREG);
4269 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4274 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4275 emit_storereg(i_regmap[hr],hr);
4286 // Load all registers (except cycle count)
4287 void load_all_regs(signed char i_regmap[])
4290 for(hr=0;hr<HOST_REGS;hr++) {
4291 if(hr!=EXCLUDE_REG) {
4292 if(i_regmap[hr]==0) {
4296 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG)
4298 emit_loadreg(i_regmap[hr],hr);
4304 // Load all current registers also needed by next instruction
4305 void load_needed_regs(signed char i_regmap[],signed char next_regmap[])
4308 for(hr=0;hr<HOST_REGS;hr++) {
4309 if(hr!=EXCLUDE_REG) {
4310 if(get_reg(next_regmap,i_regmap[hr])>=0) {
4311 if(i_regmap[hr]==0) {
4315 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG)
4317 emit_loadreg(i_regmap[hr],hr);
4324 // Load all regs, storing cycle count if necessary
4325 void load_regs_entry(int t)
4328 if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER,HOST_CCREG);
4329 else if(ccadj[t]) emit_addimm(HOST_CCREG,-ccadj[t]*CLOCK_DIVIDER,HOST_CCREG);
4330 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4331 emit_storereg(CCREG,HOST_CCREG);
4334 for(hr=0;hr<HOST_REGS;hr++) {
4335 if(regs[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<64) {
4336 if(regs[t].regmap_entry[hr]==0) {
4339 else if(regs[t].regmap_entry[hr]!=CCREG)
4341 emit_loadreg(regs[t].regmap_entry[hr],hr);
4346 for(hr=0;hr<HOST_REGS;hr++) {
4347 if(regs[t].regmap_entry[hr]>=64) {
4348 assert(regs[t].regmap_entry[hr]!=64);
4349 if((regs[t].was32>>(regs[t].regmap_entry[hr]&63))&1) {
4350 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4352 emit_loadreg(regs[t].regmap_entry[hr],hr);
4356 emit_sarimm(lr,31,hr);
4361 emit_loadreg(regs[t].regmap_entry[hr],hr);
4367 // Store dirty registers prior to branch
4368 void store_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4370 if(internal_branch(i_is32,addr))
4372 int t=(addr-start)>>2;
4374 for(hr=0;hr<HOST_REGS;hr++) {
4375 if(hr!=EXCLUDE_REG) {
4376 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4377 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4378 if((i_dirty>>hr)&1) {
4379 if(i_regmap[hr]<64) {
4380 if(!((unneeded_reg[t]>>i_regmap[hr])&1)) {
4381 emit_storereg(i_regmap[hr],hr);
4382 if( ((i_is32>>i_regmap[hr])&1) && !((unneeded_reg_upper[t]>>i_regmap[hr])&1) ) {
4383 #ifdef DESTRUCTIVE_WRITEBACK
4384 emit_sarimm(hr,31,hr);
4385 emit_storereg(i_regmap[hr]|64,hr);
4387 emit_sarimm(hr,31,HOST_TEMPREG);
4388 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4393 if( !((i_is32>>(i_regmap[hr]&63))&1) && !((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1) ) {
4394 emit_storereg(i_regmap[hr],hr);
4405 // Branch out of this block, write out all dirty regs
4406 wb_dirtys(i_regmap,i_is32,i_dirty);
4410 // Load all needed registers for branch target
4411 void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4413 //if(addr>=start && addr<(start+slen*4))
4414 if(internal_branch(i_is32,addr))
4416 int t=(addr-start)>>2;
4418 // Store the cycle count before loading something else
4419 if(i_regmap[HOST_CCREG]!=CCREG) {
4420 assert(i_regmap[HOST_CCREG]==-1);
4422 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4423 emit_storereg(CCREG,HOST_CCREG);
4426 for(hr=0;hr<HOST_REGS;hr++) {
4427 if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<64) {
4428 #ifdef DESTRUCTIVE_WRITEBACK
4429 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || ( !((regs[t].dirty>>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4431 if(i_regmap[hr]!=regs[t].regmap_entry[hr] ) {
4433 if(regs[t].regmap_entry[hr]==0) {
4436 else if(regs[t].regmap_entry[hr]!=CCREG)
4438 emit_loadreg(regs[t].regmap_entry[hr],hr);
4444 for(hr=0;hr<HOST_REGS;hr++) {
4445 if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=64) {
4446 if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4447 assert(regs[t].regmap_entry[hr]!=64);
4448 if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4449 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4451 emit_loadreg(regs[t].regmap_entry[hr],hr);
4455 emit_sarimm(lr,31,hr);
4460 emit_loadreg(regs[t].regmap_entry[hr],hr);
4463 else if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4464 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4466 emit_sarimm(lr,31,hr);
4473 int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4475 if(addr>=start && addr<start+slen*4-4)
4477 int t=(addr-start)>>2;
4479 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4480 for(hr=0;hr<HOST_REGS;hr++)
4484 if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4486 if(regs[t].regmap_entry[hr]!=-1)
4495 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4500 if(!((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1))
4505 else // Same register but is it 32-bit or dirty?
4508 if(!((regs[t].dirty>>hr)&1))
4512 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4514 //printf("%x: dirty no match\n",addr);
4519 if((((regs[t].was32^i_is32)&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)
4521 //printf("%x: is32 no match\n",addr);
4527 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4528 if(requires_32bit[t]&~i_is32) return 0;
4529 // Delay slots are not valid branch targets
4530 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4531 // Delay slots require additional processing, so do not match
4532 if(is_ds[t]) return 0;
4537 for(hr=0;hr<HOST_REGS;hr++)
4543 if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4557 // Used when a branch jumps into the delay slot of another branch
4558 void ds_assemble_entry(int i)
4560 int t=(ba[i]-start)>>2;
4561 if(!instr_addr[t]) instr_addr[t]=(u_int)out;
4562 assem_debug("Assemble delay slot at %x\n",ba[i]);
4563 assem_debug("<->\n");
4564 if(regs[t].regmap_entry[HOST_CCREG]==CCREG&®s[t].regmap[HOST_CCREG]!=CCREG)
4565 wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty,regs[t].was32);
4566 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,rs1[t],rs2[t]);
4567 address_generation(t,®s[t],regs[t].regmap_entry);
4568 if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39||(opcode[t]&0x3b)==0x3a)
4569 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,INVCP,INVCP);
4574 alu_assemble(t,®s[t]);break;
4576 imm16_assemble(t,®s[t]);break;
4578 shift_assemble(t,®s[t]);break;
4580 shiftimm_assemble(t,®s[t]);break;
4582 load_assemble(t,®s[t]);break;
4584 loadlr_assemble(t,®s[t]);break;
4586 store_assemble(t,®s[t]);break;
4588 storelr_assemble(t,®s[t]);break;
4590 cop0_assemble(t,®s[t]);break;
4592 cop1_assemble(t,®s[t]);break;
4594 c1ls_assemble(t,®s[t]);break;
4596 cop2_assemble(t,®s[t]);break;
4598 c2ls_assemble(t,®s[t]);break;
4600 c2op_assemble(t,®s[t]);break;
4602 fconv_assemble(t,®s[t]);break;
4604 float_assemble(t,®s[t]);break;
4606 fcomp_assemble(t,®s[t]);break;
4608 multdiv_assemble(t,®s[t]);break;
4610 mov_assemble(t,®s[t]);break;
4619 printf("Jump in the delay slot. This is probably a bug.\n");
4621 store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4622 load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4623 if(internal_branch(regs[t].is32,ba[i]+4))
4624 assem_debug("branch: internal\n");
4626 assem_debug("branch: external\n");
4627 assert(internal_branch(regs[t].is32,ba[i]+4));
4628 add_to_linker((int)out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4));
4632 void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
4641 //if(ba[i]>=start && ba[i]<(start+slen*4))
4642 if(internal_branch(branch_regs[i].is32,ba[i]))
4644 int t=(ba[i]-start)>>2;
4645 if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
4653 if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4655 if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
4657 //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4658 emit_andimm(HOST_CCREG,3,HOST_CCREG);
4662 else if(*adj==0||invert) {
4663 emit_addimm_and_set_flags(CLOCK_DIVIDER*(count+2),HOST_CCREG);
4669 emit_cmpimm(HOST_CCREG,-2*(count+2));
4673 add_stub(CC_STUB,jaddr,idle?idle:(int)out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
4676 void do_ccstub(int n)
4679 assem_debug("do_ccstub %x\n",start+stubs[n][4]*4);
4680 set_jump_target(stubs[n][1],(int)out);
4682 if(stubs[n][6]==NULLDS) {
4683 // Delay slot instruction is nullified ("likely" branch)
4684 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
4686 else if(stubs[n][6]!=TAKEN) {
4687 wb_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty);
4690 if(internal_branch(branch_regs[i].is32,ba[i]))
4691 wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4695 // Save PC as return address
4696 emit_movimm(stubs[n][5],EAX);
4697 emit_writeword(EAX,(int)&pcaddr);
4701 // Return address depends on which way the branch goes
4702 if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
4704 int s1l=get_reg(branch_regs[i].regmap,rs1[i]);
4705 int s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
4706 int s2l=get_reg(branch_regs[i].regmap,rs2[i]);
4707 int s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
4717 if((branch_regs[i].is32>>rs1[i])&(branch_regs[i].is32>>rs2[i])&1) {
4721 #ifdef DESTRUCTIVE_WRITEBACK
4723 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1)
4724 emit_loadreg(rs1[i],s1l);
4727 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1)
4728 emit_loadreg(rs2[i],s1l);
4731 if((branch_regs[i].dirty>>s2l)&(branch_regs[i].is32>>rs2[i])&1)
4732 emit_loadreg(rs2[i],s2l);
4735 int addr,alt,ntaddr;
4738 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4739 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4740 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4748 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4749 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4750 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4756 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
4760 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4761 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4762 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4768 assert(hr<HOST_REGS);
4770 if((opcode[i]&0x2f)==4) // BEQ
4772 #ifdef HAVE_CMOV_IMM
4774 if(s2l>=0) emit_cmp(s1l,s2l);
4775 else emit_test(s1l,s1l);
4776 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
4781 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4783 if(s2h>=0) emit_cmp(s1h,s2h);
4784 else emit_test(s1h,s1h);
4785 emit_cmovne_reg(alt,addr);
4787 if(s2l>=0) emit_cmp(s1l,s2l);
4788 else emit_test(s1l,s1l);
4789 emit_cmovne_reg(alt,addr);
4792 if((opcode[i]&0x2f)==5) // BNE
4794 #ifdef HAVE_CMOV_IMM
4796 if(s2l>=0) emit_cmp(s1l,s2l);
4797 else emit_test(s1l,s1l);
4798 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
4803 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
4805 if(s2h>=0) emit_cmp(s1h,s2h);
4806 else emit_test(s1h,s1h);
4807 emit_cmovne_reg(alt,addr);
4809 if(s2l>=0) emit_cmp(s1l,s2l);
4810 else emit_test(s1l,s1l);
4811 emit_cmovne_reg(alt,addr);
4814 if((opcode[i]&0x2f)==6) // BLEZ
4816 //emit_movimm(ba[i],alt);
4817 //emit_movimm(start+i*4+8,addr);
4818 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4820 if(s1h>=0) emit_mov(addr,ntaddr);
4821 emit_cmovl_reg(alt,addr);
4824 emit_cmovne_reg(ntaddr,addr);
4825 emit_cmovs_reg(alt,addr);
4828 if((opcode[i]&0x2f)==7) // BGTZ
4830 //emit_movimm(ba[i],addr);
4831 //emit_movimm(start+i*4+8,ntaddr);
4832 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
4834 if(s1h>=0) emit_mov(addr,alt);
4835 emit_cmovl_reg(ntaddr,addr);
4838 emit_cmovne_reg(alt,addr);
4839 emit_cmovs_reg(ntaddr,addr);
4842 if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ
4844 //emit_movimm(ba[i],alt);
4845 //emit_movimm(start+i*4+8,addr);
4846 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4847 if(s1h>=0) emit_test(s1h,s1h);
4848 else emit_test(s1l,s1l);
4849 emit_cmovs_reg(alt,addr);
4851 if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ
4853 //emit_movimm(ba[i],addr);
4854 //emit_movimm(start+i*4+8,alt);
4855 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4856 if(s1h>=0) emit_test(s1h,s1h);
4857 else emit_test(s1l,s1l);
4858 emit_cmovs_reg(alt,addr);
4860 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
4861 if(source[i]&0x10000) // BC1T
4863 //emit_movimm(ba[i],alt);
4864 //emit_movimm(start+i*4+8,addr);
4865 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4866 emit_testimm(s1l,0x800000);
4867 emit_cmovne_reg(alt,addr);
4871 //emit_movimm(ba[i],addr);
4872 //emit_movimm(start+i*4+8,alt);
4873 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4874 emit_testimm(s1l,0x800000);
4875 emit_cmovne_reg(alt,addr);
4878 emit_writeword(addr,(int)&pcaddr);
4883 int r=get_reg(branch_regs[i].regmap,rs1[i]);
4884 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
4885 r=get_reg(branch_regs[i].regmap,RTEMP);
4887 emit_writeword(r,(int)&pcaddr);
4889 else {printf("Unknown branch type in do_ccstub\n");exit(1);}
4891 // Update cycle count
4892 assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
4893 if(stubs[n][3]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
4894 emit_call((int)cc_interrupt);
4895 if(stubs[n][3]) emit_addimm(HOST_CCREG,-CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
4896 if(stubs[n][6]==TAKEN) {
4897 if(internal_branch(branch_regs[i].is32,ba[i]))
4898 load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
4899 else if(itype[i]==RJUMP) {
4900 if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
4901 emit_readword((int)&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
4903 emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i]));
4905 }else if(stubs[n][6]==NOTTAKEN) {
4906 if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
4907 else load_all_regs(branch_regs[i].regmap);
4908 }else if(stubs[n][6]==NULLDS) {
4909 // Delay slot instruction is nullified ("likely" branch)
4910 if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
4911 else load_all_regs(regs[i].regmap);
4913 load_all_regs(branch_regs[i].regmap);
4915 emit_jmp(stubs[n][2]); // return address
4917 /* This works but uses a lot of memory...
4918 emit_readword((int)&last_count,ECX);
4919 emit_add(HOST_CCREG,ECX,EAX);
4920 emit_writeword(EAX,(int)&Count);
4921 emit_call((int)gen_interupt);
4922 emit_readword((int)&Count,HOST_CCREG);
4923 emit_readword((int)&next_interupt,EAX);
4924 emit_readword((int)&pending_exception,EBX);
4925 emit_writeword(EAX,(int)&last_count);
4926 emit_sub(HOST_CCREG,EAX,HOST_CCREG);
4928 int jne_instr=(int)out;
4930 if(stubs[n][3]) emit_addimm(HOST_CCREG,-2*stubs[n][3],HOST_CCREG);
4931 load_all_regs(branch_regs[i].regmap);
4932 emit_jmp(stubs[n][2]); // return address
4933 set_jump_target(jne_instr,(int)out);
4934 emit_readword((int)&pcaddr,EAX);
4935 // Call get_addr_ht instead of doing the hash table here.
4936 // This code is executed infrequently and takes up a lot of space
4937 // so smaller is better.
4938 emit_storereg(CCREG,HOST_CCREG);
4940 emit_call((int)get_addr_ht);
4941 emit_loadreg(CCREG,HOST_CCREG);
4942 emit_addimm(ESP,4,ESP);
4946 add_to_linker(int addr,int target,int ext)
4948 link_addr[linkcount][0]=addr;
4949 link_addr[linkcount][1]=target;
4950 link_addr[linkcount][2]=ext;
4954 void ujump_assemble(int i,struct regstat *i_regs)
4956 signed char *i_regmap=i_regs->regmap;
4957 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
4958 address_generation(i+1,i_regs,regs[i].regmap_entry);
4960 int temp=get_reg(branch_regs[i].regmap,PTEMP);
4961 if(rt1[i]==31&&temp>=0)
4963 int return_address=start+i*4+8;
4964 if(get_reg(branch_regs[i].regmap,31)>0)
4965 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
4968 ds_assemble(i+1,i_regs);
4969 uint64_t bc_unneeded=branch_regs[i].u;
4970 uint64_t bc_unneeded_upper=branch_regs[i].uu;
4971 bc_unneeded|=1|(1LL<<rt1[i]);
4972 bc_unneeded_upper|=1|(1LL<<rt1[i]);
4973 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
4974 bc_unneeded,bc_unneeded_upper);
4975 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
4978 unsigned int return_address;
4979 assert(rt1[i+1]!=31);
4980 assert(rt2[i+1]!=31);
4981 rt=get_reg(branch_regs[i].regmap,31);
4982 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
4984 return_address=start+i*4+8;
4987 if(internal_branch(branch_regs[i].is32,return_address)) {
4989 if(temp==EXCLUDE_REG||temp>=HOST_REGS||
4990 branch_regs[i].regmap[temp]>=0)
4992 temp=get_reg(branch_regs[i].regmap,-1);
4995 if(temp<0) temp=HOST_TEMPREG;
4997 if(temp>=0) do_miniht_insert(return_address,rt,temp);
4998 else emit_movimm(return_address,rt);
5006 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5009 emit_movimm(return_address,rt); // PC into link register
5011 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5017 cc=get_reg(branch_regs[i].regmap,CCREG);
5018 assert(cc==HOST_CCREG);
5019 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5021 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5023 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5024 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5025 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5026 if(internal_branch(branch_regs[i].is32,ba[i]))
5027 assem_debug("branch: internal\n");
5029 assem_debug("branch: external\n");
5030 if(internal_branch(branch_regs[i].is32,ba[i])&&is_ds[(ba[i]-start)>>2]) {
5031 ds_assemble_entry(i);
5034 add_to_linker((int)out,ba[i],internal_branch(branch_regs[i].is32,ba[i]));
5039 void rjump_assemble(int i,struct regstat *i_regs)
5041 signed char *i_regmap=i_regs->regmap;
5044 rs=get_reg(branch_regs[i].regmap,rs1[i]);
5046 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5047 // Delay slot abuse, make a copy of the branch address register
5048 temp=get_reg(branch_regs[i].regmap,RTEMP);
5050 assert(regs[i].regmap[temp]==RTEMP);
5054 address_generation(i+1,i_regs,regs[i].regmap_entry);
5058 if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5059 int return_address=start+i*4+8;
5060 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5066 int rh=get_reg(regs[i].regmap,RHASH);
5067 if(rh>=0) do_preload_rhash(rh);
5070 ds_assemble(i+1,i_regs);
5071 uint64_t bc_unneeded=branch_regs[i].u;
5072 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5073 bc_unneeded|=1|(1LL<<rt1[i]);
5074 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5075 bc_unneeded&=~(1LL<<rs1[i]);
5076 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5077 bc_unneeded,bc_unneeded_upper);
5078 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
5080 int rt,return_address;
5081 assert(rt1[i+1]!=31);
5082 assert(rt2[i+1]!=31);
5083 rt=get_reg(branch_regs[i].regmap,31);
5084 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5086 return_address=start+i*4+8;
5090 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5093 emit_movimm(return_address,rt); // PC into link register
5095 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5098 cc=get_reg(branch_regs[i].regmap,CCREG);
5099 assert(cc==HOST_CCREG);
5101 int rh=get_reg(branch_regs[i].regmap,RHASH);
5102 int ht=get_reg(branch_regs[i].regmap,RHTBL);
5104 if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5105 do_preload_rhtbl(ht);
5109 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5110 #ifdef DESTRUCTIVE_WRITEBACK
5111 if((branch_regs[i].dirty>>rs)&(branch_regs[i].is32>>rs1[i])&1) {
5112 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
5113 emit_loadreg(rs1[i],rs);
5118 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5122 do_miniht_load(ht,rh);
5125 //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5126 //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5128 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5129 add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
5131 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5134 do_miniht_jump(rs,rh,ht);
5139 //if(rs!=EAX) emit_mov(rs,EAX);
5140 //emit_jmp((int)jump_vaddr_eax);
5141 emit_jmp(jump_vaddr_reg[rs]);
5146 emit_shrimm(rs,16,rs);
5147 emit_xor(temp,rs,rs);
5148 emit_movzwl_reg(rs,rs);
5149 emit_shlimm(rs,4,rs);
5150 emit_cmpmem_indexed((int)hash_table,rs,temp);
5151 emit_jne((int)out+14);
5152 emit_readword_indexed((int)hash_table+4,rs,rs);
5154 emit_cmpmem_indexed((int)hash_table+8,rs,temp);
5155 emit_addimm_no_flags(8,rs);
5156 emit_jeq((int)out-17);
5157 // No hit on hash table, call compiler
5160 #ifdef DEBUG_CYCLE_COUNT
5161 emit_readword((int)&last_count,ECX);
5162 emit_add(HOST_CCREG,ECX,HOST_CCREG);
5163 emit_readword((int)&next_interupt,ECX);
5164 emit_writeword(HOST_CCREG,(int)&Count);
5165 emit_sub(HOST_CCREG,ECX,HOST_CCREG);
5166 emit_writeword(ECX,(int)&last_count);
5169 emit_storereg(CCREG,HOST_CCREG);
5170 emit_call((int)get_addr);
5171 emit_loadreg(CCREG,HOST_CCREG);
5172 emit_addimm(ESP,4,ESP);
5174 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5175 if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5179 void cjump_assemble(int i,struct regstat *i_regs)
5181 signed char *i_regmap=i_regs->regmap;
5184 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5185 assem_debug("match=%d\n",match);
5186 int s1h,s1l,s2h,s2l;
5187 int prev_cop1_usable=cop1_usable;
5188 int unconditional=0,nop=0;
5192 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5193 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5194 if(likely[i]) ooo=0;
5195 if(!match) invert=1;
5196 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5197 if(i>(ba[i]-start)>>2) invert=1;
5201 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
5202 (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1])))
5204 // Write-after-read dependency prevents out of order execution
5205 // First test branch condition, then execute delay slot, then branch
5210 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5211 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5212 s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5213 s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5216 s1l=get_reg(i_regmap,rs1[i]);
5217 s1h=get_reg(i_regmap,rs1[i]|64);
5218 s2l=get_reg(i_regmap,rs2[i]);
5219 s2h=get_reg(i_regmap,rs2[i]|64);
5221 if(rs1[i]==0&&rs2[i]==0)
5223 if(opcode[i]&1) nop=1;
5224 else unconditional=1;
5225 //assert(opcode[i]!=5);
5226 //assert(opcode[i]!=7);
5227 //assert(opcode[i]!=0x15);
5228 //assert(opcode[i]!=0x17);
5234 only32=(regs[i].was32>>rs2[i])&1;
5239 only32=(regs[i].was32>>rs1[i])&1;
5242 only32=(regs[i].was32>>rs1[i])&(regs[i].was32>>rs2[i])&1;
5246 // Out of order execution (delay slot first)
5248 address_generation(i+1,i_regs,regs[i].regmap_entry);
5249 ds_assemble(i+1,i_regs);
5251 uint64_t bc_unneeded=branch_regs[i].u;
5252 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5253 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5254 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5256 bc_unneeded_upper|=1;
5257 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5258 bc_unneeded,bc_unneeded_upper);
5259 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
5260 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5261 cc=get_reg(branch_regs[i].regmap,CCREG);
5262 assert(cc==HOST_CCREG);
5264 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5265 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5266 //assem_debug("cycle count (adj)\n");
5268 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5269 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5270 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5271 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5273 assem_debug("branch: internal\n");
5275 assem_debug("branch: external\n");
5276 if(internal&&is_ds[(ba[i]-start)>>2]) {
5277 ds_assemble_entry(i);
5280 add_to_linker((int)out,ba[i],internal);
5283 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5284 if(((u_int)out)&7) emit_addnop(0);
5289 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5292 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5295 int taken=0,nottaken=0,nottaken1=0;
5296 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5297 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5301 if(opcode[i]==4) // BEQ
5303 if(s2h>=0) emit_cmp(s1h,s2h);
5304 else emit_test(s1h,s1h);
5308 if(opcode[i]==5) // BNE
5310 if(s2h>=0) emit_cmp(s1h,s2h);
5311 else emit_test(s1h,s1h);
5312 if(invert) taken=(int)out;
5313 else add_to_linker((int)out,ba[i],internal);
5316 if(opcode[i]==6) // BLEZ
5319 if(invert) taken=(int)out;
5320 else add_to_linker((int)out,ba[i],internal);
5325 if(opcode[i]==7) // BGTZ
5330 if(invert) taken=(int)out;
5331 else add_to_linker((int)out,ba[i],internal);
5336 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5338 if(opcode[i]==4) // BEQ
5340 if(s2l>=0) emit_cmp(s1l,s2l);
5341 else emit_test(s1l,s1l);
5346 add_to_linker((int)out,ba[i],internal);
5350 if(opcode[i]==5) // BNE
5352 if(s2l>=0) emit_cmp(s1l,s2l);
5353 else emit_test(s1l,s1l);
5358 add_to_linker((int)out,ba[i],internal);
5362 if(opcode[i]==6) // BLEZ
5369 add_to_linker((int)out,ba[i],internal);
5373 if(opcode[i]==7) // BGTZ
5380 add_to_linker((int)out,ba[i],internal);
5385 if(taken) set_jump_target(taken,(int)out);
5386 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5387 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5389 emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5390 add_to_linker((int)out,ba[i],internal);
5393 add_to_linker((int)out,ba[i],internal*2);
5399 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5400 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5401 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5403 assem_debug("branch: internal\n");
5405 assem_debug("branch: external\n");
5406 if(internal&&is_ds[(ba[i]-start)>>2]) {
5407 ds_assemble_entry(i);
5410 add_to_linker((int)out,ba[i],internal);
5414 set_jump_target(nottaken,(int)out);
5417 if(nottaken1) set_jump_target(nottaken1,(int)out);
5419 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5421 } // (!unconditional)
5425 // In-order execution (branch first)
5426 //if(likely[i]) printf("IOL\n");
5429 int taken=0,nottaken=0,nottaken1=0;
5430 if(!unconditional&&!nop) {
5434 if((opcode[i]&0x2f)==4) // BEQ
5436 if(s2h>=0) emit_cmp(s1h,s2h);
5437 else emit_test(s1h,s1h);
5441 if((opcode[i]&0x2f)==5) // BNE
5443 if(s2h>=0) emit_cmp(s1h,s2h);
5444 else emit_test(s1h,s1h);
5448 if((opcode[i]&0x2f)==6) // BLEZ
5456 if((opcode[i]&0x2f)==7) // BGTZ
5466 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5468 if((opcode[i]&0x2f)==4) // BEQ
5470 if(s2l>=0) emit_cmp(s1l,s2l);
5471 else emit_test(s1l,s1l);
5475 if((opcode[i]&0x2f)==5) // BNE
5477 if(s2l>=0) emit_cmp(s1l,s2l);
5478 else emit_test(s1l,s1l);
5482 if((opcode[i]&0x2f)==6) // BLEZ
5488 if((opcode[i]&0x2f)==7) // BGTZ
5494 } // if(!unconditional)
5496 uint64_t ds_unneeded=branch_regs[i].u;
5497 uint64_t ds_unneeded_upper=branch_regs[i].uu;
5498 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5499 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5500 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5502 ds_unneeded_upper|=1;
5505 if(taken) set_jump_target(taken,(int)out);
5506 assem_debug("1:\n");
5507 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5508 ds_unneeded,ds_unneeded_upper);
5510 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5511 address_generation(i+1,&branch_regs[i],0);
5512 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5513 ds_assemble(i+1,&branch_regs[i]);
5514 cc=get_reg(branch_regs[i].regmap,CCREG);
5516 emit_loadreg(CCREG,cc=HOST_CCREG);
5517 // CHECK: Is the following instruction (fall thru) allocated ok?
5519 assert(cc==HOST_CCREG);
5520 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5521 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5522 assem_debug("cycle count (adj)\n");
5523 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5524 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5526 assem_debug("branch: internal\n");
5528 assem_debug("branch: external\n");
5529 if(internal&&is_ds[(ba[i]-start)>>2]) {
5530 ds_assemble_entry(i);
5533 add_to_linker((int)out,ba[i],internal);
5538 cop1_usable=prev_cop1_usable;
5539 if(!unconditional) {
5540 if(nottaken1) set_jump_target(nottaken1,(int)out);
5541 set_jump_target(nottaken,(int)out);
5542 assem_debug("2:\n");
5544 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5545 ds_unneeded,ds_unneeded_upper);
5546 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5547 address_generation(i+1,&branch_regs[i],0);
5548 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5549 ds_assemble(i+1,&branch_regs[i]);
5551 cc=get_reg(branch_regs[i].regmap,CCREG);
5552 if(cc==-1&&!likely[i]) {
5553 // Cycle count isn't in a register, temporarily load it then write it out
5554 emit_loadreg(CCREG,HOST_CCREG);
5555 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5558 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5559 emit_storereg(CCREG,HOST_CCREG);
5562 cc=get_reg(i_regmap,CCREG);
5563 assert(cc==HOST_CCREG);
5564 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5567 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5573 void sjump_assemble(int i,struct regstat *i_regs)
5575 signed char *i_regmap=i_regs->regmap;
5578 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5579 assem_debug("smatch=%d\n",match);
5581 int prev_cop1_usable=cop1_usable;
5582 int unconditional=0,nevertaken=0;
5586 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5587 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5588 if(likely[i]) ooo=0;
5589 if(!match) invert=1;
5590 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5591 if(i>(ba[i]-start)>>2) invert=1;
5594 //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
5595 assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
5598 if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))
5600 // Write-after-read dependency prevents out of order execution
5601 // First test branch condition, then execute delay slot, then branch
5604 // TODO: Conditional branches w/link must execute in-order so that
5605 // condition test and write to r31 occur before cycle count test
5608 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5609 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5612 s1l=get_reg(i_regmap,rs1[i]);
5613 s1h=get_reg(i_regmap,rs1[i]|64);
5617 if(opcode2[i]&1) unconditional=1;
5619 // These are never taken (r0 is never less than zero)
5620 //assert(opcode2[i]!=0);
5621 //assert(opcode2[i]!=2);
5622 //assert(opcode2[i]!=0x10);
5623 //assert(opcode2[i]!=0x12);
5626 only32=(regs[i].was32>>rs1[i])&1;
5630 // Out of order execution (delay slot first)
5632 address_generation(i+1,i_regs,regs[i].regmap_entry);
5633 ds_assemble(i+1,i_regs);
5635 uint64_t bc_unneeded=branch_regs[i].u;
5636 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5637 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5638 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5640 bc_unneeded_upper|=1;
5641 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5642 bc_unneeded,bc_unneeded_upper);
5643 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5644 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5646 int rt,return_address;
5647 assert(rt1[i+1]!=31);
5648 assert(rt2[i+1]!=31);
5649 rt=get_reg(branch_regs[i].regmap,31);
5650 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5652 // Save the PC even if the branch is not taken
5653 return_address=start+i*4+8;
5654 emit_movimm(return_address,rt); // PC into link register
5656 if(!nevertaken) emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5660 cc=get_reg(branch_regs[i].regmap,CCREG);
5661 assert(cc==HOST_CCREG);
5663 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5664 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5665 assem_debug("cycle count (adj)\n");
5667 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5668 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5669 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5670 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5672 assem_debug("branch: internal\n");
5674 assem_debug("branch: external\n");
5675 if(internal&&is_ds[(ba[i]-start)>>2]) {
5676 ds_assemble_entry(i);
5679 add_to_linker((int)out,ba[i],internal);
5682 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5683 if(((u_int)out)&7) emit_addnop(0);
5687 else if(nevertaken) {
5688 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5691 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5695 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5696 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5700 if(opcode2[i]==0) // BLTZ
5707 add_to_linker((int)out,ba[i],internal);
5711 if(opcode2[i]==1) // BGEZ
5718 add_to_linker((int)out,ba[i],internal);
5726 if(opcode2[i]==0) // BLTZ
5733 add_to_linker((int)out,ba[i],internal);
5737 if(opcode2[i]==1) // BGEZ
5744 add_to_linker((int)out,ba[i],internal);
5751 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5752 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5754 emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5755 add_to_linker((int)out,ba[i],internal);
5758 add_to_linker((int)out,ba[i],internal*2);
5764 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5765 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5766 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5768 assem_debug("branch: internal\n");
5770 assem_debug("branch: external\n");
5771 if(internal&&is_ds[(ba[i]-start)>>2]) {
5772 ds_assemble_entry(i);
5775 add_to_linker((int)out,ba[i],internal);
5779 set_jump_target(nottaken,(int)out);
5783 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5785 } // (!unconditional)
5789 // In-order execution (branch first)
5792 if(!unconditional) {
5793 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5797 if((opcode2[i]&0x1d)==0) // BLTZ/BLTZL
5803 if((opcode2[i]&0x1d)==1) // BGEZ/BGEZL
5813 if((opcode2[i]&0x1d)==0) // BLTZ/BLTZL
5819 if((opcode2[i]&0x1d)==1) // BGEZ/BGEZL
5826 } // if(!unconditional)
5828 uint64_t ds_unneeded=branch_regs[i].u;
5829 uint64_t ds_unneeded_upper=branch_regs[i].uu;
5830 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5831 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5832 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5834 ds_unneeded_upper|=1;
5837 //assem_debug("1:\n");
5838 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5839 ds_unneeded,ds_unneeded_upper);
5841 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5842 address_generation(i+1,&branch_regs[i],0);
5843 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5844 ds_assemble(i+1,&branch_regs[i]);
5845 cc=get_reg(branch_regs[i].regmap,CCREG);
5847 emit_loadreg(CCREG,cc=HOST_CCREG);
5848 // CHECK: Is the following instruction (fall thru) allocated ok?
5850 assert(cc==HOST_CCREG);
5851 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5852 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5853 assem_debug("cycle count (adj)\n");
5854 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5855 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5857 assem_debug("branch: internal\n");
5859 assem_debug("branch: external\n");
5860 if(internal&&is_ds[(ba[i]-start)>>2]) {
5861 ds_assemble_entry(i);
5864 add_to_linker((int)out,ba[i],internal);
5869 cop1_usable=prev_cop1_usable;
5870 if(!unconditional) {
5871 set_jump_target(nottaken,(int)out);
5872 assem_debug("1:\n");
5874 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5875 ds_unneeded,ds_unneeded_upper);
5876 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5877 address_generation(i+1,&branch_regs[i],0);
5878 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5879 ds_assemble(i+1,&branch_regs[i]);
5881 cc=get_reg(branch_regs[i].regmap,CCREG);
5882 if(cc==-1&&!likely[i]) {
5883 // Cycle count isn't in a register, temporarily load it then write it out
5884 emit_loadreg(CCREG,HOST_CCREG);
5885 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5888 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5889 emit_storereg(CCREG,HOST_CCREG);
5892 cc=get_reg(i_regmap,CCREG);
5893 assert(cc==HOST_CCREG);
5894 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5897 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5903 void fjump_assemble(int i,struct regstat *i_regs)
5905 signed char *i_regmap=i_regs->regmap;
5908 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5909 assem_debug("fmatch=%d\n",match);
5914 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5915 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5916 if(likely[i]) ooo=0;
5917 if(!match) invert=1;
5918 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5919 if(i>(ba[i]-start)>>2) invert=1;
5923 if(itype[i+1]==FCOMP)
5925 // Write-after-read dependency prevents out of order execution
5926 // First test branch condition, then execute delay slot, then branch
5931 fs=get_reg(branch_regs[i].regmap,FSREG);
5932 address_generation(i+1,i_regs,regs[i].regmap_entry); // Is this okay?
5935 fs=get_reg(i_regmap,FSREG);
5938 // Check cop1 unusable
5940 cs=get_reg(i_regmap,CSREG);
5942 emit_testimm(cs,0x20000000);
5945 add_stub(FP_STUB,eaddr,(int)out,i,cs,(int)i_regs,0,0);
5950 // Out of order execution (delay slot first)
5952 ds_assemble(i+1,i_regs);
5954 uint64_t bc_unneeded=branch_regs[i].u;
5955 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5956 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5957 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5959 bc_unneeded_upper|=1;
5960 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5961 bc_unneeded,bc_unneeded_upper);
5962 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5963 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5964 cc=get_reg(branch_regs[i].regmap,CCREG);
5965 assert(cc==HOST_CCREG);
5966 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5967 assem_debug("cycle count (adj)\n");
5970 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5973 emit_testimm(fs,0x800000);
5974 if(source[i]&0x10000) // BC1T
5980 add_to_linker((int)out,ba[i],internal);
5989 add_to_linker((int)out,ba[i],internal);
5997 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5998 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5999 else if(match) emit_addnop(13);
6001 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6002 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6004 assem_debug("branch: internal\n");
6006 assem_debug("branch: external\n");
6007 if(internal&&is_ds[(ba[i]-start)>>2]) {
6008 ds_assemble_entry(i);
6011 add_to_linker((int)out,ba[i],internal);
6014 set_jump_target(nottaken,(int)out);
6018 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
6020 } // (!unconditional)
6024 // In-order execution (branch first)
6028 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6031 emit_testimm(fs,0x800000);
6032 if(source[i]&0x10000) // BC1T
6043 } // if(!unconditional)
6045 uint64_t ds_unneeded=branch_regs[i].u;
6046 uint64_t ds_unneeded_upper=branch_regs[i].uu;
6047 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6048 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6049 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6051 ds_unneeded_upper|=1;
6053 //assem_debug("1:\n");
6054 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6055 ds_unneeded,ds_unneeded_upper);
6057 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6058 address_generation(i+1,&branch_regs[i],0);
6059 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6060 ds_assemble(i+1,&branch_regs[i]);
6061 cc=get_reg(branch_regs[i].regmap,CCREG);
6063 emit_loadreg(CCREG,cc=HOST_CCREG);
6064 // CHECK: Is the following instruction (fall thru) allocated ok?
6066 assert(cc==HOST_CCREG);
6067 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6068 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6069 assem_debug("cycle count (adj)\n");
6070 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6071 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6073 assem_debug("branch: internal\n");
6075 assem_debug("branch: external\n");
6076 if(internal&&is_ds[(ba[i]-start)>>2]) {
6077 ds_assemble_entry(i);
6080 add_to_linker((int)out,ba[i],internal);
6085 if(1) { // <- FIXME (don't need this)
6086 set_jump_target(nottaken,(int)out);
6087 assem_debug("1:\n");
6089 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6090 ds_unneeded,ds_unneeded_upper);
6091 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6092 address_generation(i+1,&branch_regs[i],0);
6093 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6094 ds_assemble(i+1,&branch_regs[i]);
6096 cc=get_reg(branch_regs[i].regmap,CCREG);
6097 if(cc==-1&&!likely[i]) {
6098 // Cycle count isn't in a register, temporarily load it then write it out
6099 emit_loadreg(CCREG,HOST_CCREG);
6100 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6103 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6104 emit_storereg(CCREG,HOST_CCREG);
6107 cc=get_reg(i_regmap,CCREG);
6108 assert(cc==HOST_CCREG);
6109 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
6112 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6118 static void pagespan_assemble(int i,struct regstat *i_regs)
6120 int s1l=get_reg(i_regs->regmap,rs1[i]);
6121 int s1h=get_reg(i_regs->regmap,rs1[i]|64);
6122 int s2l=get_reg(i_regs->regmap,rs2[i]);
6123 int s2h=get_reg(i_regs->regmap,rs2[i]|64);
6124 void *nt_branch=NULL;
6127 int unconditional=0;
6137 if((i_regs->is32>>rs1[i])&(i_regs->is32>>rs2[i])&1) {
6141 int addr,alt,ntaddr;
6142 if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
6146 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
6147 (i_regs->regmap[hr]&63)!=rs1[i] &&
6148 (i_regs->regmap[hr]&63)!=rs2[i] )
6157 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6158 (i_regs->regmap[hr]&63)!=rs1[i] &&
6159 (i_regs->regmap[hr]&63)!=rs2[i] )
6165 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
6169 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6170 (i_regs->regmap[hr]&63)!=rs1[i] &&
6171 (i_regs->regmap[hr]&63)!=rs2[i] )
6178 assert(hr<HOST_REGS);
6179 if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
6180 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
6182 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6183 if(opcode[i]==2) // J
6187 if(opcode[i]==3) // JAL
6190 int rt=get_reg(i_regs->regmap,31);
6191 emit_movimm(start+i*4+8,rt);
6194 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
6197 if(opcode2[i]==9) // JALR
6199 int rt=get_reg(i_regs->regmap,31);
6200 emit_movimm(start+i*4+8,rt);
6203 if((opcode[i]&0x3f)==4) // BEQ
6210 #ifdef HAVE_CMOV_IMM
6212 if(s2l>=0) emit_cmp(s1l,s2l);
6213 else emit_test(s1l,s1l);
6214 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
6220 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6222 if(s2h>=0) emit_cmp(s1h,s2h);
6223 else emit_test(s1h,s1h);
6224 emit_cmovne_reg(alt,addr);
6226 if(s2l>=0) emit_cmp(s1l,s2l);
6227 else emit_test(s1l,s1l);
6228 emit_cmovne_reg(alt,addr);
6231 if((opcode[i]&0x3f)==5) // BNE
6233 #ifdef HAVE_CMOV_IMM
6235 if(s2l>=0) emit_cmp(s1l,s2l);
6236 else emit_test(s1l,s1l);
6237 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
6243 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
6245 if(s2h>=0) emit_cmp(s1h,s2h);
6246 else emit_test(s1h,s1h);
6247 emit_cmovne_reg(alt,addr);
6249 if(s2l>=0) emit_cmp(s1l,s2l);
6250 else emit_test(s1l,s1l);
6251 emit_cmovne_reg(alt,addr);
6254 if((opcode[i]&0x3f)==0x14) // BEQL
6257 if(s2h>=0) emit_cmp(s1h,s2h);
6258 else emit_test(s1h,s1h);
6262 if(s2l>=0) emit_cmp(s1l,s2l);
6263 else emit_test(s1l,s1l);
6264 if(nottaken) set_jump_target(nottaken,(int)out);
6268 if((opcode[i]&0x3f)==0x15) // BNEL
6271 if(s2h>=0) emit_cmp(s1h,s2h);
6272 else emit_test(s1h,s1h);
6276 if(s2l>=0) emit_cmp(s1l,s2l);
6277 else emit_test(s1l,s1l);
6280 if(taken) set_jump_target(taken,(int)out);
6282 if((opcode[i]&0x3f)==6) // BLEZ
6284 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6286 if(s1h>=0) emit_mov(addr,ntaddr);
6287 emit_cmovl_reg(alt,addr);
6290 emit_cmovne_reg(ntaddr,addr);
6291 emit_cmovs_reg(alt,addr);
6294 if((opcode[i]&0x3f)==7) // BGTZ
6296 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
6298 if(s1h>=0) emit_mov(addr,alt);
6299 emit_cmovl_reg(ntaddr,addr);
6302 emit_cmovne_reg(alt,addr);
6303 emit_cmovs_reg(ntaddr,addr);
6306 if((opcode[i]&0x3f)==0x16) // BLEZL
6308 assert((opcode[i]&0x3f)!=0x16);
6310 if((opcode[i]&0x3f)==0x17) // BGTZL
6312 assert((opcode[i]&0x3f)!=0x17);
6314 assert(opcode[i]!=1); // BLTZ/BGEZ
6316 //FIXME: Check CSREG
6317 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
6318 if((source[i]&0x30000)==0) // BC1F
6320 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6321 emit_testimm(s1l,0x800000);
6322 emit_cmovne_reg(alt,addr);
6324 if((source[i]&0x30000)==0x10000) // BC1T
6326 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6327 emit_testimm(s1l,0x800000);
6328 emit_cmovne_reg(alt,addr);
6330 if((source[i]&0x30000)==0x20000) // BC1FL
6332 emit_testimm(s1l,0x800000);
6336 if((source[i]&0x30000)==0x30000) // BC1TL
6338 emit_testimm(s1l,0x800000);
6344 assert(i_regs->regmap[HOST_CCREG]==CCREG);
6345 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6346 if(likely[i]||unconditional)
6348 emit_movimm(ba[i],HOST_BTREG);
6350 else if(addr!=HOST_BTREG)
6352 emit_mov(addr,HOST_BTREG);
6354 void *branch_addr=out;
6356 int target_addr=start+i*4+5;
6358 void *compiled_target_addr=check_addr(target_addr);
6359 emit_extjump_ds((int)branch_addr,target_addr);
6360 if(compiled_target_addr) {
6361 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6362 add_link(target_addr,stub);
6364 else set_jump_target((int)branch_addr,(int)stub);
6367 set_jump_target((int)nottaken,(int)out);
6368 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6369 void *branch_addr=out;
6371 int target_addr=start+i*4+8;
6373 void *compiled_target_addr=check_addr(target_addr);
6374 emit_extjump_ds((int)branch_addr,target_addr);
6375 if(compiled_target_addr) {
6376 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6377 add_link(target_addr,stub);
6379 else set_jump_target((int)branch_addr,(int)stub);
6383 // Assemble the delay slot for the above
6384 static void pagespan_ds()
6386 assem_debug("initial delay slot:\n");
6387 u_int vaddr=start+1;
6388 u_int page=get_page(vaddr);
6389 u_int vpage=get_vpage(vaddr);
6390 ll_add(jump_dirty+vpage,vaddr,(void *)out);
6392 ll_add(jump_in+page,vaddr,(void *)out);
6393 assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6394 if(regs[0].regmap[HOST_CCREG]!=CCREG)
6395 wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty,regs[0].was32);
6396 if(regs[0].regmap[HOST_BTREG]!=BTREG)
6397 emit_writeword(HOST_BTREG,(int)&branch_target);
6398 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,rs1[0],rs2[0]);
6399 address_generation(0,®s[0],regs[0].regmap_entry);
6400 if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39||(opcode[0]&0x3b)==0x3a)
6401 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,INVCP,INVCP);
6406 alu_assemble(0,®s[0]);break;
6408 imm16_assemble(0,®s[0]);break;
6410 shift_assemble(0,®s[0]);break;
6412 shiftimm_assemble(0,®s[0]);break;
6414 load_assemble(0,®s[0]);break;
6416 loadlr_assemble(0,®s[0]);break;
6418 store_assemble(0,®s[0]);break;
6420 storelr_assemble(0,®s[0]);break;
6422 cop0_assemble(0,®s[0]);break;
6424 cop1_assemble(0,®s[0]);break;
6426 c1ls_assemble(0,®s[0]);break;
6428 cop2_assemble(0,®s[0]);break;
6430 c2ls_assemble(0,®s[0]);break;
6432 c2op_assemble(0,®s[0]);break;
6434 fconv_assemble(0,®s[0]);break;
6436 float_assemble(0,®s[0]);break;
6438 fcomp_assemble(0,®s[0]);break;
6440 multdiv_assemble(0,®s[0]);break;
6442 mov_assemble(0,®s[0]);break;
6451 printf("Jump in the delay slot. This is probably a bug.\n");
6453 int btaddr=get_reg(regs[0].regmap,BTREG);
6455 btaddr=get_reg(regs[0].regmap,-1);
6456 emit_readword((int)&branch_target,btaddr);
6458 assert(btaddr!=HOST_CCREG);
6459 if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6461 emit_movimm(start+4,HOST_TEMPREG);
6462 emit_cmp(btaddr,HOST_TEMPREG);
6464 emit_cmpimm(btaddr,start+4);
6466 int branch=(int)out;
6468 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,-1);
6469 emit_jmp(jump_vaddr_reg[btaddr]);
6470 set_jump_target(branch,(int)out);
6471 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6472 load_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6475 // Basic liveness analysis for MIPS registers
6476 void unneeded_registers(int istart,int iend,int r)
6480 uint64_t temp_u,temp_uu;
6485 u=unneeded_reg[iend+1];
6486 uu=unneeded_reg_upper[iend+1];
6489 for (i=iend;i>=istart;i--)
6491 //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
6492 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6494 // If subroutine call, flag return address as a possible branch target
6495 if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
6497 if(ba[i]<start || ba[i]>=(start+slen*4))
6499 // Branch out of this block, flush all regs
6503 if(itype[i]==UJUMP&&rt1[i]==31)
6505 uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
6507 if(itype[i]==RJUMP&&rs1[i]==31)
6509 uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9
6511 if(start>0x80000400&&start<0x80800000) {
6512 if(itype[i]==UJUMP&&rt1[i]==31)
6514 //uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi
6515 uu=u=0x300FF0F; // Discard at, v0-v1, t0-t9
6517 if(itype[i]==RJUMP&&rs1[i]==31)
6519 //uu=u=0x30300FFF3LL; // Discard at, a0-a3, t0-t9, lo, hi
6520 uu=u=0x300FFF3; // Discard at, a0-a3, t0-t9
6523 branch_unneeded_reg[i]=u;
6524 branch_unneeded_reg_upper[i]=uu;
6525 // Merge in delay slot
6526 tdep=(~uu>>rt1[i+1])&1;
6527 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6528 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6529 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6530 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6531 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6533 // If branch is "likely" (and conditional)
6534 // then we skip the delay slot on the fall-thru path
6537 u&=unneeded_reg[i+2];
6538 uu&=unneeded_reg_upper[i+2];
6549 // Internal branch, flag target
6550 bt[(ba[i]-start)>>2]=1;
6551 if(ba[i]<=start+i*4) {
6553 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6555 // Unconditional branch
6558 // Conditional branch (not taken case)
6559 temp_u=unneeded_reg[i+2];
6560 temp_uu=unneeded_reg_upper[i+2];
6562 // Merge in delay slot
6563 tdep=(~temp_uu>>rt1[i+1])&1;
6564 temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6565 temp_uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6566 temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6567 temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6568 temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6569 temp_u|=1;temp_uu|=1;
6570 // If branch is "likely" (and conditional)
6571 // then we skip the delay slot on the fall-thru path
6574 temp_u&=unneeded_reg[i+2];
6575 temp_uu&=unneeded_reg_upper[i+2];
6583 tdep=(~temp_uu>>rt1[i])&1;
6584 temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6585 temp_uu|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6586 temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6587 temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
6588 temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i]));
6589 temp_u|=1;temp_uu|=1;
6590 unneeded_reg[i]=temp_u;
6591 unneeded_reg_upper[i]=temp_uu;
6592 // Only go three levels deep. This recursion can take an
6593 // excessive amount of time if there are a lot of nested loops.
6595 unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6597 unneeded_reg[(ba[i]-start)>>2]=1;
6598 unneeded_reg_upper[(ba[i]-start)>>2]=1;
6601 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6603 // Unconditional branch
6604 u=unneeded_reg[(ba[i]-start)>>2];
6605 uu=unneeded_reg_upper[(ba[i]-start)>>2];
6606 branch_unneeded_reg[i]=u;
6607 branch_unneeded_reg_upper[i]=uu;
6610 //branch_unneeded_reg[i]=u;
6611 //branch_unneeded_reg_upper[i]=uu;
6612 // Merge in delay slot
6613 tdep=(~uu>>rt1[i+1])&1;
6614 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6615 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6616 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6617 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6618 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6621 // Conditional branch
6622 b=unneeded_reg[(ba[i]-start)>>2];
6623 bu=unneeded_reg_upper[(ba[i]-start)>>2];
6624 branch_unneeded_reg[i]=b;
6625 branch_unneeded_reg_upper[i]=bu;
6628 //branch_unneeded_reg[i]=b;
6629 //branch_unneeded_reg_upper[i]=bu;
6630 // Branch delay slot
6631 tdep=(~uu>>rt1[i+1])&1;
6632 b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6633 bu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6634 b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6635 bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6636 bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6638 // If branch is "likely" then we skip the
6639 // delay slot on the fall-thru path
6644 u&=unneeded_reg[i+2];
6645 uu&=unneeded_reg_upper[i+2];
6656 branch_unneeded_reg[i]&=unneeded_reg[i+2];
6657 branch_unneeded_reg_upper[i]&=unneeded_reg_upper[i+2];
6658 //branch_unneeded_reg[i]=1;
6659 //branch_unneeded_reg_upper[i]=1;
6661 branch_unneeded_reg[i]=1;
6662 branch_unneeded_reg_upper[i]=1;
6668 else if(itype[i]==SYSCALL||itype[i]==HLECALL)
6670 // SYSCALL instruction (software interrupt)
6674 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
6676 // ERET instruction (return from interrupt)
6681 tdep=(~uu>>rt1[i])&1;
6682 // Written registers are unneeded
6687 // Accessed registers are needed
6692 // Source-target dependencies
6693 uu&=~(tdep<<dep1[i]);
6694 uu&=~(tdep<<dep2[i]);
6695 // R0 is always unneeded
6699 unneeded_reg_upper[i]=uu;
6701 unneeded_reg_upper[i]=-1LL;
6704 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
6707 for(r=1;r<=CCREG;r++) {
6708 if((unneeded_reg[i]>>r)&1) {
6709 if(r==HIREG) printf(" HI");
6710 else if(r==LOREG) printf(" LO");
6711 else printf(" r%d",r);
6715 for(r=1;r<=CCREG;r++) {
6716 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
6717 if(r==HIREG) printf(" HI");
6718 else if(r==LOREG) printf(" LO");
6719 else printf(" r%d",r);
6726 // Identify registers which are likely to contain 32-bit values
6727 // This is used to predict whether any branches will jump to a
6728 // location with 64-bit values in registers.
6729 static void provisional_32bit()
6733 uint64_t lastbranch=1;
6738 if(itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) {
6739 if(i>1) is32=lastbranch;
6745 if(itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP) {
6747 if(i>2) is32=lastbranch;
6751 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
6753 if(rs1[i-2]==0||rs2[i-2]==0)
6756 is32|=1LL<<rs1[i-2];
6759 is32|=1LL<<rs2[i-2];
6764 // If something jumps here with 64-bit values
6765 // then promote those registers to 64 bits
6768 uint64_t temp_is32=is32;
6771 if(ba[j]==start+i*4)
6772 //temp_is32&=branch_regs[j].is32;
6777 if(ba[j]==start+i*4)
6788 if(type==UJUMP||type==RJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
6789 // Branches don't write registers, consider the delay slot instead.
6800 if(opcode[i]==0x27||opcode[i]==0x37|| // LWU/LD
6801 opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
6810 if(op==0x1a||op==0x1b) is32&=~(1LL<<rt); // LDR/LDL
6811 if(op==0x22) is32|=1LL<<rt; // LWL
6814 if (op==0x08||op==0x09|| // ADDI/ADDIU
6815 op==0x0a||op==0x0b|| // SLTI/SLTIU
6821 if(op==0x18||op==0x19) { // DADDI/DADDIU
6824 // is32|=((is32>>s1)&1LL)<<rt;
6826 if(op==0x0d||op==0x0e) { // ORI/XORI
6827 uint64_t sr=((is32>>s1)&1LL);
6843 if(op2>=0x20&&op2<=0x23) { // ADD/ADDU/SUB/SUBU
6846 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
6849 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
6850 uint64_t sr=((is32>>s1)&(is32>>s2)&1LL);
6854 else if(op2>=0x2c&&op2<=0x2d) { // DADD/DADDU
6859 uint64_t sr=((is32>>s1)&1LL);
6864 uint64_t sr=((is32>>s2)&1LL);
6872 else if(op2>=0x2e&&op2<=0x2f) { // DSUB/DSUBU
6877 uint64_t sr=((is32>>s1)&1LL);
6887 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
6888 is32&=~((1LL<<HIREG)|(1LL<<LOREG));
6891 is32|=(1LL<<HIREG)|(1LL<<LOREG);
6896 uint64_t sr=((is32>>s1)&1LL);
6902 if(op2>=0x14&&op2<=0x17) is32&=~(1LL<<rt); // DSLLV/DSRLV/DSRAV
6903 else is32|=1LL<<rt; // SLLV/SRLV/SRAV
6907 // DSLL/DSRL/DSRA/DSLL32/DSRL32 but not DSRA32 have 64-bit result
6908 if(op2>=0x38&&op2<0x3f) is32&=~(1LL<<rt);
6911 if(op2==0) is32|=1LL<<rt; // MFC0
6915 if(op2==0) is32|=1LL<<rt; // MFC1
6916 if(op2==1) is32&=~(1LL<<rt); // DMFC1
6917 if(op2==2) is32|=1LL<<rt; // CFC1
6939 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
6941 if(rt1[i-1]==31) // JAL/JALR
6943 // Subroutine call will return here, don't alloc any registers
6948 // Internal branch will jump here, match registers to caller
6956 // Identify registers which may be assumed to contain 32-bit values
6957 // and where optimizations will rely on this.
6958 // This is used to determine whether backward branches can safely
6959 // jump to a location with 64-bit values in registers.
6960 static void provisional_r32()
6965 for (i=slen-1;i>=0;i--)
6968 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6970 if(ba[i]<start || ba[i]>=(start+slen*4))
6972 // Branch out of this block, don't need anything
6978 // Need whatever matches the target
6979 // (and doesn't get overwritten by the delay slot instruction)
6981 int t=(ba[i]-start)>>2;
6982 if(ba[i]>start+i*4) {
6984 //if(!(requires_32bit[t]&~regs[i].was32))
6985 // r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
6986 if(!(pr32[t]&~regs[i].was32))
6987 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
6990 if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
6991 r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
6994 // Conditional branch may need registers for following instructions
6995 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
6998 //r32|=requires_32bit[i+2];
7001 // Mark this address as a branch target since it may be called
7002 // upon return from interrupt
7006 // Merge in delay slot
7008 // These are overwritten unless the branch is "likely"
7009 // and the delay slot is nullified if not taken
7010 r32&=~(1LL<<rt1[i+1]);
7011 r32&=~(1LL<<rt2[i+1]);
7013 // Assume these are needed (delay slot)
7016 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
7020 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
7022 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
7024 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
7026 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
7028 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
7031 else if(itype[i]==SYSCALL||itype[i]==HLECALL)
7033 // SYSCALL instruction (software interrupt)
7036 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7038 // ERET instruction (return from interrupt)
7042 r32&=~(1LL<<rt1[i]);
7043 r32&=~(1LL<<rt2[i]);
7046 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
7050 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
7052 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
7054 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
7056 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
7058 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
7060 //requires_32bit[i]=r32;
7063 // Dirty registers which are 32-bit, require 32-bit input
7064 // as they will be written as 32-bit values
7065 for(hr=0;hr<HOST_REGS;hr++)
7067 if(regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64) {
7068 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
7069 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
7070 pr32[i]|=1LL<<regs[i].regmap_entry[hr];
7071 //requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
7078 // Write back dirty registers as soon as we will no longer modify them,
7079 // so that we don't end up with lots of writes at the branches.
7080 void clean_registers(int istart,int iend,int wr)
7084 u_int will_dirty_i,will_dirty_next,temp_will_dirty;
7085 u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
7087 will_dirty_i=will_dirty_next=0;
7088 wont_dirty_i=wont_dirty_next=0;
7090 will_dirty_i=will_dirty_next=will_dirty[iend+1];
7091 wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
7093 for (i=iend;i>=istart;i--)
7095 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7097 if(ba[i]<start || ba[i]>=(start+slen*4))
7099 // Branch out of this block, flush all regs
7100 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7102 // Unconditional branch
7105 // Merge in delay slot (will dirty)
7106 for(r=0;r<HOST_REGS;r++) {
7107 if(r!=EXCLUDE_REG) {
7108 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7109 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7110 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7111 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7112 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7113 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7114 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7115 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7116 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7117 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7118 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7119 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7120 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7121 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7127 // Conditional branch
7129 wont_dirty_i=wont_dirty_next;
7130 // Merge in delay slot (will dirty)
7131 for(r=0;r<HOST_REGS;r++) {
7132 if(r!=EXCLUDE_REG) {
7134 // Might not dirty if likely branch is not taken
7135 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7136 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7137 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7138 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7139 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7140 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
7141 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7142 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7143 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7144 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7145 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7146 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7147 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7148 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7153 // Merge in delay slot (wont dirty)
7154 for(r=0;r<HOST_REGS;r++) {
7155 if(r!=EXCLUDE_REG) {
7156 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7157 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7158 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7159 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7160 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7161 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7162 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7163 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7164 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7165 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7169 #ifndef DESTRUCTIVE_WRITEBACK
7170 branch_regs[i].dirty&=wont_dirty_i;
7172 branch_regs[i].dirty|=will_dirty_i;
7178 if(ba[i]<=start+i*4) {
7180 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7182 // Unconditional branch
7185 // Merge in delay slot (will dirty)
7186 for(r=0;r<HOST_REGS;r++) {
7187 if(r!=EXCLUDE_REG) {
7188 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7189 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7190 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7191 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7192 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7193 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7194 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7195 if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7196 if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7197 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7198 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7199 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7200 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7201 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7205 // Conditional branch (not taken case)
7206 temp_will_dirty=will_dirty_next;
7207 temp_wont_dirty=wont_dirty_next;
7208 // Merge in delay slot (will dirty)
7209 for(r=0;r<HOST_REGS;r++) {
7210 if(r!=EXCLUDE_REG) {
7212 // Will not dirty if likely branch is not taken
7213 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7214 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7215 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7216 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7217 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7218 if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
7219 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7220 //if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7221 //if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7222 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7223 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7224 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7225 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7226 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7231 // Merge in delay slot (wont dirty)
7232 for(r=0;r<HOST_REGS;r++) {
7233 if(r!=EXCLUDE_REG) {
7234 if((regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7235 if((regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7236 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7237 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7238 if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7239 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7240 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7241 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7242 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7243 if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7246 // Deal with changed mappings
7248 for(r=0;r<HOST_REGS;r++) {
7249 if(r!=EXCLUDE_REG) {
7250 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
7251 temp_will_dirty&=~(1<<r);
7252 temp_wont_dirty&=~(1<<r);
7253 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7254 temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7255 temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7257 temp_will_dirty|=1<<r;
7258 temp_wont_dirty|=1<<r;
7265 will_dirty[i]=temp_will_dirty;
7266 wont_dirty[i]=temp_wont_dirty;
7267 clean_registers((ba[i]-start)>>2,i-1,0);
7269 // Limit recursion. It can take an excessive amount
7270 // of time if there are a lot of nested loops.
7271 will_dirty[(ba[i]-start)>>2]=0;
7272 wont_dirty[(ba[i]-start)>>2]=-1;
7277 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7279 // Unconditional branch
7282 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7283 for(r=0;r<HOST_REGS;r++) {
7284 if(r!=EXCLUDE_REG) {
7285 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7286 will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
7287 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7292 // Merge in delay slot
7293 for(r=0;r<HOST_REGS;r++) {
7294 if(r!=EXCLUDE_REG) {
7295 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7296 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7297 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7298 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7299 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7300 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7301 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7302 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7303 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7304 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7305 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7306 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7307 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7308 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7312 // Conditional branch
7313 will_dirty_i=will_dirty_next;
7314 wont_dirty_i=wont_dirty_next;
7315 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7316 for(r=0;r<HOST_REGS;r++) {
7317 if(r!=EXCLUDE_REG) {
7318 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7319 will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7320 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7324 will_dirty_i&=~(1<<r);
7326 // Treat delay slot as part of branch too
7327 /*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7328 will_dirty[i+1]&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7329 wont_dirty[i+1]|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7333 will_dirty[i+1]&=~(1<<r);
7338 // Merge in delay slot
7339 for(r=0;r<HOST_REGS;r++) {
7340 if(r!=EXCLUDE_REG) {
7342 // Might not dirty if likely branch is not taken
7343 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7344 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7345 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7346 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7347 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7348 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7349 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7350 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7351 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7352 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7353 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7354 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7355 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7356 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7361 // Merge in delay slot
7362 for(r=0;r<HOST_REGS;r++) {
7363 if(r!=EXCLUDE_REG) {
7364 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7365 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7366 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7367 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7368 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7369 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7370 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7371 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7372 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7373 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7377 #ifndef DESTRUCTIVE_WRITEBACK
7378 branch_regs[i].dirty&=wont_dirty_i;
7380 branch_regs[i].dirty|=will_dirty_i;
7385 else if(itype[i]==SYSCALL||itype[i]==HLECALL)
7387 // SYSCALL instruction (software interrupt)
7391 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7393 // ERET instruction (return from interrupt)
7397 will_dirty_next=will_dirty_i;
7398 wont_dirty_next=wont_dirty_i;
7399 for(r=0;r<HOST_REGS;r++) {
7400 if(r!=EXCLUDE_REG) {
7401 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7402 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7403 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7404 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7405 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7406 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7407 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7408 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7410 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
7412 // Don't store a register immediately after writing it,
7413 // may prevent dual-issue.
7414 if((regs[i].regmap[r]&63)==rt1[i-1]) wont_dirty_i|=1<<r;
7415 if((regs[i].regmap[r]&63)==rt2[i-1]) wont_dirty_i|=1<<r;
7421 will_dirty[i]=will_dirty_i;
7422 wont_dirty[i]=wont_dirty_i;
7423 // Mark registers that won't be dirtied as not dirty
7425 /*printf("wr (%d,%d) %x will:",istart,iend,start+i*4);
7426 for(r=0;r<HOST_REGS;r++) {
7427 if((will_dirty_i>>r)&1) {
7433 //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=FJUMP)) {
7434 regs[i].dirty|=will_dirty_i;
7435 #ifndef DESTRUCTIVE_WRITEBACK
7436 regs[i].dirty&=wont_dirty_i;
7437 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7439 if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
7440 for(r=0;r<HOST_REGS;r++) {
7441 if(r!=EXCLUDE_REG) {
7442 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
7443 regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
7444 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7452 for(r=0;r<HOST_REGS;r++) {
7453 if(r!=EXCLUDE_REG) {
7454 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
7455 regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
7456 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7464 // Deal with changed mappings
7465 temp_will_dirty=will_dirty_i;
7466 temp_wont_dirty=wont_dirty_i;
7467 for(r=0;r<HOST_REGS;r++) {
7468 if(r!=EXCLUDE_REG) {
7470 if(regs[i].regmap[r]==regmap_pre[i][r]) {
7472 #ifndef DESTRUCTIVE_WRITEBACK
7473 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7475 regs[i].wasdirty|=will_dirty_i&(1<<r);
7478 else if((nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
7479 // Register moved to a different register
7480 will_dirty_i&=~(1<<r);
7481 wont_dirty_i&=~(1<<r);
7482 will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
7483 wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
7485 #ifndef DESTRUCTIVE_WRITEBACK
7486 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7488 regs[i].wasdirty|=will_dirty_i&(1<<r);
7492 will_dirty_i&=~(1<<r);
7493 wont_dirty_i&=~(1<<r);
7494 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7495 will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7496 wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7499 /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);/*assert(!((will_dirty>>r)&1));*/
7508 void disassemble_inst(int i)
7510 if (bt[i]) printf("*"); else printf(" ");
7513 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7515 printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
7517 printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
7519 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7521 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);break;
7523 printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break;
7525 if(opcode[i]==0xf) //LUI
7526 printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],rt1[i],imm[i]&0xffff);
7528 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7532 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7536 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rs2[i],rs1[i],imm[i]);
7540 printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i],rs2[i]);
7543 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rs1[i],rs2[i]);
7546 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7549 if((opcode2[i]&0x1d)==0x10)
7550 printf (" %x: %s r%d\n",start+i*4,insn[i],rt1[i]);
7551 else if((opcode2[i]&0x1d)==0x11)
7552 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7554 printf (" %x: %s\n",start+i*4,insn[i]);
7558 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC0
7559 else if(opcode2[i]==4)
7560 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC0
7561 else printf (" %x: %s\n",start+i*4,insn[i]);
7565 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC1
7566 else if(opcode2[i]>3)
7567 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC1
7568 else printf (" %x: %s\n",start+i*4,insn[i]);
7572 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC2
7573 else if(opcode2[i]>3)
7574 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC2
7575 else printf (" %x: %s\n",start+i*4,insn[i]);
7578 printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7581 printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7584 //printf (" %s %8x\n",insn[i],source[i]);
7585 printf (" %x: %s\n",start+i*4,insn[i]);
7589 void new_dynarec_init()
7591 printf("Init new dynarec\n");
7592 out=(u_char *)BASE_ADDR;
7593 if (mmap (out, 1<<TARGET_SIZE_2,
7594 PROT_READ | PROT_WRITE | PROT_EXEC,
7595 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
7596 -1, 0) <= 0) {printf("mmap() failed\n");}
7598 rdword=&readmem_dword;
7599 fake_pc.f.r.rs=&readmem_dword;
7600 fake_pc.f.r.rt=&readmem_dword;
7601 fake_pc.f.r.rd=&readmem_dword;
7604 for(n=0x80000;n<0x80800;n++)
7606 for(n=0;n<65536;n++)
7607 hash_table[n][0]=hash_table[n][2]=-1;
7608 memset(mini_ht,-1,sizeof(mini_ht));
7609 memset(restore_candidate,0,sizeof(restore_candidate));
7611 expirep=16384; // Expiry pointer, +2 blocks
7612 pending_exception=0;
7615 // Copy this into local area so we don't have to put it in every literal pool
7616 invc_ptr=invalid_code;
7621 for(n=0;n<524288;n++) // 0 .. 0x7FFFFFFF
7623 for(n=524288;n<526336;n++) // 0x80000000 .. 0x807FFFFF
7624 memory_map[n]=((u_int)rdram-0x80000000)>>2;
7625 for(n=526336;n<1048576;n++) // 0x80800000 .. 0xFFFFFFFF
7628 for(n=0;n<0x8000;n++) { // 0 .. 0x7FFFFFFF
7629 writemem[n] = write_nomem_new;
7630 writememb[n] = write_nomemb_new;
7631 writememh[n] = write_nomemh_new;
7633 writememd[n] = write_nomemd_new;
7635 readmem[n] = read_nomem_new;
7636 readmemb[n] = read_nomemb_new;
7637 readmemh[n] = read_nomemh_new;
7639 readmemd[n] = read_nomemd_new;
7642 for(n=0x8000;n<0x8080;n++) { // 0x80000000 .. 0x807FFFFF
7643 writemem[n] = write_rdram_new;
7644 writememb[n] = write_rdramb_new;
7645 writememh[n] = write_rdramh_new;
7647 writememd[n] = write_rdramd_new;
7650 for(n=0xC000;n<0x10000;n++) { // 0xC0000000 .. 0xFFFFFFFF
7651 writemem[n] = write_nomem_new;
7652 writememb[n] = write_nomemb_new;
7653 writememh[n] = write_nomemh_new;
7655 writememd[n] = write_nomemd_new;
7657 readmem[n] = read_nomem_new;
7658 readmemb[n] = read_nomemb_new;
7659 readmemh[n] = read_nomemh_new;
7661 readmemd[n] = read_nomemd_new;
7669 void new_dynarec_cleanup()
7672 if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0) {printf("munmap() failed\n");}
7673 for(n=0;n<4096;n++) ll_clear(jump_in+n);
7674 for(n=0;n<4096;n++) ll_clear(jump_out+n);
7675 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7677 if (munmap (ROM_COPY, 67108864) < 0) {printf("munmap() failed\n");}
7681 int new_recompile_block(int addr)
7684 if(addr==0x800cd050) {
7686 for(block=0x80000;block<0x80800;block++) invalidate_block(block);
7688 for(n=0;n<=2048;n++) ll_clear(jump_dirty+n);
7691 //if(Count==365117028) tracedebug=1;
7692 assem_debug("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7693 //printf("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7694 //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
7696 //printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
7697 //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
7698 /*if(Count>=312978186) {
7702 start = (u_int)addr&~3;
7703 //assert(((u_int)addr&1)==0);
7705 if (Config.HLE && start == 0x80001000) {
7706 // XXX: is this enough? Maybe check hleSoftCall?
7707 u_int page=get_page(start);
7708 ll_add(jump_in+page,start,out);
7709 invalid_code[start>>12]=0;
7710 emit_movimm(start,0);
7711 emit_writeword(0,(int)&pcaddr);
7712 emit_jmp((int)new_dyna_leave); // enough??
7715 else if ((u_int)addr < 0x00200000) {
7716 // used for BIOS calls mostly?
7717 source = (u_int *)((u_int)rdram+start-0);
7718 pagelimit = 0x00200000;
7723 if ((int)addr >= 0xa4000000 && (int)addr < 0xa4001000) {
7724 source = (u_int *)((u_int)SP_DMEM+start-0xa4000000);
7725 pagelimit = 0xa4001000;
7729 if ((int)addr >= 0x80000000 && (int)addr < 0x80800000) {
7730 source = (u_int *)((u_int)rdram+start-0x80000000);
7731 pagelimit = 0x80800000;
7734 else if ((signed int)addr >= (signed int)0xC0000000) {
7735 //printf("addr=%x mm=%x\n",(u_int)addr,(memory_map[start>>12]<<2));
7736 //if(tlb_LUT_r[start>>12])
7737 //source = (u_int *)(((int)rdram)+(tlb_LUT_r[start>>12]&0xFFFFF000)+(((int)addr)&0xFFF)-0x80000000);
7738 if((signed int)memory_map[start>>12]>=0) {
7739 source = (u_int *)((u_int)(start+(memory_map[start>>12]<<2)));
7740 pagelimit=(start+4096)&0xFFFFF000;
7741 int map=memory_map[start>>12];
7744 //printf("start: %x next: %x\n",map,memory_map[pagelimit>>12]);
7745 if((map&0xBFFFFFFF)==(memory_map[pagelimit>>12]&0xBFFFFFFF)) pagelimit+=4096;
7747 assem_debug("pagelimit=%x\n",pagelimit);
7748 assem_debug("mapping=%x (%x)\n",memory_map[start>>12],(memory_map[start>>12]<<2)+start);
7751 assem_debug("Compile at unmapped memory address: %x \n", (int)addr);
7752 //assem_debug("start: %x next: %x\n",memory_map[start>>12],memory_map[(start+4096)>>12]);
7753 return 1; // Caller will invoke exception handler
7755 //printf("source= %x\n",(int)source);
7759 printf("Compile at bogus memory address: %x \n", (int)addr);
7763 /* Pass 1: disassemble */
7764 /* Pass 2: register dependencies, branch targets */
7765 /* Pass 3: register allocation */
7766 /* Pass 4: branch dependencies */
7767 /* Pass 5: pre-alloc */
7768 /* Pass 6: optimize clean/dirty state */
7769 /* Pass 7: flag 32-bit registers */
7770 /* Pass 8: assembly */
7771 /* Pass 9: linker */
7772 /* Pass 10: garbage collection / free memory */
7776 unsigned int type,op,op2;
7778 //printf("addr = %x source = %x %x\n", addr,source,source[0]);
7780 /* Pass 1 disassembly */
7782 for(i=0;!done;i++) {
7783 bt[i]=0;likely[i]=0;op2=0;
7784 opcode[i]=op=source[i]>>26;
7787 case 0x00: strcpy(insn[i],"special"); type=NI;
7791 case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
7792 case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
7793 case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
7794 case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
7795 case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
7796 case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
7797 case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
7798 case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
7799 case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
7800 case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
7801 case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
7802 case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
7803 case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
7804 case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
7805 case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
7806 case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
7807 case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
7808 case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
7809 case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
7810 case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
7811 case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
7812 case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
7813 case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
7814 case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
7815 case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
7816 case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
7817 case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
7818 case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
7819 case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
7820 case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
7821 case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
7822 case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
7823 case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
7824 case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
7825 case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
7826 case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
7827 case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
7828 case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
7829 case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
7830 case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
7831 case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
7832 case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
7833 case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
7834 case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
7835 case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
7836 case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
7837 case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
7838 case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
7839 case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
7840 case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
7841 case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
7842 case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
7845 case 0x01: strcpy(insn[i],"regimm"); type=NI;
7846 op2=(source[i]>>16)&0x1f;
7849 case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
7850 case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
7851 case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
7852 case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
7853 case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
7854 case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
7855 case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
7856 case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
7857 case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
7858 case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
7859 case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
7860 case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
7861 case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
7862 case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
7865 case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
7866 case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
7867 case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
7868 case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
7869 case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
7870 case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
7871 case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
7872 case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
7873 case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
7874 case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
7875 case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
7876 case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
7877 case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
7878 case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
7879 case 0x10: strcpy(insn[i],"cop0"); type=NI;
7880 op2=(source[i]>>21)&0x1f;
7883 case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
7884 case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
7885 case 0x10: strcpy(insn[i],"tlb"); type=NI;
7886 switch(source[i]&0x3f)
7888 case 0x01: strcpy(insn[i],"TLBR"); type=COP0; break;
7889 case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break;
7890 case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break;
7891 case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break;
7892 case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
7896 case 0x11: strcpy(insn[i],"cop1"); type=NI;
7897 op2=(source[i]>>21)&0x1f;
7900 case 0x00: strcpy(insn[i],"MFC1"); type=COP1; break;
7901 case 0x01: strcpy(insn[i],"DMFC1"); type=COP1; break;
7902 case 0x02: strcpy(insn[i],"CFC1"); type=COP1; break;
7903 case 0x04: strcpy(insn[i],"MTC1"); type=COP1; break;
7904 case 0x05: strcpy(insn[i],"DMTC1"); type=COP1; break;
7905 case 0x06: strcpy(insn[i],"CTC1"); type=COP1; break;
7906 case 0x08: strcpy(insn[i],"BC1"); type=FJUMP;
7907 switch((source[i]>>16)&0x3)
7909 case 0x00: strcpy(insn[i],"BC1F"); break;
7910 case 0x01: strcpy(insn[i],"BC1T"); break;
7911 case 0x02: strcpy(insn[i],"BC1FL"); break;
7912 case 0x03: strcpy(insn[i],"BC1TL"); break;
7915 case 0x10: strcpy(insn[i],"C1.S"); type=NI;
7916 switch(source[i]&0x3f)
7918 case 0x00: strcpy(insn[i],"ADD.S"); type=FLOAT; break;
7919 case 0x01: strcpy(insn[i],"SUB.S"); type=FLOAT; break;
7920 case 0x02: strcpy(insn[i],"MUL.S"); type=FLOAT; break;
7921 case 0x03: strcpy(insn[i],"DIV.S"); type=FLOAT; break;
7922 case 0x04: strcpy(insn[i],"SQRT.S"); type=FLOAT; break;
7923 case 0x05: strcpy(insn[i],"ABS.S"); type=FLOAT; break;
7924 case 0x06: strcpy(insn[i],"MOV.S"); type=FLOAT; break;
7925 case 0x07: strcpy(insn[i],"NEG.S"); type=FLOAT; break;
7926 case 0x08: strcpy(insn[i],"ROUND.L.S"); type=FCONV; break;
7927 case 0x09: strcpy(insn[i],"TRUNC.L.S"); type=FCONV; break;
7928 case 0x0A: strcpy(insn[i],"CEIL.L.S"); type=FCONV; break;
7929 case 0x0B: strcpy(insn[i],"FLOOR.L.S"); type=FCONV; break;
7930 case 0x0C: strcpy(insn[i],"ROUND.W.S"); type=FCONV; break;
7931 case 0x0D: strcpy(insn[i],"TRUNC.W.S"); type=FCONV; break;
7932 case 0x0E: strcpy(insn[i],"CEIL.W.S"); type=FCONV; break;
7933 case 0x0F: strcpy(insn[i],"FLOOR.W.S"); type=FCONV; break;
7934 case 0x21: strcpy(insn[i],"CVT.D.S"); type=FCONV; break;
7935 case 0x24: strcpy(insn[i],"CVT.W.S"); type=FCONV; break;
7936 case 0x25: strcpy(insn[i],"CVT.L.S"); type=FCONV; break;
7937 case 0x30: strcpy(insn[i],"C.F.S"); type=FCOMP; break;
7938 case 0x31: strcpy(insn[i],"C.UN.S"); type=FCOMP; break;
7939 case 0x32: strcpy(insn[i],"C.EQ.S"); type=FCOMP; break;
7940 case 0x33: strcpy(insn[i],"C.UEQ.S"); type=FCOMP; break;
7941 case 0x34: strcpy(insn[i],"C.OLT.S"); type=FCOMP; break;
7942 case 0x35: strcpy(insn[i],"C.ULT.S"); type=FCOMP; break;
7943 case 0x36: strcpy(insn[i],"C.OLE.S"); type=FCOMP; break;
7944 case 0x37: strcpy(insn[i],"C.ULE.S"); type=FCOMP; break;
7945 case 0x38: strcpy(insn[i],"C.SF.S"); type=FCOMP; break;
7946 case 0x39: strcpy(insn[i],"C.NGLE.S"); type=FCOMP; break;
7947 case 0x3A: strcpy(insn[i],"C.SEQ.S"); type=FCOMP; break;
7948 case 0x3B: strcpy(insn[i],"C.NGL.S"); type=FCOMP; break;
7949 case 0x3C: strcpy(insn[i],"C.LT.S"); type=FCOMP; break;
7950 case 0x3D: strcpy(insn[i],"C.NGE.S"); type=FCOMP; break;
7951 case 0x3E: strcpy(insn[i],"C.LE.S"); type=FCOMP; break;
7952 case 0x3F: strcpy(insn[i],"C.NGT.S"); type=FCOMP; break;
7955 case 0x11: strcpy(insn[i],"C1.D"); type=NI;
7956 switch(source[i]&0x3f)
7958 case 0x00: strcpy(insn[i],"ADD.D"); type=FLOAT; break;
7959 case 0x01: strcpy(insn[i],"SUB.D"); type=FLOAT; break;
7960 case 0x02: strcpy(insn[i],"MUL.D"); type=FLOAT; break;
7961 case 0x03: strcpy(insn[i],"DIV.D"); type=FLOAT; break;
7962 case 0x04: strcpy(insn[i],"SQRT.D"); type=FLOAT; break;
7963 case 0x05: strcpy(insn[i],"ABS.D"); type=FLOAT; break;
7964 case 0x06: strcpy(insn[i],"MOV.D"); type=FLOAT; break;
7965 case 0x07: strcpy(insn[i],"NEG.D"); type=FLOAT; break;
7966 case 0x08: strcpy(insn[i],"ROUND.L.D"); type=FCONV; break;
7967 case 0x09: strcpy(insn[i],"TRUNC.L.D"); type=FCONV; break;
7968 case 0x0A: strcpy(insn[i],"CEIL.L.D"); type=FCONV; break;
7969 case 0x0B: strcpy(insn[i],"FLOOR.L.D"); type=FCONV; break;
7970 case 0x0C: strcpy(insn[i],"ROUND.W.D"); type=FCONV; break;
7971 case 0x0D: strcpy(insn[i],"TRUNC.W.D"); type=FCONV; break;
7972 case 0x0E: strcpy(insn[i],"CEIL.W.D"); type=FCONV; break;
7973 case 0x0F: strcpy(insn[i],"FLOOR.W.D"); type=FCONV; break;
7974 case 0x20: strcpy(insn[i],"CVT.S.D"); type=FCONV; break;
7975 case 0x24: strcpy(insn[i],"CVT.W.D"); type=FCONV; break;
7976 case 0x25: strcpy(insn[i],"CVT.L.D"); type=FCONV; break;
7977 case 0x30: strcpy(insn[i],"C.F.D"); type=FCOMP; break;
7978 case 0x31: strcpy(insn[i],"C.UN.D"); type=FCOMP; break;
7979 case 0x32: strcpy(insn[i],"C.EQ.D"); type=FCOMP; break;
7980 case 0x33: strcpy(insn[i],"C.UEQ.D"); type=FCOMP; break;
7981 case 0x34: strcpy(insn[i],"C.OLT.D"); type=FCOMP; break;
7982 case 0x35: strcpy(insn[i],"C.ULT.D"); type=FCOMP; break;
7983 case 0x36: strcpy(insn[i],"C.OLE.D"); type=FCOMP; break;
7984 case 0x37: strcpy(insn[i],"C.ULE.D"); type=FCOMP; break;
7985 case 0x38: strcpy(insn[i],"C.SF.D"); type=FCOMP; break;
7986 case 0x39: strcpy(insn[i],"C.NGLE.D"); type=FCOMP; break;
7987 case 0x3A: strcpy(insn[i],"C.SEQ.D"); type=FCOMP; break;
7988 case 0x3B: strcpy(insn[i],"C.NGL.D"); type=FCOMP; break;
7989 case 0x3C: strcpy(insn[i],"C.LT.D"); type=FCOMP; break;
7990 case 0x3D: strcpy(insn[i],"C.NGE.D"); type=FCOMP; break;
7991 case 0x3E: strcpy(insn[i],"C.LE.D"); type=FCOMP; break;
7992 case 0x3F: strcpy(insn[i],"C.NGT.D"); type=FCOMP; break;
7995 case 0x14: strcpy(insn[i],"C1.W"); type=NI;
7996 switch(source[i]&0x3f)
7998 case 0x20: strcpy(insn[i],"CVT.S.W"); type=FCONV; break;
7999 case 0x21: strcpy(insn[i],"CVT.D.W"); type=FCONV; break;
8002 case 0x15: strcpy(insn[i],"C1.L"); type=NI;
8003 switch(source[i]&0x3f)
8005 case 0x20: strcpy(insn[i],"CVT.S.L"); type=FCONV; break;
8006 case 0x21: strcpy(insn[i],"CVT.D.L"); type=FCONV; break;
8011 case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
8012 case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
8013 case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
8014 case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
8015 case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
8016 case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
8017 case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
8018 case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
8019 case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
8020 case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
8021 case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
8022 case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
8023 case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
8024 case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
8025 case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
8026 case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
8027 case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
8028 case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
8029 case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
8030 case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
8031 case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
8032 case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
8033 case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
8034 case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
8035 case 0x30: strcpy(insn[i],"LL"); type=NI; break;
8036 case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
8037 case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
8038 case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
8039 case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
8040 case 0x38: strcpy(insn[i],"SC"); type=NI; break;
8041 case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
8042 case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
8043 case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
8044 case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
8046 case 0x12: strcpy(insn[i],"COP2"); type=NI;
8047 op2=(source[i]>>21)&0x1f;
8050 case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
8051 case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
8052 case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
8053 case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
8055 if (gte_handlers[source[i]&0x3f]!=NULL) {
8056 snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
8062 case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
8063 case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
8064 case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
8066 default: strcpy(insn[i],"???"); type=NI;
8067 printf("NI %08x @%08x\n", source[i], addr + i*4);
8072 /* Get registers/immediates */
8080 rs1[i]=(source[i]>>21)&0x1f;
8082 rt1[i]=(source[i]>>16)&0x1f;
8084 imm[i]=(short)source[i];
8088 rs1[i]=(source[i]>>21)&0x1f;
8089 rs2[i]=(source[i]>>16)&0x1f;
8092 imm[i]=(short)source[i];
8093 if(op==0x2c||op==0x2d||op==0x3f) us1[i]=rs2[i]; // 64-bit SDL/SDR/SD
8096 // LWL/LWR only load part of the register,
8097 // therefore the target register must be treated as a source too
8098 rs1[i]=(source[i]>>21)&0x1f;
8099 rs2[i]=(source[i]>>16)&0x1f;
8100 rt1[i]=(source[i]>>16)&0x1f;
8102 imm[i]=(short)source[i];
8103 if(op==0x1a||op==0x1b) us1[i]=rs2[i]; // LDR/LDL
8104 if(op==0x26) dep1[i]=rt1[i]; // LWR
8107 if (op==0x0f) rs1[i]=0; // LUI instruction has no source register
8108 else rs1[i]=(source[i]>>21)&0x1f;
8110 rt1[i]=(source[i]>>16)&0x1f;
8112 if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
8113 imm[i]=(unsigned short)source[i];
8115 imm[i]=(short)source[i];
8117 if(op==0x18||op==0x19) us1[i]=rs1[i]; // DADDI/DADDIU
8118 if(op==0x0a||op==0x0b) us1[i]=rs1[i]; // SLTI/SLTIU
8119 if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI
8126 // The JAL instruction writes to r31.
8133 rs1[i]=(source[i]>>21)&0x1f;
8137 // The JALR instruction writes to r31.
8144 rs1[i]=(source[i]>>21)&0x1f;
8145 rs2[i]=(source[i]>>16)&0x1f;
8148 if(op&2) { // BGTZ/BLEZ
8156 rs1[i]=(source[i]>>21)&0x1f;
8161 if(op2&0x10) { // BxxAL
8163 // NOTE: If the branch is not taken, r31 is still overwritten
8165 likely[i]=(op2&2)>>1;
8172 likely[i]=((source[i])>>17)&1;
8175 rs1[i]=(source[i]>>21)&0x1f; // source
8176 rs2[i]=(source[i]>>16)&0x1f; // subtract amount
8177 rt1[i]=(source[i]>>11)&0x1f; // destination
8179 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
8180 us1[i]=rs1[i];us2[i]=rs2[i];
8182 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
8183 dep1[i]=rs1[i];dep2[i]=rs2[i];
8185 else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB
8186 dep1[i]=rs1[i];dep2[i]=rs2[i];
8190 rs1[i]=(source[i]>>21)&0x1f; // source
8191 rs2[i]=(source[i]>>16)&0x1f; // divisor
8194 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
8195 us1[i]=rs1[i];us2[i]=rs2[i];
8203 if(op2==0x10) rs1[i]=HIREG; // MFHI
8204 if(op2==0x11) rt1[i]=HIREG; // MTHI
8205 if(op2==0x12) rs1[i]=LOREG; // MFLO
8206 if(op2==0x13) rt1[i]=LOREG; // MTLO
8207 if((op2&0x1d)==0x10) rt1[i]=(source[i]>>11)&0x1f; // MFxx
8208 if((op2&0x1d)==0x11) rs1[i]=(source[i]>>21)&0x1f; // MTxx
8212 rs1[i]=(source[i]>>16)&0x1f; // target of shift
8213 rs2[i]=(source[i]>>21)&0x1f; // shift amount
8214 rt1[i]=(source[i]>>11)&0x1f; // destination
8216 // DSLLV/DSRLV/DSRAV are 64-bit
8217 if(op2>=0x14&&op2<=0x17) us1[i]=rs1[i];
8220 rs1[i]=(source[i]>>16)&0x1f;
8222 rt1[i]=(source[i]>>11)&0x1f;
8224 imm[i]=(source[i]>>6)&0x1f;
8225 // DSxx32 instructions
8226 if(op2>=0x3c) imm[i]|=0x20;
8227 // DSLL/DSRL/DSRA/DSRA32/DSRL32 but not DSLL32 require 64-bit source
8228 if(op2>=0x38&&op2!=0x3c) us1[i]=rs1[i];
8235 if(op2==0) rt1[i]=(source[i]>>16)&0x1F; // MFC0
8236 if(op2==4) rs1[i]=(source[i]>>16)&0x1F; // MTC0
8237 if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status
8238 if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET
8246 if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
8247 if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
8248 if(op2==5) us1[i]=rs1[i]; // DMTC1
8252 rs1[i]=(source[i]>>21)&0x1F;
8256 imm[i]=(short)source[i];
8259 rs1[i]=(source[i]>>21)&0x1F;
8263 imm[i]=(short)source[i];
8291 /* Calculate branch target addresses */
8293 ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
8294 else if(type==CJUMP&&rs1[i]==rs2[i]&&(op&1))
8295 ba[i]=start+i*4+8; // Ignore never taken branch
8296 else if(type==SJUMP&&rs1[i]==0&&!(op2&1))
8297 ba[i]=start+i*4+8; // Ignore never taken branch
8298 else if(type==CJUMP||type==SJUMP||type==FJUMP)
8299 ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
8301 /* Is this the end of the block? */
8302 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
8303 if(rt1[i-1]!=31) { // Continue past subroutine call (JAL)
8305 // Does the block continue due to a branch?
8308 if(ba[j]==start+i*4+4) done=j=0;
8309 if(ba[j]==start+i*4+8) done=j=0;
8313 if(stop_after_jal) done=1;
8315 if((source[i+1]&0xfc00003f)==0x0d) done=1;
8317 // Don't recompile stuff that's already compiled
8318 if(check_addr(start+i*4+4)) done=1;
8319 // Don't get too close to the limit
8320 if(i>MAXBLOCK/2) done=1;
8322 if(i>0&&itype[i-1]==SYSCALL&&stop_after_jal) done=1;
8323 if(itype[i-1]==HLECALL) done=1;
8324 assert(i<MAXBLOCK-1);
8325 if(start+i*4==pagelimit-4) done=1;
8326 assert(start+i*4<pagelimit);
8327 if (i==MAXBLOCK-1) done=1;
8328 // Stop if we're compiling junk
8329 if(itype[i]==NI&&opcode[i]==0x11) {
8330 done=stop_after_jal=1;
8331 printf("Disabled speculative precompilation\n");
8335 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP||itype[i-1]==FJUMP) {
8336 if(start+i*4==pagelimit) {
8342 /* Pass 2 - Register dependencies and branch targets */
8344 unneeded_registers(0,slen-1,0);
8346 /* Pass 3 - Register allocation */
8348 struct regstat current; // Current register allocations/status
8351 current.u=unneeded_reg[0];
8352 current.uu=unneeded_reg_upper[0];
8353 clear_all_regs(current.regmap);
8354 alloc_reg(¤t,0,CCREG);
8355 dirty_reg(¤t,CCREG);
8362 provisional_32bit();
8365 // First instruction is delay slot
8370 unneeded_reg_upper[0]=1;
8371 current.regmap[HOST_BTREG]=BTREG;
8379 for(hr=0;hr<HOST_REGS;hr++)
8381 // Is this really necessary?
8382 if(current.regmap[hr]==0) current.regmap[hr]=-1;
8388 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
8390 if(rs1[i-2]==0||rs2[i-2]==0)
8393 current.is32|=1LL<<rs1[i-2];
8394 int hr=get_reg(current.regmap,rs1[i-2]|64);
8395 if(hr>=0) current.regmap[hr]=-1;
8398 current.is32|=1LL<<rs2[i-2];
8399 int hr=get_reg(current.regmap,rs2[i-2]|64);
8400 if(hr>=0) current.regmap[hr]=-1;
8405 // If something jumps here with 64-bit values
8406 // then promote those registers to 64 bits
8409 uint64_t temp_is32=current.is32;
8412 if(ba[j]==start+i*4)
8413 temp_is32&=branch_regs[j].is32;
8417 if(ba[j]==start+i*4)
8421 if(temp_is32!=current.is32) {
8422 //printf("dumping 32-bit regs (%x)\n",start+i*4);
8423 #ifdef DESTRUCTIVE_WRITEBACK
8424 for(hr=0;hr<HOST_REGS;hr++)
8426 int r=current.regmap[hr];
8429 if((current.dirty>>hr)&((current.is32&~temp_is32)>>r)&1) {
8431 //printf("restore %d\n",r);
8436 current.is32=temp_is32;
8440 memset(p32, 0xff, sizeof(p32));
8444 memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
8445 regs[i].wasconst=current.isconst;
8446 regs[i].was32=current.is32;
8447 regs[i].wasdirty=current.dirty;
8448 #ifdef DESTRUCTIVE_WRITEBACK
8449 // To change a dirty register from 32 to 64 bits, we must write
8450 // it out during the previous cycle (for branches, 2 cycles)
8451 if(i<slen-1&&bt[i+1]&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP)
8453 uint64_t temp_is32=current.is32;
8456 if(ba[j]==start+i*4+4)
8457 temp_is32&=branch_regs[j].is32;
8461 if(ba[j]==start+i*4+4)
8465 if(temp_is32!=current.is32) {
8466 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8467 for(hr=0;hr<HOST_REGS;hr++)
8469 int r=current.regmap[hr];
8472 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8473 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP)
8475 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63))
8477 //printf("dump %d/r%d\n",hr,r);
8478 current.regmap[hr]=-1;
8479 if(get_reg(current.regmap,r|64)>=0)
8480 current.regmap[get_reg(current.regmap,r|64)]=-1;
8488 else if(i<slen-2&&bt[i+2]&&(source[i-1]>>16)!=0x1000&&(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP))
8490 uint64_t temp_is32=current.is32;
8493 if(ba[j]==start+i*4+8)
8494 temp_is32&=branch_regs[j].is32;
8498 if(ba[j]==start+i*4+8)
8502 if(temp_is32!=current.is32) {
8503 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8504 for(hr=0;hr<HOST_REGS;hr++)
8506 int r=current.regmap[hr];
8509 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8510 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63)&&rs1[i+1]!=(r&63)&&rs2[i+1]!=(r&63))
8512 //printf("dump %d/r%d\n",hr,r);
8513 current.regmap[hr]=-1;
8514 if(get_reg(current.regmap,r|64)>=0)
8515 current.regmap[get_reg(current.regmap,r|64)]=-1;
8523 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
8525 current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
8526 current.uu=unneeded_reg_upper[i+1]&~((1LL<<us1[i])|(1LL<<us2[i]));
8527 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8536 current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
8537 current.uu=branch_unneeded_reg_upper[i]&~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
8538 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
8539 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8540 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8543 } else { printf("oops, branch at end of block with no delay slot\n");exit(1); }
8547 ds=0; // Skip delay slot, already allocated as part of branch
8548 // ...but we need to alloc it in case something jumps here
8550 current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
8551 current.uu=branch_unneeded_reg_upper[i-1]&unneeded_reg_upper[i+1];
8553 current.u=branch_unneeded_reg[i-1];
8554 current.uu=branch_unneeded_reg_upper[i-1];
8556 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8557 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8558 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8561 struct regstat temp;
8562 memcpy(&temp,¤t,sizeof(current));
8563 temp.wasdirty=temp.dirty;
8564 temp.was32=temp.is32;
8565 // TODO: Take into account unconditional branches, as below
8566 delayslot_alloc(&temp,i);
8567 memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
8568 regs[i].wasdirty=temp.wasdirty;
8569 regs[i].was32=temp.was32;
8570 regs[i].dirty=temp.dirty;
8571 regs[i].is32=temp.is32;
8575 // Create entry (branch target) regmap
8576 for(hr=0;hr<HOST_REGS;hr++)
8578 int r=temp.regmap[hr];
8580 if(r!=regmap_pre[i][hr]) {
8581 regs[i].regmap_entry[hr]=-1;
8586 if((current.u>>r)&1) {
8587 regs[i].regmap_entry[hr]=-1;
8588 regs[i].regmap[hr]=-1;
8589 //Don't clear regs in the delay slot as the branch might need them
8590 //current.regmap[hr]=-1;
8592 regs[i].regmap_entry[hr]=r;
8595 if((current.uu>>(r&63))&1) {
8596 regs[i].regmap_entry[hr]=-1;
8597 regs[i].regmap[hr]=-1;
8598 //Don't clear regs in the delay slot as the branch might need them
8599 //current.regmap[hr]=-1;
8601 regs[i].regmap_entry[hr]=r;
8605 // First instruction expects CCREG to be allocated
8606 if(i==0&&hr==HOST_CCREG)
8607 regs[i].regmap_entry[hr]=CCREG;
8609 regs[i].regmap_entry[hr]=-1;
8613 else { // Not delay slot
8616 //current.isconst=0; // DEBUG
8617 //current.wasconst=0; // DEBUG
8618 //regs[i].wasconst=0; // DEBUG
8619 clear_const(¤t,rt1[i]);
8620 alloc_cc(¤t,i);
8621 dirty_reg(¤t,CCREG);
8623 alloc_reg(¤t,i,31);
8624 dirty_reg(¤t,31);
8625 assert(rs1[i+1]!=31&&rs2[i+1]!=31);
8627 alloc_reg(¤t,i,PTEMP);
8629 //current.is32|=1LL<<rt1[i];
8631 delayslot_alloc(¤t,i+1);
8632 //current.isconst=0; // DEBUG
8634 //printf("i=%d, isconst=%x\n",i,current.isconst);
8637 //current.isconst=0;
8638 //current.wasconst=0;
8639 //regs[i].wasconst=0;
8640 clear_const(¤t,rs1[i]);
8641 clear_const(¤t,rt1[i]);
8642 alloc_cc(¤t,i);
8643 dirty_reg(¤t,CCREG);
8644 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
8645 alloc_reg(¤t,i,rs1[i]);
8647 alloc_reg(¤t,i,31);
8648 dirty_reg(¤t,31);
8649 assert(rs1[i+1]!=31&&rs2[i+1]!=31);
8651 alloc_reg(¤t,i,PTEMP);
8655 if(rs1[i]==31) { // JALR
8656 alloc_reg(¤t,i,RHASH);
8657 #ifndef HOST_IMM_ADDR32
8658 alloc_reg(¤t,i,RHTBL);
8662 delayslot_alloc(¤t,i+1);
8664 // The delay slot overwrites our source register,
8665 // allocate a temporary register to hold the old value.
8669 delayslot_alloc(¤t,i+1);
8671 alloc_reg(¤t,i,RTEMP);
8673 //current.isconst=0; // DEBUG
8677 //current.isconst=0;
8678 //current.wasconst=0;
8679 //regs[i].wasconst=0;
8680 clear_const(¤t,rs1[i]);
8681 clear_const(¤t,rs2[i]);
8682 if((opcode[i]&0x3E)==4) // BEQ/BNE
8684 alloc_cc(¤t,i);
8685 dirty_reg(¤t,CCREG);
8686 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
8687 if(rs2[i]) alloc_reg(¤t,i,rs2[i]);
8688 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8690 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
8691 if(rs2[i]) alloc_reg64(¤t,i,rs2[i]);
8693 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
8694 (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) {
8695 // The delay slot overwrites one of our conditions.
8696 // Allocate the branch condition registers instead.
8697 // Note that such a sequence of instructions could
8698 // be considered a bug since the branch can not be
8699 // re-executed if an exception occurs.
8703 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
8704 if(rs2[i]) alloc_reg(¤t,i,rs2[i]);
8705 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8707 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
8708 if(rs2[i]) alloc_reg64(¤t,i,rs2[i]);
8711 else delayslot_alloc(¤t,i+1);
8714 if((opcode[i]&0x3E)==6) // BLEZ/BGTZ
8716 alloc_cc(¤t,i);
8717 dirty_reg(¤t,CCREG);
8718 alloc_reg(¤t,i,rs1[i]);
8719 if(!(current.is32>>rs1[i]&1))
8721 alloc_reg64(¤t,i,rs1[i]);
8723 if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
8724 // The delay slot overwrites one of our conditions.
8725 // Allocate the branch condition registers instead.
8726 // Note that such a sequence of instructions could
8727 // be considered a bug since the branch can not be
8728 // re-executed if an exception occurs.
8732 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
8733 if(!((current.is32>>rs1[i])&1))
8735 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
8738 else delayslot_alloc(¤t,i+1);
8741 // Don't alloc the delay slot yet because we might not execute it
8742 if((opcode[i]&0x3E)==0x14) // BEQL/BNEL
8747 alloc_cc(¤t,i);
8748 dirty_reg(¤t,CCREG);
8749 alloc_reg(¤t,i,rs1[i]);
8750 alloc_reg(¤t,i,rs2[i]);
8751 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8753 alloc_reg64(¤t,i,rs1[i]);
8754 alloc_reg64(¤t,i,rs2[i]);
8758 if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL
8763 alloc_cc(¤t,i);
8764 dirty_reg(¤t,CCREG);
8765 alloc_reg(¤t,i,rs1[i]);
8766 if(!(current.is32>>rs1[i]&1))
8768 alloc_reg64(¤t,i,rs1[i]);
8772 //current.isconst=0;
8775 //current.isconst=0;
8776 //current.wasconst=0;
8777 //regs[i].wasconst=0;
8778 clear_const(¤t,rs1[i]);
8779 clear_const(¤t,rt1[i]);
8780 //if((opcode2[i]&0x1E)==0x0) // BLTZ/BGEZ
8781 if((opcode2[i]&0x0E)==0x0) // BLTZ/BGEZ
8783 alloc_cc(¤t,i);
8784 dirty_reg(¤t,CCREG);
8785 alloc_reg(¤t,i,rs1[i]);
8786 if(!(current.is32>>rs1[i]&1))
8788 alloc_reg64(¤t,i,rs1[i]);
8790 if (rt1[i]==31) { // BLTZAL/BGEZAL
8791 alloc_reg(¤t,i,31);
8792 dirty_reg(¤t,31);
8793 assert(rs1[i+1]!=31&&rs2[i+1]!=31);
8794 //#ifdef REG_PREFETCH
8795 //alloc_reg(¤t,i,PTEMP);
8797 //current.is32|=1LL<<rt1[i];
8799 if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
8800 // The delay slot overwrites the branch condition.
8801 // Allocate the branch condition registers instead.
8802 // Note that such a sequence of instructions could
8803 // be considered a bug since the branch can not be
8804 // re-executed if an exception occurs.
8808 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
8809 if(!((current.is32>>rs1[i])&1))
8811 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
8814 else delayslot_alloc(¤t,i+1);
8817 // Don't alloc the delay slot yet because we might not execute it
8818 if((opcode2[i]&0x1E)==0x2) // BLTZL/BGEZL
8823 alloc_cc(¤t,i);
8824 dirty_reg(¤t,CCREG);
8825 alloc_reg(¤t,i,rs1[i]);
8826 if(!(current.is32>>rs1[i]&1))
8828 alloc_reg64(¤t,i,rs1[i]);
8832 //current.isconst=0;
8838 if(likely[i]==0) // BC1F/BC1T
8840 // TODO: Theoretically we can run out of registers here on x86.
8841 // The delay slot can allocate up to six, and we need to check
8842 // CSREG before executing the delay slot. Possibly we can drop
8843 // the cycle count and then reload it after checking that the
8844 // FPU is in a usable state, or don't do out-of-order execution.
8845 alloc_cc(¤t,i);
8846 dirty_reg(¤t,CCREG);
8847 alloc_reg(¤t,i,FSREG);
8848 alloc_reg(¤t,i,CSREG);
8849 if(itype[i+1]==FCOMP) {
8850 // The delay slot overwrites the branch condition.
8851 // Allocate the branch condition registers instead.
8852 // Note that such a sequence of instructions could
8853 // be considered a bug since the branch can not be
8854 // re-executed if an exception occurs.
8855 alloc_cc(¤t,i);
8856 dirty_reg(¤t,CCREG);
8857 alloc_reg(¤t,i,CSREG);
8858 alloc_reg(¤t,i,FSREG);
8861 delayslot_alloc(¤t,i+1);
8862 alloc_reg(¤t,i+1,CSREG);
8866 // Don't alloc the delay slot yet because we might not execute it
8867 if(likely[i]) // BC1FL/BC1TL
8869 alloc_cc(¤t,i);
8870 dirty_reg(¤t,CCREG);
8871 alloc_reg(¤t,i,CSREG);
8872 alloc_reg(¤t,i,FSREG);
8878 imm16_alloc(¤t,i);
8882 load_alloc(¤t,i);
8886 store_alloc(¤t,i);
8889 alu_alloc(¤t,i);
8892 shift_alloc(¤t,i);
8895 multdiv_alloc(¤t,i);
8898 shiftimm_alloc(¤t,i);
8901 mov_alloc(¤t,i);
8904 cop0_alloc(¤t,i);
8908 cop1_alloc(¤t,i);
8911 c1ls_alloc(¤t,i);
8914 c2ls_alloc(¤t,i);
8917 c2op_alloc(¤t,i);
8920 fconv_alloc(¤t,i);
8923 float_alloc(¤t,i);
8926 fcomp_alloc(¤t,i);
8930 syscall_alloc(¤t,i);
8933 pagespan_alloc(¤t,i);
8937 // Drop the upper half of registers that have become 32-bit
8938 current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i]));
8939 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
8940 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8941 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8944 current.uu|=current.is32&((1LL<<rt1[i+1])|(1LL<<rt2[i+1]));
8945 current.uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
8946 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
8947 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8951 // Create entry (branch target) regmap
8952 for(hr=0;hr<HOST_REGS;hr++)
8955 r=current.regmap[hr];
8957 if(r!=regmap_pre[i][hr]) {
8958 // TODO: delay slot (?)
8959 or=get_reg(regmap_pre[i],r); // Get old mapping for this register
8960 if(or<0||(r&63)>=TEMPREG){
8961 regs[i].regmap_entry[hr]=-1;
8965 // Just move it to a different register
8966 regs[i].regmap_entry[hr]=r;
8967 // If it was dirty before, it's still dirty
8968 if((regs[i].wasdirty>>or)&1) dirty_reg(¤t,r&63);
8975 regs[i].regmap_entry[hr]=0;
8979 if((current.u>>r)&1) {
8980 regs[i].regmap_entry[hr]=-1;
8981 //regs[i].regmap[hr]=-1;
8982 current.regmap[hr]=-1;
8984 regs[i].regmap_entry[hr]=r;
8987 if((current.uu>>(r&63))&1) {
8988 regs[i].regmap_entry[hr]=-1;
8989 //regs[i].regmap[hr]=-1;
8990 current.regmap[hr]=-1;
8992 regs[i].regmap_entry[hr]=r;
8996 // Branches expect CCREG to be allocated at the target
8997 if(regmap_pre[i][hr]==CCREG)
8998 regs[i].regmap_entry[hr]=CCREG;
9000 regs[i].regmap_entry[hr]=-1;
9003 memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
9005 /* Branch post-alloc */
9008 current.was32=current.is32;
9009 current.wasdirty=current.dirty;
9010 switch(itype[i-1]) {
9012 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9013 branch_regs[i-1].isconst=0;
9014 branch_regs[i-1].wasconst=0;
9015 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9016 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9017 alloc_cc(&branch_regs[i-1],i-1);
9018 dirty_reg(&branch_regs[i-1],CCREG);
9019 if(rt1[i-1]==31) { // JAL
9020 alloc_reg(&branch_regs[i-1],i-1,31);
9021 dirty_reg(&branch_regs[i-1],31);
9022 branch_regs[i-1].is32|=1LL<<31;
9024 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9025 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9028 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9029 branch_regs[i-1].isconst=0;
9030 branch_regs[i-1].wasconst=0;
9031 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9032 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9033 alloc_cc(&branch_regs[i-1],i-1);
9034 dirty_reg(&branch_regs[i-1],CCREG);
9035 alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]);
9036 if(rt1[i-1]==31) { // JALR
9037 alloc_reg(&branch_regs[i-1],i-1,31);
9038 dirty_reg(&branch_regs[i-1],31);
9039 branch_regs[i-1].is32|=1LL<<31;
9042 if(rs1[i-1]==31) { // JALR
9043 alloc_reg(&branch_regs[i-1],i-1,RHASH);
9044 #ifndef HOST_IMM_ADDR32
9045 alloc_reg(&branch_regs[i-1],i-1,RHTBL);
9049 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9050 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9053 if((opcode[i-1]&0x3E)==4) // BEQ/BNE
9055 alloc_cc(¤t,i-1);
9056 dirty_reg(¤t,CCREG);
9057 if((rs1[i-1]&&(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]))||
9058 (rs2[i-1]&&(rs2[i-1]==rt1[i]||rs2[i-1]==rt2[i]))) {
9059 // The delay slot overwrote one of our conditions
9060 // Delay slot goes after the test (in order)
9061 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9062 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9063 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9066 delayslot_alloc(¤t,i);
9071 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9072 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9073 // Alloc the branch condition registers
9074 if(rs1[i-1]) alloc_reg(¤t,i-1,rs1[i-1]);
9075 if(rs2[i-1]) alloc_reg(¤t,i-1,rs2[i-1]);
9076 if(!((current.is32>>rs1[i-1])&(current.is32>>rs2[i-1])&1))
9078 if(rs1[i-1]) alloc_reg64(¤t,i-1,rs1[i-1]);
9079 if(rs2[i-1]) alloc_reg64(¤t,i-1,rs2[i-1]);
9082 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9083 branch_regs[i-1].isconst=0;
9084 branch_regs[i-1].wasconst=0;
9085 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9086 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9089 if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ
9091 alloc_cc(¤t,i-1);
9092 dirty_reg(¤t,CCREG);
9093 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9094 // The delay slot overwrote the branch condition
9095 // Delay slot goes after the test (in order)
9096 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9097 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9098 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9101 delayslot_alloc(¤t,i);
9106 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9107 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9108 // Alloc the branch condition register
9109 alloc_reg(¤t,i-1,rs1[i-1]);
9110 if(!(current.is32>>rs1[i-1]&1))
9112 alloc_reg64(¤t,i-1,rs1[i-1]);
9115 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9116 branch_regs[i-1].isconst=0;
9117 branch_regs[i-1].wasconst=0;
9118 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9119 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9122 // Alloc the delay slot in case the branch is taken
9123 if((opcode[i-1]&0x3E)==0x14) // BEQL/BNEL
9125 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9126 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9127 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9128 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9129 alloc_cc(&branch_regs[i-1],i);
9130 dirty_reg(&branch_regs[i-1],CCREG);
9131 delayslot_alloc(&branch_regs[i-1],i);
9132 branch_regs[i-1].isconst=0;
9133 alloc_reg(¤t,i,CCREG); // Not taken path
9134 dirty_reg(¤t,CCREG);
9135 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9138 if((opcode[i-1]&0x3E)==0x16) // BLEZL/BGTZL
9140 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9141 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9142 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9143 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9144 alloc_cc(&branch_regs[i-1],i);
9145 dirty_reg(&branch_regs[i-1],CCREG);
9146 delayslot_alloc(&branch_regs[i-1],i);
9147 branch_regs[i-1].isconst=0;
9148 alloc_reg(¤t,i,CCREG); // Not taken path
9149 dirty_reg(¤t,CCREG);
9150 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9154 //if((opcode2[i-1]&0x1E)==0) // BLTZ/BGEZ
9155 if((opcode2[i-1]&0x0E)==0) // BLTZ/BGEZ
9157 alloc_cc(¤t,i-1);
9158 dirty_reg(¤t,CCREG);
9159 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9160 // The delay slot overwrote the branch condition
9161 // Delay slot goes after the test (in order)
9162 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9163 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9164 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9167 delayslot_alloc(¤t,i);
9172 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9173 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9174 // Alloc the branch condition register
9175 alloc_reg(¤t,i-1,rs1[i-1]);
9176 if(!(current.is32>>rs1[i-1]&1))
9178 alloc_reg64(¤t,i-1,rs1[i-1]);
9181 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9182 branch_regs[i-1].isconst=0;
9183 branch_regs[i-1].wasconst=0;
9184 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9185 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9188 // Alloc the delay slot in case the branch is taken
9189 if((opcode2[i-1]&0x1E)==2) // BLTZL/BGEZL
9191 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9192 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9193 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9194 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9195 alloc_cc(&branch_regs[i-1],i);
9196 dirty_reg(&branch_regs[i-1],CCREG);
9197 delayslot_alloc(&branch_regs[i-1],i);
9198 branch_regs[i-1].isconst=0;
9199 alloc_reg(¤t,i,CCREG); // Not taken path
9200 dirty_reg(¤t,CCREG);
9201 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9203 // FIXME: BLTZAL/BGEZAL
9204 if(opcode2[i-1]&0x10) { // BxxZAL
9205 alloc_reg(&branch_regs[i-1],i-1,31);
9206 dirty_reg(&branch_regs[i-1],31);
9207 branch_regs[i-1].is32|=1LL<<31;
9211 if(likely[i-1]==0) // BC1F/BC1T
9213 alloc_cc(¤t,i-1);
9214 dirty_reg(¤t,CCREG);
9215 if(itype[i]==FCOMP) {
9216 // The delay slot overwrote the branch condition
9217 // Delay slot goes after the test (in order)
9218 delayslot_alloc(¤t,i);
9223 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9224 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9225 // Alloc the branch condition register
9226 alloc_reg(¤t,i-1,FSREG);
9228 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9229 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9233 // Alloc the delay slot in case the branch is taken
9234 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9235 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9236 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9237 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9238 alloc_cc(&branch_regs[i-1],i);
9239 dirty_reg(&branch_regs[i-1],CCREG);
9240 delayslot_alloc(&branch_regs[i-1],i);
9241 branch_regs[i-1].isconst=0;
9242 alloc_reg(¤t,i,CCREG); // Not taken path
9243 dirty_reg(¤t,CCREG);
9244 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9249 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
9251 if(rt1[i-1]==31) // JAL/JALR
9253 // Subroutine call will return here, don't alloc any registers
9256 clear_all_regs(current.regmap);
9257 alloc_reg(¤t,i,CCREG);
9258 dirty_reg(¤t,CCREG);
9262 // Internal branch will jump here, match registers to caller
9263 current.is32=0x3FFFFFFFFLL;
9265 clear_all_regs(current.regmap);
9266 alloc_reg(¤t,i,CCREG);
9267 dirty_reg(¤t,CCREG);
9270 if(ba[j]==start+i*4+4) {
9271 memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
9272 current.is32=branch_regs[j].is32;
9273 current.dirty=branch_regs[j].dirty;
9278 if(ba[j]==start+i*4+4) {
9279 for(hr=0;hr<HOST_REGS;hr++) {
9280 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
9281 current.regmap[hr]=-1;
9283 current.is32&=branch_regs[j].is32;
9284 current.dirty&=branch_regs[j].dirty;
9293 // Count cycles in between branches
9295 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP||itype[i]==SYSCALL||itype[i]==HLECALL))
9304 flush_dirty_uppers(¤t);
9306 regs[i].is32=current.is32;
9307 regs[i].dirty=current.dirty;
9308 regs[i].isconst=current.isconst;
9309 memcpy(constmap[i],current.constmap,sizeof(current.constmap));
9311 for(hr=0;hr<HOST_REGS;hr++) {
9312 if(hr!=EXCLUDE_REG&®s[i].regmap[hr]>=0) {
9313 if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
9314 regs[i].wasconst&=~(1<<hr);
9318 if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
9321 /* Pass 4 - Cull unused host registers */
9325 for (i=slen-1;i>=0;i--)
9328 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9330 if(ba[i]<start || ba[i]>=(start+slen*4))
9332 // Branch out of this block, don't need anything
9338 // Need whatever matches the target
9340 int t=(ba[i]-start)>>2;
9341 for(hr=0;hr<HOST_REGS;hr++)
9343 if(regs[i].regmap_entry[hr]>=0) {
9344 if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
9348 // Conditional branch may need registers for following instructions
9349 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9352 nr|=needed_reg[i+2];
9353 for(hr=0;hr<HOST_REGS;hr++)
9355 if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
9356 //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
9360 // Don't need stuff which is overwritten
9361 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9362 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9363 // Merge in delay slot
9364 for(hr=0;hr<HOST_REGS;hr++)
9367 // These are overwritten unless the branch is "likely"
9368 // and the delay slot is nullified if not taken
9369 if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9370 if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9372 if(us1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9373 if(us2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9374 if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9375 if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9376 if(us1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9377 if(us2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9378 if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9379 if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9380 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1)) {
9381 if(dep1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9382 if(dep2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9384 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1)) {
9385 if(dep1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9386 if(dep2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9388 if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) {
9389 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9390 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9394 else if(itype[i]==SYSCALL||itype[i]==HLECALL)
9396 // SYSCALL instruction (software interrupt)
9399 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
9401 // ERET instruction (return from interrupt)
9407 for(hr=0;hr<HOST_REGS;hr++) {
9408 if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
9409 if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
9410 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9411 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9415 for(hr=0;hr<HOST_REGS;hr++)
9417 // Overwritten registers are not needed
9418 if(rt1[i]&&rt1[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9419 if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9420 if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9421 // Source registers are needed
9422 if(us1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9423 if(us2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9424 if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr;
9425 if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr;
9426 if(us1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9427 if(us2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9428 if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9429 if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9430 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1)) {
9431 if(dep1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9432 if(dep1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9434 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1)) {
9435 if(dep2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9436 if(dep2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9438 if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) {
9439 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9440 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9442 // Don't store a register immediately after writing it,
9443 // may prevent dual-issue.
9444 // But do so if this is a branch target, otherwise we
9445 // might have to load the register before the branch.
9446 if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) {
9447 if((regmap_pre[i][hr]>0&®map_pre[i][hr]<64&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1)) ||
9448 (regmap_pre[i][hr]>64&&!((unneeded_reg_upper[i]>>(regmap_pre[i][hr]&63))&1)) ) {
9449 if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9450 if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9452 if((regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1)) ||
9453 (regs[i].regmap_entry[hr]>64&&!((unneeded_reg_upper[i]>>(regs[i].regmap_entry[hr]&63))&1)) ) {
9454 if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9455 if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9459 // Cycle count is needed at branches. Assume it is needed at the target too.
9460 if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==FJUMP||itype[i]==SPAN) {
9461 if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9462 if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9467 // Deallocate unneeded registers
9468 for(hr=0;hr<HOST_REGS;hr++)
9471 if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
9472 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9473 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9474 (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG)
9476 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9479 regs[i].regmap[hr]=-1;
9480 regs[i].isconst&=~(1<<hr);
9481 if(i<slen-2) regmap_pre[i+2][hr]=-1;
9485 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9487 int d1=0,d2=0,map=0,temp=0;
9488 if(get_reg(regs[i].regmap,rt1[i+1]|64)>=0||get_reg(branch_regs[i].regmap,rt1[i+1]|64)>=0)
9494 if(itype[i+1]==LOAD || itype[i+1]==LOADLR ||
9495 itype[i+1]==STORE || itype[i+1]==STORELR ||
9496 itype[i+1]==C1LS || itype[i+1]==C2LS)
9499 if(itype[i+1]==STORE || itype[i+1]==STORELR ||
9500 (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
9503 if(itype[i+1]==LOADLR || itype[i+1]==STORELR ||
9504 itype[i+1]==C1LS || itype[i+1]==C2LS)
9506 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9507 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9508 (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] &&
9509 (regs[i].regmap[hr]^64)!=us1[i+1] && (regs[i].regmap[hr]^64)!=us2[i+1] &&
9510 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9511 regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] &&
9512 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
9513 regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
9514 regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
9515 regs[i].regmap[hr]!=map )
9517 regs[i].regmap[hr]=-1;
9518 regs[i].isconst&=~(1<<hr);
9519 if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] &&
9520 (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] &&
9521 (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] &&
9522 (branch_regs[i].regmap[hr]^64)!=us1[i+1] && (branch_regs[i].regmap[hr]^64)!=us2[i+1] &&
9523 (branch_regs[i].regmap[hr]^64)!=d1 && (branch_regs[i].regmap[hr]^64)!=d2 &&
9524 branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] &&
9525 (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
9526 branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
9527 branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
9528 branch_regs[i].regmap[hr]!=map)
9530 branch_regs[i].regmap[hr]=-1;
9531 branch_regs[i].regmap_entry[hr]=-1;
9532 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9534 if(!likely[i]&&i<slen-2) {
9535 regmap_pre[i+2][hr]=-1;
9546 int d1=0,d2=0,map=-1,temp=-1;
9547 if(get_reg(regs[i].regmap,rt1[i]|64)>=0)
9553 if(itype[i]==LOAD || itype[i]==LOADLR ||
9554 itype[i]==STORE || itype[i]==STORELR ||
9555 itype[i]==C1LS || itype[i]==C2LS)
9557 } else if(itype[i]==STORE || itype[i]==STORELR ||
9558 (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
9561 if(itype[i]==LOADLR || itype[i]==STORELR ||
9562 itype[i]==C1LS || itype[i]==C2LS)
9564 if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9565 (regs[i].regmap[hr]^64)!=us1[i] && (regs[i].regmap[hr]^64)!=us2[i] &&
9566 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9567 regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] &&
9568 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map &&
9569 (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG))
9571 if(i<slen-1&&!is_ds[i]) {
9572 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]!=-1)
9573 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
9574 if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
9576 printf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
9577 assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
9579 regmap_pre[i+1][hr]=-1;
9580 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
9582 regs[i].regmap[hr]=-1;
9583 regs[i].isconst&=~(1<<hr);
9591 /* Pass 5 - Pre-allocate registers */
9593 // If a register is allocated during a loop, try to allocate it for the
9594 // entire loop, if possible. This avoids loading/storing registers
9595 // inside of the loop.
9597 signed char f_regmap[HOST_REGS];
9598 clear_all_regs(f_regmap);
9599 for(i=0;i<slen-1;i++)
9601 if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9603 if(ba[i]>=start && ba[i]<(start+i*4))
9604 if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
9605 ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
9606 ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
9607 ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
9608 ||itype[i+1]==FCOMP||itype[i+1]==FCONV
9609 ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
9611 int t=(ba[i]-start)>>2;
9612 if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots
9613 if(t<2||(itype[t-2]!=UJUMP)) // call/ret assumes no registers allocated
9614 for(hr=0;hr<HOST_REGS;hr++)
9616 if(regs[i].regmap[hr]>64) {
9617 if(!((regs[i].dirty>>hr)&1))
9618 f_regmap[hr]=regs[i].regmap[hr];
9619 else f_regmap[hr]=-1;
9621 else if(regs[i].regmap[hr]>=0) f_regmap[hr]=regs[i].regmap[hr];
9622 if(branch_regs[i].regmap[hr]>64) {
9623 if(!((branch_regs[i].dirty>>hr)&1))
9624 f_regmap[hr]=branch_regs[i].regmap[hr];
9625 else f_regmap[hr]=-1;
9627 else if(branch_regs[i].regmap[hr]>=0) f_regmap[hr]=branch_regs[i].regmap[hr];
9628 if(itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
9629 ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
9630 ||itype[i+1]==FCOMP||itype[i+1]==FCONV
9631 ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
9633 // Test both in case the delay slot is ooo,
9634 // could be done better...
9635 if(count_free_regs(branch_regs[i].regmap)<2
9636 ||count_free_regs(regs[i].regmap)<2)
9637 f_regmap[hr]=branch_regs[i].regmap[hr];
9639 // Avoid dirty->clean transition
9640 // #ifdef DESTRUCTIVE_WRITEBACK here?
9641 if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
9642 if(f_regmap[hr]>0) {
9643 if(regs[t].regmap_entry[hr]<0) {
9647 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
9648 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
9649 if(r>63&&((unneeded_reg_upper[j]>>(r&63))&1)) break;
9651 // NB This can exclude the case where the upper-half
9652 // register is lower numbered than the lower-half
9653 // register. Not sure if it's worth fixing...
9654 if(get_reg(regs[j].regmap,r&63)<0) break;
9655 if(regs[j].is32&(1LL<<(r&63))) break;
9657 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
9658 //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
9660 if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
9661 if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
9663 if(get_reg(regs[i].regmap,r&63)<0) break;
9664 if(get_reg(branch_regs[i].regmap,r&63)<0) break;
9667 while(k>1&®s[k-1].regmap[hr]==-1) {
9668 if(itype[k-1]==STORE||itype[k-1]==STORELR
9669 ||itype[k-1]==C1LS||itype[k-1]==SHIFT||itype[k-1]==COP1
9670 ||itype[k-1]==FLOAT||itype[k-1]==FCONV||itype[k-1]==FCOMP
9671 ||itype[k-1]==COP2||itype[k-1]==C2LS||itype[k-1]==C2OP) {
9672 if(count_free_regs(regs[k-1].regmap)<2) {
9673 //printf("no free regs for store %x\n",start+(k-1)*4);
9678 if(itype[k-1]!=NOP&&itype[k-1]!=MOV&&itype[k-1]!=ALU&&itype[k-1]!=SHIFTIMM&&itype[k-1]!=IMM16&&itype[k-1]!=LOAD) break;
9679 if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
9680 //printf("no-match due to different register\n");
9683 if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP||itype[k-2]==FJUMP) {
9684 //printf("no-match due to branch\n");
9687 // call/ret fast path assumes no registers allocated
9688 if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)) {
9692 // NB This can exclude the case where the upper-half
9693 // register is lower numbered than the lower-half
9694 // register. Not sure if it's worth fixing...
9695 if(get_reg(regs[k-1].regmap,r&63)<0) break;
9696 if(regs[k-1].is32&(1LL<<(r&63))) break;
9701 if((regs[k].is32&(1LL<<f_regmap[hr]))!=
9702 (regs[i+2].was32&(1LL<<f_regmap[hr]))) {
9703 //printf("bad match after branch\n");
9707 if(regs[k-1].regmap[hr]==f_regmap[hr]&®map_pre[k][hr]==f_regmap[hr]) {
9708 //printf("Extend r%d, %x ->\n",hr,start+k*4);
9710 regs[k].regmap_entry[hr]=f_regmap[hr];
9711 regs[k].regmap[hr]=f_regmap[hr];
9712 regmap_pre[k+1][hr]=f_regmap[hr];
9713 regs[k].wasdirty&=~(1<<hr);
9714 regs[k].dirty&=~(1<<hr);
9715 regs[k].wasdirty|=(1<<hr)®s[k-1].dirty;
9716 regs[k].dirty|=(1<<hr)®s[k].wasdirty;
9717 regs[k].wasconst&=~(1<<hr);
9718 regs[k].isconst&=~(1<<hr);
9723 //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
9726 assert(regs[i-1].regmap[hr]==f_regmap[hr]);
9727 if(regs[i-1].regmap[hr]==f_regmap[hr]&®map_pre[i][hr]==f_regmap[hr]) {
9728 //printf("OK fill %x (r%d)\n",start+i*4,hr);
9729 regs[i].regmap_entry[hr]=f_regmap[hr];
9730 regs[i].regmap[hr]=f_regmap[hr];
9731 regs[i].wasdirty&=~(1<<hr);
9732 regs[i].dirty&=~(1<<hr);
9733 regs[i].wasdirty|=(1<<hr)®s[i-1].dirty;
9734 regs[i].dirty|=(1<<hr)®s[i-1].dirty;
9735 regs[i].wasconst&=~(1<<hr);
9736 regs[i].isconst&=~(1<<hr);
9737 branch_regs[i].regmap_entry[hr]=f_regmap[hr];
9738 branch_regs[i].wasdirty&=~(1<<hr);
9739 branch_regs[i].wasdirty|=(1<<hr)®s[i].dirty;
9740 branch_regs[i].regmap[hr]=f_regmap[hr];
9741 branch_regs[i].dirty&=~(1<<hr);
9742 branch_regs[i].dirty|=(1<<hr)®s[i].dirty;
9743 branch_regs[i].wasconst&=~(1<<hr);
9744 branch_regs[i].isconst&=~(1<<hr);
9745 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
9746 regmap_pre[i+2][hr]=f_regmap[hr];
9747 regs[i+2].wasdirty&=~(1<<hr);
9748 regs[i+2].wasdirty|=(1<<hr)®s[i].dirty;
9749 assert((branch_regs[i].is32&(1LL<<f_regmap[hr]))==
9750 (regs[i+2].was32&(1LL<<f_regmap[hr])));
9755 regs[k].regmap_entry[hr]=f_regmap[hr];
9756 regs[k].regmap[hr]=f_regmap[hr];
9757 regmap_pre[k+1][hr]=f_regmap[hr];
9758 regs[k+1].wasdirty&=~(1<<hr);
9759 regs[k].dirty&=~(1<<hr);
9760 regs[k].wasconst&=~(1<<hr);
9761 regs[k].isconst&=~(1<<hr);
9763 if(regs[j].regmap[hr]==f_regmap[hr])
9764 regs[j].regmap_entry[hr]=f_regmap[hr];
9768 if(regs[j].regmap[hr]>=0)
9770 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
9771 //printf("no-match due to different register\n");
9774 if((regs[j+1].is32&(1LL<<f_regmap[hr]))!=(regs[j].is32&(1LL<<f_regmap[hr]))) {
9775 //printf("32/64 mismatch %x %d\n",start+j*4,hr);
9778 if(itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS
9779 ||itype[j]==SHIFT||itype[j]==COP1||itype[j]==FLOAT
9780 ||itype[j]==FCOMP||itype[j]==FCONV
9781 ||itype[j]==COP2||itype[j]==C2LS||itype[j]==C2OP) {
9782 if(count_free_regs(regs[j].regmap)<2) {
9783 //printf("No free regs for store %x\n",start+j*4);
9787 else if(itype[j]!=NOP&&itype[j]!=MOV&&itype[j]!=ALU&&itype[j]!=SHIFTIMM&&itype[j]!=IMM16&&itype[j]!=LOAD) break;
9788 if(f_regmap[hr]>=64) {
9789 if(regs[j].is32&(1LL<<(f_regmap[hr]&63))) {
9794 if(get_reg(regs[j].regmap,f_regmap[hr]&63)<0) {
9806 for(hr=0;hr<HOST_REGS;hr++)
9808 if(hr!=EXCLUDE_REG) {
9809 if(regs[i].regmap[hr]>64) {
9810 if(!((regs[i].dirty>>hr)&1))
9811 f_regmap[hr]=regs[i].regmap[hr];
9813 else if(regs[i].regmap[hr]>=0) f_regmap[hr]=regs[i].regmap[hr];
9814 else if(regs[i].regmap[hr]<0) count++;
9817 // Try to restore cycle count at branch targets
9819 for(j=i;j<slen-1;j++) {
9820 if(regs[j].regmap[HOST_CCREG]!=-1) break;
9821 if(itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS
9822 ||itype[j]==SHIFT||itype[j]==COP1||itype[j]==FLOAT
9823 ||itype[j]==FCOMP||itype[j]==FCONV
9824 ||itype[j]==COP2||itype[j]==C2LS||itype[j]==C2OP) {
9825 if(count_free_regs(regs[j].regmap)<2) {
9826 //printf("no free regs for store %x\n",start+j*4);
9831 if(itype[j]!=NOP&&itype[j]!=MOV&&itype[j]!=ALU&&itype[j]!=SHIFTIMM&&itype[j]!=IMM16&&itype[j]!=LOAD) break;
9833 if(regs[j].regmap[HOST_CCREG]==CCREG) {
9835 //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
9837 regs[k].regmap_entry[HOST_CCREG]=CCREG;
9838 regs[k].regmap[HOST_CCREG]=CCREG;
9839 regmap_pre[k+1][HOST_CCREG]=CCREG;
9840 regs[k+1].wasdirty|=1<<HOST_CCREG;
9841 regs[k].dirty|=1<<HOST_CCREG;
9842 regs[k].wasconst&=~(1<<HOST_CCREG);
9843 regs[k].isconst&=~(1<<HOST_CCREG);
9846 regs[j].regmap_entry[HOST_CCREG]=CCREG;
9848 // Work backwards from the branch target
9849 if(j>i&&f_regmap[HOST_CCREG]==CCREG)
9851 //printf("Extend backwards\n");
9854 while(regs[k-1].regmap[HOST_CCREG]==-1) {
9855 if(itype[k-1]==STORE||itype[k-1]==STORELR||itype[k-1]==C1LS
9856 ||itype[k-1]==SHIFT||itype[k-1]==COP1||itype[k-1]==FLOAT
9857 ||itype[k-1]==FCONV||itype[k-1]==FCOMP
9858 ||itype[k-1]==COP2||itype[k-1]==C2LS||itype[k-1]==C2OP) {
9859 if(count_free_regs(regs[k-1].regmap)<2) {
9860 //printf("no free regs for store %x\n",start+(k-1)*4);
9865 if(itype[k-1]!=NOP&&itype[k-1]!=MOV&&itype[k-1]!=ALU&&itype[k-1]!=SHIFTIMM&&itype[k-1]!=IMM16&&itype[k-1]!=LOAD) break;
9868 if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
9869 //printf("Extend CC, %x ->\n",start+k*4);
9871 regs[k].regmap_entry[HOST_CCREG]=CCREG;
9872 regs[k].regmap[HOST_CCREG]=CCREG;
9873 regmap_pre[k+1][HOST_CCREG]=CCREG;
9874 regs[k+1].wasdirty|=1<<HOST_CCREG;
9875 regs[k].dirty|=1<<HOST_CCREG;
9876 regs[k].wasconst&=~(1<<HOST_CCREG);
9877 regs[k].isconst&=~(1<<HOST_CCREG);
9882 //printf("Fail Extend CC, %x ->\n",start+k*4);
9886 if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&&
9887 itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&&
9888 itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1&&itype[i]!=FLOAT&&
9889 itype[i]!=FCONV&&itype[i]!=FCOMP&&
9890 itype[i]!=COP2&&itype[i]!=C2LS&&itype[i]!=C2OP)
9892 memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
9897 // This allocates registers (if possible) one instruction prior
9898 // to use, which can avoid a load-use penalty on certain CPUs.
9899 for(i=0;i<slen-1;i++)
9901 if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP))
9905 if(itype[i]==ALU||itype[i]==MOV||itype[i]==LOAD||itype[i]==SHIFTIMM||itype[i]==IMM16
9906 ||((itype[i]==COP1||itype[i]==COP2)&&opcode2[i]<3))
9909 if((hr=get_reg(regs[i+1].regmap,rs1[i+1]))>=0)
9911 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
9913 regs[i].regmap[hr]=regs[i+1].regmap[hr];
9914 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
9915 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
9916 regs[i].isconst&=~(1<<hr);
9917 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
9918 constmap[i][hr]=constmap[i+1][hr];
9919 regs[i+1].wasdirty&=~(1<<hr);
9920 regs[i].dirty&=~(1<<hr);
9925 if((hr=get_reg(regs[i+1].regmap,rs2[i+1]))>=0)
9927 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
9929 regs[i].regmap[hr]=regs[i+1].regmap[hr];
9930 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
9931 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
9932 regs[i].isconst&=~(1<<hr);
9933 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
9934 constmap[i][hr]=constmap[i+1][hr];
9935 regs[i+1].wasdirty&=~(1<<hr);
9936 regs[i].dirty&=~(1<<hr);
9940 if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
9941 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
9943 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
9945 regs[i].regmap[hr]=rs1[i+1];
9946 regmap_pre[i+1][hr]=rs1[i+1];
9947 regs[i+1].regmap_entry[hr]=rs1[i+1];
9948 regs[i].isconst&=~(1<<hr);
9949 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
9950 constmap[i][hr]=constmap[i+1][hr];
9951 regs[i+1].wasdirty&=~(1<<hr);
9952 regs[i].dirty&=~(1<<hr);
9956 if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
9957 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
9959 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
9961 regs[i].regmap[hr]=rs1[i+1];
9962 regmap_pre[i+1][hr]=rs1[i+1];
9963 regs[i+1].regmap_entry[hr]=rs1[i+1];
9964 regs[i].isconst&=~(1<<hr);
9965 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
9966 constmap[i][hr]=constmap[i+1][hr];
9967 regs[i+1].wasdirty&=~(1<<hr);
9968 regs[i].dirty&=~(1<<hr);
9972 #ifndef HOST_IMM_ADDR32
9973 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
9974 hr=get_reg(regs[i+1].regmap,TLREG);
9976 int sr=get_reg(regs[i+1].regmap,rs1[i+1]);
9977 if(sr>=0&&((regs[i+1].wasconst>>sr)&1)) {
9979 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
9981 regs[i].regmap[hr]=MGEN1+((i+1)&1);
9982 regmap_pre[i+1][hr]=MGEN1+((i+1)&1);
9983 regs[i+1].regmap_entry[hr]=MGEN1+((i+1)&1);
9984 regs[i].isconst&=~(1<<hr);
9985 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
9986 constmap[i][hr]=constmap[i+1][hr];
9987 regs[i+1].wasdirty&=~(1<<hr);
9988 regs[i].dirty&=~(1<<hr);
9990 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
9992 // move it to another register
9993 regs[i+1].regmap[hr]=-1;
9994 regmap_pre[i+2][hr]=-1;
9995 regs[i+1].regmap[nr]=TLREG;
9996 regmap_pre[i+2][nr]=TLREG;
9997 regs[i].regmap[nr]=MGEN1+((i+1)&1);
9998 regmap_pre[i+1][nr]=MGEN1+((i+1)&1);
9999 regs[i+1].regmap_entry[nr]=MGEN1+((i+1)&1);
10000 regs[i].isconst&=~(1<<nr);
10001 regs[i+1].isconst&=~(1<<nr);
10002 regs[i].dirty&=~(1<<nr);
10003 regs[i+1].wasdirty&=~(1<<nr);
10004 regs[i+1].dirty&=~(1<<nr);
10005 regs[i+2].wasdirty&=~(1<<nr);
10011 if(itype[i+1]==STORE||itype[i+1]==STORELR
10012 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
10013 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10014 hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
10015 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10016 else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
10018 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10020 regs[i].regmap[hr]=rs1[i+1];
10021 regmap_pre[i+1][hr]=rs1[i+1];
10022 regs[i+1].regmap_entry[hr]=rs1[i+1];
10023 regs[i].isconst&=~(1<<hr);
10024 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10025 constmap[i][hr]=constmap[i+1][hr];
10026 regs[i+1].wasdirty&=~(1<<hr);
10027 regs[i].dirty&=~(1<<hr);
10031 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
10032 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10034 hr=get_reg(regs[i+1].regmap,FTEMP);
10036 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10038 regs[i].regmap[hr]=rs1[i+1];
10039 regmap_pre[i+1][hr]=rs1[i+1];
10040 regs[i+1].regmap_entry[hr]=rs1[i+1];
10041 regs[i].isconst&=~(1<<hr);
10042 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10043 constmap[i][hr]=constmap[i+1][hr];
10044 regs[i+1].wasdirty&=~(1<<hr);
10045 regs[i].dirty&=~(1<<hr);
10047 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10049 // move it to another register
10050 regs[i+1].regmap[hr]=-1;
10051 regmap_pre[i+2][hr]=-1;
10052 regs[i+1].regmap[nr]=FTEMP;
10053 regmap_pre[i+2][nr]=FTEMP;
10054 regs[i].regmap[nr]=rs1[i+1];
10055 regmap_pre[i+1][nr]=rs1[i+1];
10056 regs[i+1].regmap_entry[nr]=rs1[i+1];
10057 regs[i].isconst&=~(1<<nr);
10058 regs[i+1].isconst&=~(1<<nr);
10059 regs[i].dirty&=~(1<<nr);
10060 regs[i+1].wasdirty&=~(1<<nr);
10061 regs[i+1].dirty&=~(1<<nr);
10062 regs[i+2].wasdirty&=~(1<<nr);
10066 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS||||itype[i+1]==C2LS*/) {
10067 if(itype[i+1]==LOAD)
10068 hr=get_reg(regs[i+1].regmap,rt1[i+1]);
10069 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
10070 hr=get_reg(regs[i+1].regmap,FTEMP);
10071 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
10072 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
10073 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10075 if(hr>=0&®s[i].regmap[hr]<0) {
10076 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
10077 if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
10078 regs[i].regmap[hr]=AGEN1+((i+1)&1);
10079 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
10080 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
10081 regs[i].isconst&=~(1<<hr);
10082 regs[i+1].wasdirty&=~(1<<hr);
10083 regs[i].dirty&=~(1<<hr);
10092 /* Pass 6 - Optimize clean/dirty state */
10093 clean_registers(0,slen-1,1);
10095 /* Pass 7 - Identify 32-bit registers */
10101 for (i=slen-1;i>=0;i--)
10104 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10106 if(ba[i]<start || ba[i]>=(start+slen*4))
10108 // Branch out of this block, don't need anything
10114 // Need whatever matches the target
10115 // (and doesn't get overwritten by the delay slot instruction)
10117 int t=(ba[i]-start)>>2;
10118 if(ba[i]>start+i*4) {
10120 if(!(requires_32bit[t]&~regs[i].was32))
10121 r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10124 //if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
10125 // r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10126 if(!(pr32[t]&~regs[i].was32))
10127 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10130 // Conditional branch may need registers for following instructions
10131 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10134 r32|=requires_32bit[i+2];
10135 r32&=regs[i].was32;
10136 // Mark this address as a branch target since it may be called
10137 // upon return from interrupt
10141 // Merge in delay slot
10143 // These are overwritten unless the branch is "likely"
10144 // and the delay slot is nullified if not taken
10145 r32&=~(1LL<<rt1[i+1]);
10146 r32&=~(1LL<<rt2[i+1]);
10148 // Assume these are needed (delay slot)
10151 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
10155 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
10157 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
10159 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
10161 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
10163 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
10166 else if(itype[i]==SYSCALL||itype[i]==HLECALL)
10168 // SYSCALL instruction (software interrupt)
10171 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
10173 // ERET instruction (return from interrupt)
10177 r32&=~(1LL<<rt1[i]);
10178 r32&=~(1LL<<rt2[i]);
10181 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
10185 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
10187 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
10189 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
10191 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
10193 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
10195 requires_32bit[i]=r32;
10197 // Dirty registers which are 32-bit, require 32-bit input
10198 // as they will be written as 32-bit values
10199 for(hr=0;hr<HOST_REGS;hr++)
10201 if(regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64) {
10202 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
10203 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
10204 requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
10208 //requires_32bit[i]=is32[i]&~unneeded_reg_upper[i]; // DEBUG
10211 if(itype[slen-1]==SPAN) {
10212 bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
10215 /* Debug/disassembly */
10216 if((void*)assem_debug==(void*)printf)
10217 for(i=0;i<slen;i++)
10221 for(r=1;r<=CCREG;r++) {
10222 if((unneeded_reg[i]>>r)&1) {
10223 if(r==HIREG) printf(" HI");
10224 else if(r==LOREG) printf(" LO");
10225 else printf(" r%d",r);
10230 for(r=1;r<=CCREG;r++) {
10231 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
10232 if(r==HIREG) printf(" HI");
10233 else if(r==LOREG) printf(" LO");
10234 else printf(" r%d",r);
10238 for(r=0;r<=CCREG;r++) {
10239 //if(((is32[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10240 if((regs[i].was32>>r)&1) {
10241 if(r==CCREG) printf(" CC");
10242 else if(r==HIREG) printf(" HI");
10243 else if(r==LOREG) printf(" LO");
10244 else printf(" r%d",r);
10249 #if defined(__i386__) || defined(__x86_64__)
10250 printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
10253 printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
10256 if(needed_reg[i]&1) printf("eax ");
10257 if((needed_reg[i]>>1)&1) printf("ecx ");
10258 if((needed_reg[i]>>2)&1) printf("edx ");
10259 if((needed_reg[i]>>3)&1) printf("ebx ");
10260 if((needed_reg[i]>>5)&1) printf("ebp ");
10261 if((needed_reg[i]>>6)&1) printf("esi ");
10262 if((needed_reg[i]>>7)&1) printf("edi ");
10264 for(r=0;r<=CCREG;r++) {
10265 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10266 if((requires_32bit[i]>>r)&1) {
10267 if(r==CCREG) printf(" CC");
10268 else if(r==HIREG) printf(" HI");
10269 else if(r==LOREG) printf(" LO");
10270 else printf(" r%d",r);
10275 for(r=0;r<=CCREG;r++) {
10276 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10277 if((pr32[i]>>r)&1) {
10278 if(r==CCREG) printf(" CC");
10279 else if(r==HIREG) printf(" HI");
10280 else if(r==LOREG) printf(" LO");
10281 else printf(" r%d",r);
10284 if(pr32[i]!=requires_32bit[i]) printf(" OOPS");
10286 #if defined(__i386__) || defined(__x86_64__)
10287 printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
10289 if(regs[i].wasdirty&1) printf("eax ");
10290 if((regs[i].wasdirty>>1)&1) printf("ecx ");
10291 if((regs[i].wasdirty>>2)&1) printf("edx ");
10292 if((regs[i].wasdirty>>3)&1) printf("ebx ");
10293 if((regs[i].wasdirty>>5)&1) printf("ebp ");
10294 if((regs[i].wasdirty>>6)&1) printf("esi ");
10295 if((regs[i].wasdirty>>7)&1) printf("edi ");
10298 printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
10300 if(regs[i].wasdirty&1) printf("r0 ");
10301 if((regs[i].wasdirty>>1)&1) printf("r1 ");
10302 if((regs[i].wasdirty>>2)&1) printf("r2 ");
10303 if((regs[i].wasdirty>>3)&1) printf("r3 ");
10304 if((regs[i].wasdirty>>4)&1) printf("r4 ");
10305 if((regs[i].wasdirty>>5)&1) printf("r5 ");
10306 if((regs[i].wasdirty>>6)&1) printf("r6 ");
10307 if((regs[i].wasdirty>>7)&1) printf("r7 ");
10308 if((regs[i].wasdirty>>8)&1) printf("r8 ");
10309 if((regs[i].wasdirty>>9)&1) printf("r9 ");
10310 if((regs[i].wasdirty>>10)&1) printf("r10 ");
10311 if((regs[i].wasdirty>>12)&1) printf("r12 ");
10314 disassemble_inst(i);
10315 //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
10316 #if defined(__i386__) || defined(__x86_64__)
10317 printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
10318 if(regs[i].dirty&1) printf("eax ");
10319 if((regs[i].dirty>>1)&1) printf("ecx ");
10320 if((regs[i].dirty>>2)&1) printf("edx ");
10321 if((regs[i].dirty>>3)&1) printf("ebx ");
10322 if((regs[i].dirty>>5)&1) printf("ebp ");
10323 if((regs[i].dirty>>6)&1) printf("esi ");
10324 if((regs[i].dirty>>7)&1) printf("edi ");
10327 printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
10328 if(regs[i].dirty&1) printf("r0 ");
10329 if((regs[i].dirty>>1)&1) printf("r1 ");
10330 if((regs[i].dirty>>2)&1) printf("r2 ");
10331 if((regs[i].dirty>>3)&1) printf("r3 ");
10332 if((regs[i].dirty>>4)&1) printf("r4 ");
10333 if((regs[i].dirty>>5)&1) printf("r5 ");
10334 if((regs[i].dirty>>6)&1) printf("r6 ");
10335 if((regs[i].dirty>>7)&1) printf("r7 ");
10336 if((regs[i].dirty>>8)&1) printf("r8 ");
10337 if((regs[i].dirty>>9)&1) printf("r9 ");
10338 if((regs[i].dirty>>10)&1) printf("r10 ");
10339 if((regs[i].dirty>>12)&1) printf("r12 ");
10342 if(regs[i].isconst) {
10343 printf("constants: ");
10344 #if defined(__i386__) || defined(__x86_64__)
10345 if(regs[i].isconst&1) printf("eax=%x ",(int)constmap[i][0]);
10346 if((regs[i].isconst>>1)&1) printf("ecx=%x ",(int)constmap[i][1]);
10347 if((regs[i].isconst>>2)&1) printf("edx=%x ",(int)constmap[i][2]);
10348 if((regs[i].isconst>>3)&1) printf("ebx=%x ",(int)constmap[i][3]);
10349 if((regs[i].isconst>>5)&1) printf("ebp=%x ",(int)constmap[i][5]);
10350 if((regs[i].isconst>>6)&1) printf("esi=%x ",(int)constmap[i][6]);
10351 if((regs[i].isconst>>7)&1) printf("edi=%x ",(int)constmap[i][7]);
10354 if(regs[i].isconst&1) printf("r0=%x ",(int)constmap[i][0]);
10355 if((regs[i].isconst>>1)&1) printf("r1=%x ",(int)constmap[i][1]);
10356 if((regs[i].isconst>>2)&1) printf("r2=%x ",(int)constmap[i][2]);
10357 if((regs[i].isconst>>3)&1) printf("r3=%x ",(int)constmap[i][3]);
10358 if((regs[i].isconst>>4)&1) printf("r4=%x ",(int)constmap[i][4]);
10359 if((regs[i].isconst>>5)&1) printf("r5=%x ",(int)constmap[i][5]);
10360 if((regs[i].isconst>>6)&1) printf("r6=%x ",(int)constmap[i][6]);
10361 if((regs[i].isconst>>7)&1) printf("r7=%x ",(int)constmap[i][7]);
10362 if((regs[i].isconst>>8)&1) printf("r8=%x ",(int)constmap[i][8]);
10363 if((regs[i].isconst>>9)&1) printf("r9=%x ",(int)constmap[i][9]);
10364 if((regs[i].isconst>>10)&1) printf("r10=%x ",(int)constmap[i][10]);
10365 if((regs[i].isconst>>12)&1) printf("r12=%x ",(int)constmap[i][12]);
10371 for(r=0;r<=CCREG;r++) {
10372 if((regs[i].is32>>r)&1) {
10373 if(r==CCREG) printf(" CC");
10374 else if(r==HIREG) printf(" HI");
10375 else if(r==LOREG) printf(" LO");
10376 else printf(" r%d",r);
10382 for(r=0;r<=CCREG;r++) {
10383 if((p32[i]>>r)&1) {
10384 if(r==CCREG) printf(" CC");
10385 else if(r==HIREG) printf(" HI");
10386 else if(r==LOREG) printf(" LO");
10387 else printf(" r%d",r);
10390 if(p32[i]!=regs[i].is32) printf(" NO MATCH\n");
10391 else printf("\n");*/
10392 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10393 #if defined(__i386__) || defined(__x86_64__)
10394 printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
10395 if(branch_regs[i].dirty&1) printf("eax ");
10396 if((branch_regs[i].dirty>>1)&1) printf("ecx ");
10397 if((branch_regs[i].dirty>>2)&1) printf("edx ");
10398 if((branch_regs[i].dirty>>3)&1) printf("ebx ");
10399 if((branch_regs[i].dirty>>5)&1) printf("ebp ");
10400 if((branch_regs[i].dirty>>6)&1) printf("esi ");
10401 if((branch_regs[i].dirty>>7)&1) printf("edi ");
10404 printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
10405 if(branch_regs[i].dirty&1) printf("r0 ");
10406 if((branch_regs[i].dirty>>1)&1) printf("r1 ");
10407 if((branch_regs[i].dirty>>2)&1) printf("r2 ");
10408 if((branch_regs[i].dirty>>3)&1) printf("r3 ");
10409 if((branch_regs[i].dirty>>4)&1) printf("r4 ");
10410 if((branch_regs[i].dirty>>5)&1) printf("r5 ");
10411 if((branch_regs[i].dirty>>6)&1) printf("r6 ");
10412 if((branch_regs[i].dirty>>7)&1) printf("r7 ");
10413 if((branch_regs[i].dirty>>8)&1) printf("r8 ");
10414 if((branch_regs[i].dirty>>9)&1) printf("r9 ");
10415 if((branch_regs[i].dirty>>10)&1) printf("r10 ");
10416 if((branch_regs[i].dirty>>12)&1) printf("r12 ");
10420 for(r=0;r<=CCREG;r++) {
10421 if((branch_regs[i].is32>>r)&1) {
10422 if(r==CCREG) printf(" CC");
10423 else if(r==HIREG) printf(" HI");
10424 else if(r==LOREG) printf(" LO");
10425 else printf(" r%d",r);
10433 /* Pass 8 - Assembly */
10434 linkcount=0;stubcount=0;
10435 ds=0;is_delayslot=0;
10437 uint64_t is32_pre=0;
10439 u_int beginning=(u_int)out;
10440 if((u_int)addr&1) {
10444 for(i=0;i<slen;i++)
10446 //if(ds) printf("ds: ");
10447 if((void*)assem_debug==(void*)printf) disassemble_inst(i);
10449 ds=0; // Skip delay slot
10450 if(bt[i]) assem_debug("OOPS - branch into delay slot\n");
10453 #ifndef DESTRUCTIVE_WRITEBACK
10454 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
10456 wb_sx(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,is32_pre,regs[i].was32,
10457 unneeded_reg[i],unneeded_reg_upper[i]);
10458 wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre,
10459 unneeded_reg[i],unneeded_reg_upper[i]);
10461 is32_pre=regs[i].is32;
10462 dirty_pre=regs[i].dirty;
10465 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
10467 wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32,
10468 unneeded_reg[i],unneeded_reg_upper[i]);
10469 loop_preload(regmap_pre[i],regs[i].regmap_entry);
10471 // branch target entry point
10472 instr_addr[i]=(u_int)out;
10473 assem_debug("<->\n");
10475 if(regs[i].regmap_entry[HOST_CCREG]==CCREG&®s[i].regmap[HOST_CCREG]!=CCREG)
10476 wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32);
10477 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
10478 address_generation(i,®s[i],regs[i].regmap_entry);
10479 load_consts(regmap_pre[i],regs[i].regmap,regs[i].was32,i);
10480 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10482 // Load the delay slot registers if necessary
10483 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
10484 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
10485 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
10486 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
10487 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a)
10488 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
10492 // Preload registers for following instruction
10493 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
10494 if(rs1[i+1]!=rt1[i]&&rs1[i+1]!=rt2[i])
10495 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
10496 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
10497 if(rs2[i+1]!=rt1[i]&&rs2[i+1]!=rt2[i])
10498 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
10500 // TODO: if(is_ooo(i)) address_generation(i+1);
10501 if(itype[i]==CJUMP||itype[i]==FJUMP)
10502 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
10503 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a)
10504 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
10505 if(bt[i]) cop1_usable=0;
10509 alu_assemble(i,®s[i]);break;
10511 imm16_assemble(i,®s[i]);break;
10513 shift_assemble(i,®s[i]);break;
10515 shiftimm_assemble(i,®s[i]);break;
10517 load_assemble(i,®s[i]);break;
10519 loadlr_assemble(i,®s[i]);break;
10521 store_assemble(i,®s[i]);break;
10523 storelr_assemble(i,®s[i]);break;
10525 cop0_assemble(i,®s[i]);break;
10527 cop1_assemble(i,®s[i]);break;
10529 c1ls_assemble(i,®s[i]);break;
10531 cop2_assemble(i,®s[i]);break;
10533 c2ls_assemble(i,®s[i]);break;
10535 c2op_assemble(i,®s[i]);break;
10537 fconv_assemble(i,®s[i]);break;
10539 float_assemble(i,®s[i]);break;
10541 fcomp_assemble(i,®s[i]);break;
10543 multdiv_assemble(i,®s[i]);break;
10545 mov_assemble(i,®s[i]);break;
10547 syscall_assemble(i,®s[i]);break;
10549 hlecall_assemble(i,®s[i]);break;
10551 ujump_assemble(i,®s[i]);ds=1;break;
10553 rjump_assemble(i,®s[i]);ds=1;break;
10555 cjump_assemble(i,®s[i]);ds=1;break;
10557 sjump_assemble(i,®s[i]);ds=1;break;
10559 fjump_assemble(i,®s[i]);ds=1;break;
10561 pagespan_assemble(i,®s[i]);break;
10563 if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
10564 literal_pool(1024);
10566 literal_pool_jumpover(256);
10569 //assert(itype[i-2]==UJUMP||itype[i-2]==RJUMP||(source[i-2]>>16)==0x1000);
10570 // If the block did not end with an unconditional branch,
10571 // add a jump to the next instruction.
10573 if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) {
10574 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
10576 if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP&&itype[i-2]!=FJUMP) {
10577 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
10578 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
10579 emit_loadreg(CCREG,HOST_CCREG);
10580 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
10582 else if(!likely[i-2])
10584 store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].is32,branch_regs[i-2].dirty,start+i*4);
10585 assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
10589 store_regs_bt(regs[i-2].regmap,regs[i-2].is32,regs[i-2].dirty,start+i*4);
10590 assert(regs[i-2].regmap[HOST_CCREG]==CCREG);
10592 add_to_linker((int)out,start+i*4,0);
10599 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
10600 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
10601 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
10602 emit_loadreg(CCREG,HOST_CCREG);
10603 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
10604 add_to_linker((int)out,start+i*4,0);
10608 // TODO: delay slot stubs?
10610 for(i=0;i<stubcount;i++)
10612 switch(stubs[i][0])
10620 do_readstub(i);break;
10625 do_writestub(i);break;
10627 do_ccstub(i);break;
10629 do_invstub(i);break;
10631 do_cop1stub(i);break;
10633 do_unalignedwritestub(i);break;
10637 /* Pass 9 - Linker */
10638 for(i=0;i<linkcount;i++)
10640 assem_debug("%8x -> %8x\n",link_addr[i][0],link_addr[i][1]);
10642 if(!link_addr[i][2])
10645 void *addr=check_addr(link_addr[i][1]);
10646 emit_extjump(link_addr[i][0],link_addr[i][1]);
10648 set_jump_target(link_addr[i][0],(int)addr);
10649 add_link(link_addr[i][1],stub);
10651 else set_jump_target(link_addr[i][0],(int)stub);
10656 int target=(link_addr[i][1]-start)>>2;
10657 assert(target>=0&&target<slen);
10658 assert(instr_addr[target]);
10659 //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
10660 //set_jump_target_fillslot(link_addr[i][0],instr_addr[target],link_addr[i][2]>>1);
10662 set_jump_target(link_addr[i][0],instr_addr[target]);
10666 // External Branch Targets (jump_in)
10667 if(copy+slen*4>(void *)shadow+sizeof(shadow)) copy=shadow;
10668 for(i=0;i<slen;i++)
10672 if(instr_addr[i]) // TODO - delay slots (=null)
10674 u_int vaddr=start+i*4;
10675 u_int page=get_page(vaddr);
10676 u_int vpage=get_vpage(vaddr);
10678 //if(!(is32[i]&(~unneeded_reg_upper[i])&~(1LL<<CCREG)))
10679 if(!requires_32bit[i])
10681 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
10682 assem_debug("jump_in: %x\n",start+i*4);
10683 ll_add(jump_dirty+vpage,vaddr,(void *)out);
10684 int entry_point=do_dirty_stub(i);
10685 ll_add(jump_in+page,vaddr,(void *)entry_point);
10686 // If there was an existing entry in the hash table,
10687 // replace it with the new address.
10688 // Don't add new entries. We'll insert the
10689 // ones that actually get used in check_addr().
10690 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
10691 if(ht_bin[0]==vaddr) {
10692 ht_bin[1]=entry_point;
10694 if(ht_bin[2]==vaddr) {
10695 ht_bin[3]=entry_point;
10700 u_int r=requires_32bit[i]|!!(requires_32bit[i]>>32);
10701 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
10702 assem_debug("jump_in: %x (restricted - %x)\n",start+i*4,r);
10703 //int entry_point=(int)out;
10704 ////assem_debug("entry_point: %x\n",entry_point);
10705 //load_regs_entry(i);
10706 //if(entry_point==(int)out)
10707 // entry_point=instr_addr[i];
10709 // emit_jmp(instr_addr[i]);
10710 //ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
10711 ll_add_32(jump_dirty+vpage,vaddr,r,(void *)out);
10712 int entry_point=do_dirty_stub(i);
10713 ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
10718 // Write out the literal pool if necessary
10720 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
10722 if(((u_int)out)&7) emit_addnop(13);
10724 assert((u_int)out-beginning<MAX_OUTPUT_BLOCK_SIZE);
10725 //printf("shadow buffer: %x-%x\n",(int)copy,(int)copy+slen*4);
10726 memcpy(copy,source,slen*4);
10730 __clear_cache((void *)beginning,out);
10733 // If we're within 256K of the end of the buffer,
10734 // start over from the beginning. (Is 256K enough?)
10735 if((int)out>BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR;
10737 // Trap writes to any of the pages we compiled
10738 for(i=start>>12;i<=(start+slen*4)>>12;i++) {
10740 #ifndef DISABLE_TLB
10741 memory_map[i]|=0x40000000;
10742 if((signed int)start>=(signed int)0xC0000000) {
10744 j=(((u_int)i<<12)+(memory_map[i]<<2)-(u_int)rdram+(u_int)0x80000000)>>12;
10746 memory_map[j]|=0x40000000;
10747 //printf("write protect physical page: %x (virtual %x)\n",j<<12,start);
10752 /* Pass 10 - Free memory by expiring oldest blocks */
10754 int end=((((int)out-BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535;
10755 while(expirep!=end)
10757 int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
10758 int base=BASE_ADDR+((expirep>>13)<<shift); // Base address of this block
10759 inv_debug("EXP: Phase %d\n",expirep);
10760 switch((expirep>>11)&3)
10763 // Clear jump_in and jump_dirty
10764 ll_remove_matching_addrs(jump_in+(expirep&2047),base,shift);
10765 ll_remove_matching_addrs(jump_dirty+(expirep&2047),base,shift);
10766 ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base,shift);
10767 ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base,shift);
10771 ll_kill_pointers(jump_out[expirep&2047],base,shift);
10772 ll_kill_pointers(jump_out[(expirep&2047)+2048],base,shift);
10775 // Clear hash table
10776 for(i=0;i<32;i++) {
10777 int *ht_bin=hash_table[((expirep&2047)<<5)+i];
10778 if((ht_bin[3]>>shift)==(base>>shift) ||
10779 ((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
10780 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[2],ht_bin[3]);
10781 ht_bin[2]=ht_bin[3]=-1;
10783 if((ht_bin[1]>>shift)==(base>>shift) ||
10784 ((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
10785 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[0],ht_bin[1]);
10786 ht_bin[0]=ht_bin[2];
10787 ht_bin[1]=ht_bin[3];
10788 ht_bin[2]=ht_bin[3]=-1;
10795 if((expirep&2047)==0)
10796 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
10798 ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);
10799 ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base,shift);
10802 expirep=(expirep+1)&65535;
10807 // vim:shiftwidth=2:expandtab