1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
3 * Copyright (C) 2009-2011 Ari64 *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
22 #include <stdint.h> //include for uint64_t
26 #include "emu_if.h" //emulator interface
29 //#define assem_debug printf
30 //#define inv_debug printf
31 #define assem_debug(...)
32 #define inv_debug(...)
35 #include "assem_x86.h"
38 #include "assem_x64.h"
41 #include "assem_arm.h"
45 #define __clear_cache(start,end) msync(start, (size_t)((void*)end - (void*)start), MS_SYNC | MS_CACHE_ONLY | MS_INVALIDATE_ICACHE);
49 #define MAX_OUTPUT_BLOCK_SIZE 262144
53 signed char regmap_entry[HOST_REGS];
54 signed char regmap[HOST_REGS];
63 u_int loadedconst; // host regs that have constants loaded
64 u_int waswritten; // MIPS regs that were used as store base before
72 struct ll_entry *next;
78 char insn[MAXBLOCK][10];
79 u_char itype[MAXBLOCK];
80 u_char opcode[MAXBLOCK];
81 u_char opcode2[MAXBLOCK];
89 u_char dep1[MAXBLOCK];
90 u_char dep2[MAXBLOCK];
92 static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
93 static uint64_t gte_rt[MAXBLOCK];
94 static uint64_t gte_unneeded[MAXBLOCK];
95 static u_int smrv[32]; // speculated MIPS register values
96 static u_int smrv_strong; // mask or regs that are likely to have correct values
97 static u_int smrv_weak; // same, but somewhat less likely
98 static u_int smrv_strong_next; // same, but after current insn executes
99 static u_int smrv_weak_next;
102 char likely[MAXBLOCK];
103 char is_ds[MAXBLOCK];
105 uint64_t unneeded_reg[MAXBLOCK];
106 uint64_t unneeded_reg_upper[MAXBLOCK];
107 uint64_t branch_unneeded_reg[MAXBLOCK];
108 uint64_t branch_unneeded_reg_upper[MAXBLOCK];
109 uint64_t p32[MAXBLOCK];
110 uint64_t pr32[MAXBLOCK];
111 signed char regmap_pre[MAXBLOCK][HOST_REGS];
112 static uint64_t current_constmap[HOST_REGS];
113 static uint64_t constmap[MAXBLOCK][HOST_REGS];
114 static struct regstat regs[MAXBLOCK];
115 static struct regstat branch_regs[MAXBLOCK];
116 signed char minimum_free_regs[MAXBLOCK];
117 u_int needed_reg[MAXBLOCK];
118 uint64_t requires_32bit[MAXBLOCK];
119 u_int wont_dirty[MAXBLOCK];
120 u_int will_dirty[MAXBLOCK];
123 u_int instr_addr[MAXBLOCK];
124 u_int link_addr[MAXBLOCK][3];
126 u_int stubs[MAXBLOCK*3][8];
128 u_int literals[1024][2];
133 struct ll_entry *jump_in[4096];
134 struct ll_entry *jump_out[4096];
135 struct ll_entry *jump_dirty[4096];
136 u_int hash_table[65536][4] __attribute__((aligned(16)));
137 char shadow[1048576] __attribute__((aligned(16)));
143 static const u_int using_tlb=0;
145 int new_dynarec_did_compile;
146 int new_dynarec_hacks;
147 u_int stop_after_jal;
149 static u_int ram_offset;
151 static const u_int ram_offset=0;
153 extern u_char restore_candidate[512];
154 extern int cycle_count;
156 /* registers that may be allocated */
158 #define HIREG 32 // hi
159 #define LOREG 33 // lo
160 #define FSREG 34 // FPU status (FCSR)
161 #define CSREG 35 // Coprocessor status
162 #define CCREG 36 // Cycle count
163 #define INVCP 37 // Pointer to invalid_code
164 #define MMREG 38 // Pointer to memory_map
165 #define ROREG 39 // ram offset (if rdram!=0x80000000)
167 #define FTEMP 40 // FPU temporary register
168 #define PTEMP 41 // Prefetch temporary register
169 #define TLREG 42 // TLB mapping offset
170 #define RHASH 43 // Return address hash
171 #define RHTBL 44 // Return address hash table address
172 #define RTEMP 45 // JR/JALR address register
174 #define AGEN1 46 // Address generation temporary register
175 #define AGEN2 47 // Address generation temporary register
176 #define MGEN1 48 // Maptable address generation temporary register
177 #define MGEN2 49 // Maptable address generation temporary register
178 #define BTREG 50 // Branch target temporary register
180 /* instruction types */
181 #define NOP 0 // No operation
182 #define LOAD 1 // Load
183 #define STORE 2 // Store
184 #define LOADLR 3 // Unaligned load
185 #define STORELR 4 // Unaligned store
186 #define MOV 5 // Move
187 #define ALU 6 // Arithmetic/logic
188 #define MULTDIV 7 // Multiply/divide
189 #define SHIFT 8 // Shift by register
190 #define SHIFTIMM 9// Shift by immediate
191 #define IMM16 10 // 16-bit immediate
192 #define RJUMP 11 // Unconditional jump to register
193 #define UJUMP 12 // Unconditional jump
194 #define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
195 #define SJUMP 14 // Conditional branch (regimm format)
196 #define COP0 15 // Coprocessor 0
197 #define COP1 16 // Coprocessor 1
198 #define C1LS 17 // Coprocessor 1 load/store
199 #define FJUMP 18 // Conditional branch (floating point)
200 #define FLOAT 19 // Floating point unit
201 #define FCONV 20 // Convert integer to float
202 #define FCOMP 21 // Floating point compare (sets FSREG)
203 #define SYSCALL 22// SYSCALL
204 #define OTHER 23 // Other
205 #define SPAN 24 // Branch/delay slot spans 2 pages
206 #define NI 25 // Not implemented
207 #define HLECALL 26// PCSX fake opcodes for HLE
208 #define COP2 27 // Coprocessor 2 move
209 #define C2LS 28 // Coprocessor 2 load/store
210 #define C2OP 29 // Coprocessor 2 operation
211 #define INTCALL 30// Call interpreter to handle rare corner cases
220 #define LOADBU_STUB 7
221 #define LOADHU_STUB 8
222 #define STOREB_STUB 9
223 #define STOREH_STUB 10
224 #define STOREW_STUB 11
225 #define STORED_STUB 12
226 #define STORELR_STUB 13
227 #define INVCODE_STUB 14
235 int new_recompile_block(int addr);
236 void *get_addr_ht(u_int vaddr);
237 void invalidate_block(u_int block);
238 void invalidate_addr(u_int addr);
239 void remove_hash(int vaddr);
242 void dyna_linker_ds();
244 void verify_code_vm();
245 void verify_code_ds();
248 void fp_exception_ds();
250 void jump_syscall_hle();
254 void new_dyna_leave();
259 void read_nomem_new();
260 void read_nomemb_new();
261 void read_nomemh_new();
262 void read_nomemd_new();
263 void write_nomem_new();
264 void write_nomemb_new();
265 void write_nomemh_new();
266 void write_nomemd_new();
267 void write_rdram_new();
268 void write_rdramb_new();
269 void write_rdramh_new();
270 void write_rdramd_new();
271 extern u_int memory_map[1048576];
273 // Needed by assembler
274 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
275 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
276 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
277 void load_all_regs(signed char i_regmap[]);
278 void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
279 void load_regs_entry(int t);
280 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
284 //#define DEBUG_CYCLE_COUNT 1
286 #define NO_CYCLE_PENALTY_THR 12
288 int cycle_multiplier; // 100 for 1.0
290 static int CLOCK_ADJUST(int x)
293 return (x * cycle_multiplier + s * 50) / 100;
296 static void tlb_hacks()
300 if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
304 switch (ROM_HEADER->Country_code&0xFF)
316 // Unknown country code
320 u_int rom_addr=(u_int)rom;
322 // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
323 // in the lower 4G of memory to use this hack. Copy it if necessary.
324 if((void *)rom>(void *)0xffffffff) {
325 munmap(ROM_COPY, 67108864);
326 if(mmap(ROM_COPY, 12582912,
327 PROT_READ | PROT_WRITE,
328 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
329 -1, 0) <= 0) {printf("mmap() failed\n");}
330 memcpy(ROM_COPY,rom,12582912);
331 rom_addr=(u_int)ROM_COPY;
335 for(n=0x7F000;n<0x80000;n++) {
336 memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
343 static u_int get_page(u_int vaddr)
346 u_int page=(vaddr^0x80000000)>>12;
348 u_int page=vaddr&~0xe0000000;
349 if (page < 0x1000000)
350 page &= ~0x0e00000; // RAM mirrors
354 if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
356 if(page>2048) page=2048+(page&2047);
361 static u_int get_vpage(u_int vaddr)
363 u_int vpage=(vaddr^0x80000000)>>12;
365 if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
367 if(vpage>2048) vpage=2048+(vpage&2047);
371 // no virtual mem in PCSX
372 static u_int get_vpage(u_int vaddr)
374 return get_page(vaddr);
378 // Get address from virtual address
379 // This is called from the recompiled JR/JALR instructions
380 void *get_addr(u_int vaddr)
382 u_int page=get_page(vaddr);
383 u_int vpage=get_vpage(vaddr);
384 struct ll_entry *head;
385 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
388 if(head->vaddr==vaddr&&head->reg32==0) {
389 //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
390 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
393 ht_bin[1]=(int)head->addr;
399 head=jump_dirty[vpage];
401 if(head->vaddr==vaddr&&head->reg32==0) {
402 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
403 // Don't restore blocks which are about to expire from the cache
404 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
405 if(verify_dirty(head->addr)) {
406 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
407 invalid_code[vaddr>>12]=0;
408 inv_code_start=inv_code_end=~0;
410 memory_map[vaddr>>12]|=0x40000000;
414 if(tlb_LUT_r[vaddr>>12]) {
415 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
416 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
419 restore_candidate[vpage>>3]|=1<<(vpage&7);
421 else restore_candidate[page>>3]|=1<<(page&7);
422 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
423 if(ht_bin[0]==vaddr) {
424 ht_bin[1]=(int)head->addr; // Replace existing entry
430 ht_bin[1]=(int)head->addr;
438 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
439 int r=new_recompile_block(vaddr);
440 if(r==0) return get_addr(vaddr);
441 // Execute in unmapped page, generate pagefault execption
443 Cause=(vaddr<<31)|0x8;
444 EPC=(vaddr&1)?vaddr-5:vaddr;
446 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
447 EntryHi=BadVAddr&0xFFFFE000;
448 return get_addr_ht(0x80000000);
450 // Look up address in hash table first
451 void *get_addr_ht(u_int vaddr)
453 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
454 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
455 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
456 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
457 return get_addr(vaddr);
460 void *get_addr_32(u_int vaddr,u_int flags)
463 return get_addr(vaddr);
465 //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
466 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
467 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
468 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
469 u_int page=get_page(vaddr);
470 u_int vpage=get_vpage(vaddr);
471 struct ll_entry *head;
474 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
475 //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
477 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
479 ht_bin[1]=(int)head->addr;
481 }else if(ht_bin[2]==-1) {
482 ht_bin[3]=(int)head->addr;
485 //ht_bin[3]=ht_bin[1];
486 //ht_bin[2]=ht_bin[0];
487 //ht_bin[1]=(int)head->addr;
494 head=jump_dirty[vpage];
496 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
497 //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
498 // Don't restore blocks which are about to expire from the cache
499 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
500 if(verify_dirty(head->addr)) {
501 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
502 invalid_code[vaddr>>12]=0;
503 inv_code_start=inv_code_end=~0;
504 memory_map[vaddr>>12]|=0x40000000;
507 if(tlb_LUT_r[vaddr>>12]) {
508 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
509 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
512 restore_candidate[vpage>>3]|=1<<(vpage&7);
514 else restore_candidate[page>>3]|=1<<(page&7);
516 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
518 ht_bin[1]=(int)head->addr;
520 }else if(ht_bin[2]==-1) {
521 ht_bin[3]=(int)head->addr;
524 //ht_bin[3]=ht_bin[1];
525 //ht_bin[2]=ht_bin[0];
526 //ht_bin[1]=(int)head->addr;
534 //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
535 int r=new_recompile_block(vaddr);
536 if(r==0) return get_addr(vaddr);
537 // Execute in unmapped page, generate pagefault execption
539 Cause=(vaddr<<31)|0x8;
540 EPC=(vaddr&1)?vaddr-5:vaddr;
542 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
543 EntryHi=BadVAddr&0xFFFFE000;
544 return get_addr_ht(0x80000000);
548 void clear_all_regs(signed char regmap[])
551 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
554 signed char get_reg(signed char regmap[],int r)
557 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map[hr]==r) return hr;
561 // Find a register that is available for two consecutive cycles
562 signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
565 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map1[hr]==r&®map2[hr]==r) return hr;
569 int count_free_regs(signed char regmap[])
573 for(hr=0;hr<HOST_REGS;hr++)
575 if(hr!=EXCLUDE_REG) {
576 if(regmap[hr]<0) count++;
582 void dirty_reg(struct regstat *cur,signed char reg)
586 for (hr=0;hr<HOST_REGS;hr++) {
587 if((cur->regmap[hr]&63)==reg) {
593 // If we dirty the lower half of a 64 bit register which is now being
594 // sign-extended, we need to dump the upper half.
595 // Note: Do this only after completion of the instruction, because
596 // some instructions may need to read the full 64-bit value even if
597 // overwriting it (eg SLTI, DSRA32).
598 static void flush_dirty_uppers(struct regstat *cur)
601 for (hr=0;hr<HOST_REGS;hr++) {
602 if((cur->dirty>>hr)&1) {
605 if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
610 void set_const(struct regstat *cur,signed char reg,uint64_t value)
614 for (hr=0;hr<HOST_REGS;hr++) {
615 if(cur->regmap[hr]==reg) {
617 current_constmap[hr]=value;
619 else if((cur->regmap[hr]^64)==reg) {
621 current_constmap[hr]=value>>32;
626 void clear_const(struct regstat *cur,signed char reg)
630 for (hr=0;hr<HOST_REGS;hr++) {
631 if((cur->regmap[hr]&63)==reg) {
632 cur->isconst&=~(1<<hr);
637 int is_const(struct regstat *cur,signed char reg)
642 for (hr=0;hr<HOST_REGS;hr++) {
643 if((cur->regmap[hr]&63)==reg) {
644 return (cur->isconst>>hr)&1;
649 uint64_t get_const(struct regstat *cur,signed char reg)
653 for (hr=0;hr<HOST_REGS;hr++) {
654 if(cur->regmap[hr]==reg) {
655 return current_constmap[hr];
658 printf("Unknown constant in r%d\n",reg);
662 // Least soon needed registers
663 // Look at the next ten instructions and see which registers
664 // will be used. Try not to reallocate these.
665 void lsn(u_char hsn[], int i, int *preferred_reg)
675 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
677 // Don't go past an unconditonal jump
684 if(rs1[i+j]) hsn[rs1[i+j]]=j;
685 if(rs2[i+j]) hsn[rs2[i+j]]=j;
686 if(rt1[i+j]) hsn[rt1[i+j]]=j;
687 if(rt2[i+j]) hsn[rt2[i+j]]=j;
688 if(itype[i+j]==STORE || itype[i+j]==STORELR) {
689 // Stores can allocate zero
693 // On some architectures stores need invc_ptr
694 #if defined(HOST_IMM8)
695 if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
699 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
707 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
709 // Follow first branch
710 int t=(ba[i+b]-start)>>2;
711 j=7-b;if(t+j>=slen) j=slen-t-1;
714 if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
715 if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
716 //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
717 //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
720 // TODO: preferred register based on backward branch
722 // Delay slot should preferably not overwrite branch conditions or cycle count
723 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
724 if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
725 if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
731 // Coprocessor load/store needs FTEMP, even if not declared
732 if(itype[i]==C1LS||itype[i]==C2LS) {
735 // Load L/R also uses FTEMP as a temporary register
736 if(itype[i]==LOADLR) {
739 // Also SWL/SWR/SDL/SDR
740 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
743 // Don't remove the TLB registers either
744 if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
747 // Don't remove the miniht registers
748 if(itype[i]==UJUMP||itype[i]==RJUMP)
755 // We only want to allocate registers if we're going to use them again soon
756 int needed_again(int r, int i)
762 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
764 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
765 return 0; // Don't need any registers if exiting the block
773 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
775 // Don't go past an unconditonal jump
779 if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
786 if(rs1[i+j]==r) rn=j;
787 if(rs2[i+j]==r) rn=j;
788 if((unneeded_reg[i+j]>>r)&1) rn=10;
789 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
797 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
799 // Follow first branch
801 int t=(ba[i+b]-start)>>2;
802 j=7-b;if(t+j>=slen) j=slen-t-1;
805 if(!((unneeded_reg[t+j]>>r)&1)) {
806 if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
807 if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
817 // Try to match register allocations at the end of a loop with those
819 int loop_reg(int i, int r, int hr)
828 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
830 // Don't go past an unconditonal jump
837 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
842 if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
843 if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
844 if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
846 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
848 int t=(ba[i+k]-start)>>2;
849 int reg=get_reg(regs[t].regmap_entry,r);
850 if(reg>=0) return reg;
851 //reg=get_reg(regs[t+1].regmap_entry,r);
852 //if(reg>=0) return reg;
860 // Allocate every register, preserving source/target regs
861 void alloc_all(struct regstat *cur,int i)
865 for(hr=0;hr<HOST_REGS;hr++) {
866 if(hr!=EXCLUDE_REG) {
867 if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
868 ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
871 cur->dirty&=~(1<<hr);
874 if((cur->regmap[hr]&63)==0)
877 cur->dirty&=~(1<<hr);
884 void div64(int64_t dividend,int64_t divisor)
888 //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
889 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
891 void divu64(uint64_t dividend,uint64_t divisor)
895 //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
896 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
899 void mult64(uint64_t m1,uint64_t m2)
901 unsigned long long int op1, op2, op3, op4;
902 unsigned long long int result1, result2, result3, result4;
903 unsigned long long int temp1, temp2, temp3, temp4;
919 op1 = op2 & 0xFFFFFFFF;
920 op2 = (op2 >> 32) & 0xFFFFFFFF;
921 op3 = op4 & 0xFFFFFFFF;
922 op4 = (op4 >> 32) & 0xFFFFFFFF;
925 temp2 = (temp1 >> 32) + op1 * op4;
927 temp4 = (temp3 >> 32) + op2 * op4;
929 result1 = temp1 & 0xFFFFFFFF;
930 result2 = temp2 + (temp3 & 0xFFFFFFFF);
931 result3 = (result2 >> 32) + temp4;
932 result4 = (result3 >> 32);
934 lo = result1 | (result2 << 32);
935 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
944 void multu64(uint64_t m1,uint64_t m2)
946 unsigned long long int op1, op2, op3, op4;
947 unsigned long long int result1, result2, result3, result4;
948 unsigned long long int temp1, temp2, temp3, temp4;
950 op1 = m1 & 0xFFFFFFFF;
951 op2 = (m1 >> 32) & 0xFFFFFFFF;
952 op3 = m2 & 0xFFFFFFFF;
953 op4 = (m2 >> 32) & 0xFFFFFFFF;
956 temp2 = (temp1 >> 32) + op1 * op4;
958 temp4 = (temp3 >> 32) + op2 * op4;
960 result1 = temp1 & 0xFFFFFFFF;
961 result2 = temp2 + (temp3 & 0xFFFFFFFF);
962 result3 = (result2 >> 32) + temp4;
963 result4 = (result3 >> 32);
965 lo = result1 | (result2 << 32);
966 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
968 //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
969 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
972 uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
980 else original=loaded;
983 uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
986 original>>=64-(bits^56);
987 original<<=64-(bits^56);
991 else original=loaded;
997 #include "assem_x86.c"
1000 #include "assem_x64.c"
1003 #include "assem_arm.c"
1006 // Add virtual address mapping to linked list
1007 void ll_add(struct ll_entry **head,int vaddr,void *addr)
1009 struct ll_entry *new_entry;
1010 new_entry=malloc(sizeof(struct ll_entry));
1011 assert(new_entry!=NULL);
1012 new_entry->vaddr=vaddr;
1014 new_entry->addr=addr;
1015 new_entry->next=*head;
1019 // Add virtual address mapping for 32-bit compiled block
1020 void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
1022 ll_add(head,vaddr,addr);
1024 (*head)->reg32=reg32;
1028 // Check if an address is already compiled
1029 // but don't return addresses which are about to expire from the cache
1030 void *check_addr(u_int vaddr)
1032 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
1033 if(ht_bin[0]==vaddr) {
1034 if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1035 if(isclean(ht_bin[1])) return (void *)ht_bin[1];
1037 if(ht_bin[2]==vaddr) {
1038 if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1039 if(isclean(ht_bin[3])) return (void *)ht_bin[3];
1041 u_int page=get_page(vaddr);
1042 struct ll_entry *head;
1045 if(head->vaddr==vaddr&&head->reg32==0) {
1046 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1047 // Update existing entry with current address
1048 if(ht_bin[0]==vaddr) {
1049 ht_bin[1]=(int)head->addr;
1052 if(ht_bin[2]==vaddr) {
1053 ht_bin[3]=(int)head->addr;
1056 // Insert into hash table with low priority.
1057 // Don't evict existing entries, as they are probably
1058 // addresses that are being accessed frequently.
1060 ht_bin[1]=(int)head->addr;
1062 }else if(ht_bin[2]==-1) {
1063 ht_bin[3]=(int)head->addr;
1074 void remove_hash(int vaddr)
1076 //printf("remove hash: %x\n",vaddr);
1077 int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1078 if(ht_bin[2]==vaddr) {
1079 ht_bin[2]=ht_bin[3]=-1;
1081 if(ht_bin[0]==vaddr) {
1082 ht_bin[0]=ht_bin[2];
1083 ht_bin[1]=ht_bin[3];
1084 ht_bin[2]=ht_bin[3]=-1;
1088 void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1090 struct ll_entry *next;
1092 if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1093 ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1095 inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1096 remove_hash((*head)->vaddr);
1103 head=&((*head)->next);
1108 // Remove all entries from linked list
1109 void ll_clear(struct ll_entry **head)
1111 struct ll_entry *cur;
1112 struct ll_entry *next;
1123 // Dereference the pointers and remove if it matches
1124 void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1127 int ptr=get_pointer(head->addr);
1128 inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1129 if(((ptr>>shift)==(addr>>shift)) ||
1130 (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1132 inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1133 u_int host_addr=(u_int)kill_pointer(head->addr);
1135 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1142 // This is called when we write to a compiled block (see do_invstub)
1143 void invalidate_page(u_int page)
1145 struct ll_entry *head;
1146 struct ll_entry *next;
1150 inv_debug("INVALIDATE: %x\n",head->vaddr);
1151 remove_hash(head->vaddr);
1156 head=jump_out[page];
1159 inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
1160 u_int host_addr=(u_int)kill_pointer(head->addr);
1162 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1170 static void invalidate_block_range(u_int block, u_int first, u_int last)
1172 u_int page=get_page(block<<12);
1173 //printf("first=%d last=%d\n",first,last);
1174 invalidate_page(page);
1175 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1176 assert(last<page+5);
1177 // Invalidate the adjacent pages if a block crosses a 4K boundary
1179 invalidate_page(first);
1182 for(first=page+1;first<last;first++) {
1183 invalidate_page(first);
1189 // Don't trap writes
1190 invalid_code[block]=1;
1192 // If there is a valid TLB entry for this page, remove write protect
1193 if(tlb_LUT_w[block]) {
1194 assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1195 // CHECK: Is this right?
1196 memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1197 u_int real_block=tlb_LUT_w[block]>>12;
1198 invalid_code[real_block]=1;
1199 if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1201 else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
1205 memset(mini_ht,-1,sizeof(mini_ht));
1209 void invalidate_block(u_int block)
1211 u_int page=get_page(block<<12);
1212 u_int vpage=get_vpage(block<<12);
1213 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1214 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1217 struct ll_entry *head;
1218 head=jump_dirty[vpage];
1219 //printf("page=%d vpage=%d\n",page,vpage);
1222 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1223 get_bounds((int)head->addr,&start,&end);
1224 //printf("start: %x end: %x\n",start,end);
1225 if(page<2048&&start>=(u_int)rdram&&end<(u_int)rdram+RAM_SIZE) {
1226 if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1227 if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1228 if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1232 if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1233 if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1234 if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1235 if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1242 invalidate_block_range(block,first,last);
1245 void invalidate_addr(u_int addr)
1249 // this check is done by the caller
1250 //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
1251 u_int page=get_vpage(addr);
1252 if(page<2048) { // RAM
1253 struct ll_entry *head;
1254 u_int addr_min=~0, addr_max=0;
1255 u_int mask=RAM_SIZE-1;
1256 u_int addr_main=0x80000000|(addr&mask);
1258 inv_code_start=addr_main&~0xfff;
1259 inv_code_end=addr_main|0xfff;
1262 // must check previous page too because of spans..
1264 inv_code_start-=0x1000;
1266 for(;pg1<=page;pg1++) {
1267 for(head=jump_dirty[pg1];head!=NULL;head=head->next) {
1269 get_bounds((int)head->addr,&start,&end);
1274 if(start<=addr_main&&addr_main<end) {
1275 if(start<addr_min) addr_min=start;
1276 if(end>addr_max) addr_max=end;
1278 else if(addr_main<start) {
1279 if(start<inv_code_end)
1280 inv_code_end=start-1;
1283 if(end>inv_code_start)
1289 inv_debug("INV ADDR: %08x hit %08x-%08x\n", addr, addr_min, addr_max);
1290 inv_code_start=inv_code_end=~0;
1291 invalidate_block_range(addr>>12,(addr_min&mask)>>12,(addr_max&mask)>>12);
1295 inv_code_start=(addr&~mask)|(inv_code_start&mask);
1296 inv_code_end=(addr&~mask)|(inv_code_end&mask);
1297 inv_debug("INV ADDR: %08x miss, inv %08x-%08x, sk %d\n", addr, inv_code_start, inv_code_end, 0);
1302 invalidate_block(addr>>12);
1305 // This is called when loading a save state.
1306 // Anything could have changed, so invalidate everything.
1307 void invalidate_all_pages()
1310 for(page=0;page<4096;page++)
1311 invalidate_page(page);
1312 for(page=0;page<1048576;page++)
1313 if(!invalid_code[page]) {
1314 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1315 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1318 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1321 memset(mini_ht,-1,sizeof(mini_ht));
1325 for(page=0;page<0x100000;page++) {
1326 if(tlb_LUT_r[page]) {
1327 memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1328 if(!tlb_LUT_w[page]||!invalid_code[page])
1329 memory_map[page]|=0x40000000; // Write protect
1331 else memory_map[page]=-1;
1332 if(page==0x80000) page=0xC0000;
1338 // Add an entry to jump_out after making a link
1339 void add_link(u_int vaddr,void *src)
1341 u_int page=get_page(vaddr);
1342 inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1343 int *ptr=(int *)(src+4);
1344 assert((*ptr&0x0fff0000)==0x059f0000);
1345 ll_add(jump_out+page,vaddr,src);
1346 //int ptr=get_pointer(src);
1347 //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1350 // If a code block was found to be unmodified (bit was set in
1351 // restore_candidate) and it remains unmodified (bit is clear
1352 // in invalid_code) then move the entries for that 4K page from
1353 // the dirty list to the clean list.
1354 void clean_blocks(u_int page)
1356 struct ll_entry *head;
1357 inv_debug("INV: clean_blocks page=%d\n",page);
1358 head=jump_dirty[page];
1360 if(!invalid_code[head->vaddr>>12]) {
1361 // Don't restore blocks which are about to expire from the cache
1362 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1364 if(verify_dirty((int)head->addr)) {
1365 //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1368 get_bounds((int)head->addr,&start,&end);
1369 if(start-(u_int)rdram<RAM_SIZE) {
1370 for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1371 inv|=invalid_code[i];
1375 if((signed int)head->vaddr>=(signed int)0xC0000000) {
1376 u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1377 //printf("addr=%x start=%x end=%x\n",addr,start,end);
1378 if(addr<start||addr>=end) inv=1;
1381 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
1385 void * clean_addr=(void *)get_clean_addr((int)head->addr);
1386 if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1389 if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
1391 inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1392 //printf("page=%x, addr=%x\n",page,head->vaddr);
1393 //assert(head->vaddr>>12==(page|0x80000));
1394 ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1395 int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1397 if(ht_bin[0]==head->vaddr) {
1398 ht_bin[1]=(int)clean_addr; // Replace existing entry
1400 if(ht_bin[2]==head->vaddr) {
1401 ht_bin[3]=(int)clean_addr; // Replace existing entry
1414 void mov_alloc(struct regstat *current,int i)
1416 // Note: Don't need to actually alloc the source registers
1417 if((~current->is32>>rs1[i])&1) {
1418 //alloc_reg64(current,i,rs1[i]);
1419 alloc_reg64(current,i,rt1[i]);
1420 current->is32&=~(1LL<<rt1[i]);
1422 //alloc_reg(current,i,rs1[i]);
1423 alloc_reg(current,i,rt1[i]);
1424 current->is32|=(1LL<<rt1[i]);
1426 clear_const(current,rs1[i]);
1427 clear_const(current,rt1[i]);
1428 dirty_reg(current,rt1[i]);
1431 void shiftimm_alloc(struct regstat *current,int i)
1433 if(opcode2[i]<=0x3) // SLL/SRL/SRA
1436 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1438 alloc_reg(current,i,rt1[i]);
1439 current->is32|=1LL<<rt1[i];
1440 dirty_reg(current,rt1[i]);
1441 if(is_const(current,rs1[i])) {
1442 int v=get_const(current,rs1[i]);
1443 if(opcode2[i]==0x00) set_const(current,rt1[i],v<<imm[i]);
1444 if(opcode2[i]==0x02) set_const(current,rt1[i],(u_int)v>>imm[i]);
1445 if(opcode2[i]==0x03) set_const(current,rt1[i],v>>imm[i]);
1447 else clear_const(current,rt1[i]);
1452 clear_const(current,rs1[i]);
1453 clear_const(current,rt1[i]);
1456 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1459 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1460 alloc_reg64(current,i,rt1[i]);
1461 current->is32&=~(1LL<<rt1[i]);
1462 dirty_reg(current,rt1[i]);
1465 if(opcode2[i]==0x3c) // DSLL32
1468 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1469 alloc_reg64(current,i,rt1[i]);
1470 current->is32&=~(1LL<<rt1[i]);
1471 dirty_reg(current,rt1[i]);
1474 if(opcode2[i]==0x3e) // DSRL32
1477 alloc_reg64(current,i,rs1[i]);
1479 alloc_reg64(current,i,rt1[i]);
1480 current->is32&=~(1LL<<rt1[i]);
1482 alloc_reg(current,i,rt1[i]);
1483 current->is32|=1LL<<rt1[i];
1485 dirty_reg(current,rt1[i]);
1488 if(opcode2[i]==0x3f) // DSRA32
1491 alloc_reg64(current,i,rs1[i]);
1492 alloc_reg(current,i,rt1[i]);
1493 current->is32|=1LL<<rt1[i];
1494 dirty_reg(current,rt1[i]);
1499 void shift_alloc(struct regstat *current,int i)
1502 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1504 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1505 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1506 alloc_reg(current,i,rt1[i]);
1507 if(rt1[i]==rs2[i]) {
1508 alloc_reg_temp(current,i,-1);
1509 minimum_free_regs[i]=1;
1511 current->is32|=1LL<<rt1[i];
1512 } else { // DSLLV/DSRLV/DSRAV
1513 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1514 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1515 alloc_reg64(current,i,rt1[i]);
1516 current->is32&=~(1LL<<rt1[i]);
1517 if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1519 alloc_reg_temp(current,i,-1);
1520 minimum_free_regs[i]=1;
1523 clear_const(current,rs1[i]);
1524 clear_const(current,rs2[i]);
1525 clear_const(current,rt1[i]);
1526 dirty_reg(current,rt1[i]);
1530 void alu_alloc(struct regstat *current,int i)
1532 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1534 if(rs1[i]&&rs2[i]) {
1535 alloc_reg(current,i,rs1[i]);
1536 alloc_reg(current,i,rs2[i]);
1539 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1540 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1542 alloc_reg(current,i,rt1[i]);
1544 current->is32|=1LL<<rt1[i];
1546 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1548 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1550 alloc_reg64(current,i,rs1[i]);
1551 alloc_reg64(current,i,rs2[i]);
1552 alloc_reg(current,i,rt1[i]);
1554 alloc_reg(current,i,rs1[i]);
1555 alloc_reg(current,i,rs2[i]);
1556 alloc_reg(current,i,rt1[i]);
1559 current->is32|=1LL<<rt1[i];
1561 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1563 if(rs1[i]&&rs2[i]) {
1564 alloc_reg(current,i,rs1[i]);
1565 alloc_reg(current,i,rs2[i]);
1569 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1570 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1572 alloc_reg(current,i,rt1[i]);
1573 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1575 if(!((current->uu>>rt1[i])&1)) {
1576 alloc_reg64(current,i,rt1[i]);
1578 if(get_reg(current->regmap,rt1[i]|64)>=0) {
1579 if(rs1[i]&&rs2[i]) {
1580 alloc_reg64(current,i,rs1[i]);
1581 alloc_reg64(current,i,rs2[i]);
1585 // Is is really worth it to keep 64-bit values in registers?
1587 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1588 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1592 current->is32&=~(1LL<<rt1[i]);
1594 current->is32|=1LL<<rt1[i];
1598 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1600 if(rs1[i]&&rs2[i]) {
1601 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1602 alloc_reg64(current,i,rs1[i]);
1603 alloc_reg64(current,i,rs2[i]);
1604 alloc_reg64(current,i,rt1[i]);
1606 alloc_reg(current,i,rs1[i]);
1607 alloc_reg(current,i,rs2[i]);
1608 alloc_reg(current,i,rt1[i]);
1612 alloc_reg(current,i,rt1[i]);
1613 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1614 // DADD used as move, or zeroing
1615 // If we have a 64-bit source, then make the target 64 bits too
1616 if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1617 if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1618 alloc_reg64(current,i,rt1[i]);
1619 } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1620 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1621 alloc_reg64(current,i,rt1[i]);
1623 if(opcode2[i]>=0x2e&&rs2[i]) {
1624 // DSUB used as negation - 64-bit result
1625 // If we have a 32-bit register, extend it to 64 bits
1626 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1627 alloc_reg64(current,i,rt1[i]);
1631 if(rs1[i]&&rs2[i]) {
1632 current->is32&=~(1LL<<rt1[i]);
1634 current->is32&=~(1LL<<rt1[i]);
1635 if((current->is32>>rs1[i])&1)
1636 current->is32|=1LL<<rt1[i];
1638 current->is32&=~(1LL<<rt1[i]);
1639 if((current->is32>>rs2[i])&1)
1640 current->is32|=1LL<<rt1[i];
1642 current->is32|=1LL<<rt1[i];
1646 clear_const(current,rs1[i]);
1647 clear_const(current,rs2[i]);
1648 clear_const(current,rt1[i]);
1649 dirty_reg(current,rt1[i]);
1652 void imm16_alloc(struct regstat *current,int i)
1654 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1656 if(rt1[i]) alloc_reg(current,i,rt1[i]);
1657 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1658 current->is32&=~(1LL<<rt1[i]);
1659 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1660 // TODO: Could preserve the 32-bit flag if the immediate is zero
1661 alloc_reg64(current,i,rt1[i]);
1662 alloc_reg64(current,i,rs1[i]);
1664 clear_const(current,rs1[i]);
1665 clear_const(current,rt1[i]);
1667 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1668 if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1669 current->is32|=1LL<<rt1[i];
1670 clear_const(current,rs1[i]);
1671 clear_const(current,rt1[i]);
1673 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1674 if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1675 if(rs1[i]!=rt1[i]) {
1676 if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1677 alloc_reg64(current,i,rt1[i]);
1678 current->is32&=~(1LL<<rt1[i]);
1681 else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1682 if(is_const(current,rs1[i])) {
1683 int v=get_const(current,rs1[i]);
1684 if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1685 if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1686 if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1688 else clear_const(current,rt1[i]);
1690 else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1691 if(is_const(current,rs1[i])) {
1692 int v=get_const(current,rs1[i]);
1693 set_const(current,rt1[i],v+imm[i]);
1695 else clear_const(current,rt1[i]);
1696 current->is32|=1LL<<rt1[i];
1699 set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1700 current->is32|=1LL<<rt1[i];
1702 dirty_reg(current,rt1[i]);
1705 void load_alloc(struct regstat *current,int i)
1707 clear_const(current,rt1[i]);
1708 //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1709 if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1710 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1711 if(rt1[i]&&!((current->u>>rt1[i])&1)) {
1712 alloc_reg(current,i,rt1[i]);
1713 assert(get_reg(current->regmap,rt1[i])>=0);
1714 if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1716 current->is32&=~(1LL<<rt1[i]);
1717 alloc_reg64(current,i,rt1[i]);
1719 else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1721 current->is32&=~(1LL<<rt1[i]);
1722 alloc_reg64(current,i,rt1[i]);
1723 alloc_all(current,i);
1724 alloc_reg64(current,i,FTEMP);
1725 minimum_free_regs[i]=HOST_REGS;
1727 else current->is32|=1LL<<rt1[i];
1728 dirty_reg(current,rt1[i]);
1729 // If using TLB, need a register for pointer to the mapping table
1730 if(using_tlb) alloc_reg(current,i,TLREG);
1731 // LWL/LWR need a temporary register for the old value
1732 if(opcode[i]==0x22||opcode[i]==0x26)
1734 alloc_reg(current,i,FTEMP);
1735 alloc_reg_temp(current,i,-1);
1736 minimum_free_regs[i]=1;
1741 // Load to r0 or unneeded register (dummy load)
1742 // but we still need a register to calculate the address
1743 if(opcode[i]==0x22||opcode[i]==0x26)
1745 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1747 // If using TLB, need a register for pointer to the mapping table
1748 if(using_tlb) alloc_reg(current,i,TLREG);
1749 alloc_reg_temp(current,i,-1);
1750 minimum_free_regs[i]=1;
1751 if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1753 alloc_all(current,i);
1754 alloc_reg64(current,i,FTEMP);
1755 minimum_free_regs[i]=HOST_REGS;
1760 void store_alloc(struct regstat *current,int i)
1762 clear_const(current,rs2[i]);
1763 if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1764 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1765 alloc_reg(current,i,rs2[i]);
1766 if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1767 alloc_reg64(current,i,rs2[i]);
1768 if(rs2[i]) alloc_reg(current,i,FTEMP);
1770 // If using TLB, need a register for pointer to the mapping table
1771 if(using_tlb) alloc_reg(current,i,TLREG);
1772 #if defined(HOST_IMM8)
1773 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1774 else alloc_reg(current,i,INVCP);
1776 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
1777 alloc_reg(current,i,FTEMP);
1779 // We need a temporary register for address generation
1780 alloc_reg_temp(current,i,-1);
1781 minimum_free_regs[i]=1;
1784 void c1ls_alloc(struct regstat *current,int i)
1786 //clear_const(current,rs1[i]); // FIXME
1787 clear_const(current,rt1[i]);
1788 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1789 alloc_reg(current,i,CSREG); // Status
1790 alloc_reg(current,i,FTEMP);
1791 if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1792 alloc_reg64(current,i,FTEMP);
1794 // If using TLB, need a register for pointer to the mapping table
1795 if(using_tlb) alloc_reg(current,i,TLREG);
1796 #if defined(HOST_IMM8)
1797 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1798 else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1799 alloc_reg(current,i,INVCP);
1801 // We need a temporary register for address generation
1802 alloc_reg_temp(current,i,-1);
1805 void c2ls_alloc(struct regstat *current,int i)
1807 clear_const(current,rt1[i]);
1808 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1809 alloc_reg(current,i,FTEMP);
1810 // If using TLB, need a register for pointer to the mapping table
1811 if(using_tlb) alloc_reg(current,i,TLREG);
1812 #if defined(HOST_IMM8)
1813 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1814 else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1815 alloc_reg(current,i,INVCP);
1817 // We need a temporary register for address generation
1818 alloc_reg_temp(current,i,-1);
1819 minimum_free_regs[i]=1;
1822 #ifndef multdiv_alloc
1823 void multdiv_alloc(struct regstat *current,int i)
1830 // case 0x1D: DMULTU
1833 clear_const(current,rs1[i]);
1834 clear_const(current,rs2[i]);
1837 if((opcode2[i]&4)==0) // 32-bit
1839 current->u&=~(1LL<<HIREG);
1840 current->u&=~(1LL<<LOREG);
1841 alloc_reg(current,i,HIREG);
1842 alloc_reg(current,i,LOREG);
1843 alloc_reg(current,i,rs1[i]);
1844 alloc_reg(current,i,rs2[i]);
1845 current->is32|=1LL<<HIREG;
1846 current->is32|=1LL<<LOREG;
1847 dirty_reg(current,HIREG);
1848 dirty_reg(current,LOREG);
1852 current->u&=~(1LL<<HIREG);
1853 current->u&=~(1LL<<LOREG);
1854 current->uu&=~(1LL<<HIREG);
1855 current->uu&=~(1LL<<LOREG);
1856 alloc_reg64(current,i,HIREG);
1857 //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1858 alloc_reg64(current,i,rs1[i]);
1859 alloc_reg64(current,i,rs2[i]);
1860 alloc_all(current,i);
1861 current->is32&=~(1LL<<HIREG);
1862 current->is32&=~(1LL<<LOREG);
1863 dirty_reg(current,HIREG);
1864 dirty_reg(current,LOREG);
1865 minimum_free_regs[i]=HOST_REGS;
1870 // Multiply by zero is zero.
1871 // MIPS does not have a divide by zero exception.
1872 // The result is undefined, we return zero.
1873 alloc_reg(current,i,HIREG);
1874 alloc_reg(current,i,LOREG);
1875 current->is32|=1LL<<HIREG;
1876 current->is32|=1LL<<LOREG;
1877 dirty_reg(current,HIREG);
1878 dirty_reg(current,LOREG);
1883 void cop0_alloc(struct regstat *current,int i)
1885 if(opcode2[i]==0) // MFC0
1888 clear_const(current,rt1[i]);
1889 alloc_all(current,i);
1890 alloc_reg(current,i,rt1[i]);
1891 current->is32|=1LL<<rt1[i];
1892 dirty_reg(current,rt1[i]);
1895 else if(opcode2[i]==4) // MTC0
1898 clear_const(current,rs1[i]);
1899 alloc_reg(current,i,rs1[i]);
1900 alloc_all(current,i);
1903 alloc_all(current,i); // FIXME: Keep r0
1905 alloc_reg(current,i,0);
1910 // TLBR/TLBWI/TLBWR/TLBP/ERET
1911 assert(opcode2[i]==0x10);
1912 alloc_all(current,i);
1914 minimum_free_regs[i]=HOST_REGS;
1917 void cop1_alloc(struct regstat *current,int i)
1919 alloc_reg(current,i,CSREG); // Load status
1920 if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1923 clear_const(current,rt1[i]);
1925 alloc_reg64(current,i,rt1[i]); // DMFC1
1926 current->is32&=~(1LL<<rt1[i]);
1928 alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1929 current->is32|=1LL<<rt1[i];
1931 dirty_reg(current,rt1[i]);
1933 alloc_reg_temp(current,i,-1);
1935 else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1938 clear_const(current,rs1[i]);
1940 alloc_reg64(current,i,rs1[i]); // DMTC1
1942 alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1943 alloc_reg_temp(current,i,-1);
1947 alloc_reg(current,i,0);
1948 alloc_reg_temp(current,i,-1);
1951 minimum_free_regs[i]=1;
1953 void fconv_alloc(struct regstat *current,int i)
1955 alloc_reg(current,i,CSREG); // Load status
1956 alloc_reg_temp(current,i,-1);
1957 minimum_free_regs[i]=1;
1959 void float_alloc(struct regstat *current,int i)
1961 alloc_reg(current,i,CSREG); // Load status
1962 alloc_reg_temp(current,i,-1);
1963 minimum_free_regs[i]=1;
1965 void c2op_alloc(struct regstat *current,int i)
1967 alloc_reg_temp(current,i,-1);
1969 void fcomp_alloc(struct regstat *current,int i)
1971 alloc_reg(current,i,CSREG); // Load status
1972 alloc_reg(current,i,FSREG); // Load flags
1973 dirty_reg(current,FSREG); // Flag will be modified
1974 alloc_reg_temp(current,i,-1);
1975 minimum_free_regs[i]=1;
1978 void syscall_alloc(struct regstat *current,int i)
1980 alloc_cc(current,i);
1981 dirty_reg(current,CCREG);
1982 alloc_all(current,i);
1983 minimum_free_regs[i]=HOST_REGS;
1987 void delayslot_alloc(struct regstat *current,int i)
1998 assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1);
1999 printf("Disabled speculative precompilation\n");
2003 imm16_alloc(current,i);
2007 load_alloc(current,i);
2011 store_alloc(current,i);
2014 alu_alloc(current,i);
2017 shift_alloc(current,i);
2020 multdiv_alloc(current,i);
2023 shiftimm_alloc(current,i);
2026 mov_alloc(current,i);
2029 cop0_alloc(current,i);
2033 cop1_alloc(current,i);
2036 c1ls_alloc(current,i);
2039 c2ls_alloc(current,i);
2042 fconv_alloc(current,i);
2045 float_alloc(current,i);
2048 fcomp_alloc(current,i);
2051 c2op_alloc(current,i);
2056 // Special case where a branch and delay slot span two pages in virtual memory
2057 static void pagespan_alloc(struct regstat *current,int i)
2060 current->wasconst=0;
2062 minimum_free_regs[i]=HOST_REGS;
2063 alloc_all(current,i);
2064 alloc_cc(current,i);
2065 dirty_reg(current,CCREG);
2066 if(opcode[i]==3) // JAL
2068 alloc_reg(current,i,31);
2069 dirty_reg(current,31);
2071 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
2073 alloc_reg(current,i,rs1[i]);
2075 alloc_reg(current,i,rt1[i]);
2076 dirty_reg(current,rt1[i]);
2079 if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
2081 if(rs1[i]) alloc_reg(current,i,rs1[i]);
2082 if(rs2[i]) alloc_reg(current,i,rs2[i]);
2083 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
2085 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2086 if(rs2[i]) alloc_reg64(current,i,rs2[i]);
2090 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
2092 if(rs1[i]) alloc_reg(current,i,rs1[i]);
2093 if(!((current->is32>>rs1[i])&1))
2095 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2099 if(opcode[i]==0x11) // BC1
2101 alloc_reg(current,i,FSREG);
2102 alloc_reg(current,i,CSREG);
2107 add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
2109 stubs[stubcount][0]=type;
2110 stubs[stubcount][1]=addr;
2111 stubs[stubcount][2]=retaddr;
2112 stubs[stubcount][3]=a;
2113 stubs[stubcount][4]=b;
2114 stubs[stubcount][5]=c;
2115 stubs[stubcount][6]=d;
2116 stubs[stubcount][7]=e;
2120 // Write out a single register
2121 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
2124 for(hr=0;hr<HOST_REGS;hr++) {
2125 if(hr!=EXCLUDE_REG) {
2126 if((regmap[hr]&63)==r) {
2129 emit_storereg(r,hr);
2131 if((is32>>regmap[hr])&1) {
2132 emit_sarimm(hr,31,hr);
2133 emit_storereg(r|64,hr);
2137 emit_storereg(r|64,hr);
2147 //if(!tracedebug) return 0;
2150 for(i=0;i<2097152;i++) {
2151 unsigned int temp=sum;
2154 sum^=((u_int *)rdram)[i];
2163 sum^=((u_int *)reg)[i];
2171 printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2173 #ifndef DISABLE_COP1
2176 printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2186 void memdebug(int i)
2188 //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2189 //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2192 //if(Count>=-2084597794) {
2193 if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2195 printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2196 //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2197 //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2200 printf("TRACE: %x\n",(&i)[-1]);
2204 printf("TRACE: %x \n",(&j)[10]);
2205 printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2209 //printf("TRACE: %x\n",(&i)[-1]);
2212 void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2214 printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2217 void alu_assemble(int i,struct regstat *i_regs)
2219 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2221 signed char s1,s2,t;
2222 t=get_reg(i_regs->regmap,rt1[i]);
2224 s1=get_reg(i_regs->regmap,rs1[i]);
2225 s2=get_reg(i_regs->regmap,rs2[i]);
2226 if(rs1[i]&&rs2[i]) {
2229 if(opcode2[i]&2) emit_sub(s1,s2,t);
2230 else emit_add(s1,s2,t);
2233 if(s1>=0) emit_mov(s1,t);
2234 else emit_loadreg(rs1[i],t);
2238 if(opcode2[i]&2) emit_neg(s2,t);
2239 else emit_mov(s2,t);
2242 emit_loadreg(rs2[i],t);
2243 if(opcode2[i]&2) emit_neg(t,t);
2246 else emit_zeroreg(t);
2250 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2252 signed char s1l,s2l,s1h,s2h,tl,th;
2253 tl=get_reg(i_regs->regmap,rt1[i]);
2254 th=get_reg(i_regs->regmap,rt1[i]|64);
2256 s1l=get_reg(i_regs->regmap,rs1[i]);
2257 s2l=get_reg(i_regs->regmap,rs2[i]);
2258 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2259 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2260 if(rs1[i]&&rs2[i]) {
2263 if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2264 else emit_adds(s1l,s2l,tl);
2266 #ifdef INVERTED_CARRY
2267 if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2269 if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2271 else emit_add(s1h,s2h,th);
2275 if(s1l>=0) emit_mov(s1l,tl);
2276 else emit_loadreg(rs1[i],tl);
2278 if(s1h>=0) emit_mov(s1h,th);
2279 else emit_loadreg(rs1[i]|64,th);
2284 if(opcode2[i]&2) emit_negs(s2l,tl);
2285 else emit_mov(s2l,tl);
2288 emit_loadreg(rs2[i],tl);
2289 if(opcode2[i]&2) emit_negs(tl,tl);
2292 #ifdef INVERTED_CARRY
2293 if(s2h>=0) emit_mov(s2h,th);
2294 else emit_loadreg(rs2[i]|64,th);
2296 emit_adcimm(-1,th); // x86 has inverted carry flag
2301 if(s2h>=0) emit_rscimm(s2h,0,th);
2303 emit_loadreg(rs2[i]|64,th);
2304 emit_rscimm(th,0,th);
2307 if(s2h>=0) emit_mov(s2h,th);
2308 else emit_loadreg(rs2[i]|64,th);
2315 if(th>=0) emit_zeroreg(th);
2320 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2322 signed char s1l,s1h,s2l,s2h,t;
2323 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2325 t=get_reg(i_regs->regmap,rt1[i]);
2328 s1l=get_reg(i_regs->regmap,rs1[i]);
2329 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2330 s2l=get_reg(i_regs->regmap,rs2[i]);
2331 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2332 if(rs2[i]==0) // rx<r0
2335 if(opcode2[i]==0x2a) // SLT
2336 emit_shrimm(s1h,31,t);
2337 else // SLTU (unsigned can not be less than zero)
2340 else if(rs1[i]==0) // r0<rx
2343 if(opcode2[i]==0x2a) // SLT
2344 emit_set_gz64_32(s2h,s2l,t);
2345 else // SLTU (set if not zero)
2346 emit_set_nz64_32(s2h,s2l,t);
2349 assert(s1l>=0);assert(s1h>=0);
2350 assert(s2l>=0);assert(s2h>=0);
2351 if(opcode2[i]==0x2a) // SLT
2352 emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2354 emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2358 t=get_reg(i_regs->regmap,rt1[i]);
2361 s1l=get_reg(i_regs->regmap,rs1[i]);
2362 s2l=get_reg(i_regs->regmap,rs2[i]);
2363 if(rs2[i]==0) // rx<r0
2366 if(opcode2[i]==0x2a) // SLT
2367 emit_shrimm(s1l,31,t);
2368 else // SLTU (unsigned can not be less than zero)
2371 else if(rs1[i]==0) // r0<rx
2374 if(opcode2[i]==0x2a) // SLT
2375 emit_set_gz32(s2l,t);
2376 else // SLTU (set if not zero)
2377 emit_set_nz32(s2l,t);
2380 assert(s1l>=0);assert(s2l>=0);
2381 if(opcode2[i]==0x2a) // SLT
2382 emit_set_if_less32(s1l,s2l,t);
2384 emit_set_if_carry32(s1l,s2l,t);
2390 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2392 signed char s1l,s1h,s2l,s2h,th,tl;
2393 tl=get_reg(i_regs->regmap,rt1[i]);
2394 th=get_reg(i_regs->regmap,rt1[i]|64);
2395 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2399 s1l=get_reg(i_regs->regmap,rs1[i]);
2400 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2401 s2l=get_reg(i_regs->regmap,rs2[i]);
2402 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2403 if(rs1[i]&&rs2[i]) {
2404 assert(s1l>=0);assert(s1h>=0);
2405 assert(s2l>=0);assert(s2h>=0);
2406 if(opcode2[i]==0x24) { // AND
2407 emit_and(s1l,s2l,tl);
2408 emit_and(s1h,s2h,th);
2410 if(opcode2[i]==0x25) { // OR
2411 emit_or(s1l,s2l,tl);
2412 emit_or(s1h,s2h,th);
2414 if(opcode2[i]==0x26) { // XOR
2415 emit_xor(s1l,s2l,tl);
2416 emit_xor(s1h,s2h,th);
2418 if(opcode2[i]==0x27) { // NOR
2419 emit_or(s1l,s2l,tl);
2420 emit_or(s1h,s2h,th);
2427 if(opcode2[i]==0x24) { // AND
2431 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2433 if(s1l>=0) emit_mov(s1l,tl);
2434 else emit_loadreg(rs1[i],tl);
2435 if(s1h>=0) emit_mov(s1h,th);
2436 else emit_loadreg(rs1[i]|64,th);
2440 if(s2l>=0) emit_mov(s2l,tl);
2441 else emit_loadreg(rs2[i],tl);
2442 if(s2h>=0) emit_mov(s2h,th);
2443 else emit_loadreg(rs2[i]|64,th);
2450 if(opcode2[i]==0x27) { // NOR
2452 if(s1l>=0) emit_not(s1l,tl);
2454 emit_loadreg(rs1[i],tl);
2457 if(s1h>=0) emit_not(s1h,th);
2459 emit_loadreg(rs1[i]|64,th);
2465 if(s2l>=0) emit_not(s2l,tl);
2467 emit_loadreg(rs2[i],tl);
2470 if(s2h>=0) emit_not(s2h,th);
2472 emit_loadreg(rs2[i]|64,th);
2488 s1l=get_reg(i_regs->regmap,rs1[i]);
2489 s2l=get_reg(i_regs->regmap,rs2[i]);
2490 if(rs1[i]&&rs2[i]) {
2493 if(opcode2[i]==0x24) { // AND
2494 emit_and(s1l,s2l,tl);
2496 if(opcode2[i]==0x25) { // OR
2497 emit_or(s1l,s2l,tl);
2499 if(opcode2[i]==0x26) { // XOR
2500 emit_xor(s1l,s2l,tl);
2502 if(opcode2[i]==0x27) { // NOR
2503 emit_or(s1l,s2l,tl);
2509 if(opcode2[i]==0x24) { // AND
2512 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2514 if(s1l>=0) emit_mov(s1l,tl);
2515 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2519 if(s2l>=0) emit_mov(s2l,tl);
2520 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2522 else emit_zeroreg(tl);
2524 if(opcode2[i]==0x27) { // NOR
2526 if(s1l>=0) emit_not(s1l,tl);
2528 emit_loadreg(rs1[i],tl);
2534 if(s2l>=0) emit_not(s2l,tl);
2536 emit_loadreg(rs2[i],tl);
2540 else emit_movimm(-1,tl);
2549 void imm16_assemble(int i,struct regstat *i_regs)
2551 if (opcode[i]==0x0f) { // LUI
2554 t=get_reg(i_regs->regmap,rt1[i]);
2557 if(!((i_regs->isconst>>t)&1))
2558 emit_movimm(imm[i]<<16,t);
2562 if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2565 t=get_reg(i_regs->regmap,rt1[i]);
2566 s=get_reg(i_regs->regmap,rs1[i]);
2571 if(!((i_regs->isconst>>t)&1)) {
2573 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2574 emit_addimm(t,imm[i],t);
2576 if(!((i_regs->wasconst>>s)&1))
2577 emit_addimm(s,imm[i],t);
2579 emit_movimm(constmap[i][s]+imm[i],t);
2585 if(!((i_regs->isconst>>t)&1))
2586 emit_movimm(imm[i],t);
2591 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2593 signed char sh,sl,th,tl;
2594 th=get_reg(i_regs->regmap,rt1[i]|64);
2595 tl=get_reg(i_regs->regmap,rt1[i]);
2596 sh=get_reg(i_regs->regmap,rs1[i]|64);
2597 sl=get_reg(i_regs->regmap,rs1[i]);
2603 emit_addimm64_32(sh,sl,imm[i],th,tl);
2606 emit_addimm(sl,imm[i],tl);
2609 emit_movimm(imm[i],tl);
2610 if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2615 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2617 //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2618 signed char sh,sl,t;
2619 t=get_reg(i_regs->regmap,rt1[i]);
2620 sh=get_reg(i_regs->regmap,rs1[i]|64);
2621 sl=get_reg(i_regs->regmap,rs1[i]);
2625 if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2626 if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2627 if(opcode[i]==0x0a) { // SLTI
2629 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2630 emit_slti32(t,imm[i],t);
2632 emit_slti32(sl,imm[i],t);
2637 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2638 emit_sltiu32(t,imm[i],t);
2640 emit_sltiu32(sl,imm[i],t);
2645 if(opcode[i]==0x0a) // SLTI
2646 emit_slti64_32(sh,sl,imm[i],t);
2648 emit_sltiu64_32(sh,sl,imm[i],t);
2651 // SLTI(U) with r0 is just stupid,
2652 // nonetheless examples can be found
2653 if(opcode[i]==0x0a) // SLTI
2654 if(0<imm[i]) emit_movimm(1,t);
2655 else emit_zeroreg(t);
2658 if(imm[i]) emit_movimm(1,t);
2659 else emit_zeroreg(t);
2665 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2667 signed char sh,sl,th,tl;
2668 th=get_reg(i_regs->regmap,rt1[i]|64);
2669 tl=get_reg(i_regs->regmap,rt1[i]);
2670 sh=get_reg(i_regs->regmap,rs1[i]|64);
2671 sl=get_reg(i_regs->regmap,rs1[i]);
2672 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2673 if(opcode[i]==0x0c) //ANDI
2677 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2678 emit_andimm(tl,imm[i],tl);
2680 if(!((i_regs->wasconst>>sl)&1))
2681 emit_andimm(sl,imm[i],tl);
2683 emit_movimm(constmap[i][sl]&imm[i],tl);
2688 if(th>=0) emit_zeroreg(th);
2694 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2698 emit_loadreg(rs1[i]|64,th);
2703 if(opcode[i]==0x0d) //ORI
2705 emit_orimm(tl,imm[i],tl);
2707 if(!((i_regs->wasconst>>sl)&1))
2708 emit_orimm(sl,imm[i],tl);
2710 emit_movimm(constmap[i][sl]|imm[i],tl);
2712 if(opcode[i]==0x0e) //XORI
2714 emit_xorimm(tl,imm[i],tl);
2716 if(!((i_regs->wasconst>>sl)&1))
2717 emit_xorimm(sl,imm[i],tl);
2719 emit_movimm(constmap[i][sl]^imm[i],tl);
2723 emit_movimm(imm[i],tl);
2724 if(th>=0) emit_zeroreg(th);
2732 void shiftimm_assemble(int i,struct regstat *i_regs)
2734 if(opcode2[i]<=0x3) // SLL/SRL/SRA
2738 t=get_reg(i_regs->regmap,rt1[i]);
2739 s=get_reg(i_regs->regmap,rs1[i]);
2741 if(t>=0&&!((i_regs->isconst>>t)&1)){
2748 if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2750 if(opcode2[i]==0) // SLL
2752 emit_shlimm(s<0?t:s,imm[i],t);
2754 if(opcode2[i]==2) // SRL
2756 emit_shrimm(s<0?t:s,imm[i],t);
2758 if(opcode2[i]==3) // SRA
2760 emit_sarimm(s<0?t:s,imm[i],t);
2764 if(s>=0 && s!=t) emit_mov(s,t);
2768 //emit_storereg(rt1[i],t); //DEBUG
2771 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2774 signed char sh,sl,th,tl;
2775 th=get_reg(i_regs->regmap,rt1[i]|64);
2776 tl=get_reg(i_regs->regmap,rt1[i]);
2777 sh=get_reg(i_regs->regmap,rs1[i]|64);
2778 sl=get_reg(i_regs->regmap,rs1[i]);
2783 if(th>=0) emit_zeroreg(th);
2790 if(opcode2[i]==0x38) // DSLL
2792 if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2793 emit_shlimm(sl,imm[i],tl);
2795 if(opcode2[i]==0x3a) // DSRL
2797 emit_shrdimm(sl,sh,imm[i],tl);
2798 if(th>=0) emit_shrimm(sh,imm[i],th);
2800 if(opcode2[i]==0x3b) // DSRA
2802 emit_shrdimm(sl,sh,imm[i],tl);
2803 if(th>=0) emit_sarimm(sh,imm[i],th);
2807 if(sl!=tl) emit_mov(sl,tl);
2808 if(th>=0&&sh!=th) emit_mov(sh,th);
2814 if(opcode2[i]==0x3c) // DSLL32
2817 signed char sl,tl,th;
2818 tl=get_reg(i_regs->regmap,rt1[i]);
2819 th=get_reg(i_regs->regmap,rt1[i]|64);
2820 sl=get_reg(i_regs->regmap,rs1[i]);
2829 emit_shlimm(th,imm[i]&31,th);
2834 if(opcode2[i]==0x3e) // DSRL32
2837 signed char sh,tl,th;
2838 tl=get_reg(i_regs->regmap,rt1[i]);
2839 th=get_reg(i_regs->regmap,rt1[i]|64);
2840 sh=get_reg(i_regs->regmap,rs1[i]|64);
2844 if(th>=0) emit_zeroreg(th);
2847 emit_shrimm(tl,imm[i]&31,tl);
2852 if(opcode2[i]==0x3f) // DSRA32
2856 tl=get_reg(i_regs->regmap,rt1[i]);
2857 sh=get_reg(i_regs->regmap,rs1[i]|64);
2863 emit_sarimm(tl,imm[i]&31,tl);
2870 #ifndef shift_assemble
2871 void shift_assemble(int i,struct regstat *i_regs)
2873 printf("Need shift_assemble for this architecture.\n");
2878 void load_assemble(int i,struct regstat *i_regs)
2880 int s,th,tl,addr,map=-1;
2883 int memtarget=0,c=0;
2884 int fastload_reg_override=0;
2886 th=get_reg(i_regs->regmap,rt1[i]|64);
2887 tl=get_reg(i_regs->regmap,rt1[i]);
2888 s=get_reg(i_regs->regmap,rs1[i]);
2890 for(hr=0;hr<HOST_REGS;hr++) {
2891 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2893 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2895 c=(i_regs->wasconst>>s)&1;
2897 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2898 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2901 //printf("load_assemble: c=%d\n",c);
2902 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2903 // FIXME: Even if the load is a NOP, we should check for pagefaults...
2905 if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2907 // could be FIFO, must perform the read
2909 assem_debug("(forced read)\n");
2910 tl=get_reg(i_regs->regmap,-1);
2914 if(offset||s<0||c) addr=tl;
2916 //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2918 //printf("load_assemble: c=%d\n",c);
2919 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2920 assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2922 if(th>=0) reglist&=~(1<<th);
2926 map=get_reg(i_regs->regmap,ROREG);
2927 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2929 //#define R29_HACK 1
2931 // Strmnnrmn's speed hack
2932 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2935 jaddr=emit_fastpath_cmp_jump(i,addr,&fastload_reg_override);
2938 else if(ram_offset&&memtarget) {
2939 emit_addimm(addr,ram_offset,HOST_TEMPREG);
2940 fastload_reg_override=HOST_TEMPREG;
2944 if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2945 if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2946 map=get_reg(i_regs->regmap,TLREG);
2949 map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2950 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2952 int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2953 if (opcode[i]==0x20) { // LB
2956 #ifdef HOST_IMM_ADDR32
2958 emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2962 //emit_xorimm(addr,3,tl);
2963 //gen_tlb_addr_r(tl,map);
2964 //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2966 #ifdef BIG_ENDIAN_MIPS
2967 if(!c) emit_xorimm(addr,3,tl);
2968 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2972 if(fastload_reg_override) a=fastload_reg_override;
2974 emit_movsbl_indexed_tlb(x,a,map,tl);
2978 add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2981 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2983 if (opcode[i]==0x21) { // LH
2986 #ifdef HOST_IMM_ADDR32
2988 emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2993 #ifdef BIG_ENDIAN_MIPS
2994 if(!c) emit_xorimm(addr,2,tl);
2995 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2999 if(fastload_reg_override) a=fastload_reg_override;
3001 //emit_movswl_indexed_tlb(x,tl,map,tl);
3004 gen_tlb_addr_r(a,map);
3005 emit_movswl_indexed(x,a,tl);
3007 #if 1 //def RAM_OFFSET
3008 emit_movswl_indexed(x,a,tl);
3010 emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
3016 add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3019 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3021 if (opcode[i]==0x23) { // LW
3025 if(fastload_reg_override) a=fastload_reg_override;
3026 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
3027 #ifdef HOST_IMM_ADDR32
3029 emit_readword_tlb(constmap[i][s]+offset,map,tl);
3032 emit_readword_indexed_tlb(0,a,map,tl);
3035 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3038 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3040 if (opcode[i]==0x24) { // LBU
3043 #ifdef HOST_IMM_ADDR32
3045 emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
3049 //emit_xorimm(addr,3,tl);
3050 //gen_tlb_addr_r(tl,map);
3051 //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
3053 #ifdef BIG_ENDIAN_MIPS
3054 if(!c) emit_xorimm(addr,3,tl);
3055 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3059 if(fastload_reg_override) a=fastload_reg_override;
3061 emit_movzbl_indexed_tlb(x,a,map,tl);
3065 add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3068 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3070 if (opcode[i]==0x25) { // LHU
3073 #ifdef HOST_IMM_ADDR32
3075 emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
3080 #ifdef BIG_ENDIAN_MIPS
3081 if(!c) emit_xorimm(addr,2,tl);
3082 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3086 if(fastload_reg_override) a=fastload_reg_override;
3088 //emit_movzwl_indexed_tlb(x,tl,map,tl);
3091 gen_tlb_addr_r(a,map);
3092 emit_movzwl_indexed(x,a,tl);
3094 #if 1 //def RAM_OFFSET
3095 emit_movzwl_indexed(x,a,tl);
3097 emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
3103 add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3106 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3108 if (opcode[i]==0x27) { // LWU
3113 if(fastload_reg_override) a=fastload_reg_override;
3114 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
3115 #ifdef HOST_IMM_ADDR32
3117 emit_readword_tlb(constmap[i][s]+offset,map,tl);
3120 emit_readword_indexed_tlb(0,a,map,tl);
3123 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3126 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3130 if (opcode[i]==0x37) { // LD
3134 if(fastload_reg_override) a=fastload_reg_override;
3135 //gen_tlb_addr_r(tl,map);
3136 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
3137 //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
3138 #ifdef HOST_IMM_ADDR32
3140 emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3143 emit_readdword_indexed_tlb(0,a,map,th,tl);
3146 add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3149 inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3152 //emit_storereg(rt1[i],tl); // DEBUG
3153 //if(opcode[i]==0x23)
3154 //if(opcode[i]==0x24)
3155 //if(opcode[i]==0x23||opcode[i]==0x24)
3156 /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
3160 emit_readword((int)&last_count,ECX);
3162 if(get_reg(i_regs->regmap,CCREG)<0)
3163 emit_loadreg(CCREG,HOST_CCREG);
3164 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3165 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3166 emit_writeword(HOST_CCREG,(int)&Count);
3169 if(get_reg(i_regs->regmap,CCREG)<0)
3170 emit_loadreg(CCREG,0);
3172 emit_mov(HOST_CCREG,0);
3174 emit_addimm(0,2*ccadj[i],0);
3175 emit_writeword(0,(int)&Count);
3177 emit_call((int)memdebug);
3179 restore_regs(0x100f);
3183 #ifndef loadlr_assemble
3184 void loadlr_assemble(int i,struct regstat *i_regs)
3186 printf("Need loadlr_assemble for this architecture.\n");
3191 void store_assemble(int i,struct regstat *i_regs)
3196 int jaddr=0,jaddr2,type;
3197 int memtarget=0,c=0;
3198 int agr=AGEN1+(i&1);
3199 int faststore_reg_override=0;
3201 th=get_reg(i_regs->regmap,rs2[i]|64);
3202 tl=get_reg(i_regs->regmap,rs2[i]);
3203 s=get_reg(i_regs->regmap,rs1[i]);
3204 temp=get_reg(i_regs->regmap,agr);
3205 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3208 c=(i_regs->wasconst>>s)&1;
3210 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3211 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3216 for(hr=0;hr<HOST_REGS;hr++) {
3217 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3219 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3220 if(offset||s<0||c) addr=temp;
3226 // Strmnnrmn's speed hack
3227 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3229 emit_cmpimm(addr,RAM_SIZE);
3230 #ifdef DESTRUCTIVE_SHIFT
3231 if(s==addr) emit_mov(s,temp);
3235 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3239 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3240 // Hint to branch predictor that the branch is unlikely to be taken
3242 emit_jno_unlikely(0);
3248 jaddr=emit_fastpath_cmp_jump(i,addr,&faststore_reg_override);
3251 else if(ram_offset&&memtarget) {
3252 emit_addimm(addr,ram_offset,HOST_TEMPREG);
3253 faststore_reg_override=HOST_TEMPREG;
3257 if (opcode[i]==0x28) x=3; // SB
3258 if (opcode[i]==0x29) x=2; // SH
3259 map=get_reg(i_regs->regmap,TLREG);
3262 map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3263 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3266 if (opcode[i]==0x28) { // SB
3269 #ifdef BIG_ENDIAN_MIPS
3270 if(!c) emit_xorimm(addr,3,temp);
3271 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3275 if(faststore_reg_override) a=faststore_reg_override;
3276 //gen_tlb_addr_w(temp,map);
3277 //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3278 emit_writebyte_indexed_tlb(tl,x,a,map,a);
3282 if (opcode[i]==0x29) { // SH
3285 #ifdef BIG_ENDIAN_MIPS
3286 if(!c) emit_xorimm(addr,2,temp);
3287 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3291 if(faststore_reg_override) a=faststore_reg_override;
3293 //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3296 gen_tlb_addr_w(a,map);
3297 emit_writehword_indexed(tl,x,a);
3299 //emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a);
3300 emit_writehword_indexed(tl,x,a);
3304 if (opcode[i]==0x2B) { // SW
3307 if(faststore_reg_override) a=faststore_reg_override;
3308 //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3309 emit_writeword_indexed_tlb(tl,0,a,map,temp);
3313 if (opcode[i]==0x3F) { // SD
3316 if(faststore_reg_override) a=faststore_reg_override;
3319 //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3320 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3321 emit_writedword_indexed_tlb(th,tl,0,a,map,temp);
3324 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3325 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3326 emit_writedword_indexed_tlb(tl,tl,0,a,map,temp);
3333 // PCSX store handlers don't check invcode again
3335 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3339 if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
3341 #ifdef DESTRUCTIVE_SHIFT
3342 // The x86 shift operation is 'destructive'; it overwrites the
3343 // source register, so we need to make a copy first and use that.
3346 #if defined(HOST_IMM8)
3347 int ir=get_reg(i_regs->regmap,INVCP);
3349 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3351 emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3353 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3354 emit_callne(invalidate_addr_reg[addr]);
3358 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3362 u_int addr_val=constmap[i][s]+offset;
3364 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3365 } else if(c&&!memtarget) {
3366 inline_writestub(type,i,addr_val,i_regs->regmap,rs2[i],ccadj[i],reglist);
3368 // basic current block modification detection..
3369 // not looking back as that should be in mips cache already
3370 if(c&&start+i*4<addr_val&&addr_val<start+slen*4) {
3371 printf("write to %08x hits block %08x, pc=%08x\n",addr_val,start,start+i*4);
3372 assert(i_regs->regmap==regs[i].regmap); // not delay slot
3373 if(i_regs->regmap==regs[i].regmap) {
3374 load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty,i);
3375 wb_dirtys(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty);
3376 emit_movimm(start+i*4+4,0);
3377 emit_writeword(0,(int)&pcaddr);
3378 emit_jmp((int)do_interrupt);
3381 //if(opcode[i]==0x2B || opcode[i]==0x3F)
3382 //if(opcode[i]==0x2B || opcode[i]==0x28)
3383 //if(opcode[i]==0x2B || opcode[i]==0x29)
3384 //if(opcode[i]==0x2B)
3385 /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3393 emit_readword((int)&last_count,ECX);
3395 if(get_reg(i_regs->regmap,CCREG)<0)
3396 emit_loadreg(CCREG,HOST_CCREG);
3397 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3398 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3399 emit_writeword(HOST_CCREG,(int)&Count);
3402 if(get_reg(i_regs->regmap,CCREG)<0)
3403 emit_loadreg(CCREG,0);
3405 emit_mov(HOST_CCREG,0);
3407 emit_addimm(0,2*ccadj[i],0);
3408 emit_writeword(0,(int)&Count);
3410 emit_call((int)memdebug);
3415 restore_regs(0x100f);
3420 void storelr_assemble(int i,struct regstat *i_regs)
3427 int case1,case2,case3;
3428 int done0,done1,done2;
3429 int memtarget=0,c=0;
3430 int agr=AGEN1+(i&1);
3432 th=get_reg(i_regs->regmap,rs2[i]|64);
3433 tl=get_reg(i_regs->regmap,rs2[i]);
3434 s=get_reg(i_regs->regmap,rs1[i]);
3435 temp=get_reg(i_regs->regmap,agr);
3436 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3439 c=(i_regs->isconst>>s)&1;
3441 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3442 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3446 for(hr=0;hr<HOST_REGS;hr++) {
3447 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3452 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3453 if(!offset&&s!=temp) emit_mov(s,temp);
3459 if(!memtarget||!rs1[i]) {
3465 int map=get_reg(i_regs->regmap,ROREG);
3466 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3467 gen_tlb_addr_w(temp,map);
3469 if((u_int)rdram!=0x80000000)
3470 emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3473 int map=get_reg(i_regs->regmap,TLREG);
3476 map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3477 if(!c&&!offset&&s>=0) emit_mov(s,temp);
3478 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3479 if(!jaddr&&!memtarget) {
3483 gen_tlb_addr_w(temp,map);
3486 if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3487 temp2=get_reg(i_regs->regmap,FTEMP);
3488 if(!rs2[i]) temp2=th=tl;
3491 #ifndef BIG_ENDIAN_MIPS
3492 emit_xorimm(temp,3,temp);
3494 emit_testimm(temp,2);
3497 emit_testimm(temp,1);
3501 if (opcode[i]==0x2A) { // SWL
3502 emit_writeword_indexed(tl,0,temp);
3504 if (opcode[i]==0x2E) { // SWR
3505 emit_writebyte_indexed(tl,3,temp);
3507 if (opcode[i]==0x2C) { // SDL
3508 emit_writeword_indexed(th,0,temp);
3509 if(rs2[i]) emit_mov(tl,temp2);
3511 if (opcode[i]==0x2D) { // SDR
3512 emit_writebyte_indexed(tl,3,temp);
3513 if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3518 set_jump_target(case1,(int)out);
3519 if (opcode[i]==0x2A) { // SWL
3520 // Write 3 msb into three least significant bytes
3521 if(rs2[i]) emit_rorimm(tl,8,tl);
3522 emit_writehword_indexed(tl,-1,temp);
3523 if(rs2[i]) emit_rorimm(tl,16,tl);
3524 emit_writebyte_indexed(tl,1,temp);
3525 if(rs2[i]) emit_rorimm(tl,8,tl);
3527 if (opcode[i]==0x2E) { // SWR
3528 // Write two lsb into two most significant bytes
3529 emit_writehword_indexed(tl,1,temp);
3531 if (opcode[i]==0x2C) { // SDL
3532 if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3533 // Write 3 msb into three least significant bytes
3534 if(rs2[i]) emit_rorimm(th,8,th);
3535 emit_writehword_indexed(th,-1,temp);
3536 if(rs2[i]) emit_rorimm(th,16,th);
3537 emit_writebyte_indexed(th,1,temp);
3538 if(rs2[i]) emit_rorimm(th,8,th);
3540 if (opcode[i]==0x2D) { // SDR
3541 if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3542 // Write two lsb into two most significant bytes
3543 emit_writehword_indexed(tl,1,temp);
3548 set_jump_target(case2,(int)out);
3549 emit_testimm(temp,1);
3552 if (opcode[i]==0x2A) { // SWL
3553 // Write two msb into two least significant bytes
3554 if(rs2[i]) emit_rorimm(tl,16,tl);
3555 emit_writehword_indexed(tl,-2,temp);
3556 if(rs2[i]) emit_rorimm(tl,16,tl);
3558 if (opcode[i]==0x2E) { // SWR
3559 // Write 3 lsb into three most significant bytes
3560 emit_writebyte_indexed(tl,-1,temp);
3561 if(rs2[i]) emit_rorimm(tl,8,tl);
3562 emit_writehword_indexed(tl,0,temp);
3563 if(rs2[i]) emit_rorimm(tl,24,tl);
3565 if (opcode[i]==0x2C) { // SDL
3566 if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3567 // Write two msb into two least significant bytes
3568 if(rs2[i]) emit_rorimm(th,16,th);
3569 emit_writehword_indexed(th,-2,temp);
3570 if(rs2[i]) emit_rorimm(th,16,th);
3572 if (opcode[i]==0x2D) { // SDR
3573 if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3574 // Write 3 lsb into three most significant bytes
3575 emit_writebyte_indexed(tl,-1,temp);
3576 if(rs2[i]) emit_rorimm(tl,8,tl);
3577 emit_writehword_indexed(tl,0,temp);
3578 if(rs2[i]) emit_rorimm(tl,24,tl);
3583 set_jump_target(case3,(int)out);
3584 if (opcode[i]==0x2A) { // SWL
3585 // Write msb into least significant byte
3586 if(rs2[i]) emit_rorimm(tl,24,tl);
3587 emit_writebyte_indexed(tl,-3,temp);
3588 if(rs2[i]) emit_rorimm(tl,8,tl);
3590 if (opcode[i]==0x2E) { // SWR
3591 // Write entire word
3592 emit_writeword_indexed(tl,-3,temp);
3594 if (opcode[i]==0x2C) { // SDL
3595 if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3596 // Write msb into least significant byte
3597 if(rs2[i]) emit_rorimm(th,24,th);
3598 emit_writebyte_indexed(th,-3,temp);
3599 if(rs2[i]) emit_rorimm(th,8,th);
3601 if (opcode[i]==0x2D) { // SDR
3602 if(rs2[i]) emit_mov(th,temp2);
3603 // Write entire word
3604 emit_writeword_indexed(tl,-3,temp);
3606 set_jump_target(done0,(int)out);
3607 set_jump_target(done1,(int)out);
3608 set_jump_target(done2,(int)out);
3609 if (opcode[i]==0x2C) { // SDL
3610 emit_testimm(temp,4);
3613 emit_andimm(temp,~3,temp);
3614 emit_writeword_indexed(temp2,4,temp);
3615 set_jump_target(done0,(int)out);
3617 if (opcode[i]==0x2D) { // SDR
3618 emit_testimm(temp,4);
3621 emit_andimm(temp,~3,temp);
3622 emit_writeword_indexed(temp2,-4,temp);
3623 set_jump_target(done0,(int)out);
3626 add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
3627 if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
3629 int map=get_reg(i_regs->regmap,ROREG);
3630 if(map<0) map=HOST_TEMPREG;
3631 gen_orig_addr_w(temp,map);
3633 emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
3635 #if defined(HOST_IMM8)
3636 int ir=get_reg(i_regs->regmap,INVCP);
3638 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3640 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3642 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3643 emit_callne(invalidate_addr_reg[temp]);
3647 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3652 //save_regs(0x100f);
3653 emit_readword((int)&last_count,ECX);
3654 if(get_reg(i_regs->regmap,CCREG)<0)
3655 emit_loadreg(CCREG,HOST_CCREG);
3656 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3657 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3658 emit_writeword(HOST_CCREG,(int)&Count);
3659 emit_call((int)memdebug);
3661 //restore_regs(0x100f);
3665 void c1ls_assemble(int i,struct regstat *i_regs)
3667 #ifndef DISABLE_COP1
3673 int jaddr,jaddr2=0,jaddr3,type;
3674 int agr=AGEN1+(i&1);
3676 th=get_reg(i_regs->regmap,FTEMP|64);
3677 tl=get_reg(i_regs->regmap,FTEMP);
3678 s=get_reg(i_regs->regmap,rs1[i]);
3679 temp=get_reg(i_regs->regmap,agr);
3680 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3685 for(hr=0;hr<HOST_REGS;hr++) {
3686 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3688 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3689 if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3691 // Loads use a temporary register which we need to save
3694 if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3698 //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3699 //else c=(i_regs->wasconst>>s)&1;
3700 if(s>=0) c=(i_regs->wasconst>>s)&1;
3701 // Check cop1 unusable
3703 signed char rs=get_reg(i_regs->regmap,CSREG);
3705 emit_testimm(rs,0x20000000);
3708 add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3711 if (opcode[i]==0x39) { // SWC1 (get float address)
3712 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],tl);
3714 if (opcode[i]==0x3D) { // SDC1 (get double address)
3715 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],tl);
3717 // Generate address + offset
3720 emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3724 map=get_reg(i_regs->regmap,TLREG);
3727 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3728 map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
3730 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3731 map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
3734 if (opcode[i]==0x39) { // SWC1 (read float)
3735 emit_readword_indexed(0,tl,tl);
3737 if (opcode[i]==0x3D) { // SDC1 (read double)
3738 emit_readword_indexed(4,tl,th);
3739 emit_readword_indexed(0,tl,tl);
3741 if (opcode[i]==0x31) { // LWC1 (get target address)
3742 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],temp);
3744 if (opcode[i]==0x35) { // LDC1 (get target address)
3745 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],temp);
3752 else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80000000+RAM_SIZE) {
3754 emit_jmp(0); // inline_readstub/inline_writestub? Very rare case
3756 #ifdef DESTRUCTIVE_SHIFT
3757 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3758 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3762 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3763 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3765 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3766 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3769 if (opcode[i]==0x31) { // LWC1
3770 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3771 //gen_tlb_addr_r(ar,map);
3772 //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3773 #ifdef HOST_IMM_ADDR32
3774 if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3777 emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3780 if (opcode[i]==0x35) { // LDC1
3782 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3783 //gen_tlb_addr_r(ar,map);
3784 //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3785 //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3786 #ifdef HOST_IMM_ADDR32
3787 if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3790 emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3793 if (opcode[i]==0x39) { // SWC1
3794 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3795 emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3798 if (opcode[i]==0x3D) { // SDC1
3800 //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3801 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3802 emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3805 if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
3806 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3807 #ifndef DESTRUCTIVE_SHIFT
3808 temp=offset||c||s<0?ar:s;
3810 #if defined(HOST_IMM8)
3811 int ir=get_reg(i_regs->regmap,INVCP);
3813 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3815 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3817 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3818 emit_callne(invalidate_addr_reg[temp]);
3822 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3826 if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3827 if (opcode[i]==0x31) { // LWC1 (write float)
3828 emit_writeword_indexed(tl,0,temp);
3830 if (opcode[i]==0x35) { // LDC1 (write double)
3831 emit_writeword_indexed(th,4,temp);
3832 emit_writeword_indexed(tl,0,temp);
3834 //if(opcode[i]==0x39)
3835 /*if(opcode[i]==0x39||opcode[i]==0x31)
3838 emit_readword((int)&last_count,ECX);
3839 if(get_reg(i_regs->regmap,CCREG)<0)
3840 emit_loadreg(CCREG,HOST_CCREG);
3841 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3842 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3843 emit_writeword(HOST_CCREG,(int)&Count);
3844 emit_call((int)memdebug);
3848 cop1_unusable(i, i_regs);
3852 void c2ls_assemble(int i,struct regstat *i_regs)
3857 int memtarget=0,c=0;
3858 int jaddr2=0,jaddr3,type;
3859 int agr=AGEN1+(i&1);
3860 int fastio_reg_override=0;
3862 u_int copr=(source[i]>>16)&0x1f;
3863 s=get_reg(i_regs->regmap,rs1[i]);
3864 tl=get_reg(i_regs->regmap,FTEMP);
3870 for(hr=0;hr<HOST_REGS;hr++) {
3871 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3873 if(i_regs->regmap[HOST_CCREG]==CCREG)
3874 reglist&=~(1<<HOST_CCREG);
3877 if (opcode[i]==0x3a) { // SWC2
3878 ar=get_reg(i_regs->regmap,agr);
3879 if(ar<0) ar=get_reg(i_regs->regmap,-1);
3884 if(s>=0) c=(i_regs->wasconst>>s)&1;
3885 memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
3886 if (!offset&&!c&&s>=0) ar=s;
3889 if (opcode[i]==0x3a) { // SWC2
3890 cop2_get_dreg(copr,tl,HOST_TEMPREG);
3898 emit_jmp(0); // inline_readstub/inline_writestub?
3902 jaddr2=emit_fastpath_cmp_jump(i,ar,&fastio_reg_override);
3904 else if(ram_offset&&memtarget) {
3905 emit_addimm(ar,ram_offset,HOST_TEMPREG);
3906 fastio_reg_override=HOST_TEMPREG;
3908 if (opcode[i]==0x32) { // LWC2
3909 #ifdef HOST_IMM_ADDR32
3910 if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
3914 if(fastio_reg_override) a=fastio_reg_override;
3915 emit_readword_indexed(0,a,tl);
3917 if (opcode[i]==0x3a) { // SWC2
3918 #ifdef DESTRUCTIVE_SHIFT
3919 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3922 if(fastio_reg_override) a=fastio_reg_override;
3923 emit_writeword_indexed(tl,0,a);
3927 add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist);
3928 if(opcode[i]==0x3a) // SWC2
3929 if(!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
3930 #if defined(HOST_IMM8)
3931 int ir=get_reg(i_regs->regmap,INVCP);
3933 emit_cmpmem_indexedsr12_reg(ir,ar,1);
3935 emit_cmpmem_indexedsr12_imm((int)invalid_code,ar,1);
3937 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3938 emit_callne(invalidate_addr_reg[ar]);
3942 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),ar,0,0,0);
3945 if (opcode[i]==0x32) { // LWC2
3946 cop2_put_dreg(copr,tl,HOST_TEMPREG);
3950 #ifndef multdiv_assemble
3951 void multdiv_assemble(int i,struct regstat *i_regs)
3953 printf("Need multdiv_assemble for this architecture.\n");
3958 void mov_assemble(int i,struct regstat *i_regs)
3960 //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3961 //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
3963 signed char sh,sl,th,tl;
3964 th=get_reg(i_regs->regmap,rt1[i]|64);
3965 tl=get_reg(i_regs->regmap,rt1[i]);
3968 sh=get_reg(i_regs->regmap,rs1[i]|64);
3969 sl=get_reg(i_regs->regmap,rs1[i]);
3970 if(sl>=0) emit_mov(sl,tl);
3971 else emit_loadreg(rs1[i],tl);
3973 if(sh>=0) emit_mov(sh,th);
3974 else emit_loadreg(rs1[i]|64,th);
3980 #ifndef fconv_assemble
3981 void fconv_assemble(int i,struct regstat *i_regs)
3983 printf("Need fconv_assemble for this architecture.\n");
3989 void float_assemble(int i,struct regstat *i_regs)
3991 printf("Need float_assemble for this architecture.\n");
3996 void syscall_assemble(int i,struct regstat *i_regs)
3998 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3999 assert(ccreg==HOST_CCREG);
4000 assert(!is_delayslot);
4001 emit_movimm(start+i*4,EAX); // Get PC
4002 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
4003 emit_jmp((int)jump_syscall_hle); // XXX
4006 void hlecall_assemble(int i,struct regstat *i_regs)
4008 signed char ccreg=get_reg(i_regs->regmap,CCREG);
4009 assert(ccreg==HOST_CCREG);
4010 assert(!is_delayslot);
4011 emit_movimm(start+i*4+4,0); // Get PC
4012 emit_movimm((int)psxHLEt[source[i]&7],1);
4013 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // XXX
4014 emit_jmp((int)jump_hlecall);
4017 void intcall_assemble(int i,struct regstat *i_regs)
4019 signed char ccreg=get_reg(i_regs->regmap,CCREG);
4020 assert(ccreg==HOST_CCREG);
4021 assert(!is_delayslot);
4022 emit_movimm(start+i*4,0); // Get PC
4023 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG);
4024 emit_jmp((int)jump_intcall);
4027 void ds_assemble(int i,struct regstat *i_regs)
4029 speculate_register_values(i);
4033 alu_assemble(i,i_regs);break;
4035 imm16_assemble(i,i_regs);break;
4037 shift_assemble(i,i_regs);break;
4039 shiftimm_assemble(i,i_regs);break;
4041 load_assemble(i,i_regs);break;
4043 loadlr_assemble(i,i_regs);break;
4045 store_assemble(i,i_regs);break;
4047 storelr_assemble(i,i_regs);break;
4049 cop0_assemble(i,i_regs);break;
4051 cop1_assemble(i,i_regs);break;
4053 c1ls_assemble(i,i_regs);break;
4055 cop2_assemble(i,i_regs);break;
4057 c2ls_assemble(i,i_regs);break;
4059 c2op_assemble(i,i_regs);break;
4061 fconv_assemble(i,i_regs);break;
4063 float_assemble(i,i_regs);break;
4065 fcomp_assemble(i,i_regs);break;
4067 multdiv_assemble(i,i_regs);break;
4069 mov_assemble(i,i_regs);break;
4079 printf("Jump in the delay slot. This is probably a bug.\n");
4084 // Is the branch target a valid internal jump?
4085 int internal_branch(uint64_t i_is32,int addr)
4087 if(addr&1) return 0; // Indirect (register) jump
4088 if(addr>=start && addr<start+slen*4-4)
4090 int t=(addr-start)>>2;
4091 // Delay slots are not valid branch targets
4092 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4093 // 64 -> 32 bit transition requires a recompile
4094 /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
4096 if(requires_32bit[t]&~i_is32) printf("optimizable: no\n");
4097 else printf("optimizable: yes\n");
4099 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4101 if(requires_32bit[t]&~i_is32) return 0;
4109 #ifndef wb_invalidate
4110 void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
4111 uint64_t u,uint64_t uu)
4114 for(hr=0;hr<HOST_REGS;hr++) {
4115 if(hr!=EXCLUDE_REG) {
4116 if(pre[hr]!=entry[hr]) {
4119 if(get_reg(entry,pre[hr])<0) {
4121 if(!((u>>pre[hr])&1)) {
4122 emit_storereg(pre[hr],hr);
4123 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
4124 emit_sarimm(hr,31,hr);
4125 emit_storereg(pre[hr]|64,hr);
4129 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
4130 emit_storereg(pre[hr],hr);
4139 // Move from one register to another (no writeback)
4140 for(hr=0;hr<HOST_REGS;hr++) {
4141 if(hr!=EXCLUDE_REG) {
4142 if(pre[hr]!=entry[hr]) {
4143 if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
4145 if((nr=get_reg(entry,pre[hr]))>=0) {
4155 // Load the specified registers
4156 // This only loads the registers given as arguments because
4157 // we don't want to load things that will be overwritten
4158 void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
4162 for(hr=0;hr<HOST_REGS;hr++) {
4163 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4164 if(entry[hr]!=regmap[hr]) {
4165 if(regmap[hr]==rs1||regmap[hr]==rs2)
4172 emit_loadreg(regmap[hr],hr);
4179 for(hr=0;hr<HOST_REGS;hr++) {
4180 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4181 if(entry[hr]!=regmap[hr]) {
4182 if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
4184 assert(regmap[hr]!=64);
4185 if((is32>>(regmap[hr]&63))&1) {
4186 int lr=get_reg(regmap,regmap[hr]-64);
4188 emit_sarimm(lr,31,hr);
4190 emit_loadreg(regmap[hr],hr);
4194 emit_loadreg(regmap[hr],hr);
4202 // Load registers prior to the start of a loop
4203 // so that they are not loaded within the loop
4204 static void loop_preload(signed char pre[],signed char entry[])
4207 for(hr=0;hr<HOST_REGS;hr++) {
4208 if(hr!=EXCLUDE_REG) {
4209 if(pre[hr]!=entry[hr]) {
4211 if(get_reg(pre,entry[hr])<0) {
4212 assem_debug("loop preload:\n");
4213 //printf("loop preload: %d\n",hr);
4217 else if(entry[hr]<TEMPREG)
4219 emit_loadreg(entry[hr],hr);
4221 else if(entry[hr]-64<TEMPREG)
4223 emit_loadreg(entry[hr],hr);
4232 // Generate address for load/store instruction
4233 // goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
4234 void address_generation(int i,struct regstat *i_regs,signed char entry[])
4236 if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS||itype[i]==C2LS) {
4238 int agr=AGEN1+(i&1);
4239 int mgr=MGEN1+(i&1);
4240 if(itype[i]==LOAD) {
4241 ra=get_reg(i_regs->regmap,rt1[i]);
4242 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4245 if(itype[i]==LOADLR) {
4246 ra=get_reg(i_regs->regmap,FTEMP);
4248 if(itype[i]==STORE||itype[i]==STORELR) {
4249 ra=get_reg(i_regs->regmap,agr);
4250 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4252 if(itype[i]==C1LS||itype[i]==C2LS) {
4253 if ((opcode[i]&0x3b)==0x31||(opcode[i]&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
4254 ra=get_reg(i_regs->regmap,FTEMP);
4255 else { // SWC1/SDC1/SWC2/SDC2
4256 ra=get_reg(i_regs->regmap,agr);
4257 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4260 int rs=get_reg(i_regs->regmap,rs1[i]);
4261 int rm=get_reg(i_regs->regmap,TLREG);
4264 int c=(i_regs->wasconst>>rs)&1;
4266 // Using r0 as a base address
4268 if(!entry||entry[rm]!=mgr) {
4269 generate_map_const(offset,rm);
4270 } // else did it in the previous cycle
4272 if(!entry||entry[ra]!=agr) {
4273 if (opcode[i]==0x22||opcode[i]==0x26) {
4274 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4275 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4276 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4278 emit_movimm(offset,ra);
4280 } // else did it in the previous cycle
4283 if(!entry||entry[ra]!=rs1[i])
4284 emit_loadreg(rs1[i],ra);
4285 //if(!entry||entry[ra]!=rs1[i])
4286 // printf("poor load scheduling!\n");
4291 if(!entry||entry[rm]!=mgr) {
4292 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a) {
4293 // Stores to memory go thru the mapper to detect self-modifying
4294 // code, loads don't.
4295 if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
4296 (unsigned int)(constmap[i][rs]+offset)<0x80000000+RAM_SIZE )
4297 generate_map_const(constmap[i][rs]+offset,rm);
4299 if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
4300 generate_map_const(constmap[i][rs]+offset,rm);
4305 if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
4306 if(!entry||entry[ra]!=agr) {
4307 if (opcode[i]==0x22||opcode[i]==0x26) {
4308 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4309 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4310 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4312 #ifdef HOST_IMM_ADDR32
4313 if((itype[i]!=LOAD&&(opcode[i]&0x3b)!=0x31&&(opcode[i]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4314 (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
4316 emit_movimm(constmap[i][rs]+offset,ra);
4317 regs[i].loadedconst|=1<<ra;
4319 } // else did it in the previous cycle
4320 } // else load_consts already did it
4322 if(offset&&!c&&rs1[i]) {
4324 emit_addimm(rs,offset,ra);
4326 emit_addimm(ra,offset,ra);
4331 // Preload constants for next instruction
4332 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
4334 #if !defined(HOST_IMM_ADDR32) && !defined(DISABLE_TLB)
4336 agr=MGEN1+((i+1)&1);
4337 ra=get_reg(i_regs->regmap,agr);
4339 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4340 int offset=imm[i+1];
4341 int c=(regs[i+1].wasconst>>rs)&1;
4343 if(itype[i+1]==STORE||itype[i+1]==STORELR
4344 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1, SWC2/SDC2
4345 // Stores to memory go thru the mapper to detect self-modifying
4346 // code, loads don't.
4347 if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
4348 (unsigned int)(constmap[i+1][rs]+offset)<0x80000000+RAM_SIZE )
4349 generate_map_const(constmap[i+1][rs]+offset,ra);
4351 if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
4352 generate_map_const(constmap[i+1][rs]+offset,ra);
4355 /*else if(rs1[i]==0) {
4356 generate_map_const(offset,ra);
4361 agr=AGEN1+((i+1)&1);
4362 ra=get_reg(i_regs->regmap,agr);
4364 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4365 int offset=imm[i+1];
4366 int c=(regs[i+1].wasconst>>rs)&1;
4367 if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
4368 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4369 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4370 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4371 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4373 #ifdef HOST_IMM_ADDR32
4374 if((itype[i+1]!=LOAD&&(opcode[i+1]&0x3b)!=0x31&&(opcode[i+1]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4375 (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000))
4377 emit_movimm(constmap[i+1][rs]+offset,ra);
4378 regs[i+1].loadedconst|=1<<ra;
4381 else if(rs1[i+1]==0) {
4382 // Using r0 as a base address
4383 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4384 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4385 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4386 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4388 emit_movimm(offset,ra);
4395 int get_final_value(int hr, int i, int *value)
4397 int reg=regs[i].regmap[hr];
4399 if(regs[i+1].regmap[hr]!=reg) break;
4400 if(!((regs[i+1].isconst>>hr)&1)) break;
4405 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
4406 *value=constmap[i][hr];
4410 if(itype[i+1]==UJUMP||itype[i+1]==RJUMP||itype[i+1]==CJUMP||itype[i+1]==SJUMP) {
4411 // Load in delay slot, out-of-order execution
4412 if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
4414 #ifdef HOST_IMM_ADDR32
4415 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+2])<(signed int)0xC0000000) return 0;
4417 // Precompute load address
4418 *value=constmap[i][hr]+imm[i+2];
4422 if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)
4424 #ifdef HOST_IMM_ADDR32
4425 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+1])<(signed int)0xC0000000) return 0;
4427 // Precompute load address
4428 *value=constmap[i][hr]+imm[i+1];
4429 //printf("c=%x imm=%x\n",(int)constmap[i][hr],imm[i+1]);
4434 *value=constmap[i][hr];
4435 //printf("c=%x\n",(int)constmap[i][hr]);
4436 if(i==slen-1) return 1;
4438 return !((unneeded_reg[i+1]>>reg)&1);
4440 return !((unneeded_reg_upper[i+1]>>reg)&1);
4444 // Load registers with known constants
4445 void load_consts(signed char pre[],signed char regmap[],int is32,int i)
4448 // propagate loaded constant flags
4450 regs[i].loadedconst=0;
4452 for(hr=0;hr<HOST_REGS;hr++) {
4453 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((regs[i-1].isconst>>hr)&1)&&pre[hr]==regmap[hr]
4454 &®map[hr]==regs[i-1].regmap[hr]&&((regs[i-1].loadedconst>>hr)&1))
4456 regs[i].loadedconst|=1<<hr;
4461 for(hr=0;hr<HOST_REGS;hr++) {
4462 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4463 //if(entry[hr]!=regmap[hr]) {
4464 if(!((regs[i].loadedconst>>hr)&1)) {
4465 if(((regs[i].isconst>>hr)&1)&®map[hr]<64&®map[hr]>0) {
4466 int value,similar=0;
4467 if(get_final_value(hr,i,&value)) {
4468 // see if some other register has similar value
4469 for(hr2=0;hr2<HOST_REGS;hr2++) {
4470 if(hr2!=EXCLUDE_REG&&((regs[i].loadedconst>>hr2)&1)) {
4471 if(is_similar_value(value,constmap[i][hr2])) {
4479 if(get_final_value(hr2,i,&value2)) // is this needed?
4480 emit_movimm_from(value2,hr2,value,hr);
4482 emit_movimm(value,hr);
4488 emit_movimm(value,hr);
4491 regs[i].loadedconst|=1<<hr;
4497 for(hr=0;hr<HOST_REGS;hr++) {
4498 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4499 //if(entry[hr]!=regmap[hr]) {
4500 if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4501 if(((regs[i].isconst>>hr)&1)&®map[hr]>64) {
4502 if((is32>>(regmap[hr]&63))&1) {
4503 int lr=get_reg(regmap,regmap[hr]-64);
4505 emit_sarimm(lr,31,hr);
4510 if(get_final_value(hr,i,&value)) {
4515 emit_movimm(value,hr);
4524 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i)
4528 for(hr=0;hr<HOST_REGS;hr++) {
4529 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) {
4530 if(((regs[i].isconst>>hr)&1)&®map[hr]<64&®map[hr]>0) {
4531 int value=constmap[i][hr];
4536 emit_movimm(value,hr);
4542 for(hr=0;hr<HOST_REGS;hr++) {
4543 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) {
4544 if(((regs[i].isconst>>hr)&1)&®map[hr]>64) {
4545 if((is32>>(regmap[hr]&63))&1) {
4546 int lr=get_reg(regmap,regmap[hr]-64);
4548 emit_sarimm(lr,31,hr);
4552 int value=constmap[i][hr];
4557 emit_movimm(value,hr);
4565 // Write out all dirty registers (except cycle count)
4566 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty)
4569 for(hr=0;hr<HOST_REGS;hr++) {
4570 if(hr!=EXCLUDE_REG) {
4571 if(i_regmap[hr]>0) {
4572 if(i_regmap[hr]!=CCREG) {
4573 if((i_dirty>>hr)&1) {
4574 if(i_regmap[hr]<64) {
4575 emit_storereg(i_regmap[hr],hr);
4577 if( ((i_is32>>i_regmap[hr])&1) ) {
4578 #ifdef DESTRUCTIVE_WRITEBACK
4579 emit_sarimm(hr,31,hr);
4580 emit_storereg(i_regmap[hr]|64,hr);
4582 emit_sarimm(hr,31,HOST_TEMPREG);
4583 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4588 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4589 emit_storereg(i_regmap[hr],hr);
4598 // Write out dirty registers that we need to reload (pair with load_needed_regs)
4599 // This writes the registers not written by store_regs_bt
4600 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4603 int t=(addr-start)>>2;
4604 for(hr=0;hr<HOST_REGS;hr++) {
4605 if(hr!=EXCLUDE_REG) {
4606 if(i_regmap[hr]>0) {
4607 if(i_regmap[hr]!=CCREG) {
4608 if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1) && !(((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4609 if((i_dirty>>hr)&1) {
4610 if(i_regmap[hr]<64) {
4611 emit_storereg(i_regmap[hr],hr);
4613 if( ((i_is32>>i_regmap[hr])&1) ) {
4614 #ifdef DESTRUCTIVE_WRITEBACK
4615 emit_sarimm(hr,31,hr);
4616 emit_storereg(i_regmap[hr]|64,hr);
4618 emit_sarimm(hr,31,HOST_TEMPREG);
4619 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4624 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4625 emit_storereg(i_regmap[hr],hr);
4636 // Load all registers (except cycle count)
4637 void load_all_regs(signed char i_regmap[])
4640 for(hr=0;hr<HOST_REGS;hr++) {
4641 if(hr!=EXCLUDE_REG) {
4642 if(i_regmap[hr]==0) {
4646 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4648 emit_loadreg(i_regmap[hr],hr);
4654 // Load all current registers also needed by next instruction
4655 void load_needed_regs(signed char i_regmap[],signed char next_regmap[])
4658 for(hr=0;hr<HOST_REGS;hr++) {
4659 if(hr!=EXCLUDE_REG) {
4660 if(get_reg(next_regmap,i_regmap[hr])>=0) {
4661 if(i_regmap[hr]==0) {
4665 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4667 emit_loadreg(i_regmap[hr],hr);
4674 // Load all regs, storing cycle count if necessary
4675 void load_regs_entry(int t)
4678 if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_ADJUST(1),HOST_CCREG);
4679 else if(ccadj[t]) emit_addimm(HOST_CCREG,-CLOCK_ADJUST(ccadj[t]),HOST_CCREG);
4680 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4681 emit_storereg(CCREG,HOST_CCREG);
4684 for(hr=0;hr<HOST_REGS;hr++) {
4685 if(regs[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) {
4686 if(regs[t].regmap_entry[hr]==0) {
4689 else if(regs[t].regmap_entry[hr]!=CCREG)
4691 emit_loadreg(regs[t].regmap_entry[hr],hr);
4696 for(hr=0;hr<HOST_REGS;hr++) {
4697 if(regs[t].regmap_entry[hr]>=64&®s[t].regmap_entry[hr]<TEMPREG+64) {
4698 assert(regs[t].regmap_entry[hr]!=64);
4699 if((regs[t].was32>>(regs[t].regmap_entry[hr]&63))&1) {
4700 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4702 emit_loadreg(regs[t].regmap_entry[hr],hr);
4706 emit_sarimm(lr,31,hr);
4711 emit_loadreg(regs[t].regmap_entry[hr],hr);
4717 // Store dirty registers prior to branch
4718 void store_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4720 if(internal_branch(i_is32,addr))
4722 int t=(addr-start)>>2;
4724 for(hr=0;hr<HOST_REGS;hr++) {
4725 if(hr!=EXCLUDE_REG) {
4726 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4727 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4728 if((i_dirty>>hr)&1) {
4729 if(i_regmap[hr]<64) {
4730 if(!((unneeded_reg[t]>>i_regmap[hr])&1)) {
4731 emit_storereg(i_regmap[hr],hr);
4732 if( ((i_is32>>i_regmap[hr])&1) && !((unneeded_reg_upper[t]>>i_regmap[hr])&1) ) {
4733 #ifdef DESTRUCTIVE_WRITEBACK
4734 emit_sarimm(hr,31,hr);
4735 emit_storereg(i_regmap[hr]|64,hr);
4737 emit_sarimm(hr,31,HOST_TEMPREG);
4738 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4743 if( !((i_is32>>(i_regmap[hr]&63))&1) && !((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1) ) {
4744 emit_storereg(i_regmap[hr],hr);
4755 // Branch out of this block, write out all dirty regs
4756 wb_dirtys(i_regmap,i_is32,i_dirty);
4760 // Load all needed registers for branch target
4761 void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4763 //if(addr>=start && addr<(start+slen*4))
4764 if(internal_branch(i_is32,addr))
4766 int t=(addr-start)>>2;
4768 // Store the cycle count before loading something else
4769 if(i_regmap[HOST_CCREG]!=CCREG) {
4770 assert(i_regmap[HOST_CCREG]==-1);
4772 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4773 emit_storereg(CCREG,HOST_CCREG);
4776 for(hr=0;hr<HOST_REGS;hr++) {
4777 if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) {
4778 #ifdef DESTRUCTIVE_WRITEBACK
4779 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || ( !((regs[t].dirty>>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4781 if(i_regmap[hr]!=regs[t].regmap_entry[hr] ) {
4783 if(regs[t].regmap_entry[hr]==0) {
4786 else if(regs[t].regmap_entry[hr]!=CCREG)
4788 emit_loadreg(regs[t].regmap_entry[hr],hr);
4794 for(hr=0;hr<HOST_REGS;hr++) {
4795 if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=64&®s[t].regmap_entry[hr]<TEMPREG+64) {
4796 if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4797 assert(regs[t].regmap_entry[hr]!=64);
4798 if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4799 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4801 emit_loadreg(regs[t].regmap_entry[hr],hr);
4805 emit_sarimm(lr,31,hr);
4810 emit_loadreg(regs[t].regmap_entry[hr],hr);
4813 else if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4814 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4816 emit_sarimm(lr,31,hr);
4823 int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4825 if(addr>=start && addr<start+slen*4-4)
4827 int t=(addr-start)>>2;
4829 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4830 for(hr=0;hr<HOST_REGS;hr++)
4834 if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4836 if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
4843 if(i_regmap[hr]<TEMPREG)
4845 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4848 else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
4850 if(!((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1))
4855 else // Same register but is it 32-bit or dirty?
4858 if(!((regs[t].dirty>>hr)&1))
4862 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4864 //printf("%x: dirty no match\n",addr);
4869 if((((regs[t].was32^i_is32)&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)
4871 //printf("%x: is32 no match\n",addr);
4877 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4879 if(requires_32bit[t]&~i_is32) return 0;
4881 // Delay slots are not valid branch targets
4882 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4883 // Delay slots require additional processing, so do not match
4884 if(is_ds[t]) return 0;
4889 for(hr=0;hr<HOST_REGS;hr++)
4895 if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4909 // Used when a branch jumps into the delay slot of another branch
4910 void ds_assemble_entry(int i)
4912 int t=(ba[i]-start)>>2;
4913 if(!instr_addr[t]) instr_addr[t]=(u_int)out;
4914 assem_debug("Assemble delay slot at %x\n",ba[i]);
4915 assem_debug("<->\n");
4916 if(regs[t].regmap_entry[HOST_CCREG]==CCREG&®s[t].regmap[HOST_CCREG]!=CCREG)
4917 wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty,regs[t].was32);
4918 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,rs1[t],rs2[t]);
4919 address_generation(t,®s[t],regs[t].regmap_entry);
4920 if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39||(opcode[t]&0x3b)==0x3a)
4921 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,INVCP,INVCP);
4926 alu_assemble(t,®s[t]);break;
4928 imm16_assemble(t,®s[t]);break;
4930 shift_assemble(t,®s[t]);break;
4932 shiftimm_assemble(t,®s[t]);break;
4934 load_assemble(t,®s[t]);break;
4936 loadlr_assemble(t,®s[t]);break;
4938 store_assemble(t,®s[t]);break;
4940 storelr_assemble(t,®s[t]);break;
4942 cop0_assemble(t,®s[t]);break;
4944 cop1_assemble(t,®s[t]);break;
4946 c1ls_assemble(t,®s[t]);break;
4948 cop2_assemble(t,®s[t]);break;
4950 c2ls_assemble(t,®s[t]);break;
4952 c2op_assemble(t,®s[t]);break;
4954 fconv_assemble(t,®s[t]);break;
4956 float_assemble(t,®s[t]);break;
4958 fcomp_assemble(t,®s[t]);break;
4960 multdiv_assemble(t,®s[t]);break;
4962 mov_assemble(t,®s[t]);break;
4972 printf("Jump in the delay slot. This is probably a bug.\n");
4974 store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4975 load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4976 if(internal_branch(regs[t].is32,ba[i]+4))
4977 assem_debug("branch: internal\n");
4979 assem_debug("branch: external\n");
4980 assert(internal_branch(regs[t].is32,ba[i]+4));
4981 add_to_linker((int)out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4));
4985 void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
4995 //if(ba[i]>=start && ba[i]<(start+slen*4))
4996 if(internal_branch(branch_regs[i].is32,ba[i]))
4999 if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
5007 if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
5009 if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
5011 //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
5012 emit_andimm(HOST_CCREG,3,HOST_CCREG);
5016 else if(*adj==0||invert) {
5017 int cycles=CLOCK_ADJUST(count+2);
5021 if(-NO_CYCLE_PENALTY_THR<rel&&rel<0)
5022 cycles=CLOCK_ADJUST(*adj)+count+2-*adj;
5024 emit_addimm_and_set_flags(cycles,HOST_CCREG);
5030 emit_cmpimm(HOST_CCREG,-CLOCK_ADJUST(count+2));
5034 add_stub(CC_STUB,jaddr,idle?idle:(int)out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
5037 void do_ccstub(int n)
5040 assem_debug("do_ccstub %x\n",start+stubs[n][4]*4);
5041 set_jump_target(stubs[n][1],(int)out);
5043 if(stubs[n][6]==NULLDS) {
5044 // Delay slot instruction is nullified ("likely" branch)
5045 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
5047 else if(stubs[n][6]!=TAKEN) {
5048 wb_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty);
5051 if(internal_branch(branch_regs[i].is32,ba[i]))
5052 wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5056 // Save PC as return address
5057 emit_movimm(stubs[n][5],EAX);
5058 emit_writeword(EAX,(int)&pcaddr);
5062 // Return address depends on which way the branch goes
5063 if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
5065 int s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5066 int s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5067 int s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5068 int s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5078 if((branch_regs[i].is32>>rs1[i])&(branch_regs[i].is32>>rs2[i])&1) {
5082 #ifdef DESTRUCTIVE_WRITEBACK
5084 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1)
5085 emit_loadreg(rs1[i],s1l);
5088 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1)
5089 emit_loadreg(rs2[i],s1l);
5092 if((branch_regs[i].dirty>>s2l)&(branch_regs[i].is32>>rs2[i])&1)
5093 emit_loadreg(rs2[i],s2l);
5096 int addr=-1,alt=-1,ntaddr=-1;
5099 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5100 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5101 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5109 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5110 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5111 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5117 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
5121 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5122 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5123 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5129 assert(hr<HOST_REGS);
5131 if((opcode[i]&0x2f)==4) // BEQ
5133 #ifdef HAVE_CMOV_IMM
5135 if(s2l>=0) emit_cmp(s1l,s2l);
5136 else emit_test(s1l,s1l);
5137 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
5142 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5144 if(s2h>=0) emit_cmp(s1h,s2h);
5145 else emit_test(s1h,s1h);
5146 emit_cmovne_reg(alt,addr);
5148 if(s2l>=0) emit_cmp(s1l,s2l);
5149 else emit_test(s1l,s1l);
5150 emit_cmovne_reg(alt,addr);
5153 if((opcode[i]&0x2f)==5) // BNE
5155 #ifdef HAVE_CMOV_IMM
5157 if(s2l>=0) emit_cmp(s1l,s2l);
5158 else emit_test(s1l,s1l);
5159 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
5164 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
5166 if(s2h>=0) emit_cmp(s1h,s2h);
5167 else emit_test(s1h,s1h);
5168 emit_cmovne_reg(alt,addr);
5170 if(s2l>=0) emit_cmp(s1l,s2l);
5171 else emit_test(s1l,s1l);
5172 emit_cmovne_reg(alt,addr);
5175 if((opcode[i]&0x2f)==6) // BLEZ
5177 //emit_movimm(ba[i],alt);
5178 //emit_movimm(start+i*4+8,addr);
5179 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5181 if(s1h>=0) emit_mov(addr,ntaddr);
5182 emit_cmovl_reg(alt,addr);
5185 emit_cmovne_reg(ntaddr,addr);
5186 emit_cmovs_reg(alt,addr);
5189 if((opcode[i]&0x2f)==7) // BGTZ
5191 //emit_movimm(ba[i],addr);
5192 //emit_movimm(start+i*4+8,ntaddr);
5193 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
5195 if(s1h>=0) emit_mov(addr,alt);
5196 emit_cmovl_reg(ntaddr,addr);
5199 emit_cmovne_reg(alt,addr);
5200 emit_cmovs_reg(ntaddr,addr);
5203 if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ
5205 //emit_movimm(ba[i],alt);
5206 //emit_movimm(start+i*4+8,addr);
5207 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5208 if(s1h>=0) emit_test(s1h,s1h);
5209 else emit_test(s1l,s1l);
5210 emit_cmovs_reg(alt,addr);
5212 if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ
5214 //emit_movimm(ba[i],addr);
5215 //emit_movimm(start+i*4+8,alt);
5216 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5217 if(s1h>=0) emit_test(s1h,s1h);
5218 else emit_test(s1l,s1l);
5219 emit_cmovs_reg(alt,addr);
5221 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
5222 if(source[i]&0x10000) // BC1T
5224 //emit_movimm(ba[i],alt);
5225 //emit_movimm(start+i*4+8,addr);
5226 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5227 emit_testimm(s1l,0x800000);
5228 emit_cmovne_reg(alt,addr);
5232 //emit_movimm(ba[i],addr);
5233 //emit_movimm(start+i*4+8,alt);
5234 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5235 emit_testimm(s1l,0x800000);
5236 emit_cmovne_reg(alt,addr);
5239 emit_writeword(addr,(int)&pcaddr);
5244 int r=get_reg(branch_regs[i].regmap,rs1[i]);
5245 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5246 r=get_reg(branch_regs[i].regmap,RTEMP);
5248 emit_writeword(r,(int)&pcaddr);
5250 else {printf("Unknown branch type in do_ccstub\n");exit(1);}
5252 // Update cycle count
5253 assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
5254 if(stubs[n][3]) emit_addimm(HOST_CCREG,CLOCK_ADJUST((int)stubs[n][3]),HOST_CCREG);
5255 emit_call((int)cc_interrupt);
5256 if(stubs[n][3]) emit_addimm(HOST_CCREG,-CLOCK_ADJUST((int)stubs[n][3]),HOST_CCREG);
5257 if(stubs[n][6]==TAKEN) {
5258 if(internal_branch(branch_regs[i].is32,ba[i]))
5259 load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
5260 else if(itype[i]==RJUMP) {
5261 if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
5262 emit_readword((int)&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
5264 emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i]));
5266 }else if(stubs[n][6]==NOTTAKEN) {
5267 if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5268 else load_all_regs(branch_regs[i].regmap);
5269 }else if(stubs[n][6]==NULLDS) {
5270 // Delay slot instruction is nullified ("likely" branch)
5271 if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
5272 else load_all_regs(regs[i].regmap);
5274 load_all_regs(branch_regs[i].regmap);
5276 emit_jmp(stubs[n][2]); // return address
5278 /* This works but uses a lot of memory...
5279 emit_readword((int)&last_count,ECX);
5280 emit_add(HOST_CCREG,ECX,EAX);
5281 emit_writeword(EAX,(int)&Count);
5282 emit_call((int)gen_interupt);
5283 emit_readword((int)&Count,HOST_CCREG);
5284 emit_readword((int)&next_interupt,EAX);
5285 emit_readword((int)&pending_exception,EBX);
5286 emit_writeword(EAX,(int)&last_count);
5287 emit_sub(HOST_CCREG,EAX,HOST_CCREG);
5289 int jne_instr=(int)out;
5291 if(stubs[n][3]) emit_addimm(HOST_CCREG,-2*stubs[n][3],HOST_CCREG);
5292 load_all_regs(branch_regs[i].regmap);
5293 emit_jmp(stubs[n][2]); // return address
5294 set_jump_target(jne_instr,(int)out);
5295 emit_readword((int)&pcaddr,EAX);
5296 // Call get_addr_ht instead of doing the hash table here.
5297 // This code is executed infrequently and takes up a lot of space
5298 // so smaller is better.
5299 emit_storereg(CCREG,HOST_CCREG);
5301 emit_call((int)get_addr_ht);
5302 emit_loadreg(CCREG,HOST_CCREG);
5303 emit_addimm(ESP,4,ESP);
5307 add_to_linker(int addr,int target,int ext)
5309 link_addr[linkcount][0]=addr;
5310 link_addr[linkcount][1]=target;
5311 link_addr[linkcount][2]=ext;
5315 static void ujump_assemble_write_ra(int i)
5318 unsigned int return_address;
5319 rt=get_reg(branch_regs[i].regmap,31);
5320 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5322 return_address=start+i*4+8;
5325 if(internal_branch(branch_regs[i].is32,return_address)&&rt1[i+1]!=31) {
5326 int temp=-1; // note: must be ds-safe
5330 if(temp>=0) do_miniht_insert(return_address,rt,temp);
5331 else emit_movimm(return_address,rt);
5339 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5342 emit_movimm(return_address,rt); // PC into link register
5344 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5350 void ujump_assemble(int i,struct regstat *i_regs)
5352 signed char *i_regmap=i_regs->regmap;
5354 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5355 address_generation(i+1,i_regs,regs[i].regmap_entry);
5357 int temp=get_reg(branch_regs[i].regmap,PTEMP);
5358 if(rt1[i]==31&&temp>=0)
5360 int return_address=start+i*4+8;
5361 if(get_reg(branch_regs[i].regmap,31)>0)
5362 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5365 if(rt1[i]==31&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
5366 ujump_assemble_write_ra(i); // writeback ra for DS
5369 ds_assemble(i+1,i_regs);
5370 uint64_t bc_unneeded=branch_regs[i].u;
5371 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5372 bc_unneeded|=1|(1LL<<rt1[i]);
5373 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5374 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5375 bc_unneeded,bc_unneeded_upper);
5376 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5377 if(!ra_done&&rt1[i]==31)
5378 ujump_assemble_write_ra(i);
5380 cc=get_reg(branch_regs[i].regmap,CCREG);
5381 assert(cc==HOST_CCREG);
5382 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5384 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5386 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5387 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5388 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5389 if(internal_branch(branch_regs[i].is32,ba[i]))
5390 assem_debug("branch: internal\n");
5392 assem_debug("branch: external\n");
5393 if(internal_branch(branch_regs[i].is32,ba[i])&&is_ds[(ba[i]-start)>>2]) {
5394 ds_assemble_entry(i);
5397 add_to_linker((int)out,ba[i],internal_branch(branch_regs[i].is32,ba[i]));
5402 static void rjump_assemble_write_ra(int i)
5404 int rt,return_address;
5405 assert(rt1[i+1]!=rt1[i]);
5406 assert(rt2[i+1]!=rt1[i]);
5407 rt=get_reg(branch_regs[i].regmap,rt1[i]);
5408 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5410 return_address=start+i*4+8;
5414 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5417 emit_movimm(return_address,rt); // PC into link register
5419 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5423 void rjump_assemble(int i,struct regstat *i_regs)
5425 signed char *i_regmap=i_regs->regmap;
5429 rs=get_reg(branch_regs[i].regmap,rs1[i]);
5431 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5432 // Delay slot abuse, make a copy of the branch address register
5433 temp=get_reg(branch_regs[i].regmap,RTEMP);
5435 assert(regs[i].regmap[temp]==RTEMP);
5439 address_generation(i+1,i_regs,regs[i].regmap_entry);
5443 if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5444 int return_address=start+i*4+8;
5445 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5451 int rh=get_reg(regs[i].regmap,RHASH);
5452 if(rh>=0) do_preload_rhash(rh);
5455 if(rt1[i]!=0&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
5456 rjump_assemble_write_ra(i);
5459 ds_assemble(i+1,i_regs);
5460 uint64_t bc_unneeded=branch_regs[i].u;
5461 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5462 bc_unneeded|=1|(1LL<<rt1[i]);
5463 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5464 bc_unneeded&=~(1LL<<rs1[i]);
5465 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5466 bc_unneeded,bc_unneeded_upper);
5467 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
5468 if(!ra_done&&rt1[i]!=0)
5469 rjump_assemble_write_ra(i);
5470 cc=get_reg(branch_regs[i].regmap,CCREG);
5471 assert(cc==HOST_CCREG);
5473 int rh=get_reg(branch_regs[i].regmap,RHASH);
5474 int ht=get_reg(branch_regs[i].regmap,RHTBL);
5476 if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5477 do_preload_rhtbl(ht);
5481 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5482 #ifdef DESTRUCTIVE_WRITEBACK
5483 if((branch_regs[i].dirty>>rs)&(branch_regs[i].is32>>rs1[i])&1) {
5484 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
5485 emit_loadreg(rs1[i],rs);
5490 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5494 do_miniht_load(ht,rh);
5497 //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5498 //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5500 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
5501 add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
5503 if(itype[i+1]==COP0&&(source[i+1]&0x3f)==0x10)
5504 // special case for RFE
5509 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5512 do_miniht_jump(rs,rh,ht);
5517 //if(rs!=EAX) emit_mov(rs,EAX);
5518 //emit_jmp((int)jump_vaddr_eax);
5519 emit_jmp(jump_vaddr_reg[rs]);
5524 emit_shrimm(rs,16,rs);
5525 emit_xor(temp,rs,rs);
5526 emit_movzwl_reg(rs,rs);
5527 emit_shlimm(rs,4,rs);
5528 emit_cmpmem_indexed((int)hash_table,rs,temp);
5529 emit_jne((int)out+14);
5530 emit_readword_indexed((int)hash_table+4,rs,rs);
5532 emit_cmpmem_indexed((int)hash_table+8,rs,temp);
5533 emit_addimm_no_flags(8,rs);
5534 emit_jeq((int)out-17);
5535 // No hit on hash table, call compiler
5538 #ifdef DEBUG_CYCLE_COUNT
5539 emit_readword((int)&last_count,ECX);
5540 emit_add(HOST_CCREG,ECX,HOST_CCREG);
5541 emit_readword((int)&next_interupt,ECX);
5542 emit_writeword(HOST_CCREG,(int)&Count);
5543 emit_sub(HOST_CCREG,ECX,HOST_CCREG);
5544 emit_writeword(ECX,(int)&last_count);
5547 emit_storereg(CCREG,HOST_CCREG);
5548 emit_call((int)get_addr);
5549 emit_loadreg(CCREG,HOST_CCREG);
5550 emit_addimm(ESP,4,ESP);
5552 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5553 if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5557 void cjump_assemble(int i,struct regstat *i_regs)
5559 signed char *i_regmap=i_regs->regmap;
5562 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5563 assem_debug("match=%d\n",match);
5564 int s1h,s1l,s2h,s2l;
5565 int prev_cop1_usable=cop1_usable;
5566 int unconditional=0,nop=0;
5569 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5570 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5571 if(!match) invert=1;
5572 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5573 if(i>(ba[i]-start)>>2) invert=1;
5577 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5578 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5579 s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5580 s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5583 s1l=get_reg(i_regmap,rs1[i]);
5584 s1h=get_reg(i_regmap,rs1[i]|64);
5585 s2l=get_reg(i_regmap,rs2[i]);
5586 s2h=get_reg(i_regmap,rs2[i]|64);
5588 if(rs1[i]==0&&rs2[i]==0)
5590 if(opcode[i]&1) nop=1;
5591 else unconditional=1;
5592 //assert(opcode[i]!=5);
5593 //assert(opcode[i]!=7);
5594 //assert(opcode[i]!=0x15);
5595 //assert(opcode[i]!=0x17);
5601 only32=(regs[i].was32>>rs2[i])&1;
5606 only32=(regs[i].was32>>rs1[i])&1;
5609 only32=(regs[i].was32>>rs1[i])&(regs[i].was32>>rs2[i])&1;
5613 // Out of order execution (delay slot first)
5615 address_generation(i+1,i_regs,regs[i].regmap_entry);
5616 ds_assemble(i+1,i_regs);
5618 uint64_t bc_unneeded=branch_regs[i].u;
5619 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5620 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5621 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5623 bc_unneeded_upper|=1;
5624 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5625 bc_unneeded,bc_unneeded_upper);
5626 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
5627 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5628 cc=get_reg(branch_regs[i].regmap,CCREG);
5629 assert(cc==HOST_CCREG);
5631 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5632 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5633 //assem_debug("cycle count (adj)\n");
5635 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5636 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5637 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5638 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5640 assem_debug("branch: internal\n");
5642 assem_debug("branch: external\n");
5643 if(internal&&is_ds[(ba[i]-start)>>2]) {
5644 ds_assemble_entry(i);
5647 add_to_linker((int)out,ba[i],internal);
5650 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5651 if(((u_int)out)&7) emit_addnop(0);
5656 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5659 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5662 int taken=0,nottaken=0,nottaken1=0;
5663 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5664 if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5668 if(opcode[i]==4) // BEQ
5670 if(s2h>=0) emit_cmp(s1h,s2h);
5671 else emit_test(s1h,s1h);
5675 if(opcode[i]==5) // BNE
5677 if(s2h>=0) emit_cmp(s1h,s2h);
5678 else emit_test(s1h,s1h);
5679 if(invert) taken=(int)out;
5680 else add_to_linker((int)out,ba[i],internal);
5683 if(opcode[i]==6) // BLEZ
5686 if(invert) taken=(int)out;
5687 else add_to_linker((int)out,ba[i],internal);
5692 if(opcode[i]==7) // BGTZ
5697 if(invert) taken=(int)out;
5698 else add_to_linker((int)out,ba[i],internal);
5703 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5705 if(opcode[i]==4) // BEQ
5707 if(s2l>=0) emit_cmp(s1l,s2l);
5708 else emit_test(s1l,s1l);
5713 add_to_linker((int)out,ba[i],internal);
5717 if(opcode[i]==5) // BNE
5719 if(s2l>=0) emit_cmp(s1l,s2l);
5720 else emit_test(s1l,s1l);
5725 add_to_linker((int)out,ba[i],internal);
5729 if(opcode[i]==6) // BLEZ
5736 add_to_linker((int)out,ba[i],internal);
5740 if(opcode[i]==7) // BGTZ
5747 add_to_linker((int)out,ba[i],internal);
5752 if(taken) set_jump_target(taken,(int)out);
5753 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5754 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5756 emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
5757 add_to_linker((int)out,ba[i],internal);
5760 add_to_linker((int)out,ba[i],internal*2);
5766 if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
5767 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5768 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5770 assem_debug("branch: internal\n");
5772 assem_debug("branch: external\n");
5773 if(internal&&is_ds[(ba[i]-start)>>2]) {
5774 ds_assemble_entry(i);
5777 add_to_linker((int)out,ba[i],internal);
5781 set_jump_target(nottaken,(int)out);
5784 if(nottaken1) set_jump_target(nottaken1,(int)out);
5786 if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
5788 } // (!unconditional)
5792 // In-order execution (branch first)
5793 //if(likely[i]) printf("IOL\n");
5796 int taken=0,nottaken=0,nottaken1=0;
5797 if(!unconditional&&!nop) {
5801 if((opcode[i]&0x2f)==4) // BEQ
5803 if(s2h>=0) emit_cmp(s1h,s2h);
5804 else emit_test(s1h,s1h);
5808 if((opcode[i]&0x2f)==5) // BNE
5810 if(s2h>=0) emit_cmp(s1h,s2h);
5811 else emit_test(s1h,s1h);
5815 if((opcode[i]&0x2f)==6) // BLEZ
5823 if((opcode[i]&0x2f)==7) // BGTZ
5833 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5835 if((opcode[i]&0x2f)==4) // BEQ
5837 if(s2l>=0) emit_cmp(s1l,s2l);
5838 else emit_test(s1l,s1l);
5842 if((opcode[i]&0x2f)==5) // BNE
5844 if(s2l>=0) emit_cmp(s1l,s2l);
5845 else emit_test(s1l,s1l);
5849 if((opcode[i]&0x2f)==6) // BLEZ
5855 if((opcode[i]&0x2f)==7) // BGTZ
5861 } // if(!unconditional)
5863 uint64_t ds_unneeded=branch_regs[i].u;
5864 uint64_t ds_unneeded_upper=branch_regs[i].uu;
5865 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5866 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5867 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5869 ds_unneeded_upper|=1;
5872 if(taken) set_jump_target(taken,(int)out);
5873 assem_debug("1:\n");
5874 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5875 ds_unneeded,ds_unneeded_upper);
5877 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5878 address_generation(i+1,&branch_regs[i],0);
5879 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5880 ds_assemble(i+1,&branch_regs[i]);
5881 cc=get_reg(branch_regs[i].regmap,CCREG);
5883 emit_loadreg(CCREG,cc=HOST_CCREG);
5884 // CHECK: Is the following instruction (fall thru) allocated ok?
5886 assert(cc==HOST_CCREG);
5887 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5888 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5889 assem_debug("cycle count (adj)\n");
5890 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5891 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5893 assem_debug("branch: internal\n");
5895 assem_debug("branch: external\n");
5896 if(internal&&is_ds[(ba[i]-start)>>2]) {
5897 ds_assemble_entry(i);
5900 add_to_linker((int)out,ba[i],internal);
5905 cop1_usable=prev_cop1_usable;
5906 if(!unconditional) {
5907 if(nottaken1) set_jump_target(nottaken1,(int)out);
5908 set_jump_target(nottaken,(int)out);
5909 assem_debug("2:\n");
5911 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5912 ds_unneeded,ds_unneeded_upper);
5913 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5914 address_generation(i+1,&branch_regs[i],0);
5915 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5916 ds_assemble(i+1,&branch_regs[i]);
5918 cc=get_reg(branch_regs[i].regmap,CCREG);
5919 if(cc==-1&&!likely[i]) {
5920 // Cycle count isn't in a register, temporarily load it then write it out
5921 emit_loadreg(CCREG,HOST_CCREG);
5922 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
5925 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5926 emit_storereg(CCREG,HOST_CCREG);
5929 cc=get_reg(i_regmap,CCREG);
5930 assert(cc==HOST_CCREG);
5931 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5934 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5940 void sjump_assemble(int i,struct regstat *i_regs)
5942 signed char *i_regmap=i_regs->regmap;
5945 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5946 assem_debug("smatch=%d\n",match);
5948 int prev_cop1_usable=cop1_usable;
5949 int unconditional=0,nevertaken=0;
5952 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5953 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5954 if(!match) invert=1;
5955 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5956 if(i>(ba[i]-start)>>2) invert=1;
5959 //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
5960 //assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
5963 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5964 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5967 s1l=get_reg(i_regmap,rs1[i]);
5968 s1h=get_reg(i_regmap,rs1[i]|64);
5972 if(opcode2[i]&1) unconditional=1;
5974 // These are never taken (r0 is never less than zero)
5975 //assert(opcode2[i]!=0);
5976 //assert(opcode2[i]!=2);
5977 //assert(opcode2[i]!=0x10);
5978 //assert(opcode2[i]!=0x12);
5981 only32=(regs[i].was32>>rs1[i])&1;
5985 // Out of order execution (delay slot first)
5987 address_generation(i+1,i_regs,regs[i].regmap_entry);
5988 ds_assemble(i+1,i_regs);
5990 uint64_t bc_unneeded=branch_regs[i].u;
5991 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5992 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5993 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5995 bc_unneeded_upper|=1;
5996 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5997 bc_unneeded,bc_unneeded_upper);
5998 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5999 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6001 int rt,return_address;
6002 rt=get_reg(branch_regs[i].regmap,31);
6003 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6005 // Save the PC even if the branch is not taken
6006 return_address=start+i*4+8;
6007 emit_movimm(return_address,rt); // PC into link register
6009 if(!nevertaken) emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
6013 cc=get_reg(branch_regs[i].regmap,CCREG);
6014 assert(cc==HOST_CCREG);
6016 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6017 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
6018 assem_debug("cycle count (adj)\n");
6020 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
6021 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
6022 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6023 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6025 assem_debug("branch: internal\n");
6027 assem_debug("branch: external\n");
6028 if(internal&&is_ds[(ba[i]-start)>>2]) {
6029 ds_assemble_entry(i);
6032 add_to_linker((int)out,ba[i],internal);
6035 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6036 if(((u_int)out)&7) emit_addnop(0);
6040 else if(nevertaken) {
6041 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
6044 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6048 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
6049 if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6053 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
6060 add_to_linker((int)out,ba[i],internal);
6064 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
6071 add_to_linker((int)out,ba[i],internal);
6079 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
6086 add_to_linker((int)out,ba[i],internal);
6090 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
6097 add_to_linker((int)out,ba[i],internal);
6104 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6105 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
6107 emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
6108 add_to_linker((int)out,ba[i],internal);
6111 add_to_linker((int)out,ba[i],internal*2);
6117 if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
6118 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6119 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6121 assem_debug("branch: internal\n");
6123 assem_debug("branch: external\n");
6124 if(internal&&is_ds[(ba[i]-start)>>2]) {
6125 ds_assemble_entry(i);
6128 add_to_linker((int)out,ba[i],internal);
6132 set_jump_target(nottaken,(int)out);
6136 if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
6138 } // (!unconditional)
6142 // In-order execution (branch first)
6146 int rt,return_address;
6147 rt=get_reg(branch_regs[i].regmap,31);
6149 // Save the PC even if the branch is not taken
6150 return_address=start+i*4+8;
6151 emit_movimm(return_address,rt); // PC into link register
6153 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
6157 if(!unconditional) {
6158 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6162 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
6168 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
6178 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
6184 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
6191 } // if(!unconditional)
6193 uint64_t ds_unneeded=branch_regs[i].u;
6194 uint64_t ds_unneeded_upper=branch_regs[i].uu;
6195 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6196 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6197 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6199 ds_unneeded_upper|=1;
6202 //assem_debug("1:\n");
6203 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6204 ds_unneeded,ds_unneeded_upper);
6206 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6207 address_generation(i+1,&branch_regs[i],0);
6208 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6209 ds_assemble(i+1,&branch_regs[i]);
6210 cc=get_reg(branch_regs[i].regmap,CCREG);
6212 emit_loadreg(CCREG,cc=HOST_CCREG);
6213 // CHECK: Is the following instruction (fall thru) allocated ok?
6215 assert(cc==HOST_CCREG);
6216 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6217 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6218 assem_debug("cycle count (adj)\n");
6219 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6220 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6222 assem_debug("branch: internal\n");
6224 assem_debug("branch: external\n");
6225 if(internal&&is_ds[(ba[i]-start)>>2]) {
6226 ds_assemble_entry(i);
6229 add_to_linker((int)out,ba[i],internal);
6234 cop1_usable=prev_cop1_usable;
6235 if(!unconditional) {
6236 set_jump_target(nottaken,(int)out);
6237 assem_debug("1:\n");
6239 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6240 ds_unneeded,ds_unneeded_upper);
6241 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6242 address_generation(i+1,&branch_regs[i],0);
6243 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6244 ds_assemble(i+1,&branch_regs[i]);
6246 cc=get_reg(branch_regs[i].regmap,CCREG);
6247 if(cc==-1&&!likely[i]) {
6248 // Cycle count isn't in a register, temporarily load it then write it out
6249 emit_loadreg(CCREG,HOST_CCREG);
6250 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
6253 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6254 emit_storereg(CCREG,HOST_CCREG);
6257 cc=get_reg(i_regmap,CCREG);
6258 assert(cc==HOST_CCREG);
6259 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
6262 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6268 void fjump_assemble(int i,struct regstat *i_regs)
6270 signed char *i_regmap=i_regs->regmap;
6273 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6274 assem_debug("fmatch=%d\n",match);
6278 int internal=internal_branch(branch_regs[i].is32,ba[i]);
6279 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
6280 if(!match) invert=1;
6281 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6282 if(i>(ba[i]-start)>>2) invert=1;
6286 fs=get_reg(branch_regs[i].regmap,FSREG);
6287 address_generation(i+1,i_regs,regs[i].regmap_entry); // Is this okay?
6290 fs=get_reg(i_regmap,FSREG);
6293 // Check cop1 unusable
6295 cs=get_reg(i_regmap,CSREG);
6297 emit_testimm(cs,0x20000000);
6300 add_stub(FP_STUB,eaddr,(int)out,i,cs,(int)i_regs,0,0);
6305 // Out of order execution (delay slot first)
6307 ds_assemble(i+1,i_regs);
6309 uint64_t bc_unneeded=branch_regs[i].u;
6310 uint64_t bc_unneeded_upper=branch_regs[i].uu;
6311 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6312 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
6314 bc_unneeded_upper|=1;
6315 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6316 bc_unneeded,bc_unneeded_upper);
6317 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
6318 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6319 cc=get_reg(branch_regs[i].regmap,CCREG);
6320 assert(cc==HOST_CCREG);
6321 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
6322 assem_debug("cycle count (adj)\n");
6325 if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6328 emit_testimm(fs,0x800000);
6329 if(source[i]&0x10000) // BC1T
6335 add_to_linker((int)out,ba[i],internal);
6344 add_to_linker((int)out,ba[i],internal);
6352 if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
6353 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6354 else if(match) emit_addnop(13);
6356 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6357 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6359 assem_debug("branch: internal\n");
6361 assem_debug("branch: external\n");
6362 if(internal&&is_ds[(ba[i]-start)>>2]) {
6363 ds_assemble_entry(i);
6366 add_to_linker((int)out,ba[i],internal);
6369 set_jump_target(nottaken,(int)out);
6373 if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
6375 } // (!unconditional)
6379 // In-order execution (branch first)
6383 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6386 emit_testimm(fs,0x800000);
6387 if(source[i]&0x10000) // BC1T
6398 } // if(!unconditional)
6400 uint64_t ds_unneeded=branch_regs[i].u;
6401 uint64_t ds_unneeded_upper=branch_regs[i].uu;
6402 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6403 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6404 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6406 ds_unneeded_upper|=1;
6408 //assem_debug("1:\n");
6409 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6410 ds_unneeded,ds_unneeded_upper);
6412 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6413 address_generation(i+1,&branch_regs[i],0);
6414 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6415 ds_assemble(i+1,&branch_regs[i]);
6416 cc=get_reg(branch_regs[i].regmap,CCREG);
6418 emit_loadreg(CCREG,cc=HOST_CCREG);
6419 // CHECK: Is the following instruction (fall thru) allocated ok?
6421 assert(cc==HOST_CCREG);
6422 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6423 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6424 assem_debug("cycle count (adj)\n");
6425 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6426 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6428 assem_debug("branch: internal\n");
6430 assem_debug("branch: external\n");
6431 if(internal&&is_ds[(ba[i]-start)>>2]) {
6432 ds_assemble_entry(i);
6435 add_to_linker((int)out,ba[i],internal);
6440 if(1) { // <- FIXME (don't need this)
6441 set_jump_target(nottaken,(int)out);
6442 assem_debug("1:\n");
6444 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6445 ds_unneeded,ds_unneeded_upper);
6446 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6447 address_generation(i+1,&branch_regs[i],0);
6448 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6449 ds_assemble(i+1,&branch_regs[i]);
6451 cc=get_reg(branch_regs[i].regmap,CCREG);
6452 if(cc==-1&&!likely[i]) {
6453 // Cycle count isn't in a register, temporarily load it then write it out
6454 emit_loadreg(CCREG,HOST_CCREG);
6455 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
6458 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6459 emit_storereg(CCREG,HOST_CCREG);
6462 cc=get_reg(i_regmap,CCREG);
6463 assert(cc==HOST_CCREG);
6464 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
6467 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6473 static void pagespan_assemble(int i,struct regstat *i_regs)
6475 int s1l=get_reg(i_regs->regmap,rs1[i]);
6476 int s1h=get_reg(i_regs->regmap,rs1[i]|64);
6477 int s2l=get_reg(i_regs->regmap,rs2[i]);
6478 int s2h=get_reg(i_regs->regmap,rs2[i]|64);
6479 void *nt_branch=NULL;
6482 int unconditional=0;
6492 if((i_regs->is32>>rs1[i])&(i_regs->is32>>rs2[i])&1) {
6496 int addr,alt,ntaddr;
6497 if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
6501 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
6502 (i_regs->regmap[hr]&63)!=rs1[i] &&
6503 (i_regs->regmap[hr]&63)!=rs2[i] )
6512 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6513 (i_regs->regmap[hr]&63)!=rs1[i] &&
6514 (i_regs->regmap[hr]&63)!=rs2[i] )
6520 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
6524 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6525 (i_regs->regmap[hr]&63)!=rs1[i] &&
6526 (i_regs->regmap[hr]&63)!=rs2[i] )
6533 assert(hr<HOST_REGS);
6534 if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
6535 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
6537 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
6538 if(opcode[i]==2) // J
6542 if(opcode[i]==3) // JAL
6545 int rt=get_reg(i_regs->regmap,31);
6546 emit_movimm(start+i*4+8,rt);
6549 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
6552 if(opcode2[i]==9) // JALR
6554 int rt=get_reg(i_regs->regmap,rt1[i]);
6555 emit_movimm(start+i*4+8,rt);
6558 if((opcode[i]&0x3f)==4) // BEQ
6565 #ifdef HAVE_CMOV_IMM
6567 if(s2l>=0) emit_cmp(s1l,s2l);
6568 else emit_test(s1l,s1l);
6569 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
6575 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6577 if(s2h>=0) emit_cmp(s1h,s2h);
6578 else emit_test(s1h,s1h);
6579 emit_cmovne_reg(alt,addr);
6581 if(s2l>=0) emit_cmp(s1l,s2l);
6582 else emit_test(s1l,s1l);
6583 emit_cmovne_reg(alt,addr);
6586 if((opcode[i]&0x3f)==5) // BNE
6588 #ifdef HAVE_CMOV_IMM
6590 if(s2l>=0) emit_cmp(s1l,s2l);
6591 else emit_test(s1l,s1l);
6592 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
6598 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
6600 if(s2h>=0) emit_cmp(s1h,s2h);
6601 else emit_test(s1h,s1h);
6602 emit_cmovne_reg(alt,addr);
6604 if(s2l>=0) emit_cmp(s1l,s2l);
6605 else emit_test(s1l,s1l);
6606 emit_cmovne_reg(alt,addr);
6609 if((opcode[i]&0x3f)==0x14) // BEQL
6612 if(s2h>=0) emit_cmp(s1h,s2h);
6613 else emit_test(s1h,s1h);
6617 if(s2l>=0) emit_cmp(s1l,s2l);
6618 else emit_test(s1l,s1l);
6619 if(nottaken) set_jump_target(nottaken,(int)out);
6623 if((opcode[i]&0x3f)==0x15) // BNEL
6626 if(s2h>=0) emit_cmp(s1h,s2h);
6627 else emit_test(s1h,s1h);
6631 if(s2l>=0) emit_cmp(s1l,s2l);
6632 else emit_test(s1l,s1l);
6635 if(taken) set_jump_target(taken,(int)out);
6637 if((opcode[i]&0x3f)==6) // BLEZ
6639 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6641 if(s1h>=0) emit_mov(addr,ntaddr);
6642 emit_cmovl_reg(alt,addr);
6645 emit_cmovne_reg(ntaddr,addr);
6646 emit_cmovs_reg(alt,addr);
6649 if((opcode[i]&0x3f)==7) // BGTZ
6651 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
6653 if(s1h>=0) emit_mov(addr,alt);
6654 emit_cmovl_reg(ntaddr,addr);
6657 emit_cmovne_reg(alt,addr);
6658 emit_cmovs_reg(ntaddr,addr);
6661 if((opcode[i]&0x3f)==0x16) // BLEZL
6663 assert((opcode[i]&0x3f)!=0x16);
6665 if((opcode[i]&0x3f)==0x17) // BGTZL
6667 assert((opcode[i]&0x3f)!=0x17);
6669 assert(opcode[i]!=1); // BLTZ/BGEZ
6671 //FIXME: Check CSREG
6672 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
6673 if((source[i]&0x30000)==0) // BC1F
6675 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6676 emit_testimm(s1l,0x800000);
6677 emit_cmovne_reg(alt,addr);
6679 if((source[i]&0x30000)==0x10000) // BC1T
6681 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6682 emit_testimm(s1l,0x800000);
6683 emit_cmovne_reg(alt,addr);
6685 if((source[i]&0x30000)==0x20000) // BC1FL
6687 emit_testimm(s1l,0x800000);
6691 if((source[i]&0x30000)==0x30000) // BC1TL
6693 emit_testimm(s1l,0x800000);
6699 assert(i_regs->regmap[HOST_CCREG]==CCREG);
6700 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6701 if(likely[i]||unconditional)
6703 emit_movimm(ba[i],HOST_BTREG);
6705 else if(addr!=HOST_BTREG)
6707 emit_mov(addr,HOST_BTREG);
6709 void *branch_addr=out;
6711 int target_addr=start+i*4+5;
6713 void *compiled_target_addr=check_addr(target_addr);
6714 emit_extjump_ds((int)branch_addr,target_addr);
6715 if(compiled_target_addr) {
6716 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6717 add_link(target_addr,stub);
6719 else set_jump_target((int)branch_addr,(int)stub);
6722 set_jump_target((int)nottaken,(int)out);
6723 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6724 void *branch_addr=out;
6726 int target_addr=start+i*4+8;
6728 void *compiled_target_addr=check_addr(target_addr);
6729 emit_extjump_ds((int)branch_addr,target_addr);
6730 if(compiled_target_addr) {
6731 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6732 add_link(target_addr,stub);
6734 else set_jump_target((int)branch_addr,(int)stub);
6738 // Assemble the delay slot for the above
6739 static void pagespan_ds()
6741 assem_debug("initial delay slot:\n");
6742 u_int vaddr=start+1;
6743 u_int page=get_page(vaddr);
6744 u_int vpage=get_vpage(vaddr);
6745 ll_add(jump_dirty+vpage,vaddr,(void *)out);
6747 ll_add(jump_in+page,vaddr,(void *)out);
6748 assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6749 if(regs[0].regmap[HOST_CCREG]!=CCREG)
6750 wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty,regs[0].was32);
6751 if(regs[0].regmap[HOST_BTREG]!=BTREG)
6752 emit_writeword(HOST_BTREG,(int)&branch_target);
6753 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,rs1[0],rs2[0]);
6754 address_generation(0,®s[0],regs[0].regmap_entry);
6755 if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39||(opcode[0]&0x3b)==0x3a)
6756 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,INVCP,INVCP);
6761 alu_assemble(0,®s[0]);break;
6763 imm16_assemble(0,®s[0]);break;
6765 shift_assemble(0,®s[0]);break;
6767 shiftimm_assemble(0,®s[0]);break;
6769 load_assemble(0,®s[0]);break;
6771 loadlr_assemble(0,®s[0]);break;
6773 store_assemble(0,®s[0]);break;
6775 storelr_assemble(0,®s[0]);break;
6777 cop0_assemble(0,®s[0]);break;
6779 cop1_assemble(0,®s[0]);break;
6781 c1ls_assemble(0,®s[0]);break;
6783 cop2_assemble(0,®s[0]);break;
6785 c2ls_assemble(0,®s[0]);break;
6787 c2op_assemble(0,®s[0]);break;
6789 fconv_assemble(0,®s[0]);break;
6791 float_assemble(0,®s[0]);break;
6793 fcomp_assemble(0,®s[0]);break;
6795 multdiv_assemble(0,®s[0]);break;
6797 mov_assemble(0,®s[0]);break;
6807 printf("Jump in the delay slot. This is probably a bug.\n");
6809 int btaddr=get_reg(regs[0].regmap,BTREG);
6811 btaddr=get_reg(regs[0].regmap,-1);
6812 emit_readword((int)&branch_target,btaddr);
6814 assert(btaddr!=HOST_CCREG);
6815 if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6817 emit_movimm(start+4,HOST_TEMPREG);
6818 emit_cmp(btaddr,HOST_TEMPREG);
6820 emit_cmpimm(btaddr,start+4);
6822 int branch=(int)out;
6824 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,-1);
6825 emit_jmp(jump_vaddr_reg[btaddr]);
6826 set_jump_target(branch,(int)out);
6827 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6828 load_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6831 // Basic liveness analysis for MIPS registers
6832 void unneeded_registers(int istart,int iend,int r)
6835 uint64_t u,uu,gte_u,b,bu,gte_bu;
6836 uint64_t temp_u,temp_uu,temp_gte_u=0;
6838 uint64_t gte_u_unknown=0;
6839 if(new_dynarec_hacks&NDHACK_GTE_UNNEEDED)
6843 gte_u=gte_u_unknown;
6845 u=unneeded_reg[iend+1];
6846 uu=unneeded_reg_upper[iend+1];
6848 gte_u=gte_unneeded[iend+1];
6851 for (i=iend;i>=istart;i--)
6853 //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
6854 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6856 // If subroutine call, flag return address as a possible branch target
6857 if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
6859 if(ba[i]<start || ba[i]>=(start+slen*4))
6861 // Branch out of this block, flush all regs
6864 gte_u=gte_u_unknown;
6866 if(itype[i]==UJUMP&&rt1[i]==31)
6868 uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
6870 if(itype[i]==RJUMP&&rs1[i]==31)
6872 uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9
6874 if(start>0x80000400&&start<0x80000000+RAM_SIZE) {
6875 if(itype[i]==UJUMP&&rt1[i]==31)
6877 //uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi
6878 uu=u=0x300FF0F; // Discard at, v0-v1, t0-t9
6880 if(itype[i]==RJUMP&&rs1[i]==31)
6882 //uu=u=0x30300FFF3LL; // Discard at, a0-a3, t0-t9, lo, hi
6883 uu=u=0x300FFF3; // Discard at, a0-a3, t0-t9
6886 branch_unneeded_reg[i]=u;
6887 branch_unneeded_reg_upper[i]=uu;
6888 // Merge in delay slot
6889 tdep=(~uu>>rt1[i+1])&1;
6890 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6891 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6892 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6893 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6894 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6897 gte_u&=~gte_rs[i+1];
6898 // If branch is "likely" (and conditional)
6899 // then we skip the delay slot on the fall-thru path
6902 u&=unneeded_reg[i+2];
6903 uu&=unneeded_reg_upper[i+2];
6904 gte_u&=gte_unneeded[i+2];
6910 gte_u=gte_u_unknown;
6916 // Internal branch, flag target
6917 bt[(ba[i]-start)>>2]=1;
6918 if(ba[i]<=start+i*4) {
6920 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6922 // Unconditional branch
6926 // Conditional branch (not taken case)
6927 temp_u=unneeded_reg[i+2];
6928 temp_uu=unneeded_reg_upper[i+2];
6929 temp_gte_u&=gte_unneeded[i+2];
6931 // Merge in delay slot
6932 tdep=(~temp_uu>>rt1[i+1])&1;
6933 temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6934 temp_uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6935 temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6936 temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6937 temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6938 temp_u|=1;temp_uu|=1;
6939 temp_gte_u|=gte_rt[i+1];
6940 temp_gte_u&=~gte_rs[i+1];
6941 // If branch is "likely" (and conditional)
6942 // then we skip the delay slot on the fall-thru path
6945 temp_u&=unneeded_reg[i+2];
6946 temp_uu&=unneeded_reg_upper[i+2];
6947 temp_gte_u&=gte_unneeded[i+2];
6953 temp_gte_u=gte_u_unknown;
6956 tdep=(~temp_uu>>rt1[i])&1;
6957 temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6958 temp_uu|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6959 temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6960 temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
6961 temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i]));
6962 temp_u|=1;temp_uu|=1;
6963 temp_gte_u|=gte_rt[i];
6964 temp_gte_u&=~gte_rs[i];
6965 unneeded_reg[i]=temp_u;
6966 unneeded_reg_upper[i]=temp_uu;
6967 gte_unneeded[i]=temp_gte_u;
6968 // Only go three levels deep. This recursion can take an
6969 // excessive amount of time if there are a lot of nested loops.
6971 unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6973 unneeded_reg[(ba[i]-start)>>2]=1;
6974 unneeded_reg_upper[(ba[i]-start)>>2]=1;
6975 gte_unneeded[(ba[i]-start)>>2]=gte_u_unknown;
6978 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6980 // Unconditional branch
6981 u=unneeded_reg[(ba[i]-start)>>2];
6982 uu=unneeded_reg_upper[(ba[i]-start)>>2];
6983 gte_u=gte_unneeded[(ba[i]-start)>>2];
6984 branch_unneeded_reg[i]=u;
6985 branch_unneeded_reg_upper[i]=uu;
6988 //branch_unneeded_reg[i]=u;
6989 //branch_unneeded_reg_upper[i]=uu;
6990 // Merge in delay slot
6991 tdep=(~uu>>rt1[i+1])&1;
6992 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6993 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6994 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6995 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6996 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6999 gte_u&=~gte_rs[i+1];
7001 // Conditional branch
7002 b=unneeded_reg[(ba[i]-start)>>2];
7003 bu=unneeded_reg_upper[(ba[i]-start)>>2];
7004 gte_bu=gte_unneeded[(ba[i]-start)>>2];
7005 branch_unneeded_reg[i]=b;
7006 branch_unneeded_reg_upper[i]=bu;
7009 //branch_unneeded_reg[i]=b;
7010 //branch_unneeded_reg_upper[i]=bu;
7011 // Branch delay slot
7012 tdep=(~uu>>rt1[i+1])&1;
7013 b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
7014 bu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
7015 b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
7016 bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
7017 bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
7019 gte_bu|=gte_rt[i+1];
7020 gte_bu&=~gte_rs[i+1];
7021 // If branch is "likely" then we skip the
7022 // delay slot on the fall-thru path
7028 u&=unneeded_reg[i+2];
7029 uu&=unneeded_reg_upper[i+2];
7030 gte_u&=gte_unneeded[i+2];
7042 branch_unneeded_reg[i]&=unneeded_reg[i+2];
7043 branch_unneeded_reg_upper[i]&=unneeded_reg_upper[i+2];
7044 //branch_unneeded_reg[i]=1;
7045 //branch_unneeded_reg_upper[i]=1;
7047 branch_unneeded_reg[i]=1;
7048 branch_unneeded_reg_upper[i]=1;
7054 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7056 // SYSCALL instruction (software interrupt)
7060 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7062 // ERET instruction (return from interrupt)
7067 tdep=(~uu>>rt1[i])&1;
7068 // Written registers are unneeded
7074 // Accessed registers are needed
7080 if(gte_rs[i]&&rt1[i]&&(unneeded_reg[i+1]&(1ll<<rt1[i])))
7081 gte_u|=gte_rs[i]>e_unneeded[i+1]; // MFC2/CFC2 to dead register, unneeded
7082 // Source-target dependencies
7083 uu&=~(tdep<<dep1[i]);
7084 uu&=~(tdep<<dep2[i]);
7085 // R0 is always unneeded
7089 unneeded_reg_upper[i]=uu;
7090 gte_unneeded[i]=gte_u;
7092 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
7095 for(r=1;r<=CCREG;r++) {
7096 if((unneeded_reg[i]>>r)&1) {
7097 if(r==HIREG) printf(" HI");
7098 else if(r==LOREG) printf(" LO");
7099 else printf(" r%d",r);
7103 for(r=1;r<=CCREG;r++) {
7104 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
7105 if(r==HIREG) printf(" HI");
7106 else if(r==LOREG) printf(" LO");
7107 else printf(" r%d",r);
7113 for (i=iend;i>=istart;i--)
7115 unneeded_reg_upper[i]=branch_unneeded_reg_upper[i]=-1LL;
7120 // Identify registers which are likely to contain 32-bit values
7121 // This is used to predict whether any branches will jump to a
7122 // location with 64-bit values in registers.
7123 static void provisional_32bit()
7127 uint64_t lastbranch=1;
7132 if(itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) {
7133 if(i>1) is32=lastbranch;
7139 if(itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP) {
7141 if(i>2) is32=lastbranch;
7145 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
7147 if(rs1[i-2]==0||rs2[i-2]==0)
7150 is32|=1LL<<rs1[i-2];
7153 is32|=1LL<<rs2[i-2];
7158 // If something jumps here with 64-bit values
7159 // then promote those registers to 64 bits
7162 uint64_t temp_is32=is32;
7165 if(ba[j]==start+i*4)
7166 //temp_is32&=branch_regs[j].is32;
7171 if(ba[j]==start+i*4)
7182 if(type==UJUMP||type==RJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
7183 // Branches don't write registers, consider the delay slot instead.
7194 if(opcode[i]==0x27||opcode[i]==0x37|| // LWU/LD
7195 opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
7204 if(op==0x1a||op==0x1b) is32&=~(1LL<<rt); // LDR/LDL
7205 if(op==0x22) is32|=1LL<<rt; // LWL
7208 if (op==0x08||op==0x09|| // ADDI/ADDIU
7209 op==0x0a||op==0x0b|| // SLTI/SLTIU
7215 if(op==0x18||op==0x19) { // DADDI/DADDIU
7218 // is32|=((is32>>s1)&1LL)<<rt;
7220 if(op==0x0d||op==0x0e) { // ORI/XORI
7221 uint64_t sr=((is32>>s1)&1LL);
7237 if(op2>=0x20&&op2<=0x23) { // ADD/ADDU/SUB/SUBU
7240 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
7243 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
7244 uint64_t sr=((is32>>s1)&(is32>>s2)&1LL);
7248 else if(op2>=0x2c&&op2<=0x2d) { // DADD/DADDU
7253 uint64_t sr=((is32>>s1)&1LL);
7258 uint64_t sr=((is32>>s2)&1LL);
7266 else if(op2>=0x2e&&op2<=0x2f) { // DSUB/DSUBU
7271 uint64_t sr=((is32>>s1)&1LL);
7281 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
7282 is32&=~((1LL<<HIREG)|(1LL<<LOREG));
7285 is32|=(1LL<<HIREG)|(1LL<<LOREG);
7290 uint64_t sr=((is32>>s1)&1LL);
7296 if(op2>=0x14&&op2<=0x17) is32&=~(1LL<<rt); // DSLLV/DSRLV/DSRAV
7297 else is32|=1LL<<rt; // SLLV/SRLV/SRAV
7301 // DSLL/DSRL/DSRA/DSLL32/DSRL32 but not DSRA32 have 64-bit result
7302 if(op2>=0x38&&op2<0x3f) is32&=~(1LL<<rt);
7305 if(op2==0) is32|=1LL<<rt; // MFC0
7309 if(op2==0) is32|=1LL<<rt; // MFC1
7310 if(op2==1) is32&=~(1LL<<rt); // DMFC1
7311 if(op2==2) is32|=1LL<<rt; // CFC1
7333 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
7335 if(rt1[i-1]==31) // JAL/JALR
7337 // Subroutine call will return here, don't alloc any registers
7342 // Internal branch will jump here, match registers to caller
7350 // Identify registers which may be assumed to contain 32-bit values
7351 // and where optimizations will rely on this.
7352 // This is used to determine whether backward branches can safely
7353 // jump to a location with 64-bit values in registers.
7354 static void provisional_r32()
7359 for (i=slen-1;i>=0;i--)
7362 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7364 if(ba[i]<start || ba[i]>=(start+slen*4))
7366 // Branch out of this block, don't need anything
7372 // Need whatever matches the target
7373 // (and doesn't get overwritten by the delay slot instruction)
7375 int t=(ba[i]-start)>>2;
7376 if(ba[i]>start+i*4) {
7378 //if(!(requires_32bit[t]&~regs[i].was32))
7379 // r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7380 if(!(pr32[t]&~regs[i].was32))
7381 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7384 if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
7385 r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7388 // Conditional branch may need registers for following instructions
7389 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
7392 //r32|=requires_32bit[i+2];
7395 // Mark this address as a branch target since it may be called
7396 // upon return from interrupt
7400 // Merge in delay slot
7402 // These are overwritten unless the branch is "likely"
7403 // and the delay slot is nullified if not taken
7404 r32&=~(1LL<<rt1[i+1]);
7405 r32&=~(1LL<<rt2[i+1]);
7407 // Assume these are needed (delay slot)
7410 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
7414 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
7416 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
7418 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
7420 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
7422 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
7425 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7427 // SYSCALL instruction (software interrupt)
7430 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7432 // ERET instruction (return from interrupt)
7436 r32&=~(1LL<<rt1[i]);
7437 r32&=~(1LL<<rt2[i]);
7440 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
7444 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
7446 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
7448 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
7450 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
7452 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
7454 //requires_32bit[i]=r32;
7457 // Dirty registers which are 32-bit, require 32-bit input
7458 // as they will be written as 32-bit values
7459 for(hr=0;hr<HOST_REGS;hr++)
7461 if(regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64) {
7462 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
7463 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
7464 pr32[i]|=1LL<<regs[i].regmap_entry[hr];
7465 //requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
7472 // Write back dirty registers as soon as we will no longer modify them,
7473 // so that we don't end up with lots of writes at the branches.
7474 void clean_registers(int istart,int iend,int wr)
7478 u_int will_dirty_i,will_dirty_next,temp_will_dirty;
7479 u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
7481 will_dirty_i=will_dirty_next=0;
7482 wont_dirty_i=wont_dirty_next=0;
7484 will_dirty_i=will_dirty_next=will_dirty[iend+1];
7485 wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
7487 for (i=iend;i>=istart;i--)
7489 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7491 if(ba[i]<start || ba[i]>=(start+slen*4))
7493 // Branch out of this block, flush all regs
7494 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7496 // Unconditional branch
7499 // Merge in delay slot (will dirty)
7500 for(r=0;r<HOST_REGS;r++) {
7501 if(r!=EXCLUDE_REG) {
7502 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7503 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7504 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7505 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7506 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7507 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7508 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7509 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7510 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7511 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7512 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7513 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7514 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7515 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7521 // Conditional branch
7523 wont_dirty_i=wont_dirty_next;
7524 // Merge in delay slot (will dirty)
7525 for(r=0;r<HOST_REGS;r++) {
7526 if(r!=EXCLUDE_REG) {
7528 // Might not dirty if likely branch is not taken
7529 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7530 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7531 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7532 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7533 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7534 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
7535 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7536 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7537 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7538 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7539 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7540 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7541 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7542 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7547 // Merge in delay slot (wont dirty)
7548 for(r=0;r<HOST_REGS;r++) {
7549 if(r!=EXCLUDE_REG) {
7550 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7551 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7552 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7553 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7554 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7555 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7556 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7557 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7558 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7559 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7563 #ifndef DESTRUCTIVE_WRITEBACK
7564 branch_regs[i].dirty&=wont_dirty_i;
7566 branch_regs[i].dirty|=will_dirty_i;
7572 if(ba[i]<=start+i*4) {
7574 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7576 // Unconditional branch
7579 // Merge in delay slot (will dirty)
7580 for(r=0;r<HOST_REGS;r++) {
7581 if(r!=EXCLUDE_REG) {
7582 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7583 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7584 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7585 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7586 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7587 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7588 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7589 if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7590 if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7591 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7592 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7593 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7594 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7595 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7599 // Conditional branch (not taken case)
7600 temp_will_dirty=will_dirty_next;
7601 temp_wont_dirty=wont_dirty_next;
7602 // Merge in delay slot (will dirty)
7603 for(r=0;r<HOST_REGS;r++) {
7604 if(r!=EXCLUDE_REG) {
7606 // Will not dirty if likely branch is not taken
7607 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7608 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7609 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7610 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7611 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7612 if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
7613 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7614 //if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7615 //if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7616 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7617 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7618 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7619 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7620 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7625 // Merge in delay slot (wont dirty)
7626 for(r=0;r<HOST_REGS;r++) {
7627 if(r!=EXCLUDE_REG) {
7628 if((regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7629 if((regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7630 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7631 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7632 if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7633 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7634 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7635 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7636 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7637 if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7640 // Deal with changed mappings
7642 for(r=0;r<HOST_REGS;r++) {
7643 if(r!=EXCLUDE_REG) {
7644 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
7645 temp_will_dirty&=~(1<<r);
7646 temp_wont_dirty&=~(1<<r);
7647 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7648 temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7649 temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7651 temp_will_dirty|=1<<r;
7652 temp_wont_dirty|=1<<r;
7659 will_dirty[i]=temp_will_dirty;
7660 wont_dirty[i]=temp_wont_dirty;
7661 clean_registers((ba[i]-start)>>2,i-1,0);
7663 // Limit recursion. It can take an excessive amount
7664 // of time if there are a lot of nested loops.
7665 will_dirty[(ba[i]-start)>>2]=0;
7666 wont_dirty[(ba[i]-start)>>2]=-1;
7671 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7673 // Unconditional branch
7676 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7677 for(r=0;r<HOST_REGS;r++) {
7678 if(r!=EXCLUDE_REG) {
7679 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7680 will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
7681 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7683 if(branch_regs[i].regmap[r]>=0) {
7684 will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7685 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7690 // Merge in delay slot
7691 for(r=0;r<HOST_REGS;r++) {
7692 if(r!=EXCLUDE_REG) {
7693 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7694 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7695 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7696 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7697 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7698 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7699 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7700 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7701 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7702 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7703 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7704 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7705 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7706 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7710 // Conditional branch
7711 will_dirty_i=will_dirty_next;
7712 wont_dirty_i=wont_dirty_next;
7713 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7714 for(r=0;r<HOST_REGS;r++) {
7715 if(r!=EXCLUDE_REG) {
7716 signed char target_reg=branch_regs[i].regmap[r];
7717 if(target_reg==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7718 will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7719 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7721 else if(target_reg>=0) {
7722 will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
7723 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
7725 // Treat delay slot as part of branch too
7726 /*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7727 will_dirty[i+1]&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7728 wont_dirty[i+1]|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7732 will_dirty[i+1]&=~(1<<r);
7737 // Merge in delay slot
7738 for(r=0;r<HOST_REGS;r++) {
7739 if(r!=EXCLUDE_REG) {
7741 // Might not dirty if likely branch is not taken
7742 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7743 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7744 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7745 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7746 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7747 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7748 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7749 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7750 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7751 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7752 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7753 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7754 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7755 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7760 // Merge in delay slot (won't dirty)
7761 for(r=0;r<HOST_REGS;r++) {
7762 if(r!=EXCLUDE_REG) {
7763 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7764 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7765 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7766 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7767 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7768 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7769 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7770 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7771 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7772 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7776 #ifndef DESTRUCTIVE_WRITEBACK
7777 branch_regs[i].dirty&=wont_dirty_i;
7779 branch_regs[i].dirty|=will_dirty_i;
7784 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7786 // SYSCALL instruction (software interrupt)
7790 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7792 // ERET instruction (return from interrupt)
7796 will_dirty_next=will_dirty_i;
7797 wont_dirty_next=wont_dirty_i;
7798 for(r=0;r<HOST_REGS;r++) {
7799 if(r!=EXCLUDE_REG) {
7800 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7801 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7802 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7803 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7804 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7805 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7806 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7807 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7809 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
7811 // Don't store a register immediately after writing it,
7812 // may prevent dual-issue.
7813 if((regs[i].regmap[r]&63)==rt1[i-1]) wont_dirty_i|=1<<r;
7814 if((regs[i].regmap[r]&63)==rt2[i-1]) wont_dirty_i|=1<<r;
7820 will_dirty[i]=will_dirty_i;
7821 wont_dirty[i]=wont_dirty_i;
7822 // Mark registers that won't be dirtied as not dirty
7824 /*printf("wr (%d,%d) %x will:",istart,iend,start+i*4);
7825 for(r=0;r<HOST_REGS;r++) {
7826 if((will_dirty_i>>r)&1) {
7832 //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=FJUMP)) {
7833 regs[i].dirty|=will_dirty_i;
7834 #ifndef DESTRUCTIVE_WRITEBACK
7835 regs[i].dirty&=wont_dirty_i;
7836 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7838 if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
7839 for(r=0;r<HOST_REGS;r++) {
7840 if(r!=EXCLUDE_REG) {
7841 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
7842 regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
7843 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7851 for(r=0;r<HOST_REGS;r++) {
7852 if(r!=EXCLUDE_REG) {
7853 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
7854 regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
7855 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7863 // Deal with changed mappings
7864 temp_will_dirty=will_dirty_i;
7865 temp_wont_dirty=wont_dirty_i;
7866 for(r=0;r<HOST_REGS;r++) {
7867 if(r!=EXCLUDE_REG) {
7869 if(regs[i].regmap[r]==regmap_pre[i][r]) {
7871 #ifndef DESTRUCTIVE_WRITEBACK
7872 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7874 regs[i].wasdirty|=will_dirty_i&(1<<r);
7877 else if(regmap_pre[i][r]>=0&&(nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
7878 // Register moved to a different register
7879 will_dirty_i&=~(1<<r);
7880 wont_dirty_i&=~(1<<r);
7881 will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
7882 wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
7884 #ifndef DESTRUCTIVE_WRITEBACK
7885 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7887 regs[i].wasdirty|=will_dirty_i&(1<<r);
7891 will_dirty_i&=~(1<<r);
7892 wont_dirty_i&=~(1<<r);
7893 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7894 will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7895 wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7898 /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);/*assert(!((will_dirty>>r)&1));*/
7908 void disassemble_inst(int i)
7910 if (bt[i]) printf("*"); else printf(" ");
7913 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7915 printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
7917 printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
7919 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7921 if (opcode[i]==0x9&&rt1[i]!=31)
7922 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i]);
7924 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7927 printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break;
7929 if(opcode[i]==0xf) //LUI
7930 printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],rt1[i],imm[i]&0xffff);
7932 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7936 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7940 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rs2[i],rs1[i],imm[i]);
7944 printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i],rs2[i]);
7947 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rs1[i],rs2[i]);
7950 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7953 if((opcode2[i]&0x1d)==0x10)
7954 printf (" %x: %s r%d\n",start+i*4,insn[i],rt1[i]);
7955 else if((opcode2[i]&0x1d)==0x11)
7956 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7958 printf (" %x: %s\n",start+i*4,insn[i]);
7962 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC0
7963 else if(opcode2[i]==4)
7964 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC0
7965 else printf (" %x: %s\n",start+i*4,insn[i]);
7969 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC1
7970 else if(opcode2[i]>3)
7971 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC1
7972 else printf (" %x: %s\n",start+i*4,insn[i]);
7976 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC2
7977 else if(opcode2[i]>3)
7978 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC2
7979 else printf (" %x: %s\n",start+i*4,insn[i]);
7982 printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7985 printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7988 printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
7991 //printf (" %s %8x\n",insn[i],source[i]);
7992 printf (" %x: %s\n",start+i*4,insn[i]);
7996 static void disassemble_inst(int i) {}
7999 // clear the state completely, instead of just marking
8000 // things invalid like invalidate_all_pages() does
8001 void new_dynarec_clear_full()
8004 out=(u_char *)BASE_ADDR;
8005 memset(invalid_code,1,sizeof(invalid_code));
8006 memset(hash_table,0xff,sizeof(hash_table));
8007 memset(mini_ht,-1,sizeof(mini_ht));
8008 memset(restore_candidate,0,sizeof(restore_candidate));
8009 memset(shadow,0,sizeof(shadow));
8011 expirep=16384; // Expiry pointer, +2 blocks
8012 pending_exception=0;
8015 inv_code_start=inv_code_end=~0;
8019 for(n=0;n<524288;n++) // 0 .. 0x7FFFFFFF
8021 for(n=524288;n<526336;n++) // 0x80000000 .. 0x807FFFFF
8022 memory_map[n]=((u_int)rdram-0x80000000)>>2;
8023 for(n=526336;n<1048576;n++) // 0x80800000 .. 0xFFFFFFFF
8026 for(n=0;n<4096;n++) ll_clear(jump_in+n);
8027 for(n=0;n<4096;n++) ll_clear(jump_out+n);
8028 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
8031 void new_dynarec_init()
8033 printf("Init new dynarec\n");
8034 out=(u_char *)BASE_ADDR;
8036 if (mmap (out, 1<<TARGET_SIZE_2,
8037 PROT_READ | PROT_WRITE | PROT_EXEC,
8038 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
8039 -1, 0) <= 0) {printf("mmap() failed\n");}
8041 // not all systems allow execute in data segment by default
8042 if (mprotect(out, 1<<TARGET_SIZE_2, PROT_READ | PROT_WRITE | PROT_EXEC) != 0)
8043 printf("mprotect() failed\n");
8046 rdword=&readmem_dword;
8047 fake_pc.f.r.rs=&readmem_dword;
8048 fake_pc.f.r.rt=&readmem_dword;
8049 fake_pc.f.r.rd=&readmem_dword;
8052 cycle_multiplier=200;
8053 new_dynarec_clear_full();
8055 // Copy this into local area so we don't have to put it in every literal pool
8056 invc_ptr=invalid_code;
8059 for(n=0;n<0x8000;n++) { // 0 .. 0x7FFFFFFF
8060 writemem[n] = write_nomem_new;
8061 writememb[n] = write_nomemb_new;
8062 writememh[n] = write_nomemh_new;
8064 writememd[n] = write_nomemd_new;
8066 readmem[n] = read_nomem_new;
8067 readmemb[n] = read_nomemb_new;
8068 readmemh[n] = read_nomemh_new;
8070 readmemd[n] = read_nomemd_new;
8073 for(n=0x8000;n<0x8080;n++) { // 0x80000000 .. 0x807FFFFF
8074 writemem[n] = write_rdram_new;
8075 writememb[n] = write_rdramb_new;
8076 writememh[n] = write_rdramh_new;
8078 writememd[n] = write_rdramd_new;
8081 for(n=0xC000;n<0x10000;n++) { // 0xC0000000 .. 0xFFFFFFFF
8082 writemem[n] = write_nomem_new;
8083 writememb[n] = write_nomemb_new;
8084 writememh[n] = write_nomemh_new;
8086 writememd[n] = write_nomemd_new;
8088 readmem[n] = read_nomem_new;
8089 readmemb[n] = read_nomemb_new;
8090 readmemh[n] = read_nomemh_new;
8092 readmemd[n] = read_nomemd_new;
8099 ram_offset=(u_int)rdram-0x80000000;
8102 printf("warning: RAM is not directly mapped, performance will suffer\n");
8105 void new_dynarec_cleanup()
8109 if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0) {printf("munmap() failed\n");}
8111 for(n=0;n<4096;n++) ll_clear(jump_in+n);
8112 for(n=0;n<4096;n++) ll_clear(jump_out+n);
8113 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
8115 if (munmap (ROM_COPY, 67108864) < 0) {printf("munmap() failed\n");}
8119 int new_recompile_block(int addr)
8122 if(addr==0x800cd050) {
8124 for(block=0x80000;block<0x80800;block++) invalidate_block(block);
8126 for(n=0;n<=2048;n++) ll_clear(jump_dirty+n);
8129 //if(Count==365117028) tracedebug=1;
8130 assem_debug("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
8131 //printf("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
8132 //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
8134 //printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
8135 //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
8136 /*if(Count>=312978186) {
8140 start = (u_int)addr&~3;
8141 //assert(((u_int)addr&1)==0);
8142 new_dynarec_did_compile=1;
8144 if (Config.HLE && start == 0x80001000) // hlecall
8146 // XXX: is this enough? Maybe check hleSoftCall?
8147 u_int beginning=(u_int)out;
8148 u_int page=get_page(start);
8149 invalid_code[start>>12]=0;
8150 emit_movimm(start,0);
8151 emit_writeword(0,(int)&pcaddr);
8152 emit_jmp((int)new_dyna_leave);
8155 __clear_cache((void *)beginning,out);
8157 ll_add(jump_in+page,start,(void *)beginning);
8160 else if ((u_int)addr < 0x00200000 ||
8161 (0xa0000000 <= addr && addr < 0xa0200000)) {
8162 // used for BIOS calls mostly?
8163 source = (u_int *)((u_int)rdram+(start&0x1fffff));
8164 pagelimit = (addr&0xa0000000)|0x00200000;
8166 else if (!Config.HLE && (
8167 /* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
8168 (0xbfc00000 <= addr && addr < 0xbfc80000))) {
8170 source = (u_int *)((u_int)psxR+(start&0x7ffff));
8171 pagelimit = (addr&0xfff00000)|0x80000;
8176 if ((int)addr >= 0xa4000000 && (int)addr < 0xa4001000) {
8177 source = (u_int *)((u_int)SP_DMEM+start-0xa4000000);
8178 pagelimit = 0xa4001000;
8182 if ((int)addr >= 0x80000000 && (int)addr < 0x80000000+RAM_SIZE) {
8183 source = (u_int *)((u_int)rdram+start-0x80000000);
8184 pagelimit = 0x80000000+RAM_SIZE;
8187 else if ((signed int)addr >= (signed int)0xC0000000) {
8188 //printf("addr=%x mm=%x\n",(u_int)addr,(memory_map[start>>12]<<2));
8189 //if(tlb_LUT_r[start>>12])
8190 //source = (u_int *)(((int)rdram)+(tlb_LUT_r[start>>12]&0xFFFFF000)+(((int)addr)&0xFFF)-0x80000000);
8191 if((signed int)memory_map[start>>12]>=0) {
8192 source = (u_int *)((u_int)(start+(memory_map[start>>12]<<2)));
8193 pagelimit=(start+4096)&0xFFFFF000;
8194 int map=memory_map[start>>12];
8197 //printf("start: %x next: %x\n",map,memory_map[pagelimit>>12]);
8198 if((map&0xBFFFFFFF)==(memory_map[pagelimit>>12]&0xBFFFFFFF)) pagelimit+=4096;
8200 assem_debug("pagelimit=%x\n",pagelimit);
8201 assem_debug("mapping=%x (%x)\n",memory_map[start>>12],(memory_map[start>>12]<<2)+start);
8204 assem_debug("Compile at unmapped memory address: %x \n", (int)addr);
8205 //assem_debug("start: %x next: %x\n",memory_map[start>>12],memory_map[(start+4096)>>12]);
8206 return -1; // Caller will invoke exception handler
8208 //printf("source= %x\n",(int)source);
8212 printf("Compile at bogus memory address: %x \n", (int)addr);
8216 /* Pass 1: disassemble */
8217 /* Pass 2: register dependencies, branch targets */
8218 /* Pass 3: register allocation */
8219 /* Pass 4: branch dependencies */
8220 /* Pass 5: pre-alloc */
8221 /* Pass 6: optimize clean/dirty state */
8222 /* Pass 7: flag 32-bit registers */
8223 /* Pass 8: assembly */
8224 /* Pass 9: linker */
8225 /* Pass 10: garbage collection / free memory */
8229 unsigned int type,op,op2;
8231 //printf("addr = %x source = %x %x\n", addr,source,source[0]);
8233 /* Pass 1 disassembly */
8235 for(i=0;!done;i++) {
8236 bt[i]=0;likely[i]=0;ooo[i]=0;op2=0;
8237 minimum_free_regs[i]=0;
8238 opcode[i]=op=source[i]>>26;
8241 case 0x00: strcpy(insn[i],"special"); type=NI;
8245 case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
8246 case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
8247 case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
8248 case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
8249 case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
8250 case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
8251 case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
8252 case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
8253 case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
8254 case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
8255 case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
8256 case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
8257 case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
8258 case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
8259 case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
8260 case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
8261 case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
8262 case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
8263 case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
8264 case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
8265 case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
8266 case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
8267 case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
8268 case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
8269 case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
8270 case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
8271 case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
8272 case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
8273 case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
8274 case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
8275 case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
8276 case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
8277 case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
8278 case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
8279 case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
8281 case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
8282 case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
8283 case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
8284 case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
8285 case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
8286 case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
8287 case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
8288 case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
8289 case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
8290 case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
8291 case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
8292 case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
8293 case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
8294 case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
8295 case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
8296 case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
8297 case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
8301 case 0x01: strcpy(insn[i],"regimm"); type=NI;
8302 op2=(source[i]>>16)&0x1f;
8305 case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
8306 case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
8307 case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
8308 case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
8309 case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
8310 case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
8311 case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
8312 case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
8313 case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
8314 case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
8315 case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
8316 case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
8317 case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
8318 case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
8321 case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
8322 case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
8323 case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
8324 case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
8325 case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
8326 case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
8327 case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
8328 case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
8329 case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
8330 case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
8331 case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
8332 case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
8333 case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
8334 case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
8335 case 0x10: strcpy(insn[i],"cop0"); type=NI;
8336 op2=(source[i]>>21)&0x1f;
8339 case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
8340 case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
8341 case 0x10: strcpy(insn[i],"tlb"); type=NI;
8342 switch(source[i]&0x3f)
8344 case 0x01: strcpy(insn[i],"TLBR"); type=COP0; break;
8345 case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break;
8346 case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break;
8347 case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break;
8349 case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
8351 case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
8356 case 0x11: strcpy(insn[i],"cop1"); type=NI;
8357 op2=(source[i]>>21)&0x1f;
8360 case 0x00: strcpy(insn[i],"MFC1"); type=COP1; break;
8361 case 0x01: strcpy(insn[i],"DMFC1"); type=COP1; break;
8362 case 0x02: strcpy(insn[i],"CFC1"); type=COP1; break;
8363 case 0x04: strcpy(insn[i],"MTC1"); type=COP1; break;
8364 case 0x05: strcpy(insn[i],"DMTC1"); type=COP1; break;
8365 case 0x06: strcpy(insn[i],"CTC1"); type=COP1; break;
8366 case 0x08: strcpy(insn[i],"BC1"); type=FJUMP;
8367 switch((source[i]>>16)&0x3)
8369 case 0x00: strcpy(insn[i],"BC1F"); break;
8370 case 0x01: strcpy(insn[i],"BC1T"); break;
8371 case 0x02: strcpy(insn[i],"BC1FL"); break;
8372 case 0x03: strcpy(insn[i],"BC1TL"); break;
8375 case 0x10: strcpy(insn[i],"C1.S"); type=NI;
8376 switch(source[i]&0x3f)
8378 case 0x00: strcpy(insn[i],"ADD.S"); type=FLOAT; break;
8379 case 0x01: strcpy(insn[i],"SUB.S"); type=FLOAT; break;
8380 case 0x02: strcpy(insn[i],"MUL.S"); type=FLOAT; break;
8381 case 0x03: strcpy(insn[i],"DIV.S"); type=FLOAT; break;
8382 case 0x04: strcpy(insn[i],"SQRT.S"); type=FLOAT; break;
8383 case 0x05: strcpy(insn[i],"ABS.S"); type=FLOAT; break;
8384 case 0x06: strcpy(insn[i],"MOV.S"); type=FLOAT; break;
8385 case 0x07: strcpy(insn[i],"NEG.S"); type=FLOAT; break;
8386 case 0x08: strcpy(insn[i],"ROUND.L.S"); type=FCONV; break;
8387 case 0x09: strcpy(insn[i],"TRUNC.L.S"); type=FCONV; break;
8388 case 0x0A: strcpy(insn[i],"CEIL.L.S"); type=FCONV; break;
8389 case 0x0B: strcpy(insn[i],"FLOOR.L.S"); type=FCONV; break;
8390 case 0x0C: strcpy(insn[i],"ROUND.W.S"); type=FCONV; break;
8391 case 0x0D: strcpy(insn[i],"TRUNC.W.S"); type=FCONV; break;
8392 case 0x0E: strcpy(insn[i],"CEIL.W.S"); type=FCONV; break;
8393 case 0x0F: strcpy(insn[i],"FLOOR.W.S"); type=FCONV; break;
8394 case 0x21: strcpy(insn[i],"CVT.D.S"); type=FCONV; break;
8395 case 0x24: strcpy(insn[i],"CVT.W.S"); type=FCONV; break;
8396 case 0x25: strcpy(insn[i],"CVT.L.S"); type=FCONV; break;
8397 case 0x30: strcpy(insn[i],"C.F.S"); type=FCOMP; break;
8398 case 0x31: strcpy(insn[i],"C.UN.S"); type=FCOMP; break;
8399 case 0x32: strcpy(insn[i],"C.EQ.S"); type=FCOMP; break;
8400 case 0x33: strcpy(insn[i],"C.UEQ.S"); type=FCOMP; break;
8401 case 0x34: strcpy(insn[i],"C.OLT.S"); type=FCOMP; break;
8402 case 0x35: strcpy(insn[i],"C.ULT.S"); type=FCOMP; break;
8403 case 0x36: strcpy(insn[i],"C.OLE.S"); type=FCOMP; break;
8404 case 0x37: strcpy(insn[i],"C.ULE.S"); type=FCOMP; break;
8405 case 0x38: strcpy(insn[i],"C.SF.S"); type=FCOMP; break;
8406 case 0x39: strcpy(insn[i],"C.NGLE.S"); type=FCOMP; break;
8407 case 0x3A: strcpy(insn[i],"C.SEQ.S"); type=FCOMP; break;
8408 case 0x3B: strcpy(insn[i],"C.NGL.S"); type=FCOMP; break;
8409 case 0x3C: strcpy(insn[i],"C.LT.S"); type=FCOMP; break;
8410 case 0x3D: strcpy(insn[i],"C.NGE.S"); type=FCOMP; break;
8411 case 0x3E: strcpy(insn[i],"C.LE.S"); type=FCOMP; break;
8412 case 0x3F: strcpy(insn[i],"C.NGT.S"); type=FCOMP; break;
8415 case 0x11: strcpy(insn[i],"C1.D"); type=NI;
8416 switch(source[i]&0x3f)
8418 case 0x00: strcpy(insn[i],"ADD.D"); type=FLOAT; break;
8419 case 0x01: strcpy(insn[i],"SUB.D"); type=FLOAT; break;
8420 case 0x02: strcpy(insn[i],"MUL.D"); type=FLOAT; break;
8421 case 0x03: strcpy(insn[i],"DIV.D"); type=FLOAT; break;
8422 case 0x04: strcpy(insn[i],"SQRT.D"); type=FLOAT; break;
8423 case 0x05: strcpy(insn[i],"ABS.D"); type=FLOAT; break;
8424 case 0x06: strcpy(insn[i],"MOV.D"); type=FLOAT; break;
8425 case 0x07: strcpy(insn[i],"NEG.D"); type=FLOAT; break;
8426 case 0x08: strcpy(insn[i],"ROUND.L.D"); type=FCONV; break;
8427 case 0x09: strcpy(insn[i],"TRUNC.L.D"); type=FCONV; break;
8428 case 0x0A: strcpy(insn[i],"CEIL.L.D"); type=FCONV; break;
8429 case 0x0B: strcpy(insn[i],"FLOOR.L.D"); type=FCONV; break;
8430 case 0x0C: strcpy(insn[i],"ROUND.W.D"); type=FCONV; break;
8431 case 0x0D: strcpy(insn[i],"TRUNC.W.D"); type=FCONV; break;
8432 case 0x0E: strcpy(insn[i],"CEIL.W.D"); type=FCONV; break;
8433 case 0x0F: strcpy(insn[i],"FLOOR.W.D"); type=FCONV; break;
8434 case 0x20: strcpy(insn[i],"CVT.S.D"); type=FCONV; break;
8435 case 0x24: strcpy(insn[i],"CVT.W.D"); type=FCONV; break;
8436 case 0x25: strcpy(insn[i],"CVT.L.D"); type=FCONV; break;
8437 case 0x30: strcpy(insn[i],"C.F.D"); type=FCOMP; break;
8438 case 0x31: strcpy(insn[i],"C.UN.D"); type=FCOMP; break;
8439 case 0x32: strcpy(insn[i],"C.EQ.D"); type=FCOMP; break;
8440 case 0x33: strcpy(insn[i],"C.UEQ.D"); type=FCOMP; break;
8441 case 0x34: strcpy(insn[i],"C.OLT.D"); type=FCOMP; break;
8442 case 0x35: strcpy(insn[i],"C.ULT.D"); type=FCOMP; break;
8443 case 0x36: strcpy(insn[i],"C.OLE.D"); type=FCOMP; break;
8444 case 0x37: strcpy(insn[i],"C.ULE.D"); type=FCOMP; break;
8445 case 0x38: strcpy(insn[i],"C.SF.D"); type=FCOMP; break;
8446 case 0x39: strcpy(insn[i],"C.NGLE.D"); type=FCOMP; break;
8447 case 0x3A: strcpy(insn[i],"C.SEQ.D"); type=FCOMP; break;
8448 case 0x3B: strcpy(insn[i],"C.NGL.D"); type=FCOMP; break;
8449 case 0x3C: strcpy(insn[i],"C.LT.D"); type=FCOMP; break;
8450 case 0x3D: strcpy(insn[i],"C.NGE.D"); type=FCOMP; break;
8451 case 0x3E: strcpy(insn[i],"C.LE.D"); type=FCOMP; break;
8452 case 0x3F: strcpy(insn[i],"C.NGT.D"); type=FCOMP; break;
8455 case 0x14: strcpy(insn[i],"C1.W"); type=NI;
8456 switch(source[i]&0x3f)
8458 case 0x20: strcpy(insn[i],"CVT.S.W"); type=FCONV; break;
8459 case 0x21: strcpy(insn[i],"CVT.D.W"); type=FCONV; break;
8462 case 0x15: strcpy(insn[i],"C1.L"); type=NI;
8463 switch(source[i]&0x3f)
8465 case 0x20: strcpy(insn[i],"CVT.S.L"); type=FCONV; break;
8466 case 0x21: strcpy(insn[i],"CVT.D.L"); type=FCONV; break;
8472 case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
8473 case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
8474 case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
8475 case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
8476 case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
8477 case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
8478 case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
8479 case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
8481 case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
8482 case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
8483 case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
8484 case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
8485 case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
8486 case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
8487 case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
8489 case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
8491 case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
8492 case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
8493 case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
8494 case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
8496 case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
8497 case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
8499 case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
8500 case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
8501 case 0x30: strcpy(insn[i],"LL"); type=NI; break;
8502 case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
8504 case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
8505 case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
8506 case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
8508 case 0x38: strcpy(insn[i],"SC"); type=NI; break;
8509 case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
8511 case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
8512 case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
8513 case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
8516 case 0x12: strcpy(insn[i],"COP2"); type=NI;
8517 op2=(source[i]>>21)&0x1f;
8519 if (source[i]&0x3f) { // use this hack to support old savestates with patched gte insns
8520 if (gte_handlers[source[i]&0x3f]!=NULL) {
8521 if (gte_regnames[source[i]&0x3f]!=NULL)
8522 strcpy(insn[i],gte_regnames[source[i]&0x3f]);
8524 snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
8530 case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
8531 case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
8532 case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
8533 case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
8536 case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
8537 case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
8538 case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
8540 default: strcpy(insn[i],"???"); type=NI;
8541 printf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
8546 /* Get registers/immediates */
8552 gte_rs[i]=gte_rt[i]=0;
8555 rs1[i]=(source[i]>>21)&0x1f;
8557 rt1[i]=(source[i]>>16)&0x1f;
8559 imm[i]=(short)source[i];
8563 rs1[i]=(source[i]>>21)&0x1f;
8564 rs2[i]=(source[i]>>16)&0x1f;
8567 imm[i]=(short)source[i];
8568 if(op==0x2c||op==0x2d||op==0x3f) us1[i]=rs2[i]; // 64-bit SDL/SDR/SD
8571 // LWL/LWR only load part of the register,
8572 // therefore the target register must be treated as a source too
8573 rs1[i]=(source[i]>>21)&0x1f;
8574 rs2[i]=(source[i]>>16)&0x1f;
8575 rt1[i]=(source[i]>>16)&0x1f;
8577 imm[i]=(short)source[i];
8578 if(op==0x1a||op==0x1b) us1[i]=rs2[i]; // LDR/LDL
8579 if(op==0x26) dep1[i]=rt1[i]; // LWR
8582 if (op==0x0f) rs1[i]=0; // LUI instruction has no source register
8583 else rs1[i]=(source[i]>>21)&0x1f;
8585 rt1[i]=(source[i]>>16)&0x1f;
8587 if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
8588 imm[i]=(unsigned short)source[i];
8590 imm[i]=(short)source[i];
8592 if(op==0x18||op==0x19) us1[i]=rs1[i]; // DADDI/DADDIU
8593 if(op==0x0a||op==0x0b) us1[i]=rs1[i]; // SLTI/SLTIU
8594 if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI
8601 // The JAL instruction writes to r31.
8608 rs1[i]=(source[i]>>21)&0x1f;
8612 // The JALR instruction writes to rd.
8614 rt1[i]=(source[i]>>11)&0x1f;
8619 rs1[i]=(source[i]>>21)&0x1f;
8620 rs2[i]=(source[i]>>16)&0x1f;
8623 if(op&2) { // BGTZ/BLEZ
8631 rs1[i]=(source[i]>>21)&0x1f;
8636 if(op2&0x10) { // BxxAL
8638 // NOTE: If the branch is not taken, r31 is still overwritten
8640 likely[i]=(op2&2)>>1;
8647 likely[i]=((source[i])>>17)&1;
8650 rs1[i]=(source[i]>>21)&0x1f; // source
8651 rs2[i]=(source[i]>>16)&0x1f; // subtract amount
8652 rt1[i]=(source[i]>>11)&0x1f; // destination
8654 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
8655 us1[i]=rs1[i];us2[i]=rs2[i];
8657 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
8658 dep1[i]=rs1[i];dep2[i]=rs2[i];
8660 else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB
8661 dep1[i]=rs1[i];dep2[i]=rs2[i];
8665 rs1[i]=(source[i]>>21)&0x1f; // source
8666 rs2[i]=(source[i]>>16)&0x1f; // divisor
8669 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
8670 us1[i]=rs1[i];us2[i]=rs2[i];
8678 if(op2==0x10) rs1[i]=HIREG; // MFHI
8679 if(op2==0x11) rt1[i]=HIREG; // MTHI
8680 if(op2==0x12) rs1[i]=LOREG; // MFLO
8681 if(op2==0x13) rt1[i]=LOREG; // MTLO
8682 if((op2&0x1d)==0x10) rt1[i]=(source[i]>>11)&0x1f; // MFxx
8683 if((op2&0x1d)==0x11) rs1[i]=(source[i]>>21)&0x1f; // MTxx
8687 rs1[i]=(source[i]>>16)&0x1f; // target of shift
8688 rs2[i]=(source[i]>>21)&0x1f; // shift amount
8689 rt1[i]=(source[i]>>11)&0x1f; // destination
8691 // DSLLV/DSRLV/DSRAV are 64-bit
8692 if(op2>=0x14&&op2<=0x17) us1[i]=rs1[i];
8695 rs1[i]=(source[i]>>16)&0x1f;
8697 rt1[i]=(source[i]>>11)&0x1f;
8699 imm[i]=(source[i]>>6)&0x1f;
8700 // DSxx32 instructions
8701 if(op2>=0x3c) imm[i]|=0x20;
8702 // DSLL/DSRL/DSRA/DSRA32/DSRL32 but not DSLL32 require 64-bit source
8703 if(op2>=0x38&&op2!=0x3c) us1[i]=rs1[i];
8710 if(op2==0) rt1[i]=(source[i]>>16)&0x1F; // MFC0
8711 if(op2==4) rs1[i]=(source[i]>>16)&0x1F; // MTC0
8712 if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status
8713 if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET
8720 if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
8721 if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
8722 if(op2==5) us1[i]=rs1[i]; // DMTC1
8730 if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC2/CFC2
8731 if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC2/CTC2
8733 int gr=(source[i]>>11)&0x1F;
8736 case 0x00: gte_rs[i]=1ll<<gr; break; // MFC2
8737 case 0x04: gte_rt[i]=1ll<<gr; break; // MTC2
8738 case 0x02: gte_rs[i]=1ll<<(gr+32); break; // CFC2
8739 case 0x06: gte_rt[i]=1ll<<(gr+32); break; // CTC2
8743 rs1[i]=(source[i]>>21)&0x1F;
8747 imm[i]=(short)source[i];
8750 rs1[i]=(source[i]>>21)&0x1F;
8754 imm[i]=(short)source[i];
8755 if(op==0x32) gte_rt[i]=1ll<<((source[i]>>16)&0x1F); // LWC2
8756 else gte_rs[i]=1ll<<((source[i]>>16)&0x1F); // SWC2
8763 gte_rs[i]=gte_reg_reads[source[i]&0x3f];
8764 gte_rt[i]=gte_reg_writes[source[i]&0x3f];
8765 gte_rt[i]|=1ll<<63; // every op changes flags
8766 if((source[i]&0x3f)==GTE_MVMVA) {
8767 int v = (source[i] >> 15) & 3;
8768 gte_rs[i]&=~0xe3fll;
8769 if(v==3) gte_rs[i]|=0xe00ll;
8770 else gte_rs[i]|=3ll<<(v*2);
8800 /* Calculate branch target addresses */
8802 ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
8803 else if(type==CJUMP&&rs1[i]==rs2[i]&&(op&1))
8804 ba[i]=start+i*4+8; // Ignore never taken branch
8805 else if(type==SJUMP&&rs1[i]==0&&!(op2&1))
8806 ba[i]=start+i*4+8; // Ignore never taken branch
8807 else if(type==CJUMP||type==SJUMP||type==FJUMP)
8808 ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
8811 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
8813 // branch in delay slot?
8814 if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
8815 // don't handle first branch and call interpreter if it's hit
8816 printf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr);
8819 // basic load delay detection
8820 else if((type==LOAD||type==LOADLR||type==COP0||type==COP2||type==C2LS)&&rt1[i]!=0) {
8821 int t=(ba[i-1]-start)/4;
8822 if(0 <= t && t < i &&(rt1[i]==rs1[t]||rt1[i]==rs2[t])&&itype[t]!=CJUMP&&itype[t]!=SJUMP) {
8823 // jump target wants DS result - potential load delay effect
8824 printf("load delay @%08x (%08x)\n", addr + i*4, addr);
8826 bt[t+1]=1; // expected return from interpreter
8828 else if(i>=2&&rt1[i-2]==2&&rt1[i]==2&&rs1[i]!=2&&rs2[i]!=2&&rs1[i-1]!=2&&rs2[i-1]!=2&&
8829 !(i>=3&&(itype[i-3]==RJUMP||itype[i-3]==UJUMP||itype[i-3]==CJUMP||itype[i-3]==SJUMP))) {
8830 // v0 overwrite like this is a sign of trouble, bail out
8831 printf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr);
8837 rs2[i-1]=rt1[i-1]=rt2[i-1]=0;
8841 i--; // don't compile the DS
8845 /* Is this the end of the block? */
8846 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
8847 if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
8851 if(stop_after_jal) done=1;
8853 if((source[i+1]&0xfc00003f)==0x0d) done=1;
8855 // Don't recompile stuff that's already compiled
8856 if(check_addr(start+i*4+4)) done=1;
8857 // Don't get too close to the limit
8858 if(i>MAXBLOCK/2) done=1;
8860 if(itype[i]==SYSCALL&&stop_after_jal) done=1;
8861 if(itype[i]==HLECALL||itype[i]==INTCALL) done=2;
8863 // Does the block continue due to a branch?
8866 if(ba[j]==start+i*4) done=j=0; // Branch into delay slot
8867 if(ba[j]==start+i*4+4) done=j=0;
8868 if(ba[j]==start+i*4+8) done=j=0;
8871 //assert(i<MAXBLOCK-1);
8872 if(start+i*4==pagelimit-4) done=1;
8873 assert(start+i*4<pagelimit);
8874 if (i==MAXBLOCK-1) done=1;
8875 // Stop if we're compiling junk
8876 if(itype[i]==NI&&opcode[i]==0x11) {
8877 done=stop_after_jal=1;
8878 printf("Disabled speculative precompilation\n");
8882 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP||itype[i-1]==FJUMP) {
8883 if(start+i*4==pagelimit) {
8889 /* Pass 2 - Register dependencies and branch targets */
8891 unneeded_registers(0,slen-1,0);
8893 /* Pass 3 - Register allocation */
8895 struct regstat current; // Current register allocations/status
8898 current.u=unneeded_reg[0];
8899 current.uu=unneeded_reg_upper[0];
8900 clear_all_regs(current.regmap);
8901 alloc_reg(¤t,0,CCREG);
8902 dirty_reg(¤t,CCREG);
8905 current.waswritten=0;
8911 provisional_32bit();
8914 // First instruction is delay slot
8919 unneeded_reg_upper[0]=1;
8920 current.regmap[HOST_BTREG]=BTREG;
8928 for(hr=0;hr<HOST_REGS;hr++)
8930 // Is this really necessary?
8931 if(current.regmap[hr]==0) current.regmap[hr]=-1;
8934 current.waswritten=0;
8938 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
8940 if(rs1[i-2]==0||rs2[i-2]==0)
8943 current.is32|=1LL<<rs1[i-2];
8944 int hr=get_reg(current.regmap,rs1[i-2]|64);
8945 if(hr>=0) current.regmap[hr]=-1;
8948 current.is32|=1LL<<rs2[i-2];
8949 int hr=get_reg(current.regmap,rs2[i-2]|64);
8950 if(hr>=0) current.regmap[hr]=-1;
8956 // If something jumps here with 64-bit values
8957 // then promote those registers to 64 bits
8960 uint64_t temp_is32=current.is32;
8963 if(ba[j]==start+i*4)
8964 temp_is32&=branch_regs[j].is32;
8968 if(ba[j]==start+i*4)
8972 if(temp_is32!=current.is32) {
8973 //printf("dumping 32-bit regs (%x)\n",start+i*4);
8974 #ifndef DESTRUCTIVE_WRITEBACK
8977 for(hr=0;hr<HOST_REGS;hr++)
8979 int r=current.regmap[hr];
8982 if((current.dirty>>hr)&((current.is32&~temp_is32)>>r)&1) {
8984 //printf("restore %d\n",r);
8988 current.is32=temp_is32;
8995 memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
8996 regs[i].wasconst=current.isconst;
8997 regs[i].was32=current.is32;
8998 regs[i].wasdirty=current.dirty;
8999 regs[i].loadedconst=0;
9000 #if defined(DESTRUCTIVE_WRITEBACK) && !defined(FORCE32)
9001 // To change a dirty register from 32 to 64 bits, we must write
9002 // it out during the previous cycle (for branches, 2 cycles)
9003 if(i<slen-1&&bt[i+1]&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP)
9005 uint64_t temp_is32=current.is32;
9008 if(ba[j]==start+i*4+4)
9009 temp_is32&=branch_regs[j].is32;
9013 if(ba[j]==start+i*4+4)
9017 if(temp_is32!=current.is32) {
9018 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
9019 for(hr=0;hr<HOST_REGS;hr++)
9021 int r=current.regmap[hr];
9024 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
9025 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP)
9027 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63))
9029 //printf("dump %d/r%d\n",hr,r);
9030 current.regmap[hr]=-1;
9031 if(get_reg(current.regmap,r|64)>=0)
9032 current.regmap[get_reg(current.regmap,r|64)]=-1;
9040 else if(i<slen-2&&bt[i+2]&&(source[i-1]>>16)!=0x1000&&(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP))
9042 uint64_t temp_is32=current.is32;
9045 if(ba[j]==start+i*4+8)
9046 temp_is32&=branch_regs[j].is32;
9050 if(ba[j]==start+i*4+8)
9054 if(temp_is32!=current.is32) {
9055 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
9056 for(hr=0;hr<HOST_REGS;hr++)
9058 int r=current.regmap[hr];
9061 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
9062 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63)&&rs1[i+1]!=(r&63)&&rs2[i+1]!=(r&63))
9064 //printf("dump %d/r%d\n",hr,r);
9065 current.regmap[hr]=-1;
9066 if(get_reg(current.regmap,r|64)>=0)
9067 current.regmap[get_reg(current.regmap,r|64)]=-1;
9075 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
9077 current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9078 current.uu=unneeded_reg_upper[i+1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9079 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9088 current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
9089 current.uu=branch_unneeded_reg_upper[i]&~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
9090 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
9091 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
9092 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9095 } else { printf("oops, branch at end of block with no delay slot\n");exit(1); }
9099 ds=0; // Skip delay slot, already allocated as part of branch
9100 // ...but we need to alloc it in case something jumps here
9102 current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
9103 current.uu=branch_unneeded_reg_upper[i-1]&unneeded_reg_upper[i+1];
9105 current.u=branch_unneeded_reg[i-1];
9106 current.uu=branch_unneeded_reg_upper[i-1];
9108 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
9109 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9110 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9113 struct regstat temp;
9114 memcpy(&temp,¤t,sizeof(current));
9115 temp.wasdirty=temp.dirty;
9116 temp.was32=temp.is32;
9117 // TODO: Take into account unconditional branches, as below
9118 delayslot_alloc(&temp,i);
9119 memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
9120 regs[i].wasdirty=temp.wasdirty;
9121 regs[i].was32=temp.was32;
9122 regs[i].dirty=temp.dirty;
9123 regs[i].is32=temp.is32;
9127 // Create entry (branch target) regmap
9128 for(hr=0;hr<HOST_REGS;hr++)
9130 int r=temp.regmap[hr];
9132 if(r!=regmap_pre[i][hr]) {
9133 regs[i].regmap_entry[hr]=-1;
9138 if((current.u>>r)&1) {
9139 regs[i].regmap_entry[hr]=-1;
9140 regs[i].regmap[hr]=-1;
9141 //Don't clear regs in the delay slot as the branch might need them
9142 //current.regmap[hr]=-1;
9144 regs[i].regmap_entry[hr]=r;
9147 if((current.uu>>(r&63))&1) {
9148 regs[i].regmap_entry[hr]=-1;
9149 regs[i].regmap[hr]=-1;
9150 //Don't clear regs in the delay slot as the branch might need them
9151 //current.regmap[hr]=-1;
9153 regs[i].regmap_entry[hr]=r;
9157 // First instruction expects CCREG to be allocated
9158 if(i==0&&hr==HOST_CCREG)
9159 regs[i].regmap_entry[hr]=CCREG;
9161 regs[i].regmap_entry[hr]=-1;
9165 else { // Not delay slot
9168 //current.isconst=0; // DEBUG
9169 //current.wasconst=0; // DEBUG
9170 //regs[i].wasconst=0; // DEBUG
9171 clear_const(¤t,rt1[i]);
9172 alloc_cc(¤t,i);
9173 dirty_reg(¤t,CCREG);
9175 alloc_reg(¤t,i,31);
9176 dirty_reg(¤t,31);
9177 //assert(rs1[i+1]!=31&&rs2[i+1]!=31);
9178 //assert(rt1[i+1]!=rt1[i]);
9180 alloc_reg(¤t,i,PTEMP);
9182 //current.is32|=1LL<<rt1[i];
9185 delayslot_alloc(¤t,i+1);
9186 //current.isconst=0; // DEBUG
9188 //printf("i=%d, isconst=%x\n",i,current.isconst);
9191 //current.isconst=0;
9192 //current.wasconst=0;
9193 //regs[i].wasconst=0;
9194 clear_const(¤t,rs1[i]);
9195 clear_const(¤t,rt1[i]);
9196 alloc_cc(¤t,i);
9197 dirty_reg(¤t,CCREG);
9198 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
9199 alloc_reg(¤t,i,rs1[i]);
9201 alloc_reg(¤t,i,rt1[i]);
9202 dirty_reg(¤t,rt1[i]);
9203 assert(rs1[i+1]!=rt1[i]&&rs2[i+1]!=rt1[i]);
9204 assert(rt1[i+1]!=rt1[i]);
9206 alloc_reg(¤t,i,PTEMP);
9210 if(rs1[i]==31) { // JALR
9211 alloc_reg(¤t,i,RHASH);
9212 #ifndef HOST_IMM_ADDR32
9213 alloc_reg(¤t,i,RHTBL);
9217 delayslot_alloc(¤t,i+1);
9219 // The delay slot overwrites our source register,
9220 // allocate a temporary register to hold the old value.
9224 delayslot_alloc(¤t,i+1);
9226 alloc_reg(¤t,i,RTEMP);
9228 //current.isconst=0; // DEBUG
9233 //current.isconst=0;
9234 //current.wasconst=0;
9235 //regs[i].wasconst=0;
9236 clear_const(¤t,rs1[i]);
9237 clear_const(¤t,rs2[i]);
9238 if((opcode[i]&0x3E)==4) // BEQ/BNE
9240 alloc_cc(¤t,i);
9241 dirty_reg(¤t,CCREG);
9242 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
9243 if(rs2[i]) alloc_reg(¤t,i,rs2[i]);
9244 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9246 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
9247 if(rs2[i]) alloc_reg64(¤t,i,rs2[i]);
9249 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
9250 (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) {
9251 // The delay slot overwrites one of our conditions.
9252 // Allocate the branch condition registers instead.
9256 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
9257 if(rs2[i]) alloc_reg(¤t,i,rs2[i]);
9258 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9260 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
9261 if(rs2[i]) alloc_reg64(¤t,i,rs2[i]);
9267 delayslot_alloc(¤t,i+1);
9271 if((opcode[i]&0x3E)==6) // BLEZ/BGTZ
9273 alloc_cc(¤t,i);
9274 dirty_reg(¤t,CCREG);
9275 alloc_reg(¤t,i,rs1[i]);
9276 if(!(current.is32>>rs1[i]&1))
9278 alloc_reg64(¤t,i,rs1[i]);
9280 if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
9281 // The delay slot overwrites one of our conditions.
9282 // Allocate the branch condition registers instead.
9286 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
9287 if(!((current.is32>>rs1[i])&1))
9289 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
9295 delayslot_alloc(¤t,i+1);
9299 // Don't alloc the delay slot yet because we might not execute it
9300 if((opcode[i]&0x3E)==0x14) // BEQL/BNEL
9305 alloc_cc(¤t,i);
9306 dirty_reg(¤t,CCREG);
9307 alloc_reg(¤t,i,rs1[i]);
9308 alloc_reg(¤t,i,rs2[i]);
9309 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9311 alloc_reg64(¤t,i,rs1[i]);
9312 alloc_reg64(¤t,i,rs2[i]);
9316 if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL
9321 alloc_cc(¤t,i);
9322 dirty_reg(¤t,CCREG);
9323 alloc_reg(¤t,i,rs1[i]);
9324 if(!(current.is32>>rs1[i]&1))
9326 alloc_reg64(¤t,i,rs1[i]);
9330 //current.isconst=0;
9333 //current.isconst=0;
9334 //current.wasconst=0;
9335 //regs[i].wasconst=0;
9336 clear_const(¤t,rs1[i]);
9337 clear_const(¤t,rt1[i]);
9338 //if((opcode2[i]&0x1E)==0x0) // BLTZ/BGEZ
9339 if((opcode2[i]&0x0E)==0x0) // BLTZ/BGEZ
9341 alloc_cc(¤t,i);
9342 dirty_reg(¤t,CCREG);
9343 alloc_reg(¤t,i,rs1[i]);
9344 if(!(current.is32>>rs1[i]&1))
9346 alloc_reg64(¤t,i,rs1[i]);
9348 if (rt1[i]==31) { // BLTZAL/BGEZAL
9349 alloc_reg(¤t,i,31);
9350 dirty_reg(¤t,31);
9351 //#ifdef REG_PREFETCH
9352 //alloc_reg(¤t,i,PTEMP);
9354 //current.is32|=1LL<<rt1[i];
9356 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) // The delay slot overwrites the branch condition.
9357 ||(rt1[i]==31&&(rs1[i+1]==31||rs2[i+1]==31||rt1[i+1]==31||rt2[i+1]==31))) { // DS touches $ra
9358 // Allocate the branch condition registers instead.
9362 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
9363 if(!((current.is32>>rs1[i])&1))
9365 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
9371 delayslot_alloc(¤t,i+1);
9375 // Don't alloc the delay slot yet because we might not execute it
9376 if((opcode2[i]&0x1E)==0x2) // BLTZL/BGEZL
9381 alloc_cc(¤t,i);
9382 dirty_reg(¤t,CCREG);
9383 alloc_reg(¤t,i,rs1[i]);
9384 if(!(current.is32>>rs1[i]&1))
9386 alloc_reg64(¤t,i,rs1[i]);
9390 //current.isconst=0;
9396 if(likely[i]==0) // BC1F/BC1T
9398 // TODO: Theoretically we can run out of registers here on x86.
9399 // The delay slot can allocate up to six, and we need to check
9400 // CSREG before executing the delay slot. Possibly we can drop
9401 // the cycle count and then reload it after checking that the
9402 // FPU is in a usable state, or don't do out-of-order execution.
9403 alloc_cc(¤t,i);
9404 dirty_reg(¤t,CCREG);
9405 alloc_reg(¤t,i,FSREG);
9406 alloc_reg(¤t,i,CSREG);
9407 if(itype[i+1]==FCOMP) {
9408 // The delay slot overwrites the branch condition.
9409 // Allocate the branch condition registers instead.
9410 alloc_cc(¤t,i);
9411 dirty_reg(¤t,CCREG);
9412 alloc_reg(¤t,i,CSREG);
9413 alloc_reg(¤t,i,FSREG);
9417 delayslot_alloc(¤t,i+1);
9418 alloc_reg(¤t,i+1,CSREG);
9422 // Don't alloc the delay slot yet because we might not execute it
9423 if(likely[i]) // BC1FL/BC1TL
9425 alloc_cc(¤t,i);
9426 dirty_reg(¤t,CCREG);
9427 alloc_reg(¤t,i,CSREG);
9428 alloc_reg(¤t,i,FSREG);
9434 imm16_alloc(¤t,i);
9438 load_alloc(¤t,i);
9442 store_alloc(¤t,i);
9445 alu_alloc(¤t,i);
9448 shift_alloc(¤t,i);
9451 multdiv_alloc(¤t,i);
9454 shiftimm_alloc(¤t,i);
9457 mov_alloc(¤t,i);
9460 cop0_alloc(¤t,i);
9464 cop1_alloc(¤t,i);
9467 c1ls_alloc(¤t,i);
9470 c2ls_alloc(¤t,i);
9473 c2op_alloc(¤t,i);
9476 fconv_alloc(¤t,i);
9479 float_alloc(¤t,i);
9482 fcomp_alloc(¤t,i);
9487 syscall_alloc(¤t,i);
9490 pagespan_alloc(¤t,i);
9494 // Drop the upper half of registers that have become 32-bit
9495 current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i]));
9496 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
9497 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9498 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9501 current.uu|=current.is32&((1LL<<rt1[i+1])|(1LL<<rt2[i+1]));
9502 current.uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
9503 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
9504 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9508 // Create entry (branch target) regmap
9509 for(hr=0;hr<HOST_REGS;hr++)
9512 r=current.regmap[hr];
9514 if(r!=regmap_pre[i][hr]) {
9515 // TODO: delay slot (?)
9516 or=get_reg(regmap_pre[i],r); // Get old mapping for this register
9517 if(or<0||(r&63)>=TEMPREG){
9518 regs[i].regmap_entry[hr]=-1;
9522 // Just move it to a different register
9523 regs[i].regmap_entry[hr]=r;
9524 // If it was dirty before, it's still dirty
9525 if((regs[i].wasdirty>>or)&1) dirty_reg(¤t,r&63);
9532 regs[i].regmap_entry[hr]=0;
9536 if((current.u>>r)&1) {
9537 regs[i].regmap_entry[hr]=-1;
9538 //regs[i].regmap[hr]=-1;
9539 current.regmap[hr]=-1;
9541 regs[i].regmap_entry[hr]=r;
9544 if((current.uu>>(r&63))&1) {
9545 regs[i].regmap_entry[hr]=-1;
9546 //regs[i].regmap[hr]=-1;
9547 current.regmap[hr]=-1;
9549 regs[i].regmap_entry[hr]=r;
9553 // Branches expect CCREG to be allocated at the target
9554 if(regmap_pre[i][hr]==CCREG)
9555 regs[i].regmap_entry[hr]=CCREG;
9557 regs[i].regmap_entry[hr]=-1;
9560 memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
9563 if(i>0&&(itype[i-1]==STORE||itype[i-1]==STORELR||(itype[i-1]==C2LS&&opcode[i-1]==0x3a))&&(u_int)imm[i-1]<0x800)
9564 current.waswritten|=1<<rs1[i-1];
9565 current.waswritten&=~(1<<rt1[i]);
9566 current.waswritten&=~(1<<rt2[i]);
9567 if((itype[i]==STORE||itype[i]==STORELR||(itype[i]==C2LS&&opcode[i]==0x3a))&&(u_int)imm[i]>=0x800)
9568 current.waswritten&=~(1<<rs1[i]);
9570 /* Branch post-alloc */
9573 current.was32=current.is32;
9574 current.wasdirty=current.dirty;
9575 switch(itype[i-1]) {
9577 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9578 branch_regs[i-1].isconst=0;
9579 branch_regs[i-1].wasconst=0;
9580 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9581 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9582 alloc_cc(&branch_regs[i-1],i-1);
9583 dirty_reg(&branch_regs[i-1],CCREG);
9584 if(rt1[i-1]==31) { // JAL
9585 alloc_reg(&branch_regs[i-1],i-1,31);
9586 dirty_reg(&branch_regs[i-1],31);
9587 branch_regs[i-1].is32|=1LL<<31;
9589 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9590 memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
9593 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9594 branch_regs[i-1].isconst=0;
9595 branch_regs[i-1].wasconst=0;
9596 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9597 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9598 alloc_cc(&branch_regs[i-1],i-1);
9599 dirty_reg(&branch_regs[i-1],CCREG);
9600 alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]);
9601 if(rt1[i-1]!=0) { // JALR
9602 alloc_reg(&branch_regs[i-1],i-1,rt1[i-1]);
9603 dirty_reg(&branch_regs[i-1],rt1[i-1]);
9604 branch_regs[i-1].is32|=1LL<<rt1[i-1];
9607 if(rs1[i-1]==31) { // JALR
9608 alloc_reg(&branch_regs[i-1],i-1,RHASH);
9609 #ifndef HOST_IMM_ADDR32
9610 alloc_reg(&branch_regs[i-1],i-1,RHTBL);
9614 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9615 memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
9618 if((opcode[i-1]&0x3E)==4) // BEQ/BNE
9620 alloc_cc(¤t,i-1);
9621 dirty_reg(¤t,CCREG);
9622 if((rs1[i-1]&&(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]))||
9623 (rs2[i-1]&&(rs2[i-1]==rt1[i]||rs2[i-1]==rt2[i]))) {
9624 // The delay slot overwrote one of our conditions
9625 // Delay slot goes after the test (in order)
9626 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9627 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9628 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9631 delayslot_alloc(¤t,i);
9636 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9637 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9638 // Alloc the branch condition registers
9639 if(rs1[i-1]) alloc_reg(¤t,i-1,rs1[i-1]);
9640 if(rs2[i-1]) alloc_reg(¤t,i-1,rs2[i-1]);
9641 if(!((current.is32>>rs1[i-1])&(current.is32>>rs2[i-1])&1))
9643 if(rs1[i-1]) alloc_reg64(¤t,i-1,rs1[i-1]);
9644 if(rs2[i-1]) alloc_reg64(¤t,i-1,rs2[i-1]);
9647 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9648 branch_regs[i-1].isconst=0;
9649 branch_regs[i-1].wasconst=0;
9650 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9651 memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
9654 if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ
9656 alloc_cc(¤t,i-1);
9657 dirty_reg(¤t,CCREG);
9658 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9659 // The delay slot overwrote the branch condition
9660 // Delay slot goes after the test (in order)
9661 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9662 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9663 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9666 delayslot_alloc(¤t,i);
9671 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9672 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9673 // Alloc the branch condition register
9674 alloc_reg(¤t,i-1,rs1[i-1]);
9675 if(!(current.is32>>rs1[i-1]&1))
9677 alloc_reg64(¤t,i-1,rs1[i-1]);
9680 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9681 branch_regs[i-1].isconst=0;
9682 branch_regs[i-1].wasconst=0;
9683 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9684 memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
9687 // Alloc the delay slot in case the branch is taken
9688 if((opcode[i-1]&0x3E)==0x14) // BEQL/BNEL
9690 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9691 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9692 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9693 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9694 alloc_cc(&branch_regs[i-1],i);
9695 dirty_reg(&branch_regs[i-1],CCREG);
9696 delayslot_alloc(&branch_regs[i-1],i);
9697 branch_regs[i-1].isconst=0;
9698 alloc_reg(¤t,i,CCREG); // Not taken path
9699 dirty_reg(¤t,CCREG);
9700 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9703 if((opcode[i-1]&0x3E)==0x16) // BLEZL/BGTZL
9705 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9706 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9707 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9708 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9709 alloc_cc(&branch_regs[i-1],i);
9710 dirty_reg(&branch_regs[i-1],CCREG);
9711 delayslot_alloc(&branch_regs[i-1],i);
9712 branch_regs[i-1].isconst=0;
9713 alloc_reg(¤t,i,CCREG); // Not taken path
9714 dirty_reg(¤t,CCREG);
9715 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9719 //if((opcode2[i-1]&0x1E)==0) // BLTZ/BGEZ
9720 if((opcode2[i-1]&0x0E)==0) // BLTZ/BGEZ
9722 alloc_cc(¤t,i-1);
9723 dirty_reg(¤t,CCREG);
9724 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9725 // The delay slot overwrote the branch condition
9726 // Delay slot goes after the test (in order)
9727 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9728 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9729 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9732 delayslot_alloc(¤t,i);
9737 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9738 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9739 // Alloc the branch condition register
9740 alloc_reg(¤t,i-1,rs1[i-1]);
9741 if(!(current.is32>>rs1[i-1]&1))
9743 alloc_reg64(¤t,i-1,rs1[i-1]);
9746 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9747 branch_regs[i-1].isconst=0;
9748 branch_regs[i-1].wasconst=0;
9749 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9750 memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
9753 // Alloc the delay slot in case the branch is taken
9754 if((opcode2[i-1]&0x1E)==2) // BLTZL/BGEZL
9756 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9757 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9758 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9759 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9760 alloc_cc(&branch_regs[i-1],i);
9761 dirty_reg(&branch_regs[i-1],CCREG);
9762 delayslot_alloc(&branch_regs[i-1],i);
9763 branch_regs[i-1].isconst=0;
9764 alloc_reg(¤t,i,CCREG); // Not taken path
9765 dirty_reg(¤t,CCREG);
9766 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9768 // FIXME: BLTZAL/BGEZAL
9769 if(opcode2[i-1]&0x10) { // BxxZAL
9770 alloc_reg(&branch_regs[i-1],i-1,31);
9771 dirty_reg(&branch_regs[i-1],31);
9772 branch_regs[i-1].is32|=1LL<<31;
9776 if(likely[i-1]==0) // BC1F/BC1T
9778 alloc_cc(¤t,i-1);
9779 dirty_reg(¤t,CCREG);
9780 if(itype[i]==FCOMP) {
9781 // The delay slot overwrote the branch condition
9782 // Delay slot goes after the test (in order)
9783 delayslot_alloc(¤t,i);
9788 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9789 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9790 // Alloc the branch condition register
9791 alloc_reg(¤t,i-1,FSREG);
9793 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9794 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9798 // Alloc the delay slot in case the branch is taken
9799 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9800 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9801 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9802 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9803 alloc_cc(&branch_regs[i-1],i);
9804 dirty_reg(&branch_regs[i-1],CCREG);
9805 delayslot_alloc(&branch_regs[i-1],i);
9806 branch_regs[i-1].isconst=0;
9807 alloc_reg(¤t,i,CCREG); // Not taken path
9808 dirty_reg(¤t,CCREG);
9809 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9814 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
9816 if(rt1[i-1]==31) // JAL/JALR
9818 // Subroutine call will return here, don't alloc any registers
9821 clear_all_regs(current.regmap);
9822 alloc_reg(¤t,i,CCREG);
9823 dirty_reg(¤t,CCREG);
9827 // Internal branch will jump here, match registers to caller
9828 current.is32=0x3FFFFFFFFLL;
9830 clear_all_regs(current.regmap);
9831 alloc_reg(¤t,i,CCREG);
9832 dirty_reg(¤t,CCREG);
9835 if(ba[j]==start+i*4+4) {
9836 memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
9837 current.is32=branch_regs[j].is32;
9838 current.dirty=branch_regs[j].dirty;
9843 if(ba[j]==start+i*4+4) {
9844 for(hr=0;hr<HOST_REGS;hr++) {
9845 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
9846 current.regmap[hr]=-1;
9848 current.is32&=branch_regs[j].is32;
9849 current.dirty&=branch_regs[j].dirty;
9858 // Count cycles in between branches
9860 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP||itype[i]==SYSCALL||itype[i]==HLECALL))
9864 #if defined(PCSX) && !defined(DRC_DBG)
9865 else if(itype[i]==C2OP&>e_cycletab[source[i]&0x3f]>2)
9867 // GTE runs in parallel until accessed, divide by 2 for a rough guess
9868 cc+=gte_cycletab[source[i]&0x3f]/2;
9870 else if(/*itype[i]==LOAD||itype[i]==STORE||*/itype[i]==C1LS) // load,store causes weird timing issues
9872 cc+=2; // 2 cycle penalty (after CLOCK_DIVIDER)
9874 else if(itype[i]==C2LS)
9884 flush_dirty_uppers(¤t);
9886 regs[i].is32=current.is32;
9887 regs[i].dirty=current.dirty;
9888 regs[i].isconst=current.isconst;
9889 memcpy(constmap[i],current_constmap,sizeof(current_constmap));
9891 for(hr=0;hr<HOST_REGS;hr++) {
9892 if(hr!=EXCLUDE_REG&®s[i].regmap[hr]>=0) {
9893 if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
9894 regs[i].wasconst&=~(1<<hr);
9898 if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
9899 regs[i].waswritten=current.waswritten;
9902 /* Pass 4 - Cull unused host registers */
9906 for (i=slen-1;i>=0;i--)
9909 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9911 if(ba[i]<start || ba[i]>=(start+slen*4))
9913 // Branch out of this block, don't need anything
9919 // Need whatever matches the target
9921 int t=(ba[i]-start)>>2;
9922 for(hr=0;hr<HOST_REGS;hr++)
9924 if(regs[i].regmap_entry[hr]>=0) {
9925 if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
9929 // Conditional branch may need registers for following instructions
9930 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9933 nr|=needed_reg[i+2];
9934 for(hr=0;hr<HOST_REGS;hr++)
9936 if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
9937 //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
9941 // Don't need stuff which is overwritten
9942 //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9943 //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9944 // Merge in delay slot
9945 for(hr=0;hr<HOST_REGS;hr++)
9948 // These are overwritten unless the branch is "likely"
9949 // and the delay slot is nullified if not taken
9950 if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9951 if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9953 if(us1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9954 if(us2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9955 if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9956 if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9957 if(us1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9958 if(us2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9959 if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9960 if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9961 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1)) {
9962 if(dep1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9963 if(dep2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9965 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1)) {
9966 if(dep1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9967 if(dep2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9969 if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) {
9970 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9971 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9975 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
9977 // SYSCALL instruction (software interrupt)
9980 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
9982 // ERET instruction (return from interrupt)
9988 for(hr=0;hr<HOST_REGS;hr++) {
9989 if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
9990 if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
9991 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9992 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9996 for(hr=0;hr<HOST_REGS;hr++)
9998 // Overwritten registers are not needed
9999 if(rt1[i]&&rt1[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
10000 if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
10001 if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
10002 // Source registers are needed
10003 if(us1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
10004 if(us2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
10005 if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr;
10006 if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr;
10007 if(us1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
10008 if(us2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
10009 if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
10010 if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
10011 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1)) {
10012 if(dep1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
10013 if(dep1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
10015 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1)) {
10016 if(dep2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
10017 if(dep2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
10019 if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) {
10020 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
10021 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
10023 // Don't store a register immediately after writing it,
10024 // may prevent dual-issue.
10025 // But do so if this is a branch target, otherwise we
10026 // might have to load the register before the branch.
10027 if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) {
10028 if((regmap_pre[i][hr]>0&®map_pre[i][hr]<64&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1)) ||
10029 (regmap_pre[i][hr]>64&&!((unneeded_reg_upper[i]>>(regmap_pre[i][hr]&63))&1)) ) {
10030 if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
10031 if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
10033 if((regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1)) ||
10034 (regs[i].regmap_entry[hr]>64&&!((unneeded_reg_upper[i]>>(regs[i].regmap_entry[hr]&63))&1)) ) {
10035 if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
10036 if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
10040 // Cycle count is needed at branches. Assume it is needed at the target too.
10041 if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==FJUMP||itype[i]==SPAN) {
10042 if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
10043 if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
10048 // Deallocate unneeded registers
10049 for(hr=0;hr<HOST_REGS;hr++)
10051 if(!((nr>>hr)&1)) {
10052 if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
10053 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
10054 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
10055 (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG)
10057 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10060 regs[i].regmap[hr]=-1;
10061 regs[i].isconst&=~(1<<hr);
10063 regmap_pre[i+2][hr]=-1;
10064 regs[i+2].wasconst&=~(1<<hr);
10069 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10071 int d1=0,d2=0,map=0,temp=0;
10072 if(get_reg(regs[i].regmap,rt1[i+1]|64)>=0||get_reg(branch_regs[i].regmap,rt1[i+1]|64)>=0)
10078 if(itype[i+1]==LOAD || itype[i+1]==LOADLR ||
10079 itype[i+1]==STORE || itype[i+1]==STORELR ||
10080 itype[i+1]==C1LS || itype[i+1]==C2LS)
10083 if(itype[i+1]==STORE || itype[i+1]==STORELR ||
10084 (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
10087 if(itype[i+1]==LOADLR || itype[i+1]==STORELR ||
10088 itype[i+1]==C1LS || itype[i+1]==C2LS)
10090 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
10091 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
10092 (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] &&
10093 (regs[i].regmap[hr]^64)!=us1[i+1] && (regs[i].regmap[hr]^64)!=us2[i+1] &&
10094 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
10095 regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] &&
10096 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
10097 regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
10098 regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
10099 regs[i].regmap[hr]!=map )
10101 regs[i].regmap[hr]=-1;
10102 regs[i].isconst&=~(1<<hr);
10103 if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] &&
10104 (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] &&
10105 (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] &&
10106 (branch_regs[i].regmap[hr]^64)!=us1[i+1] && (branch_regs[i].regmap[hr]^64)!=us2[i+1] &&
10107 (branch_regs[i].regmap[hr]^64)!=d1 && (branch_regs[i].regmap[hr]^64)!=d2 &&
10108 branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] &&
10109 (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
10110 branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
10111 branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
10112 branch_regs[i].regmap[hr]!=map)
10114 branch_regs[i].regmap[hr]=-1;
10115 branch_regs[i].regmap_entry[hr]=-1;
10116 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10118 if(!likely[i]&&i<slen-2) {
10119 regmap_pre[i+2][hr]=-1;
10120 regs[i+2].wasconst&=~(1<<hr);
10131 int d1=0,d2=0,map=-1,temp=-1;
10132 if(get_reg(regs[i].regmap,rt1[i]|64)>=0)
10138 if(itype[i]==LOAD || itype[i]==LOADLR ||
10139 itype[i]==STORE || itype[i]==STORELR ||
10140 itype[i]==C1LS || itype[i]==C2LS)
10142 } else if(itype[i]==STORE || itype[i]==STORELR ||
10143 (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
10146 if(itype[i]==LOADLR || itype[i]==STORELR ||
10147 itype[i]==C1LS || itype[i]==C2LS)
10149 if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
10150 (regs[i].regmap[hr]^64)!=us1[i] && (regs[i].regmap[hr]^64)!=us2[i] &&
10151 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
10152 regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] &&
10153 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map &&
10154 (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG))
10156 if(i<slen-1&&!is_ds[i]) {
10157 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]!=-1)
10158 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
10159 if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
10161 printf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
10162 assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
10164 regmap_pre[i+1][hr]=-1;
10165 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
10166 regs[i+1].wasconst&=~(1<<hr);
10168 regs[i].regmap[hr]=-1;
10169 regs[i].isconst&=~(1<<hr);
10177 /* Pass 5 - Pre-allocate registers */
10179 // If a register is allocated during a loop, try to allocate it for the
10180 // entire loop, if possible. This avoids loading/storing registers
10181 // inside of the loop.
10183 signed char f_regmap[HOST_REGS];
10184 clear_all_regs(f_regmap);
10185 for(i=0;i<slen-1;i++)
10187 if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10189 if(ba[i]>=start && ba[i]<(start+i*4))
10190 if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
10191 ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
10192 ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
10193 ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
10194 ||itype[i+1]==FCOMP||itype[i+1]==FCONV
10195 ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
10197 int t=(ba[i]-start)>>2;
10198 if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots
10199 if(t<2||(itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||rt1[t-2]!=31) // call/ret assumes no registers allocated
10200 for(hr=0;hr<HOST_REGS;hr++)
10202 if(regs[i].regmap[hr]>64) {
10203 if(!((regs[i].dirty>>hr)&1))
10204 f_regmap[hr]=regs[i].regmap[hr];
10205 else f_regmap[hr]=-1;
10207 else if(regs[i].regmap[hr]>=0) {
10208 if(f_regmap[hr]!=regs[i].regmap[hr]) {
10209 // dealloc old register
10211 for(n=0;n<HOST_REGS;n++)
10213 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
10215 // and alloc new one
10216 f_regmap[hr]=regs[i].regmap[hr];
10219 if(branch_regs[i].regmap[hr]>64) {
10220 if(!((branch_regs[i].dirty>>hr)&1))
10221 f_regmap[hr]=branch_regs[i].regmap[hr];
10222 else f_regmap[hr]=-1;
10224 else if(branch_regs[i].regmap[hr]>=0) {
10225 if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
10226 // dealloc old register
10228 for(n=0;n<HOST_REGS;n++)
10230 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
10232 // and alloc new one
10233 f_regmap[hr]=branch_regs[i].regmap[hr];
10237 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
10238 f_regmap[hr]=branch_regs[i].regmap[hr];
10240 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
10241 f_regmap[hr]=branch_regs[i].regmap[hr];
10243 // Avoid dirty->clean transition
10244 #ifdef DESTRUCTIVE_WRITEBACK
10245 if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
10247 // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
10248 // case above, however it's always a good idea. We can't hoist the
10249 // load if the register was already allocated, so there's no point
10250 // wasting time analyzing most of these cases. It only "succeeds"
10251 // when the mapping was different and the load can be replaced with
10252 // a mov, which is of negligible benefit. So such cases are
10254 if(f_regmap[hr]>0) {
10255 if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
10256 int r=f_regmap[hr];
10259 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
10260 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
10261 if(r>63&&((unneeded_reg_upper[j]>>(r&63))&1)) break;
10263 // NB This can exclude the case where the upper-half
10264 // register is lower numbered than the lower-half
10265 // register. Not sure if it's worth fixing...
10266 if(get_reg(regs[j].regmap,r&63)<0) break;
10267 if(get_reg(regs[j].regmap_entry,r&63)<0) break;
10268 if(regs[j].is32&(1LL<<(r&63))) break;
10270 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
10271 //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
10273 if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
10274 if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
10276 if(get_reg(regs[i].regmap,r&63)<0) break;
10277 if(get_reg(branch_regs[i].regmap,r&63)<0) break;
10280 while(k>1&®s[k-1].regmap[hr]==-1) {
10281 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10282 //printf("no free regs for store %x\n",start+(k-1)*4);
10285 if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
10286 //printf("no-match due to different register\n");
10289 if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP||itype[k-2]==FJUMP) {
10290 //printf("no-match due to branch\n");
10293 // call/ret fast path assumes no registers allocated
10294 if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)&&rt1[k-3]==31) {
10298 // NB This can exclude the case where the upper-half
10299 // register is lower numbered than the lower-half
10300 // register. Not sure if it's worth fixing...
10301 if(get_reg(regs[k-1].regmap,r&63)<0) break;
10302 if(regs[k-1].is32&(1LL<<(r&63))) break;
10307 if((regs[k].is32&(1LL<<f_regmap[hr]))!=
10308 (regs[i+2].was32&(1LL<<f_regmap[hr]))) {
10309 //printf("bad match after branch\n");
10313 if(regs[k-1].regmap[hr]==f_regmap[hr]&®map_pre[k][hr]==f_regmap[hr]) {
10314 //printf("Extend r%d, %x ->\n",hr,start+k*4);
10316 regs[k].regmap_entry[hr]=f_regmap[hr];
10317 regs[k].regmap[hr]=f_regmap[hr];
10318 regmap_pre[k+1][hr]=f_regmap[hr];
10319 regs[k].wasdirty&=~(1<<hr);
10320 regs[k].dirty&=~(1<<hr);
10321 regs[k].wasdirty|=(1<<hr)®s[k-1].dirty;
10322 regs[k].dirty|=(1<<hr)®s[k].wasdirty;
10323 regs[k].wasconst&=~(1<<hr);
10324 regs[k].isconst&=~(1<<hr);
10329 //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
10332 assert(regs[i-1].regmap[hr]==f_regmap[hr]);
10333 if(regs[i-1].regmap[hr]==f_regmap[hr]&®map_pre[i][hr]==f_regmap[hr]) {
10334 //printf("OK fill %x (r%d)\n",start+i*4,hr);
10335 regs[i].regmap_entry[hr]=f_regmap[hr];
10336 regs[i].regmap[hr]=f_regmap[hr];
10337 regs[i].wasdirty&=~(1<<hr);
10338 regs[i].dirty&=~(1<<hr);
10339 regs[i].wasdirty|=(1<<hr)®s[i-1].dirty;
10340 regs[i].dirty|=(1<<hr)®s[i-1].dirty;
10341 regs[i].wasconst&=~(1<<hr);
10342 regs[i].isconst&=~(1<<hr);
10343 branch_regs[i].regmap_entry[hr]=f_regmap[hr];
10344 branch_regs[i].wasdirty&=~(1<<hr);
10345 branch_regs[i].wasdirty|=(1<<hr)®s[i].dirty;
10346 branch_regs[i].regmap[hr]=f_regmap[hr];
10347 branch_regs[i].dirty&=~(1<<hr);
10348 branch_regs[i].dirty|=(1<<hr)®s[i].dirty;
10349 branch_regs[i].wasconst&=~(1<<hr);
10350 branch_regs[i].isconst&=~(1<<hr);
10351 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
10352 regmap_pre[i+2][hr]=f_regmap[hr];
10353 regs[i+2].wasdirty&=~(1<<hr);
10354 regs[i+2].wasdirty|=(1<<hr)®s[i].dirty;
10355 assert((branch_regs[i].is32&(1LL<<f_regmap[hr]))==
10356 (regs[i+2].was32&(1LL<<f_regmap[hr])));
10361 // Alloc register clean at beginning of loop,
10362 // but may dirty it in pass 6
10363 regs[k].regmap_entry[hr]=f_regmap[hr];
10364 regs[k].regmap[hr]=f_regmap[hr];
10365 regs[k].dirty&=~(1<<hr);
10366 regs[k].wasconst&=~(1<<hr);
10367 regs[k].isconst&=~(1<<hr);
10368 if(itype[k]==UJUMP||itype[k]==RJUMP||itype[k]==CJUMP||itype[k]==SJUMP||itype[k]==FJUMP) {
10369 branch_regs[k].regmap_entry[hr]=f_regmap[hr];
10370 branch_regs[k].regmap[hr]=f_regmap[hr];
10371 branch_regs[k].dirty&=~(1<<hr);
10372 branch_regs[k].wasconst&=~(1<<hr);
10373 branch_regs[k].isconst&=~(1<<hr);
10374 if(itype[k]!=RJUMP&&itype[k]!=UJUMP&&(source[k]>>16)!=0x1000) {
10375 regmap_pre[k+2][hr]=f_regmap[hr];
10376 regs[k+2].wasdirty&=~(1<<hr);
10377 assert((branch_regs[k].is32&(1LL<<f_regmap[hr]))==
10378 (regs[k+2].was32&(1LL<<f_regmap[hr])));
10383 regmap_pre[k+1][hr]=f_regmap[hr];
10384 regs[k+1].wasdirty&=~(1<<hr);
10387 if(regs[j].regmap[hr]==f_regmap[hr])
10388 regs[j].regmap_entry[hr]=f_regmap[hr];
10392 if(regs[j].regmap[hr]>=0)
10394 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
10395 //printf("no-match due to different register\n");
10398 if((regs[j+1].is32&(1LL<<f_regmap[hr]))!=(regs[j].is32&(1LL<<f_regmap[hr]))) {
10399 //printf("32/64 mismatch %x %d\n",start+j*4,hr);
10402 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10404 // Stop on unconditional branch
10407 if(itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP)
10410 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
10413 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
10416 if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
10417 //printf("no-match due to different register (branch)\n");
10421 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10422 //printf("No free regs for store %x\n",start+j*4);
10425 if(f_regmap[hr]>=64) {
10426 if(regs[j].is32&(1LL<<(f_regmap[hr]&63))) {
10431 if(get_reg(regs[j].regmap,f_regmap[hr]&63)<0) {
10442 // Non branch or undetermined branch target
10443 for(hr=0;hr<HOST_REGS;hr++)
10445 if(hr!=EXCLUDE_REG) {
10446 if(regs[i].regmap[hr]>64) {
10447 if(!((regs[i].dirty>>hr)&1))
10448 f_regmap[hr]=regs[i].regmap[hr];
10450 else if(regs[i].regmap[hr]>=0) {
10451 if(f_regmap[hr]!=regs[i].regmap[hr]) {
10452 // dealloc old register
10454 for(n=0;n<HOST_REGS;n++)
10456 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
10458 // and alloc new one
10459 f_regmap[hr]=regs[i].regmap[hr];
10464 // Try to restore cycle count at branch targets
10466 for(j=i;j<slen-1;j++) {
10467 if(regs[j].regmap[HOST_CCREG]!=-1) break;
10468 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10469 //printf("no free regs for store %x\n",start+j*4);
10473 if(regs[j].regmap[HOST_CCREG]==CCREG) {
10475 //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
10477 regs[k].regmap_entry[HOST_CCREG]=CCREG;
10478 regs[k].regmap[HOST_CCREG]=CCREG;
10479 regmap_pre[k+1][HOST_CCREG]=CCREG;
10480 regs[k+1].wasdirty|=1<<HOST_CCREG;
10481 regs[k].dirty|=1<<HOST_CCREG;
10482 regs[k].wasconst&=~(1<<HOST_CCREG);
10483 regs[k].isconst&=~(1<<HOST_CCREG);
10486 regs[j].regmap_entry[HOST_CCREG]=CCREG;
10488 // Work backwards from the branch target
10489 if(j>i&&f_regmap[HOST_CCREG]==CCREG)
10491 //printf("Extend backwards\n");
10494 while(regs[k-1].regmap[HOST_CCREG]==-1) {
10495 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10496 //printf("no free regs for store %x\n",start+(k-1)*4);
10501 if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
10502 //printf("Extend CC, %x ->\n",start+k*4);
10504 regs[k].regmap_entry[HOST_CCREG]=CCREG;
10505 regs[k].regmap[HOST_CCREG]=CCREG;
10506 regmap_pre[k+1][HOST_CCREG]=CCREG;
10507 regs[k+1].wasdirty|=1<<HOST_CCREG;
10508 regs[k].dirty|=1<<HOST_CCREG;
10509 regs[k].wasconst&=~(1<<HOST_CCREG);
10510 regs[k].isconst&=~(1<<HOST_CCREG);
10515 //printf("Fail Extend CC, %x ->\n",start+k*4);
10519 if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&&
10520 itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&&
10521 itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1&&itype[i]!=FLOAT&&
10522 itype[i]!=FCONV&&itype[i]!=FCOMP)
10524 memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
10529 // Cache memory offset or tlb map pointer if a register is available
10530 #ifndef HOST_IMM_ADDR32
10535 int earliest_available[HOST_REGS];
10536 int loop_start[HOST_REGS];
10537 int score[HOST_REGS];
10538 int end[HOST_REGS];
10539 int reg=using_tlb?MMREG:ROREG;
10542 for(hr=0;hr<HOST_REGS;hr++) {
10543 score[hr]=0;earliest_available[hr]=0;
10544 loop_start[hr]=MAXBLOCK;
10546 for(i=0;i<slen-1;i++)
10548 // Can't do anything if no registers are available
10549 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i]) {
10550 for(hr=0;hr<HOST_REGS;hr++) {
10551 score[hr]=0;earliest_available[hr]=i+1;
10552 loop_start[hr]=MAXBLOCK;
10555 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10557 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1]) {
10558 for(hr=0;hr<HOST_REGS;hr++) {
10559 score[hr]=0;earliest_available[hr]=i+1;
10560 loop_start[hr]=MAXBLOCK;
10564 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1]) {
10565 for(hr=0;hr<HOST_REGS;hr++) {
10566 score[hr]=0;earliest_available[hr]=i+1;
10567 loop_start[hr]=MAXBLOCK;
10572 // Mark unavailable registers
10573 for(hr=0;hr<HOST_REGS;hr++) {
10574 if(regs[i].regmap[hr]>=0) {
10575 score[hr]=0;earliest_available[hr]=i+1;
10576 loop_start[hr]=MAXBLOCK;
10578 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10579 if(branch_regs[i].regmap[hr]>=0) {
10580 score[hr]=0;earliest_available[hr]=i+2;
10581 loop_start[hr]=MAXBLOCK;
10585 // No register allocations after unconditional jumps
10586 if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
10588 for(hr=0;hr<HOST_REGS;hr++) {
10589 score[hr]=0;earliest_available[hr]=i+2;
10590 loop_start[hr]=MAXBLOCK;
10592 i++; // Skip delay slot too
10593 //printf("skip delay slot: %x\n",start+i*4);
10597 if(itype[i]==LOAD||itype[i]==LOADLR||
10598 itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS) {
10599 for(hr=0;hr<HOST_REGS;hr++) {
10600 if(hr!=EXCLUDE_REG) {
10602 for(j=i;j<slen-1;j++) {
10603 if(regs[j].regmap[hr]>=0) break;
10604 if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10605 if(branch_regs[j].regmap[hr]>=0) break;
10607 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1]) break;
10609 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1]) break;
10612 else if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) break;
10613 if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10614 int t=(ba[j]-start)>>2;
10615 if(t<j&&t>=earliest_available[hr]) {
10616 if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) { // call/ret assumes no registers allocated
10617 // Score a point for hoisting loop invariant
10618 if(t<loop_start[hr]) loop_start[hr]=t;
10619 //printf("set loop_start: i=%x j=%x (%x)\n",start+i*4,start+j*4,start+t*4);
10625 if(regs[t].regmap[hr]==reg) {
10626 // Score a point if the branch target matches this register
10631 if(itype[j+1]==LOAD||itype[j+1]==LOADLR||
10632 itype[j+1]==STORE||itype[j+1]==STORELR||itype[j+1]==C1LS) {
10637 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10639 // Stop on unconditional branch
10643 if(itype[j]==LOAD||itype[j]==LOADLR||
10644 itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS) {
10651 // Find highest score and allocate that register
10653 for(hr=0;hr<HOST_REGS;hr++) {
10654 if(hr!=EXCLUDE_REG) {
10655 if(score[hr]>score[maxscore]) {
10657 //printf("highest score: %d %d (%x->%x)\n",score[hr],hr,start+i*4,start+end[hr]*4);
10661 if(score[maxscore]>1)
10663 if(i<loop_start[maxscore]) loop_start[maxscore]=i;
10664 for(j=loop_start[maxscore];j<slen&&j<=end[maxscore];j++) {
10665 //if(regs[j].regmap[maxscore]>=0) {printf("oops: %x %x was %d=%d\n",loop_start[maxscore]*4+start,j*4+start,maxscore,regs[j].regmap[maxscore]);}
10666 assert(regs[j].regmap[maxscore]<0);
10667 if(j>loop_start[maxscore]) regs[j].regmap_entry[maxscore]=reg;
10668 regs[j].regmap[maxscore]=reg;
10669 regs[j].dirty&=~(1<<maxscore);
10670 regs[j].wasconst&=~(1<<maxscore);
10671 regs[j].isconst&=~(1<<maxscore);
10672 if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10673 branch_regs[j].regmap[maxscore]=reg;
10674 branch_regs[j].wasdirty&=~(1<<maxscore);
10675 branch_regs[j].dirty&=~(1<<maxscore);
10676 branch_regs[j].wasconst&=~(1<<maxscore);
10677 branch_regs[j].isconst&=~(1<<maxscore);
10678 if(itype[j]!=RJUMP&&itype[j]!=UJUMP&&(source[j]>>16)!=0x1000) {
10679 regmap_pre[j+2][maxscore]=reg;
10680 regs[j+2].wasdirty&=~(1<<maxscore);
10682 // loop optimization (loop_preload)
10683 int t=(ba[j]-start)>>2;
10684 if(t==loop_start[maxscore]) {
10685 if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) // call/ret assumes no registers allocated
10686 regs[t].regmap_entry[maxscore]=reg;
10691 if(j<1||(itype[j-1]!=RJUMP&&itype[j-1]!=UJUMP&&itype[j-1]!=CJUMP&&itype[j-1]!=SJUMP&&itype[j-1]!=FJUMP)) {
10692 regmap_pre[j+1][maxscore]=reg;
10693 regs[j+1].wasdirty&=~(1<<maxscore);
10698 if(itype[j-1]==RJUMP||itype[j-1]==UJUMP||itype[j-1]==CJUMP||itype[j-1]==SJUMP||itype[j-1]==FJUMP) i++; // skip delay slot
10699 for(hr=0;hr<HOST_REGS;hr++) {
10700 score[hr]=0;earliest_available[hr]=i+i;
10701 loop_start[hr]=MAXBLOCK;
10709 // This allocates registers (if possible) one instruction prior
10710 // to use, which can avoid a load-use penalty on certain CPUs.
10711 for(i=0;i<slen-1;i++)
10713 if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP))
10717 if(itype[i]==ALU||itype[i]==MOV||itype[i]==LOAD||itype[i]==SHIFTIMM||itype[i]==IMM16
10718 ||((itype[i]==COP1||itype[i]==COP2)&&opcode2[i]<3))
10721 if((hr=get_reg(regs[i+1].regmap,rs1[i+1]))>=0)
10723 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10725 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10726 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10727 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10728 regs[i].isconst&=~(1<<hr);
10729 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10730 constmap[i][hr]=constmap[i+1][hr];
10731 regs[i+1].wasdirty&=~(1<<hr);
10732 regs[i].dirty&=~(1<<hr);
10737 if((hr=get_reg(regs[i+1].regmap,rs2[i+1]))>=0)
10739 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10741 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10742 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10743 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10744 regs[i].isconst&=~(1<<hr);
10745 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10746 constmap[i][hr]=constmap[i+1][hr];
10747 regs[i+1].wasdirty&=~(1<<hr);
10748 regs[i].dirty&=~(1<<hr);
10752 // Preload target address for load instruction (non-constant)
10753 if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10754 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10756 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10758 regs[i].regmap[hr]=rs1[i+1];
10759 regmap_pre[i+1][hr]=rs1[i+1];
10760 regs[i+1].regmap_entry[hr]=rs1[i+1];
10761 regs[i].isconst&=~(1<<hr);
10762 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10763 constmap[i][hr]=constmap[i+1][hr];
10764 regs[i+1].wasdirty&=~(1<<hr);
10765 regs[i].dirty&=~(1<<hr);
10769 // Load source into target register
10770 if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10771 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10773 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10775 regs[i].regmap[hr]=rs1[i+1];
10776 regmap_pre[i+1][hr]=rs1[i+1];
10777 regs[i+1].regmap_entry[hr]=rs1[i+1];
10778 regs[i].isconst&=~(1<<hr);
10779 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10780 constmap[i][hr]=constmap[i+1][hr];
10781 regs[i+1].wasdirty&=~(1<<hr);
10782 regs[i].dirty&=~(1<<hr);
10786 // Preload map address
10787 #ifndef HOST_IMM_ADDR32
10788 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
10789 hr=get_reg(regs[i+1].regmap,TLREG);
10791 int sr=get_reg(regs[i+1].regmap,rs1[i+1]);
10792 if(sr>=0&&((regs[i+1].wasconst>>sr)&1)) {
10794 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10796 regs[i].regmap[hr]=MGEN1+((i+1)&1);
10797 regmap_pre[i+1][hr]=MGEN1+((i+1)&1);
10798 regs[i+1].regmap_entry[hr]=MGEN1+((i+1)&1);
10799 regs[i].isconst&=~(1<<hr);
10800 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10801 constmap[i][hr]=constmap[i+1][hr];
10802 regs[i+1].wasdirty&=~(1<<hr);
10803 regs[i].dirty&=~(1<<hr);
10805 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10807 // move it to another register
10808 regs[i+1].regmap[hr]=-1;
10809 regmap_pre[i+2][hr]=-1;
10810 regs[i+1].regmap[nr]=TLREG;
10811 regmap_pre[i+2][nr]=TLREG;
10812 regs[i].regmap[nr]=MGEN1+((i+1)&1);
10813 regmap_pre[i+1][nr]=MGEN1+((i+1)&1);
10814 regs[i+1].regmap_entry[nr]=MGEN1+((i+1)&1);
10815 regs[i].isconst&=~(1<<nr);
10816 regs[i+1].isconst&=~(1<<nr);
10817 regs[i].dirty&=~(1<<nr);
10818 regs[i+1].wasdirty&=~(1<<nr);
10819 regs[i+1].dirty&=~(1<<nr);
10820 regs[i+2].wasdirty&=~(1<<nr);
10826 // Address for store instruction (non-constant)
10827 if(itype[i+1]==STORE||itype[i+1]==STORELR
10828 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
10829 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10830 hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
10831 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10832 else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
10834 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10836 regs[i].regmap[hr]=rs1[i+1];
10837 regmap_pre[i+1][hr]=rs1[i+1];
10838 regs[i+1].regmap_entry[hr]=rs1[i+1];
10839 regs[i].isconst&=~(1<<hr);
10840 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10841 constmap[i][hr]=constmap[i+1][hr];
10842 regs[i+1].wasdirty&=~(1<<hr);
10843 regs[i].dirty&=~(1<<hr);
10847 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
10848 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10850 hr=get_reg(regs[i+1].regmap,FTEMP);
10852 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10854 regs[i].regmap[hr]=rs1[i+1];
10855 regmap_pre[i+1][hr]=rs1[i+1];
10856 regs[i+1].regmap_entry[hr]=rs1[i+1];
10857 regs[i].isconst&=~(1<<hr);
10858 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10859 constmap[i][hr]=constmap[i+1][hr];
10860 regs[i+1].wasdirty&=~(1<<hr);
10861 regs[i].dirty&=~(1<<hr);
10863 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10865 // move it to another register
10866 regs[i+1].regmap[hr]=-1;
10867 regmap_pre[i+2][hr]=-1;
10868 regs[i+1].regmap[nr]=FTEMP;
10869 regmap_pre[i+2][nr]=FTEMP;
10870 regs[i].regmap[nr]=rs1[i+1];
10871 regmap_pre[i+1][nr]=rs1[i+1];
10872 regs[i+1].regmap_entry[nr]=rs1[i+1];
10873 regs[i].isconst&=~(1<<nr);
10874 regs[i+1].isconst&=~(1<<nr);
10875 regs[i].dirty&=~(1<<nr);
10876 regs[i+1].wasdirty&=~(1<<nr);
10877 regs[i+1].dirty&=~(1<<nr);
10878 regs[i+2].wasdirty&=~(1<<nr);
10882 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS||||itype[i+1]==C2LS*/) {
10883 if(itype[i+1]==LOAD)
10884 hr=get_reg(regs[i+1].regmap,rt1[i+1]);
10885 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
10886 hr=get_reg(regs[i+1].regmap,FTEMP);
10887 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
10888 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
10889 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10891 if(hr>=0&®s[i].regmap[hr]<0) {
10892 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
10893 if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
10894 regs[i].regmap[hr]=AGEN1+((i+1)&1);
10895 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
10896 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
10897 regs[i].isconst&=~(1<<hr);
10898 regs[i+1].wasdirty&=~(1<<hr);
10899 regs[i].dirty&=~(1<<hr);
10908 /* Pass 6 - Optimize clean/dirty state */
10909 clean_registers(0,slen-1,1);
10911 /* Pass 7 - Identify 32-bit registers */
10917 for (i=slen-1;i>=0;i--)
10920 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10922 if(ba[i]<start || ba[i]>=(start+slen*4))
10924 // Branch out of this block, don't need anything
10930 // Need whatever matches the target
10931 // (and doesn't get overwritten by the delay slot instruction)
10933 int t=(ba[i]-start)>>2;
10934 if(ba[i]>start+i*4) {
10936 if(!(requires_32bit[t]&~regs[i].was32))
10937 r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10940 //if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
10941 // r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10942 if(!(pr32[t]&~regs[i].was32))
10943 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10946 // Conditional branch may need registers for following instructions
10947 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10950 r32|=requires_32bit[i+2];
10951 r32&=regs[i].was32;
10952 // Mark this address as a branch target since it may be called
10953 // upon return from interrupt
10957 // Merge in delay slot
10959 // These are overwritten unless the branch is "likely"
10960 // and the delay slot is nullified if not taken
10961 r32&=~(1LL<<rt1[i+1]);
10962 r32&=~(1LL<<rt2[i+1]);
10964 // Assume these are needed (delay slot)
10967 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
10971 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
10973 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
10975 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
10977 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
10979 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
10982 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
10984 // SYSCALL instruction (software interrupt)
10987 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
10989 // ERET instruction (return from interrupt)
10993 r32&=~(1LL<<rt1[i]);
10994 r32&=~(1LL<<rt2[i]);
10997 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
11001 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
11003 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
11005 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
11007 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
11009 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
11011 requires_32bit[i]=r32;
11013 // Dirty registers which are 32-bit, require 32-bit input
11014 // as they will be written as 32-bit values
11015 for(hr=0;hr<HOST_REGS;hr++)
11017 if(regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64) {
11018 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
11019 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
11020 requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
11024 //requires_32bit[i]=is32[i]&~unneeded_reg_upper[i]; // DEBUG
11027 for (i=slen-1;i>=0;i--)
11029 if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
11031 // Conditional branch
11032 if((source[i]>>16)!=0x1000&&i<slen-2) {
11033 // Mark this address as a branch target since it may be called
11034 // upon return from interrupt
11041 if(itype[slen-1]==SPAN) {
11042 bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
11046 /* Debug/disassembly */
11047 for(i=0;i<slen;i++)
11051 for(r=1;r<=CCREG;r++) {
11052 if((unneeded_reg[i]>>r)&1) {
11053 if(r==HIREG) printf(" HI");
11054 else if(r==LOREG) printf(" LO");
11055 else printf(" r%d",r);
11060 for(r=1;r<=CCREG;r++) {
11061 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
11062 if(r==HIREG) printf(" HI");
11063 else if(r==LOREG) printf(" LO");
11064 else printf(" r%d",r);
11068 for(r=0;r<=CCREG;r++) {
11069 //if(((is32[i]>>r)&(~unneeded_reg[i]>>r))&1) {
11070 if((regs[i].was32>>r)&1) {
11071 if(r==CCREG) printf(" CC");
11072 else if(r==HIREG) printf(" HI");
11073 else if(r==LOREG) printf(" LO");
11074 else printf(" r%d",r);
11079 #if defined(__i386__) || defined(__x86_64__)
11080 printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
11083 printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
11086 if(needed_reg[i]&1) printf("eax ");
11087 if((needed_reg[i]>>1)&1) printf("ecx ");
11088 if((needed_reg[i]>>2)&1) printf("edx ");
11089 if((needed_reg[i]>>3)&1) printf("ebx ");
11090 if((needed_reg[i]>>5)&1) printf("ebp ");
11091 if((needed_reg[i]>>6)&1) printf("esi ");
11092 if((needed_reg[i]>>7)&1) printf("edi ");
11094 for(r=0;r<=CCREG;r++) {
11095 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
11096 if((requires_32bit[i]>>r)&1) {
11097 if(r==CCREG) printf(" CC");
11098 else if(r==HIREG) printf(" HI");
11099 else if(r==LOREG) printf(" LO");
11100 else printf(" r%d",r);
11105 for(r=0;r<=CCREG;r++) {
11106 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
11107 if((pr32[i]>>r)&1) {
11108 if(r==CCREG) printf(" CC");
11109 else if(r==HIREG) printf(" HI");
11110 else if(r==LOREG) printf(" LO");
11111 else printf(" r%d",r);
11114 if(pr32[i]!=requires_32bit[i]) printf(" OOPS");
11116 #if defined(__i386__) || defined(__x86_64__)
11117 printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
11119 if(regs[i].wasdirty&1) printf("eax ");
11120 if((regs[i].wasdirty>>1)&1) printf("ecx ");
11121 if((regs[i].wasdirty>>2)&1) printf("edx ");
11122 if((regs[i].wasdirty>>3)&1) printf("ebx ");
11123 if((regs[i].wasdirty>>5)&1) printf("ebp ");
11124 if((regs[i].wasdirty>>6)&1) printf("esi ");
11125 if((regs[i].wasdirty>>7)&1) printf("edi ");
11128 printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
11130 if(regs[i].wasdirty&1) printf("r0 ");
11131 if((regs[i].wasdirty>>1)&1) printf("r1 ");
11132 if((regs[i].wasdirty>>2)&1) printf("r2 ");
11133 if((regs[i].wasdirty>>3)&1) printf("r3 ");
11134 if((regs[i].wasdirty>>4)&1) printf("r4 ");
11135 if((regs[i].wasdirty>>5)&1) printf("r5 ");
11136 if((regs[i].wasdirty>>6)&1) printf("r6 ");
11137 if((regs[i].wasdirty>>7)&1) printf("r7 ");
11138 if((regs[i].wasdirty>>8)&1) printf("r8 ");
11139 if((regs[i].wasdirty>>9)&1) printf("r9 ");
11140 if((regs[i].wasdirty>>10)&1) printf("r10 ");
11141 if((regs[i].wasdirty>>12)&1) printf("r12 ");
11144 disassemble_inst(i);
11145 //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
11146 #if defined(__i386__) || defined(__x86_64__)
11147 printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
11148 if(regs[i].dirty&1) printf("eax ");
11149 if((regs[i].dirty>>1)&1) printf("ecx ");
11150 if((regs[i].dirty>>2)&1) printf("edx ");
11151 if((regs[i].dirty>>3)&1) printf("ebx ");
11152 if((regs[i].dirty>>5)&1) printf("ebp ");
11153 if((regs[i].dirty>>6)&1) printf("esi ");
11154 if((regs[i].dirty>>7)&1) printf("edi ");
11157 printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
11158 if(regs[i].dirty&1) printf("r0 ");
11159 if((regs[i].dirty>>1)&1) printf("r1 ");
11160 if((regs[i].dirty>>2)&1) printf("r2 ");
11161 if((regs[i].dirty>>3)&1) printf("r3 ");
11162 if((regs[i].dirty>>4)&1) printf("r4 ");
11163 if((regs[i].dirty>>5)&1) printf("r5 ");
11164 if((regs[i].dirty>>6)&1) printf("r6 ");
11165 if((regs[i].dirty>>7)&1) printf("r7 ");
11166 if((regs[i].dirty>>8)&1) printf("r8 ");
11167 if((regs[i].dirty>>9)&1) printf("r9 ");
11168 if((regs[i].dirty>>10)&1) printf("r10 ");
11169 if((regs[i].dirty>>12)&1) printf("r12 ");
11172 if(regs[i].isconst) {
11173 printf("constants: ");
11174 #if defined(__i386__) || defined(__x86_64__)
11175 if(regs[i].isconst&1) printf("eax=%x ",(int)constmap[i][0]);
11176 if((regs[i].isconst>>1)&1) printf("ecx=%x ",(int)constmap[i][1]);
11177 if((regs[i].isconst>>2)&1) printf("edx=%x ",(int)constmap[i][2]);
11178 if((regs[i].isconst>>3)&1) printf("ebx=%x ",(int)constmap[i][3]);
11179 if((regs[i].isconst>>5)&1) printf("ebp=%x ",(int)constmap[i][5]);
11180 if((regs[i].isconst>>6)&1) printf("esi=%x ",(int)constmap[i][6]);
11181 if((regs[i].isconst>>7)&1) printf("edi=%x ",(int)constmap[i][7]);
11184 if(regs[i].isconst&1) printf("r0=%x ",(int)constmap[i][0]);
11185 if((regs[i].isconst>>1)&1) printf("r1=%x ",(int)constmap[i][1]);
11186 if((regs[i].isconst>>2)&1) printf("r2=%x ",(int)constmap[i][2]);
11187 if((regs[i].isconst>>3)&1) printf("r3=%x ",(int)constmap[i][3]);
11188 if((regs[i].isconst>>4)&1) printf("r4=%x ",(int)constmap[i][4]);
11189 if((regs[i].isconst>>5)&1) printf("r5=%x ",(int)constmap[i][5]);
11190 if((regs[i].isconst>>6)&1) printf("r6=%x ",(int)constmap[i][6]);
11191 if((regs[i].isconst>>7)&1) printf("r7=%x ",(int)constmap[i][7]);
11192 if((regs[i].isconst>>8)&1) printf("r8=%x ",(int)constmap[i][8]);
11193 if((regs[i].isconst>>9)&1) printf("r9=%x ",(int)constmap[i][9]);
11194 if((regs[i].isconst>>10)&1) printf("r10=%x ",(int)constmap[i][10]);
11195 if((regs[i].isconst>>12)&1) printf("r12=%x ",(int)constmap[i][12]);
11201 for(r=0;r<=CCREG;r++) {
11202 if((regs[i].is32>>r)&1) {
11203 if(r==CCREG) printf(" CC");
11204 else if(r==HIREG) printf(" HI");
11205 else if(r==LOREG) printf(" LO");
11206 else printf(" r%d",r);
11212 for(r=0;r<=CCREG;r++) {
11213 if((p32[i]>>r)&1) {
11214 if(r==CCREG) printf(" CC");
11215 else if(r==HIREG) printf(" HI");
11216 else if(r==LOREG) printf(" LO");
11217 else printf(" r%d",r);
11220 if(p32[i]!=regs[i].is32) printf(" NO MATCH\n");
11221 else printf("\n");*/
11222 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
11223 #if defined(__i386__) || defined(__x86_64__)
11224 printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
11225 if(branch_regs[i].dirty&1) printf("eax ");
11226 if((branch_regs[i].dirty>>1)&1) printf("ecx ");
11227 if((branch_regs[i].dirty>>2)&1) printf("edx ");
11228 if((branch_regs[i].dirty>>3)&1) printf("ebx ");
11229 if((branch_regs[i].dirty>>5)&1) printf("ebp ");
11230 if((branch_regs[i].dirty>>6)&1) printf("esi ");
11231 if((branch_regs[i].dirty>>7)&1) printf("edi ");
11234 printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
11235 if(branch_regs[i].dirty&1) printf("r0 ");
11236 if((branch_regs[i].dirty>>1)&1) printf("r1 ");
11237 if((branch_regs[i].dirty>>2)&1) printf("r2 ");
11238 if((branch_regs[i].dirty>>3)&1) printf("r3 ");
11239 if((branch_regs[i].dirty>>4)&1) printf("r4 ");
11240 if((branch_regs[i].dirty>>5)&1) printf("r5 ");
11241 if((branch_regs[i].dirty>>6)&1) printf("r6 ");
11242 if((branch_regs[i].dirty>>7)&1) printf("r7 ");
11243 if((branch_regs[i].dirty>>8)&1) printf("r8 ");
11244 if((branch_regs[i].dirty>>9)&1) printf("r9 ");
11245 if((branch_regs[i].dirty>>10)&1) printf("r10 ");
11246 if((branch_regs[i].dirty>>12)&1) printf("r12 ");
11250 for(r=0;r<=CCREG;r++) {
11251 if((branch_regs[i].is32>>r)&1) {
11252 if(r==CCREG) printf(" CC");
11253 else if(r==HIREG) printf(" HI");
11254 else if(r==LOREG) printf(" LO");
11255 else printf(" r%d",r);
11264 /* Pass 8 - Assembly */
11265 linkcount=0;stubcount=0;
11266 ds=0;is_delayslot=0;
11268 uint64_t is32_pre=0;
11270 u_int beginning=(u_int)out;
11271 if((u_int)addr&1) {
11275 u_int instr_addr0_override=0;
11278 if (start == 0x80030000) {
11279 // nasty hack for fastbios thing
11280 // override block entry to this code
11281 instr_addr0_override=(u_int)out;
11282 emit_movimm(start,0);
11283 // abuse io address var as a flag that we
11284 // have already returned here once
11285 emit_readword((int)&address,1);
11286 emit_writeword(0,(int)&pcaddr);
11287 emit_writeword(0,(int)&address);
11289 emit_jne((int)new_dyna_leave);
11292 for(i=0;i<slen;i++)
11294 //if(ds) printf("ds: ");
11295 disassemble_inst(i);
11297 ds=0; // Skip delay slot
11298 if(bt[i]) assem_debug("OOPS - branch into delay slot\n");
11301 speculate_register_values(i);
11302 #ifndef DESTRUCTIVE_WRITEBACK
11303 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
11305 wb_sx(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,is32_pre,regs[i].was32,
11306 unneeded_reg[i],unneeded_reg_upper[i]);
11307 wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre,
11308 unneeded_reg[i],unneeded_reg_upper[i]);
11310 if((itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)&&!likely[i]) {
11311 is32_pre=branch_regs[i].is32;
11312 dirty_pre=branch_regs[i].dirty;
11314 is32_pre=regs[i].is32;
11315 dirty_pre=regs[i].dirty;
11319 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
11321 wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32,
11322 unneeded_reg[i],unneeded_reg_upper[i]);
11323 loop_preload(regmap_pre[i],regs[i].regmap_entry);
11325 // branch target entry point
11326 instr_addr[i]=(u_int)out;
11327 assem_debug("<->\n");
11329 if(regs[i].regmap_entry[HOST_CCREG]==CCREG&®s[i].regmap[HOST_CCREG]!=CCREG)
11330 wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32);
11331 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
11332 address_generation(i,®s[i],regs[i].regmap_entry);
11333 load_consts(regmap_pre[i],regs[i].regmap,regs[i].was32,i);
11334 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
11336 // Load the delay slot registers if necessary
11337 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i]&&(rs1[i+1]!=rt1[i]||rt1[i]==0))
11338 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
11339 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i]&&(rs2[i+1]!=rt1[i]||rt1[i]==0))
11340 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
11341 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a)
11342 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
11346 // Preload registers for following instruction
11347 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
11348 if(rs1[i+1]!=rt1[i]&&rs1[i+1]!=rt2[i])
11349 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
11350 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
11351 if(rs2[i+1]!=rt1[i]&&rs2[i+1]!=rt2[i])
11352 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
11354 // TODO: if(is_ooo(i)) address_generation(i+1);
11355 if(itype[i]==CJUMP||itype[i]==FJUMP)
11356 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
11357 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a)
11358 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
11359 if(bt[i]) cop1_usable=0;
11363 alu_assemble(i,®s[i]);break;
11365 imm16_assemble(i,®s[i]);break;
11367 shift_assemble(i,®s[i]);break;
11369 shiftimm_assemble(i,®s[i]);break;
11371 load_assemble(i,®s[i]);break;
11373 loadlr_assemble(i,®s[i]);break;
11375 store_assemble(i,®s[i]);break;
11377 storelr_assemble(i,®s[i]);break;
11379 cop0_assemble(i,®s[i]);break;
11381 cop1_assemble(i,®s[i]);break;
11383 c1ls_assemble(i,®s[i]);break;
11385 cop2_assemble(i,®s[i]);break;
11387 c2ls_assemble(i,®s[i]);break;
11389 c2op_assemble(i,®s[i]);break;
11391 fconv_assemble(i,®s[i]);break;
11393 float_assemble(i,®s[i]);break;
11395 fcomp_assemble(i,®s[i]);break;
11397 multdiv_assemble(i,®s[i]);break;
11399 mov_assemble(i,®s[i]);break;
11401 syscall_assemble(i,®s[i]);break;
11403 hlecall_assemble(i,®s[i]);break;
11405 intcall_assemble(i,®s[i]);break;
11407 ujump_assemble(i,®s[i]);ds=1;break;
11409 rjump_assemble(i,®s[i]);ds=1;break;
11411 cjump_assemble(i,®s[i]);ds=1;break;
11413 sjump_assemble(i,®s[i]);ds=1;break;
11415 fjump_assemble(i,®s[i]);ds=1;break;
11417 pagespan_assemble(i,®s[i]);break;
11419 if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
11420 literal_pool(1024);
11422 literal_pool_jumpover(256);
11425 //assert(itype[i-2]==UJUMP||itype[i-2]==RJUMP||(source[i-2]>>16)==0x1000);
11426 // If the block did not end with an unconditional branch,
11427 // add a jump to the next instruction.
11429 if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) {
11430 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
11432 if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP&&itype[i-2]!=FJUMP) {
11433 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
11434 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
11435 emit_loadreg(CCREG,HOST_CCREG);
11436 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG);
11438 else if(!likely[i-2])
11440 store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].is32,branch_regs[i-2].dirty,start+i*4);
11441 assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
11445 store_regs_bt(regs[i-2].regmap,regs[i-2].is32,regs[i-2].dirty,start+i*4);
11446 assert(regs[i-2].regmap[HOST_CCREG]==CCREG);
11448 add_to_linker((int)out,start+i*4,0);
11455 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
11456 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
11457 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
11458 emit_loadreg(CCREG,HOST_CCREG);
11459 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG);
11460 add_to_linker((int)out,start+i*4,0);
11464 // TODO: delay slot stubs?
11466 for(i=0;i<stubcount;i++)
11468 switch(stubs[i][0])
11476 do_readstub(i);break;
11481 do_writestub(i);break;
11483 do_ccstub(i);break;
11485 do_invstub(i);break;
11487 do_cop1stub(i);break;
11489 do_unalignedwritestub(i);break;
11493 if (instr_addr0_override)
11494 instr_addr[0] = instr_addr0_override;
11496 /* Pass 9 - Linker */
11497 for(i=0;i<linkcount;i++)
11499 assem_debug("%8x -> %8x\n",link_addr[i][0],link_addr[i][1]);
11501 if(!link_addr[i][2])
11504 void *addr=check_addr(link_addr[i][1]);
11505 emit_extjump(link_addr[i][0],link_addr[i][1]);
11507 set_jump_target(link_addr[i][0],(int)addr);
11508 add_link(link_addr[i][1],stub);
11510 else set_jump_target(link_addr[i][0],(int)stub);
11515 int target=(link_addr[i][1]-start)>>2;
11516 assert(target>=0&&target<slen);
11517 assert(instr_addr[target]);
11518 //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11519 //set_jump_target_fillslot(link_addr[i][0],instr_addr[target],link_addr[i][2]>>1);
11521 set_jump_target(link_addr[i][0],instr_addr[target]);
11525 // External Branch Targets (jump_in)
11526 if(copy+slen*4>(void *)shadow+sizeof(shadow)) copy=shadow;
11527 for(i=0;i<slen;i++)
11531 if(instr_addr[i]) // TODO - delay slots (=null)
11533 u_int vaddr=start+i*4;
11534 u_int page=get_page(vaddr);
11535 u_int vpage=get_vpage(vaddr);
11537 //if(!(is32[i]&(~unneeded_reg_upper[i])&~(1LL<<CCREG)))
11539 if(!requires_32bit[i])
11544 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
11545 assem_debug("jump_in: %x\n",start+i*4);
11546 ll_add(jump_dirty+vpage,vaddr,(void *)out);
11547 int entry_point=do_dirty_stub(i);
11548 ll_add(jump_in+page,vaddr,(void *)entry_point);
11549 // If there was an existing entry in the hash table,
11550 // replace it with the new address.
11551 // Don't add new entries. We'll insert the
11552 // ones that actually get used in check_addr().
11553 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
11554 if(ht_bin[0]==vaddr) {
11555 ht_bin[1]=entry_point;
11557 if(ht_bin[2]==vaddr) {
11558 ht_bin[3]=entry_point;
11563 u_int r=requires_32bit[i]|!!(requires_32bit[i]>>32);
11564 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
11565 assem_debug("jump_in: %x (restricted - %x)\n",start+i*4,r);
11566 //int entry_point=(int)out;
11567 ////assem_debug("entry_point: %x\n",entry_point);
11568 //load_regs_entry(i);
11569 //if(entry_point==(int)out)
11570 // entry_point=instr_addr[i];
11572 // emit_jmp(instr_addr[i]);
11573 //ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11574 ll_add_32(jump_dirty+vpage,vaddr,r,(void *)out);
11575 int entry_point=do_dirty_stub(i);
11576 ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11581 // Write out the literal pool if necessary
11583 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11585 if(((u_int)out)&7) emit_addnop(13);
11587 assert((u_int)out-beginning<MAX_OUTPUT_BLOCK_SIZE);
11588 //printf("shadow buffer: %x-%x\n",(int)copy,(int)copy+slen*4);
11589 memcpy(copy,source,slen*4);
11593 __clear_cache((void *)beginning,out);
11596 // If we're within 256K of the end of the buffer,
11597 // start over from the beginning. (Is 256K enough?)
11598 if((u_int)out>(u_int)BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR;
11600 // Trap writes to any of the pages we compiled
11601 for(i=start>>12;i<=(start+slen*4)>>12;i++) {
11603 #ifndef DISABLE_TLB
11604 memory_map[i]|=0x40000000;
11605 if((signed int)start>=(signed int)0xC0000000) {
11607 j=(((u_int)i<<12)+(memory_map[i]<<2)-(u_int)rdram+(u_int)0x80000000)>>12;
11609 memory_map[j]|=0x40000000;
11610 //printf("write protect physical page: %x (virtual %x)\n",j<<12,start);
11614 inv_code_start=inv_code_end=~0;
11616 // for PCSX we need to mark all mirrors too
11617 if(get_page(start)<(RAM_SIZE>>12))
11618 for(i=start>>12;i<=(start+slen*4)>>12;i++)
11619 invalid_code[((u_int)0x00000000>>12)|(i&0x1ff)]=
11620 invalid_code[((u_int)0x80000000>>12)|(i&0x1ff)]=
11621 invalid_code[((u_int)0xa0000000>>12)|(i&0x1ff)]=0;
11624 /* Pass 10 - Free memory by expiring oldest blocks */
11626 int end=((((int)out-(int)BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535;
11627 while(expirep!=end)
11629 int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
11630 int base=(int)BASE_ADDR+((expirep>>13)<<shift); // Base address of this block
11631 inv_debug("EXP: Phase %d\n",expirep);
11632 switch((expirep>>11)&3)
11635 // Clear jump_in and jump_dirty
11636 ll_remove_matching_addrs(jump_in+(expirep&2047),base,shift);
11637 ll_remove_matching_addrs(jump_dirty+(expirep&2047),base,shift);
11638 ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base,shift);
11639 ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base,shift);
11643 ll_kill_pointers(jump_out[expirep&2047],base,shift);
11644 ll_kill_pointers(jump_out[(expirep&2047)+2048],base,shift);
11647 // Clear hash table
11648 for(i=0;i<32;i++) {
11649 int *ht_bin=hash_table[((expirep&2047)<<5)+i];
11650 if((ht_bin[3]>>shift)==(base>>shift) ||
11651 ((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11652 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[2],ht_bin[3]);
11653 ht_bin[2]=ht_bin[3]=-1;
11655 if((ht_bin[1]>>shift)==(base>>shift) ||
11656 ((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11657 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[0],ht_bin[1]);
11658 ht_bin[0]=ht_bin[2];
11659 ht_bin[1]=ht_bin[3];
11660 ht_bin[2]=ht_bin[3]=-1;
11667 if((expirep&2047)==0)
11670 ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);
11671 ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base,shift);
11674 expirep=(expirep+1)&65535;
11679 // vim:shiftwidth=2:expandtab