1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
3 * Copyright (C) 2009-2011 Ari64 *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
22 #include <stdint.h> //include for uint64_t
27 #include <libkern/OSCacheControl.h>
30 #include <3ds_utils.h>
33 #include <psp2/kernel/sysmem.h>
37 #include "new_dynarec_config.h"
38 #include "../psxhle.h"
39 #include "../psxinterpreter.h"
41 #include "emu_if.h" // emulator interface
43 #define noinline __attribute__((noinline,noclone))
45 #define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
48 #define min(a, b) ((b) < (a) ? (b) : (a))
51 #define max(a, b) ((b) > (a) ? (b) : (a))
58 #define assem_debug printf
60 #define assem_debug(...)
62 //#define inv_debug printf
63 #define inv_debug(...)
66 #include "assem_x86.h"
69 #include "assem_x64.h"
72 #include "assem_arm.h"
75 #include "assem_arm64.h"
78 #define RAM_SIZE 0x200000
80 #define MAX_OUTPUT_BLOCK_SIZE 262144
84 u_char translation_cache[1 << TARGET_SIZE_2];
87 struct tramp_insns ops[2048 / sizeof(struct tramp_insns)];
88 const void *f[2048 / sizeof(void *)];
92 #ifdef BASE_ADDR_DYNAMIC
93 static struct ndrc_mem *ndrc;
95 static struct ndrc_mem ndrc_ __attribute__((aligned(4096)));
96 static struct ndrc_mem *ndrc = &ndrc_;
119 signed char regmap_entry[HOST_REGS]; // pre-insn + loop preloaded regs?
120 signed char regmap[HOST_REGS];
126 u_int loadedconst; // host regs that have constants loaded
127 u_int waswritten; // MIPS regs that were used as store base before
130 // note: asm depends on this layout
136 struct ll_entry *next;
164 static struct decoded_insn
185 struct ht_entry hash_table[65536] __attribute__((aligned(16)));
186 struct ll_entry *jump_in[4096] __attribute__((aligned(16)));
187 struct ll_entry *jump_dirty[4096];
189 static struct ll_entry *jump_out[4096];
191 static u_int *source;
192 static char insn[MAXBLOCK][10];
193 static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
194 static uint64_t gte_rt[MAXBLOCK];
195 static uint64_t gte_unneeded[MAXBLOCK];
196 static u_int smrv[32]; // speculated MIPS register values
197 static u_int smrv_strong; // mask or regs that are likely to have correct values
198 static u_int smrv_weak; // same, but somewhat less likely
199 static u_int smrv_strong_next; // same, but after current insn executes
200 static u_int smrv_weak_next;
201 static int imm[MAXBLOCK];
202 static u_int ba[MAXBLOCK];
203 static uint64_t unneeded_reg[MAXBLOCK];
204 static uint64_t branch_unneeded_reg[MAXBLOCK];
205 // pre-instruction [i], excluding loop-preload regs?
206 static signed char regmap_pre[MAXBLOCK][HOST_REGS];
207 // contains 'real' consts at [i] insn, but may differ from what's actually
208 // loaded in host reg as 'final' value is always loaded, see get_final_value()
209 static uint32_t current_constmap[HOST_REGS];
210 static uint32_t constmap[MAXBLOCK][HOST_REGS];
211 static struct regstat regs[MAXBLOCK];
212 static struct regstat branch_regs[MAXBLOCK];
213 static signed char minimum_free_regs[MAXBLOCK];
214 static u_int needed_reg[MAXBLOCK];
215 static u_int wont_dirty[MAXBLOCK];
216 static u_int will_dirty[MAXBLOCK];
217 static int ccadj[MAXBLOCK];
219 static void *instr_addr[MAXBLOCK];
220 static struct link_entry link_addr[MAXBLOCK];
221 static int linkcount;
222 static struct code_stub stubs[MAXBLOCK*3];
223 static int stubcount;
224 static u_int literals[1024][2];
225 static int literalcount;
226 static int is_delayslot;
227 static char shadow[1048576] __attribute__((aligned(16)));
230 static u_int stop_after_jal;
231 static u_int f1_hack; // 0 - off, ~0 - capture address, else addr
233 int new_dynarec_hacks;
234 int new_dynarec_hacks_pergame;
235 int new_dynarec_hacks_old;
236 int new_dynarec_did_compile;
238 #define HACK_ENABLED(x) ((new_dynarec_hacks | new_dynarec_hacks_pergame) & (x))
240 extern int cycle_count; // ... until end of the timeslice, counts -N -> 0
241 extern int last_count; // last absolute target, often = next_interupt
243 extern int pending_exception;
244 extern int branch_target;
245 extern uintptr_t ram_offset;
246 extern uintptr_t mini_ht[32][2];
247 extern u_char restore_candidate[512];
249 /* registers that may be allocated */
251 #define LOREG 32 // lo
252 #define HIREG 33 // hi
253 //#define FSREG 34 // FPU status (FCSR)
254 #define CSREG 35 // Coprocessor status
255 #define CCREG 36 // Cycle count
256 #define INVCP 37 // Pointer to invalid_code
257 //#define MMREG 38 // Pointer to memory_map
258 #define ROREG 39 // ram offset (if rdram!=0x80000000)
260 #define FTEMP 40 // FPU temporary register
261 #define PTEMP 41 // Prefetch temporary register
262 //#define TLREG 42 // TLB mapping offset
263 #define RHASH 43 // Return address hash
264 #define RHTBL 44 // Return address hash table address
265 #define RTEMP 45 // JR/JALR address register
267 #define AGEN1 46 // Address generation temporary register
268 //#define AGEN2 47 // Address generation temporary register
269 //#define MGEN1 48 // Maptable address generation temporary register
270 //#define MGEN2 49 // Maptable address generation temporary register
271 #define BTREG 50 // Branch target temporary register
273 /* instruction types */
274 #define NOP 0 // No operation
275 #define LOAD 1 // Load
276 #define STORE 2 // Store
277 #define LOADLR 3 // Unaligned load
278 #define STORELR 4 // Unaligned store
279 #define MOV 5 // Move
280 #define ALU 6 // Arithmetic/logic
281 #define MULTDIV 7 // Multiply/divide
282 #define SHIFT 8 // Shift by register
283 #define SHIFTIMM 9// Shift by immediate
284 #define IMM16 10 // 16-bit immediate
285 #define RJUMP 11 // Unconditional jump to register
286 #define UJUMP 12 // Unconditional jump
287 #define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
288 #define SJUMP 14 // Conditional branch (regimm format)
289 #define COP0 15 // Coprocessor 0
290 #define COP1 16 // Coprocessor 1
291 #define C1LS 17 // Coprocessor 1 load/store
292 //#define FJUMP 18 // Conditional branch (floating point)
293 //#define FLOAT 19 // Floating point unit
294 //#define FCONV 20 // Convert integer to float
295 //#define FCOMP 21 // Floating point compare (sets FSREG)
296 #define SYSCALL 22// SYSCALL
297 #define OTHER 23 // Other
298 #define SPAN 24 // Branch/delay slot spans 2 pages
299 #define NI 25 // Not implemented
300 #define HLECALL 26// PCSX fake opcodes for HLE
301 #define COP2 27 // Coprocessor 2 move
302 #define C2LS 28 // Coprocessor 2 load/store
303 #define C2OP 29 // Coprocessor 2 operation
304 #define INTCALL 30// Call interpreter to handle rare corner cases
311 #define DJT_1 (void *)1l // no function, just a label in assem_debug log
312 #define DJT_2 (void *)2l
315 int new_recompile_block(u_int addr);
316 void *get_addr_ht(u_int vaddr);
317 void invalidate_block(u_int block);
318 void invalidate_addr(u_int addr);
319 void remove_hash(int vaddr);
321 void dyna_linker_ds();
323 void verify_code_ds();
326 void fp_exception_ds();
327 void jump_to_new_pc();
328 void call_gteStall();
329 void new_dyna_leave();
331 // Needed by assembler
332 static void wb_register(signed char r, const signed char regmap[], uint64_t dirty);
333 static void wb_dirtys(const signed char i_regmap[], uint64_t i_dirty);
334 static void wb_needed_dirtys(const signed char i_regmap[], uint64_t i_dirty, int addr);
335 static void load_all_regs(const signed char i_regmap[]);
336 static void load_needed_regs(const signed char i_regmap[], const signed char next_regmap[]);
337 static void load_regs_entry(int t);
338 static void load_all_consts(const signed char regmap[], u_int dirty, int i);
339 static u_int get_host_reglist(const signed char *regmap);
341 static int verify_dirty(const u_int *ptr);
342 static int get_final_value(int hr, int i, int *value);
343 static void add_stub(enum stub_type type, void *addr, void *retaddr,
344 u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e);
345 static void add_stub_r(enum stub_type type, void *addr, void *retaddr,
346 int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist);
347 static void add_to_linker(void *addr, u_int target, int ext);
348 static void *emit_fastpath_cmp_jump(int i, const struct regstat *i_regs,
349 int addr, int *offset_reg, int *addr_reg_override);
350 static void *get_direct_memhandler(void *table, u_int addr,
351 enum stub_type type, uintptr_t *addr_host);
352 static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist);
353 static void pass_args(int a0, int a1);
354 static void emit_far_jump(const void *f);
355 static void emit_far_call(const void *f);
357 static void mprotect_w_x(void *start, void *end, int is_x)
361 // *Open* enables write on all memory that was
362 // allocated by sceKernelAllocMemBlockForVM()?
364 sceKernelCloseVMDomain();
366 sceKernelOpenVMDomain();
368 u_long mstart = (u_long)start & ~4095ul;
369 u_long mend = (u_long)end;
370 if (mprotect((void *)mstart, mend - mstart,
371 PROT_READ | (is_x ? PROT_EXEC : PROT_WRITE)) != 0)
372 SysPrintf("mprotect(%c) failed: %s\n", is_x ? 'x' : 'w', strerror(errno));
377 static void start_tcache_write(void *start, void *end)
379 mprotect_w_x(start, end, 0);
382 static void end_tcache_write(void *start, void *end)
384 #if defined(__arm__) || defined(__aarch64__)
385 size_t len = (char *)end - (char *)start;
386 #if defined(__BLACKBERRY_QNX__)
387 msync(start, len, MS_SYNC | MS_CACHE_ONLY | MS_INVALIDATE_ICACHE);
388 #elif defined(__MACH__)
389 sys_cache_control(kCacheFunctionPrepareForExecution, start, len);
391 sceKernelSyncVMDomain(sceBlock, start, len);
393 ctr_flush_invalidate_cache();
394 #elif defined(__aarch64__)
395 // as of 2021, __clear_cache() is still broken on arm64
396 // so here is a custom one :(
397 clear_cache_arm64(start, end);
399 __clear_cache(start, end);
404 mprotect_w_x(start, end, 1);
407 static void *start_block(void)
409 u_char *end = out + MAX_OUTPUT_BLOCK_SIZE;
410 if (end > ndrc->translation_cache + sizeof(ndrc->translation_cache))
411 end = ndrc->translation_cache + sizeof(ndrc->translation_cache);
412 start_tcache_write(out, end);
416 static void end_block(void *start)
418 end_tcache_write(start, out);
421 // also takes care of w^x mappings when patching code
422 static u_int needs_clear_cache[1<<(TARGET_SIZE_2-17)];
424 static void mark_clear_cache(void *target)
426 uintptr_t offset = (u_char *)target - ndrc->translation_cache;
427 u_int mask = 1u << ((offset >> 12) & 31);
428 if (!(needs_clear_cache[offset >> 17] & mask)) {
429 char *start = (char *)((uintptr_t)target & ~4095l);
430 start_tcache_write(start, start + 4095);
431 needs_clear_cache[offset >> 17] |= mask;
435 // Clearing the cache is rather slow on ARM Linux, so mark the areas
436 // that need to be cleared, and then only clear these areas once.
437 static void do_clear_cache(void)
440 for (i = 0; i < (1<<(TARGET_SIZE_2-17)); i++)
442 u_int bitmap = needs_clear_cache[i];
445 for (j = 0; j < 32; j++)
448 if (!(bitmap & (1<<j)))
451 start = ndrc->translation_cache + i*131072 + j*4096;
453 for (j++; j < 32; j++) {
454 if (!(bitmap & (1<<j)))
458 end_tcache_write(start, end);
460 needs_clear_cache[i] = 0;
464 //#define DEBUG_CYCLE_COUNT 1
466 #define NO_CYCLE_PENALTY_THR 12
468 int cycle_multiplier = CYCLE_MULT_DEFAULT; // 100 for 1.0
469 int cycle_multiplier_override;
470 int cycle_multiplier_old;
472 static int CLOCK_ADJUST(int x)
474 int m = cycle_multiplier_override && cycle_multiplier == CYCLE_MULT_DEFAULT
475 ? cycle_multiplier_override : cycle_multiplier;
477 return (x * m + s * 50) / 100;
480 static int ds_writes_rjump_rs(int i)
482 return dops[i].rs1 != 0 && (dops[i].rs1 == dops[i+1].rt1 || dops[i].rs1 == dops[i+1].rt2);
485 static u_int get_page(u_int vaddr)
487 u_int page=vaddr&~0xe0000000;
488 if (page < 0x1000000)
489 page &= ~0x0e00000; // RAM mirrors
491 if(page>2048) page=2048+(page&2047);
495 // no virtual mem in PCSX
496 static u_int get_vpage(u_int vaddr)
498 return get_page(vaddr);
501 static struct ht_entry *hash_table_get(u_int vaddr)
503 return &hash_table[((vaddr>>16)^vaddr)&0xFFFF];
506 static void hash_table_add(struct ht_entry *ht_bin, u_int vaddr, void *tcaddr)
508 ht_bin->vaddr[1] = ht_bin->vaddr[0];
509 ht_bin->tcaddr[1] = ht_bin->tcaddr[0];
510 ht_bin->vaddr[0] = vaddr;
511 ht_bin->tcaddr[0] = tcaddr;
514 // some messy ari64's code, seems to rely on unsigned 32bit overflow
515 static int doesnt_expire_soon(void *tcaddr)
517 u_int diff = (u_int)((u_char *)tcaddr - out) << (32-TARGET_SIZE_2);
518 return diff > (u_int)(0x60000000 + (MAX_OUTPUT_BLOCK_SIZE << (32-TARGET_SIZE_2)));
521 // Get address from virtual address
522 // This is called from the recompiled JR/JALR instructions
523 void noinline *get_addr(u_int vaddr)
525 u_int page=get_page(vaddr);
526 u_int vpage=get_vpage(vaddr);
527 struct ll_entry *head;
528 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
531 if(head->vaddr==vaddr) {
532 //printf("TRACE: count=%d next=%d (get_addr match %x: %p)\n",Count,next_interupt,vaddr,head->addr);
533 hash_table_add(hash_table_get(vaddr), vaddr, head->addr);
538 head=jump_dirty[vpage];
540 if(head->vaddr==vaddr) {
541 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %p)\n",Count,next_interupt,vaddr,head->addr);
542 // Don't restore blocks which are about to expire from the cache
543 if (doesnt_expire_soon(head->addr))
544 if (verify_dirty(head->addr)) {
545 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
546 invalid_code[vaddr>>12]=0;
547 inv_code_start=inv_code_end=~0;
549 restore_candidate[vpage>>3]|=1<<(vpage&7);
551 else restore_candidate[page>>3]|=1<<(page&7);
552 struct ht_entry *ht_bin = hash_table_get(vaddr);
553 if (ht_bin->vaddr[0] == vaddr)
554 ht_bin->tcaddr[0] = head->addr; // Replace existing entry
556 hash_table_add(ht_bin, vaddr, head->addr);
563 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
564 int r=new_recompile_block(vaddr);
565 if(r==0) return get_addr(vaddr);
566 // Execute in unmapped page, generate pagefault execption
568 Cause=(vaddr<<31)|0x8;
569 EPC=(vaddr&1)?vaddr-5:vaddr;
571 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
572 EntryHi=BadVAddr&0xFFFFE000;
573 return get_addr_ht(0x80000000);
575 // Look up address in hash table first
576 void *get_addr_ht(u_int vaddr)
578 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
579 const struct ht_entry *ht_bin = hash_table_get(vaddr);
580 if (ht_bin->vaddr[0] == vaddr) return ht_bin->tcaddr[0];
581 if (ht_bin->vaddr[1] == vaddr) return ht_bin->tcaddr[1];
582 return get_addr(vaddr);
585 void clear_all_regs(signed char regmap[])
588 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
591 static signed char get_reg(const signed char regmap[],int r)
594 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map[hr]==r) return hr;
598 // Find a register that is available for two consecutive cycles
599 static signed char get_reg2(signed char regmap1[], const signed char regmap2[], int r)
602 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map1[hr]==r&®map2[hr]==r) return hr;
606 int count_free_regs(signed char regmap[])
610 for(hr=0;hr<HOST_REGS;hr++)
612 if(hr!=EXCLUDE_REG) {
613 if(regmap[hr]<0) count++;
619 void dirty_reg(struct regstat *cur,signed char reg)
623 for (hr=0;hr<HOST_REGS;hr++) {
624 if((cur->regmap[hr]&63)==reg) {
630 static void set_const(struct regstat *cur, signed char reg, uint32_t value)
634 for (hr=0;hr<HOST_REGS;hr++) {
635 if(cur->regmap[hr]==reg) {
637 current_constmap[hr]=value;
642 static void clear_const(struct regstat *cur, signed char reg)
646 for (hr=0;hr<HOST_REGS;hr++) {
647 if((cur->regmap[hr]&63)==reg) {
648 cur->isconst&=~(1<<hr);
653 static int is_const(struct regstat *cur, signed char reg)
658 for (hr=0;hr<HOST_REGS;hr++) {
659 if((cur->regmap[hr]&63)==reg) {
660 return (cur->isconst>>hr)&1;
666 static uint32_t get_const(struct regstat *cur, signed char reg)
670 for (hr=0;hr<HOST_REGS;hr++) {
671 if(cur->regmap[hr]==reg) {
672 return current_constmap[hr];
675 SysPrintf("Unknown constant in r%d\n",reg);
679 // Least soon needed registers
680 // Look at the next ten instructions and see which registers
681 // will be used. Try not to reallocate these.
682 void lsn(u_char hsn[], int i, int *preferred_reg)
692 if (dops[i+j].is_ujump)
694 // Don't go past an unconditonal jump
701 if(dops[i+j].rs1) hsn[dops[i+j].rs1]=j;
702 if(dops[i+j].rs2) hsn[dops[i+j].rs2]=j;
703 if(dops[i+j].rt1) hsn[dops[i+j].rt1]=j;
704 if(dops[i+j].rt2) hsn[dops[i+j].rt2]=j;
705 if(dops[i+j].itype==STORE || dops[i+j].itype==STORELR) {
706 // Stores can allocate zero
707 hsn[dops[i+j].rs1]=j;
708 hsn[dops[i+j].rs2]=j;
710 if (ram_offset && (dops[i+j].is_load || dops[i+j].is_store))
712 // On some architectures stores need invc_ptr
713 #if defined(HOST_IMM8)
714 if (dops[i+j].is_store)
717 if(i+j>=0&&(dops[i+j].itype==UJUMP||dops[i+j].itype==CJUMP||dops[i+j].itype==SJUMP))
725 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
727 // Follow first branch
728 int t=(ba[i+b]-start)>>2;
729 j=7-b;if(t+j>=slen) j=slen-t-1;
732 if(dops[t+j].rs1) if(hsn[dops[t+j].rs1]>j+b+2) hsn[dops[t+j].rs1]=j+b+2;
733 if(dops[t+j].rs2) if(hsn[dops[t+j].rs2]>j+b+2) hsn[dops[t+j].rs2]=j+b+2;
734 //if(dops[t+j].rt1) if(hsn[dops[t+j].rt1]>j+b+2) hsn[dops[t+j].rt1]=j+b+2;
735 //if(dops[t+j].rt2) if(hsn[dops[t+j].rt2]>j+b+2) hsn[dops[t+j].rt2]=j+b+2;
738 // TODO: preferred register based on backward branch
740 // Delay slot should preferably not overwrite branch conditions or cycle count
741 if (i > 0 && dops[i-1].is_jump) {
742 if(dops[i-1].rs1) if(hsn[dops[i-1].rs1]>1) hsn[dops[i-1].rs1]=1;
743 if(dops[i-1].rs2) if(hsn[dops[i-1].rs2]>1) hsn[dops[i-1].rs2]=1;
749 // Coprocessor load/store needs FTEMP, even if not declared
750 if(dops[i].itype==C2LS) {
753 // Load L/R also uses FTEMP as a temporary register
754 if(dops[i].itype==LOADLR) {
757 // Also SWL/SWR/SDL/SDR
758 if(dops[i].opcode==0x2a||dops[i].opcode==0x2e||dops[i].opcode==0x2c||dops[i].opcode==0x2d) {
761 // Don't remove the miniht registers
762 if(dops[i].itype==UJUMP||dops[i].itype==RJUMP)
769 // We only want to allocate registers if we're going to use them again soon
770 int needed_again(int r, int i)
776 if (i > 0 && dops[i-1].is_ujump)
778 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
779 return 0; // Don't need any registers if exiting the block
787 if (dops[i+j].is_ujump)
789 // Don't go past an unconditonal jump
793 if(dops[i+j].itype==SYSCALL||dops[i+j].itype==HLECALL||dops[i+j].itype==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
800 if(dops[i+j].rs1==r) rn=j;
801 if(dops[i+j].rs2==r) rn=j;
802 if((unneeded_reg[i+j]>>r)&1) rn=10;
803 if(i+j>=0&&(dops[i+j].itype==UJUMP||dops[i+j].itype==CJUMP||dops[i+j].itype==SJUMP))
813 // Try to match register allocations at the end of a loop with those
815 int loop_reg(int i, int r, int hr)
824 if (dops[i+j].is_ujump)
826 // Don't go past an unconditonal jump
833 if(dops[i-1].itype==UJUMP||dops[i-1].itype==CJUMP||dops[i-1].itype==SJUMP)
839 if((unneeded_reg[i+k]>>r)&1) return hr;
840 if(i+k>=0&&(dops[i+k].itype==UJUMP||dops[i+k].itype==CJUMP||dops[i+k].itype==SJUMP))
842 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
844 int t=(ba[i+k]-start)>>2;
845 int reg=get_reg(regs[t].regmap_entry,r);
846 if(reg>=0) return reg;
847 //reg=get_reg(regs[t+1].regmap_entry,r);
848 //if(reg>=0) return reg;
856 // Allocate every register, preserving source/target regs
857 void alloc_all(struct regstat *cur,int i)
861 for(hr=0;hr<HOST_REGS;hr++) {
862 if(hr!=EXCLUDE_REG) {
863 if(((cur->regmap[hr]&63)!=dops[i].rs1)&&((cur->regmap[hr]&63)!=dops[i].rs2)&&
864 ((cur->regmap[hr]&63)!=dops[i].rt1)&&((cur->regmap[hr]&63)!=dops[i].rt2))
867 cur->dirty&=~(1<<hr);
870 if((cur->regmap[hr]&63)==0)
873 cur->dirty&=~(1<<hr);
880 static int host_tempreg_in_use;
882 static void host_tempreg_acquire(void)
884 assert(!host_tempreg_in_use);
885 host_tempreg_in_use = 1;
888 static void host_tempreg_release(void)
890 host_tempreg_in_use = 0;
893 static void host_tempreg_acquire(void) {}
894 static void host_tempreg_release(void) {}
898 extern void gen_interupt();
899 extern void do_insn_cmp();
900 #define FUNCNAME(f) { f, " " #f }
901 static const struct {
904 } function_names[] = {
905 FUNCNAME(cc_interrupt),
906 FUNCNAME(gen_interupt),
907 FUNCNAME(get_addr_ht),
909 FUNCNAME(jump_handler_read8),
910 FUNCNAME(jump_handler_read16),
911 FUNCNAME(jump_handler_read32),
912 FUNCNAME(jump_handler_write8),
913 FUNCNAME(jump_handler_write16),
914 FUNCNAME(jump_handler_write32),
915 FUNCNAME(invalidate_addr),
916 FUNCNAME(jump_to_new_pc),
917 FUNCNAME(call_gteStall),
918 FUNCNAME(new_dyna_leave),
920 FUNCNAME(pcsx_mtc0_ds),
922 FUNCNAME(do_insn_cmp),
925 FUNCNAME(verify_code),
929 static const char *func_name(const void *a)
932 for (i = 0; i < sizeof(function_names)/sizeof(function_names[0]); i++)
933 if (function_names[i].addr == a)
934 return function_names[i].name;
938 #define func_name(x) ""
942 #include "assem_x86.c"
945 #include "assem_x64.c"
948 #include "assem_arm.c"
951 #include "assem_arm64.c"
954 static void *get_trampoline(const void *f)
958 for (i = 0; i < ARRAY_SIZE(ndrc->tramp.f); i++) {
959 if (ndrc->tramp.f[i] == f || ndrc->tramp.f[i] == NULL)
962 if (i == ARRAY_SIZE(ndrc->tramp.f)) {
963 SysPrintf("trampoline table is full, last func %p\n", f);
966 if (ndrc->tramp.f[i] == NULL) {
967 start_tcache_write(&ndrc->tramp.f[i], &ndrc->tramp.f[i + 1]);
968 ndrc->tramp.f[i] = f;
969 end_tcache_write(&ndrc->tramp.f[i], &ndrc->tramp.f[i + 1]);
971 return &ndrc->tramp.ops[i];
974 static void emit_far_jump(const void *f)
976 if (can_jump_or_call(f)) {
981 f = get_trampoline(f);
985 static void emit_far_call(const void *f)
987 if (can_jump_or_call(f)) {
992 f = get_trampoline(f);
996 // Add virtual address mapping to linked list
997 void ll_add(struct ll_entry **head,int vaddr,void *addr)
999 struct ll_entry *new_entry;
1000 new_entry=malloc(sizeof(struct ll_entry));
1001 assert(new_entry!=NULL);
1002 new_entry->vaddr=vaddr;
1003 new_entry->reg_sv_flags=0;
1004 new_entry->addr=addr;
1005 new_entry->next=*head;
1009 void ll_add_flags(struct ll_entry **head,int vaddr,u_int reg_sv_flags,void *addr)
1011 ll_add(head,vaddr,addr);
1012 (*head)->reg_sv_flags=reg_sv_flags;
1015 // Check if an address is already compiled
1016 // but don't return addresses which are about to expire from the cache
1017 void *check_addr(u_int vaddr)
1019 struct ht_entry *ht_bin = hash_table_get(vaddr);
1021 for (i = 0; i < ARRAY_SIZE(ht_bin->vaddr); i++) {
1022 if (ht_bin->vaddr[i] == vaddr)
1023 if (doesnt_expire_soon((u_char *)ht_bin->tcaddr[i] - MAX_OUTPUT_BLOCK_SIZE))
1024 if (isclean(ht_bin->tcaddr[i]))
1025 return ht_bin->tcaddr[i];
1027 u_int page=get_page(vaddr);
1028 struct ll_entry *head;
1030 while (head != NULL) {
1031 if (head->vaddr == vaddr) {
1032 if (doesnt_expire_soon(head->addr)) {
1033 // Update existing entry with current address
1034 if (ht_bin->vaddr[0] == vaddr) {
1035 ht_bin->tcaddr[0] = head->addr;
1038 if (ht_bin->vaddr[1] == vaddr) {
1039 ht_bin->tcaddr[1] = head->addr;
1042 // Insert into hash table with low priority.
1043 // Don't evict existing entries, as they are probably
1044 // addresses that are being accessed frequently.
1045 if (ht_bin->vaddr[0] == -1) {
1046 ht_bin->vaddr[0] = vaddr;
1047 ht_bin->tcaddr[0] = head->addr;
1049 else if (ht_bin->vaddr[1] == -1) {
1050 ht_bin->vaddr[1] = vaddr;
1051 ht_bin->tcaddr[1] = head->addr;
1061 void remove_hash(int vaddr)
1063 //printf("remove hash: %x\n",vaddr);
1064 struct ht_entry *ht_bin = hash_table_get(vaddr);
1065 if (ht_bin->vaddr[1] == vaddr) {
1066 ht_bin->vaddr[1] = -1;
1067 ht_bin->tcaddr[1] = NULL;
1069 if (ht_bin->vaddr[0] == vaddr) {
1070 ht_bin->vaddr[0] = ht_bin->vaddr[1];
1071 ht_bin->tcaddr[0] = ht_bin->tcaddr[1];
1072 ht_bin->vaddr[1] = -1;
1073 ht_bin->tcaddr[1] = NULL;
1077 static void ll_remove_matching_addrs(struct ll_entry **head,
1078 uintptr_t base_offs_s, int shift)
1080 struct ll_entry *next;
1082 uintptr_t o1 = (u_char *)(*head)->addr - ndrc->translation_cache;
1083 uintptr_t o2 = o1 - MAX_OUTPUT_BLOCK_SIZE;
1084 if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s)
1086 inv_debug("EXP: Remove pointer to %p (%x)\n",(*head)->addr,(*head)->vaddr);
1087 remove_hash((*head)->vaddr);
1094 head=&((*head)->next);
1099 // Remove all entries from linked list
1100 void ll_clear(struct ll_entry **head)
1102 struct ll_entry *cur;
1103 struct ll_entry *next;
1114 // Dereference the pointers and remove if it matches
1115 static void ll_kill_pointers(struct ll_entry *head,
1116 uintptr_t base_offs_s, int shift)
1119 u_char *ptr = get_pointer(head->addr);
1120 uintptr_t o1 = ptr - ndrc->translation_cache;
1121 uintptr_t o2 = o1 - MAX_OUTPUT_BLOCK_SIZE;
1122 inv_debug("EXP: Lookup pointer to %p at %p (%x)\n",ptr,head->addr,head->vaddr);
1123 if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s)
1125 inv_debug("EXP: Kill pointer at %p (%x)\n",head->addr,head->vaddr);
1126 void *host_addr=find_extjump_insn(head->addr);
1127 mark_clear_cache(host_addr);
1128 set_jump_target(host_addr, head->addr);
1134 // This is called when we write to a compiled block (see do_invstub)
1135 static void invalidate_page(u_int page)
1137 struct ll_entry *head;
1138 struct ll_entry *next;
1142 inv_debug("INVALIDATE: %x\n",head->vaddr);
1143 remove_hash(head->vaddr);
1148 head=jump_out[page];
1151 inv_debug("INVALIDATE: kill pointer to %x (%p)\n",head->vaddr,head->addr);
1152 void *host_addr=find_extjump_insn(head->addr);
1153 mark_clear_cache(host_addr);
1154 set_jump_target(host_addr, head->addr); // point back to dyna_linker
1161 static void invalidate_block_range(u_int block, u_int first, u_int last)
1163 u_int page=get_page(block<<12);
1164 //printf("first=%d last=%d\n",first,last);
1165 invalidate_page(page);
1166 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1167 assert(last<page+5);
1168 // Invalidate the adjacent pages if a block crosses a 4K boundary
1170 invalidate_page(first);
1173 for(first=page+1;first<last;first++) {
1174 invalidate_page(first);
1178 // Don't trap writes
1179 invalid_code[block]=1;
1182 memset(mini_ht,-1,sizeof(mini_ht));
1186 void invalidate_block(u_int block)
1188 u_int page=get_page(block<<12);
1189 u_int vpage=get_vpage(block<<12);
1190 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1191 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1194 struct ll_entry *head;
1195 head=jump_dirty[vpage];
1196 //printf("page=%d vpage=%d\n",page,vpage);
1198 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1199 u_char *start, *end;
1200 get_bounds(head->addr, &start, &end);
1201 //printf("start: %p end: %p\n", start, end);
1202 if (page < 2048 && start >= rdram && end < rdram+RAM_SIZE) {
1203 if (((start-rdram)>>12) <= page && ((end-1-rdram)>>12) >= page) {
1204 if ((((start-rdram)>>12)&2047) < first) first = ((start-rdram)>>12)&2047;
1205 if ((((end-1-rdram)>>12)&2047) > last) last = ((end-1-rdram)>>12)&2047;
1211 invalidate_block_range(block,first,last);
1214 void invalidate_addr(u_int addr)
1217 // this check is done by the caller
1218 //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
1219 u_int page=get_vpage(addr);
1220 if(page<2048) { // RAM
1221 struct ll_entry *head;
1222 u_int addr_min=~0, addr_max=0;
1223 u_int mask=RAM_SIZE-1;
1224 u_int addr_main=0x80000000|(addr&mask);
1226 inv_code_start=addr_main&~0xfff;
1227 inv_code_end=addr_main|0xfff;
1230 // must check previous page too because of spans..
1232 inv_code_start-=0x1000;
1234 for(;pg1<=page;pg1++) {
1235 for(head=jump_dirty[pg1];head!=NULL;head=head->next) {
1236 u_char *start_h, *end_h;
1238 get_bounds(head->addr, &start_h, &end_h);
1239 start = (uintptr_t)start_h - ram_offset;
1240 end = (uintptr_t)end_h - ram_offset;
1241 if(start<=addr_main&&addr_main<end) {
1242 if(start<addr_min) addr_min=start;
1243 if(end>addr_max) addr_max=end;
1245 else if(addr_main<start) {
1246 if(start<inv_code_end)
1247 inv_code_end=start-1;
1250 if(end>inv_code_start)
1256 inv_debug("INV ADDR: %08x hit %08x-%08x\n", addr, addr_min, addr_max);
1257 inv_code_start=inv_code_end=~0;
1258 invalidate_block_range(addr>>12,(addr_min&mask)>>12,(addr_max&mask)>>12);
1262 inv_code_start=(addr&~mask)|(inv_code_start&mask);
1263 inv_code_end=(addr&~mask)|(inv_code_end&mask);
1264 inv_debug("INV ADDR: %08x miss, inv %08x-%08x, sk %d\n", addr, inv_code_start, inv_code_end, 0);
1268 invalidate_block(addr>>12);
1271 // This is called when loading a save state.
1272 // Anything could have changed, so invalidate everything.
1273 void invalidate_all_pages(void)
1276 for(page=0;page<4096;page++)
1277 invalidate_page(page);
1278 for(page=0;page<1048576;page++)
1279 if(!invalid_code[page]) {
1280 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1281 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1284 memset(mini_ht,-1,sizeof(mini_ht));
1289 static void do_invstub(int n)
1292 u_int reglist=stubs[n].a;
1293 set_jump_target(stubs[n].addr, out);
1295 if(stubs[n].b!=0) emit_mov(stubs[n].b,0);
1296 emit_far_call(invalidate_addr);
1297 restore_regs(reglist);
1298 emit_jmp(stubs[n].retaddr); // return address
1301 // Add an entry to jump_out after making a link
1302 // src should point to code by emit_extjump2()
1303 void add_jump_out(u_int vaddr,void *src)
1305 u_int page=get_page(vaddr);
1306 inv_debug("add_jump_out: %p -> %x (%d)\n",src,vaddr,page);
1307 check_extjump2(src);
1308 ll_add(jump_out+page,vaddr,src);
1309 //inv_debug("add_jump_out: to %p\n",get_pointer(src));
1312 // If a code block was found to be unmodified (bit was set in
1313 // restore_candidate) and it remains unmodified (bit is clear
1314 // in invalid_code) then move the entries for that 4K page from
1315 // the dirty list to the clean list.
1316 void clean_blocks(u_int page)
1318 struct ll_entry *head;
1319 inv_debug("INV: clean_blocks page=%d\n",page);
1320 head=jump_dirty[page];
1322 if(!invalid_code[head->vaddr>>12]) {
1323 // Don't restore blocks which are about to expire from the cache
1324 if (doesnt_expire_soon(head->addr)) {
1325 if(verify_dirty(head->addr)) {
1326 u_char *start, *end;
1327 //printf("Possibly Restore %x (%p)\n",head->vaddr, head->addr);
1330 get_bounds(head->addr, &start, &end);
1331 if (start - rdram < RAM_SIZE) {
1332 for (i = (start-rdram+0x80000000)>>12; i <= (end-1-rdram+0x80000000)>>12; i++) {
1333 inv|=invalid_code[i];
1336 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
1340 void *clean_addr = get_clean_addr(head->addr);
1341 if (doesnt_expire_soon(clean_addr)) {
1343 inv_debug("INV: Restored %x (%p/%p)\n",head->vaddr, head->addr, clean_addr);
1344 //printf("page=%x, addr=%x\n",page,head->vaddr);
1345 //assert(head->vaddr>>12==(page|0x80000));
1346 ll_add_flags(jump_in+ppage,head->vaddr,head->reg_sv_flags,clean_addr);
1347 struct ht_entry *ht_bin = hash_table_get(head->vaddr);
1348 if (ht_bin->vaddr[0] == head->vaddr)
1349 ht_bin->tcaddr[0] = clean_addr; // Replace existing entry
1350 if (ht_bin->vaddr[1] == head->vaddr)
1351 ht_bin->tcaddr[1] = clean_addr; // Replace existing entry
1361 /* Register allocation */
1363 // Note: registers are allocated clean (unmodified state)
1364 // if you intend to modify the register, you must call dirty_reg().
1365 static void alloc_reg(struct regstat *cur,int i,signed char reg)
1368 int preferred_reg = PREFERRED_REG_FIRST
1369 + reg % (PREFERRED_REG_LAST - PREFERRED_REG_FIRST + 1);
1370 if (reg == CCREG) preferred_reg = HOST_CCREG;
1371 if (reg == PTEMP || reg == FTEMP) preferred_reg = 12;
1372 assert(PREFERRED_REG_FIRST != EXCLUDE_REG && EXCLUDE_REG != HOST_REGS);
1374 // Don't allocate unused registers
1375 if((cur->u>>reg)&1) return;
1377 // see if it's already allocated
1378 for(hr=0;hr<HOST_REGS;hr++)
1380 if(cur->regmap[hr]==reg) return;
1383 // Keep the same mapping if the register was already allocated in a loop
1384 preferred_reg = loop_reg(i,reg,preferred_reg);
1386 // Try to allocate the preferred register
1387 if(cur->regmap[preferred_reg]==-1) {
1388 cur->regmap[preferred_reg]=reg;
1389 cur->dirty&=~(1<<preferred_reg);
1390 cur->isconst&=~(1<<preferred_reg);
1393 r=cur->regmap[preferred_reg];
1396 cur->regmap[preferred_reg]=reg;
1397 cur->dirty&=~(1<<preferred_reg);
1398 cur->isconst&=~(1<<preferred_reg);
1402 // Clear any unneeded registers
1403 // We try to keep the mapping consistent, if possible, because it
1404 // makes branches easier (especially loops). So we try to allocate
1405 // first (see above) before removing old mappings. If this is not
1406 // possible then go ahead and clear out the registers that are no
1408 for(hr=0;hr<HOST_REGS;hr++)
1413 if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
1417 // Try to allocate any available register, but prefer
1418 // registers that have not been used recently.
1420 for (hr = PREFERRED_REG_FIRST; ; ) {
1421 if (cur->regmap[hr] < 0) {
1422 int oldreg = regs[i-1].regmap[hr];
1423 if (oldreg < 0 || (oldreg != dops[i-1].rs1 && oldreg != dops[i-1].rs2
1424 && oldreg != dops[i-1].rt1 && oldreg != dops[i-1].rt2))
1426 cur->regmap[hr]=reg;
1427 cur->dirty&=~(1<<hr);
1428 cur->isconst&=~(1<<hr);
1433 if (hr == EXCLUDE_REG)
1435 if (hr == HOST_REGS)
1437 if (hr == PREFERRED_REG_FIRST)
1442 // Try to allocate any available register
1443 for (hr = PREFERRED_REG_FIRST; ; ) {
1444 if (cur->regmap[hr] < 0) {
1445 cur->regmap[hr]=reg;
1446 cur->dirty&=~(1<<hr);
1447 cur->isconst&=~(1<<hr);
1451 if (hr == EXCLUDE_REG)
1453 if (hr == HOST_REGS)
1455 if (hr == PREFERRED_REG_FIRST)
1459 // Ok, now we have to evict someone
1460 // Pick a register we hopefully won't need soon
1461 u_char hsn[MAXREG+1];
1462 memset(hsn,10,sizeof(hsn));
1464 lsn(hsn,i,&preferred_reg);
1465 //printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",cur->regmap[0],cur->regmap[1],cur->regmap[2],cur->regmap[3],cur->regmap[5],cur->regmap[6],cur->regmap[7]);
1466 //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
1468 // Don't evict the cycle count at entry points, otherwise the entry
1469 // stub will have to write it.
1470 if(dops[i].bt&&hsn[CCREG]>2) hsn[CCREG]=2;
1471 if (i>1 && hsn[CCREG] > 2 && dops[i-2].is_jump) hsn[CCREG]=2;
1474 // Alloc preferred register if available
1475 if(hsn[r=cur->regmap[preferred_reg]&63]==j) {
1476 for(hr=0;hr<HOST_REGS;hr++) {
1477 // Evict both parts of a 64-bit register
1478 if((cur->regmap[hr]&63)==r) {
1480 cur->dirty&=~(1<<hr);
1481 cur->isconst&=~(1<<hr);
1484 cur->regmap[preferred_reg]=reg;
1487 for(r=1;r<=MAXREG;r++)
1489 if(hsn[r]==j&&r!=dops[i-1].rs1&&r!=dops[i-1].rs2&&r!=dops[i-1].rt1&&r!=dops[i-1].rt2) {
1490 for(hr=0;hr<HOST_REGS;hr++) {
1491 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
1492 if(cur->regmap[hr]==r) {
1493 cur->regmap[hr]=reg;
1494 cur->dirty&=~(1<<hr);
1495 cur->isconst&=~(1<<hr);
1506 for(r=1;r<=MAXREG;r++)
1509 for(hr=0;hr<HOST_REGS;hr++) {
1510 if(cur->regmap[hr]==r) {
1511 cur->regmap[hr]=reg;
1512 cur->dirty&=~(1<<hr);
1513 cur->isconst&=~(1<<hr);
1520 SysPrintf("This shouldn't happen (alloc_reg)");abort();
1523 // Allocate a temporary register. This is done without regard to
1524 // dirty status or whether the register we request is on the unneeded list
1525 // Note: This will only allocate one register, even if called multiple times
1526 static void alloc_reg_temp(struct regstat *cur,int i,signed char reg)
1529 int preferred_reg = -1;
1531 // see if it's already allocated
1532 for(hr=0;hr<HOST_REGS;hr++)
1534 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==reg) return;
1537 // Try to allocate any available register
1538 for(hr=HOST_REGS-1;hr>=0;hr--) {
1539 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
1540 cur->regmap[hr]=reg;
1541 cur->dirty&=~(1<<hr);
1542 cur->isconst&=~(1<<hr);
1547 // Find an unneeded register
1548 for(hr=HOST_REGS-1;hr>=0;hr--)
1554 if(i==0||((unneeded_reg[i-1]>>r)&1)) {
1555 cur->regmap[hr]=reg;
1556 cur->dirty&=~(1<<hr);
1557 cur->isconst&=~(1<<hr);
1564 // Ok, now we have to evict someone
1565 // Pick a register we hopefully won't need soon
1566 // TODO: we might want to follow unconditional jumps here
1567 // TODO: get rid of dupe code and make this into a function
1568 u_char hsn[MAXREG+1];
1569 memset(hsn,10,sizeof(hsn));
1571 lsn(hsn,i,&preferred_reg);
1572 //printf("hsn: %d %d %d %d %d %d %d\n",hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
1574 // Don't evict the cycle count at entry points, otherwise the entry
1575 // stub will have to write it.
1576 if(dops[i].bt&&hsn[CCREG]>2) hsn[CCREG]=2;
1577 if (i>1 && hsn[CCREG] > 2 && dops[i-2].is_jump) hsn[CCREG]=2;
1580 for(r=1;r<=MAXREG;r++)
1582 if(hsn[r]==j&&r!=dops[i-1].rs1&&r!=dops[i-1].rs2&&r!=dops[i-1].rt1&&r!=dops[i-1].rt2) {
1583 for(hr=0;hr<HOST_REGS;hr++) {
1584 if(hr!=HOST_CCREG||hsn[CCREG]>2) {
1585 if(cur->regmap[hr]==r) {
1586 cur->regmap[hr]=reg;
1587 cur->dirty&=~(1<<hr);
1588 cur->isconst&=~(1<<hr);
1599 for(r=1;r<=MAXREG;r++)
1602 for(hr=0;hr<HOST_REGS;hr++) {
1603 if(cur->regmap[hr]==r) {
1604 cur->regmap[hr]=reg;
1605 cur->dirty&=~(1<<hr);
1606 cur->isconst&=~(1<<hr);
1613 SysPrintf("This shouldn't happen");abort();
1616 static void mov_alloc(struct regstat *current,int i)
1618 if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) {
1619 // logically this is needed but just won't work, no idea why
1620 //alloc_cc(current,i); // for stalls
1621 //dirty_reg(current,CCREG);
1624 // Note: Don't need to actually alloc the source registers
1625 //alloc_reg(current,i,dops[i].rs1);
1626 alloc_reg(current,i,dops[i].rt1);
1628 clear_const(current,dops[i].rs1);
1629 clear_const(current,dops[i].rt1);
1630 dirty_reg(current,dops[i].rt1);
1633 static void shiftimm_alloc(struct regstat *current,int i)
1635 if(dops[i].opcode2<=0x3) // SLL/SRL/SRA
1638 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1639 else dops[i].lt1=dops[i].rs1;
1640 alloc_reg(current,i,dops[i].rt1);
1641 dirty_reg(current,dops[i].rt1);
1642 if(is_const(current,dops[i].rs1)) {
1643 int v=get_const(current,dops[i].rs1);
1644 if(dops[i].opcode2==0x00) set_const(current,dops[i].rt1,v<<imm[i]);
1645 if(dops[i].opcode2==0x02) set_const(current,dops[i].rt1,(u_int)v>>imm[i]);
1646 if(dops[i].opcode2==0x03) set_const(current,dops[i].rt1,v>>imm[i]);
1648 else clear_const(current,dops[i].rt1);
1653 clear_const(current,dops[i].rs1);
1654 clear_const(current,dops[i].rt1);
1657 if(dops[i].opcode2>=0x38&&dops[i].opcode2<=0x3b) // DSLL/DSRL/DSRA
1661 if(dops[i].opcode2==0x3c) // DSLL32
1665 if(dops[i].opcode2==0x3e) // DSRL32
1669 if(dops[i].opcode2==0x3f) // DSRA32
1675 static void shift_alloc(struct regstat *current,int i)
1678 if(dops[i].opcode2<=0x07) // SLLV/SRLV/SRAV
1680 if(dops[i].rs1) alloc_reg(current,i,dops[i].rs1);
1681 if(dops[i].rs2) alloc_reg(current,i,dops[i].rs2);
1682 alloc_reg(current,i,dops[i].rt1);
1683 if(dops[i].rt1==dops[i].rs2) {
1684 alloc_reg_temp(current,i,-1);
1685 minimum_free_regs[i]=1;
1687 } else { // DSLLV/DSRLV/DSRAV
1690 clear_const(current,dops[i].rs1);
1691 clear_const(current,dops[i].rs2);
1692 clear_const(current,dops[i].rt1);
1693 dirty_reg(current,dops[i].rt1);
1697 static void alu_alloc(struct regstat *current,int i)
1699 if(dops[i].opcode2>=0x20&&dops[i].opcode2<=0x23) { // ADD/ADDU/SUB/SUBU
1701 if(dops[i].rs1&&dops[i].rs2) {
1702 alloc_reg(current,i,dops[i].rs1);
1703 alloc_reg(current,i,dops[i].rs2);
1706 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1707 if(dops[i].rs2&&needed_again(dops[i].rs2,i)) alloc_reg(current,i,dops[i].rs2);
1709 alloc_reg(current,i,dops[i].rt1);
1712 if(dops[i].opcode2==0x2a||dops[i].opcode2==0x2b) { // SLT/SLTU
1714 alloc_reg(current,i,dops[i].rs1);
1715 alloc_reg(current,i,dops[i].rs2);
1716 alloc_reg(current,i,dops[i].rt1);
1719 if(dops[i].opcode2>=0x24&&dops[i].opcode2<=0x27) { // AND/OR/XOR/NOR
1721 if(dops[i].rs1&&dops[i].rs2) {
1722 alloc_reg(current,i,dops[i].rs1);
1723 alloc_reg(current,i,dops[i].rs2);
1727 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1728 if(dops[i].rs2&&needed_again(dops[i].rs2,i)) alloc_reg(current,i,dops[i].rs2);
1730 alloc_reg(current,i,dops[i].rt1);
1733 if(dops[i].opcode2>=0x2c&&dops[i].opcode2<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1736 clear_const(current,dops[i].rs1);
1737 clear_const(current,dops[i].rs2);
1738 clear_const(current,dops[i].rt1);
1739 dirty_reg(current,dops[i].rt1);
1742 static void imm16_alloc(struct regstat *current,int i)
1744 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1745 else dops[i].lt1=dops[i].rs1;
1746 if(dops[i].rt1) alloc_reg(current,i,dops[i].rt1);
1747 if(dops[i].opcode==0x18||dops[i].opcode==0x19) { // DADDI/DADDIU
1750 else if(dops[i].opcode==0x0a||dops[i].opcode==0x0b) { // SLTI/SLTIU
1751 clear_const(current,dops[i].rs1);
1752 clear_const(current,dops[i].rt1);
1754 else if(dops[i].opcode>=0x0c&&dops[i].opcode<=0x0e) { // ANDI/ORI/XORI
1755 if(is_const(current,dops[i].rs1)) {
1756 int v=get_const(current,dops[i].rs1);
1757 if(dops[i].opcode==0x0c) set_const(current,dops[i].rt1,v&imm[i]);
1758 if(dops[i].opcode==0x0d) set_const(current,dops[i].rt1,v|imm[i]);
1759 if(dops[i].opcode==0x0e) set_const(current,dops[i].rt1,v^imm[i]);
1761 else clear_const(current,dops[i].rt1);
1763 else if(dops[i].opcode==0x08||dops[i].opcode==0x09) { // ADDI/ADDIU
1764 if(is_const(current,dops[i].rs1)) {
1765 int v=get_const(current,dops[i].rs1);
1766 set_const(current,dops[i].rt1,v+imm[i]);
1768 else clear_const(current,dops[i].rt1);
1771 set_const(current,dops[i].rt1,imm[i]<<16); // LUI
1773 dirty_reg(current,dops[i].rt1);
1776 static void load_alloc(struct regstat *current,int i)
1778 clear_const(current,dops[i].rt1);
1779 //if(dops[i].rs1!=dops[i].rt1&&needed_again(dops[i].rs1,i)) clear_const(current,dops[i].rs1); // Does this help or hurt?
1780 if(!dops[i].rs1) current->u&=~1LL; // Allow allocating r0 if it's the source register
1781 if (needed_again(dops[i].rs1, i))
1782 alloc_reg(current, i, dops[i].rs1);
1784 alloc_reg(current, i, ROREG);
1785 if(dops[i].rt1&&!((current->u>>dops[i].rt1)&1)) {
1786 alloc_reg(current,i,dops[i].rt1);
1787 assert(get_reg(current->regmap,dops[i].rt1)>=0);
1788 if(dops[i].opcode==0x27||dops[i].opcode==0x37) // LWU/LD
1792 else if(dops[i].opcode==0x1A||dops[i].opcode==0x1B) // LDL/LDR
1796 dirty_reg(current,dops[i].rt1);
1797 // LWL/LWR need a temporary register for the old value
1798 if(dops[i].opcode==0x22||dops[i].opcode==0x26)
1800 alloc_reg(current,i,FTEMP);
1801 alloc_reg_temp(current,i,-1);
1802 minimum_free_regs[i]=1;
1807 // Load to r0 or unneeded register (dummy load)
1808 // but we still need a register to calculate the address
1809 if(dops[i].opcode==0x22||dops[i].opcode==0x26)
1811 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1813 alloc_reg_temp(current,i,-1);
1814 minimum_free_regs[i]=1;
1815 if(dops[i].opcode==0x1A||dops[i].opcode==0x1B) // LDL/LDR
1822 void store_alloc(struct regstat *current,int i)
1824 clear_const(current,dops[i].rs2);
1825 if(!(dops[i].rs2)) current->u&=~1LL; // Allow allocating r0 if necessary
1826 if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1827 alloc_reg(current,i,dops[i].rs2);
1828 if(dops[i].opcode==0x2c||dops[i].opcode==0x2d||dops[i].opcode==0x3f) { // 64-bit SDL/SDR/SD
1832 alloc_reg(current, i, ROREG);
1833 #if defined(HOST_IMM8)
1834 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1835 alloc_reg(current, i, INVCP);
1837 if(dops[i].opcode==0x2a||dops[i].opcode==0x2e||dops[i].opcode==0x2c||dops[i].opcode==0x2d) { // SWL/SWL/SDL/SDR
1838 alloc_reg(current,i,FTEMP);
1840 // We need a temporary register for address generation
1841 alloc_reg_temp(current,i,-1);
1842 minimum_free_regs[i]=1;
1845 void c1ls_alloc(struct regstat *current,int i)
1847 clear_const(current,dops[i].rt1);
1848 alloc_reg(current,i,CSREG); // Status
1851 void c2ls_alloc(struct regstat *current,int i)
1853 clear_const(current,dops[i].rt1);
1854 if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1855 alloc_reg(current,i,FTEMP);
1857 alloc_reg(current, i, ROREG);
1858 #if defined(HOST_IMM8)
1859 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1860 if (dops[i].opcode == 0x3a) // SWC2
1861 alloc_reg(current,i,INVCP);
1863 // We need a temporary register for address generation
1864 alloc_reg_temp(current,i,-1);
1865 minimum_free_regs[i]=1;
1868 #ifndef multdiv_alloc
1869 void multdiv_alloc(struct regstat *current,int i)
1876 // case 0x1D: DMULTU
1879 clear_const(current,dops[i].rs1);
1880 clear_const(current,dops[i].rs2);
1881 alloc_cc(current,i); // for stalls
1882 if(dops[i].rs1&&dops[i].rs2)
1884 if((dops[i].opcode2&4)==0) // 32-bit
1886 current->u&=~(1LL<<HIREG);
1887 current->u&=~(1LL<<LOREG);
1888 alloc_reg(current,i,HIREG);
1889 alloc_reg(current,i,LOREG);
1890 alloc_reg(current,i,dops[i].rs1);
1891 alloc_reg(current,i,dops[i].rs2);
1892 dirty_reg(current,HIREG);
1893 dirty_reg(current,LOREG);
1902 // Multiply by zero is zero.
1903 // MIPS does not have a divide by zero exception.
1904 // The result is undefined, we return zero.
1905 alloc_reg(current,i,HIREG);
1906 alloc_reg(current,i,LOREG);
1907 dirty_reg(current,HIREG);
1908 dirty_reg(current,LOREG);
1913 void cop0_alloc(struct regstat *current,int i)
1915 if(dops[i].opcode2==0) // MFC0
1918 clear_const(current,dops[i].rt1);
1919 alloc_all(current,i);
1920 alloc_reg(current,i,dops[i].rt1);
1921 dirty_reg(current,dops[i].rt1);
1924 else if(dops[i].opcode2==4) // MTC0
1927 clear_const(current,dops[i].rs1);
1928 alloc_reg(current,i,dops[i].rs1);
1929 alloc_all(current,i);
1932 alloc_all(current,i); // FIXME: Keep r0
1934 alloc_reg(current,i,0);
1939 // TLBR/TLBWI/TLBWR/TLBP/ERET
1940 assert(dops[i].opcode2==0x10);
1941 alloc_all(current,i);
1943 minimum_free_regs[i]=HOST_REGS;
1946 static void cop2_alloc(struct regstat *current,int i)
1948 if (dops[i].opcode2 < 3) // MFC2/CFC2
1950 alloc_cc(current,i); // for stalls
1951 dirty_reg(current,CCREG);
1953 clear_const(current,dops[i].rt1);
1954 alloc_reg(current,i,dops[i].rt1);
1955 dirty_reg(current,dops[i].rt1);
1958 else if (dops[i].opcode2 > 3) // MTC2/CTC2
1961 clear_const(current,dops[i].rs1);
1962 alloc_reg(current,i,dops[i].rs1);
1966 alloc_reg(current,i,0);
1969 alloc_reg_temp(current,i,-1);
1970 minimum_free_regs[i]=1;
1973 void c2op_alloc(struct regstat *current,int i)
1975 alloc_cc(current,i); // for stalls
1976 dirty_reg(current,CCREG);
1977 alloc_reg_temp(current,i,-1);
1980 void syscall_alloc(struct regstat *current,int i)
1982 alloc_cc(current,i);
1983 dirty_reg(current,CCREG);
1984 alloc_all(current,i);
1985 minimum_free_regs[i]=HOST_REGS;
1989 void delayslot_alloc(struct regstat *current,int i)
1991 switch(dops[i].itype) {
1999 assem_debug("jump in the delay slot. this shouldn't happen.\n");//abort();
2000 SysPrintf("Disabled speculative precompilation\n");
2004 imm16_alloc(current,i);
2008 load_alloc(current,i);
2012 store_alloc(current,i);
2015 alu_alloc(current,i);
2018 shift_alloc(current,i);
2021 multdiv_alloc(current,i);
2024 shiftimm_alloc(current,i);
2027 mov_alloc(current,i);
2030 cop0_alloc(current,i);
2035 cop2_alloc(current,i);
2038 c1ls_alloc(current,i);
2041 c2ls_alloc(current,i);
2044 c2op_alloc(current,i);
2049 // Special case where a branch and delay slot span two pages in virtual memory
2050 static void pagespan_alloc(struct regstat *current,int i)
2053 current->wasconst=0;
2055 minimum_free_regs[i]=HOST_REGS;
2056 alloc_all(current,i);
2057 alloc_cc(current,i);
2058 dirty_reg(current,CCREG);
2059 if(dops[i].opcode==3) // JAL
2061 alloc_reg(current,i,31);
2062 dirty_reg(current,31);
2064 if(dops[i].opcode==0&&(dops[i].opcode2&0x3E)==8) // JR/JALR
2066 alloc_reg(current,i,dops[i].rs1);
2067 if (dops[i].rt1!=0) {
2068 alloc_reg(current,i,dops[i].rt1);
2069 dirty_reg(current,dops[i].rt1);
2072 if((dops[i].opcode&0x2E)==4) // BEQ/BNE/BEQL/BNEL
2074 if(dops[i].rs1) alloc_reg(current,i,dops[i].rs1);
2075 if(dops[i].rs2) alloc_reg(current,i,dops[i].rs2);
2078 if((dops[i].opcode&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
2080 if(dops[i].rs1) alloc_reg(current,i,dops[i].rs1);
2085 static void add_stub(enum stub_type type, void *addr, void *retaddr,
2086 u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e)
2088 assert(stubcount < ARRAY_SIZE(stubs));
2089 stubs[stubcount].type = type;
2090 stubs[stubcount].addr = addr;
2091 stubs[stubcount].retaddr = retaddr;
2092 stubs[stubcount].a = a;
2093 stubs[stubcount].b = b;
2094 stubs[stubcount].c = c;
2095 stubs[stubcount].d = d;
2096 stubs[stubcount].e = e;
2100 static void add_stub_r(enum stub_type type, void *addr, void *retaddr,
2101 int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist)
2103 add_stub(type, addr, retaddr, i, addr_reg, (uintptr_t)i_regs, ccadj, reglist);
2106 // Write out a single register
2107 static void wb_register(signed char r, const signed char regmap[], uint64_t dirty)
2110 for(hr=0;hr<HOST_REGS;hr++) {
2111 if(hr!=EXCLUDE_REG) {
2112 if((regmap[hr]&63)==r) {
2114 assert(regmap[hr]<64);
2115 emit_storereg(r,hr);
2122 static void wb_valid(signed char pre[],signed char entry[],u_int dirty_pre,u_int dirty,uint64_t u)
2124 //if(dirty_pre==dirty) return;
2126 for(hr=0;hr<HOST_REGS;hr++) {
2127 if(hr!=EXCLUDE_REG) {
2129 if(((~u)>>(reg&63))&1) {
2131 if(((dirty_pre&~dirty)>>hr)&1) {
2133 emit_storereg(reg,hr);
2146 static void pass_args(int a0, int a1)
2150 emit_mov(a0,2); emit_mov(a1,1); emit_mov(2,0);
2152 else if(a0!=0&&a1==0) {
2154 if (a0>=0) emit_mov(a0,0);
2157 if(a0>=0&&a0!=0) emit_mov(a0,0);
2158 if(a1>=0&&a1!=1) emit_mov(a1,1);
2162 static void alu_assemble(int i, const struct regstat *i_regs)
2164 if(dops[i].opcode2>=0x20&&dops[i].opcode2<=0x23) { // ADD/ADDU/SUB/SUBU
2166 signed char s1,s2,t;
2167 t=get_reg(i_regs->regmap,dops[i].rt1);
2169 s1=get_reg(i_regs->regmap,dops[i].rs1);
2170 s2=get_reg(i_regs->regmap,dops[i].rs2);
2171 if(dops[i].rs1&&dops[i].rs2) {
2174 if(dops[i].opcode2&2) emit_sub(s1,s2,t);
2175 else emit_add(s1,s2,t);
2177 else if(dops[i].rs1) {
2178 if(s1>=0) emit_mov(s1,t);
2179 else emit_loadreg(dops[i].rs1,t);
2181 else if(dops[i].rs2) {
2183 if(dops[i].opcode2&2) emit_neg(s2,t);
2184 else emit_mov(s2,t);
2187 emit_loadreg(dops[i].rs2,t);
2188 if(dops[i].opcode2&2) emit_neg(t,t);
2191 else emit_zeroreg(t);
2195 if(dops[i].opcode2>=0x2c&&dops[i].opcode2<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2198 if(dops[i].opcode2==0x2a||dops[i].opcode2==0x2b) { // SLT/SLTU
2200 signed char s1l,s2l,t;
2202 t=get_reg(i_regs->regmap,dops[i].rt1);
2205 s1l=get_reg(i_regs->regmap,dops[i].rs1);
2206 s2l=get_reg(i_regs->regmap,dops[i].rs2);
2207 if(dops[i].rs2==0) // rx<r0
2209 if(dops[i].opcode2==0x2a&&dops[i].rs1!=0) { // SLT
2211 emit_shrimm(s1l,31,t);
2213 else // SLTU (unsigned can not be less than zero, 0<0)
2216 else if(dops[i].rs1==0) // r0<rx
2219 if(dops[i].opcode2==0x2a) // SLT
2220 emit_set_gz32(s2l,t);
2221 else // SLTU (set if not zero)
2222 emit_set_nz32(s2l,t);
2225 assert(s1l>=0);assert(s2l>=0);
2226 if(dops[i].opcode2==0x2a) // SLT
2227 emit_set_if_less32(s1l,s2l,t);
2229 emit_set_if_carry32(s1l,s2l,t);
2235 if(dops[i].opcode2>=0x24&&dops[i].opcode2<=0x27) { // AND/OR/XOR/NOR
2237 signed char s1l,s2l,tl;
2238 tl=get_reg(i_regs->regmap,dops[i].rt1);
2241 s1l=get_reg(i_regs->regmap,dops[i].rs1);
2242 s2l=get_reg(i_regs->regmap,dops[i].rs2);
2243 if(dops[i].rs1&&dops[i].rs2) {
2246 if(dops[i].opcode2==0x24) { // AND
2247 emit_and(s1l,s2l,tl);
2249 if(dops[i].opcode2==0x25) { // OR
2250 emit_or(s1l,s2l,tl);
2252 if(dops[i].opcode2==0x26) { // XOR
2253 emit_xor(s1l,s2l,tl);
2255 if(dops[i].opcode2==0x27) { // NOR
2256 emit_or(s1l,s2l,tl);
2262 if(dops[i].opcode2==0x24) { // AND
2265 if(dops[i].opcode2==0x25||dops[i].opcode2==0x26) { // OR/XOR
2267 if(s1l>=0) emit_mov(s1l,tl);
2268 else emit_loadreg(dops[i].rs1,tl); // CHECK: regmap_entry?
2272 if(s2l>=0) emit_mov(s2l,tl);
2273 else emit_loadreg(dops[i].rs2,tl); // CHECK: regmap_entry?
2275 else emit_zeroreg(tl);
2277 if(dops[i].opcode2==0x27) { // NOR
2279 if(s1l>=0) emit_not(s1l,tl);
2281 emit_loadreg(dops[i].rs1,tl);
2287 if(s2l>=0) emit_not(s2l,tl);
2289 emit_loadreg(dops[i].rs2,tl);
2293 else emit_movimm(-1,tl);
2302 static void imm16_assemble(int i, const struct regstat *i_regs)
2304 if (dops[i].opcode==0x0f) { // LUI
2307 t=get_reg(i_regs->regmap,dops[i].rt1);
2310 if(!((i_regs->isconst>>t)&1))
2311 emit_movimm(imm[i]<<16,t);
2315 if(dops[i].opcode==0x08||dops[i].opcode==0x09) { // ADDI/ADDIU
2318 t=get_reg(i_regs->regmap,dops[i].rt1);
2319 s=get_reg(i_regs->regmap,dops[i].rs1);
2324 if(!((i_regs->isconst>>t)&1)) {
2326 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
2327 emit_addimm(t,imm[i],t);
2329 if(!((i_regs->wasconst>>s)&1))
2330 emit_addimm(s,imm[i],t);
2332 emit_movimm(constmap[i][s]+imm[i],t);
2338 if(!((i_regs->isconst>>t)&1))
2339 emit_movimm(imm[i],t);
2344 if(dops[i].opcode==0x18||dops[i].opcode==0x19) { // DADDI/DADDIU
2347 tl=get_reg(i_regs->regmap,dops[i].rt1);
2348 sl=get_reg(i_regs->regmap,dops[i].rs1);
2352 emit_addimm(sl,imm[i],tl);
2354 emit_movimm(imm[i],tl);
2359 else if(dops[i].opcode==0x0a||dops[i].opcode==0x0b) { // SLTI/SLTIU
2361 //assert(dops[i].rs1!=0); // r0 might be valid, but it's probably a bug
2363 t=get_reg(i_regs->regmap,dops[i].rt1);
2364 sl=get_reg(i_regs->regmap,dops[i].rs1);
2368 if(dops[i].opcode==0x0a) { // SLTI
2370 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
2371 emit_slti32(t,imm[i],t);
2373 emit_slti32(sl,imm[i],t);
2378 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
2379 emit_sltiu32(t,imm[i],t);
2381 emit_sltiu32(sl,imm[i],t);
2385 // SLTI(U) with r0 is just stupid,
2386 // nonetheless examples can be found
2387 if(dops[i].opcode==0x0a) // SLTI
2388 if(0<imm[i]) emit_movimm(1,t);
2389 else emit_zeroreg(t);
2392 if(imm[i]) emit_movimm(1,t);
2393 else emit_zeroreg(t);
2399 else if(dops[i].opcode>=0x0c&&dops[i].opcode<=0x0e) { // ANDI/ORI/XORI
2402 tl=get_reg(i_regs->regmap,dops[i].rt1);
2403 sl=get_reg(i_regs->regmap,dops[i].rs1);
2404 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2405 if(dops[i].opcode==0x0c) //ANDI
2409 if(i_regs->regmap_entry[tl]!=dops[i].rs1) emit_loadreg(dops[i].rs1,tl);
2410 emit_andimm(tl,imm[i],tl);
2412 if(!((i_regs->wasconst>>sl)&1))
2413 emit_andimm(sl,imm[i],tl);
2415 emit_movimm(constmap[i][sl]&imm[i],tl);
2425 if(i_regs->regmap_entry[tl]!=dops[i].rs1) emit_loadreg(dops[i].rs1,tl);
2427 if(dops[i].opcode==0x0d) { // ORI
2429 emit_orimm(tl,imm[i],tl);
2431 if(!((i_regs->wasconst>>sl)&1))
2432 emit_orimm(sl,imm[i],tl);
2434 emit_movimm(constmap[i][sl]|imm[i],tl);
2437 if(dops[i].opcode==0x0e) { // XORI
2439 emit_xorimm(tl,imm[i],tl);
2441 if(!((i_regs->wasconst>>sl)&1))
2442 emit_xorimm(sl,imm[i],tl);
2444 emit_movimm(constmap[i][sl]^imm[i],tl);
2449 emit_movimm(imm[i],tl);
2457 static void shiftimm_assemble(int i, const struct regstat *i_regs)
2459 if(dops[i].opcode2<=0x3) // SLL/SRL/SRA
2463 t=get_reg(i_regs->regmap,dops[i].rt1);
2464 s=get_reg(i_regs->regmap,dops[i].rs1);
2466 if(t>=0&&!((i_regs->isconst>>t)&1)){
2473 if(s<0&&i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
2475 if(dops[i].opcode2==0) // SLL
2477 emit_shlimm(s<0?t:s,imm[i],t);
2479 if(dops[i].opcode2==2) // SRL
2481 emit_shrimm(s<0?t:s,imm[i],t);
2483 if(dops[i].opcode2==3) // SRA
2485 emit_sarimm(s<0?t:s,imm[i],t);
2489 if(s>=0 && s!=t) emit_mov(s,t);
2493 //emit_storereg(dops[i].rt1,t); //DEBUG
2496 if(dops[i].opcode2>=0x38&&dops[i].opcode2<=0x3b) // DSLL/DSRL/DSRA
2500 if(dops[i].opcode2==0x3c) // DSLL32
2504 if(dops[i].opcode2==0x3e) // DSRL32
2508 if(dops[i].opcode2==0x3f) // DSRA32
2514 #ifndef shift_assemble
2515 static void shift_assemble(int i, const struct regstat *i_regs)
2517 signed char s,t,shift;
2518 if (dops[i].rt1 == 0)
2520 assert(dops[i].opcode2<=0x07); // SLLV/SRLV/SRAV
2521 t = get_reg(i_regs->regmap, dops[i].rt1);
2522 s = get_reg(i_regs->regmap, dops[i].rs1);
2523 shift = get_reg(i_regs->regmap, dops[i].rs2);
2529 else if(dops[i].rs2==0) {
2531 if(s!=t) emit_mov(s,t);
2534 host_tempreg_acquire();
2535 emit_andimm(shift,31,HOST_TEMPREG);
2536 switch(dops[i].opcode2) {
2538 emit_shl(s,HOST_TEMPREG,t);
2541 emit_shr(s,HOST_TEMPREG,t);
2544 emit_sar(s,HOST_TEMPREG,t);
2549 host_tempreg_release();
2563 static int get_ptr_mem_type(u_int a)
2565 if(a < 0x00200000) {
2566 if(a<0x1000&&((start>>20)==0xbfc||(start>>24)==0xa0))
2567 // return wrong, must use memhandler for BIOS self-test to pass
2568 // 007 does similar stuff from a00 mirror, weird stuff
2572 if(0x1f800000 <= a && a < 0x1f801000)
2574 if(0x80200000 <= a && a < 0x80800000)
2576 if(0xa0000000 <= a && a < 0xa0200000)
2581 static int get_ro_reg(const struct regstat *i_regs, int host_tempreg_free)
2583 int r = get_reg(i_regs->regmap, ROREG);
2584 if (r < 0 && host_tempreg_free) {
2585 host_tempreg_acquire();
2586 emit_loadreg(ROREG, r = HOST_TEMPREG);
2593 static void *emit_fastpath_cmp_jump(int i, const struct regstat *i_regs,
2594 int addr, int *offset_reg, int *addr_reg_override)
2598 int mr = dops[i].rs1;
2600 if(((smrv_strong|smrv_weak)>>mr)&1) {
2601 type=get_ptr_mem_type(smrv[mr]);
2602 //printf("set %08x @%08x r%d %d\n", smrv[mr], start+i*4, mr, type);
2605 // use the mirror we are running on
2606 type=get_ptr_mem_type(start);
2607 //printf("set nospec @%08x r%d %d\n", start+i*4, mr, type);
2610 if(type==MTYPE_8020) { // RAM 80200000+ mirror
2611 host_tempreg_acquire();
2612 emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
2613 addr=*addr_reg_override=HOST_TEMPREG;
2616 else if(type==MTYPE_0000) { // RAM 0 mirror
2617 host_tempreg_acquire();
2618 emit_orimm(addr,0x80000000,HOST_TEMPREG);
2619 addr=*addr_reg_override=HOST_TEMPREG;
2622 else if(type==MTYPE_A000) { // RAM A mirror
2623 host_tempreg_acquire();
2624 emit_andimm(addr,~0x20000000,HOST_TEMPREG);
2625 addr=*addr_reg_override=HOST_TEMPREG;
2628 else if(type==MTYPE_1F80) { // scratchpad
2629 if (psxH == (void *)0x1f800000) {
2630 host_tempreg_acquire();
2631 emit_xorimm(addr,0x1f800000,HOST_TEMPREG);
2632 emit_cmpimm(HOST_TEMPREG,0x1000);
2633 host_tempreg_release();
2638 // do the usual RAM check, jump will go to the right handler
2643 if (type == 0) // need ram check
2645 emit_cmpimm(addr,RAM_SIZE);
2647 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2648 // Hint to branch predictor that the branch is unlikely to be taken
2649 if (dops[i].rs1 >= 28)
2650 emit_jno_unlikely(0);
2654 if (ram_offset != 0)
2655 *offset_reg = get_ro_reg(i_regs, 0);
2661 // return memhandler, or get directly accessable address and return 0
2662 static void *get_direct_memhandler(void *table, u_int addr,
2663 enum stub_type type, uintptr_t *addr_host)
2665 uintptr_t msb = 1ull << (sizeof(uintptr_t)*8 - 1);
2666 uintptr_t l1, l2 = 0;
2667 l1 = ((uintptr_t *)table)[addr>>12];
2669 uintptr_t v = l1 << 1;
2670 *addr_host = v + addr;
2675 if (type == LOADB_STUB || type == LOADBU_STUB || type == STOREB_STUB)
2676 l2 = ((uintptr_t *)l1)[0x1000/4 + 0x1000/2 + (addr&0xfff)];
2677 else if (type == LOADH_STUB || type == LOADHU_STUB || type == STOREH_STUB)
2678 l2 = ((uintptr_t *)l1)[0x1000/4 + (addr&0xfff)/2];
2680 l2 = ((uintptr_t *)l1)[(addr&0xfff)/4];
2682 uintptr_t v = l2 << 1;
2683 *addr_host = v + (addr&0xfff);
2686 return (void *)(l2 << 1);
2690 static u_int get_host_reglist(const signed char *regmap)
2692 u_int reglist = 0, hr;
2693 for (hr = 0; hr < HOST_REGS; hr++) {
2694 if (hr != EXCLUDE_REG && regmap[hr] >= 0)
2700 static u_int reglist_exclude(u_int reglist, int r1, int r2)
2703 reglist &= ~(1u << r1);
2705 reglist &= ~(1u << r2);
2709 // find a temp caller-saved register not in reglist (so assumed to be free)
2710 static int reglist_find_free(u_int reglist)
2712 u_int free_regs = ~reglist & CALLER_SAVE_REGS;
2715 return __builtin_ctz(free_regs);
2718 static void do_load_word(int a, int rt, int offset_reg)
2720 if (offset_reg >= 0)
2721 emit_ldr_dualindexed(offset_reg, a, rt);
2723 emit_readword_indexed(0, a, rt);
2726 static void do_store_word(int a, int ofs, int rt, int offset_reg, int preseve_a)
2728 if (offset_reg < 0) {
2729 emit_writeword_indexed(rt, ofs, a);
2733 emit_addimm(a, ofs, a);
2734 emit_str_dualindexed(offset_reg, a, rt);
2735 if (ofs != 0 && preseve_a)
2736 emit_addimm(a, -ofs, a);
2739 static void do_store_hword(int a, int ofs, int rt, int offset_reg, int preseve_a)
2741 if (offset_reg < 0) {
2742 emit_writehword_indexed(rt, ofs, a);
2746 emit_addimm(a, ofs, a);
2747 emit_strh_dualindexed(offset_reg, a, rt);
2748 if (ofs != 0 && preseve_a)
2749 emit_addimm(a, -ofs, a);
2752 static void do_store_byte(int a, int rt, int offset_reg)
2754 if (offset_reg >= 0)
2755 emit_strb_dualindexed(offset_reg, a, rt);
2757 emit_writebyte_indexed(rt, 0, a);
2760 static void load_assemble(int i, const struct regstat *i_regs, int ccadj_)
2765 int memtarget=0,c=0;
2766 int offset_reg = -1;
2767 int fastio_reg_override = -1;
2768 u_int reglist=get_host_reglist(i_regs->regmap);
2769 tl=get_reg(i_regs->regmap,dops[i].rt1);
2770 s=get_reg(i_regs->regmap,dops[i].rs1);
2772 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2774 c=(i_regs->wasconst>>s)&1;
2776 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2779 //printf("load_assemble: c=%d\n",c);
2780 //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset);
2781 // FIXME: Even if the load is a NOP, we should check for pagefaults...
2782 if((tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80))
2784 // could be FIFO, must perform the read
2786 assem_debug("(forced read)\n");
2787 tl=get_reg(i_regs->regmap,-1);
2790 if(offset||s<0||c) addr=tl;
2792 //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2794 //printf("load_assemble: c=%d\n",c);
2795 //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset);
2796 assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2800 // Strmnnrmn's speed hack
2801 if(dops[i].rs1!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2804 jaddr = emit_fastpath_cmp_jump(i, i_regs, addr,
2805 &offset_reg, &fastio_reg_override);
2808 else if (ram_offset && memtarget) {
2809 offset_reg = get_ro_reg(i_regs, 0);
2811 int dummy=(dops[i].rt1==0)||(tl!=get_reg(i_regs->regmap,dops[i].rt1)); // ignore loads to r0 and unneeded reg
2812 switch (dops[i].opcode) {
2818 if (fastio_reg_override >= 0)
2819 a = fastio_reg_override;
2821 if (offset_reg >= 0)
2822 emit_ldrsb_dualindexed(offset_reg, a, tl);
2824 emit_movsbl_indexed(0, a, tl);
2827 add_stub_r(LOADB_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
2830 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
2837 if (fastio_reg_override >= 0)
2838 a = fastio_reg_override;
2839 if (offset_reg >= 0)
2840 emit_ldrsh_dualindexed(offset_reg, a, tl);
2842 emit_movswl_indexed(0, a, tl);
2845 add_stub_r(LOADH_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
2848 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
2854 if (fastio_reg_override >= 0)
2855 a = fastio_reg_override;
2856 do_load_word(a, tl, offset_reg);
2859 add_stub_r(LOADW_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
2862 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
2869 if (fastio_reg_override >= 0)
2870 a = fastio_reg_override;
2872 if (offset_reg >= 0)
2873 emit_ldrb_dualindexed(offset_reg, a, tl);
2875 emit_movzbl_indexed(0, a, tl);
2878 add_stub_r(LOADBU_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
2881 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
2888 if (fastio_reg_override >= 0)
2889 a = fastio_reg_override;
2890 if (offset_reg >= 0)
2891 emit_ldrh_dualindexed(offset_reg, a, tl);
2893 emit_movzwl_indexed(0, a, tl);
2896 add_stub_r(LOADHU_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
2899 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
2907 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
2908 host_tempreg_release();
2911 #ifndef loadlr_assemble
2912 static void loadlr_assemble(int i, const struct regstat *i_regs, int ccadj_)
2914 int s,tl,temp,temp2,addr;
2917 int memtarget=0,c=0;
2918 int offset_reg = -1;
2919 int fastio_reg_override = -1;
2920 u_int reglist=get_host_reglist(i_regs->regmap);
2921 tl=get_reg(i_regs->regmap,dops[i].rt1);
2922 s=get_reg(i_regs->regmap,dops[i].rs1);
2923 temp=get_reg(i_regs->regmap,-1);
2924 temp2=get_reg(i_regs->regmap,FTEMP);
2925 addr=get_reg(i_regs->regmap,AGEN1+(i&1));
2929 if(offset||s<0||c) addr=temp2;
2932 c=(i_regs->wasconst>>s)&1;
2934 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2938 emit_shlimm(addr,3,temp);
2939 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
2940 emit_andimm(addr,0xFFFFFFFC,temp2); // LWL/LWR
2942 emit_andimm(addr,0xFFFFFFF8,temp2); // LDL/LDR
2944 jaddr = emit_fastpath_cmp_jump(i, i_regs, temp2,
2945 &offset_reg, &fastio_reg_override);
2948 if (ram_offset && memtarget) {
2949 offset_reg = get_ro_reg(i_regs, 0);
2951 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
2952 emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR
2954 emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR
2957 if (dops[i].opcode==0x22||dops[i].opcode==0x26) { // LWL/LWR
2960 if (fastio_reg_override >= 0)
2961 a = fastio_reg_override;
2962 do_load_word(a, temp2, offset_reg);
2963 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
2964 host_tempreg_release();
2965 if(jaddr) add_stub_r(LOADW_STUB,jaddr,out,i,temp2,i_regs,ccadj_,reglist);
2968 inline_readstub(LOADW_STUB,i,(constmap[i][s]+offset)&0xFFFFFFFC,i_regs->regmap,FTEMP,ccadj_,reglist);
2971 emit_andimm(temp,24,temp);
2972 if (dops[i].opcode==0x22) // LWL
2973 emit_xorimm(temp,24,temp);
2974 host_tempreg_acquire();
2975 emit_movimm(-1,HOST_TEMPREG);
2976 if (dops[i].opcode==0x26) {
2977 emit_shr(temp2,temp,temp2);
2978 emit_bic_lsr(tl,HOST_TEMPREG,temp,tl);
2980 emit_shl(temp2,temp,temp2);
2981 emit_bic_lsl(tl,HOST_TEMPREG,temp,tl);
2983 host_tempreg_release();
2984 emit_or(temp2,tl,tl);
2986 //emit_storereg(dops[i].rt1,tl); // DEBUG
2988 if (dops[i].opcode==0x1A||dops[i].opcode==0x1B) { // LDL/LDR
2994 static void store_assemble(int i, const struct regstat *i_regs, int ccadj_)
3000 enum stub_type type=0;
3001 int memtarget=0,c=0;
3002 int agr=AGEN1+(i&1);
3003 int offset_reg = -1;
3004 int fastio_reg_override = -1;
3005 u_int reglist=get_host_reglist(i_regs->regmap);
3006 tl=get_reg(i_regs->regmap,dops[i].rs2);
3007 s=get_reg(i_regs->regmap,dops[i].rs1);
3008 temp=get_reg(i_regs->regmap,agr);
3009 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3012 c=(i_regs->wasconst>>s)&1;
3014 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3019 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3020 if(offset||s<0||c) addr=temp;
3023 jaddr = emit_fastpath_cmp_jump(i, i_regs, addr,
3024 &offset_reg, &fastio_reg_override);
3026 else if (ram_offset && memtarget) {
3027 offset_reg = get_ro_reg(i_regs, 0);
3030 switch (dops[i].opcode) {
3035 if (fastio_reg_override >= 0)
3036 a = fastio_reg_override;
3037 do_store_byte(a, tl, offset_reg);
3045 if (fastio_reg_override >= 0)
3046 a = fastio_reg_override;
3047 do_store_hword(a, 0, tl, offset_reg, 1);
3054 if (fastio_reg_override >= 0)
3055 a = fastio_reg_override;
3056 do_store_word(a, 0, tl, offset_reg, 1);
3064 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
3065 host_tempreg_release();
3067 // PCSX store handlers don't check invcode again
3069 add_stub_r(type,jaddr,out,i,addr,i_regs,ccadj_,reglist);
3072 if(!(i_regs->waswritten&(1<<dops[i].rs1)) && !HACK_ENABLED(NDHACK_NO_SMC_CHECK)) {
3074 #ifdef DESTRUCTIVE_SHIFT
3075 // The x86 shift operation is 'destructive'; it overwrites the
3076 // source register, so we need to make a copy first and use that.
3079 #if defined(HOST_IMM8)
3080 int ir=get_reg(i_regs->regmap,INVCP);
3082 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3084 emit_cmpmem_indexedsr12_imm(invalid_code,addr,1);
3086 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3087 emit_callne(invalidate_addr_reg[addr]);
3091 add_stub(INVCODE_STUB,jaddr2,out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3095 u_int addr_val=constmap[i][s]+offset;
3097 add_stub_r(type,jaddr,out,i,addr,i_regs,ccadj_,reglist);
3098 } else if(c&&!memtarget) {
3099 inline_writestub(type,i,addr_val,i_regs->regmap,dops[i].rs2,ccadj_,reglist);
3101 // basic current block modification detection..
3102 // not looking back as that should be in mips cache already
3103 // (see Spyro2 title->attract mode)
3104 if(c&&start+i*4<addr_val&&addr_val<start+slen*4) {
3105 SysPrintf("write to %08x hits block %08x, pc=%08x\n",addr_val,start,start+i*4);
3106 assert(i_regs->regmap==regs[i].regmap); // not delay slot
3107 if(i_regs->regmap==regs[i].regmap) {
3108 load_all_consts(regs[i].regmap_entry,regs[i].wasdirty,i);
3109 wb_dirtys(regs[i].regmap_entry,regs[i].wasdirty);
3110 emit_movimm(start+i*4+4,0);
3111 emit_writeword(0,&pcaddr);
3112 emit_addimm(HOST_CCREG,2,HOST_CCREG);
3113 emit_far_call(get_addr_ht);
3119 static void storelr_assemble(int i, const struct regstat *i_regs, int ccadj_)
3125 void *case1, *case23, *case3;
3126 void *done0, *done1, *done2;
3127 int memtarget=0,c=0;
3128 int agr=AGEN1+(i&1);
3129 int offset_reg = -1;
3130 u_int reglist=get_host_reglist(i_regs->regmap);
3131 tl=get_reg(i_regs->regmap,dops[i].rs2);
3132 s=get_reg(i_regs->regmap,dops[i].rs1);
3133 temp=get_reg(i_regs->regmap,agr);
3134 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3137 c=(i_regs->isconst>>s)&1;
3139 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3145 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3146 if(!offset&&s!=temp) emit_mov(s,temp);
3152 if(!memtarget||!dops[i].rs1) {
3158 offset_reg = get_ro_reg(i_regs, 0);
3160 if (dops[i].opcode==0x2C||dops[i].opcode==0x2D) { // SDL/SDR
3164 emit_testimm(temp,2);
3167 emit_testimm(temp,1);
3171 if (dops[i].opcode == 0x2A) { // SWL
3172 // Write msb into least significant byte
3173 if (dops[i].rs2) emit_rorimm(tl, 24, tl);
3174 do_store_byte(temp, tl, offset_reg);
3175 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3177 else if (dops[i].opcode == 0x2E) { // SWR
3178 // Write entire word
3179 do_store_word(temp, 0, tl, offset_reg, 1);
3184 set_jump_target(case1, out);
3185 if (dops[i].opcode == 0x2A) { // SWL
3186 // Write two msb into two least significant bytes
3187 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
3188 do_store_hword(temp, -1, tl, offset_reg, 0);
3189 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
3191 else if (dops[i].opcode == 0x2E) { // SWR
3192 // Write 3 lsb into three most significant bytes
3193 do_store_byte(temp, tl, offset_reg);
3194 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3195 do_store_hword(temp, 1, tl, offset_reg, 0);
3196 if (dops[i].rs2) emit_rorimm(tl, 24, tl);
3201 set_jump_target(case23, out);
3202 emit_testimm(temp,1);
3206 if (dops[i].opcode==0x2A) { // SWL
3207 // Write 3 msb into three least significant bytes
3208 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3209 do_store_hword(temp, -2, tl, offset_reg, 1);
3210 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
3211 do_store_byte(temp, tl, offset_reg);
3212 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3214 else if (dops[i].opcode == 0x2E) { // SWR
3215 // Write two lsb into two most significant bytes
3216 do_store_hword(temp, 0, tl, offset_reg, 1);
3221 set_jump_target(case3, out);
3222 if (dops[i].opcode == 0x2A) { // SWL
3223 do_store_word(temp, -3, tl, offset_reg, 0);
3225 else if (dops[i].opcode == 0x2E) { // SWR
3226 do_store_byte(temp, tl, offset_reg);
3228 set_jump_target(done0, out);
3229 set_jump_target(done1, out);
3230 set_jump_target(done2, out);
3231 if (offset_reg == HOST_TEMPREG)
3232 host_tempreg_release();
3234 add_stub_r(STORELR_STUB,jaddr,out,i,temp,i_regs,ccadj_,reglist);
3235 if(!(i_regs->waswritten&(1<<dops[i].rs1)) && !HACK_ENABLED(NDHACK_NO_SMC_CHECK)) {
3236 #if defined(HOST_IMM8)
3237 int ir=get_reg(i_regs->regmap,INVCP);
3239 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3241 emit_cmpmem_indexedsr12_imm(invalid_code,temp,1);
3243 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3244 emit_callne(invalidate_addr_reg[temp]);
3248 add_stub(INVCODE_STUB,jaddr2,out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3253 static void cop0_assemble(int i, const struct regstat *i_regs, int ccadj_)
3255 if(dops[i].opcode2==0) // MFC0
3257 signed char t=get_reg(i_regs->regmap,dops[i].rt1);
3258 u_int copr=(source[i]>>11)&0x1f;
3259 //assert(t>=0); // Why does this happen? OOT is weird
3260 if(t>=0&&dops[i].rt1!=0) {
3261 emit_readword(®_cop0[copr],t);
3264 else if(dops[i].opcode2==4) // MTC0
3266 signed char s=get_reg(i_regs->regmap,dops[i].rs1);
3267 char copr=(source[i]>>11)&0x1f;
3269 wb_register(dops[i].rs1,i_regs->regmap,i_regs->dirty);
3270 if(copr==9||copr==11||copr==12||copr==13) {
3271 emit_readword(&last_count,HOST_TEMPREG);
3272 emit_loadreg(CCREG,HOST_CCREG); // TODO: do proper reg alloc
3273 emit_add(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
3274 emit_addimm(HOST_CCREG,ccadj_,HOST_CCREG);
3275 emit_writeword(HOST_CCREG,&Count);
3277 // What a mess. The status register (12) can enable interrupts,
3278 // so needs a special case to handle a pending interrupt.
3279 // The interrupt must be taken immediately, because a subsequent
3280 // instruction might disable interrupts again.
3281 if(copr==12||copr==13) {
3283 // burn cycles to cause cc_interrupt, which will
3284 // reschedule next_interupt. Relies on CCREG from above.
3285 assem_debug("MTC0 DS %d\n", copr);
3286 emit_writeword(HOST_CCREG,&last_count);
3287 emit_movimm(0,HOST_CCREG);
3288 emit_storereg(CCREG,HOST_CCREG);
3289 emit_loadreg(dops[i].rs1,1);
3290 emit_movimm(copr,0);
3291 emit_far_call(pcsx_mtc0_ds);
3292 emit_loadreg(dops[i].rs1,s);
3295 emit_movimm(start+i*4+4,HOST_TEMPREG);
3296 emit_writeword(HOST_TEMPREG,&pcaddr);
3297 emit_movimm(0,HOST_TEMPREG);
3298 emit_writeword(HOST_TEMPREG,&pending_exception);
3301 emit_loadreg(dops[i].rs1,1);
3304 emit_movimm(copr,0);
3305 emit_far_call(pcsx_mtc0);
3306 if(copr==9||copr==11||copr==12||copr==13) {
3307 emit_readword(&Count,HOST_CCREG);
3308 emit_readword(&next_interupt,HOST_TEMPREG);
3309 emit_addimm(HOST_CCREG,-ccadj_,HOST_CCREG);
3310 emit_sub(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
3311 emit_writeword(HOST_TEMPREG,&last_count);
3312 emit_storereg(CCREG,HOST_CCREG);
3314 if(copr==12||copr==13) {
3315 assert(!is_delayslot);
3316 emit_readword(&pending_exception,14);
3320 emit_readword(&pcaddr, 0);
3321 emit_addimm(HOST_CCREG,2,HOST_CCREG);
3322 emit_far_call(get_addr_ht);
3324 set_jump_target(jaddr, out);
3326 emit_loadreg(dops[i].rs1,s);
3330 assert(dops[i].opcode2==0x10);
3331 //if((source[i]&0x3f)==0x10) // RFE
3333 emit_readword(&Status,0);
3334 emit_andimm(0,0x3c,1);
3335 emit_andimm(0,~0xf,0);
3336 emit_orrshr_imm(1,2,0);
3337 emit_writeword(0,&Status);
3342 static void cop1_unusable(int i, const struct regstat *i_regs)
3344 // XXX: should just just do the exception instead
3349 add_stub_r(FP_STUB,jaddr,out,i,0,i_regs,is_delayslot,0);
3353 static void cop1_assemble(int i, const struct regstat *i_regs)
3355 cop1_unusable(i, i_regs);
3358 static void c1ls_assemble(int i, const struct regstat *i_regs)
3360 cop1_unusable(i, i_regs);
3364 static void do_cop1stub(int n)
3367 assem_debug("do_cop1stub %x\n",start+stubs[n].a*4);
3368 set_jump_target(stubs[n].addr, out);
3370 // int rs=stubs[n].b;
3371 struct regstat *i_regs=(struct regstat *)stubs[n].c;
3374 load_all_consts(regs[i].regmap_entry,regs[i].wasdirty,i);
3375 //if(i_regs!=®s[i]) printf("oops: regs[i]=%x i_regs=%x",(int)®s[i],(int)i_regs);
3377 //else {printf("fp exception in delay slot\n");}
3378 wb_dirtys(i_regs->regmap_entry,i_regs->wasdirty);
3379 if(regs[i].regmap_entry[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
3380 emit_movimm(start+(i-ds)*4,EAX); // Get PC
3381 emit_addimm(HOST_CCREG,ccadj[i],HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
3382 emit_far_jump(ds?fp_exception_ds:fp_exception);
3385 static int cop2_is_stalling_op(int i, int *cycles)
3387 if (dops[i].opcode == 0x3a) { // SWC2
3391 if (dops[i].itype == COP2 && (dops[i].opcode2 == 0 || dops[i].opcode2 == 2)) { // MFC2/CFC2
3395 if (dops[i].itype == C2OP) {
3396 *cycles = gte_cycletab[source[i] & 0x3f];
3399 // ... what about MTC2/CTC2/LWC2?
3404 static void log_gte_stall(int stall, u_int cycle)
3406 if ((u_int)stall <= 44)
3407 printf("x stall %2d %u\n", stall, cycle + last_count);
3410 static void emit_log_gte_stall(int i, int stall, u_int reglist)
3414 emit_movimm(stall, 0);
3416 emit_mov(HOST_TEMPREG, 0);
3417 emit_addimm(HOST_CCREG, ccadj[i], 1);
3418 emit_far_call(log_gte_stall);
3419 restore_regs(reglist);
3423 static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist)
3425 int j = i, other_gte_op_cycles = -1, stall = -MAXBLOCK, cycles_passed;
3426 int rtmp = reglist_find_free(reglist);
3428 if (HACK_ENABLED(NDHACK_NO_STALLS))
3430 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) {
3431 // happens occasionally... cc evicted? Don't bother then
3432 //printf("no cc %08x\n", start + i*4);
3436 for (j = i - 1; j >= 0; j--) {
3437 //if (dops[j].is_ds) break;
3438 if (cop2_is_stalling_op(j, &other_gte_op_cycles) || dops[j].bt)
3440 if (j > 0 && ccadj[j - 1] > ccadj[j])
3445 cycles_passed = ccadj[i] - ccadj[j];
3446 if (other_gte_op_cycles >= 0)
3447 stall = other_gte_op_cycles - cycles_passed;
3448 else if (cycles_passed >= 44)
3449 stall = 0; // can't stall
3450 if (stall == -MAXBLOCK && rtmp >= 0) {
3451 // unknown stall, do the expensive runtime check
3452 assem_debug("; cop2_do_stall_check\n");
3455 emit_movimm(gte_cycletab[op], 0);
3456 emit_addimm(HOST_CCREG, ccadj[i], 1);
3457 emit_far_call(call_gteStall);
3458 restore_regs(reglist);
3460 host_tempreg_acquire();
3461 emit_readword(&psxRegs.gteBusyCycle, rtmp);
3462 emit_addimm(rtmp, -ccadj[i], rtmp);
3463 emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG);
3464 emit_cmpimm(HOST_TEMPREG, 44);
3465 emit_cmovb_reg(rtmp, HOST_CCREG);
3466 //emit_log_gte_stall(i, 0, reglist);
3467 host_tempreg_release();
3470 else if (stall > 0) {
3471 //emit_log_gte_stall(i, stall, reglist);
3472 emit_addimm(HOST_CCREG, stall, HOST_CCREG);
3475 // save gteBusyCycle, if needed
3476 if (gte_cycletab[op] == 0)
3478 other_gte_op_cycles = -1;
3479 for (j = i + 1; j < slen; j++) {
3480 if (cop2_is_stalling_op(j, &other_gte_op_cycles))
3482 if (dops[j].is_jump) {
3484 if (j + 1 < slen && cop2_is_stalling_op(j + 1, &other_gte_op_cycles))
3489 if (other_gte_op_cycles >= 0)
3490 // will handle stall when assembling that op
3492 cycles_passed = ccadj[min(j, slen -1)] - ccadj[i];
3493 if (cycles_passed >= 44)
3495 assem_debug("; save gteBusyCycle\n");
3496 host_tempreg_acquire();
3498 emit_readword(&last_count, HOST_TEMPREG);
3499 emit_add(HOST_TEMPREG, HOST_CCREG, HOST_TEMPREG);
3500 emit_addimm(HOST_TEMPREG, ccadj[i], HOST_TEMPREG);
3501 emit_addimm(HOST_TEMPREG, gte_cycletab[op]), HOST_TEMPREG);
3502 emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle);
3504 emit_addimm(HOST_CCREG, ccadj[i] + gte_cycletab[op], HOST_TEMPREG);
3505 emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle);
3507 host_tempreg_release();
3510 static int is_mflohi(int i)
3512 return (dops[i].itype == MOV && (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG));
3515 static int check_multdiv(int i, int *cycles)
3517 if (dops[i].itype != MULTDIV)
3519 if (dops[i].opcode2 == 0x18 || dops[i].opcode2 == 0x19) // MULT(U)
3520 *cycles = 11; // approx from 7 11 14
3526 static void multdiv_prepare_stall(int i, const struct regstat *i_regs, int ccadj_)
3528 int j, found = 0, c = 0;
3529 if (HACK_ENABLED(NDHACK_NO_STALLS))
3531 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) {
3532 // happens occasionally... cc evicted? Don't bother then
3535 for (j = i + 1; j < slen; j++) {
3538 if ((found = is_mflohi(j)))
3540 if (dops[j].is_jump) {
3542 if (j + 1 < slen && (found = is_mflohi(j + 1)))
3548 // handle all in multdiv_do_stall()
3550 check_multdiv(i, &c);
3552 assem_debug("; muldiv prepare stall %d\n", c);
3553 host_tempreg_acquire();
3554 emit_addimm(HOST_CCREG, ccadj_ + c, HOST_TEMPREG);
3555 emit_writeword(HOST_TEMPREG, &psxRegs.muldivBusyCycle);
3556 host_tempreg_release();
3559 static void multdiv_do_stall(int i, const struct regstat *i_regs)
3561 int j, known_cycles = 0;
3562 u_int reglist = get_host_reglist(i_regs->regmap);
3563 int rtmp = get_reg(i_regs->regmap, -1);
3565 rtmp = reglist_find_free(reglist);
3566 if (HACK_ENABLED(NDHACK_NO_STALLS))
3568 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG || rtmp < 0) {
3569 // happens occasionally... cc evicted? Don't bother then
3570 //printf("no cc/rtmp %08x\n", start + i*4);
3574 for (j = i - 1; j >= 0; j--) {
3575 if (dops[j].is_ds) break;
3576 if (check_multdiv(j, &known_cycles))
3579 // already handled by this op
3581 if (dops[j].bt || (j > 0 && ccadj[j - 1] > ccadj[j]))
3586 if (known_cycles > 0) {
3587 known_cycles -= ccadj[i] - ccadj[j];
3588 assem_debug("; muldiv stall resolved %d\n", known_cycles);
3589 if (known_cycles > 0)
3590 emit_addimm(HOST_CCREG, known_cycles, HOST_CCREG);
3593 assem_debug("; muldiv stall unresolved\n");
3594 host_tempreg_acquire();
3595 emit_readword(&psxRegs.muldivBusyCycle, rtmp);
3596 emit_addimm(rtmp, -ccadj[i], rtmp);
3597 emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG);
3598 emit_cmpimm(HOST_TEMPREG, 37);
3599 emit_cmovb_reg(rtmp, HOST_CCREG);
3600 //emit_log_gte_stall(i, 0, reglist);
3601 host_tempreg_release();
3604 static void cop2_get_dreg(u_int copr,signed char tl,signed char temp)
3614 emit_readword(®_cop2d[copr],tl);
3615 emit_signextend16(tl,tl);
3616 emit_writeword(tl,®_cop2d[copr]); // hmh
3623 emit_readword(®_cop2d[copr],tl);
3624 emit_andimm(tl,0xffff,tl);
3625 emit_writeword(tl,®_cop2d[copr]);
3628 emit_readword(®_cop2d[14],tl); // SXY2
3629 emit_writeword(tl,®_cop2d[copr]);
3633 c2op_mfc2_29_assemble(tl,temp);
3636 emit_readword(®_cop2d[copr],tl);
3641 static void cop2_put_dreg(u_int copr,signed char sl,signed char temp)
3645 emit_readword(®_cop2d[13],temp); // SXY1
3646 emit_writeword(sl,®_cop2d[copr]);
3647 emit_writeword(temp,®_cop2d[12]); // SXY0
3648 emit_readword(®_cop2d[14],temp); // SXY2
3649 emit_writeword(sl,®_cop2d[14]);
3650 emit_writeword(temp,®_cop2d[13]); // SXY1
3653 emit_andimm(sl,0x001f,temp);
3654 emit_shlimm(temp,7,temp);
3655 emit_writeword(temp,®_cop2d[9]);
3656 emit_andimm(sl,0x03e0,temp);
3657 emit_shlimm(temp,2,temp);
3658 emit_writeword(temp,®_cop2d[10]);
3659 emit_andimm(sl,0x7c00,temp);
3660 emit_shrimm(temp,3,temp);
3661 emit_writeword(temp,®_cop2d[11]);
3662 emit_writeword(sl,®_cop2d[28]);
3665 emit_xorsar_imm(sl,sl,31,temp);
3666 #if defined(HAVE_ARMV5) || defined(__aarch64__)
3667 emit_clz(temp,temp);
3669 emit_movs(temp,HOST_TEMPREG);
3670 emit_movimm(0,temp);
3671 emit_jeq((int)out+4*4);
3672 emit_addpl_imm(temp,1,temp);
3673 emit_lslpls_imm(HOST_TEMPREG,1,HOST_TEMPREG);
3674 emit_jns((int)out-2*4);
3676 emit_writeword(sl,®_cop2d[30]);
3677 emit_writeword(temp,®_cop2d[31]);
3682 emit_writeword(sl,®_cop2d[copr]);
3687 static void c2ls_assemble(int i, const struct regstat *i_regs, int ccadj_)
3692 int memtarget=0,c=0;
3694 enum stub_type type;
3695 int agr=AGEN1+(i&1);
3696 int offset_reg = -1;
3697 int fastio_reg_override = -1;
3698 u_int reglist=get_host_reglist(i_regs->regmap);
3699 u_int copr=(source[i]>>16)&0x1f;
3700 s=get_reg(i_regs->regmap,dops[i].rs1);
3701 tl=get_reg(i_regs->regmap,FTEMP);
3703 assert(dops[i].rs1>0);
3706 if(i_regs->regmap[HOST_CCREG]==CCREG)
3707 reglist&=~(1<<HOST_CCREG);
3710 if (dops[i].opcode==0x3a) { // SWC2
3711 ar=get_reg(i_regs->regmap,agr);
3712 if(ar<0) ar=get_reg(i_regs->regmap,-1);
3717 if(s>=0) c=(i_regs->wasconst>>s)&1;
3718 memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
3719 if (!offset&&!c&&s>=0) ar=s;
3722 cop2_do_stall_check(0, i, i_regs, reglist);
3724 if (dops[i].opcode==0x3a) { // SWC2
3725 cop2_get_dreg(copr,tl,-1);
3733 emit_jmp(0); // inline_readstub/inline_writestub?
3737 jaddr2 = emit_fastpath_cmp_jump(i, i_regs, ar,
3738 &offset_reg, &fastio_reg_override);
3740 else if (ram_offset && memtarget) {
3741 offset_reg = get_ro_reg(i_regs, 0);
3743 switch (dops[i].opcode) {
3744 case 0x32: { // LWC2
3746 if (fastio_reg_override >= 0)
3747 a = fastio_reg_override;
3748 do_load_word(a, tl, offset_reg);
3751 case 0x3a: { // SWC2
3752 #ifdef DESTRUCTIVE_SHIFT
3753 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3756 if (fastio_reg_override >= 0)
3757 a = fastio_reg_override;
3758 do_store_word(a, 0, tl, offset_reg, 1);
3765 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
3766 host_tempreg_release();
3768 add_stub_r(type,jaddr2,out,i,ar,i_regs,ccadj_,reglist);
3769 if(dops[i].opcode==0x3a) // SWC2
3770 if(!(i_regs->waswritten&(1<<dops[i].rs1)) && !HACK_ENABLED(NDHACK_NO_SMC_CHECK)) {
3771 #if defined(HOST_IMM8)
3772 int ir=get_reg(i_regs->regmap,INVCP);
3774 emit_cmpmem_indexedsr12_reg(ir,ar,1);
3776 emit_cmpmem_indexedsr12_imm(invalid_code,ar,1);
3778 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3779 emit_callne(invalidate_addr_reg[ar]);
3783 add_stub(INVCODE_STUB,jaddr3,out,reglist|(1<<HOST_CCREG),ar,0,0,0);
3786 if (dops[i].opcode==0x32) { // LWC2
3787 host_tempreg_acquire();
3788 cop2_put_dreg(copr,tl,HOST_TEMPREG);
3789 host_tempreg_release();
3793 static void cop2_assemble(int i, const struct regstat *i_regs)
3795 u_int copr = (source[i]>>11) & 0x1f;
3796 signed char temp = get_reg(i_regs->regmap, -1);
3798 if (!HACK_ENABLED(NDHACK_NO_STALLS)) {
3799 u_int reglist = reglist_exclude(get_host_reglist(i_regs->regmap), temp, -1);
3800 if (dops[i].opcode2 == 0 || dops[i].opcode2 == 2) { // MFC2/CFC2
3801 signed char tl = get_reg(i_regs->regmap, dops[i].rt1);
3802 reglist = reglist_exclude(reglist, tl, -1);
3804 cop2_do_stall_check(0, i, i_regs, reglist);
3806 if (dops[i].opcode2==0) { // MFC2
3807 signed char tl=get_reg(i_regs->regmap,dops[i].rt1);
3808 if(tl>=0&&dops[i].rt1!=0)
3809 cop2_get_dreg(copr,tl,temp);
3811 else if (dops[i].opcode2==4) { // MTC2
3812 signed char sl=get_reg(i_regs->regmap,dops[i].rs1);
3813 cop2_put_dreg(copr,sl,temp);
3815 else if (dops[i].opcode2==2) // CFC2
3817 signed char tl=get_reg(i_regs->regmap,dops[i].rt1);
3818 if(tl>=0&&dops[i].rt1!=0)
3819 emit_readword(®_cop2c[copr],tl);
3821 else if (dops[i].opcode2==6) // CTC2
3823 signed char sl=get_reg(i_regs->regmap,dops[i].rs1);
3832 emit_signextend16(sl,temp);
3835 c2op_ctc2_31_assemble(sl,temp);
3841 emit_writeword(temp,®_cop2c[copr]);
3846 static void do_unalignedwritestub(int n)
3848 assem_debug("do_unalignedwritestub %x\n",start+stubs[n].a*4);
3850 set_jump_target(stubs[n].addr, out);
3853 struct regstat *i_regs=(struct regstat *)stubs[n].c;
3854 int addr=stubs[n].b;
3855 u_int reglist=stubs[n].e;
3856 signed char *i_regmap=i_regs->regmap;
3857 int temp2=get_reg(i_regmap,FTEMP);
3859 rt=get_reg(i_regmap,dops[i].rs2);
3862 assert(dops[i].opcode==0x2a||dops[i].opcode==0x2e); // SWL/SWR only implemented
3864 reglist&=~(1<<temp2);
3866 // don't bother with it and call write handler
3869 int cc=get_reg(i_regmap,CCREG);
3871 emit_loadreg(CCREG,2);
3872 emit_addimm(cc<0?2:cc,(int)stubs[n].d+1,2);
3873 emit_far_call((dops[i].opcode==0x2a?jump_handle_swl:jump_handle_swr));
3874 emit_addimm(0,-((int)stubs[n].d+1),cc<0?2:cc);
3876 emit_storereg(CCREG,2);
3877 restore_regs(reglist);
3878 emit_jmp(stubs[n].retaddr); // return address
3881 #ifndef multdiv_assemble
3882 void multdiv_assemble(int i,struct regstat *i_regs)
3884 printf("Need multdiv_assemble for this architecture.\n");
3889 static void mov_assemble(int i, const struct regstat *i_regs)
3891 //if(dops[i].opcode2==0x10||dops[i].opcode2==0x12) { // MFHI/MFLO
3892 //if(dops[i].opcode2==0x11||dops[i].opcode2==0x13) { // MTHI/MTLO
3895 tl=get_reg(i_regs->regmap,dops[i].rt1);
3898 sl=get_reg(i_regs->regmap,dops[i].rs1);
3899 if(sl>=0) emit_mov(sl,tl);
3900 else emit_loadreg(dops[i].rs1,tl);
3903 if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) // MFHI/MFLO
3904 multdiv_do_stall(i, i_regs);
3907 // call interpreter, exception handler, things that change pc/regs/cycles ...
3908 static void call_c_cpu_handler(int i, const struct regstat *i_regs, int ccadj_, u_int pc, void *func)
3910 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3911 assert(ccreg==HOST_CCREG);
3912 assert(!is_delayslot);
3915 emit_movimm(pc,3); // Get PC
3916 emit_readword(&last_count,2);
3917 emit_writeword(3,&psxRegs.pc);
3918 emit_addimm(HOST_CCREG,ccadj_,HOST_CCREG);
3919 emit_add(2,HOST_CCREG,2);
3920 emit_writeword(2,&psxRegs.cycle);
3921 emit_far_call(func);
3922 emit_far_jump(jump_to_new_pc);
3925 static void syscall_assemble(int i, const struct regstat *i_regs, int ccadj_)
3927 emit_movimm(0x20,0); // cause code
3928 emit_movimm(0,1); // not in delay slot
3929 call_c_cpu_handler(i, i_regs, ccadj_, start+i*4, psxException);
3932 static void hlecall_assemble(int i, const struct regstat *i_regs, int ccadj_)
3934 void *hlefunc = psxNULL;
3935 uint32_t hleCode = source[i] & 0x03ffffff;
3936 if (hleCode < ARRAY_SIZE(psxHLEt))
3937 hlefunc = psxHLEt[hleCode];
3939 call_c_cpu_handler(i, i_regs, ccadj_, start + i*4+4, hlefunc);
3942 static void intcall_assemble(int i, const struct regstat *i_regs, int ccadj_)
3944 call_c_cpu_handler(i, i_regs, ccadj_, start + i*4, execI);
3947 static void speculate_mov(int rs,int rt)
3950 smrv_strong_next|=1<<rt;
3955 static void speculate_mov_weak(int rs,int rt)
3958 smrv_weak_next|=1<<rt;
3963 static void speculate_register_values(int i)
3966 memcpy(smrv,psxRegs.GPR.r,sizeof(smrv));
3967 // gp,sp are likely to stay the same throughout the block
3968 smrv_strong_next=(1<<28)|(1<<29)|(1<<30);
3969 smrv_weak_next=~smrv_strong_next;
3970 //printf(" llr %08x\n", smrv[4]);
3972 smrv_strong=smrv_strong_next;
3973 smrv_weak=smrv_weak_next;
3974 switch(dops[i].itype) {
3976 if ((smrv_strong>>dops[i].rs1)&1) speculate_mov(dops[i].rs1,dops[i].rt1);
3977 else if((smrv_strong>>dops[i].rs2)&1) speculate_mov(dops[i].rs2,dops[i].rt1);
3978 else if((smrv_weak>>dops[i].rs1)&1) speculate_mov_weak(dops[i].rs1,dops[i].rt1);
3979 else if((smrv_weak>>dops[i].rs2)&1) speculate_mov_weak(dops[i].rs2,dops[i].rt1);
3981 smrv_strong_next&=~(1<<dops[i].rt1);
3982 smrv_weak_next&=~(1<<dops[i].rt1);
3986 smrv_strong_next&=~(1<<dops[i].rt1);
3987 smrv_weak_next&=~(1<<dops[i].rt1);
3990 if(dops[i].rt1&&is_const(®s[i],dops[i].rt1)) {
3991 int value,hr=get_reg(regs[i].regmap,dops[i].rt1);
3993 if(get_final_value(hr,i,&value))
3994 smrv[dops[i].rt1]=value;
3995 else smrv[dops[i].rt1]=constmap[i][hr];
3996 smrv_strong_next|=1<<dops[i].rt1;
4000 if ((smrv_strong>>dops[i].rs1)&1) speculate_mov(dops[i].rs1,dops[i].rt1);
4001 else if((smrv_weak>>dops[i].rs1)&1) speculate_mov_weak(dops[i].rs1,dops[i].rt1);
4005 if(start<0x2000&&(dops[i].rt1==26||(smrv[dops[i].rt1]>>24)==0xa0)) {
4006 // special case for BIOS
4007 smrv[dops[i].rt1]=0xa0000000;
4008 smrv_strong_next|=1<<dops[i].rt1;
4015 smrv_strong_next&=~(1<<dops[i].rt1);
4016 smrv_weak_next&=~(1<<dops[i].rt1);
4020 if(dops[i].opcode2==0||dops[i].opcode2==2) { // MFC/CFC
4021 smrv_strong_next&=~(1<<dops[i].rt1);
4022 smrv_weak_next&=~(1<<dops[i].rt1);
4026 if (dops[i].opcode==0x32) { // LWC2
4027 smrv_strong_next&=~(1<<dops[i].rt1);
4028 smrv_weak_next&=~(1<<dops[i].rt1);
4034 printf("x %08x %08x %d %d c %08x %08x\n",smrv[r],start+i*4,
4035 ((smrv_strong>>r)&1),(smrv_weak>>r)&1,regs[i].isconst,regs[i].wasconst);
4039 static void ujump_assemble(int i, const struct regstat *i_regs);
4040 static void rjump_assemble(int i, const struct regstat *i_regs);
4041 static void cjump_assemble(int i, const struct regstat *i_regs);
4042 static void sjump_assemble(int i, const struct regstat *i_regs);
4043 static void pagespan_assemble(int i, const struct regstat *i_regs);
4045 static int assemble(int i, const struct regstat *i_regs, int ccadj_)
4048 switch (dops[i].itype) {
4050 alu_assemble(i, i_regs);
4053 imm16_assemble(i, i_regs);
4056 shift_assemble(i, i_regs);
4059 shiftimm_assemble(i, i_regs);
4062 load_assemble(i, i_regs, ccadj_);
4065 loadlr_assemble(i, i_regs, ccadj_);
4068 store_assemble(i, i_regs, ccadj_);
4071 storelr_assemble(i, i_regs, ccadj_);
4074 cop0_assemble(i, i_regs, ccadj_);
4077 cop1_assemble(i, i_regs);
4080 c1ls_assemble(i, i_regs);
4083 cop2_assemble(i, i_regs);
4086 c2ls_assemble(i, i_regs, ccadj_);
4089 c2op_assemble(i, i_regs);
4092 multdiv_assemble(i, i_regs);
4093 multdiv_prepare_stall(i, i_regs, ccadj_);
4096 mov_assemble(i, i_regs);
4099 syscall_assemble(i, i_regs, ccadj_);
4102 hlecall_assemble(i, i_regs, ccadj_);
4105 intcall_assemble(i, i_regs, ccadj_);
4108 ujump_assemble(i, i_regs);
4112 rjump_assemble(i, i_regs);
4116 cjump_assemble(i, i_regs);
4120 sjump_assemble(i, i_regs);
4124 pagespan_assemble(i, i_regs);
4128 // not handled, just skip
4136 static void ds_assemble(int i, const struct regstat *i_regs)
4138 speculate_register_values(i);
4140 switch (dops[i].itype) {
4149 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
4152 assemble(i, i_regs, ccadj[i]);
4157 // Is the branch target a valid internal jump?
4158 static int internal_branch(int addr)
4160 if(addr&1) return 0; // Indirect (register) jump
4161 if(addr>=start && addr<start+slen*4-4)
4168 static void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t u)
4171 for(hr=0;hr<HOST_REGS;hr++) {
4172 if(hr!=EXCLUDE_REG) {
4173 if(pre[hr]!=entry[hr]) {
4176 if(get_reg(entry,pre[hr])<0) {
4178 if(!((u>>pre[hr])&1))
4179 emit_storereg(pre[hr],hr);
4186 // Move from one register to another (no writeback)
4187 for(hr=0;hr<HOST_REGS;hr++) {
4188 if(hr!=EXCLUDE_REG) {
4189 if(pre[hr]!=entry[hr]) {
4190 if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
4192 if((nr=get_reg(entry,pre[hr]))>=0) {
4201 // Load the specified registers
4202 // This only loads the registers given as arguments because
4203 // we don't want to load things that will be overwritten
4204 static void load_regs(signed char entry[],signed char regmap[],int rs1,int rs2)
4208 for(hr=0;hr<HOST_REGS;hr++) {
4209 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4210 if(entry[hr]!=regmap[hr]) {
4211 if(regmap[hr]==rs1||regmap[hr]==rs2)
4218 emit_loadreg(regmap[hr],hr);
4226 // Load registers prior to the start of a loop
4227 // so that they are not loaded within the loop
4228 static void loop_preload(signed char pre[],signed char entry[])
4231 for(hr=0;hr<HOST_REGS;hr++) {
4232 if(hr!=EXCLUDE_REG) {
4233 if(pre[hr]!=entry[hr]) {
4235 if(get_reg(pre,entry[hr])<0) {
4236 assem_debug("loop preload:\n");
4237 //printf("loop preload: %d\n",hr);
4241 else if(entry[hr]<TEMPREG)
4243 emit_loadreg(entry[hr],hr);
4245 else if(entry[hr]-64<TEMPREG)
4247 emit_loadreg(entry[hr],hr);
4256 // Generate address for load/store instruction
4257 // goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
4258 void address_generation(int i, const struct regstat *i_regs, signed char entry[])
4260 if (dops[i].is_load || dops[i].is_store) {
4262 int agr=AGEN1+(i&1);
4263 if(dops[i].itype==LOAD) {
4264 ra=get_reg(i_regs->regmap,dops[i].rt1);
4265 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4268 if(dops[i].itype==LOADLR) {
4269 ra=get_reg(i_regs->regmap,FTEMP);
4271 if(dops[i].itype==STORE||dops[i].itype==STORELR) {
4272 ra=get_reg(i_regs->regmap,agr);
4273 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4275 if(dops[i].itype==C2LS) {
4276 if ((dops[i].opcode&0x3b)==0x31||(dops[i].opcode&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
4277 ra=get_reg(i_regs->regmap,FTEMP);
4278 else { // SWC1/SDC1/SWC2/SDC2
4279 ra=get_reg(i_regs->regmap,agr);
4280 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4283 int rs=get_reg(i_regs->regmap,dops[i].rs1);
4286 int c=(i_regs->wasconst>>rs)&1;
4287 if(dops[i].rs1==0) {
4288 // Using r0 as a base address
4289 if(!entry||entry[ra]!=agr) {
4290 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
4291 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4292 }else if (dops[i].opcode==0x1a||dops[i].opcode==0x1b) {
4293 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4295 emit_movimm(offset,ra);
4297 } // else did it in the previous cycle
4300 if(!entry||entry[ra]!=dops[i].rs1)
4301 emit_loadreg(dops[i].rs1,ra);
4302 //if(!entry||entry[ra]!=dops[i].rs1)
4303 // printf("poor load scheduling!\n");
4306 if(dops[i].rs1!=dops[i].rt1||dops[i].itype!=LOAD) {
4307 if(!entry||entry[ra]!=agr) {
4308 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
4309 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4310 }else if (dops[i].opcode==0x1a||dops[i].opcode==0x1b) {
4311 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4313 emit_movimm(constmap[i][rs]+offset,ra);
4314 regs[i].loadedconst|=1<<ra;
4316 } // else did it in the previous cycle
4317 } // else load_consts already did it
4319 if(offset&&!c&&dops[i].rs1) {
4321 emit_addimm(rs,offset,ra);
4323 emit_addimm(ra,offset,ra);
4328 // Preload constants for next instruction
4329 if (dops[i+1].is_load || dops[i+1].is_store) {
4332 agr=AGEN1+((i+1)&1);
4333 ra=get_reg(i_regs->regmap,agr);
4335 int rs=get_reg(regs[i+1].regmap,dops[i+1].rs1);
4336 int offset=imm[i+1];
4337 int c=(regs[i+1].wasconst>>rs)&1;
4338 if(c&&(dops[i+1].rs1!=dops[i+1].rt1||dops[i+1].itype!=LOAD)) {
4339 if (dops[i+1].opcode==0x22||dops[i+1].opcode==0x26) {
4340 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4341 }else if (dops[i+1].opcode==0x1a||dops[i+1].opcode==0x1b) {
4342 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4344 emit_movimm(constmap[i+1][rs]+offset,ra);
4345 regs[i+1].loadedconst|=1<<ra;
4348 else if(dops[i+1].rs1==0) {
4349 // Using r0 as a base address
4350 if (dops[i+1].opcode==0x22||dops[i+1].opcode==0x26) {
4351 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4352 }else if (dops[i+1].opcode==0x1a||dops[i+1].opcode==0x1b) {
4353 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4355 emit_movimm(offset,ra);
4362 static int get_final_value(int hr, int i, int *value)
4364 int reg=regs[i].regmap[hr];
4366 if(regs[i+1].regmap[hr]!=reg) break;
4367 if(!((regs[i+1].isconst>>hr)&1)) break;
4368 if(dops[i+1].bt) break;
4372 if (dops[i].is_jump) {
4373 *value=constmap[i][hr];
4377 if (dops[i+1].is_jump) {
4378 // Load in delay slot, out-of-order execution
4379 if(dops[i+2].itype==LOAD&&dops[i+2].rs1==reg&&dops[i+2].rt1==reg&&((regs[i+1].wasconst>>hr)&1))
4381 // Precompute load address
4382 *value=constmap[i][hr]+imm[i+2];
4386 if(dops[i+1].itype==LOAD&&dops[i+1].rs1==reg&&dops[i+1].rt1==reg)
4388 // Precompute load address
4389 *value=constmap[i][hr]+imm[i+1];
4390 //printf("c=%x imm=%lx\n",(long)constmap[i][hr],imm[i+1]);
4395 *value=constmap[i][hr];
4396 //printf("c=%lx\n",(long)constmap[i][hr]);
4397 if(i==slen-1) return 1;
4399 return !((unneeded_reg[i+1]>>reg)&1);
4402 // Load registers with known constants
4403 static void load_consts(signed char pre[],signed char regmap[],int i)
4406 // propagate loaded constant flags
4407 if(i==0||dops[i].bt)
4408 regs[i].loadedconst=0;
4410 for(hr=0;hr<HOST_REGS;hr++) {
4411 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((regs[i-1].isconst>>hr)&1)&&pre[hr]==regmap[hr]
4412 &®map[hr]==regs[i-1].regmap[hr]&&((regs[i-1].loadedconst>>hr)&1))
4414 regs[i].loadedconst|=1<<hr;
4419 for(hr=0;hr<HOST_REGS;hr++) {
4420 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4421 //if(entry[hr]!=regmap[hr]) {
4422 if(!((regs[i].loadedconst>>hr)&1)) {
4423 assert(regmap[hr]<64);
4424 if(((regs[i].isconst>>hr)&1)&®map[hr]>0) {
4425 int value,similar=0;
4426 if(get_final_value(hr,i,&value)) {
4427 // see if some other register has similar value
4428 for(hr2=0;hr2<HOST_REGS;hr2++) {
4429 if(hr2!=EXCLUDE_REG&&((regs[i].loadedconst>>hr2)&1)) {
4430 if(is_similar_value(value,constmap[i][hr2])) {
4438 if(get_final_value(hr2,i,&value2)) // is this needed?
4439 emit_movimm_from(value2,hr2,value,hr);
4441 emit_movimm(value,hr);
4447 emit_movimm(value,hr);
4450 regs[i].loadedconst|=1<<hr;
4457 static void load_all_consts(const signed char regmap[], u_int dirty, int i)
4461 for(hr=0;hr<HOST_REGS;hr++) {
4462 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) {
4463 assert(regmap[hr] < 64);
4464 if(((regs[i].isconst>>hr)&1)&®map[hr]>0) {
4465 int value=constmap[i][hr];
4470 emit_movimm(value,hr);
4477 // Write out all dirty registers (except cycle count)
4478 static void wb_dirtys(const signed char i_regmap[], uint64_t i_dirty)
4481 for(hr=0;hr<HOST_REGS;hr++) {
4482 if(hr!=EXCLUDE_REG) {
4483 if(i_regmap[hr]>0) {
4484 if(i_regmap[hr]!=CCREG) {
4485 if((i_dirty>>hr)&1) {
4486 assert(i_regmap[hr]<64);
4487 emit_storereg(i_regmap[hr],hr);
4495 // Write out dirty registers that we need to reload (pair with load_needed_regs)
4496 // This writes the registers not written by store_regs_bt
4497 static void wb_needed_dirtys(const signed char i_regmap[], uint64_t i_dirty, int addr)
4500 int t=(addr-start)>>2;
4501 for(hr=0;hr<HOST_REGS;hr++) {
4502 if(hr!=EXCLUDE_REG) {
4503 if(i_regmap[hr]>0) {
4504 if(i_regmap[hr]!=CCREG) {
4505 if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1)) {
4506 if((i_dirty>>hr)&1) {
4507 assert(i_regmap[hr]<64);
4508 emit_storereg(i_regmap[hr],hr);
4517 // Load all registers (except cycle count)
4518 static void load_all_regs(const signed char i_regmap[])
4521 for(hr=0;hr<HOST_REGS;hr++) {
4522 if(hr!=EXCLUDE_REG) {
4523 if(i_regmap[hr]==0) {
4527 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4529 emit_loadreg(i_regmap[hr],hr);
4535 // Load all current registers also needed by next instruction
4536 static void load_needed_regs(const signed char i_regmap[], const signed char next_regmap[])
4539 for(hr=0;hr<HOST_REGS;hr++) {
4540 if(hr!=EXCLUDE_REG) {
4541 if(get_reg(next_regmap,i_regmap[hr])>=0) {
4542 if(i_regmap[hr]==0) {
4546 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4548 emit_loadreg(i_regmap[hr],hr);
4555 // Load all regs, storing cycle count if necessary
4556 static void load_regs_entry(int t)
4559 if(dops[t].is_ds) emit_addimm(HOST_CCREG,CLOCK_ADJUST(1),HOST_CCREG);
4560 else if(ccadj[t]) emit_addimm(HOST_CCREG,-ccadj[t],HOST_CCREG);
4561 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4562 emit_storereg(CCREG,HOST_CCREG);
4565 for(hr=0;hr<HOST_REGS;hr++) {
4566 if(regs[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) {
4567 if(regs[t].regmap_entry[hr]==0) {
4570 else if(regs[t].regmap_entry[hr]!=CCREG)
4572 emit_loadreg(regs[t].regmap_entry[hr],hr);
4578 // Store dirty registers prior to branch
4579 void store_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
4581 if(internal_branch(addr))
4583 int t=(addr-start)>>2;
4585 for(hr=0;hr<HOST_REGS;hr++) {
4586 if(hr!=EXCLUDE_REG) {
4587 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4588 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1)) {
4589 if((i_dirty>>hr)&1) {
4590 assert(i_regmap[hr]<64);
4591 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4592 emit_storereg(i_regmap[hr],hr);
4601 // Branch out of this block, write out all dirty regs
4602 wb_dirtys(i_regmap,i_dirty);
4606 // Load all needed registers for branch target
4607 static void load_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
4609 //if(addr>=start && addr<(start+slen*4))
4610 if(internal_branch(addr))
4612 int t=(addr-start)>>2;
4614 // Store the cycle count before loading something else
4615 if(i_regmap[HOST_CCREG]!=CCREG) {
4616 assert(i_regmap[HOST_CCREG]==-1);
4618 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4619 emit_storereg(CCREG,HOST_CCREG);
4622 for(hr=0;hr<HOST_REGS;hr++) {
4623 if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) {
4624 if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4625 if(regs[t].regmap_entry[hr]==0) {
4628 else if(regs[t].regmap_entry[hr]!=CCREG)
4630 emit_loadreg(regs[t].regmap_entry[hr],hr);
4638 static int match_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
4640 if(addr>=start && addr<start+slen*4-4)
4642 int t=(addr-start)>>2;
4644 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4645 for(hr=0;hr<HOST_REGS;hr++)
4649 if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4651 if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
4658 if(i_regmap[hr]<TEMPREG)
4660 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4663 else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
4669 else // Same register but is it 32-bit or dirty?
4672 if(!((regs[t].dirty>>hr)&1))
4676 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4678 //printf("%x: dirty no match\n",addr);
4686 // Delay slots are not valid branch targets
4687 //if(t>0&&(dops[t-1].is_jump) return 0;
4688 // Delay slots require additional processing, so do not match
4689 if(dops[t].is_ds) return 0;
4694 for(hr=0;hr<HOST_REGS;hr++)
4700 if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4715 static void drc_dbg_emit_do_cmp(int i, int ccadj_)
4717 extern void do_insn_cmp();
4719 u_int hr, reglist = get_host_reglist(regs[i].regmap);
4721 assem_debug("//do_insn_cmp %08x\n", start+i*4);
4723 // write out changed consts to match the interpreter
4724 if (i > 0 && !dops[i].bt) {
4725 for (hr = 0; hr < HOST_REGS; hr++) {
4726 int reg = regs[i].regmap_entry[hr]; // regs[i-1].regmap[hr];
4727 if (hr == EXCLUDE_REG || reg < 0)
4729 if (!((regs[i-1].isconst >> hr) & 1))
4731 if (i > 1 && reg == regs[i-2].regmap[hr] && constmap[i-1][hr] == constmap[i-2][hr])
4733 emit_movimm(constmap[i-1][hr],0);
4734 emit_storereg(reg, 0);
4737 emit_movimm(start+i*4,0);
4738 emit_writeword(0,&pcaddr);
4739 int cc = get_reg(regs[i].regmap_entry, CCREG);
4741 emit_loadreg(CCREG, cc = 0);
4742 emit_addimm(cc, ccadj_, 0);
4743 emit_writeword(0, &psxRegs.cycle);
4744 emit_far_call(do_insn_cmp);
4745 //emit_readword(&cycle,0);
4746 //emit_addimm(0,2,0);
4747 //emit_writeword(0,&cycle);
4749 restore_regs(reglist);
4750 assem_debug("\\\\do_insn_cmp\n");
4753 #define drc_dbg_emit_do_cmp(x,y)
4756 // Used when a branch jumps into the delay slot of another branch
4757 static void ds_assemble_entry(int i)
4759 int t = (ba[i] - start) >> 2;
4760 int ccadj_ = -CLOCK_ADJUST(1);
4762 instr_addr[t] = out;
4763 assem_debug("Assemble delay slot at %x\n",ba[i]);
4764 assem_debug("<->\n");
4765 drc_dbg_emit_do_cmp(t, ccadj_);
4766 if(regs[t].regmap_entry[HOST_CCREG]==CCREG&®s[t].regmap[HOST_CCREG]!=CCREG)
4767 wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty);
4768 load_regs(regs[t].regmap_entry,regs[t].regmap,dops[t].rs1,dops[t].rs2);
4769 address_generation(t,®s[t],regs[t].regmap_entry);
4770 if (ram_offset && (dops[t].is_load || dops[t].is_store))
4771 load_regs(regs[t].regmap_entry,regs[t].regmap,ROREG,ROREG);
4772 if (dops[t].is_store)
4773 load_regs(regs[t].regmap_entry,regs[t].regmap,INVCP,INVCP);
4775 switch (dops[t].itype) {
4784 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
4787 assemble(t, ®s[t], ccadj_);
4789 store_regs_bt(regs[t].regmap,regs[t].dirty,ba[i]+4);
4790 load_regs_bt(regs[t].regmap,regs[t].dirty,ba[i]+4);
4791 if(internal_branch(ba[i]+4))
4792 assem_debug("branch: internal\n");
4794 assem_debug("branch: external\n");
4795 assert(internal_branch(ba[i]+4));
4796 add_to_linker(out,ba[i]+4,internal_branch(ba[i]+4));
4800 static void emit_extjump(void *addr, u_int target)
4802 emit_extjump2(addr, target, dyna_linker);
4805 static void emit_extjump_ds(void *addr, u_int target)
4807 emit_extjump2(addr, target, dyna_linker_ds);
4810 // Load 2 immediates optimizing for small code size
4811 static void emit_mov2imm_compact(int imm1,u_int rt1,int imm2,u_int rt2)
4813 emit_movimm(imm1,rt1);
4814 emit_movimm_from(imm1,rt1,imm2,rt2);
4817 static void do_cc(int i, const signed char i_regmap[], int *adj,
4818 int addr, int taken, int invert)
4820 int count, count_plus2;
4824 if(dops[i].itype==RJUMP)
4828 //if(ba[i]>=start && ba[i]<(start+slen*4))
4829 if(internal_branch(ba[i]))
4832 if(dops[t].is_ds) *adj=-CLOCK_ADJUST(1); // Branch into delay slot adds an extra cycle
4840 count_plus2 = count + CLOCK_ADJUST(2);
4841 if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4843 if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
4845 //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4846 emit_andimm(HOST_CCREG,3,HOST_CCREG);
4850 else if(*adj==0||invert) {
4851 int cycles = count_plus2;
4856 if(-NO_CYCLE_PENALTY_THR<rel&&rel<0)
4857 cycles=*adj+count+2-*adj;
4860 emit_addimm_and_set_flags(cycles, HOST_CCREG);
4866 emit_cmpimm(HOST_CCREG, -count_plus2);
4870 add_stub(CC_STUB,jaddr,idle?idle:out,(*adj==0||invert||idle)?0:count_plus2,i,addr,taken,0);
4873 static void do_ccstub(int n)
4876 assem_debug("do_ccstub %x\n",start+(u_int)stubs[n].b*4);
4877 set_jump_target(stubs[n].addr, out);
4879 if(stubs[n].d==NULLDS) {
4880 // Delay slot instruction is nullified ("likely" branch)
4881 wb_dirtys(regs[i].regmap,regs[i].dirty);
4883 else if(stubs[n].d!=TAKEN) {
4884 wb_dirtys(branch_regs[i].regmap,branch_regs[i].dirty);
4887 if(internal_branch(ba[i]))
4888 wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
4892 // Save PC as return address
4893 emit_movimm(stubs[n].c,EAX);
4894 emit_writeword(EAX,&pcaddr);
4898 // Return address depends on which way the branch goes
4899 if(dops[i].itype==CJUMP||dops[i].itype==SJUMP)
4901 int s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
4902 int s2l=get_reg(branch_regs[i].regmap,dops[i].rs2);
4908 else if(dops[i].rs2==0)
4913 #ifdef DESTRUCTIVE_WRITEBACK
4915 if((branch_regs[i].dirty>>s1l)&&1)
4916 emit_loadreg(dops[i].rs1,s1l);
4919 if((branch_regs[i].dirty>>s1l)&1)
4920 emit_loadreg(dops[i].rs2,s1l);
4923 if((branch_regs[i].dirty>>s2l)&1)
4924 emit_loadreg(dops[i].rs2,s2l);
4927 int addr=-1,alt=-1,ntaddr=-1;
4930 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4931 (branch_regs[i].regmap[hr]&63)!=dops[i].rs1 &&
4932 (branch_regs[i].regmap[hr]&63)!=dops[i].rs2 )
4940 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4941 (branch_regs[i].regmap[hr]&63)!=dops[i].rs1 &&
4942 (branch_regs[i].regmap[hr]&63)!=dops[i].rs2 )
4948 if((dops[i].opcode&0x2E)==6) // BLEZ/BGTZ needs another register
4952 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4953 (branch_regs[i].regmap[hr]&63)!=dops[i].rs1 &&
4954 (branch_regs[i].regmap[hr]&63)!=dops[i].rs2 )
4960 assert(hr<HOST_REGS);
4962 if((dops[i].opcode&0x2f)==4) // BEQ
4964 #ifdef HAVE_CMOV_IMM
4965 if(s2l>=0) emit_cmp(s1l,s2l);
4966 else emit_test(s1l,s1l);
4967 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
4969 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4970 if(s2l>=0) emit_cmp(s1l,s2l);
4971 else emit_test(s1l,s1l);
4972 emit_cmovne_reg(alt,addr);
4975 if((dops[i].opcode&0x2f)==5) // BNE
4977 #ifdef HAVE_CMOV_IMM
4978 if(s2l>=0) emit_cmp(s1l,s2l);
4979 else emit_test(s1l,s1l);
4980 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
4982 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
4983 if(s2l>=0) emit_cmp(s1l,s2l);
4984 else emit_test(s1l,s1l);
4985 emit_cmovne_reg(alt,addr);
4988 if((dops[i].opcode&0x2f)==6) // BLEZ
4990 //emit_movimm(ba[i],alt);
4991 //emit_movimm(start+i*4+8,addr);
4992 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4994 emit_cmovl_reg(alt,addr);
4996 if((dops[i].opcode&0x2f)==7) // BGTZ
4998 //emit_movimm(ba[i],addr);
4999 //emit_movimm(start+i*4+8,ntaddr);
5000 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
5002 emit_cmovl_reg(ntaddr,addr);
5004 if((dops[i].opcode==1)&&(dops[i].opcode2&0x2D)==0) // BLTZ
5006 //emit_movimm(ba[i],alt);
5007 //emit_movimm(start+i*4+8,addr);
5008 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5010 emit_cmovs_reg(alt,addr);
5012 if((dops[i].opcode==1)&&(dops[i].opcode2&0x2D)==1) // BGEZ
5014 //emit_movimm(ba[i],addr);
5015 //emit_movimm(start+i*4+8,alt);
5016 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5018 emit_cmovs_reg(alt,addr);
5020 if(dops[i].opcode==0x11 && dops[i].opcode2==0x08 ) {
5021 if(source[i]&0x10000) // BC1T
5023 //emit_movimm(ba[i],alt);
5024 //emit_movimm(start+i*4+8,addr);
5025 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5026 emit_testimm(s1l,0x800000);
5027 emit_cmovne_reg(alt,addr);
5031 //emit_movimm(ba[i],addr);
5032 //emit_movimm(start+i*4+8,alt);
5033 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5034 emit_testimm(s1l,0x800000);
5035 emit_cmovne_reg(alt,addr);
5038 emit_writeword(addr,&pcaddr);
5041 if(dops[i].itype==RJUMP)
5043 int r=get_reg(branch_regs[i].regmap,dops[i].rs1);
5044 if (ds_writes_rjump_rs(i)) {
5045 r=get_reg(branch_regs[i].regmap,RTEMP);
5047 emit_writeword(r,&pcaddr);
5049 else {SysPrintf("Unknown branch type in do_ccstub\n");abort();}
5051 // Update cycle count
5052 assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
5053 if(stubs[n].a) emit_addimm(HOST_CCREG,(int)stubs[n].a,HOST_CCREG);
5054 emit_far_call(cc_interrupt);
5055 if(stubs[n].a) emit_addimm(HOST_CCREG,-(int)stubs[n].a,HOST_CCREG);
5056 if(stubs[n].d==TAKEN) {
5057 if(internal_branch(ba[i]))
5058 load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
5059 else if(dops[i].itype==RJUMP) {
5060 if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
5061 emit_readword(&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
5063 emit_loadreg(dops[i].rs1,get_reg(branch_regs[i].regmap,dops[i].rs1));
5065 }else if(stubs[n].d==NOTTAKEN) {
5066 if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5067 else load_all_regs(branch_regs[i].regmap);
5068 }else if(stubs[n].d==NULLDS) {
5069 // Delay slot instruction is nullified ("likely" branch)
5070 if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
5071 else load_all_regs(regs[i].regmap);
5073 load_all_regs(branch_regs[i].regmap);
5075 if (stubs[n].retaddr)
5076 emit_jmp(stubs[n].retaddr);
5078 do_jump_vaddr(stubs[n].e);
5081 static void add_to_linker(void *addr, u_int target, int ext)
5083 assert(linkcount < ARRAY_SIZE(link_addr));
5084 link_addr[linkcount].addr = addr;
5085 link_addr[linkcount].target = target;
5086 link_addr[linkcount].ext = ext;
5090 static void ujump_assemble_write_ra(int i)
5093 unsigned int return_address;
5094 rt=get_reg(branch_regs[i].regmap,31);
5095 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5097 return_address=start+i*4+8;
5100 if(internal_branch(return_address)&&dops[i+1].rt1!=31) {
5101 int temp=-1; // note: must be ds-safe
5105 if(temp>=0) do_miniht_insert(return_address,rt,temp);
5106 else emit_movimm(return_address,rt);
5114 if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
5117 emit_movimm(return_address,rt); // PC into link register
5119 emit_prefetch(hash_table_get(return_address));
5125 static void ujump_assemble(int i, const struct regstat *i_regs)
5128 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5129 address_generation(i+1,i_regs,regs[i].regmap_entry);
5131 int temp=get_reg(branch_regs[i].regmap,PTEMP);
5132 if(dops[i].rt1==31&&temp>=0)
5134 signed char *i_regmap=i_regs->regmap;
5135 int return_address=start+i*4+8;
5136 if(get_reg(branch_regs[i].regmap,31)>0)
5137 if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
5140 if(dops[i].rt1==31&&(dops[i].rt1==dops[i+1].rs1||dops[i].rt1==dops[i+1].rs2)) {
5141 ujump_assemble_write_ra(i); // writeback ra for DS
5144 ds_assemble(i+1,i_regs);
5145 uint64_t bc_unneeded=branch_regs[i].u;
5146 bc_unneeded|=1|(1LL<<dops[i].rt1);
5147 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
5148 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG);
5149 if(!ra_done&&dops[i].rt1==31)
5150 ujump_assemble_write_ra(i);
5152 cc=get_reg(branch_regs[i].regmap,CCREG);
5153 assert(cc==HOST_CCREG);
5154 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5156 if(dops[i].rt1==31&&temp>=0) emit_prefetchreg(temp);
5158 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5159 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
5160 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5161 if(internal_branch(ba[i]))
5162 assem_debug("branch: internal\n");
5164 assem_debug("branch: external\n");
5165 if (internal_branch(ba[i]) && dops[(ba[i]-start)>>2].is_ds) {
5166 ds_assemble_entry(i);
5169 add_to_linker(out,ba[i],internal_branch(ba[i]));
5174 static void rjump_assemble_write_ra(int i)
5176 int rt,return_address;
5177 assert(dops[i+1].rt1!=dops[i].rt1);
5178 assert(dops[i+1].rt2!=dops[i].rt1);
5179 rt=get_reg(branch_regs[i].regmap,dops[i].rt1);
5180 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5182 return_address=start+i*4+8;
5186 if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
5189 emit_movimm(return_address,rt); // PC into link register
5191 emit_prefetch(hash_table_get(return_address));
5195 static void rjump_assemble(int i, const struct regstat *i_regs)
5200 rs=get_reg(branch_regs[i].regmap,dops[i].rs1);
5202 if (ds_writes_rjump_rs(i)) {
5203 // Delay slot abuse, make a copy of the branch address register
5204 temp=get_reg(branch_regs[i].regmap,RTEMP);
5206 assert(regs[i].regmap[temp]==RTEMP);
5210 address_generation(i+1,i_regs,regs[i].regmap_entry);
5214 if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5215 signed char *i_regmap=i_regs->regmap;
5216 int return_address=start+i*4+8;
5217 if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
5222 if(dops[i].rs1==31) {
5223 int rh=get_reg(regs[i].regmap,RHASH);
5224 if(rh>=0) do_preload_rhash(rh);
5227 if(dops[i].rt1!=0&&(dops[i].rt1==dops[i+1].rs1||dops[i].rt1==dops[i+1].rs2)) {
5228 rjump_assemble_write_ra(i);
5231 ds_assemble(i+1,i_regs);
5232 uint64_t bc_unneeded=branch_regs[i].u;
5233 bc_unneeded|=1|(1LL<<dops[i].rt1);
5234 bc_unneeded&=~(1LL<<dops[i].rs1);
5235 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
5236 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,CCREG);
5237 if(!ra_done&&dops[i].rt1!=0)
5238 rjump_assemble_write_ra(i);
5239 cc=get_reg(branch_regs[i].regmap,CCREG);
5240 assert(cc==HOST_CCREG);
5243 int rh=get_reg(branch_regs[i].regmap,RHASH);
5244 int ht=get_reg(branch_regs[i].regmap,RHTBL);
5245 if(dops[i].rs1==31) {
5246 if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5247 do_preload_rhtbl(ht);
5251 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1);
5252 #ifdef DESTRUCTIVE_WRITEBACK
5253 if((branch_regs[i].dirty>>rs)&1) {
5254 if(dops[i].rs1!=dops[i+1].rt1&&dops[i].rs1!=dops[i+1].rt2) {
5255 emit_loadreg(dops[i].rs1,rs);
5260 if(dops[i].rt1==31&&temp>=0) emit_prefetchreg(temp);
5263 if(dops[i].rs1==31) {
5264 do_miniht_load(ht,rh);
5267 //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5268 //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5270 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG);
5271 add_stub(CC_STUB,out,NULL,0,i,-1,TAKEN,rs);
5272 if(dops[i+1].itype==COP0&&(source[i+1]&0x3f)==0x10)
5273 // special case for RFE
5277 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1);
5279 if(dops[i].rs1==31) {
5280 do_miniht_jump(rs,rh,ht);
5287 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5288 if(dops[i].rt1!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5292 static void cjump_assemble(int i, const struct regstat *i_regs)
5294 const signed char *i_regmap = i_regs->regmap;
5297 match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5298 assem_debug("match=%d\n",match);
5300 int unconditional=0,nop=0;
5302 int internal=internal_branch(ba[i]);
5303 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5304 if(!match) invert=1;
5305 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5306 if(i>(ba[i]-start)>>2) invert=1;
5309 invert=1; // because of near cond. branches
5313 s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
5314 s2l=get_reg(branch_regs[i].regmap,dops[i].rs2);
5317 s1l=get_reg(i_regmap,dops[i].rs1);
5318 s2l=get_reg(i_regmap,dops[i].rs2);
5320 if(dops[i].rs1==0&&dops[i].rs2==0)
5322 if(dops[i].opcode&1) nop=1;
5323 else unconditional=1;
5324 //assert(dops[i].opcode!=5);
5325 //assert(dops[i].opcode!=7);
5326 //assert(dops[i].opcode!=0x15);
5327 //assert(dops[i].opcode!=0x17);
5329 else if(dops[i].rs1==0)
5334 else if(dops[i].rs2==0)
5340 // Out of order execution (delay slot first)
5342 address_generation(i+1,i_regs,regs[i].regmap_entry);
5343 ds_assemble(i+1,i_regs);
5345 uint64_t bc_unneeded=branch_regs[i].u;
5346 bc_unneeded&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
5348 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
5349 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,dops[i].rs2);
5350 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG);
5351 cc=get_reg(branch_regs[i].regmap,CCREG);
5352 assert(cc==HOST_CCREG);
5354 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5355 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5356 //assem_debug("cycle count (adj)\n");
5358 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5359 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5360 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
5361 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5363 assem_debug("branch: internal\n");
5365 assem_debug("branch: external\n");
5366 if (internal && dops[(ba[i]-start)>>2].is_ds) {
5367 ds_assemble_entry(i);
5370 add_to_linker(out,ba[i],internal);
5373 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5374 if(((u_int)out)&7) emit_addnop(0);
5379 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc);
5382 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5385 void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL;
5386 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5387 if(adj&&!invert) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
5389 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5391 if(dops[i].opcode==4) // BEQ
5393 if(s2l>=0) emit_cmp(s1l,s2l);
5394 else emit_test(s1l,s1l);
5399 add_to_linker(out,ba[i],internal);
5403 if(dops[i].opcode==5) // BNE
5405 if(s2l>=0) emit_cmp(s1l,s2l);
5406 else emit_test(s1l,s1l);
5411 add_to_linker(out,ba[i],internal);
5415 if(dops[i].opcode==6) // BLEZ
5422 add_to_linker(out,ba[i],internal);
5426 if(dops[i].opcode==7) // BGTZ
5433 add_to_linker(out,ba[i],internal);
5438 if(taken) set_jump_target(taken, out);
5439 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5440 if (match && (!internal || !dops[(ba[i]-start)>>2].is_ds)) {
5442 emit_addimm(cc,-adj,cc);
5443 add_to_linker(out,ba[i],internal);
5446 add_to_linker(out,ba[i],internal*2);
5452 if(adj) emit_addimm(cc,-adj,cc);
5453 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5454 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5456 assem_debug("branch: internal\n");
5458 assem_debug("branch: external\n");
5459 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
5460 ds_assemble_entry(i);
5463 add_to_linker(out,ba[i],internal);
5467 set_jump_target(nottaken, out);
5470 if(nottaken1) set_jump_target(nottaken1, out);
5472 if(!invert) emit_addimm(cc,adj,cc);
5474 } // (!unconditional)
5478 // In-order execution (branch first)
5479 void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL;
5480 if(!unconditional&&!nop) {
5481 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5483 if((dops[i].opcode&0x2f)==4) // BEQ
5485 if(s2l>=0) emit_cmp(s1l,s2l);
5486 else emit_test(s1l,s1l);
5490 if((dops[i].opcode&0x2f)==5) // BNE
5492 if(s2l>=0) emit_cmp(s1l,s2l);
5493 else emit_test(s1l,s1l);
5497 if((dops[i].opcode&0x2f)==6) // BLEZ
5503 if((dops[i].opcode&0x2f)==7) // BGTZ
5509 } // if(!unconditional)
5511 uint64_t ds_unneeded=branch_regs[i].u;
5512 ds_unneeded&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
5516 if(taken) set_jump_target(taken, out);
5517 assem_debug("1:\n");
5518 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5520 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5521 address_generation(i+1,&branch_regs[i],0);
5523 load_regs(regs[i].regmap,branch_regs[i].regmap,ROREG,ROREG);
5524 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
5525 ds_assemble(i+1,&branch_regs[i]);
5526 cc=get_reg(branch_regs[i].regmap,CCREG);
5528 emit_loadreg(CCREG,cc=HOST_CCREG);
5529 // CHECK: Is the following instruction (fall thru) allocated ok?
5531 assert(cc==HOST_CCREG);
5532 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5533 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5534 assem_debug("cycle count (adj)\n");
5535 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
5536 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5538 assem_debug("branch: internal\n");
5540 assem_debug("branch: external\n");
5541 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
5542 ds_assemble_entry(i);
5545 add_to_linker(out,ba[i],internal);
5550 if(!unconditional) {
5551 if(nottaken1) set_jump_target(nottaken1, out);
5552 set_jump_target(nottaken, out);
5553 assem_debug("2:\n");
5554 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5556 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5557 address_generation(i+1,&branch_regs[i],0);
5559 load_regs(regs[i].regmap,branch_regs[i].regmap,ROREG,ROREG);
5560 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
5561 ds_assemble(i+1,&branch_regs[i]);
5562 cc=get_reg(branch_regs[i].regmap,CCREG);
5564 // Cycle count isn't in a register, temporarily load it then write it out
5565 emit_loadreg(CCREG,HOST_CCREG);
5566 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG);
5569 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5570 emit_storereg(CCREG,HOST_CCREG);
5573 cc=get_reg(i_regmap,CCREG);
5574 assert(cc==HOST_CCREG);
5575 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc);
5578 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5584 static void sjump_assemble(int i, const struct regstat *i_regs)
5586 const signed char *i_regmap = i_regs->regmap;
5589 match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5590 assem_debug("smatch=%d\n",match);
5592 int unconditional=0,nevertaken=0;
5594 int internal=internal_branch(ba[i]);
5595 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5596 if(!match) invert=1;
5597 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5598 if(i>(ba[i]-start)>>2) invert=1;
5601 invert=1; // because of near cond. branches
5604 //if(dops[i].opcode2>=0x10) return; // FIXME (BxxZAL)
5605 //assert(dops[i].opcode2<0x10||dops[i].rs1==0); // FIXME (BxxZAL)
5608 s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
5611 s1l=get_reg(i_regmap,dops[i].rs1);
5615 if(dops[i].opcode2&1) unconditional=1;
5617 // These are never taken (r0 is never less than zero)
5618 //assert(dops[i].opcode2!=0);
5619 //assert(dops[i].opcode2!=2);
5620 //assert(dops[i].opcode2!=0x10);
5621 //assert(dops[i].opcode2!=0x12);
5625 // Out of order execution (delay slot first)
5627 address_generation(i+1,i_regs,regs[i].regmap_entry);
5628 ds_assemble(i+1,i_regs);
5630 uint64_t bc_unneeded=branch_regs[i].u;
5631 bc_unneeded&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
5633 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
5634 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,dops[i].rs1);
5635 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG);
5636 if(dops[i].rt1==31) {
5637 int rt,return_address;
5638 rt=get_reg(branch_regs[i].regmap,31);
5639 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5641 // Save the PC even if the branch is not taken
5642 return_address=start+i*4+8;
5643 emit_movimm(return_address,rt); // PC into link register
5645 if(!nevertaken) emit_prefetch(hash_table_get(return_address));
5649 cc=get_reg(branch_regs[i].regmap,CCREG);
5650 assert(cc==HOST_CCREG);
5652 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5653 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5654 assem_debug("cycle count (adj)\n");
5656 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5657 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5658 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
5659 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5661 assem_debug("branch: internal\n");
5663 assem_debug("branch: external\n");
5664 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
5665 ds_assemble_entry(i);
5668 add_to_linker(out,ba[i],internal);
5671 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5672 if(((u_int)out)&7) emit_addnop(0);
5676 else if(nevertaken) {
5677 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc);
5680 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5683 void *nottaken = NULL;
5684 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5685 if(adj&&!invert) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
5688 if((dops[i].opcode2&0xf)==0) // BLTZ/BLTZAL
5695 add_to_linker(out,ba[i],internal);
5699 if((dops[i].opcode2&0xf)==1) // BGEZ/BLTZAL
5706 add_to_linker(out,ba[i],internal);
5713 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5714 if (match && (!internal || !dops[(ba[i] - start) >> 2].is_ds)) {
5716 emit_addimm(cc,-adj,cc);
5717 add_to_linker(out,ba[i],internal);
5720 add_to_linker(out,ba[i],internal*2);
5726 if(adj) emit_addimm(cc,-adj,cc);
5727 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5728 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5730 assem_debug("branch: internal\n");
5732 assem_debug("branch: external\n");
5733 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
5734 ds_assemble_entry(i);
5737 add_to_linker(out,ba[i],internal);
5741 set_jump_target(nottaken, out);
5745 if(!invert) emit_addimm(cc,adj,cc);
5747 } // (!unconditional)
5751 // In-order execution (branch first)
5753 void *nottaken = NULL;
5754 if(dops[i].rt1==31) {
5755 int rt,return_address;
5756 rt=get_reg(branch_regs[i].regmap,31);
5758 // Save the PC even if the branch is not taken
5759 return_address=start+i*4+8;
5760 emit_movimm(return_address,rt); // PC into link register
5762 emit_prefetch(hash_table_get(return_address));
5766 if(!unconditional) {
5767 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5769 if((dops[i].opcode2&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
5775 if((dops[i].opcode2&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
5781 } // if(!unconditional)
5783 uint64_t ds_unneeded=branch_regs[i].u;
5784 ds_unneeded&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
5788 //assem_debug("1:\n");
5789 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5791 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5792 address_generation(i+1,&branch_regs[i],0);
5794 load_regs(regs[i].regmap,branch_regs[i].regmap,ROREG,ROREG);
5795 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
5796 ds_assemble(i+1,&branch_regs[i]);
5797 cc=get_reg(branch_regs[i].regmap,CCREG);
5799 emit_loadreg(CCREG,cc=HOST_CCREG);
5800 // CHECK: Is the following instruction (fall thru) allocated ok?
5802 assert(cc==HOST_CCREG);
5803 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5804 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5805 assem_debug("cycle count (adj)\n");
5806 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
5807 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5809 assem_debug("branch: internal\n");
5811 assem_debug("branch: external\n");
5812 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
5813 ds_assemble_entry(i);
5816 add_to_linker(out,ba[i],internal);
5821 if(!unconditional) {
5822 set_jump_target(nottaken, out);
5823 assem_debug("1:\n");
5824 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5825 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5826 address_generation(i+1,&branch_regs[i],0);
5827 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG);
5828 ds_assemble(i+1,&branch_regs[i]);
5829 cc=get_reg(branch_regs[i].regmap,CCREG);
5831 // Cycle count isn't in a register, temporarily load it then write it out
5832 emit_loadreg(CCREG,HOST_CCREG);
5833 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG);
5836 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5837 emit_storereg(CCREG,HOST_CCREG);
5840 cc=get_reg(i_regmap,CCREG);
5841 assert(cc==HOST_CCREG);
5842 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc);
5845 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5851 static void pagespan_assemble(int i, const struct regstat *i_regs)
5853 int s1l=get_reg(i_regs->regmap,dops[i].rs1);
5854 int s2l=get_reg(i_regs->regmap,dops[i].rs2);
5856 void *nottaken = NULL;
5857 int unconditional=0;
5863 else if(dops[i].rs2==0)
5868 int addr=-1,alt=-1,ntaddr=-1;
5869 if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
5873 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5874 (i_regs->regmap[hr]&63)!=dops[i].rs1 &&
5875 (i_regs->regmap[hr]&63)!=dops[i].rs2 )
5884 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
5885 (i_regs->regmap[hr]&63)!=dops[i].rs1 &&
5886 (i_regs->regmap[hr]&63)!=dops[i].rs2 )
5892 if((dops[i].opcode&0x2E)==6) // BLEZ/BGTZ needs another register
5896 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
5897 (i_regs->regmap[hr]&63)!=dops[i].rs1 &&
5898 (i_regs->regmap[hr]&63)!=dops[i].rs2 )
5905 assert(hr<HOST_REGS);
5906 if((dops[i].opcode&0x2e)==4||dops[i].opcode==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
5907 load_regs(regs[i].regmap_entry,regs[i].regmap,CCREG,CCREG);
5909 emit_addimm(HOST_CCREG, ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG);
5910 if(dops[i].opcode==2) // J
5914 if(dops[i].opcode==3) // JAL
5917 int rt=get_reg(i_regs->regmap,31);
5918 emit_movimm(start+i*4+8,rt);
5921 if(dops[i].opcode==0&&(dops[i].opcode2&0x3E)==8) // JR/JALR
5924 if(dops[i].opcode2==9) // JALR
5926 int rt=get_reg(i_regs->regmap,dops[i].rt1);
5927 emit_movimm(start+i*4+8,rt);
5930 if((dops[i].opcode&0x3f)==4) // BEQ
5932 if(dops[i].rs1==dops[i].rs2)
5937 #ifdef HAVE_CMOV_IMM
5939 if(s2l>=0) emit_cmp(s1l,s2l);
5940 else emit_test(s1l,s1l);
5941 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
5947 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5948 if(s2l>=0) emit_cmp(s1l,s2l);
5949 else emit_test(s1l,s1l);
5950 emit_cmovne_reg(alt,addr);
5953 if((dops[i].opcode&0x3f)==5) // BNE
5955 #ifdef HAVE_CMOV_IMM
5956 if(s2l>=0) emit_cmp(s1l,s2l);
5957 else emit_test(s1l,s1l);
5958 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
5961 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
5962 if(s2l>=0) emit_cmp(s1l,s2l);
5963 else emit_test(s1l,s1l);
5964 emit_cmovne_reg(alt,addr);
5967 if((dops[i].opcode&0x3f)==0x14) // BEQL
5969 if(s2l>=0) emit_cmp(s1l,s2l);
5970 else emit_test(s1l,s1l);
5971 if(nottaken) set_jump_target(nottaken, out);
5975 if((dops[i].opcode&0x3f)==0x15) // BNEL
5977 if(s2l>=0) emit_cmp(s1l,s2l);
5978 else emit_test(s1l,s1l);
5981 if(taken) set_jump_target(taken, out);
5983 if((dops[i].opcode&0x3f)==6) // BLEZ
5985 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5987 emit_cmovl_reg(alt,addr);
5989 if((dops[i].opcode&0x3f)==7) // BGTZ
5991 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
5993 emit_cmovl_reg(ntaddr,addr);
5995 if((dops[i].opcode&0x3f)==0x16) // BLEZL
5997 assert((dops[i].opcode&0x3f)!=0x16);
5999 if((dops[i].opcode&0x3f)==0x17) // BGTZL
6001 assert((dops[i].opcode&0x3f)!=0x17);
6003 assert(dops[i].opcode!=1); // BLTZ/BGEZ
6005 //FIXME: Check CSREG
6006 if(dops[i].opcode==0x11 && dops[i].opcode2==0x08 ) {
6007 if((source[i]&0x30000)==0) // BC1F
6009 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6010 emit_testimm(s1l,0x800000);
6011 emit_cmovne_reg(alt,addr);
6013 if((source[i]&0x30000)==0x10000) // BC1T
6015 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6016 emit_testimm(s1l,0x800000);
6017 emit_cmovne_reg(alt,addr);
6019 if((source[i]&0x30000)==0x20000) // BC1FL
6021 emit_testimm(s1l,0x800000);
6025 if((source[i]&0x30000)==0x30000) // BC1TL
6027 emit_testimm(s1l,0x800000);
6033 assert(i_regs->regmap[HOST_CCREG]==CCREG);
6034 wb_dirtys(regs[i].regmap,regs[i].dirty);
6037 emit_movimm(ba[i],HOST_BTREG);
6039 else if(addr!=HOST_BTREG)
6041 emit_mov(addr,HOST_BTREG);
6043 void *branch_addr=out;
6045 int target_addr=start+i*4+5;
6047 void *compiled_target_addr=check_addr(target_addr);
6048 emit_extjump_ds(branch_addr, target_addr);
6049 if(compiled_target_addr) {
6050 set_jump_target(branch_addr, compiled_target_addr);
6051 add_jump_out(target_addr,stub);
6053 else set_jump_target(branch_addr, stub);
6056 // Assemble the delay slot for the above
6057 static void pagespan_ds()
6059 assem_debug("initial delay slot:\n");
6060 u_int vaddr=start+1;
6061 u_int page=get_page(vaddr);
6062 u_int vpage=get_vpage(vaddr);
6063 ll_add(jump_dirty+vpage,vaddr,(void *)out);
6064 do_dirty_stub_ds(slen*4);
6065 ll_add(jump_in+page,vaddr,(void *)out);
6066 assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6067 if(regs[0].regmap[HOST_CCREG]!=CCREG)
6068 wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty);
6069 if(regs[0].regmap[HOST_BTREG]!=BTREG)
6070 emit_writeword(HOST_BTREG,&branch_target);
6071 load_regs(regs[0].regmap_entry,regs[0].regmap,dops[0].rs1,dops[0].rs2);
6072 address_generation(0,®s[0],regs[0].regmap_entry);
6073 if (ram_offset && (dops[0].is_load || dops[0].is_store))
6074 load_regs(regs[0].regmap_entry,regs[0].regmap,ROREG,ROREG);
6075 if (dops[0].is_store)
6076 load_regs(regs[0].regmap_entry,regs[0].regmap,INVCP,INVCP);
6078 switch (dops[0].itype) {
6087 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
6090 assemble(0, ®s[0], 0);
6092 int btaddr=get_reg(regs[0].regmap,BTREG);
6094 btaddr=get_reg(regs[0].regmap,-1);
6095 emit_readword(&branch_target,btaddr);
6097 assert(btaddr!=HOST_CCREG);
6098 if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6100 host_tempreg_acquire();
6101 emit_movimm(start+4,HOST_TEMPREG);
6102 emit_cmp(btaddr,HOST_TEMPREG);
6103 host_tempreg_release();
6105 emit_cmpimm(btaddr,start+4);
6109 store_regs_bt(regs[0].regmap,regs[0].dirty,-1);
6110 do_jump_vaddr(btaddr);
6111 set_jump_target(branch, out);
6112 store_regs_bt(regs[0].regmap,regs[0].dirty,start+4);
6113 load_regs_bt(regs[0].regmap,regs[0].dirty,start+4);
6116 // Basic liveness analysis for MIPS registers
6117 void unneeded_registers(int istart,int iend,int r)
6120 uint64_t u,gte_u,b,gte_b;
6121 uint64_t temp_u,temp_gte_u=0;
6122 uint64_t gte_u_unknown=0;
6123 if (HACK_ENABLED(NDHACK_GTE_UNNEEDED))
6127 gte_u=gte_u_unknown;
6129 //u=unneeded_reg[iend+1];
6131 gte_u=gte_unneeded[iend+1];
6134 for (i=iend;i>=istart;i--)
6136 //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
6139 // If subroutine call, flag return address as a possible branch target
6140 if(dops[i].rt1==31 && i<slen-2) dops[i+2].bt=1;
6142 if(ba[i]<start || ba[i]>=(start+slen*4))
6144 // Branch out of this block, flush all regs
6146 gte_u=gte_u_unknown;
6147 branch_unneeded_reg[i]=u;
6148 // Merge in delay slot
6149 u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
6150 u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
6153 gte_u&=~gte_rs[i+1];
6157 // Internal branch, flag target
6158 dops[(ba[i]-start)>>2].bt=1;
6159 if(ba[i]<=start+i*4) {
6161 if(dops[i].is_ujump)
6163 // Unconditional branch
6167 // Conditional branch (not taken case)
6168 temp_u=unneeded_reg[i+2];
6169 temp_gte_u&=gte_unneeded[i+2];
6171 // Merge in delay slot
6172 temp_u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
6173 temp_u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
6175 temp_gte_u|=gte_rt[i+1];
6176 temp_gte_u&=~gte_rs[i+1];
6177 temp_u|=(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2);
6178 temp_u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
6180 temp_gte_u|=gte_rt[i];
6181 temp_gte_u&=~gte_rs[i];
6182 unneeded_reg[i]=temp_u;
6183 gte_unneeded[i]=temp_gte_u;
6184 // Only go three levels deep. This recursion can take an
6185 // excessive amount of time if there are a lot of nested loops.
6187 unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6189 unneeded_reg[(ba[i]-start)>>2]=1;
6190 gte_unneeded[(ba[i]-start)>>2]=gte_u_unknown;
6193 if (dops[i].is_ujump)
6195 // Unconditional branch
6196 u=unneeded_reg[(ba[i]-start)>>2];
6197 gte_u=gte_unneeded[(ba[i]-start)>>2];
6198 branch_unneeded_reg[i]=u;
6199 // Merge in delay slot
6200 u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
6201 u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
6204 gte_u&=~gte_rs[i+1];
6206 // Conditional branch
6207 b=unneeded_reg[(ba[i]-start)>>2];
6208 gte_b=gte_unneeded[(ba[i]-start)>>2];
6209 branch_unneeded_reg[i]=b;
6210 // Branch delay slot
6211 b|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
6212 b&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
6215 gte_b&=~gte_rs[i+1];
6219 branch_unneeded_reg[i]&=unneeded_reg[i+2];
6221 branch_unneeded_reg[i]=1;
6227 else if(dops[i].itype==SYSCALL||dops[i].itype==HLECALL||dops[i].itype==INTCALL)
6229 // SYSCALL instruction (software interrupt)
6232 else if(dops[i].itype==COP0 && (source[i]&0x3f)==0x18)
6234 // ERET instruction (return from interrupt)
6238 // Written registers are unneeded
6239 u|=1LL<<dops[i].rt1;
6240 u|=1LL<<dops[i].rt2;
6242 // Accessed registers are needed
6243 u&=~(1LL<<dops[i].rs1);
6244 u&=~(1LL<<dops[i].rs2);
6246 if(gte_rs[i]&&dops[i].rt1&&(unneeded_reg[i+1]&(1ll<<dops[i].rt1)))
6247 gte_u|=gte_rs[i]>e_unneeded[i+1]; // MFC2/CFC2 to dead register, unneeded
6248 // Source-target dependencies
6249 // R0 is always unneeded
6253 gte_unneeded[i]=gte_u;
6255 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
6258 for(r=1;r<=CCREG;r++) {
6259 if((unneeded_reg[i]>>r)&1) {
6260 if(r==HIREG) printf(" HI");
6261 else if(r==LOREG) printf(" LO");
6262 else printf(" r%d",r);
6270 // Write back dirty registers as soon as we will no longer modify them,
6271 // so that we don't end up with lots of writes at the branches.
6272 void clean_registers(int istart,int iend,int wr)
6276 u_int will_dirty_i,will_dirty_next,temp_will_dirty;
6277 u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
6279 will_dirty_i=will_dirty_next=0;
6280 wont_dirty_i=wont_dirty_next=0;
6282 will_dirty_i=will_dirty_next=will_dirty[iend+1];
6283 wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
6285 for (i=iend;i>=istart;i--)
6289 if(ba[i]<start || ba[i]>=(start+slen*4))
6291 // Branch out of this block, flush all regs
6292 if (dops[i].is_ujump)
6294 // Unconditional branch
6297 // Merge in delay slot (will dirty)
6298 for(r=0;r<HOST_REGS;r++) {
6299 if(r!=EXCLUDE_REG) {
6300 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6301 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6302 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6303 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
6304 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6305 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6306 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6307 if((regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6308 if((regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6309 if((regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6310 if((regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
6311 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6312 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6313 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6319 // Conditional branch
6321 wont_dirty_i=wont_dirty_next;
6322 // Merge in delay slot (will dirty)
6323 for(r=0;r<HOST_REGS;r++) {
6324 if(r!=EXCLUDE_REG) {
6325 if (1) { // !dops[i].likely) {
6326 // Might not dirty if likely branch is not taken
6327 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6328 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6329 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6330 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
6331 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6332 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
6333 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6334 //if((regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6335 //if((regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6336 if((regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6337 if((regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
6338 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6339 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6340 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6345 // Merge in delay slot (wont dirty)
6346 for(r=0;r<HOST_REGS;r++) {
6347 if(r!=EXCLUDE_REG) {
6348 if((regs[i].regmap[r]&63)==dops[i].rt1) wont_dirty_i|=1<<r;
6349 if((regs[i].regmap[r]&63)==dops[i].rt2) wont_dirty_i|=1<<r;
6350 if((regs[i].regmap[r]&63)==dops[i+1].rt1) wont_dirty_i|=1<<r;
6351 if((regs[i].regmap[r]&63)==dops[i+1].rt2) wont_dirty_i|=1<<r;
6352 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6353 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) wont_dirty_i|=1<<r;
6354 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) wont_dirty_i|=1<<r;
6355 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) wont_dirty_i|=1<<r;
6356 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) wont_dirty_i|=1<<r;
6357 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6361 #ifndef DESTRUCTIVE_WRITEBACK
6362 branch_regs[i].dirty&=wont_dirty_i;
6364 branch_regs[i].dirty|=will_dirty_i;
6370 if(ba[i]<=start+i*4) {
6372 if (dops[i].is_ujump)
6374 // Unconditional branch
6377 // Merge in delay slot (will dirty)
6378 for(r=0;r<HOST_REGS;r++) {
6379 if(r!=EXCLUDE_REG) {
6380 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) temp_will_dirty|=1<<r;
6381 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) temp_will_dirty|=1<<r;
6382 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) temp_will_dirty|=1<<r;
6383 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) temp_will_dirty|=1<<r;
6384 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
6385 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
6386 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
6387 if((regs[i].regmap[r]&63)==dops[i].rt1) temp_will_dirty|=1<<r;
6388 if((regs[i].regmap[r]&63)==dops[i].rt2) temp_will_dirty|=1<<r;
6389 if((regs[i].regmap[r]&63)==dops[i+1].rt1) temp_will_dirty|=1<<r;
6390 if((regs[i].regmap[r]&63)==dops[i+1].rt2) temp_will_dirty|=1<<r;
6391 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
6392 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
6393 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
6397 // Conditional branch (not taken case)
6398 temp_will_dirty=will_dirty_next;
6399 temp_wont_dirty=wont_dirty_next;
6400 // Merge in delay slot (will dirty)
6401 for(r=0;r<HOST_REGS;r++) {
6402 if(r!=EXCLUDE_REG) {
6403 if (1) { // !dops[i].likely) {
6404 // Will not dirty if likely branch is not taken
6405 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) temp_will_dirty|=1<<r;
6406 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) temp_will_dirty|=1<<r;
6407 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) temp_will_dirty|=1<<r;
6408 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) temp_will_dirty|=1<<r;
6409 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
6410 if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
6411 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
6412 //if((regs[i].regmap[r]&63)==dops[i].rt1) temp_will_dirty|=1<<r;
6413 //if((regs[i].regmap[r]&63)==dops[i].rt2) temp_will_dirty|=1<<r;
6414 if((regs[i].regmap[r]&63)==dops[i+1].rt1) temp_will_dirty|=1<<r;
6415 if((regs[i].regmap[r]&63)==dops[i+1].rt2) temp_will_dirty|=1<<r;
6416 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
6417 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
6418 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
6423 // Merge in delay slot (wont dirty)
6424 for(r=0;r<HOST_REGS;r++) {
6425 if(r!=EXCLUDE_REG) {
6426 if((regs[i].regmap[r]&63)==dops[i].rt1) temp_wont_dirty|=1<<r;
6427 if((regs[i].regmap[r]&63)==dops[i].rt2) temp_wont_dirty|=1<<r;
6428 if((regs[i].regmap[r]&63)==dops[i+1].rt1) temp_wont_dirty|=1<<r;
6429 if((regs[i].regmap[r]&63)==dops[i+1].rt2) temp_wont_dirty|=1<<r;
6430 if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
6431 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) temp_wont_dirty|=1<<r;
6432 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) temp_wont_dirty|=1<<r;
6433 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) temp_wont_dirty|=1<<r;
6434 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) temp_wont_dirty|=1<<r;
6435 if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
6438 // Deal with changed mappings
6440 for(r=0;r<HOST_REGS;r++) {
6441 if(r!=EXCLUDE_REG) {
6442 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
6443 temp_will_dirty&=~(1<<r);
6444 temp_wont_dirty&=~(1<<r);
6445 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
6446 temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6447 temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6449 temp_will_dirty|=1<<r;
6450 temp_wont_dirty|=1<<r;
6457 will_dirty[i]=temp_will_dirty;
6458 wont_dirty[i]=temp_wont_dirty;
6459 clean_registers((ba[i]-start)>>2,i-1,0);
6461 // Limit recursion. It can take an excessive amount
6462 // of time if there are a lot of nested loops.
6463 will_dirty[(ba[i]-start)>>2]=0;
6464 wont_dirty[(ba[i]-start)>>2]=-1;
6469 if (dops[i].is_ujump)
6471 // Unconditional branch
6474 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
6475 for(r=0;r<HOST_REGS;r++) {
6476 if(r!=EXCLUDE_REG) {
6477 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
6478 will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
6479 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
6481 if(branch_regs[i].regmap[r]>=0) {
6482 will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
6483 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
6488 // Merge in delay slot
6489 for(r=0;r<HOST_REGS;r++) {
6490 if(r!=EXCLUDE_REG) {
6491 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6492 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6493 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6494 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
6495 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6496 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6497 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6498 if((regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6499 if((regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6500 if((regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6501 if((regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
6502 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6503 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6504 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6508 // Conditional branch
6509 will_dirty_i=will_dirty_next;
6510 wont_dirty_i=wont_dirty_next;
6511 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
6512 for(r=0;r<HOST_REGS;r++) {
6513 if(r!=EXCLUDE_REG) {
6514 signed char target_reg=branch_regs[i].regmap[r];
6515 if(target_reg==regs[(ba[i]-start)>>2].regmap_entry[r]) {
6516 will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
6517 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
6519 else if(target_reg>=0) {
6520 will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
6521 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
6526 // Merge in delay slot
6527 for(r=0;r<HOST_REGS;r++) {
6528 if(r!=EXCLUDE_REG) {
6529 if (1) { // !dops[i].likely) {
6530 // Might not dirty if likely branch is not taken
6531 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6532 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6533 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6534 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
6535 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6536 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6537 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6538 //if((regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6539 //if((regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6540 if((regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6541 if((regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
6542 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6543 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6544 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6549 // Merge in delay slot (won't dirty)
6550 for(r=0;r<HOST_REGS;r++) {
6551 if(r!=EXCLUDE_REG) {
6552 if((regs[i].regmap[r]&63)==dops[i].rt1) wont_dirty_i|=1<<r;
6553 if((regs[i].regmap[r]&63)==dops[i].rt2) wont_dirty_i|=1<<r;
6554 if((regs[i].regmap[r]&63)==dops[i+1].rt1) wont_dirty_i|=1<<r;
6555 if((regs[i].regmap[r]&63)==dops[i+1].rt2) wont_dirty_i|=1<<r;
6556 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6557 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) wont_dirty_i|=1<<r;
6558 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) wont_dirty_i|=1<<r;
6559 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) wont_dirty_i|=1<<r;
6560 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) wont_dirty_i|=1<<r;
6561 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6565 #ifndef DESTRUCTIVE_WRITEBACK
6566 branch_regs[i].dirty&=wont_dirty_i;
6568 branch_regs[i].dirty|=will_dirty_i;
6573 else if(dops[i].itype==SYSCALL||dops[i].itype==HLECALL||dops[i].itype==INTCALL)
6575 // SYSCALL instruction (software interrupt)
6579 else if(dops[i].itype==COP0 && (source[i]&0x3f)==0x18)
6581 // ERET instruction (return from interrupt)
6585 will_dirty_next=will_dirty_i;
6586 wont_dirty_next=wont_dirty_i;
6587 for(r=0;r<HOST_REGS;r++) {
6588 if(r!=EXCLUDE_REG) {
6589 if((regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6590 if((regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6591 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6592 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6593 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6594 if((regs[i].regmap[r]&63)==dops[i].rt1) wont_dirty_i|=1<<r;
6595 if((regs[i].regmap[r]&63)==dops[i].rt2) wont_dirty_i|=1<<r;
6596 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6598 if (!dops[i].is_jump)
6600 // Don't store a register immediately after writing it,
6601 // may prevent dual-issue.
6602 if((regs[i].regmap[r]&63)==dops[i-1].rt1) wont_dirty_i|=1<<r;
6603 if((regs[i].regmap[r]&63)==dops[i-1].rt2) wont_dirty_i|=1<<r;
6609 will_dirty[i]=will_dirty_i;
6610 wont_dirty[i]=wont_dirty_i;
6611 // Mark registers that won't be dirtied as not dirty
6613 regs[i].dirty|=will_dirty_i;
6614 #ifndef DESTRUCTIVE_WRITEBACK
6615 regs[i].dirty&=wont_dirty_i;
6618 if (i < iend-1 && !dops[i].is_ujump) {
6619 for(r=0;r<HOST_REGS;r++) {
6620 if(r!=EXCLUDE_REG) {
6621 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
6622 regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
6623 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
6631 for(r=0;r<HOST_REGS;r++) {
6632 if(r!=EXCLUDE_REG) {
6633 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
6634 regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
6635 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
6643 // Deal with changed mappings
6644 temp_will_dirty=will_dirty_i;
6645 temp_wont_dirty=wont_dirty_i;
6646 for(r=0;r<HOST_REGS;r++) {
6647 if(r!=EXCLUDE_REG) {
6649 if(regs[i].regmap[r]==regmap_pre[i][r]) {
6651 #ifndef DESTRUCTIVE_WRITEBACK
6652 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
6654 regs[i].wasdirty|=will_dirty_i&(1<<r);
6657 else if(regmap_pre[i][r]>=0&&(nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
6658 // Register moved to a different register
6659 will_dirty_i&=~(1<<r);
6660 wont_dirty_i&=~(1<<r);
6661 will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
6662 wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
6664 #ifndef DESTRUCTIVE_WRITEBACK
6665 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
6667 regs[i].wasdirty|=will_dirty_i&(1<<r);
6671 will_dirty_i&=~(1<<r);
6672 wont_dirty_i&=~(1<<r);
6673 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
6674 will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6675 wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6678 /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);assert(!((will_dirty>>r)&1));*/
6688 void disassemble_inst(int i)
6690 if (dops[i].bt) printf("*"); else printf(" ");
6691 switch(dops[i].itype) {
6693 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
6695 printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2,i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
6697 printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
6699 if (dops[i].opcode==0x9&&dops[i].rt1!=31)
6700 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1);
6702 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rs1);
6705 printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2,ba[i]);break;
6707 if(dops[i].opcode==0xf) //LUI
6708 printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],dops[i].rt1,imm[i]&0xffff);
6710 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,imm[i]);
6714 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,imm[i]);
6718 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],dops[i].rs2,dops[i].rs1,imm[i]);
6722 printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,dops[i].rs2);
6725 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2);
6728 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,imm[i]);
6731 if((dops[i].opcode2&0x1d)==0x10)
6732 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rt1);
6733 else if((dops[i].opcode2&0x1d)==0x11)
6734 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rs1);
6736 printf (" %x: %s\n",start+i*4,insn[i]);
6739 if(dops[i].opcode2==0)
6740 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC0
6741 else if(dops[i].opcode2==4)
6742 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC0
6743 else printf (" %x: %s\n",start+i*4,insn[i]);
6746 if(dops[i].opcode2<3)
6747 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC1
6748 else if(dops[i].opcode2>3)
6749 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC1
6750 else printf (" %x: %s\n",start+i*4,insn[i]);
6753 if(dops[i].opcode2<3)
6754 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC2
6755 else if(dops[i].opcode2>3)
6756 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC2
6757 else printf (" %x: %s\n",start+i*4,insn[i]);
6760 printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,dops[i].rs1,imm[i]);
6763 printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,dops[i].rs1,imm[i]);
6766 printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
6769 //printf (" %s %8x\n",insn[i],source[i]);
6770 printf (" %x: %s\n",start+i*4,insn[i]);
6774 static void disassemble_inst(int i) {}
6777 #define DRC_TEST_VAL 0x74657374
6779 static void new_dynarec_test(void)
6781 int (*testfunc)(void);
6786 // check structure linkage
6787 if ((u_char *)rcnts - (u_char *)&psxRegs != sizeof(psxRegs))
6789 SysPrintf("linkage_arm* miscompilation/breakage detected.\n");
6792 SysPrintf("testing if we can run recompiled code...\n");
6793 ((volatile u_int *)out)[0]++; // make cache dirty
6795 for (i = 0; i < ARRAY_SIZE(ret); i++) {
6796 out = ndrc->translation_cache;
6797 beginning = start_block();
6798 emit_movimm(DRC_TEST_VAL + i, 0); // test
6801 end_block(beginning);
6802 testfunc = beginning;
6803 ret[i] = testfunc();
6806 if (ret[0] == DRC_TEST_VAL && ret[1] == DRC_TEST_VAL + 1)
6807 SysPrintf("test passed.\n");
6809 SysPrintf("test failed, will likely crash soon (r=%08x %08x)\n", ret[0], ret[1]);
6810 out = ndrc->translation_cache;
6813 // clear the state completely, instead of just marking
6814 // things invalid like invalidate_all_pages() does
6815 void new_dynarec_clear_full(void)
6818 out = ndrc->translation_cache;
6819 memset(invalid_code,1,sizeof(invalid_code));
6820 memset(hash_table,0xff,sizeof(hash_table));
6821 memset(mini_ht,-1,sizeof(mini_ht));
6822 memset(restore_candidate,0,sizeof(restore_candidate));
6823 memset(shadow,0,sizeof(shadow));
6825 expirep=16384; // Expiry pointer, +2 blocks
6826 pending_exception=0;
6829 inv_code_start=inv_code_end=~0;
6832 for(n=0;n<4096;n++) ll_clear(jump_in+n);
6833 for(n=0;n<4096;n++) ll_clear(jump_out+n);
6834 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
6836 cycle_multiplier_old = cycle_multiplier;
6837 new_dynarec_hacks_old = new_dynarec_hacks;
6840 void new_dynarec_init(void)
6842 SysPrintf("Init new dynarec\n");
6844 #ifdef BASE_ADDR_DYNAMIC
6846 sceBlock = sceKernelAllocMemBlockForVM("code", 1 << TARGET_SIZE_2);
6848 SysPrintf("sceKernelAllocMemBlockForVM failed\n");
6849 int ret = sceKernelGetMemBlockBase(sceBlock, (void **)&ndrc);
6851 SysPrintf("sceKernelGetMemBlockBase failed\n");
6853 uintptr_t desired_addr = 0;
6856 desired_addr = ((uintptr_t)&_end + 0xffffff) & ~0xffffffl;
6858 ndrc = mmap((void *)desired_addr, sizeof(*ndrc),
6859 PROT_READ | PROT_WRITE | PROT_EXEC,
6860 MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
6861 if (ndrc == MAP_FAILED) {
6862 SysPrintf("mmap() failed: %s\n", strerror(errno));
6867 #ifndef NO_WRITE_EXEC
6868 // not all systems allow execute in data segment by default
6869 if (mprotect(ndrc, sizeof(ndrc->translation_cache) + sizeof(ndrc->tramp.ops),
6870 PROT_READ | PROT_WRITE | PROT_EXEC) != 0)
6871 SysPrintf("mprotect() failed: %s\n", strerror(errno));
6874 out = ndrc->translation_cache;
6875 cycle_multiplier=200;
6876 new_dynarec_clear_full();
6878 // Copy this into local area so we don't have to put it in every literal pool
6879 invc_ptr=invalid_code;
6883 ram_offset=(uintptr_t)rdram-0x80000000;
6885 SysPrintf("warning: RAM is not directly mapped, performance will suffer\n");
6888 void new_dynarec_cleanup(void)
6891 #ifdef BASE_ADDR_DYNAMIC
6893 sceKernelFreeMemBlock(sceBlock);
6896 if (munmap(ndrc, sizeof(*ndrc)) < 0)
6897 SysPrintf("munmap() failed\n");
6900 for(n=0;n<4096;n++) ll_clear(jump_in+n);
6901 for(n=0;n<4096;n++) ll_clear(jump_out+n);
6902 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
6904 if (munmap (ROM_COPY, 67108864) < 0) {SysPrintf("munmap() failed\n");}
6908 static u_int *get_source_start(u_int addr, u_int *limit)
6910 if (!HACK_ENABLED(NDHACK_OVERRIDE_CYCLE_M))
6911 cycle_multiplier_override = 0;
6913 if (addr < 0x00200000 ||
6914 (0xa0000000 <= addr && addr < 0xa0200000))
6916 // used for BIOS calls mostly?
6917 *limit = (addr&0xa0000000)|0x00200000;
6918 return (u_int *)(rdram + (addr&0x1fffff));
6920 else if (!Config.HLE && (
6921 /* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
6922 (0xbfc00000 <= addr && addr < 0xbfc80000)))
6924 // BIOS. The multiplier should be much higher as it's uncached 8bit mem,
6925 // but timings in PCSX are too tied to the interpreter's BIAS
6926 if (!HACK_ENABLED(NDHACK_OVERRIDE_CYCLE_M))
6927 cycle_multiplier_override = 200;
6929 *limit = (addr & 0xfff00000) | 0x80000;
6930 return (u_int *)((u_char *)psxR + (addr&0x7ffff));
6932 else if (addr >= 0x80000000 && addr < 0x80000000+RAM_SIZE) {
6933 *limit = (addr & 0x80600000) + 0x00200000;
6934 return (u_int *)(rdram + (addr&0x1fffff));
6939 static u_int scan_for_ret(u_int addr)
6944 mem = get_source_start(addr, &limit);
6948 if (limit > addr + 0x1000)
6949 limit = addr + 0x1000;
6950 for (; addr < limit; addr += 4, mem++) {
6951 if (*mem == 0x03e00008) // jr $ra
6957 struct savestate_block {
6962 static int addr_cmp(const void *p1_, const void *p2_)
6964 const struct savestate_block *p1 = p1_, *p2 = p2_;
6965 return p1->addr - p2->addr;
6968 int new_dynarec_save_blocks(void *save, int size)
6970 struct savestate_block *blocks = save;
6971 int maxcount = size / sizeof(blocks[0]);
6972 struct savestate_block tmp_blocks[1024];
6973 struct ll_entry *head;
6974 int p, s, d, o, bcnt;
6978 for (p = 0; p < ARRAY_SIZE(jump_in); p++) {
6980 for (head = jump_in[p]; head != NULL; head = head->next) {
6981 tmp_blocks[bcnt].addr = head->vaddr;
6982 tmp_blocks[bcnt].regflags = head->reg_sv_flags;
6987 qsort(tmp_blocks, bcnt, sizeof(tmp_blocks[0]), addr_cmp);
6989 addr = tmp_blocks[0].addr;
6990 for (s = d = 0; s < bcnt; s++) {
6991 if (tmp_blocks[s].addr < addr)
6993 if (d == 0 || tmp_blocks[d-1].addr != tmp_blocks[s].addr)
6994 tmp_blocks[d++] = tmp_blocks[s];
6995 addr = scan_for_ret(tmp_blocks[s].addr);
6998 if (o + d > maxcount)
7000 memcpy(&blocks[o], tmp_blocks, d * sizeof(blocks[0]));
7004 return o * sizeof(blocks[0]);
7007 void new_dynarec_load_blocks(const void *save, int size)
7009 const struct savestate_block *blocks = save;
7010 int count = size / sizeof(blocks[0]);
7011 u_int regs_save[32];
7015 get_addr(psxRegs.pc);
7017 // change GPRs for speculation to at least partially work..
7018 memcpy(regs_save, &psxRegs.GPR, sizeof(regs_save));
7019 for (i = 1; i < 32; i++)
7020 psxRegs.GPR.r[i] = 0x80000000;
7022 for (b = 0; b < count; b++) {
7023 for (f = blocks[b].regflags, i = 0; f; f >>= 1, i++) {
7025 psxRegs.GPR.r[i] = 0x1f800000;
7028 get_addr(blocks[b].addr);
7030 for (f = blocks[b].regflags, i = 0; f; f >>= 1, i++) {
7032 psxRegs.GPR.r[i] = 0x80000000;
7036 memcpy(&psxRegs.GPR, regs_save, sizeof(regs_save));
7039 int new_recompile_block(u_int addr)
7041 u_int pagelimit = 0;
7042 u_int state_rflags = 0;
7045 assem_debug("NOTCOMPILED: addr = %x -> %p\n", addr, out);
7046 //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
7048 //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
7050 // this is just for speculation
7051 for (i = 1; i < 32; i++) {
7052 if ((psxRegs.GPR.r[i] & 0xffff0000) == 0x1f800000)
7053 state_rflags |= 1 << i;
7056 start = (u_int)addr&~3;
7057 //assert(((u_int)addr&1)==0); // start-in-delay-slot flag
7058 new_dynarec_did_compile=1;
7059 if (Config.HLE && start == 0x80001000) // hlecall
7061 // XXX: is this enough? Maybe check hleSoftCall?
7062 void *beginning=start_block();
7063 u_int page=get_page(start);
7065 invalid_code[start>>12]=0;
7066 emit_movimm(start,0);
7067 emit_writeword(0,&pcaddr);
7068 emit_far_jump(new_dyna_leave);
7070 end_block(beginning);
7071 ll_add_flags(jump_in+page,start,state_rflags,(void *)beginning);
7074 else if (f1_hack == ~0u || (f1_hack != 0 && start == f1_hack)) {
7075 void *beginning = start_block();
7076 u_int page = get_page(start);
7077 emit_readword(&psxRegs.GPR.n.sp, 0);
7078 emit_readptr(&mem_rtab, 1);
7079 emit_shrimm(0, 12, 2);
7080 emit_readptr_dualindexedx_ptrlen(1, 2, 1);
7081 emit_addimm(0, 0x18, 0);
7082 emit_adds_ptr(1, 1, 1);
7083 emit_ldr_dualindexed(1, 0, 0);
7084 emit_writeword(0, &psxRegs.GPR.r[26]); // lw k0, 0x18(sp)
7085 emit_far_call(get_addr_ht);
7086 emit_jmpreg(0); // jr k0
7088 end_block(beginning);
7090 ll_add_flags(jump_in + page, start, state_rflags, beginning);
7091 SysPrintf("F1 hack to %08x\n", start);
7096 source = get_source_start(start, &pagelimit);
7097 if (source == NULL) {
7098 SysPrintf("Compile at bogus memory address: %08x\n", addr);
7102 /* Pass 1: disassemble */
7103 /* Pass 2: register dependencies, branch targets */
7104 /* Pass 3: register allocation */
7105 /* Pass 4: branch dependencies */
7106 /* Pass 5: pre-alloc */
7107 /* Pass 6: optimize clean/dirty state */
7108 /* Pass 7: flag 32-bit registers */
7109 /* Pass 8: assembly */
7110 /* Pass 9: linker */
7111 /* Pass 10: garbage collection / free memory */
7115 unsigned int type,op,op2;
7117 //printf("addr = %x source = %x %x\n", addr,source,source[0]);
7119 /* Pass 1 disassembly */
7121 for(i=0;!done;i++) {
7125 minimum_free_regs[i]=0;
7126 dops[i].opcode=op=source[i]>>26;
7129 case 0x00: strcpy(insn[i],"special"); type=NI;
7133 case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
7134 case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
7135 case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
7136 case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
7137 case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
7138 case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
7139 case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
7140 case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
7141 case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
7142 case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
7143 case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
7144 case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
7145 case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
7146 case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
7147 case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
7148 case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
7149 case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
7150 case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
7151 case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
7152 case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
7153 case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
7154 case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
7155 case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
7156 case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
7157 case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
7158 case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
7159 case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
7160 case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
7161 case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
7162 case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
7163 case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
7164 case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
7165 case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
7166 case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
7167 case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
7169 case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
7170 case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
7171 case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
7172 case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
7173 case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
7174 case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
7175 case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
7176 case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
7177 case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
7178 case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
7179 case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
7180 case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
7181 case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
7182 case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
7183 case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
7184 case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
7185 case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
7189 case 0x01: strcpy(insn[i],"regimm"); type=NI;
7190 op2=(source[i]>>16)&0x1f;
7193 case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
7194 case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
7195 //case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
7196 //case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
7197 //case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
7198 //case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
7199 //case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
7200 //case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
7201 //case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
7202 //case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
7203 case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
7204 case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
7205 //case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
7206 //case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
7209 case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
7210 case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
7211 case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
7212 case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
7213 case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
7214 case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
7215 case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
7216 case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
7217 case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
7218 case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
7219 case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
7220 case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
7221 case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
7222 case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
7223 case 0x10: strcpy(insn[i],"cop0"); type=NI;
7224 op2=(source[i]>>21)&0x1f;
7227 case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
7228 case 0x02: strcpy(insn[i],"CFC0"); type=COP0; break;
7229 case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
7230 case 0x06: strcpy(insn[i],"CTC0"); type=COP0; break;
7231 case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
7234 case 0x11: strcpy(insn[i],"cop1"); type=COP1;
7235 op2=(source[i]>>21)&0x1f;
7238 case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
7239 case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
7240 case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
7241 case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
7242 case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
7243 case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
7244 case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
7245 case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
7247 case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
7248 case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
7249 case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
7250 case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
7251 case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
7252 case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
7253 case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
7255 case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
7257 case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
7258 case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
7259 case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
7260 case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
7262 case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
7263 case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
7265 case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
7266 case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
7267 case 0x30: strcpy(insn[i],"LL"); type=NI; break;
7268 case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
7270 case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
7271 case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
7272 case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
7274 case 0x38: strcpy(insn[i],"SC"); type=NI; break;
7275 case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
7277 case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
7278 case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
7279 case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
7281 case 0x12: strcpy(insn[i],"COP2"); type=NI;
7282 op2=(source[i]>>21)&0x1f;
7284 if (source[i]&0x3f) { // use this hack to support old savestates with patched gte insns
7285 if (gte_handlers[source[i]&0x3f]!=NULL) {
7286 if (gte_regnames[source[i]&0x3f]!=NULL)
7287 strcpy(insn[i],gte_regnames[source[i]&0x3f]);
7289 snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
7295 case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
7296 case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
7297 case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
7298 case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
7301 case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
7302 case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
7303 case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
7304 default: strcpy(insn[i],"???"); type=NI;
7305 SysPrintf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
7309 dops[i].opcode2=op2;
7310 /* Get registers/immediates */
7312 gte_rs[i]=gte_rt[i]=0;
7315 dops[i].rs1=(source[i]>>21)&0x1f;
7317 dops[i].rt1=(source[i]>>16)&0x1f;
7319 imm[i]=(short)source[i];
7323 dops[i].rs1=(source[i]>>21)&0x1f;
7324 dops[i].rs2=(source[i]>>16)&0x1f;
7327 imm[i]=(short)source[i];
7330 // LWL/LWR only load part of the register,
7331 // therefore the target register must be treated as a source too
7332 dops[i].rs1=(source[i]>>21)&0x1f;
7333 dops[i].rs2=(source[i]>>16)&0x1f;
7334 dops[i].rt1=(source[i]>>16)&0x1f;
7336 imm[i]=(short)source[i];
7339 if (op==0x0f) dops[i].rs1=0; // LUI instruction has no source register
7340 else dops[i].rs1=(source[i]>>21)&0x1f;
7342 dops[i].rt1=(source[i]>>16)&0x1f;
7344 if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
7345 imm[i]=(unsigned short)source[i];
7347 imm[i]=(short)source[i];
7355 // The JAL instruction writes to r31.
7362 dops[i].rs1=(source[i]>>21)&0x1f;
7366 // The JALR instruction writes to rd.
7368 dops[i].rt1=(source[i]>>11)&0x1f;
7373 dops[i].rs1=(source[i]>>21)&0x1f;
7374 dops[i].rs2=(source[i]>>16)&0x1f;
7377 if(op&2) { // BGTZ/BLEZ
7382 dops[i].rs1=(source[i]>>21)&0x1f;
7386 if(op2&0x10) { // BxxAL
7388 // NOTE: If the branch is not taken, r31 is still overwritten
7392 dops[i].rs1=(source[i]>>21)&0x1f; // source
7393 dops[i].rs2=(source[i]>>16)&0x1f; // subtract amount
7394 dops[i].rt1=(source[i]>>11)&0x1f; // destination
7398 dops[i].rs1=(source[i]>>21)&0x1f; // source
7399 dops[i].rs2=(source[i]>>16)&0x1f; // divisor
7408 if(op2==0x10) dops[i].rs1=HIREG; // MFHI
7409 if(op2==0x11) dops[i].rt1=HIREG; // MTHI
7410 if(op2==0x12) dops[i].rs1=LOREG; // MFLO
7411 if(op2==0x13) dops[i].rt1=LOREG; // MTLO
7412 if((op2&0x1d)==0x10) dops[i].rt1=(source[i]>>11)&0x1f; // MFxx
7413 if((op2&0x1d)==0x11) dops[i].rs1=(source[i]>>21)&0x1f; // MTxx
7416 dops[i].rs1=(source[i]>>16)&0x1f; // target of shift
7417 dops[i].rs2=(source[i]>>21)&0x1f; // shift amount
7418 dops[i].rt1=(source[i]>>11)&0x1f; // destination
7422 dops[i].rs1=(source[i]>>16)&0x1f;
7424 dops[i].rt1=(source[i]>>11)&0x1f;
7426 imm[i]=(source[i]>>6)&0x1f;
7427 // DSxx32 instructions
7428 if(op2>=0x3c) imm[i]|=0x20;
7435 if(op2==0||op2==2) dops[i].rt1=(source[i]>>16)&0x1F; // MFC0/CFC0
7436 if(op2==4||op2==6) dops[i].rs1=(source[i]>>16)&0x1F; // MTC0/CTC0
7437 if(op2==4&&((source[i]>>11)&0x1f)==12) dops[i].rt2=CSREG; // Status
7438 if(op2==16) if((source[i]&0x3f)==0x18) dops[i].rs2=CCREG; // ERET
7445 if(op2<3) dops[i].rt1=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
7446 if(op2>3) dops[i].rs1=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
7454 if(op2<3) dops[i].rt1=(source[i]>>16)&0x1F; // MFC2/CFC2
7455 if(op2>3) dops[i].rs1=(source[i]>>16)&0x1F; // MTC2/CTC2
7457 int gr=(source[i]>>11)&0x1F;
7460 case 0x00: gte_rs[i]=1ll<<gr; break; // MFC2
7461 case 0x04: gte_rt[i]=1ll<<gr; break; // MTC2
7462 case 0x02: gte_rs[i]=1ll<<(gr+32); break; // CFC2
7463 case 0x06: gte_rt[i]=1ll<<(gr+32); break; // CTC2
7467 dops[i].rs1=(source[i]>>21)&0x1F;
7471 imm[i]=(short)source[i];
7474 dops[i].rs1=(source[i]>>21)&0x1F;
7478 imm[i]=(short)source[i];
7479 if(op==0x32) gte_rt[i]=1ll<<((source[i]>>16)&0x1F); // LWC2
7480 else gte_rs[i]=1ll<<((source[i]>>16)&0x1F); // SWC2
7487 gte_rs[i]=gte_reg_reads[source[i]&0x3f];
7488 gte_rt[i]=gte_reg_writes[source[i]&0x3f];
7489 gte_rt[i]|=1ll<<63; // every op changes flags
7490 if((source[i]&0x3f)==GTE_MVMVA) {
7491 int v = (source[i] >> 15) & 3;
7492 gte_rs[i]&=~0xe3fll;
7493 if(v==3) gte_rs[i]|=0xe00ll;
7494 else gte_rs[i]|=3ll<<(v*2);
7511 /* Calculate branch target addresses */
7513 ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
7514 else if(type==CJUMP&&dops[i].rs1==dops[i].rs2&&(op&1))
7515 ba[i]=start+i*4+8; // Ignore never taken branch
7516 else if(type==SJUMP&&dops[i].rs1==0&&!(op2&1))
7517 ba[i]=start+i*4+8; // Ignore never taken branch
7518 else if(type==CJUMP||type==SJUMP)
7519 ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
7522 /* simplify always (not)taken branches */
7523 if (type == CJUMP && dops[i].rs1 == dops[i].rs2) {
7524 dops[i].rs1 = dops[i].rs2 = 0;
7526 dops[i].itype = type = UJUMP;
7527 dops[i].rs2 = CCREG;
7530 else if (type == SJUMP && dops[i].rs1 == 0 && (op2 & 1))
7531 dops[i].itype = type = UJUMP;
7533 dops[i].is_jump = (dops[i].itype == RJUMP || dops[i].itype == UJUMP || dops[i].itype == CJUMP || dops[i].itype == SJUMP);
7534 dops[i].is_ujump = (dops[i].itype == RJUMP || dops[i].itype == UJUMP); // || (source[i] >> 16) == 0x1000 // beq r0,r0
7535 dops[i].is_load = (dops[i].itype == LOAD || dops[i].itype == LOADLR || op == 0x32); // LWC2
7536 dops[i].is_store = (dops[i].itype == STORE || dops[i].itype == STORELR || op == 0x3a); // SWC2
7538 /* messy cases to just pass over to the interpreter */
7539 if (i > 0 && dops[i-1].is_jump) {
7541 // branch in delay slot?
7542 if (dops[i].is_jump) {
7543 // don't handle first branch and call interpreter if it's hit
7544 SysPrintf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr);
7547 // basic load delay detection
7548 else if((type==LOAD||type==LOADLR||type==COP0||type==COP2||type==C2LS)&&dops[i].rt1!=0) {
7549 int t=(ba[i-1]-start)/4;
7550 if(0 <= t && t < i &&(dops[i].rt1==dops[t].rs1||dops[i].rt1==dops[t].rs2)&&dops[t].itype!=CJUMP&&dops[t].itype!=SJUMP) {
7551 // jump target wants DS result - potential load delay effect
7552 SysPrintf("load delay @%08x (%08x)\n", addr + i*4, addr);
7554 dops[t+1].bt=1; // expected return from interpreter
7556 else if(i>=2&&dops[i-2].rt1==2&&dops[i].rt1==2&&dops[i].rs1!=2&&dops[i].rs2!=2&&dops[i-1].rs1!=2&&dops[i-1].rs2!=2&&
7557 !(i>=3&&dops[i-3].is_jump)) {
7558 // v0 overwrite like this is a sign of trouble, bail out
7559 SysPrintf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr);
7564 dops[i-1].rs1=CCREG;
7565 dops[i-1].rs2=dops[i-1].rt1=dops[i-1].rt2=0;
7567 dops[i-1].itype=INTCALL;
7569 i--; // don't compile the DS
7573 /* Is this the end of the block? */
7574 if (i > 0 && dops[i-1].is_ujump) {
7575 if(dops[i-1].rt1==0) { // Continue past subroutine call (JAL)
7579 if(stop_after_jal) done=1;
7581 if((source[i+1]&0xfc00003f)==0x0d) done=1;
7583 // Don't recompile stuff that's already compiled
7584 if(check_addr(start+i*4+4)) done=1;
7585 // Don't get too close to the limit
7586 if(i>MAXBLOCK/2) done=1;
7588 if(dops[i].itype==SYSCALL&&stop_after_jal) done=1;
7589 if(dops[i].itype==HLECALL||dops[i].itype==INTCALL) done=2;
7591 // Does the block continue due to a branch?
7594 if(ba[j]==start+i*4) done=j=0; // Branch into delay slot
7595 if(ba[j]==start+i*4+4) done=j=0;
7596 if(ba[j]==start+i*4+8) done=j=0;
7599 //assert(i<MAXBLOCK-1);
7600 if(start+i*4==pagelimit-4) done=1;
7601 assert(start+i*4<pagelimit);
7602 if (i==MAXBLOCK-1) done=1;
7603 // Stop if we're compiling junk
7604 if(dops[i].itype==NI&&dops[i].opcode==0x11) {
7605 done=stop_after_jal=1;
7606 SysPrintf("Disabled speculative precompilation\n");
7610 if (dops[i-1].is_jump) {
7611 if(start+i*4==pagelimit) {
7612 dops[i-1].itype=SPAN;
7617 /* spacial hack(s) */
7618 if (i > 10 && source[i-1] == 0 && source[i-2] == 0x03e00008
7619 && source[i-4] == 0x8fbf0018 && source[i-6] == 0x00c0f809
7620 && dops[i-7].itype == STORE)
7623 if (dops[i].itype == IMM16)
7625 // swl r2, 15(r6); swr r2, 12(r6); sw r6, *; jalr r6
7626 if (dops[i].itype == STORELR && dops[i].rs1 == 6
7627 && dops[i-1].itype == STORELR && dops[i-1].rs1 == 6)
7629 SysPrintf("F1 hack from %08x\n", start);
7635 /* Pass 2 - Register dependencies and branch targets */
7637 unneeded_registers(0,slen-1,0);
7639 /* Pass 3 - Register allocation */
7641 struct regstat current; // Current register allocations/status
7643 current.u=unneeded_reg[0];
7644 clear_all_regs(current.regmap);
7645 alloc_reg(¤t,0,CCREG);
7646 dirty_reg(¤t,CCREG);
7649 current.waswritten=0;
7655 // First instruction is delay slot
7660 current.regmap[HOST_BTREG]=BTREG;
7668 for(hr=0;hr<HOST_REGS;hr++)
7670 // Is this really necessary?
7671 if(current.regmap[hr]==0) current.regmap[hr]=-1;
7674 current.waswritten=0;
7677 memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
7678 regs[i].wasconst=current.isconst;
7679 regs[i].wasdirty=current.dirty;
7680 regs[i].loadedconst=0;
7681 if (!dops[i].is_jump) {
7683 current.u=unneeded_reg[i+1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7690 current.u=branch_unneeded_reg[i]&~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7691 current.u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7693 } else { SysPrintf("oops, branch at end of block with no delay slot\n");abort(); }
7697 ds=0; // Skip delay slot, already allocated as part of branch
7698 // ...but we need to alloc it in case something jumps here
7700 current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
7702 current.u=branch_unneeded_reg[i-1];
7704 current.u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7706 struct regstat temp;
7707 memcpy(&temp,¤t,sizeof(current));
7708 temp.wasdirty=temp.dirty;
7709 // TODO: Take into account unconditional branches, as below
7710 delayslot_alloc(&temp,i);
7711 memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
7712 regs[i].wasdirty=temp.wasdirty;
7713 regs[i].dirty=temp.dirty;
7717 // Create entry (branch target) regmap
7718 for(hr=0;hr<HOST_REGS;hr++)
7720 int r=temp.regmap[hr];
7722 if(r!=regmap_pre[i][hr]) {
7723 regs[i].regmap_entry[hr]=-1;
7728 if((current.u>>r)&1) {
7729 regs[i].regmap_entry[hr]=-1;
7730 regs[i].regmap[hr]=-1;
7731 //Don't clear regs in the delay slot as the branch might need them
7732 //current.regmap[hr]=-1;
7734 regs[i].regmap_entry[hr]=r;
7737 // First instruction expects CCREG to be allocated
7738 if(i==0&&hr==HOST_CCREG)
7739 regs[i].regmap_entry[hr]=CCREG;
7741 regs[i].regmap_entry[hr]=-1;
7745 else { // Not delay slot
7746 switch(dops[i].itype) {
7748 //current.isconst=0; // DEBUG
7749 //current.wasconst=0; // DEBUG
7750 //regs[i].wasconst=0; // DEBUG
7751 clear_const(¤t,dops[i].rt1);
7752 alloc_cc(¤t,i);
7753 dirty_reg(¤t,CCREG);
7754 if (dops[i].rt1==31) {
7755 alloc_reg(¤t,i,31);
7756 dirty_reg(¤t,31);
7757 //assert(dops[i+1].rs1!=31&&dops[i+1].rs2!=31);
7758 //assert(dops[i+1].rt1!=dops[i].rt1);
7760 alloc_reg(¤t,i,PTEMP);
7764 delayslot_alloc(¤t,i+1);
7765 //current.isconst=0; // DEBUG
7767 //printf("i=%d, isconst=%x\n",i,current.isconst);
7770 //current.isconst=0;
7771 //current.wasconst=0;
7772 //regs[i].wasconst=0;
7773 clear_const(¤t,dops[i].rs1);
7774 clear_const(¤t,dops[i].rt1);
7775 alloc_cc(¤t,i);
7776 dirty_reg(¤t,CCREG);
7777 if (!ds_writes_rjump_rs(i)) {
7778 alloc_reg(¤t,i,dops[i].rs1);
7779 if (dops[i].rt1!=0) {
7780 alloc_reg(¤t,i,dops[i].rt1);
7781 dirty_reg(¤t,dops[i].rt1);
7782 assert(dops[i+1].rs1!=dops[i].rt1&&dops[i+1].rs2!=dops[i].rt1);
7783 assert(dops[i+1].rt1!=dops[i].rt1);
7785 alloc_reg(¤t,i,PTEMP);
7789 if(dops[i].rs1==31) { // JALR
7790 alloc_reg(¤t,i,RHASH);
7791 alloc_reg(¤t,i,RHTBL);
7794 delayslot_alloc(¤t,i+1);
7796 // The delay slot overwrites our source register,
7797 // allocate a temporary register to hold the old value.
7801 delayslot_alloc(¤t,i+1);
7803 alloc_reg(¤t,i,RTEMP);
7805 //current.isconst=0; // DEBUG
7810 //current.isconst=0;
7811 //current.wasconst=0;
7812 //regs[i].wasconst=0;
7813 clear_const(¤t,dops[i].rs1);
7814 clear_const(¤t,dops[i].rs2);
7815 if((dops[i].opcode&0x3E)==4) // BEQ/BNE
7817 alloc_cc(¤t,i);
7818 dirty_reg(¤t,CCREG);
7819 if(dops[i].rs1) alloc_reg(¤t,i,dops[i].rs1);
7820 if(dops[i].rs2) alloc_reg(¤t,i,dops[i].rs2);
7821 if((dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2))||
7822 (dops[i].rs2&&(dops[i].rs2==dops[i+1].rt1||dops[i].rs2==dops[i+1].rt2))) {
7823 // The delay slot overwrites one of our conditions.
7824 // Allocate the branch condition registers instead.
7828 if(dops[i].rs1) alloc_reg(¤t,i,dops[i].rs1);
7829 if(dops[i].rs2) alloc_reg(¤t,i,dops[i].rs2);
7834 delayslot_alloc(¤t,i+1);
7838 if((dops[i].opcode&0x3E)==6) // BLEZ/BGTZ
7840 alloc_cc(¤t,i);
7841 dirty_reg(¤t,CCREG);
7842 alloc_reg(¤t,i,dops[i].rs1);
7843 if(dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2)) {
7844 // The delay slot overwrites one of our conditions.
7845 // Allocate the branch condition registers instead.
7849 if(dops[i].rs1) alloc_reg(¤t,i,dops[i].rs1);
7854 delayslot_alloc(¤t,i+1);
7858 // Don't alloc the delay slot yet because we might not execute it
7859 if((dops[i].opcode&0x3E)==0x14) // BEQL/BNEL
7864 alloc_cc(¤t,i);
7865 dirty_reg(¤t,CCREG);
7866 alloc_reg(¤t,i,dops[i].rs1);
7867 alloc_reg(¤t,i,dops[i].rs2);
7870 if((dops[i].opcode&0x3E)==0x16) // BLEZL/BGTZL
7875 alloc_cc(¤t,i);
7876 dirty_reg(¤t,CCREG);
7877 alloc_reg(¤t,i,dops[i].rs1);
7880 //current.isconst=0;
7883 //current.isconst=0;
7884 //current.wasconst=0;
7885 //regs[i].wasconst=0;
7886 clear_const(¤t,dops[i].rs1);
7887 clear_const(¤t,dops[i].rt1);
7888 //if((dops[i].opcode2&0x1E)==0x0) // BLTZ/BGEZ
7889 if((dops[i].opcode2&0x0E)==0x0) // BLTZ/BGEZ
7891 alloc_cc(¤t,i);
7892 dirty_reg(¤t,CCREG);
7893 alloc_reg(¤t,i,dops[i].rs1);
7894 if (dops[i].rt1==31) { // BLTZAL/BGEZAL
7895 alloc_reg(¤t,i,31);
7896 dirty_reg(¤t,31);
7897 //#ifdef REG_PREFETCH
7898 //alloc_reg(¤t,i,PTEMP);
7901 if((dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2)) // The delay slot overwrites the branch condition.
7902 ||(dops[i].rt1==31&&(dops[i+1].rs1==31||dops[i+1].rs2==31||dops[i+1].rt1==31||dops[i+1].rt2==31))) { // DS touches $ra
7903 // Allocate the branch condition registers instead.
7907 if(dops[i].rs1) alloc_reg(¤t,i,dops[i].rs1);
7912 delayslot_alloc(¤t,i+1);
7916 // Don't alloc the delay slot yet because we might not execute it
7917 if((dops[i].opcode2&0x1E)==0x2) // BLTZL/BGEZL
7922 alloc_cc(¤t,i);
7923 dirty_reg(¤t,CCREG);
7924 alloc_reg(¤t,i,dops[i].rs1);
7927 //current.isconst=0;
7930 imm16_alloc(¤t,i);
7934 load_alloc(¤t,i);
7938 store_alloc(¤t,i);
7941 alu_alloc(¤t,i);
7944 shift_alloc(¤t,i);
7947 multdiv_alloc(¤t,i);
7950 shiftimm_alloc(¤t,i);
7953 mov_alloc(¤t,i);
7956 cop0_alloc(¤t,i);
7961 cop2_alloc(¤t,i);
7964 c1ls_alloc(¤t,i);
7967 c2ls_alloc(¤t,i);
7970 c2op_alloc(¤t,i);
7975 syscall_alloc(¤t,i);
7978 pagespan_alloc(¤t,i);
7982 // Create entry (branch target) regmap
7983 for(hr=0;hr<HOST_REGS;hr++)
7986 r=current.regmap[hr];
7988 if(r!=regmap_pre[i][hr]) {
7989 // TODO: delay slot (?)
7990 or=get_reg(regmap_pre[i],r); // Get old mapping for this register
7991 if(or<0||(r&63)>=TEMPREG){
7992 regs[i].regmap_entry[hr]=-1;
7996 // Just move it to a different register
7997 regs[i].regmap_entry[hr]=r;
7998 // If it was dirty before, it's still dirty
7999 if((regs[i].wasdirty>>or)&1) dirty_reg(¤t,r&63);
8006 regs[i].regmap_entry[hr]=0;
8011 if((current.u>>r)&1) {
8012 regs[i].regmap_entry[hr]=-1;
8013 //regs[i].regmap[hr]=-1;
8014 current.regmap[hr]=-1;
8016 regs[i].regmap_entry[hr]=r;
8020 // Branches expect CCREG to be allocated at the target
8021 if(regmap_pre[i][hr]==CCREG)
8022 regs[i].regmap_entry[hr]=CCREG;
8024 regs[i].regmap_entry[hr]=-1;
8027 memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
8030 if(i>0&&(dops[i-1].itype==STORE||dops[i-1].itype==STORELR||(dops[i-1].itype==C2LS&&dops[i-1].opcode==0x3a))&&(u_int)imm[i-1]<0x800)
8031 current.waswritten|=1<<dops[i-1].rs1;
8032 current.waswritten&=~(1<<dops[i].rt1);
8033 current.waswritten&=~(1<<dops[i].rt2);
8034 if((dops[i].itype==STORE||dops[i].itype==STORELR||(dops[i].itype==C2LS&&dops[i].opcode==0x3a))&&(u_int)imm[i]>=0x800)
8035 current.waswritten&=~(1<<dops[i].rs1);
8037 /* Branch post-alloc */
8040 current.wasdirty=current.dirty;
8041 switch(dops[i-1].itype) {
8043 memcpy(&branch_regs[i-1],¤t,sizeof(current));
8044 branch_regs[i-1].isconst=0;
8045 branch_regs[i-1].wasconst=0;
8046 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
8047 alloc_cc(&branch_regs[i-1],i-1);
8048 dirty_reg(&branch_regs[i-1],CCREG);
8049 if(dops[i-1].rt1==31) { // JAL
8050 alloc_reg(&branch_regs[i-1],i-1,31);
8051 dirty_reg(&branch_regs[i-1],31);
8053 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8054 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
8057 memcpy(&branch_regs[i-1],¤t,sizeof(current));
8058 branch_regs[i-1].isconst=0;
8059 branch_regs[i-1].wasconst=0;
8060 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
8061 alloc_cc(&branch_regs[i-1],i-1);
8062 dirty_reg(&branch_regs[i-1],CCREG);
8063 alloc_reg(&branch_regs[i-1],i-1,dops[i-1].rs1);
8064 if(dops[i-1].rt1!=0) { // JALR
8065 alloc_reg(&branch_regs[i-1],i-1,dops[i-1].rt1);
8066 dirty_reg(&branch_regs[i-1],dops[i-1].rt1);
8069 if(dops[i-1].rs1==31) { // JALR
8070 alloc_reg(&branch_regs[i-1],i-1,RHASH);
8071 alloc_reg(&branch_regs[i-1],i-1,RHTBL);
8074 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8075 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
8078 if((dops[i-1].opcode&0x3E)==4) // BEQ/BNE
8080 alloc_cc(¤t,i-1);
8081 dirty_reg(¤t,CCREG);
8082 if((dops[i-1].rs1&&(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2))||
8083 (dops[i-1].rs2&&(dops[i-1].rs2==dops[i].rt1||dops[i-1].rs2==dops[i].rt2))) {
8084 // The delay slot overwrote one of our conditions
8085 // Delay slot goes after the test (in order)
8086 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
8088 delayslot_alloc(¤t,i);
8093 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
8094 // Alloc the branch condition registers
8095 if(dops[i-1].rs1) alloc_reg(¤t,i-1,dops[i-1].rs1);
8096 if(dops[i-1].rs2) alloc_reg(¤t,i-1,dops[i-1].rs2);
8098 memcpy(&branch_regs[i-1],¤t,sizeof(current));
8099 branch_regs[i-1].isconst=0;
8100 branch_regs[i-1].wasconst=0;
8101 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
8102 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
8105 if((dops[i-1].opcode&0x3E)==6) // BLEZ/BGTZ
8107 alloc_cc(¤t,i-1);
8108 dirty_reg(¤t,CCREG);
8109 if(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2) {
8110 // The delay slot overwrote the branch condition
8111 // Delay slot goes after the test (in order)
8112 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
8114 delayslot_alloc(¤t,i);
8119 current.u=branch_unneeded_reg[i-1]&~(1LL<<dops[i-1].rs1);
8120 // Alloc the branch condition register
8121 alloc_reg(¤t,i-1,dops[i-1].rs1);
8123 memcpy(&branch_regs[i-1],¤t,sizeof(current));
8124 branch_regs[i-1].isconst=0;
8125 branch_regs[i-1].wasconst=0;
8126 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
8127 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
8130 // Alloc the delay slot in case the branch is taken
8131 if((dops[i-1].opcode&0x3E)==0x14) // BEQL/BNEL
8133 memcpy(&branch_regs[i-1],¤t,sizeof(current));
8134 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)|(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2)))|1;
8135 alloc_cc(&branch_regs[i-1],i);
8136 dirty_reg(&branch_regs[i-1],CCREG);
8137 delayslot_alloc(&branch_regs[i-1],i);
8138 branch_regs[i-1].isconst=0;
8139 alloc_reg(¤t,i,CCREG); // Not taken path
8140 dirty_reg(¤t,CCREG);
8141 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8144 if((dops[i-1].opcode&0x3E)==0x16) // BLEZL/BGTZL
8146 memcpy(&branch_regs[i-1],¤t,sizeof(current));
8147 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)|(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2)))|1;
8148 alloc_cc(&branch_regs[i-1],i);
8149 dirty_reg(&branch_regs[i-1],CCREG);
8150 delayslot_alloc(&branch_regs[i-1],i);
8151 branch_regs[i-1].isconst=0;
8152 alloc_reg(¤t,i,CCREG); // Not taken path
8153 dirty_reg(¤t,CCREG);
8154 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8158 //if((dops[i-1].opcode2&0x1E)==0) // BLTZ/BGEZ
8159 if((dops[i-1].opcode2&0x0E)==0) // BLTZ/BGEZ
8161 alloc_cc(¤t,i-1);
8162 dirty_reg(¤t,CCREG);
8163 if(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2) {
8164 // The delay slot overwrote the branch condition
8165 // Delay slot goes after the test (in order)
8166 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
8168 delayslot_alloc(¤t,i);
8173 current.u=branch_unneeded_reg[i-1]&~(1LL<<dops[i-1].rs1);
8174 // Alloc the branch condition register
8175 alloc_reg(¤t,i-1,dops[i-1].rs1);
8177 memcpy(&branch_regs[i-1],¤t,sizeof(current));
8178 branch_regs[i-1].isconst=0;
8179 branch_regs[i-1].wasconst=0;
8180 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
8181 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
8184 // Alloc the delay slot in case the branch is taken
8185 if((dops[i-1].opcode2&0x1E)==2) // BLTZL/BGEZL
8187 memcpy(&branch_regs[i-1],¤t,sizeof(current));
8188 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)|(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2)))|1;
8189 alloc_cc(&branch_regs[i-1],i);
8190 dirty_reg(&branch_regs[i-1],CCREG);
8191 delayslot_alloc(&branch_regs[i-1],i);
8192 branch_regs[i-1].isconst=0;
8193 alloc_reg(¤t,i,CCREG); // Not taken path
8194 dirty_reg(¤t,CCREG);
8195 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8197 // FIXME: BLTZAL/BGEZAL
8198 if(dops[i-1].opcode2&0x10) { // BxxZAL
8199 alloc_reg(&branch_regs[i-1],i-1,31);
8200 dirty_reg(&branch_regs[i-1],31);
8205 if (dops[i-1].is_ujump)
8207 if(dops[i-1].rt1==31) // JAL/JALR
8209 // Subroutine call will return here, don't alloc any registers
8211 clear_all_regs(current.regmap);
8212 alloc_reg(¤t,i,CCREG);
8213 dirty_reg(¤t,CCREG);
8217 // Internal branch will jump here, match registers to caller
8219 clear_all_regs(current.regmap);
8220 alloc_reg(¤t,i,CCREG);
8221 dirty_reg(¤t,CCREG);
8224 if(ba[j]==start+i*4+4) {
8225 memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
8226 current.dirty=branch_regs[j].dirty;
8231 if(ba[j]==start+i*4+4) {
8232 for(hr=0;hr<HOST_REGS;hr++) {
8233 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
8234 current.regmap[hr]=-1;
8236 current.dirty&=branch_regs[j].dirty;
8245 // Count cycles in between branches
8246 ccadj[i] = CLOCK_ADJUST(cc);
8247 if (i > 0 && (dops[i-1].is_jump || dops[i].itype == SYSCALL || dops[i].itype == HLECALL))
8251 #if !defined(DRC_DBG)
8252 else if(dops[i].itype==C2OP&>e_cycletab[source[i]&0x3f]>2)
8254 // this should really be removed since the real stalls have been implemented,
8255 // but doing so causes sizeable perf regression against the older version
8256 u_int gtec = gte_cycletab[source[i] & 0x3f];
8257 cc += HACK_ENABLED(NDHACK_NO_STALLS) ? gtec/2 : 2;
8259 else if(i>1&&dops[i].itype==STORE&&dops[i-1].itype==STORE&&dops[i-2].itype==STORE&&!dops[i].bt)
8263 else if(dops[i].itype==C2LS)
8265 // same as with C2OP
8266 cc += HACK_ENABLED(NDHACK_NO_STALLS) ? 4 : 2;
8274 if(!dops[i].is_ds) {
8275 regs[i].dirty=current.dirty;
8276 regs[i].isconst=current.isconst;
8277 memcpy(constmap[i],current_constmap,sizeof(constmap[i]));
8279 for(hr=0;hr<HOST_REGS;hr++) {
8280 if(hr!=EXCLUDE_REG&®s[i].regmap[hr]>=0) {
8281 if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
8282 regs[i].wasconst&=~(1<<hr);
8286 if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
8287 regs[i].waswritten=current.waswritten;
8290 /* Pass 4 - Cull unused host registers */
8294 for (i=slen-1;i>=0;i--)
8299 if(ba[i]<start || ba[i]>=(start+slen*4))
8301 // Branch out of this block, don't need anything
8307 // Need whatever matches the target
8309 int t=(ba[i]-start)>>2;
8310 for(hr=0;hr<HOST_REGS;hr++)
8312 if(regs[i].regmap_entry[hr]>=0) {
8313 if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
8317 // Conditional branch may need registers for following instructions
8318 if (!dops[i].is_ujump)
8321 nr|=needed_reg[i+2];
8322 for(hr=0;hr<HOST_REGS;hr++)
8324 if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
8325 //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
8329 // Don't need stuff which is overwritten
8330 //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
8331 //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
8332 // Merge in delay slot
8333 for(hr=0;hr<HOST_REGS;hr++)
8335 if(dops[i+1].rt1&&dops[i+1].rt1==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
8336 if(dops[i+1].rt2&&dops[i+1].rt2==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
8337 if(dops[i+1].rs1==regmap_pre[i][hr]) nr|=1<<hr;
8338 if(dops[i+1].rs2==regmap_pre[i][hr]) nr|=1<<hr;
8339 if(dops[i+1].rs1==regs[i].regmap_entry[hr]) nr|=1<<hr;
8340 if(dops[i+1].rs2==regs[i].regmap_entry[hr]) nr|=1<<hr;
8341 if(ram_offset && (dops[i+1].is_load || dops[i+1].is_store)) {
8342 if(regmap_pre[i][hr]==ROREG) nr|=1<<hr;
8343 if(regs[i].regmap_entry[hr]==ROREG) nr|=1<<hr;
8345 if(dops[i+1].is_store) {
8346 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
8347 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
8351 else if(dops[i].itype==SYSCALL||dops[i].itype==HLECALL||dops[i].itype==INTCALL)
8353 // SYSCALL instruction (software interrupt)
8356 else if(dops[i].itype==COP0 && (source[i]&0x3f)==0x18)
8358 // ERET instruction (return from interrupt)
8364 for(hr=0;hr<HOST_REGS;hr++) {
8365 if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
8366 if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
8367 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
8368 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
8372 for(hr=0;hr<HOST_REGS;hr++)
8374 // Overwritten registers are not needed
8375 if(dops[i].rt1&&dops[i].rt1==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
8376 if(dops[i].rt2&&dops[i].rt2==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
8377 if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
8378 // Source registers are needed
8379 if(dops[i].rs1==regmap_pre[i][hr]) nr|=1<<hr;
8380 if(dops[i].rs2==regmap_pre[i][hr]) nr|=1<<hr;
8381 if(dops[i].rs1==regs[i].regmap_entry[hr]) nr|=1<<hr;
8382 if(dops[i].rs2==regs[i].regmap_entry[hr]) nr|=1<<hr;
8383 if(ram_offset && (dops[i].is_load || dops[i].is_store)) {
8384 if(regmap_pre[i][hr]==ROREG) nr|=1<<hr;
8385 if(regs[i].regmap_entry[hr]==ROREG) nr|=1<<hr;
8387 if(dops[i].is_store) {
8388 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
8389 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
8391 // Don't store a register immediately after writing it,
8392 // may prevent dual-issue.
8393 // But do so if this is a branch target, otherwise we
8394 // might have to load the register before the branch.
8395 if(i>0&&!dops[i].bt&&((regs[i].wasdirty>>hr)&1)) {
8396 if((regmap_pre[i][hr]>0&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1))) {
8397 if(dops[i-1].rt1==(regmap_pre[i][hr]&63)) nr|=1<<hr;
8398 if(dops[i-1].rt2==(regmap_pre[i][hr]&63)) nr|=1<<hr;
8400 if((regs[i].regmap_entry[hr]>0&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1))) {
8401 if(dops[i-1].rt1==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
8402 if(dops[i-1].rt2==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
8406 // Cycle count is needed at branches. Assume it is needed at the target too.
8407 if(i==0||dops[i].bt||dops[i].itype==CJUMP||dops[i].itype==SPAN) {
8408 if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
8409 if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
8414 // Deallocate unneeded registers
8415 for(hr=0;hr<HOST_REGS;hr++)
8418 if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
8421 int map1 = 0, map2 = 0, temp = 0; // or -1 ??
8422 if (dops[i+1].is_load || dops[i+1].is_store)
8424 if (dops[i+1].is_store)
8426 if(dops[i+1].itype==LOADLR || dops[i+1].itype==STORELR || dops[i+1].itype==C2LS)
8428 if((regs[i].regmap[hr]&63)!=dops[i].rs1 && (regs[i].regmap[hr]&63)!=dops[i].rs2 &&
8429 (regs[i].regmap[hr]&63)!=dops[i].rt1 && (regs[i].regmap[hr]&63)!=dops[i].rt2 &&
8430 (regs[i].regmap[hr]&63)!=dops[i+1].rt1 && (regs[i].regmap[hr]&63)!=dops[i+1].rt2 &&
8431 regs[i].regmap[hr]!=dops[i+1].rs1 && regs[i].regmap[hr]!=dops[i+1].rs2 &&
8432 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
8433 regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
8434 regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
8435 regs[i].regmap[hr]!=map1 && regs[i].regmap[hr]!=map2)
8437 regs[i].regmap[hr]=-1;
8438 regs[i].isconst&=~(1<<hr);
8439 if((branch_regs[i].regmap[hr]&63)!=dops[i].rs1 && (branch_regs[i].regmap[hr]&63)!=dops[i].rs2 &&
8440 (branch_regs[i].regmap[hr]&63)!=dops[i].rt1 && (branch_regs[i].regmap[hr]&63)!=dops[i].rt2 &&
8441 (branch_regs[i].regmap[hr]&63)!=dops[i+1].rt1 && (branch_regs[i].regmap[hr]&63)!=dops[i+1].rt2 &&
8442 branch_regs[i].regmap[hr]!=dops[i+1].rs1 && branch_regs[i].regmap[hr]!=dops[i+1].rs2 &&
8443 (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
8444 branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
8445 branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
8446 branch_regs[i].regmap[hr]!=map1 && branch_regs[i].regmap[hr]!=map2)
8448 branch_regs[i].regmap[hr]=-1;
8449 branch_regs[i].regmap_entry[hr]=-1;
8450 if (!dops[i].is_ujump)
8453 regmap_pre[i+2][hr]=-1;
8454 regs[i+2].wasconst&=~(1<<hr);
8465 int map1 = -1, map2 = -1, temp=-1;
8466 if (dops[i].is_load || dops[i].is_store)
8468 if (dops[i].is_store)
8470 if (dops[i].itype==LOADLR || dops[i].itype==STORELR || dops[i].itype==C2LS)
8472 if((regs[i].regmap[hr]&63)!=dops[i].rt1 && (regs[i].regmap[hr]&63)!=dops[i].rt2 &&
8473 regs[i].regmap[hr]!=dops[i].rs1 && regs[i].regmap[hr]!=dops[i].rs2 &&
8474 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map1 && regs[i].regmap[hr]!=map2 &&
8475 //(dops[i].itype!=SPAN||regs[i].regmap[hr]!=CCREG)
8476 regs[i].regmap[hr] != CCREG)
8478 if(i<slen-1&&!dops[i].is_ds) {
8479 assert(regs[i].regmap[hr]<64);
8480 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]>0)
8481 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
8483 SysPrintf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
8484 assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
8486 regmap_pre[i+1][hr]=-1;
8487 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
8488 regs[i+1].wasconst&=~(1<<hr);
8490 regs[i].regmap[hr]=-1;
8491 regs[i].isconst&=~(1<<hr);
8499 /* Pass 5 - Pre-allocate registers */
8501 // If a register is allocated during a loop, try to allocate it for the
8502 // entire loop, if possible. This avoids loading/storing registers
8503 // inside of the loop.
8505 signed char f_regmap[HOST_REGS];
8506 clear_all_regs(f_regmap);
8507 for(i=0;i<slen-1;i++)
8509 if(dops[i].itype==UJUMP||dops[i].itype==CJUMP||dops[i].itype==SJUMP)
8511 if(ba[i]>=start && ba[i]<(start+i*4))
8512 if(dops[i+1].itype==NOP||dops[i+1].itype==MOV||dops[i+1].itype==ALU
8513 ||dops[i+1].itype==SHIFTIMM||dops[i+1].itype==IMM16||dops[i+1].itype==LOAD
8514 ||dops[i+1].itype==STORE||dops[i+1].itype==STORELR||dops[i+1].itype==C1LS
8515 ||dops[i+1].itype==SHIFT||dops[i+1].itype==COP1
8516 ||dops[i+1].itype==COP2||dops[i+1].itype==C2LS||dops[i+1].itype==C2OP)
8518 int t=(ba[i]-start)>>2;
8519 if(t > 0 && !dops[t-1].is_jump) // loop_preload can't handle jumps into delay slots
8520 if(t<2||(dops[t-2].itype!=UJUMP&&dops[t-2].itype!=RJUMP)||dops[t-2].rt1!=31) // call/ret assumes no registers allocated
8521 for(hr=0;hr<HOST_REGS;hr++)
8523 if(regs[i].regmap[hr]>=0) {
8524 if(f_regmap[hr]!=regs[i].regmap[hr]) {
8525 // dealloc old register
8527 for(n=0;n<HOST_REGS;n++)
8529 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
8531 // and alloc new one
8532 f_regmap[hr]=regs[i].regmap[hr];
8535 if(branch_regs[i].regmap[hr]>=0) {
8536 if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
8537 // dealloc old register
8539 for(n=0;n<HOST_REGS;n++)
8541 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
8543 // and alloc new one
8544 f_regmap[hr]=branch_regs[i].regmap[hr];
8548 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
8549 f_regmap[hr]=branch_regs[i].regmap[hr];
8551 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
8552 f_regmap[hr]=branch_regs[i].regmap[hr];
8554 // Avoid dirty->clean transition
8555 #ifdef DESTRUCTIVE_WRITEBACK
8556 if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
8558 // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
8559 // case above, however it's always a good idea. We can't hoist the
8560 // load if the register was already allocated, so there's no point
8561 // wasting time analyzing most of these cases. It only "succeeds"
8562 // when the mapping was different and the load can be replaced with
8563 // a mov, which is of negligible benefit. So such cases are
8565 if(f_regmap[hr]>0) {
8566 if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
8570 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
8571 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
8573 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
8574 //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
8576 if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
8577 if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
8579 if(get_reg(regs[i].regmap,r&63)<0) break;
8580 if(get_reg(branch_regs[i].regmap,r&63)<0) break;
8583 while(k>1&®s[k-1].regmap[hr]==-1) {
8584 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
8585 //printf("no free regs for store %x\n",start+(k-1)*4);
8588 if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
8589 //printf("no-match due to different register\n");
8592 if (dops[k-2].is_jump) {
8593 //printf("no-match due to branch\n");
8596 // call/ret fast path assumes no registers allocated
8597 if(k>2&&(dops[k-3].itype==UJUMP||dops[k-3].itype==RJUMP)&&dops[k-3].rt1==31) {
8603 if(regs[k-1].regmap[hr]==f_regmap[hr]&®map_pre[k][hr]==f_regmap[hr]) {
8604 //printf("Extend r%d, %x ->\n",hr,start+k*4);
8606 regs[k].regmap_entry[hr]=f_regmap[hr];
8607 regs[k].regmap[hr]=f_regmap[hr];
8608 regmap_pre[k+1][hr]=f_regmap[hr];
8609 regs[k].wasdirty&=~(1<<hr);
8610 regs[k].dirty&=~(1<<hr);
8611 regs[k].wasdirty|=(1<<hr)®s[k-1].dirty;
8612 regs[k].dirty|=(1<<hr)®s[k].wasdirty;
8613 regs[k].wasconst&=~(1<<hr);
8614 regs[k].isconst&=~(1<<hr);
8619 //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
8622 assert(regs[i-1].regmap[hr]==f_regmap[hr]);
8623 if(regs[i-1].regmap[hr]==f_regmap[hr]&®map_pre[i][hr]==f_regmap[hr]) {
8624 //printf("OK fill %x (r%d)\n",start+i*4,hr);
8625 regs[i].regmap_entry[hr]=f_regmap[hr];
8626 regs[i].regmap[hr]=f_regmap[hr];
8627 regs[i].wasdirty&=~(1<<hr);
8628 regs[i].dirty&=~(1<<hr);
8629 regs[i].wasdirty|=(1<<hr)®s[i-1].dirty;
8630 regs[i].dirty|=(1<<hr)®s[i-1].dirty;
8631 regs[i].wasconst&=~(1<<hr);
8632 regs[i].isconst&=~(1<<hr);
8633 branch_regs[i].regmap_entry[hr]=f_regmap[hr];
8634 branch_regs[i].wasdirty&=~(1<<hr);
8635 branch_regs[i].wasdirty|=(1<<hr)®s[i].dirty;
8636 branch_regs[i].regmap[hr]=f_regmap[hr];
8637 branch_regs[i].dirty&=~(1<<hr);
8638 branch_regs[i].dirty|=(1<<hr)®s[i].dirty;
8639 branch_regs[i].wasconst&=~(1<<hr);
8640 branch_regs[i].isconst&=~(1<<hr);
8641 if (!dops[i].is_ujump) {
8642 regmap_pre[i+2][hr]=f_regmap[hr];
8643 regs[i+2].wasdirty&=~(1<<hr);
8644 regs[i+2].wasdirty|=(1<<hr)®s[i].dirty;
8649 // Alloc register clean at beginning of loop,
8650 // but may dirty it in pass 6
8651 regs[k].regmap_entry[hr]=f_regmap[hr];
8652 regs[k].regmap[hr]=f_regmap[hr];
8653 regs[k].dirty&=~(1<<hr);
8654 regs[k].wasconst&=~(1<<hr);
8655 regs[k].isconst&=~(1<<hr);
8656 if (dops[k].is_jump) {
8657 branch_regs[k].regmap_entry[hr]=f_regmap[hr];
8658 branch_regs[k].regmap[hr]=f_regmap[hr];
8659 branch_regs[k].dirty&=~(1<<hr);
8660 branch_regs[k].wasconst&=~(1<<hr);
8661 branch_regs[k].isconst&=~(1<<hr);
8662 if (!dops[k].is_ujump) {
8663 regmap_pre[k+2][hr]=f_regmap[hr];
8664 regs[k+2].wasdirty&=~(1<<hr);
8669 regmap_pre[k+1][hr]=f_regmap[hr];
8670 regs[k+1].wasdirty&=~(1<<hr);
8673 if(regs[j].regmap[hr]==f_regmap[hr])
8674 regs[j].regmap_entry[hr]=f_regmap[hr];
8678 if(regs[j].regmap[hr]>=0)
8680 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
8681 //printf("no-match due to different register\n");
8684 if (dops[j].is_ujump)
8686 // Stop on unconditional branch
8689 if(dops[j].itype==CJUMP||dops[j].itype==SJUMP)
8692 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
8695 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
8698 if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
8699 //printf("no-match due to different register (branch)\n");
8703 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
8704 //printf("No free regs for store %x\n",start+j*4);
8707 assert(f_regmap[hr]<64);
8714 // Non branch or undetermined branch target
8715 for(hr=0;hr<HOST_REGS;hr++)
8717 if(hr!=EXCLUDE_REG) {
8718 if(regs[i].regmap[hr]>=0) {
8719 if(f_regmap[hr]!=regs[i].regmap[hr]) {
8720 // dealloc old register
8722 for(n=0;n<HOST_REGS;n++)
8724 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
8726 // and alloc new one
8727 f_regmap[hr]=regs[i].regmap[hr];
8732 // Try to restore cycle count at branch targets
8734 for(j=i;j<slen-1;j++) {
8735 if(regs[j].regmap[HOST_CCREG]!=-1) break;
8736 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
8737 //printf("no free regs for store %x\n",start+j*4);
8741 if(regs[j].regmap[HOST_CCREG]==CCREG) {
8743 //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
8745 regs[k].regmap_entry[HOST_CCREG]=CCREG;
8746 regs[k].regmap[HOST_CCREG]=CCREG;
8747 regmap_pre[k+1][HOST_CCREG]=CCREG;
8748 regs[k+1].wasdirty|=1<<HOST_CCREG;
8749 regs[k].dirty|=1<<HOST_CCREG;
8750 regs[k].wasconst&=~(1<<HOST_CCREG);
8751 regs[k].isconst&=~(1<<HOST_CCREG);
8754 regs[j].regmap_entry[HOST_CCREG]=CCREG;
8756 // Work backwards from the branch target
8757 if(j>i&&f_regmap[HOST_CCREG]==CCREG)
8759 //printf("Extend backwards\n");
8762 while(regs[k-1].regmap[HOST_CCREG]==-1) {
8763 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
8764 //printf("no free regs for store %x\n",start+(k-1)*4);
8769 if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
8770 //printf("Extend CC, %x ->\n",start+k*4);
8772 regs[k].regmap_entry[HOST_CCREG]=CCREG;
8773 regs[k].regmap[HOST_CCREG]=CCREG;
8774 regmap_pre[k+1][HOST_CCREG]=CCREG;
8775 regs[k+1].wasdirty|=1<<HOST_CCREG;
8776 regs[k].dirty|=1<<HOST_CCREG;
8777 regs[k].wasconst&=~(1<<HOST_CCREG);
8778 regs[k].isconst&=~(1<<HOST_CCREG);
8783 //printf("Fail Extend CC, %x ->\n",start+k*4);
8787 if(dops[i].itype!=STORE&&dops[i].itype!=STORELR&&dops[i].itype!=C1LS&&dops[i].itype!=SHIFT&&
8788 dops[i].itype!=NOP&&dops[i].itype!=MOV&&dops[i].itype!=ALU&&dops[i].itype!=SHIFTIMM&&
8789 dops[i].itype!=IMM16&&dops[i].itype!=LOAD&&dops[i].itype!=COP1)
8791 memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
8796 // This allocates registers (if possible) one instruction prior
8797 // to use, which can avoid a load-use penalty on certain CPUs.
8798 for(i=0;i<slen-1;i++)
8800 if (!i || !dops[i-1].is_jump)
8804 if(dops[i].itype==ALU||dops[i].itype==MOV||dops[i].itype==LOAD||dops[i].itype==SHIFTIMM||dops[i].itype==IMM16
8805 ||((dops[i].itype==COP1||dops[i].itype==COP2)&&dops[i].opcode2<3))
8808 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rs1))>=0)
8810 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
8812 regs[i].regmap[hr]=regs[i+1].regmap[hr];
8813 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
8814 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
8815 regs[i].isconst&=~(1<<hr);
8816 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8817 constmap[i][hr]=constmap[i+1][hr];
8818 regs[i+1].wasdirty&=~(1<<hr);
8819 regs[i].dirty&=~(1<<hr);
8824 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rs2))>=0)
8826 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
8828 regs[i].regmap[hr]=regs[i+1].regmap[hr];
8829 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
8830 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
8831 regs[i].isconst&=~(1<<hr);
8832 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8833 constmap[i][hr]=constmap[i+1][hr];
8834 regs[i+1].wasdirty&=~(1<<hr);
8835 regs[i].dirty&=~(1<<hr);
8839 // Preload target address for load instruction (non-constant)
8840 if(dops[i+1].itype==LOAD&&dops[i+1].rs1&&get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8841 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rt1))>=0)
8843 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
8845 regs[i].regmap[hr]=dops[i+1].rs1;
8846 regmap_pre[i+1][hr]=dops[i+1].rs1;
8847 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8848 regs[i].isconst&=~(1<<hr);
8849 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8850 constmap[i][hr]=constmap[i+1][hr];
8851 regs[i+1].wasdirty&=~(1<<hr);
8852 regs[i].dirty&=~(1<<hr);
8856 // Load source into target register
8857 if(dops[i+1].lt1&&get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8858 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rt1))>=0)
8860 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
8862 regs[i].regmap[hr]=dops[i+1].rs1;
8863 regmap_pre[i+1][hr]=dops[i+1].rs1;
8864 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8865 regs[i].isconst&=~(1<<hr);
8866 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8867 constmap[i][hr]=constmap[i+1][hr];
8868 regs[i+1].wasdirty&=~(1<<hr);
8869 regs[i].dirty&=~(1<<hr);
8873 // Address for store instruction (non-constant)
8874 if(dops[i+1].itype==STORE||dops[i+1].itype==STORELR
8875 ||(dops[i+1].opcode&0x3b)==0x39||(dops[i+1].opcode&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
8876 if(get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8877 hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
8878 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
8879 else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
8881 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
8883 regs[i].regmap[hr]=dops[i+1].rs1;
8884 regmap_pre[i+1][hr]=dops[i+1].rs1;
8885 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8886 regs[i].isconst&=~(1<<hr);
8887 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8888 constmap[i][hr]=constmap[i+1][hr];
8889 regs[i+1].wasdirty&=~(1<<hr);
8890 regs[i].dirty&=~(1<<hr);
8894 if(dops[i+1].itype==LOADLR||(dops[i+1].opcode&0x3b)==0x31||(dops[i+1].opcode&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
8895 if(get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8897 hr=get_reg(regs[i+1].regmap,FTEMP);
8899 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
8901 regs[i].regmap[hr]=dops[i+1].rs1;
8902 regmap_pre[i+1][hr]=dops[i+1].rs1;
8903 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8904 regs[i].isconst&=~(1<<hr);
8905 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8906 constmap[i][hr]=constmap[i+1][hr];
8907 regs[i+1].wasdirty&=~(1<<hr);
8908 regs[i].dirty&=~(1<<hr);
8910 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
8912 // move it to another register
8913 regs[i+1].regmap[hr]=-1;
8914 regmap_pre[i+2][hr]=-1;
8915 regs[i+1].regmap[nr]=FTEMP;
8916 regmap_pre[i+2][nr]=FTEMP;
8917 regs[i].regmap[nr]=dops[i+1].rs1;
8918 regmap_pre[i+1][nr]=dops[i+1].rs1;
8919 regs[i+1].regmap_entry[nr]=dops[i+1].rs1;
8920 regs[i].isconst&=~(1<<nr);
8921 regs[i+1].isconst&=~(1<<nr);
8922 regs[i].dirty&=~(1<<nr);
8923 regs[i+1].wasdirty&=~(1<<nr);
8924 regs[i+1].dirty&=~(1<<nr);
8925 regs[i+2].wasdirty&=~(1<<nr);
8929 if(dops[i+1].itype==LOAD||dops[i+1].itype==LOADLR||dops[i+1].itype==STORE||dops[i+1].itype==STORELR/*||dops[i+1].itype==C1LS||||dops[i+1].itype==C2LS*/) {
8930 if(dops[i+1].itype==LOAD)
8931 hr=get_reg(regs[i+1].regmap,dops[i+1].rt1);
8932 if(dops[i+1].itype==LOADLR||(dops[i+1].opcode&0x3b)==0x31||(dops[i+1].opcode&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
8933 hr=get_reg(regs[i+1].regmap,FTEMP);
8934 if(dops[i+1].itype==STORE||dops[i+1].itype==STORELR||(dops[i+1].opcode&0x3b)==0x39||(dops[i+1].opcode&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
8935 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
8936 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
8938 if(hr>=0&®s[i].regmap[hr]<0) {
8939 int rs=get_reg(regs[i+1].regmap,dops[i+1].rs1);
8940 if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
8941 regs[i].regmap[hr]=AGEN1+((i+1)&1);
8942 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
8943 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
8944 regs[i].isconst&=~(1<<hr);
8945 regs[i+1].wasdirty&=~(1<<hr);
8946 regs[i].dirty&=~(1<<hr);
8955 /* Pass 6 - Optimize clean/dirty state */
8956 clean_registers(0,slen-1,1);
8958 /* Pass 7 - Identify 32-bit registers */
8959 for (i=slen-1;i>=0;i--)
8961 if(dops[i].itype==CJUMP||dops[i].itype==SJUMP)
8963 // Conditional branch
8964 if((source[i]>>16)!=0x1000&&i<slen-2) {
8965 // Mark this address as a branch target since it may be called
8966 // upon return from interrupt
8972 if(dops[slen-1].itype==SPAN) {
8973 dops[slen-1].bt=1; // Mark as a branch target so instruction can restart after exception
8977 /* Debug/disassembly */
8982 for(r=1;r<=CCREG;r++) {
8983 if((unneeded_reg[i]>>r)&1) {
8984 if(r==HIREG) printf(" HI");
8985 else if(r==LOREG) printf(" LO");
8986 else printf(" r%d",r);
8990 #if defined(__i386__) || defined(__x86_64__)
8991 printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
8994 printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
8996 #if defined(__i386__) || defined(__x86_64__)
8998 if(needed_reg[i]&1) printf("eax ");
8999 if((needed_reg[i]>>1)&1) printf("ecx ");
9000 if((needed_reg[i]>>2)&1) printf("edx ");
9001 if((needed_reg[i]>>3)&1) printf("ebx ");
9002 if((needed_reg[i]>>5)&1) printf("ebp ");
9003 if((needed_reg[i]>>6)&1) printf("esi ");
9004 if((needed_reg[i]>>7)&1) printf("edi ");
9006 printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
9008 if(regs[i].wasdirty&1) printf("eax ");
9009 if((regs[i].wasdirty>>1)&1) printf("ecx ");
9010 if((regs[i].wasdirty>>2)&1) printf("edx ");
9011 if((regs[i].wasdirty>>3)&1) printf("ebx ");
9012 if((regs[i].wasdirty>>5)&1) printf("ebp ");
9013 if((regs[i].wasdirty>>6)&1) printf("esi ");
9014 if((regs[i].wasdirty>>7)&1) printf("edi ");
9017 printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
9019 if(regs[i].wasdirty&1) printf("r0 ");
9020 if((regs[i].wasdirty>>1)&1) printf("r1 ");
9021 if((regs[i].wasdirty>>2)&1) printf("r2 ");
9022 if((regs[i].wasdirty>>3)&1) printf("r3 ");
9023 if((regs[i].wasdirty>>4)&1) printf("r4 ");
9024 if((regs[i].wasdirty>>5)&1) printf("r5 ");
9025 if((regs[i].wasdirty>>6)&1) printf("r6 ");
9026 if((regs[i].wasdirty>>7)&1) printf("r7 ");
9027 if((regs[i].wasdirty>>8)&1) printf("r8 ");
9028 if((regs[i].wasdirty>>9)&1) printf("r9 ");
9029 if((regs[i].wasdirty>>10)&1) printf("r10 ");
9030 if((regs[i].wasdirty>>12)&1) printf("r12 ");
9033 disassemble_inst(i);
9034 //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
9035 #if defined(__i386__) || defined(__x86_64__)
9036 printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
9037 if(regs[i].dirty&1) printf("eax ");
9038 if((regs[i].dirty>>1)&1) printf("ecx ");
9039 if((regs[i].dirty>>2)&1) printf("edx ");
9040 if((regs[i].dirty>>3)&1) printf("ebx ");
9041 if((regs[i].dirty>>5)&1) printf("ebp ");
9042 if((regs[i].dirty>>6)&1) printf("esi ");
9043 if((regs[i].dirty>>7)&1) printf("edi ");
9046 printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
9047 if(regs[i].dirty&1) printf("r0 ");
9048 if((regs[i].dirty>>1)&1) printf("r1 ");
9049 if((regs[i].dirty>>2)&1) printf("r2 ");
9050 if((regs[i].dirty>>3)&1) printf("r3 ");
9051 if((regs[i].dirty>>4)&1) printf("r4 ");
9052 if((regs[i].dirty>>5)&1) printf("r5 ");
9053 if((regs[i].dirty>>6)&1) printf("r6 ");
9054 if((regs[i].dirty>>7)&1) printf("r7 ");
9055 if((regs[i].dirty>>8)&1) printf("r8 ");
9056 if((regs[i].dirty>>9)&1) printf("r9 ");
9057 if((regs[i].dirty>>10)&1) printf("r10 ");
9058 if((regs[i].dirty>>12)&1) printf("r12 ");
9061 if(regs[i].isconst) {
9062 printf("constants: ");
9063 #if defined(__i386__) || defined(__x86_64__)
9064 if(regs[i].isconst&1) printf("eax=%x ",(u_int)constmap[i][0]);
9065 if((regs[i].isconst>>1)&1) printf("ecx=%x ",(u_int)constmap[i][1]);
9066 if((regs[i].isconst>>2)&1) printf("edx=%x ",(u_int)constmap[i][2]);
9067 if((regs[i].isconst>>3)&1) printf("ebx=%x ",(u_int)constmap[i][3]);
9068 if((regs[i].isconst>>5)&1) printf("ebp=%x ",(u_int)constmap[i][5]);
9069 if((regs[i].isconst>>6)&1) printf("esi=%x ",(u_int)constmap[i][6]);
9070 if((regs[i].isconst>>7)&1) printf("edi=%x ",(u_int)constmap[i][7]);
9072 #if defined(__arm__) || defined(__aarch64__)
9074 for (r = 0; r < ARRAY_SIZE(constmap[i]); r++)
9075 if ((regs[i].isconst >> r) & 1)
9076 printf(" r%d=%x", r, (u_int)constmap[i][r]);
9080 if(dops[i].is_jump) {
9081 #if defined(__i386__) || defined(__x86_64__)
9082 printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
9083 if(branch_regs[i].dirty&1) printf("eax ");
9084 if((branch_regs[i].dirty>>1)&1) printf("ecx ");
9085 if((branch_regs[i].dirty>>2)&1) printf("edx ");
9086 if((branch_regs[i].dirty>>3)&1) printf("ebx ");
9087 if((branch_regs[i].dirty>>5)&1) printf("ebp ");
9088 if((branch_regs[i].dirty>>6)&1) printf("esi ");
9089 if((branch_regs[i].dirty>>7)&1) printf("edi ");
9092 printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
9093 if(branch_regs[i].dirty&1) printf("r0 ");
9094 if((branch_regs[i].dirty>>1)&1) printf("r1 ");
9095 if((branch_regs[i].dirty>>2)&1) printf("r2 ");
9096 if((branch_regs[i].dirty>>3)&1) printf("r3 ");
9097 if((branch_regs[i].dirty>>4)&1) printf("r4 ");
9098 if((branch_regs[i].dirty>>5)&1) printf("r5 ");
9099 if((branch_regs[i].dirty>>6)&1) printf("r6 ");
9100 if((branch_regs[i].dirty>>7)&1) printf("r7 ");
9101 if((branch_regs[i].dirty>>8)&1) printf("r8 ");
9102 if((branch_regs[i].dirty>>9)&1) printf("r9 ");
9103 if((branch_regs[i].dirty>>10)&1) printf("r10 ");
9104 if((branch_regs[i].dirty>>12)&1) printf("r12 ");
9110 /* Pass 8 - Assembly */
9111 linkcount=0;stubcount=0;
9112 ds=0;is_delayslot=0;
9114 void *beginning=start_block();
9119 void *instr_addr0_override = NULL;
9121 if (start == 0x80030000) {
9122 // nasty hack for the fastbios thing
9123 // override block entry to this code
9124 instr_addr0_override = out;
9125 emit_movimm(start,0);
9126 // abuse io address var as a flag that we
9127 // have already returned here once
9128 emit_readword(&address,1);
9129 emit_writeword(0,&pcaddr);
9130 emit_writeword(0,&address);
9133 emit_jeq(out + 4*2);
9134 emit_far_jump(new_dyna_leave);
9136 emit_jne(new_dyna_leave);
9141 //if(ds) printf("ds: ");
9142 disassemble_inst(i);
9144 ds=0; // Skip delay slot
9145 if(dops[i].bt) assem_debug("OOPS - branch into delay slot\n");
9146 instr_addr[i] = NULL;
9148 speculate_register_values(i);
9149 #ifndef DESTRUCTIVE_WRITEBACK
9150 if (i < 2 || !dops[i-2].is_ujump)
9152 wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,unneeded_reg[i]);
9154 if((dops[i].itype==CJUMP||dops[i].itype==SJUMP)) {
9155 dirty_pre=branch_regs[i].dirty;
9157 dirty_pre=regs[i].dirty;
9161 if (i < 2 || !dops[i-2].is_ujump)
9163 wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,unneeded_reg[i]);
9164 loop_preload(regmap_pre[i],regs[i].regmap_entry);
9166 // branch target entry point
9167 instr_addr[i] = out;
9168 assem_debug("<->\n");
9169 drc_dbg_emit_do_cmp(i, ccadj[i]);
9172 if(regs[i].regmap_entry[HOST_CCREG]==CCREG&®s[i].regmap[HOST_CCREG]!=CCREG)
9173 wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty);
9174 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i].rs1,dops[i].rs2);
9175 address_generation(i,®s[i],regs[i].regmap_entry);
9176 load_consts(regmap_pre[i],regs[i].regmap,i);
9179 // Load the delay slot registers if necessary
9180 if(dops[i+1].rs1!=dops[i].rs1&&dops[i+1].rs1!=dops[i].rs2&&(dops[i+1].rs1!=dops[i].rt1||dops[i].rt1==0))
9181 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs1,dops[i+1].rs1);
9182 if(dops[i+1].rs2!=dops[i+1].rs1&&dops[i+1].rs2!=dops[i].rs1&&dops[i+1].rs2!=dops[i].rs2&&(dops[i+1].rs2!=dops[i].rt1||dops[i].rt1==0))
9183 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2);
9184 if (ram_offset && (dops[i+1].is_load || dops[i+1].is_store))
9185 load_regs(regs[i].regmap_entry,regs[i].regmap,ROREG,ROREG);
9186 if (dops[i+1].is_store)
9187 load_regs(regs[i].regmap_entry,regs[i].regmap,INVCP,INVCP);
9191 // Preload registers for following instruction
9192 if(dops[i+1].rs1!=dops[i].rs1&&dops[i+1].rs1!=dops[i].rs2)
9193 if(dops[i+1].rs1!=dops[i].rt1&&dops[i+1].rs1!=dops[i].rt2)
9194 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs1,dops[i+1].rs1);
9195 if(dops[i+1].rs2!=dops[i+1].rs1&&dops[i+1].rs2!=dops[i].rs1&&dops[i+1].rs2!=dops[i].rs2)
9196 if(dops[i+1].rs2!=dops[i].rt1&&dops[i+1].rs2!=dops[i].rt2)
9197 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2);
9199 // TODO: if(is_ooo(i)) address_generation(i+1);
9200 if (dops[i].itype == CJUMP)
9201 load_regs(regs[i].regmap_entry,regs[i].regmap,CCREG,CCREG);
9202 if (ram_offset && (dops[i].is_load || dops[i].is_store))
9203 load_regs(regs[i].regmap_entry,regs[i].regmap,ROREG,ROREG);
9204 if (dops[i].is_store)
9205 load_regs(regs[i].regmap_entry,regs[i].regmap,INVCP,INVCP);
9207 ds = assemble(i, ®s[i], ccadj[i]);
9209 if (dops[i].is_ujump)
9212 literal_pool_jumpover(256);
9217 if (slen > 0 && dops[slen-1].itype == INTCALL) {
9218 // no ending needed for this block since INTCALL never returns
9220 // If the block did not end with an unconditional branch,
9221 // add a jump to the next instruction.
9223 if (!dops[i-2].is_ujump && dops[i-1].itype != SPAN) {
9224 assert(!dops[i-1].is_jump);
9226 if(dops[i-2].itype!=CJUMP&&dops[i-2].itype!=SJUMP) {
9227 store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4);
9228 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
9229 emit_loadreg(CCREG,HOST_CCREG);
9230 emit_addimm(HOST_CCREG, ccadj[i-1] + CLOCK_ADJUST(1), HOST_CCREG);
9234 store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].dirty,start+i*4);
9235 assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
9237 add_to_linker(out,start+i*4,0);
9244 assert(!dops[i-1].is_jump);
9245 store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4);
9246 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
9247 emit_loadreg(CCREG,HOST_CCREG);
9248 emit_addimm(HOST_CCREG, ccadj[i-1] + CLOCK_ADJUST(1), HOST_CCREG);
9249 add_to_linker(out,start+i*4,0);
9253 // TODO: delay slot stubs?
9255 for(i=0;i<stubcount;i++)
9257 switch(stubs[i].type)
9265 do_readstub(i);break;
9270 do_writestub(i);break;
9274 do_invstub(i);break;
9276 do_cop1stub(i);break;
9278 do_unalignedwritestub(i);break;
9282 if (instr_addr0_override)
9283 instr_addr[0] = instr_addr0_override;
9285 /* Pass 9 - Linker */
9286 for(i=0;i<linkcount;i++)
9288 assem_debug("%p -> %8x\n",link_addr[i].addr,link_addr[i].target);
9290 if (!link_addr[i].ext)
9293 void *addr = check_addr(link_addr[i].target);
9294 emit_extjump(link_addr[i].addr, link_addr[i].target);
9296 set_jump_target(link_addr[i].addr, addr);
9297 add_jump_out(link_addr[i].target,stub);
9300 set_jump_target(link_addr[i].addr, stub);
9305 int target=(link_addr[i].target-start)>>2;
9306 assert(target>=0&&target<slen);
9307 assert(instr_addr[target]);
9308 //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
9309 //set_jump_target_fillslot(link_addr[i].addr,instr_addr[target],link_addr[i].ext>>1);
9311 set_jump_target(link_addr[i].addr, instr_addr[target]);
9316 u_int source_len = slen*4;
9317 if (dops[slen-1].itype == INTCALL && source_len > 4)
9318 // no need to treat the last instruction as compiled
9319 // as interpreter fully handles it
9322 if ((u_char *)copy + source_len > (u_char *)shadow + sizeof(shadow))
9325 // External Branch Targets (jump_in)
9328 if(dops[i].bt||i==0)
9330 if(instr_addr[i]) // TODO - delay slots (=null)
9332 u_int vaddr=start+i*4;
9333 u_int page=get_page(vaddr);
9334 u_int vpage=get_vpage(vaddr);
9337 assem_debug("%p (%d) <- %8x\n",instr_addr[i],i,start+i*4);
9338 assem_debug("jump_in: %x\n",start+i*4);
9339 ll_add(jump_dirty+vpage,vaddr,out);
9340 void *entry_point = do_dirty_stub(i, source_len);
9341 ll_add_flags(jump_in+page,vaddr,state_rflags,entry_point);
9342 // If there was an existing entry in the hash table,
9343 // replace it with the new address.
9344 // Don't add new entries. We'll insert the
9345 // ones that actually get used in check_addr().
9346 struct ht_entry *ht_bin = hash_table_get(vaddr);
9347 if (ht_bin->vaddr[0] == vaddr)
9348 ht_bin->tcaddr[0] = entry_point;
9349 if (ht_bin->vaddr[1] == vaddr)
9350 ht_bin->tcaddr[1] = entry_point;
9355 // Write out the literal pool if necessary
9357 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
9359 if(((u_int)out)&7) emit_addnop(13);
9361 assert(out - (u_char *)beginning < MAX_OUTPUT_BLOCK_SIZE);
9362 //printf("shadow buffer: %p-%p\n",copy,(u_char *)copy+slen*4);
9363 memcpy(copy, source, source_len);
9366 end_block(beginning);
9368 // If we're within 256K of the end of the buffer,
9369 // start over from the beginning. (Is 256K enough?)
9370 if (out > ndrc->translation_cache + sizeof(ndrc->translation_cache) - MAX_OUTPUT_BLOCK_SIZE)
9371 out = ndrc->translation_cache;
9373 // Trap writes to any of the pages we compiled
9374 for(i=start>>12;i<=(start+slen*4)>>12;i++) {
9377 inv_code_start=inv_code_end=~0;
9379 // for PCSX we need to mark all mirrors too
9380 if(get_page(start)<(RAM_SIZE>>12))
9381 for(i=start>>12;i<=(start+slen*4)>>12;i++)
9382 invalid_code[((u_int)0x00000000>>12)|(i&0x1ff)]=
9383 invalid_code[((u_int)0x80000000>>12)|(i&0x1ff)]=
9384 invalid_code[((u_int)0xa0000000>>12)|(i&0x1ff)]=0;
9386 /* Pass 10 - Free memory by expiring oldest blocks */
9388 int end=(((out-ndrc->translation_cache)>>(TARGET_SIZE_2-16))+16384)&65535;
9391 int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
9392 uintptr_t base_offs = ((uintptr_t)(expirep >> 13) << shift); // Base offset of this block
9393 uintptr_t base_offs_s = base_offs >> shift;
9394 inv_debug("EXP: Phase %d\n",expirep);
9395 switch((expirep>>11)&3)
9398 // Clear jump_in and jump_dirty
9399 ll_remove_matching_addrs(jump_in+(expirep&2047),base_offs_s,shift);
9400 ll_remove_matching_addrs(jump_dirty+(expirep&2047),base_offs_s,shift);
9401 ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base_offs_s,shift);
9402 ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base_offs_s,shift);
9406 ll_kill_pointers(jump_out[expirep&2047],base_offs_s,shift);
9407 ll_kill_pointers(jump_out[(expirep&2047)+2048],base_offs_s,shift);
9412 struct ht_entry *ht_bin = &hash_table[((expirep&2047)<<5)+i];
9413 uintptr_t o1 = (u_char *)ht_bin->tcaddr[1] - ndrc->translation_cache;
9414 uintptr_t o2 = o1 - MAX_OUTPUT_BLOCK_SIZE;
9415 if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s) {
9416 inv_debug("EXP: Remove hash %x -> %p\n",ht_bin->vaddr[1],ht_bin->tcaddr[1]);
9417 ht_bin->vaddr[1] = -1;
9418 ht_bin->tcaddr[1] = NULL;
9420 o1 = (u_char *)ht_bin->tcaddr[0] - ndrc->translation_cache;
9421 o2 = o1 - MAX_OUTPUT_BLOCK_SIZE;
9422 if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s) {
9423 inv_debug("EXP: Remove hash %x -> %p\n",ht_bin->vaddr[0],ht_bin->tcaddr[0]);
9424 ht_bin->vaddr[0] = ht_bin->vaddr[1];
9425 ht_bin->tcaddr[0] = ht_bin->tcaddr[1];
9426 ht_bin->vaddr[1] = -1;
9427 ht_bin->tcaddr[1] = NULL;
9433 if((expirep&2047)==0)
9435 ll_remove_matching_addrs(jump_out+(expirep&2047),base_offs_s,shift);
9436 ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base_offs_s,shift);
9439 expirep=(expirep+1)&65535;
9447 // vim:shiftwidth=2:expandtab