1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
3 * Copyright (C) 2009-2011 Ari64 *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
22 #include <stdint.h> //include for uint64_t
27 #include <libkern/OSCacheControl.h>
30 #include <3ds_utils.h>
33 #include "new_dynarec_config.h"
34 #include "../psxhle.h"
35 #include "../psxinterpreter.h"
37 #include "emu_if.h" // emulator interface
38 #include "arm_features.h"
40 #define noinline __attribute__((noinline,noclone))
42 #define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
45 #define min(a, b) ((b) < (a) ? (b) : (a))
48 #define max(a, b) ((b) > (a) ? (b) : (a))
56 #define assem_debug printf
58 #define assem_debug(...)
60 //#define inv_debug printf
61 #define inv_debug(...)
64 #include "assem_x86.h"
67 #include "assem_x64.h"
70 #include "assem_arm.h"
73 #include "assem_arm64.h"
76 #define RAM_SIZE 0x200000
78 #define MAX_OUTPUT_BLOCK_SIZE 262144
81 // apparently Vita has a 16MB limit, so either we cut tc in half,
82 // or use this hack (it's a hack because tc size was designed to be power-of-2)
83 #define TC_REDUCE_BYTES 4096
85 #define TC_REDUCE_BYTES 0
90 u_char translation_cache[(1 << TARGET_SIZE_2) - TC_REDUCE_BYTES];
93 struct tramp_insns ops[2048 / sizeof(struct tramp_insns)];
94 const void *f[2048 / sizeof(void *)];
98 #ifdef BASE_ADDR_DYNAMIC
99 static struct ndrc_mem *ndrc;
101 static struct ndrc_mem ndrc_ __attribute__((aligned(4096)));
102 static struct ndrc_mem *ndrc = &ndrc_;
123 // regmap_pre[i] - regs before [i] insn starts; dirty things here that
124 // don't match .regmap will be written back
125 // [i].regmap_entry - regs that must be set up if someone jumps here
126 // [i].regmap - regs [i] insn will read/(over)write
127 // branch_regs[i].* - same as above but for branches, takes delay slot into account
130 signed char regmap_entry[HOST_REGS];
131 signed char regmap[HOST_REGS];
135 u_int wasconst; // before; for example 'lw r2, (r2)' wasconst is true
136 u_int isconst; // ... but isconst is false when r2 is known
137 u_int loadedconst; // host regs that have constants loaded
138 u_int waswritten; // MIPS regs that were used as store base before
141 // note: asm depends on this layout
146 struct ll_entry *next;
176 struct block_info *next;
179 u_int start; // vaddr of the block start
180 u_int len; // of the whole block source
192 static struct decoded_insn
212 static struct ht_entry hash_table[65536];
213 static struct block_info *blocks[4096];
214 static struct ll_entry *jump_out[4096];
216 static u_int *source;
217 static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
218 static uint64_t gte_rt[MAXBLOCK];
219 static uint64_t gte_unneeded[MAXBLOCK];
220 static u_int smrv[32]; // speculated MIPS register values
221 static u_int smrv_strong; // mask or regs that are likely to have correct values
222 static u_int smrv_weak; // same, but somewhat less likely
223 static u_int smrv_strong_next; // same, but after current insn executes
224 static u_int smrv_weak_next;
225 static int imm[MAXBLOCK];
226 static u_int ba[MAXBLOCK];
227 static uint64_t unneeded_reg[MAXBLOCK];
228 static uint64_t branch_unneeded_reg[MAXBLOCK];
229 // see 'struct regstat' for a description
230 static signed char regmap_pre[MAXBLOCK][HOST_REGS];
231 // contains 'real' consts at [i] insn, but may differ from what's actually
232 // loaded in host reg as 'final' value is always loaded, see get_final_value()
233 static uint32_t current_constmap[HOST_REGS];
234 static uint32_t constmap[MAXBLOCK][HOST_REGS];
235 static struct regstat regs[MAXBLOCK];
236 static struct regstat branch_regs[MAXBLOCK];
237 static signed char minimum_free_regs[MAXBLOCK];
238 static int ccadj[MAXBLOCK];
240 static void *instr_addr[MAXBLOCK];
241 static struct link_entry link_addr[MAXBLOCK];
242 static int linkcount;
243 static struct code_stub stubs[MAXBLOCK*3];
244 static int stubcount;
245 static u_int literals[1024][2];
246 static int literalcount;
247 static int is_delayslot;
248 static char shadow[1048576] __attribute__((aligned(16)));
251 static u_int stop_after_jal;
252 static u_int f1_hack;
254 static int stat_bc_direct;
255 static int stat_bc_pre;
256 static int stat_bc_restore;
257 static int stat_ht_lookups;
258 static int stat_jump_in_lookups;
259 static int stat_restore_tries;
260 static int stat_restore_compares;
261 static int stat_inv_addr_calls;
262 static int stat_inv_hits;
263 static int stat_blocks;
264 static int stat_links;
265 #define stat_inc(s) s++
266 #define stat_dec(s) s--
267 #define stat_clear(s) s = 0
271 #define stat_clear(s)
274 int new_dynarec_hacks;
275 int new_dynarec_hacks_pergame;
276 int new_dynarec_hacks_old;
277 int new_dynarec_did_compile;
279 #define HACK_ENABLED(x) ((new_dynarec_hacks | new_dynarec_hacks_pergame) & (x))
281 extern int cycle_count; // ... until end of the timeslice, counts -N -> 0
282 extern int last_count; // last absolute target, often = next_interupt
284 extern int pending_exception;
285 extern int branch_target;
286 extern uintptr_t ram_offset;
287 extern uintptr_t mini_ht[32][2];
289 /* registers that may be allocated */
291 #define LOREG 32 // lo
292 #define HIREG 33 // hi
293 //#define FSREG 34 // FPU status (FCSR)
294 #define CSREG 35 // Coprocessor status
295 #define CCREG 36 // Cycle count
296 #define INVCP 37 // Pointer to invalid_code
297 //#define MMREG 38 // Pointer to memory_map
298 #define ROREG 39 // ram offset (if rdram!=0x80000000)
300 #define FTEMP 40 // FPU temporary register
301 #define PTEMP 41 // Prefetch temporary register
302 //#define TLREG 42 // TLB mapping offset
303 #define RHASH 43 // Return address hash
304 #define RHTBL 44 // Return address hash table address
305 #define RTEMP 45 // JR/JALR address register
307 #define AGEN1 46 // Address generation temporary register
308 //#define AGEN2 47 // Address generation temporary register
309 //#define MGEN1 48 // Maptable address generation temporary register
310 //#define MGEN2 49 // Maptable address generation temporary register
311 #define BTREG 50 // Branch target temporary register
313 /* instruction types */
314 #define NOP 0 // No operation
315 #define LOAD 1 // Load
316 #define STORE 2 // Store
317 #define LOADLR 3 // Unaligned load
318 #define STORELR 4 // Unaligned store
319 #define MOV 5 // Move
320 #define ALU 6 // Arithmetic/logic
321 #define MULTDIV 7 // Multiply/divide
322 #define SHIFT 8 // Shift by register
323 #define SHIFTIMM 9// Shift by immediate
324 #define IMM16 10 // 16-bit immediate
325 #define RJUMP 11 // Unconditional jump to register
326 #define UJUMP 12 // Unconditional jump
327 #define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
328 #define SJUMP 14 // Conditional branch (regimm format)
329 #define COP0 15 // Coprocessor 0
330 #define COP1 16 // Coprocessor 1
331 #define C1LS 17 // Coprocessor 1 load/store
332 //#define FJUMP 18 // Conditional branch (floating point)
333 //#define FLOAT 19 // Floating point unit
334 //#define FCONV 20 // Convert integer to float
335 //#define FCOMP 21 // Floating point compare (sets FSREG)
336 #define SYSCALL 22// SYSCALL,BREAK
337 #define OTHER 23 // Other
338 //#define SPAN 24 // Branch/delay slot spans 2 pages
339 #define NI 25 // Not implemented
340 #define HLECALL 26// PCSX fake opcodes for HLE
341 #define COP2 27 // Coprocessor 2 move
342 #define C2LS 28 // Coprocessor 2 load/store
343 #define C2OP 29 // Coprocessor 2 operation
344 #define INTCALL 30// Call interpreter to handle rare corner cases
351 #define DJT_1 (void *)1l // no function, just a label in assem_debug log
352 #define DJT_2 (void *)2l
358 void fp_exception_ds();
359 void jump_syscall (u_int u0, u_int u1, u_int pc);
360 void jump_syscall_ds(u_int u0, u_int u1, u_int pc);
361 void jump_break (u_int u0, u_int u1, u_int pc);
362 void jump_break_ds(u_int u0, u_int u1, u_int pc);
363 void jump_to_new_pc();
364 void call_gteStall();
365 void new_dyna_leave();
367 void *ndrc_get_addr_ht_param(u_int vaddr, int can_compile);
368 void *ndrc_get_addr_ht(u_int vaddr);
369 void ndrc_invalidate_addr(u_int addr);
370 void ndrc_add_jump_out(u_int vaddr, void *src);
372 static int new_recompile_block(u_int addr);
373 static void invalidate_block(struct block_info *block);
375 // Needed by assembler
376 static void wb_register(signed char r, const signed char regmap[], uint64_t dirty);
377 static void wb_dirtys(const signed char i_regmap[], uint64_t i_dirty);
378 static void wb_needed_dirtys(const signed char i_regmap[], uint64_t i_dirty, int addr);
379 static void load_all_regs(const signed char i_regmap[]);
380 static void load_needed_regs(const signed char i_regmap[], const signed char next_regmap[]);
381 static void load_regs_entry(int t);
382 static void load_all_consts(const signed char regmap[], u_int dirty, int i);
383 static u_int get_host_reglist(const signed char *regmap);
385 static int get_final_value(int hr, int i, int *value);
386 static void add_stub(enum stub_type type, void *addr, void *retaddr,
387 u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e);
388 static void add_stub_r(enum stub_type type, void *addr, void *retaddr,
389 int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist);
390 static void add_to_linker(void *addr, u_int target, int ext);
391 static void *emit_fastpath_cmp_jump(int i, const struct regstat *i_regs,
392 int addr, int *offset_reg, int *addr_reg_override);
393 static void *get_direct_memhandler(void *table, u_int addr,
394 enum stub_type type, uintptr_t *addr_host);
395 static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist);
396 static void pass_args(int a0, int a1);
397 static void emit_far_jump(const void *f);
398 static void emit_far_call(const void *f);
401 #include <psp2/kernel/sysmem.h>
403 // note: this interacts with RetroArch's Vita bootstrap code: bootstrap/vita/sbrk.c
404 extern int getVMBlock();
405 int _newlib_vm_size_user = sizeof(*ndrc);
408 static void mprotect_w_x(void *start, void *end, int is_x)
412 // *Open* enables write on all memory that was
413 // allocated by sceKernelAllocMemBlockForVM()?
415 sceKernelCloseVMDomain();
417 sceKernelOpenVMDomain();
419 u_long mstart = (u_long)start & ~4095ul;
420 u_long mend = (u_long)end;
421 if (mprotect((void *)mstart, mend - mstart,
422 PROT_READ | (is_x ? PROT_EXEC : PROT_WRITE)) != 0)
423 SysPrintf("mprotect(%c) failed: %s\n", is_x ? 'x' : 'w', strerror(errno));
428 static void start_tcache_write(void *start, void *end)
430 mprotect_w_x(start, end, 0);
433 static void end_tcache_write(void *start, void *end)
435 #if defined(__arm__) || defined(__aarch64__)
436 size_t len = (char *)end - (char *)start;
437 #if defined(__BLACKBERRY_QNX__)
438 msync(start, len, MS_SYNC | MS_CACHE_ONLY | MS_INVALIDATE_ICACHE);
439 #elif defined(__MACH__)
440 sys_cache_control(kCacheFunctionPrepareForExecution, start, len);
442 sceKernelSyncVMDomain(sceBlock, start, len);
444 ctr_flush_invalidate_cache();
445 #elif defined(__aarch64__)
446 // as of 2021, __clear_cache() is still broken on arm64
447 // so here is a custom one :(
448 clear_cache_arm64(start, end);
450 __clear_cache(start, end);
455 mprotect_w_x(start, end, 1);
458 static void *start_block(void)
460 u_char *end = out + MAX_OUTPUT_BLOCK_SIZE;
461 if (end > ndrc->translation_cache + sizeof(ndrc->translation_cache))
462 end = ndrc->translation_cache + sizeof(ndrc->translation_cache);
463 start_tcache_write(out, end);
467 static void end_block(void *start)
469 end_tcache_write(start, out);
472 // also takes care of w^x mappings when patching code
473 static u_int needs_clear_cache[1<<(TARGET_SIZE_2-17)];
475 static void mark_clear_cache(void *target)
477 uintptr_t offset = (u_char *)target - ndrc->translation_cache;
478 u_int mask = 1u << ((offset >> 12) & 31);
479 if (!(needs_clear_cache[offset >> 17] & mask)) {
480 char *start = (char *)((uintptr_t)target & ~4095l);
481 start_tcache_write(start, start + 4095);
482 needs_clear_cache[offset >> 17] |= mask;
486 // Clearing the cache is rather slow on ARM Linux, so mark the areas
487 // that need to be cleared, and then only clear these areas once.
488 static void do_clear_cache(void)
491 for (i = 0; i < (1<<(TARGET_SIZE_2-17)); i++)
493 u_int bitmap = needs_clear_cache[i];
496 for (j = 0; j < 32; j++)
499 if (!(bitmap & (1<<j)))
502 start = ndrc->translation_cache + i*131072 + j*4096;
504 for (j++; j < 32; j++) {
505 if (!(bitmap & (1<<j)))
509 end_tcache_write(start, end);
511 needs_clear_cache[i] = 0;
515 //#define DEBUG_CYCLE_COUNT 1
517 #define NO_CYCLE_PENALTY_THR 12
519 int cycle_multiplier = CYCLE_MULT_DEFAULT; // 100 for 1.0
520 int cycle_multiplier_override;
521 int cycle_multiplier_old;
522 static int cycle_multiplier_active;
524 static int CLOCK_ADJUST(int x)
526 int m = cycle_multiplier_active;
527 int s = (x >> 31) | 1;
528 return (x * m + s * 50) / 100;
531 static int ds_writes_rjump_rs(int i)
533 return dops[i].rs1 != 0 && (dops[i].rs1 == dops[i+1].rt1 || dops[i].rs1 == dops[i+1].rt2);
536 // psx addr mirror masking (for invalidation)
537 static u_int pmmask(u_int vaddr)
539 vaddr &= ~0xe0000000;
540 if (vaddr < 0x01000000)
541 vaddr &= ~0x00e00000; // RAM mirrors
545 static u_int get_page(u_int vaddr)
547 u_int page = pmmask(vaddr) >> 12;
548 if(page>2048) page=2048+(page&2047);
552 // get a page for looking for a block that has vaddr
553 // (needed because the block may start in previous page)
554 static u_int get_page_prev(u_int vaddr)
556 assert(MAXBLOCK <= (1 << 12));
557 u_int page = get_page(vaddr);
563 static struct ht_entry *hash_table_get(u_int vaddr)
565 return &hash_table[((vaddr>>16)^vaddr)&0xFFFF];
568 static void hash_table_add(u_int vaddr, void *tcaddr)
570 struct ht_entry *ht_bin = hash_table_get(vaddr);
572 ht_bin->vaddr[1] = ht_bin->vaddr[0];
573 ht_bin->tcaddr[1] = ht_bin->tcaddr[0];
574 ht_bin->vaddr[0] = vaddr;
575 ht_bin->tcaddr[0] = tcaddr;
578 static void hash_table_remove(int vaddr)
580 //printf("remove hash: %x\n",vaddr);
581 struct ht_entry *ht_bin = hash_table_get(vaddr);
582 if (ht_bin->vaddr[1] == vaddr) {
583 ht_bin->vaddr[1] = -1;
584 ht_bin->tcaddr[1] = NULL;
586 if (ht_bin->vaddr[0] == vaddr) {
587 ht_bin->vaddr[0] = ht_bin->vaddr[1];
588 ht_bin->tcaddr[0] = ht_bin->tcaddr[1];
589 ht_bin->vaddr[1] = -1;
590 ht_bin->tcaddr[1] = NULL;
594 static void mark_invalid_code(u_int vaddr, u_int len, char invalid)
598 for (i = vaddr & ~0xfff; i < vaddr + len; i += 0x1000) {
599 // ram mirrors, but should not hurt bios
600 for (j = 0; j < 0x800000; j += 0x200000) {
601 invalid_code[(i|j) >> 12] =
602 invalid_code[(i|j|0x80000000u) >> 12] =
603 invalid_code[(i|j|0xa0000000u) >> 12] = invalid;
607 inv_code_start = inv_code_end = ~0;
610 // some messy ari64's code, seems to rely on unsigned 32bit overflow
611 static int doesnt_expire_soon(void *tcaddr)
613 u_int diff = (u_int)((u_char *)tcaddr - out) << (32-TARGET_SIZE_2);
614 return diff > (u_int)(0x60000000 + (MAX_OUTPUT_BLOCK_SIZE << (32-TARGET_SIZE_2)));
617 static void *try_restore_block(u_int vaddr, u_int start_page, u_int end_page)
619 void *found_clean = NULL;
622 stat_inc(stat_restore_tries);
623 for (page = start_page; page <= end_page; page++) {
624 struct block_info *block;
625 for (block = blocks[page]; block != NULL; block = block->next) {
626 if (vaddr < block->start)
628 if (!block->is_dirty || vaddr >= block->start + block->len)
630 for (i = 0; i < block->jump_in_cnt; i++)
631 if (block->jump_in[i].vaddr == vaddr)
633 if (i == block->jump_in_cnt)
635 assert(block->source && block->copy);
636 stat_inc(stat_restore_compares);
637 if (memcmp(block->source, block->copy, block->len))
641 found_clean = block->jump_in[i].addr;
642 hash_table_add(vaddr, found_clean);
643 mark_invalid_code(block->start, block->len, 0);
644 stat_inc(stat_bc_restore);
645 inv_debug("INV: restored %08x %p (%d)\n", vaddr, found_clean, block->jump_in_cnt);
652 // Get address from virtual address
653 // This is called from the recompiled JR/JALR instructions
654 static void noinline *get_addr(u_int vaddr, int can_compile)
656 u_int start_page = get_page_prev(vaddr);
657 u_int i, page, end_page = get_page(vaddr);
658 void *found_clean = NULL;
660 stat_inc(stat_jump_in_lookups);
661 for (page = start_page; page <= end_page; page++) {
662 const struct block_info *block;
663 for (block = blocks[page]; block != NULL; block = block->next) {
664 if (vaddr < block->start)
666 if (block->is_dirty || vaddr >= block->start + block->len)
668 for (i = 0; i < block->jump_in_cnt; i++)
669 if (block->jump_in[i].vaddr == vaddr)
671 if (i == block->jump_in_cnt)
673 found_clean = block->jump_in[i].addr;
674 hash_table_add(vaddr, found_clean);
678 found_clean = try_restore_block(vaddr, start_page, end_page);
685 int r = new_recompile_block(vaddr);
687 return ndrc_get_addr_ht(vaddr);
689 // generate an address error
691 Cause=(vaddr<<31)|(4<<2);
692 EPC=(vaddr&1)?vaddr-5:vaddr;
694 return ndrc_get_addr_ht(0x80000080);
697 // Look up address in hash table first
698 void *ndrc_get_addr_ht_param(u_int vaddr, int can_compile)
700 const struct ht_entry *ht_bin = hash_table_get(vaddr);
701 stat_inc(stat_ht_lookups);
702 if (ht_bin->vaddr[0] == vaddr) return ht_bin->tcaddr[0];
703 if (ht_bin->vaddr[1] == vaddr) return ht_bin->tcaddr[1];
704 return get_addr(vaddr, can_compile);
707 void *ndrc_get_addr_ht(u_int vaddr)
709 return ndrc_get_addr_ht_param(vaddr, 1);
712 static void clear_all_regs(signed char regmap[])
714 memset(regmap, -1, sizeof(regmap[0]) * HOST_REGS);
717 // get_reg: get allocated host reg from mips reg
718 // returns -1 if no such mips reg was allocated
719 #if defined(__arm__) && defined(HAVE_ARMV6) && HOST_REGS == 13 && EXCLUDE_REG == 11
721 extern signed char get_reg(const signed char regmap[], signed char r);
725 static signed char get_reg(const signed char regmap[], signed char r)
728 for (hr = 0; hr < HOST_REGS; hr++) {
729 if (hr == EXCLUDE_REG)
739 // get reg as mask bit (1 << hr)
740 static u_int get_regm(const signed char regmap[], signed char r)
742 return (1u << (get_reg(regmap, r) & 31)) & ~(1u << 31);
745 static signed char get_reg_temp(const signed char regmap[])
748 for (hr = 0; hr < HOST_REGS; hr++) {
749 if (hr == EXCLUDE_REG)
751 if (regmap[hr] == (signed char)-1)
757 // Find a register that is available for two consecutive cycles
758 static signed char get_reg2(signed char regmap1[], const signed char regmap2[], int r)
761 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map1[hr]==r&®map2[hr]==r) return hr;
765 // reverse reg map: mips -> host
766 #define RRMAP_SIZE 64
767 static void make_rregs(const signed char regmap[], signed char rrmap[RRMAP_SIZE],
768 u_int *regs_can_change)
770 u_int r, hr, hr_can_change = 0;
771 memset(rrmap, -1, RRMAP_SIZE);
772 for (hr = 0; hr < HOST_REGS; )
775 rrmap[r & (RRMAP_SIZE - 1)] = hr;
776 // only add mips $1-$31+$lo, others shifted out
777 hr_can_change |= (uint64_t)1 << (hr + ((r - 1) & 32));
779 if (hr == EXCLUDE_REG)
782 hr_can_change |= 1u << (rrmap[33] & 31);
783 hr_can_change |= 1u << (rrmap[CCREG] & 31);
784 hr_can_change &= ~(1u << 31);
785 *regs_can_change = hr_can_change;
788 // same as get_reg, but takes rrmap
789 static signed char get_rreg(signed char rrmap[RRMAP_SIZE], signed char r)
791 assert(0 <= r && r < RRMAP_SIZE);
795 static int count_free_regs(const signed char regmap[])
799 for(hr=0;hr<HOST_REGS;hr++)
801 if(hr!=EXCLUDE_REG) {
802 if(regmap[hr]<0) count++;
808 static void dirty_reg(struct regstat *cur, signed char reg)
812 hr = get_reg(cur->regmap, reg);
817 static void set_const(struct regstat *cur, signed char reg, uint32_t value)
821 hr = get_reg(cur->regmap, reg);
823 cur->isconst |= 1<<hr;
824 current_constmap[hr] = value;
828 static void clear_const(struct regstat *cur, signed char reg)
832 hr = get_reg(cur->regmap, reg);
834 cur->isconst &= ~(1<<hr);
837 static int is_const(const struct regstat *cur, signed char reg)
840 if (reg < 0) return 0;
842 hr = get_reg(cur->regmap, reg);
844 return (cur->isconst>>hr)&1;
848 static uint32_t get_const(const struct regstat *cur, signed char reg)
852 hr = get_reg(cur->regmap, reg);
854 return current_constmap[hr];
856 SysPrintf("Unknown constant in r%d\n", reg);
860 // Least soon needed registers
861 // Look at the next ten instructions and see which registers
862 // will be used. Try not to reallocate these.
863 static void lsn(u_char hsn[], int i, int *preferred_reg)
873 if (dops[i+j].is_ujump)
875 // Don't go past an unconditonal jump
882 if(dops[i+j].rs1) hsn[dops[i+j].rs1]=j;
883 if(dops[i+j].rs2) hsn[dops[i+j].rs2]=j;
884 if(dops[i+j].rt1) hsn[dops[i+j].rt1]=j;
885 if(dops[i+j].rt2) hsn[dops[i+j].rt2]=j;
886 if(dops[i+j].itype==STORE || dops[i+j].itype==STORELR) {
887 // Stores can allocate zero
888 hsn[dops[i+j].rs1]=j;
889 hsn[dops[i+j].rs2]=j;
891 if (ram_offset && (dops[i+j].is_load || dops[i+j].is_store))
893 // On some architectures stores need invc_ptr
894 #if defined(HOST_IMM8)
895 if (dops[i+j].is_store)
898 if(i+j>=0&&(dops[i+j].itype==UJUMP||dops[i+j].itype==CJUMP||dops[i+j].itype==SJUMP))
906 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
908 // Follow first branch
909 int t=(ba[i+b]-start)>>2;
910 j=7-b;if(t+j>=slen) j=slen-t-1;
913 if(dops[t+j].rs1) if(hsn[dops[t+j].rs1]>j+b+2) hsn[dops[t+j].rs1]=j+b+2;
914 if(dops[t+j].rs2) if(hsn[dops[t+j].rs2]>j+b+2) hsn[dops[t+j].rs2]=j+b+2;
915 //if(dops[t+j].rt1) if(hsn[dops[t+j].rt1]>j+b+2) hsn[dops[t+j].rt1]=j+b+2;
916 //if(dops[t+j].rt2) if(hsn[dops[t+j].rt2]>j+b+2) hsn[dops[t+j].rt2]=j+b+2;
919 // TODO: preferred register based on backward branch
921 // Delay slot should preferably not overwrite branch conditions or cycle count
922 if (i > 0 && dops[i-1].is_jump) {
923 if(dops[i-1].rs1) if(hsn[dops[i-1].rs1]>1) hsn[dops[i-1].rs1]=1;
924 if(dops[i-1].rs2) if(hsn[dops[i-1].rs2]>1) hsn[dops[i-1].rs2]=1;
930 // Coprocessor load/store needs FTEMP, even if not declared
931 if(dops[i].itype==C2LS) {
934 // Load L/R also uses FTEMP as a temporary register
935 if(dops[i].itype==LOADLR) {
938 // Also SWL/SWR/SDL/SDR
939 if(dops[i].opcode==0x2a||dops[i].opcode==0x2e||dops[i].opcode==0x2c||dops[i].opcode==0x2d) {
942 // Don't remove the miniht registers
943 if(dops[i].itype==UJUMP||dops[i].itype==RJUMP)
950 // We only want to allocate registers if we're going to use them again soon
951 static int needed_again(int r, int i)
957 if (i > 0 && dops[i-1].is_ujump)
959 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
960 return 0; // Don't need any registers if exiting the block
968 if (dops[i+j].is_ujump)
970 // Don't go past an unconditonal jump
974 if(dops[i+j].itype==SYSCALL||dops[i+j].itype==HLECALL||dops[i+j].itype==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
981 if(dops[i+j].rs1==r) rn=j;
982 if(dops[i+j].rs2==r) rn=j;
983 if((unneeded_reg[i+j]>>r)&1) rn=10;
984 if(i+j>=0&&(dops[i+j].itype==UJUMP||dops[i+j].itype==CJUMP||dops[i+j].itype==SJUMP))
994 // Try to match register allocations at the end of a loop with those
996 static int loop_reg(int i, int r, int hr)
1005 if (dops[i+j].is_ujump)
1007 // Don't go past an unconditonal jump
1014 if(dops[i-1].itype==UJUMP||dops[i-1].itype==CJUMP||dops[i-1].itype==SJUMP)
1020 if((unneeded_reg[i+k]>>r)&1) return hr;
1021 if(i+k>=0&&(dops[i+k].itype==UJUMP||dops[i+k].itype==CJUMP||dops[i+k].itype==SJUMP))
1023 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
1025 int t=(ba[i+k]-start)>>2;
1026 int reg=get_reg(regs[t].regmap_entry,r);
1027 if(reg>=0) return reg;
1028 //reg=get_reg(regs[t+1].regmap_entry,r);
1029 //if(reg>=0) return reg;
1037 // Allocate every register, preserving source/target regs
1038 static void alloc_all(struct regstat *cur,int i)
1042 for(hr=0;hr<HOST_REGS;hr++) {
1043 if(hr!=EXCLUDE_REG) {
1044 if((cur->regmap[hr]!=dops[i].rs1)&&(cur->regmap[hr]!=dops[i].rs2)&&
1045 (cur->regmap[hr]!=dops[i].rt1)&&(cur->regmap[hr]!=dops[i].rt2))
1048 cur->dirty&=~(1<<hr);
1051 if(cur->regmap[hr]==0)
1054 cur->dirty&=~(1<<hr);
1061 static int host_tempreg_in_use;
1063 static void host_tempreg_acquire(void)
1065 assert(!host_tempreg_in_use);
1066 host_tempreg_in_use = 1;
1069 static void host_tempreg_release(void)
1071 host_tempreg_in_use = 0;
1074 static void host_tempreg_acquire(void) {}
1075 static void host_tempreg_release(void) {}
1079 extern void gen_interupt();
1080 extern void do_insn_cmp();
1081 #define FUNCNAME(f) { f, " " #f }
1082 static const struct {
1085 } function_names[] = {
1086 FUNCNAME(cc_interrupt),
1087 FUNCNAME(gen_interupt),
1088 FUNCNAME(ndrc_get_addr_ht),
1089 FUNCNAME(jump_handler_read8),
1090 FUNCNAME(jump_handler_read16),
1091 FUNCNAME(jump_handler_read32),
1092 FUNCNAME(jump_handler_write8),
1093 FUNCNAME(jump_handler_write16),
1094 FUNCNAME(jump_handler_write32),
1095 FUNCNAME(ndrc_invalidate_addr),
1096 FUNCNAME(jump_to_new_pc),
1097 FUNCNAME(jump_break),
1098 FUNCNAME(jump_break_ds),
1099 FUNCNAME(jump_syscall),
1100 FUNCNAME(jump_syscall_ds),
1101 FUNCNAME(call_gteStall),
1102 FUNCNAME(new_dyna_leave),
1103 FUNCNAME(pcsx_mtc0),
1104 FUNCNAME(pcsx_mtc0_ds),
1106 FUNCNAME(do_insn_cmp),
1110 static const char *func_name(const void *a)
1113 for (i = 0; i < sizeof(function_names)/sizeof(function_names[0]); i++)
1114 if (function_names[i].addr == a)
1115 return function_names[i].name;
1119 #define func_name(x) ""
1123 #include "assem_x86.c"
1126 #include "assem_x64.c"
1129 #include "assem_arm.c"
1132 #include "assem_arm64.c"
1135 static void *get_trampoline(const void *f)
1139 for (i = 0; i < ARRAY_SIZE(ndrc->tramp.f); i++) {
1140 if (ndrc->tramp.f[i] == f || ndrc->tramp.f[i] == NULL)
1143 if (i == ARRAY_SIZE(ndrc->tramp.f)) {
1144 SysPrintf("trampoline table is full, last func %p\n", f);
1147 if (ndrc->tramp.f[i] == NULL) {
1148 start_tcache_write(&ndrc->tramp.f[i], &ndrc->tramp.f[i + 1]);
1149 ndrc->tramp.f[i] = f;
1150 end_tcache_write(&ndrc->tramp.f[i], &ndrc->tramp.f[i + 1]);
1152 return &ndrc->tramp.ops[i];
1155 static void emit_far_jump(const void *f)
1157 if (can_jump_or_call(f)) {
1162 f = get_trampoline(f);
1166 static void emit_far_call(const void *f)
1168 if (can_jump_or_call(f)) {
1173 f = get_trampoline(f);
1177 // Add virtual address mapping to linked list
1178 static void ll_add(struct ll_entry **head,int vaddr,void *addr)
1180 struct ll_entry *new_entry;
1181 new_entry=malloc(sizeof(struct ll_entry));
1182 assert(new_entry!=NULL);
1183 new_entry->vaddr=vaddr;
1184 new_entry->addr=addr;
1185 new_entry->next=*head;
1189 // Check if an address is already compiled
1190 // but don't return addresses which are about to expire from the cache
1191 static void *check_addr(u_int vaddr)
1193 struct ht_entry *ht_bin = hash_table_get(vaddr);
1195 for (i = 0; i < ARRAY_SIZE(ht_bin->vaddr); i++) {
1196 if (ht_bin->vaddr[i] == vaddr)
1197 if (doesnt_expire_soon((u_char *)ht_bin->tcaddr[i] - MAX_OUTPUT_BLOCK_SIZE))
1198 return ht_bin->tcaddr[i];
1201 // refactor to get_addr_nocompile?
1202 u_int start_page = get_page_prev(vaddr);
1203 u_int page, end_page = get_page(vaddr);
1205 stat_inc(stat_jump_in_lookups);
1206 for (page = start_page; page <= end_page; page++) {
1207 const struct block_info *block;
1208 for (block = blocks[page]; block != NULL; block = block->next) {
1209 if (vaddr < block->start)
1211 if (block->is_dirty || vaddr >= block->start + block->len)
1213 if (!doesnt_expire_soon(ndrc->translation_cache + block->tc_offs))
1215 for (i = 0; i < block->jump_in_cnt; i++)
1216 if (block->jump_in[i].vaddr == vaddr)
1218 if (i == block->jump_in_cnt)
1221 // Update existing entry with current address
1222 void *addr = block->jump_in[i].addr;
1223 if (ht_bin->vaddr[0] == vaddr) {
1224 ht_bin->tcaddr[0] = addr;
1227 if (ht_bin->vaddr[1] == vaddr) {
1228 ht_bin->tcaddr[1] = addr;
1231 // Insert into hash table with low priority.
1232 // Don't evict existing entries, as they are probably
1233 // addresses that are being accessed frequently.
1234 if (ht_bin->vaddr[0] == -1) {
1235 ht_bin->vaddr[0] = vaddr;
1236 ht_bin->tcaddr[0] = addr;
1238 else if (ht_bin->vaddr[1] == -1) {
1239 ht_bin->vaddr[1] = vaddr;
1240 ht_bin->tcaddr[1] = addr;
1248 static void ll_remove_matching_addrs(struct ll_entry **head,
1249 uintptr_t base_offs_s, int shift)
1251 struct ll_entry *next;
1253 uintptr_t o1 = (u_char *)(*head)->addr - ndrc->translation_cache;
1254 uintptr_t o2 = o1 - MAX_OUTPUT_BLOCK_SIZE;
1255 if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s)
1257 inv_debug("EXP: rm pointer to %08x (%p)\n", (*head)->vaddr, (*head)->addr);
1258 hash_table_remove((*head)->vaddr);
1262 stat_dec(stat_links);
1266 head=&((*head)->next);
1271 // Remove all entries from linked list
1272 static void ll_clear(struct ll_entry **head)
1274 struct ll_entry *cur;
1275 struct ll_entry *next;
1287 // Dereference the pointers and remove if it matches
1288 static void ll_kill_pointers(struct ll_entry *head,
1289 uintptr_t base_offs_s, int shift)
1292 u_char *ptr = get_pointer(head->addr);
1293 uintptr_t o1 = ptr - ndrc->translation_cache;
1294 uintptr_t o2 = o1 - MAX_OUTPUT_BLOCK_SIZE;
1295 inv_debug("EXP: Lookup pointer to %p at %p (%x)\n",ptr,head->addr,head->vaddr);
1296 if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s)
1298 inv_debug("EXP: Kill pointer at %p (%x)\n",head->addr,head->vaddr);
1299 void *host_addr=find_extjump_insn(head->addr);
1300 mark_clear_cache(host_addr);
1301 set_jump_target(host_addr, head->addr);
1308 static void blocks_clear(struct block_info **head)
1310 struct block_info *cur, *next;
1312 if ((cur = *head)) {
1322 static void blocks_remove_matching_addrs(struct block_info **head,
1323 uintptr_t base_offs_s, int shift)
1325 struct block_info *next;
1327 u_int o1 = (*head)->tc_offs;
1328 u_int o2 = o1 - MAX_OUTPUT_BLOCK_SIZE;
1329 if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s)
1331 inv_debug("EXP: rm block %08x (tc_offs %u)\n", (*head)->start, o1);
1332 invalidate_block(*head);
1333 next = (*head)->next;
1336 stat_dec(stat_blocks);
1340 head = &((*head)->next);
1345 // This is called when we write to a compiled block (see do_invstub)
1346 static void unlink_jumps_range(u_int start, u_int end)
1348 u_int page, start_page = get_page(start), end_page = get_page(end - 1);
1349 struct ll_entry **head, *next;
1351 for (page = start_page; page <= end_page; page++) {
1352 for (head = &jump_out[page]; *head; ) {
1353 if ((*head)->vaddr < start || (*head)->vaddr >= end) {
1354 head = &((*head)->next);
1357 inv_debug("INV: rm pointer to %08x (%p)\n", (*head)->vaddr, (*head)->addr);
1358 void *host_addr = find_extjump_insn((*head)->addr);
1359 mark_clear_cache(host_addr);
1360 set_jump_target(host_addr, (*head)->addr); // point back to dyna_linker stub
1362 next = (*head)->next;
1365 stat_dec(stat_links);
1370 static void invalidate_block(struct block_info *block)
1374 block->is_dirty = 1;
1375 unlink_jumps_range(block->start, block->start + block->len);
1376 for (i = 0; i < block->jump_in_cnt; i++)
1377 hash_table_remove(block->jump_in[i].vaddr);
1380 static int invalidate_range(u_int start, u_int end,
1381 u32 *inv_start_ret, u32 *inv_end_ret)
1383 u_int start_page = get_page_prev(start);
1384 u_int end_page = get_page(end - 1);
1385 u_int start_m = pmmask(start);
1386 u_int end_m = pmmask(end);
1387 u_int inv_start, inv_end;
1388 u_int blk_start_m, blk_end_m;
1392 // additional area without code (to supplement invalid_code[]), [start, end)
1393 // avoids excessive ndrc_invalidate_addr() calls
1394 inv_start = start_m & ~0xfff;
1395 inv_end = end_m | 0xfff;
1397 for (page = start_page; page <= end_page; page++) {
1398 struct block_info *block;
1399 for (block = blocks[page]; block != NULL; block = block->next) {
1400 if (block->is_dirty)
1402 blk_end_m = pmmask(block->start + block->len);
1403 if (blk_end_m <= start_m) {
1404 inv_start = max(inv_start, blk_end_m);
1407 blk_start_m = pmmask(block->start);
1408 if (end_m <= blk_start_m) {
1409 inv_end = min(inv_end, blk_start_m - 1);
1412 if (!block->source) // "hack" block - leave it alone
1416 invalidate_block(block);
1417 stat_inc(stat_inv_hits);
1424 memset(mini_ht, -1, sizeof(mini_ht));
1427 if (inv_start <= (start_m & ~0xfff) && inv_end >= (start_m | 0xfff))
1428 // the whole page is empty now
1429 mark_invalid_code(start, 1, 1);
1431 if (inv_start_ret) *inv_start_ret = inv_start | (start & 0xe0000000);
1432 if (inv_end_ret) *inv_end_ret = inv_end | (end & 0xe0000000);
1436 void new_dynarec_invalidate_range(unsigned int start, unsigned int end)
1438 invalidate_range(start, end, NULL, NULL);
1441 void ndrc_invalidate_addr(u_int addr)
1443 // this check is done by the caller
1444 //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
1445 int ret = invalidate_range(addr, addr + 4, &inv_code_start, &inv_code_end);
1447 inv_debug("INV ADDR: %08x hit %d blocks\n", addr, ret);
1449 inv_debug("INV ADDR: %08x miss, inv %08x-%08x\n", addr, inv_code_start, inv_code_end);
1450 stat_inc(stat_inv_addr_calls);
1453 // This is called when loading a save state.
1454 // Anything could have changed, so invalidate everything.
1455 void new_dynarec_invalidate_all_pages(void)
1457 struct block_info *block;
1459 for (page = 0; page < ARRAY_SIZE(blocks); page++) {
1460 for (block = blocks[page]; block != NULL; block = block->next) {
1461 if (block->is_dirty)
1463 if (!block->source) // hack block?
1465 invalidate_block(block);
1470 memset(mini_ht,-1,sizeof(mini_ht));
1475 static void do_invstub(int n)
1478 u_int reglist=stubs[n].a;
1479 set_jump_target(stubs[n].addr, out);
1481 if(stubs[n].b!=0) emit_mov(stubs[n].b,0);
1482 emit_far_call(ndrc_invalidate_addr);
1483 restore_regs(reglist);
1484 emit_jmp(stubs[n].retaddr); // return address
1487 // Add an entry to jump_out after making a link
1488 // src should point to code by emit_extjump()
1489 void ndrc_add_jump_out(u_int vaddr,void *src)
1491 u_int page=get_page(vaddr);
1492 inv_debug("ndrc_add_jump_out: %p -> %x (%d)\n",src,vaddr,page);
1493 check_extjump2(src);
1494 ll_add(jump_out+page,vaddr,src);
1495 //inv_debug("ndrc_add_jump_out: to %p\n",get_pointer(src));
1496 stat_inc(stat_links);
1499 /* Register allocation */
1501 // Note: registers are allocated clean (unmodified state)
1502 // if you intend to modify the register, you must call dirty_reg().
1503 static void alloc_reg(struct regstat *cur,int i,signed char reg)
1506 int preferred_reg = PREFERRED_REG_FIRST
1507 + reg % (PREFERRED_REG_LAST - PREFERRED_REG_FIRST + 1);
1508 if (reg == CCREG) preferred_reg = HOST_CCREG;
1509 if (reg == PTEMP || reg == FTEMP) preferred_reg = 12;
1510 assert(PREFERRED_REG_FIRST != EXCLUDE_REG && EXCLUDE_REG != HOST_REGS);
1513 // Don't allocate unused registers
1514 if((cur->u>>reg)&1) return;
1516 // see if it's already allocated
1517 if (get_reg(cur->regmap, reg) >= 0)
1520 // Keep the same mapping if the register was already allocated in a loop
1521 preferred_reg = loop_reg(i,reg,preferred_reg);
1523 // Try to allocate the preferred register
1524 if(cur->regmap[preferred_reg]==-1) {
1525 cur->regmap[preferred_reg]=reg;
1526 cur->dirty&=~(1<<preferred_reg);
1527 cur->isconst&=~(1<<preferred_reg);
1530 r=cur->regmap[preferred_reg];
1533 cur->regmap[preferred_reg]=reg;
1534 cur->dirty&=~(1<<preferred_reg);
1535 cur->isconst&=~(1<<preferred_reg);
1539 // Clear any unneeded registers
1540 // We try to keep the mapping consistent, if possible, because it
1541 // makes branches easier (especially loops). So we try to allocate
1542 // first (see above) before removing old mappings. If this is not
1543 // possible then go ahead and clear out the registers that are no
1545 for(hr=0;hr<HOST_REGS;hr++)
1550 if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
1554 // Try to allocate any available register, but prefer
1555 // registers that have not been used recently.
1557 for (hr = PREFERRED_REG_FIRST; ; ) {
1558 if (cur->regmap[hr] < 0) {
1559 int oldreg = regs[i-1].regmap[hr];
1560 if (oldreg < 0 || (oldreg != dops[i-1].rs1 && oldreg != dops[i-1].rs2
1561 && oldreg != dops[i-1].rt1 && oldreg != dops[i-1].rt2))
1563 cur->regmap[hr]=reg;
1564 cur->dirty&=~(1<<hr);
1565 cur->isconst&=~(1<<hr);
1570 if (hr == EXCLUDE_REG)
1572 if (hr == HOST_REGS)
1574 if (hr == PREFERRED_REG_FIRST)
1579 // Try to allocate any available register
1580 for (hr = PREFERRED_REG_FIRST; ; ) {
1581 if (cur->regmap[hr] < 0) {
1582 cur->regmap[hr]=reg;
1583 cur->dirty&=~(1<<hr);
1584 cur->isconst&=~(1<<hr);
1588 if (hr == EXCLUDE_REG)
1590 if (hr == HOST_REGS)
1592 if (hr == PREFERRED_REG_FIRST)
1596 // Ok, now we have to evict someone
1597 // Pick a register we hopefully won't need soon
1598 u_char hsn[MAXREG+1];
1599 memset(hsn,10,sizeof(hsn));
1601 lsn(hsn,i,&preferred_reg);
1602 //printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",cur->regmap[0],cur->regmap[1],cur->regmap[2],cur->regmap[3],cur->regmap[5],cur->regmap[6],cur->regmap[7]);
1603 //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
1605 // Don't evict the cycle count at entry points, otherwise the entry
1606 // stub will have to write it.
1607 if(dops[i].bt&&hsn[CCREG]>2) hsn[CCREG]=2;
1608 if (i>1 && hsn[CCREG] > 2 && dops[i-2].is_jump) hsn[CCREG]=2;
1611 // Alloc preferred register if available
1612 if(hsn[r=cur->regmap[preferred_reg]&63]==j) {
1613 for(hr=0;hr<HOST_REGS;hr++) {
1614 // Evict both parts of a 64-bit register
1615 if(cur->regmap[hr]==r) {
1617 cur->dirty&=~(1<<hr);
1618 cur->isconst&=~(1<<hr);
1621 cur->regmap[preferred_reg]=reg;
1624 for(r=1;r<=MAXREG;r++)
1626 if(hsn[r]==j&&r!=dops[i-1].rs1&&r!=dops[i-1].rs2&&r!=dops[i-1].rt1&&r!=dops[i-1].rt2) {
1627 for(hr=0;hr<HOST_REGS;hr++) {
1628 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
1629 if(cur->regmap[hr]==r) {
1630 cur->regmap[hr]=reg;
1631 cur->dirty&=~(1<<hr);
1632 cur->isconst&=~(1<<hr);
1643 for(r=1;r<=MAXREG;r++)
1646 for(hr=0;hr<HOST_REGS;hr++) {
1647 if(cur->regmap[hr]==r) {
1648 cur->regmap[hr]=reg;
1649 cur->dirty&=~(1<<hr);
1650 cur->isconst&=~(1<<hr);
1657 SysPrintf("This shouldn't happen (alloc_reg)");abort();
1660 // Allocate a temporary register. This is done without regard to
1661 // dirty status or whether the register we request is on the unneeded list
1662 // Note: This will only allocate one register, even if called multiple times
1663 static void alloc_reg_temp(struct regstat *cur,int i,signed char reg)
1666 int preferred_reg = -1;
1668 // see if it's already allocated
1669 for(hr=0;hr<HOST_REGS;hr++)
1671 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==reg) return;
1674 // Try to allocate any available register
1675 for(hr=HOST_REGS-1;hr>=0;hr--) {
1676 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
1677 cur->regmap[hr]=reg;
1678 cur->dirty&=~(1<<hr);
1679 cur->isconst&=~(1<<hr);
1684 // Find an unneeded register
1685 for(hr=HOST_REGS-1;hr>=0;hr--)
1691 if(i==0||((unneeded_reg[i-1]>>r)&1)) {
1692 cur->regmap[hr]=reg;
1693 cur->dirty&=~(1<<hr);
1694 cur->isconst&=~(1<<hr);
1701 // Ok, now we have to evict someone
1702 // Pick a register we hopefully won't need soon
1703 // TODO: we might want to follow unconditional jumps here
1704 // TODO: get rid of dupe code and make this into a function
1705 u_char hsn[MAXREG+1];
1706 memset(hsn,10,sizeof(hsn));
1708 lsn(hsn,i,&preferred_reg);
1709 //printf("hsn: %d %d %d %d %d %d %d\n",hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
1711 // Don't evict the cycle count at entry points, otherwise the entry
1712 // stub will have to write it.
1713 if(dops[i].bt&&hsn[CCREG]>2) hsn[CCREG]=2;
1714 if (i>1 && hsn[CCREG] > 2 && dops[i-2].is_jump) hsn[CCREG]=2;
1717 for(r=1;r<=MAXREG;r++)
1719 if(hsn[r]==j&&r!=dops[i-1].rs1&&r!=dops[i-1].rs2&&r!=dops[i-1].rt1&&r!=dops[i-1].rt2) {
1720 for(hr=0;hr<HOST_REGS;hr++) {
1721 if(hr!=HOST_CCREG||hsn[CCREG]>2) {
1722 if(cur->regmap[hr]==r) {
1723 cur->regmap[hr]=reg;
1724 cur->dirty&=~(1<<hr);
1725 cur->isconst&=~(1<<hr);
1736 for(r=1;r<=MAXREG;r++)
1739 for(hr=0;hr<HOST_REGS;hr++) {
1740 if(cur->regmap[hr]==r) {
1741 cur->regmap[hr]=reg;
1742 cur->dirty&=~(1<<hr);
1743 cur->isconst&=~(1<<hr);
1750 SysPrintf("This shouldn't happen");abort();
1753 static void mov_alloc(struct regstat *current,int i)
1755 if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) {
1756 alloc_cc(current,i); // for stalls
1757 dirty_reg(current,CCREG);
1760 // Note: Don't need to actually alloc the source registers
1761 //alloc_reg(current,i,dops[i].rs1);
1762 alloc_reg(current,i,dops[i].rt1);
1764 clear_const(current,dops[i].rs1);
1765 clear_const(current,dops[i].rt1);
1766 dirty_reg(current,dops[i].rt1);
1769 static void shiftimm_alloc(struct regstat *current,int i)
1771 if(dops[i].opcode2<=0x3) // SLL/SRL/SRA
1774 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1775 else dops[i].use_lt1=!!dops[i].rs1;
1776 alloc_reg(current,i,dops[i].rt1);
1777 dirty_reg(current,dops[i].rt1);
1778 if(is_const(current,dops[i].rs1)) {
1779 int v=get_const(current,dops[i].rs1);
1780 if(dops[i].opcode2==0x00) set_const(current,dops[i].rt1,v<<imm[i]);
1781 if(dops[i].opcode2==0x02) set_const(current,dops[i].rt1,(u_int)v>>imm[i]);
1782 if(dops[i].opcode2==0x03) set_const(current,dops[i].rt1,v>>imm[i]);
1784 else clear_const(current,dops[i].rt1);
1789 clear_const(current,dops[i].rs1);
1790 clear_const(current,dops[i].rt1);
1793 if(dops[i].opcode2>=0x38&&dops[i].opcode2<=0x3b) // DSLL/DSRL/DSRA
1797 if(dops[i].opcode2==0x3c) // DSLL32
1801 if(dops[i].opcode2==0x3e) // DSRL32
1805 if(dops[i].opcode2==0x3f) // DSRA32
1811 static void shift_alloc(struct regstat *current,int i)
1814 if(dops[i].opcode2<=0x07) // SLLV/SRLV/SRAV
1816 if(dops[i].rs1) alloc_reg(current,i,dops[i].rs1);
1817 if(dops[i].rs2) alloc_reg(current,i,dops[i].rs2);
1818 alloc_reg(current,i,dops[i].rt1);
1819 if(dops[i].rt1==dops[i].rs2) {
1820 alloc_reg_temp(current,i,-1);
1821 minimum_free_regs[i]=1;
1823 } else { // DSLLV/DSRLV/DSRAV
1826 clear_const(current,dops[i].rs1);
1827 clear_const(current,dops[i].rs2);
1828 clear_const(current,dops[i].rt1);
1829 dirty_reg(current,dops[i].rt1);
1833 static void alu_alloc(struct regstat *current,int i)
1835 if(dops[i].opcode2>=0x20&&dops[i].opcode2<=0x23) { // ADD/ADDU/SUB/SUBU
1837 if(dops[i].rs1&&dops[i].rs2) {
1838 alloc_reg(current,i,dops[i].rs1);
1839 alloc_reg(current,i,dops[i].rs2);
1842 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1843 if(dops[i].rs2&&needed_again(dops[i].rs2,i)) alloc_reg(current,i,dops[i].rs2);
1845 alloc_reg(current,i,dops[i].rt1);
1848 if(dops[i].opcode2==0x2a||dops[i].opcode2==0x2b) { // SLT/SLTU
1850 alloc_reg(current,i,dops[i].rs1);
1851 alloc_reg(current,i,dops[i].rs2);
1852 alloc_reg(current,i,dops[i].rt1);
1855 if(dops[i].opcode2>=0x24&&dops[i].opcode2<=0x27) { // AND/OR/XOR/NOR
1857 if(dops[i].rs1&&dops[i].rs2) {
1858 alloc_reg(current,i,dops[i].rs1);
1859 alloc_reg(current,i,dops[i].rs2);
1863 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1864 if(dops[i].rs2&&needed_again(dops[i].rs2,i)) alloc_reg(current,i,dops[i].rs2);
1866 alloc_reg(current,i,dops[i].rt1);
1869 if(dops[i].opcode2>=0x2c&&dops[i].opcode2<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1872 clear_const(current,dops[i].rs1);
1873 clear_const(current,dops[i].rs2);
1874 clear_const(current,dops[i].rt1);
1875 dirty_reg(current,dops[i].rt1);
1878 static void imm16_alloc(struct regstat *current,int i)
1880 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1881 else dops[i].use_lt1=!!dops[i].rs1;
1882 if(dops[i].rt1) alloc_reg(current,i,dops[i].rt1);
1883 if(dops[i].opcode==0x18||dops[i].opcode==0x19) { // DADDI/DADDIU
1886 else if(dops[i].opcode==0x0a||dops[i].opcode==0x0b) { // SLTI/SLTIU
1887 clear_const(current,dops[i].rs1);
1888 clear_const(current,dops[i].rt1);
1890 else if(dops[i].opcode>=0x0c&&dops[i].opcode<=0x0e) { // ANDI/ORI/XORI
1891 if(is_const(current,dops[i].rs1)) {
1892 int v=get_const(current,dops[i].rs1);
1893 if(dops[i].opcode==0x0c) set_const(current,dops[i].rt1,v&imm[i]);
1894 if(dops[i].opcode==0x0d) set_const(current,dops[i].rt1,v|imm[i]);
1895 if(dops[i].opcode==0x0e) set_const(current,dops[i].rt1,v^imm[i]);
1897 else clear_const(current,dops[i].rt1);
1899 else if(dops[i].opcode==0x08||dops[i].opcode==0x09) { // ADDI/ADDIU
1900 if(is_const(current,dops[i].rs1)) {
1901 int v=get_const(current,dops[i].rs1);
1902 set_const(current,dops[i].rt1,v+imm[i]);
1904 else clear_const(current,dops[i].rt1);
1907 set_const(current,dops[i].rt1,imm[i]<<16); // LUI
1909 dirty_reg(current,dops[i].rt1);
1912 static void load_alloc(struct regstat *current,int i)
1914 clear_const(current,dops[i].rt1);
1915 //if(dops[i].rs1!=dops[i].rt1&&needed_again(dops[i].rs1,i)) clear_const(current,dops[i].rs1); // Does this help or hurt?
1916 if(!dops[i].rs1) current->u&=~1LL; // Allow allocating r0 if it's the source register
1917 if (needed_again(dops[i].rs1, i))
1918 alloc_reg(current, i, dops[i].rs1);
1920 alloc_reg(current, i, ROREG);
1921 if(dops[i].rt1&&!((current->u>>dops[i].rt1)&1)) {
1922 alloc_reg(current,i,dops[i].rt1);
1923 assert(get_reg(current->regmap,dops[i].rt1)>=0);
1924 if(dops[i].opcode==0x27||dops[i].opcode==0x37) // LWU/LD
1928 else if(dops[i].opcode==0x1A||dops[i].opcode==0x1B) // LDL/LDR
1932 dirty_reg(current,dops[i].rt1);
1933 // LWL/LWR need a temporary register for the old value
1934 if(dops[i].opcode==0x22||dops[i].opcode==0x26)
1936 alloc_reg(current,i,FTEMP);
1937 alloc_reg_temp(current,i,-1);
1938 minimum_free_regs[i]=1;
1943 // Load to r0 or unneeded register (dummy load)
1944 // but we still need a register to calculate the address
1945 if(dops[i].opcode==0x22||dops[i].opcode==0x26)
1947 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1949 alloc_reg_temp(current,i,-1);
1950 minimum_free_regs[i]=1;
1951 if(dops[i].opcode==0x1A||dops[i].opcode==0x1B) // LDL/LDR
1958 static void store_alloc(struct regstat *current,int i)
1960 clear_const(current,dops[i].rs2);
1961 if(!(dops[i].rs2)) current->u&=~1LL; // Allow allocating r0 if necessary
1962 if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1963 alloc_reg(current,i,dops[i].rs2);
1964 if(dops[i].opcode==0x2c||dops[i].opcode==0x2d||dops[i].opcode==0x3f) { // 64-bit SDL/SDR/SD
1968 alloc_reg(current, i, ROREG);
1969 #if defined(HOST_IMM8)
1970 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1971 alloc_reg(current, i, INVCP);
1973 if(dops[i].opcode==0x2a||dops[i].opcode==0x2e||dops[i].opcode==0x2c||dops[i].opcode==0x2d) { // SWL/SWL/SDL/SDR
1974 alloc_reg(current,i,FTEMP);
1976 // We need a temporary register for address generation
1977 alloc_reg_temp(current,i,-1);
1978 minimum_free_regs[i]=1;
1981 static void c1ls_alloc(struct regstat *current,int i)
1983 clear_const(current,dops[i].rt1);
1984 alloc_reg(current,i,CSREG); // Status
1987 static void c2ls_alloc(struct regstat *current,int i)
1989 clear_const(current,dops[i].rt1);
1990 if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1991 alloc_reg(current,i,FTEMP);
1993 alloc_reg(current, i, ROREG);
1994 #if defined(HOST_IMM8)
1995 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1996 if (dops[i].opcode == 0x3a) // SWC2
1997 alloc_reg(current,i,INVCP);
1999 // We need a temporary register for address generation
2000 alloc_reg_temp(current,i,-1);
2001 minimum_free_regs[i]=1;
2004 #ifndef multdiv_alloc
2005 static void multdiv_alloc(struct regstat *current,int i)
2012 // case 0x1D: DMULTU
2015 clear_const(current,dops[i].rs1);
2016 clear_const(current,dops[i].rs2);
2017 alloc_cc(current,i); // for stalls
2018 if(dops[i].rs1&&dops[i].rs2)
2020 if((dops[i].opcode2&4)==0) // 32-bit
2022 current->u&=~(1LL<<HIREG);
2023 current->u&=~(1LL<<LOREG);
2024 alloc_reg(current,i,HIREG);
2025 alloc_reg(current,i,LOREG);
2026 alloc_reg(current,i,dops[i].rs1);
2027 alloc_reg(current,i,dops[i].rs2);
2028 dirty_reg(current,HIREG);
2029 dirty_reg(current,LOREG);
2038 // Multiply by zero is zero.
2039 // MIPS does not have a divide by zero exception.
2040 // The result is undefined, we return zero.
2041 alloc_reg(current,i,HIREG);
2042 alloc_reg(current,i,LOREG);
2043 dirty_reg(current,HIREG);
2044 dirty_reg(current,LOREG);
2049 static void cop0_alloc(struct regstat *current,int i)
2051 if(dops[i].opcode2==0) // MFC0
2054 clear_const(current,dops[i].rt1);
2055 alloc_all(current,i);
2056 alloc_reg(current,i,dops[i].rt1);
2057 dirty_reg(current,dops[i].rt1);
2060 else if(dops[i].opcode2==4) // MTC0
2063 clear_const(current,dops[i].rs1);
2064 alloc_reg(current,i,dops[i].rs1);
2065 alloc_all(current,i);
2068 alloc_all(current,i); // FIXME: Keep r0
2070 alloc_reg(current,i,0);
2075 // TLBR/TLBWI/TLBWR/TLBP/ERET
2076 assert(dops[i].opcode2==0x10);
2077 alloc_all(current,i);
2079 minimum_free_regs[i]=HOST_REGS;
2082 static void cop2_alloc(struct regstat *current,int i)
2084 if (dops[i].opcode2 < 3) // MFC2/CFC2
2086 alloc_cc(current,i); // for stalls
2087 dirty_reg(current,CCREG);
2089 clear_const(current,dops[i].rt1);
2090 alloc_reg(current,i,dops[i].rt1);
2091 dirty_reg(current,dops[i].rt1);
2094 else if (dops[i].opcode2 > 3) // MTC2/CTC2
2097 clear_const(current,dops[i].rs1);
2098 alloc_reg(current,i,dops[i].rs1);
2102 alloc_reg(current,i,0);
2105 alloc_reg_temp(current,i,-1);
2106 minimum_free_regs[i]=1;
2109 static void c2op_alloc(struct regstat *current,int i)
2111 alloc_cc(current,i); // for stalls
2112 dirty_reg(current,CCREG);
2113 alloc_reg_temp(current,i,-1);
2116 static void syscall_alloc(struct regstat *current,int i)
2118 alloc_cc(current,i);
2119 dirty_reg(current,CCREG);
2120 alloc_all(current,i);
2121 minimum_free_regs[i]=HOST_REGS;
2125 static void delayslot_alloc(struct regstat *current,int i)
2127 switch(dops[i].itype) {
2135 imm16_alloc(current,i);
2139 load_alloc(current,i);
2143 store_alloc(current,i);
2146 alu_alloc(current,i);
2149 shift_alloc(current,i);
2152 multdiv_alloc(current,i);
2155 shiftimm_alloc(current,i);
2158 mov_alloc(current,i);
2161 cop0_alloc(current,i);
2166 cop2_alloc(current,i);
2169 c1ls_alloc(current,i);
2172 c2ls_alloc(current,i);
2175 c2op_alloc(current,i);
2180 static void add_stub(enum stub_type type, void *addr, void *retaddr,
2181 u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e)
2183 assert(stubcount < ARRAY_SIZE(stubs));
2184 stubs[stubcount].type = type;
2185 stubs[stubcount].addr = addr;
2186 stubs[stubcount].retaddr = retaddr;
2187 stubs[stubcount].a = a;
2188 stubs[stubcount].b = b;
2189 stubs[stubcount].c = c;
2190 stubs[stubcount].d = d;
2191 stubs[stubcount].e = e;
2195 static void add_stub_r(enum stub_type type, void *addr, void *retaddr,
2196 int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist)
2198 add_stub(type, addr, retaddr, i, addr_reg, (uintptr_t)i_regs, ccadj, reglist);
2201 // Write out a single register
2202 static void wb_register(signed char r, const signed char regmap[], uint64_t dirty)
2205 for(hr=0;hr<HOST_REGS;hr++) {
2206 if(hr!=EXCLUDE_REG) {
2209 assert(regmap[hr]<64);
2210 emit_storereg(r,hr);
2217 static void wb_valid(signed char pre[],signed char entry[],u_int dirty_pre,u_int dirty,uint64_t u)
2219 //if(dirty_pre==dirty) return;
2221 for (hr = 0; hr < HOST_REGS; hr++) {
2223 if (r < 1 || r > 33 || ((u >> r) & 1))
2225 if (((dirty_pre & ~dirty) >> hr) & 1)
2226 emit_storereg(r, hr);
2231 static void pass_args(int a0, int a1)
2235 emit_mov(a0,2); emit_mov(a1,1); emit_mov(2,0);
2237 else if(a0!=0&&a1==0) {
2239 if (a0>=0) emit_mov(a0,0);
2242 if(a0>=0&&a0!=0) emit_mov(a0,0);
2243 if(a1>=0&&a1!=1) emit_mov(a1,1);
2247 static void alu_assemble(int i, const struct regstat *i_regs)
2249 if(dops[i].opcode2>=0x20&&dops[i].opcode2<=0x23) { // ADD/ADDU/SUB/SUBU
2251 signed char s1,s2,t;
2252 t=get_reg(i_regs->regmap,dops[i].rt1);
2254 s1=get_reg(i_regs->regmap,dops[i].rs1);
2255 s2=get_reg(i_regs->regmap,dops[i].rs2);
2256 if(dops[i].rs1&&dops[i].rs2) {
2259 if(dops[i].opcode2&2) emit_sub(s1,s2,t);
2260 else emit_add(s1,s2,t);
2262 else if(dops[i].rs1) {
2263 if(s1>=0) emit_mov(s1,t);
2264 else emit_loadreg(dops[i].rs1,t);
2266 else if(dops[i].rs2) {
2268 if(dops[i].opcode2&2) emit_neg(s2,t);
2269 else emit_mov(s2,t);
2272 emit_loadreg(dops[i].rs2,t);
2273 if(dops[i].opcode2&2) emit_neg(t,t);
2276 else emit_zeroreg(t);
2280 if(dops[i].opcode2>=0x2c&&dops[i].opcode2<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2283 if(dops[i].opcode2==0x2a||dops[i].opcode2==0x2b) { // SLT/SLTU
2285 signed char s1l,s2l,t;
2287 t=get_reg(i_regs->regmap,dops[i].rt1);
2290 s1l=get_reg(i_regs->regmap,dops[i].rs1);
2291 s2l=get_reg(i_regs->regmap,dops[i].rs2);
2292 if(dops[i].rs2==0) // rx<r0
2294 if(dops[i].opcode2==0x2a&&dops[i].rs1!=0) { // SLT
2296 emit_shrimm(s1l,31,t);
2298 else // SLTU (unsigned can not be less than zero, 0<0)
2301 else if(dops[i].rs1==0) // r0<rx
2304 if(dops[i].opcode2==0x2a) // SLT
2305 emit_set_gz32(s2l,t);
2306 else // SLTU (set if not zero)
2307 emit_set_nz32(s2l,t);
2310 assert(s1l>=0);assert(s2l>=0);
2311 if(dops[i].opcode2==0x2a) // SLT
2312 emit_set_if_less32(s1l,s2l,t);
2314 emit_set_if_carry32(s1l,s2l,t);
2320 if(dops[i].opcode2>=0x24&&dops[i].opcode2<=0x27) { // AND/OR/XOR/NOR
2322 signed char s1l,s2l,tl;
2323 tl=get_reg(i_regs->regmap,dops[i].rt1);
2326 s1l=get_reg(i_regs->regmap,dops[i].rs1);
2327 s2l=get_reg(i_regs->regmap,dops[i].rs2);
2328 if(dops[i].rs1&&dops[i].rs2) {
2331 if(dops[i].opcode2==0x24) { // AND
2332 emit_and(s1l,s2l,tl);
2334 if(dops[i].opcode2==0x25) { // OR
2335 emit_or(s1l,s2l,tl);
2337 if(dops[i].opcode2==0x26) { // XOR
2338 emit_xor(s1l,s2l,tl);
2340 if(dops[i].opcode2==0x27) { // NOR
2341 emit_or(s1l,s2l,tl);
2347 if(dops[i].opcode2==0x24) { // AND
2350 if(dops[i].opcode2==0x25||dops[i].opcode2==0x26) { // OR/XOR
2352 if(s1l>=0) emit_mov(s1l,tl);
2353 else emit_loadreg(dops[i].rs1,tl); // CHECK: regmap_entry?
2357 if(s2l>=0) emit_mov(s2l,tl);
2358 else emit_loadreg(dops[i].rs2,tl); // CHECK: regmap_entry?
2360 else emit_zeroreg(tl);
2362 if(dops[i].opcode2==0x27) { // NOR
2364 if(s1l>=0) emit_not(s1l,tl);
2366 emit_loadreg(dops[i].rs1,tl);
2372 if(s2l>=0) emit_not(s2l,tl);
2374 emit_loadreg(dops[i].rs2,tl);
2378 else emit_movimm(-1,tl);
2387 static void imm16_assemble(int i, const struct regstat *i_regs)
2389 if (dops[i].opcode==0x0f) { // LUI
2392 t=get_reg(i_regs->regmap,dops[i].rt1);
2395 if(!((i_regs->isconst>>t)&1))
2396 emit_movimm(imm[i]<<16,t);
2400 if(dops[i].opcode==0x08||dops[i].opcode==0x09) { // ADDI/ADDIU
2403 t=get_reg(i_regs->regmap,dops[i].rt1);
2404 s=get_reg(i_regs->regmap,dops[i].rs1);
2409 if(!((i_regs->isconst>>t)&1)) {
2411 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
2412 emit_addimm(t,imm[i],t);
2414 if(!((i_regs->wasconst>>s)&1))
2415 emit_addimm(s,imm[i],t);
2417 emit_movimm(constmap[i][s]+imm[i],t);
2423 if(!((i_regs->isconst>>t)&1))
2424 emit_movimm(imm[i],t);
2429 if(dops[i].opcode==0x18||dops[i].opcode==0x19) { // DADDI/DADDIU
2432 tl=get_reg(i_regs->regmap,dops[i].rt1);
2433 sl=get_reg(i_regs->regmap,dops[i].rs1);
2437 emit_addimm(sl,imm[i],tl);
2439 emit_movimm(imm[i],tl);
2444 else if(dops[i].opcode==0x0a||dops[i].opcode==0x0b) { // SLTI/SLTIU
2446 //assert(dops[i].rs1!=0); // r0 might be valid, but it's probably a bug
2448 t=get_reg(i_regs->regmap,dops[i].rt1);
2449 sl=get_reg(i_regs->regmap,dops[i].rs1);
2453 if(dops[i].opcode==0x0a) { // SLTI
2455 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
2456 emit_slti32(t,imm[i],t);
2458 emit_slti32(sl,imm[i],t);
2463 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
2464 emit_sltiu32(t,imm[i],t);
2466 emit_sltiu32(sl,imm[i],t);
2470 // SLTI(U) with r0 is just stupid,
2471 // nonetheless examples can be found
2472 if(dops[i].opcode==0x0a) // SLTI
2473 if(0<imm[i]) emit_movimm(1,t);
2474 else emit_zeroreg(t);
2477 if(imm[i]) emit_movimm(1,t);
2478 else emit_zeroreg(t);
2484 else if(dops[i].opcode>=0x0c&&dops[i].opcode<=0x0e) { // ANDI/ORI/XORI
2487 tl=get_reg(i_regs->regmap,dops[i].rt1);
2488 sl=get_reg(i_regs->regmap,dops[i].rs1);
2489 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2490 if(dops[i].opcode==0x0c) //ANDI
2494 if(i_regs->regmap_entry[tl]!=dops[i].rs1) emit_loadreg(dops[i].rs1,tl);
2495 emit_andimm(tl,imm[i],tl);
2497 if(!((i_regs->wasconst>>sl)&1))
2498 emit_andimm(sl,imm[i],tl);
2500 emit_movimm(constmap[i][sl]&imm[i],tl);
2510 if(i_regs->regmap_entry[tl]!=dops[i].rs1) emit_loadreg(dops[i].rs1,tl);
2512 if(dops[i].opcode==0x0d) { // ORI
2514 emit_orimm(tl,imm[i],tl);
2516 if(!((i_regs->wasconst>>sl)&1))
2517 emit_orimm(sl,imm[i],tl);
2519 emit_movimm(constmap[i][sl]|imm[i],tl);
2522 if(dops[i].opcode==0x0e) { // XORI
2524 emit_xorimm(tl,imm[i],tl);
2526 if(!((i_regs->wasconst>>sl)&1))
2527 emit_xorimm(sl,imm[i],tl);
2529 emit_movimm(constmap[i][sl]^imm[i],tl);
2534 emit_movimm(imm[i],tl);
2542 static void shiftimm_assemble(int i, const struct regstat *i_regs)
2544 if(dops[i].opcode2<=0x3) // SLL/SRL/SRA
2548 t=get_reg(i_regs->regmap,dops[i].rt1);
2549 s=get_reg(i_regs->regmap,dops[i].rs1);
2551 if(t>=0&&!((i_regs->isconst>>t)&1)){
2558 if(s<0&&i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
2560 if(dops[i].opcode2==0) // SLL
2562 emit_shlimm(s<0?t:s,imm[i],t);
2564 if(dops[i].opcode2==2) // SRL
2566 emit_shrimm(s<0?t:s,imm[i],t);
2568 if(dops[i].opcode2==3) // SRA
2570 emit_sarimm(s<0?t:s,imm[i],t);
2574 if(s>=0 && s!=t) emit_mov(s,t);
2578 //emit_storereg(dops[i].rt1,t); //DEBUG
2581 if(dops[i].opcode2>=0x38&&dops[i].opcode2<=0x3b) // DSLL/DSRL/DSRA
2585 if(dops[i].opcode2==0x3c) // DSLL32
2589 if(dops[i].opcode2==0x3e) // DSRL32
2593 if(dops[i].opcode2==0x3f) // DSRA32
2599 #ifndef shift_assemble
2600 static void shift_assemble(int i, const struct regstat *i_regs)
2602 signed char s,t,shift;
2603 if (dops[i].rt1 == 0)
2605 assert(dops[i].opcode2<=0x07); // SLLV/SRLV/SRAV
2606 t = get_reg(i_regs->regmap, dops[i].rt1);
2607 s = get_reg(i_regs->regmap, dops[i].rs1);
2608 shift = get_reg(i_regs->regmap, dops[i].rs2);
2614 else if(dops[i].rs2==0) {
2616 if(s!=t) emit_mov(s,t);
2619 host_tempreg_acquire();
2620 emit_andimm(shift,31,HOST_TEMPREG);
2621 switch(dops[i].opcode2) {
2623 emit_shl(s,HOST_TEMPREG,t);
2626 emit_shr(s,HOST_TEMPREG,t);
2629 emit_sar(s,HOST_TEMPREG,t);
2634 host_tempreg_release();
2648 static int get_ptr_mem_type(u_int a)
2650 if(a < 0x00200000) {
2651 if(a<0x1000&&((start>>20)==0xbfc||(start>>24)==0xa0))
2652 // return wrong, must use memhandler for BIOS self-test to pass
2653 // 007 does similar stuff from a00 mirror, weird stuff
2657 if(0x1f800000 <= a && a < 0x1f801000)
2659 if(0x80200000 <= a && a < 0x80800000)
2661 if(0xa0000000 <= a && a < 0xa0200000)
2666 static int get_ro_reg(const struct regstat *i_regs, int host_tempreg_free)
2668 int r = get_reg(i_regs->regmap, ROREG);
2669 if (r < 0 && host_tempreg_free) {
2670 host_tempreg_acquire();
2671 emit_loadreg(ROREG, r = HOST_TEMPREG);
2678 static void *emit_fastpath_cmp_jump(int i, const struct regstat *i_regs,
2679 int addr, int *offset_reg, int *addr_reg_override)
2683 int mr = dops[i].rs1;
2685 if(((smrv_strong|smrv_weak)>>mr)&1) {
2686 type=get_ptr_mem_type(smrv[mr]);
2687 //printf("set %08x @%08x r%d %d\n", smrv[mr], start+i*4, mr, type);
2690 // use the mirror we are running on
2691 type=get_ptr_mem_type(start);
2692 //printf("set nospec @%08x r%d %d\n", start+i*4, mr, type);
2695 if(type==MTYPE_8020) { // RAM 80200000+ mirror
2696 host_tempreg_acquire();
2697 emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
2698 addr=*addr_reg_override=HOST_TEMPREG;
2701 else if(type==MTYPE_0000) { // RAM 0 mirror
2702 host_tempreg_acquire();
2703 emit_orimm(addr,0x80000000,HOST_TEMPREG);
2704 addr=*addr_reg_override=HOST_TEMPREG;
2707 else if(type==MTYPE_A000) { // RAM A mirror
2708 host_tempreg_acquire();
2709 emit_andimm(addr,~0x20000000,HOST_TEMPREG);
2710 addr=*addr_reg_override=HOST_TEMPREG;
2713 else if(type==MTYPE_1F80) { // scratchpad
2714 if (psxH == (void *)0x1f800000) {
2715 host_tempreg_acquire();
2716 emit_xorimm(addr,0x1f800000,HOST_TEMPREG);
2717 emit_cmpimm(HOST_TEMPREG,0x1000);
2718 host_tempreg_release();
2723 // do the usual RAM check, jump will go to the right handler
2728 if (type == 0) // need ram check
2730 emit_cmpimm(addr,RAM_SIZE);
2732 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2733 // Hint to branch predictor that the branch is unlikely to be taken
2734 if (dops[i].rs1 >= 28)
2735 emit_jno_unlikely(0);
2739 if (ram_offset != 0)
2740 *offset_reg = get_ro_reg(i_regs, 0);
2746 // return memhandler, or get directly accessable address and return 0
2747 static void *get_direct_memhandler(void *table, u_int addr,
2748 enum stub_type type, uintptr_t *addr_host)
2750 uintptr_t msb = 1ull << (sizeof(uintptr_t)*8 - 1);
2751 uintptr_t l1, l2 = 0;
2752 l1 = ((uintptr_t *)table)[addr>>12];
2754 uintptr_t v = l1 << 1;
2755 *addr_host = v + addr;
2760 if (type == LOADB_STUB || type == LOADBU_STUB || type == STOREB_STUB)
2761 l2 = ((uintptr_t *)l1)[0x1000/4 + 0x1000/2 + (addr&0xfff)];
2762 else if (type == LOADH_STUB || type == LOADHU_STUB || type == STOREH_STUB)
2763 l2 = ((uintptr_t *)l1)[0x1000/4 + (addr&0xfff)/2];
2765 l2 = ((uintptr_t *)l1)[(addr&0xfff)/4];
2767 uintptr_t v = l2 << 1;
2768 *addr_host = v + (addr&0xfff);
2771 return (void *)(l2 << 1);
2775 static u_int get_host_reglist(const signed char *regmap)
2777 u_int reglist = 0, hr;
2778 for (hr = 0; hr < HOST_REGS; hr++) {
2779 if (hr != EXCLUDE_REG && regmap[hr] >= 0)
2785 static u_int reglist_exclude(u_int reglist, int r1, int r2)
2788 reglist &= ~(1u << r1);
2790 reglist &= ~(1u << r2);
2794 // find a temp caller-saved register not in reglist (so assumed to be free)
2795 static int reglist_find_free(u_int reglist)
2797 u_int free_regs = ~reglist & CALLER_SAVE_REGS;
2800 return __builtin_ctz(free_regs);
2803 static void do_load_word(int a, int rt, int offset_reg)
2805 if (offset_reg >= 0)
2806 emit_ldr_dualindexed(offset_reg, a, rt);
2808 emit_readword_indexed(0, a, rt);
2811 static void do_store_word(int a, int ofs, int rt, int offset_reg, int preseve_a)
2813 if (offset_reg < 0) {
2814 emit_writeword_indexed(rt, ofs, a);
2818 emit_addimm(a, ofs, a);
2819 emit_str_dualindexed(offset_reg, a, rt);
2820 if (ofs != 0 && preseve_a)
2821 emit_addimm(a, -ofs, a);
2824 static void do_store_hword(int a, int ofs, int rt, int offset_reg, int preseve_a)
2826 if (offset_reg < 0) {
2827 emit_writehword_indexed(rt, ofs, a);
2831 emit_addimm(a, ofs, a);
2832 emit_strh_dualindexed(offset_reg, a, rt);
2833 if (ofs != 0 && preseve_a)
2834 emit_addimm(a, -ofs, a);
2837 static void do_store_byte(int a, int rt, int offset_reg)
2839 if (offset_reg >= 0)
2840 emit_strb_dualindexed(offset_reg, a, rt);
2842 emit_writebyte_indexed(rt, 0, a);
2845 static void load_assemble(int i, const struct regstat *i_regs, int ccadj_)
2850 int memtarget=0,c=0;
2851 int offset_reg = -1;
2852 int fastio_reg_override = -1;
2853 u_int reglist=get_host_reglist(i_regs->regmap);
2854 tl=get_reg(i_regs->regmap,dops[i].rt1);
2855 s=get_reg(i_regs->regmap,dops[i].rs1);
2857 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2859 c=(i_regs->wasconst>>s)&1;
2861 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2864 //printf("load_assemble: c=%d\n",c);
2865 //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset);
2866 // FIXME: Even if the load is a NOP, we should check for pagefaults...
2867 if((tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80))
2869 // could be FIFO, must perform the read
2871 assem_debug("(forced read)\n");
2872 tl=get_reg_temp(i_regs->regmap);
2875 if(offset||s<0||c) addr=tl;
2877 //if(tl<0) tl=get_reg_temp(i_regs->regmap);
2879 //printf("load_assemble: c=%d\n",c);
2880 //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset);
2881 assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2885 // Strmnnrmn's speed hack
2886 if(dops[i].rs1!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2889 jaddr = emit_fastpath_cmp_jump(i, i_regs, addr,
2890 &offset_reg, &fastio_reg_override);
2893 else if (ram_offset && memtarget) {
2894 offset_reg = get_ro_reg(i_regs, 0);
2896 int dummy=(dops[i].rt1==0)||(tl!=get_reg(i_regs->regmap,dops[i].rt1)); // ignore loads to r0 and unneeded reg
2897 switch (dops[i].opcode) {
2903 if (fastio_reg_override >= 0)
2904 a = fastio_reg_override;
2906 if (offset_reg >= 0)
2907 emit_ldrsb_dualindexed(offset_reg, a, tl);
2909 emit_movsbl_indexed(0, a, tl);
2912 add_stub_r(LOADB_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
2915 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
2922 if (fastio_reg_override >= 0)
2923 a = fastio_reg_override;
2924 if (offset_reg >= 0)
2925 emit_ldrsh_dualindexed(offset_reg, a, tl);
2927 emit_movswl_indexed(0, a, tl);
2930 add_stub_r(LOADH_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
2933 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
2939 if (fastio_reg_override >= 0)
2940 a = fastio_reg_override;
2941 do_load_word(a, tl, offset_reg);
2944 add_stub_r(LOADW_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
2947 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
2954 if (fastio_reg_override >= 0)
2955 a = fastio_reg_override;
2957 if (offset_reg >= 0)
2958 emit_ldrb_dualindexed(offset_reg, a, tl);
2960 emit_movzbl_indexed(0, a, tl);
2963 add_stub_r(LOADBU_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
2966 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
2973 if (fastio_reg_override >= 0)
2974 a = fastio_reg_override;
2975 if (offset_reg >= 0)
2976 emit_ldrh_dualindexed(offset_reg, a, tl);
2978 emit_movzwl_indexed(0, a, tl);
2981 add_stub_r(LOADHU_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
2984 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
2992 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
2993 host_tempreg_release();
2996 #ifndef loadlr_assemble
2997 static void loadlr_assemble(int i, const struct regstat *i_regs, int ccadj_)
2999 int s,tl,temp,temp2,addr;
3002 int memtarget=0,c=0;
3003 int offset_reg = -1;
3004 int fastio_reg_override = -1;
3005 u_int reglist=get_host_reglist(i_regs->regmap);
3006 tl=get_reg(i_regs->regmap,dops[i].rt1);
3007 s=get_reg(i_regs->regmap,dops[i].rs1);
3008 temp=get_reg_temp(i_regs->regmap);
3009 temp2=get_reg(i_regs->regmap,FTEMP);
3010 addr=get_reg(i_regs->regmap,AGEN1+(i&1));
3014 if(offset||s<0||c) addr=temp2;
3017 c=(i_regs->wasconst>>s)&1;
3019 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3023 emit_shlimm(addr,3,temp);
3024 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
3025 emit_andimm(addr,0xFFFFFFFC,temp2); // LWL/LWR
3027 emit_andimm(addr,0xFFFFFFF8,temp2); // LDL/LDR
3029 jaddr = emit_fastpath_cmp_jump(i, i_regs, temp2,
3030 &offset_reg, &fastio_reg_override);
3033 if (ram_offset && memtarget) {
3034 offset_reg = get_ro_reg(i_regs, 0);
3036 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
3037 emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR
3039 emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR
3042 if (dops[i].opcode==0x22||dops[i].opcode==0x26) { // LWL/LWR
3045 if (fastio_reg_override >= 0)
3046 a = fastio_reg_override;
3047 do_load_word(a, temp2, offset_reg);
3048 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
3049 host_tempreg_release();
3050 if(jaddr) add_stub_r(LOADW_STUB,jaddr,out,i,temp2,i_regs,ccadj_,reglist);
3053 inline_readstub(LOADW_STUB,i,(constmap[i][s]+offset)&0xFFFFFFFC,i_regs->regmap,FTEMP,ccadj_,reglist);
3056 emit_andimm(temp,24,temp);
3057 if (dops[i].opcode==0x22) // LWL
3058 emit_xorimm(temp,24,temp);
3059 host_tempreg_acquire();
3060 emit_movimm(-1,HOST_TEMPREG);
3061 if (dops[i].opcode==0x26) {
3062 emit_shr(temp2,temp,temp2);
3063 emit_bic_lsr(tl,HOST_TEMPREG,temp,tl);
3065 emit_shl(temp2,temp,temp2);
3066 emit_bic_lsl(tl,HOST_TEMPREG,temp,tl);
3068 host_tempreg_release();
3069 emit_or(temp2,tl,tl);
3071 //emit_storereg(dops[i].rt1,tl); // DEBUG
3073 if (dops[i].opcode==0x1A||dops[i].opcode==0x1B) { // LDL/LDR
3079 static void store_assemble(int i, const struct regstat *i_regs, int ccadj_)
3085 enum stub_type type=0;
3086 int memtarget=0,c=0;
3087 int agr=AGEN1+(i&1);
3088 int offset_reg = -1;
3089 int fastio_reg_override = -1;
3090 u_int reglist=get_host_reglist(i_regs->regmap);
3091 tl=get_reg(i_regs->regmap,dops[i].rs2);
3092 s=get_reg(i_regs->regmap,dops[i].rs1);
3093 temp=get_reg(i_regs->regmap,agr);
3094 if(temp<0) temp=get_reg_temp(i_regs->regmap);
3097 c=(i_regs->wasconst>>s)&1;
3099 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3104 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3105 if(offset||s<0||c) addr=temp;
3108 jaddr = emit_fastpath_cmp_jump(i, i_regs, addr,
3109 &offset_reg, &fastio_reg_override);
3111 else if (ram_offset && memtarget) {
3112 offset_reg = get_ro_reg(i_regs, 0);
3115 switch (dops[i].opcode) {
3120 if (fastio_reg_override >= 0)
3121 a = fastio_reg_override;
3122 do_store_byte(a, tl, offset_reg);
3130 if (fastio_reg_override >= 0)
3131 a = fastio_reg_override;
3132 do_store_hword(a, 0, tl, offset_reg, 1);
3139 if (fastio_reg_override >= 0)
3140 a = fastio_reg_override;
3141 do_store_word(a, 0, tl, offset_reg, 1);
3149 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
3150 host_tempreg_release();
3152 // PCSX store handlers don't check invcode again
3154 add_stub_r(type,jaddr,out,i,addr,i_regs,ccadj_,reglist);
3157 if(!(i_regs->waswritten&(1<<dops[i].rs1)) && !HACK_ENABLED(NDHACK_NO_SMC_CHECK)) {
3159 #ifdef DESTRUCTIVE_SHIFT
3160 // The x86 shift operation is 'destructive'; it overwrites the
3161 // source register, so we need to make a copy first and use that.
3164 #if defined(HOST_IMM8)
3165 int ir=get_reg(i_regs->regmap,INVCP);
3167 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3169 emit_cmpmem_indexedsr12_imm(invalid_code,addr,1);
3171 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3172 emit_callne(invalidate_addr_reg[addr]);
3176 add_stub(INVCODE_STUB,jaddr2,out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3180 u_int addr_val=constmap[i][s]+offset;
3182 add_stub_r(type,jaddr,out,i,addr,i_regs,ccadj_,reglist);
3183 } else if(c&&!memtarget) {
3184 inline_writestub(type,i,addr_val,i_regs->regmap,dops[i].rs2,ccadj_,reglist);
3186 // basic current block modification detection..
3187 // not looking back as that should be in mips cache already
3188 // (see Spyro2 title->attract mode)
3189 if(c&&start+i*4<addr_val&&addr_val<start+slen*4) {
3190 SysPrintf("write to %08x hits block %08x, pc=%08x\n",addr_val,start,start+i*4);
3191 assert(i_regs->regmap==regs[i].regmap); // not delay slot
3192 if(i_regs->regmap==regs[i].regmap) {
3193 load_all_consts(regs[i].regmap_entry,regs[i].wasdirty,i);
3194 wb_dirtys(regs[i].regmap_entry,regs[i].wasdirty);
3195 emit_movimm(start+i*4+4,0);
3196 emit_writeword(0,&pcaddr);
3197 emit_addimm(HOST_CCREG,2,HOST_CCREG);
3198 emit_far_call(ndrc_get_addr_ht);
3204 static void storelr_assemble(int i, const struct regstat *i_regs, int ccadj_)
3210 void *case1, *case23, *case3;
3211 void *done0, *done1, *done2;
3212 int memtarget=0,c=0;
3213 int agr=AGEN1+(i&1);
3214 int offset_reg = -1;
3215 u_int reglist=get_host_reglist(i_regs->regmap);
3216 tl=get_reg(i_regs->regmap,dops[i].rs2);
3217 s=get_reg(i_regs->regmap,dops[i].rs1);
3218 temp=get_reg(i_regs->regmap,agr);
3219 if(temp<0) temp=get_reg_temp(i_regs->regmap);
3222 c=(i_regs->isconst>>s)&1;
3224 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3230 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3231 if(!offset&&s!=temp) emit_mov(s,temp);
3237 if(!memtarget||!dops[i].rs1) {
3243 offset_reg = get_ro_reg(i_regs, 0);
3245 if (dops[i].opcode==0x2C||dops[i].opcode==0x2D) { // SDL/SDR
3249 emit_testimm(temp,2);
3252 emit_testimm(temp,1);
3256 if (dops[i].opcode == 0x2A) { // SWL
3257 // Write msb into least significant byte
3258 if (dops[i].rs2) emit_rorimm(tl, 24, tl);
3259 do_store_byte(temp, tl, offset_reg);
3260 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3262 else if (dops[i].opcode == 0x2E) { // SWR
3263 // Write entire word
3264 do_store_word(temp, 0, tl, offset_reg, 1);
3269 set_jump_target(case1, out);
3270 if (dops[i].opcode == 0x2A) { // SWL
3271 // Write two msb into two least significant bytes
3272 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
3273 do_store_hword(temp, -1, tl, offset_reg, 0);
3274 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
3276 else if (dops[i].opcode == 0x2E) { // SWR
3277 // Write 3 lsb into three most significant bytes
3278 do_store_byte(temp, tl, offset_reg);
3279 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3280 do_store_hword(temp, 1, tl, offset_reg, 0);
3281 if (dops[i].rs2) emit_rorimm(tl, 24, tl);
3286 set_jump_target(case23, out);
3287 emit_testimm(temp,1);
3291 if (dops[i].opcode==0x2A) { // SWL
3292 // Write 3 msb into three least significant bytes
3293 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3294 do_store_hword(temp, -2, tl, offset_reg, 1);
3295 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
3296 do_store_byte(temp, tl, offset_reg);
3297 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3299 else if (dops[i].opcode == 0x2E) { // SWR
3300 // Write two lsb into two most significant bytes
3301 do_store_hword(temp, 0, tl, offset_reg, 1);
3306 set_jump_target(case3, out);
3307 if (dops[i].opcode == 0x2A) { // SWL
3308 do_store_word(temp, -3, tl, offset_reg, 0);
3310 else if (dops[i].opcode == 0x2E) { // SWR
3311 do_store_byte(temp, tl, offset_reg);
3313 set_jump_target(done0, out);
3314 set_jump_target(done1, out);
3315 set_jump_target(done2, out);
3316 if (offset_reg == HOST_TEMPREG)
3317 host_tempreg_release();
3319 add_stub_r(STORELR_STUB,jaddr,out,i,temp,i_regs,ccadj_,reglist);
3320 if(!(i_regs->waswritten&(1<<dops[i].rs1)) && !HACK_ENABLED(NDHACK_NO_SMC_CHECK)) {
3321 #if defined(HOST_IMM8)
3322 int ir=get_reg(i_regs->regmap,INVCP);
3324 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3326 emit_cmpmem_indexedsr12_imm(invalid_code,temp,1);
3328 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3329 emit_callne(invalidate_addr_reg[temp]);
3333 add_stub(INVCODE_STUB,jaddr2,out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3338 static void cop0_assemble(int i, const struct regstat *i_regs, int ccadj_)
3340 if(dops[i].opcode2==0) // MFC0
3342 signed char t=get_reg(i_regs->regmap,dops[i].rt1);
3343 u_int copr=(source[i]>>11)&0x1f;
3344 //assert(t>=0); // Why does this happen? OOT is weird
3345 if(t>=0&&dops[i].rt1!=0) {
3346 emit_readword(®_cop0[copr],t);
3349 else if(dops[i].opcode2==4) // MTC0
3351 signed char s=get_reg(i_regs->regmap,dops[i].rs1);
3352 char copr=(source[i]>>11)&0x1f;
3354 wb_register(dops[i].rs1,i_regs->regmap,i_regs->dirty);
3355 if(copr==9||copr==11||copr==12||copr==13) {
3356 emit_readword(&last_count,HOST_TEMPREG);
3357 emit_loadreg(CCREG,HOST_CCREG); // TODO: do proper reg alloc
3358 emit_add(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
3359 emit_addimm(HOST_CCREG,ccadj_,HOST_CCREG);
3360 emit_writeword(HOST_CCREG,&Count);
3362 // What a mess. The status register (12) can enable interrupts,
3363 // so needs a special case to handle a pending interrupt.
3364 // The interrupt must be taken immediately, because a subsequent
3365 // instruction might disable interrupts again.
3366 if(copr==12||copr==13) {
3368 // burn cycles to cause cc_interrupt, which will
3369 // reschedule next_interupt. Relies on CCREG from above.
3370 assem_debug("MTC0 DS %d\n", copr);
3371 emit_writeword(HOST_CCREG,&last_count);
3372 emit_movimm(0,HOST_CCREG);
3373 emit_storereg(CCREG,HOST_CCREG);
3374 emit_loadreg(dops[i].rs1,1);
3375 emit_movimm(copr,0);
3376 emit_far_call(pcsx_mtc0_ds);
3377 emit_loadreg(dops[i].rs1,s);
3380 emit_movimm(start+i*4+4,HOST_TEMPREG);
3381 emit_writeword(HOST_TEMPREG,&pcaddr);
3382 emit_movimm(0,HOST_TEMPREG);
3383 emit_writeword(HOST_TEMPREG,&pending_exception);
3386 emit_loadreg(dops[i].rs1,1);
3389 emit_movimm(copr,0);
3390 emit_far_call(pcsx_mtc0);
3391 if(copr==9||copr==11||copr==12||copr==13) {
3392 emit_readword(&Count,HOST_CCREG);
3393 emit_readword(&next_interupt,HOST_TEMPREG);
3394 emit_addimm(HOST_CCREG,-ccadj_,HOST_CCREG);
3395 emit_sub(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
3396 emit_writeword(HOST_TEMPREG,&last_count);
3397 emit_storereg(CCREG,HOST_CCREG);
3399 if(copr==12||copr==13) {
3400 assert(!is_delayslot);
3401 emit_readword(&pending_exception,14);
3405 emit_readword(&pcaddr, 0);
3406 emit_addimm(HOST_CCREG,2,HOST_CCREG);
3407 emit_far_call(ndrc_get_addr_ht);
3409 set_jump_target(jaddr, out);
3411 emit_loadreg(dops[i].rs1,s);
3415 assert(dops[i].opcode2==0x10);
3416 //if((source[i]&0x3f)==0x10) // RFE
3418 emit_readword(&Status,0);
3419 emit_andimm(0,0x3c,1);
3420 emit_andimm(0,~0xf,0);
3421 emit_orrshr_imm(1,2,0);
3422 emit_writeword(0,&Status);
3427 static void cop1_unusable(int i, const struct regstat *i_regs)
3429 // XXX: should just just do the exception instead
3434 add_stub_r(FP_STUB,jaddr,out,i,0,i_regs,is_delayslot,0);
3438 static void cop1_assemble(int i, const struct regstat *i_regs)
3440 cop1_unusable(i, i_regs);
3443 static void c1ls_assemble(int i, const struct regstat *i_regs)
3445 cop1_unusable(i, i_regs);
3449 static void do_cop1stub(int n)
3452 assem_debug("do_cop1stub %x\n",start+stubs[n].a*4);
3453 set_jump_target(stubs[n].addr, out);
3455 // int rs=stubs[n].b;
3456 struct regstat *i_regs=(struct regstat *)stubs[n].c;
3459 load_all_consts(regs[i].regmap_entry,regs[i].wasdirty,i);
3460 //if(i_regs!=®s[i]) printf("oops: regs[i]=%x i_regs=%x",(int)®s[i],(int)i_regs);
3462 //else {printf("fp exception in delay slot\n");}
3463 wb_dirtys(i_regs->regmap_entry,i_regs->wasdirty);
3464 if(regs[i].regmap_entry[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
3465 emit_movimm(start+(i-ds)*4,EAX); // Get PC
3466 emit_addimm(HOST_CCREG,ccadj[i],HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
3467 emit_far_jump(ds?fp_exception_ds:fp_exception);
3470 static int cop2_is_stalling_op(int i, int *cycles)
3472 if (dops[i].opcode == 0x3a) { // SWC2
3476 if (dops[i].itype == COP2 && (dops[i].opcode2 == 0 || dops[i].opcode2 == 2)) { // MFC2/CFC2
3480 if (dops[i].itype == C2OP) {
3481 *cycles = gte_cycletab[source[i] & 0x3f];
3484 // ... what about MTC2/CTC2/LWC2?
3489 static void log_gte_stall(int stall, u_int cycle)
3491 if ((u_int)stall <= 44)
3492 printf("x stall %2d %u\n", stall, cycle + last_count);
3495 static void emit_log_gte_stall(int i, int stall, u_int reglist)
3499 emit_movimm(stall, 0);
3501 emit_mov(HOST_TEMPREG, 0);
3502 emit_addimm(HOST_CCREG, ccadj[i], 1);
3503 emit_far_call(log_gte_stall);
3504 restore_regs(reglist);
3508 static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist)
3510 int j = i, other_gte_op_cycles = -1, stall = -MAXBLOCK, cycles_passed;
3511 int rtmp = reglist_find_free(reglist);
3513 if (HACK_ENABLED(NDHACK_NO_STALLS))
3515 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) {
3516 // happens occasionally... cc evicted? Don't bother then
3517 //printf("no cc %08x\n", start + i*4);
3521 for (j = i - 1; j >= 0; j--) {
3522 //if (dops[j].is_ds) break;
3523 if (cop2_is_stalling_op(j, &other_gte_op_cycles) || dops[j].bt)
3525 if (j > 0 && ccadj[j - 1] > ccadj[j])
3530 cycles_passed = ccadj[i] - ccadj[j];
3531 if (other_gte_op_cycles >= 0)
3532 stall = other_gte_op_cycles - cycles_passed;
3533 else if (cycles_passed >= 44)
3534 stall = 0; // can't stall
3535 if (stall == -MAXBLOCK && rtmp >= 0) {
3536 // unknown stall, do the expensive runtime check
3537 assem_debug("; cop2_do_stall_check\n");
3540 emit_movimm(gte_cycletab[op], 0);
3541 emit_addimm(HOST_CCREG, ccadj[i], 1);
3542 emit_far_call(call_gteStall);
3543 restore_regs(reglist);
3545 host_tempreg_acquire();
3546 emit_readword(&psxRegs.gteBusyCycle, rtmp);
3547 emit_addimm(rtmp, -ccadj[i], rtmp);
3548 emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG);
3549 emit_cmpimm(HOST_TEMPREG, 44);
3550 emit_cmovb_reg(rtmp, HOST_CCREG);
3551 //emit_log_gte_stall(i, 0, reglist);
3552 host_tempreg_release();
3555 else if (stall > 0) {
3556 //emit_log_gte_stall(i, stall, reglist);
3557 emit_addimm(HOST_CCREG, stall, HOST_CCREG);
3560 // save gteBusyCycle, if needed
3561 if (gte_cycletab[op] == 0)
3563 other_gte_op_cycles = -1;
3564 for (j = i + 1; j < slen; j++) {
3565 if (cop2_is_stalling_op(j, &other_gte_op_cycles))
3567 if (dops[j].is_jump) {
3569 if (j + 1 < slen && cop2_is_stalling_op(j + 1, &other_gte_op_cycles))
3574 if (other_gte_op_cycles >= 0)
3575 // will handle stall when assembling that op
3577 cycles_passed = ccadj[min(j, slen -1)] - ccadj[i];
3578 if (cycles_passed >= 44)
3580 assem_debug("; save gteBusyCycle\n");
3581 host_tempreg_acquire();
3583 emit_readword(&last_count, HOST_TEMPREG);
3584 emit_add(HOST_TEMPREG, HOST_CCREG, HOST_TEMPREG);
3585 emit_addimm(HOST_TEMPREG, ccadj[i], HOST_TEMPREG);
3586 emit_addimm(HOST_TEMPREG, gte_cycletab[op]), HOST_TEMPREG);
3587 emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle);
3589 emit_addimm(HOST_CCREG, ccadj[i] + gte_cycletab[op], HOST_TEMPREG);
3590 emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle);
3592 host_tempreg_release();
3595 static int is_mflohi(int i)
3597 return (dops[i].itype == MOV && (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG));
3600 static int check_multdiv(int i, int *cycles)
3602 if (dops[i].itype != MULTDIV)
3604 if (dops[i].opcode2 == 0x18 || dops[i].opcode2 == 0x19) // MULT(U)
3605 *cycles = 11; // approx from 7 11 14
3611 static void multdiv_prepare_stall(int i, const struct regstat *i_regs, int ccadj_)
3613 int j, found = 0, c = 0;
3614 if (HACK_ENABLED(NDHACK_NO_STALLS))
3616 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) {
3617 // happens occasionally... cc evicted? Don't bother then
3620 for (j = i + 1; j < slen; j++) {
3623 if ((found = is_mflohi(j)))
3625 if (dops[j].is_jump) {
3627 if (j + 1 < slen && (found = is_mflohi(j + 1)))
3633 // handle all in multdiv_do_stall()
3635 check_multdiv(i, &c);
3637 assem_debug("; muldiv prepare stall %d\n", c);
3638 host_tempreg_acquire();
3639 emit_addimm(HOST_CCREG, ccadj_ + c, HOST_TEMPREG);
3640 emit_writeword(HOST_TEMPREG, &psxRegs.muldivBusyCycle);
3641 host_tempreg_release();
3644 static void multdiv_do_stall(int i, const struct regstat *i_regs)
3646 int j, known_cycles = 0;
3647 u_int reglist = get_host_reglist(i_regs->regmap);
3648 int rtmp = get_reg_temp(i_regs->regmap);
3650 rtmp = reglist_find_free(reglist);
3651 if (HACK_ENABLED(NDHACK_NO_STALLS))
3653 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG || rtmp < 0) {
3654 // happens occasionally... cc evicted? Don't bother then
3655 //printf("no cc/rtmp %08x\n", start + i*4);
3659 for (j = i - 1; j >= 0; j--) {
3660 if (dops[j].is_ds) break;
3661 if (check_multdiv(j, &known_cycles))
3664 // already handled by this op
3666 if (dops[j].bt || (j > 0 && ccadj[j - 1] > ccadj[j]))
3671 if (known_cycles > 0) {
3672 known_cycles -= ccadj[i] - ccadj[j];
3673 assem_debug("; muldiv stall resolved %d\n", known_cycles);
3674 if (known_cycles > 0)
3675 emit_addimm(HOST_CCREG, known_cycles, HOST_CCREG);
3678 assem_debug("; muldiv stall unresolved\n");
3679 host_tempreg_acquire();
3680 emit_readword(&psxRegs.muldivBusyCycle, rtmp);
3681 emit_addimm(rtmp, -ccadj[i], rtmp);
3682 emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG);
3683 emit_cmpimm(HOST_TEMPREG, 37);
3684 emit_cmovb_reg(rtmp, HOST_CCREG);
3685 //emit_log_gte_stall(i, 0, reglist);
3686 host_tempreg_release();
3689 static void cop2_get_dreg(u_int copr,signed char tl,signed char temp)
3699 emit_readword(®_cop2d[copr],tl);
3700 emit_signextend16(tl,tl);
3701 emit_writeword(tl,®_cop2d[copr]); // hmh
3708 emit_readword(®_cop2d[copr],tl);
3709 emit_andimm(tl,0xffff,tl);
3710 emit_writeword(tl,®_cop2d[copr]);
3713 emit_readword(®_cop2d[14],tl); // SXY2
3714 emit_writeword(tl,®_cop2d[copr]);
3718 c2op_mfc2_29_assemble(tl,temp);
3721 emit_readword(®_cop2d[copr],tl);
3726 static void cop2_put_dreg(u_int copr,signed char sl,signed char temp)
3730 emit_readword(®_cop2d[13],temp); // SXY1
3731 emit_writeword(sl,®_cop2d[copr]);
3732 emit_writeword(temp,®_cop2d[12]); // SXY0
3733 emit_readword(®_cop2d[14],temp); // SXY2
3734 emit_writeword(sl,®_cop2d[14]);
3735 emit_writeword(temp,®_cop2d[13]); // SXY1
3738 emit_andimm(sl,0x001f,temp);
3739 emit_shlimm(temp,7,temp);
3740 emit_writeword(temp,®_cop2d[9]);
3741 emit_andimm(sl,0x03e0,temp);
3742 emit_shlimm(temp,2,temp);
3743 emit_writeword(temp,®_cop2d[10]);
3744 emit_andimm(sl,0x7c00,temp);
3745 emit_shrimm(temp,3,temp);
3746 emit_writeword(temp,®_cop2d[11]);
3747 emit_writeword(sl,®_cop2d[28]);
3750 emit_xorsar_imm(sl,sl,31,temp);
3751 #if defined(HAVE_ARMV5) || defined(__aarch64__)
3752 emit_clz(temp,temp);
3754 emit_movs(temp,HOST_TEMPREG);
3755 emit_movimm(0,temp);
3756 emit_jeq((int)out+4*4);
3757 emit_addpl_imm(temp,1,temp);
3758 emit_lslpls_imm(HOST_TEMPREG,1,HOST_TEMPREG);
3759 emit_jns((int)out-2*4);
3761 emit_writeword(sl,®_cop2d[30]);
3762 emit_writeword(temp,®_cop2d[31]);
3767 emit_writeword(sl,®_cop2d[copr]);
3772 static void c2ls_assemble(int i, const struct regstat *i_regs, int ccadj_)
3777 int memtarget=0,c=0;
3779 enum stub_type type;
3780 int agr=AGEN1+(i&1);
3781 int offset_reg = -1;
3782 int fastio_reg_override = -1;
3783 u_int reglist=get_host_reglist(i_regs->regmap);
3784 u_int copr=(source[i]>>16)&0x1f;
3785 s=get_reg(i_regs->regmap,dops[i].rs1);
3786 tl=get_reg(i_regs->regmap,FTEMP);
3788 assert(dops[i].rs1>0);
3791 if(i_regs->regmap[HOST_CCREG]==CCREG)
3792 reglist&=~(1<<HOST_CCREG);
3795 if (dops[i].opcode==0x3a) { // SWC2
3796 ar=get_reg(i_regs->regmap,agr);
3797 if(ar<0) ar=get_reg_temp(i_regs->regmap);
3802 if(s>=0) c=(i_regs->wasconst>>s)&1;
3803 memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
3804 if (!offset&&!c&&s>=0) ar=s;
3807 cop2_do_stall_check(0, i, i_regs, reglist);
3809 if (dops[i].opcode==0x3a) { // SWC2
3810 cop2_get_dreg(copr,tl,-1);
3818 emit_jmp(0); // inline_readstub/inline_writestub?
3822 jaddr2 = emit_fastpath_cmp_jump(i, i_regs, ar,
3823 &offset_reg, &fastio_reg_override);
3825 else if (ram_offset && memtarget) {
3826 offset_reg = get_ro_reg(i_regs, 0);
3828 switch (dops[i].opcode) {
3829 case 0x32: { // LWC2
3831 if (fastio_reg_override >= 0)
3832 a = fastio_reg_override;
3833 do_load_word(a, tl, offset_reg);
3836 case 0x3a: { // SWC2
3837 #ifdef DESTRUCTIVE_SHIFT
3838 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3841 if (fastio_reg_override >= 0)
3842 a = fastio_reg_override;
3843 do_store_word(a, 0, tl, offset_reg, 1);
3850 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
3851 host_tempreg_release();
3853 add_stub_r(type,jaddr2,out,i,ar,i_regs,ccadj_,reglist);
3854 if(dops[i].opcode==0x3a) // SWC2
3855 if(!(i_regs->waswritten&(1<<dops[i].rs1)) && !HACK_ENABLED(NDHACK_NO_SMC_CHECK)) {
3856 #if defined(HOST_IMM8)
3857 int ir=get_reg(i_regs->regmap,INVCP);
3859 emit_cmpmem_indexedsr12_reg(ir,ar,1);
3861 emit_cmpmem_indexedsr12_imm(invalid_code,ar,1);
3863 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3864 emit_callne(invalidate_addr_reg[ar]);
3868 add_stub(INVCODE_STUB,jaddr3,out,reglist|(1<<HOST_CCREG),ar,0,0,0);
3871 if (dops[i].opcode==0x32) { // LWC2
3872 host_tempreg_acquire();
3873 cop2_put_dreg(copr,tl,HOST_TEMPREG);
3874 host_tempreg_release();
3878 static void cop2_assemble(int i, const struct regstat *i_regs)
3880 u_int copr = (source[i]>>11) & 0x1f;
3881 signed char temp = get_reg_temp(i_regs->regmap);
3883 if (!HACK_ENABLED(NDHACK_NO_STALLS)) {
3884 u_int reglist = reglist_exclude(get_host_reglist(i_regs->regmap), temp, -1);
3885 if (dops[i].opcode2 == 0 || dops[i].opcode2 == 2) { // MFC2/CFC2
3886 signed char tl = get_reg(i_regs->regmap, dops[i].rt1);
3887 reglist = reglist_exclude(reglist, tl, -1);
3889 cop2_do_stall_check(0, i, i_regs, reglist);
3891 if (dops[i].opcode2==0) { // MFC2
3892 signed char tl=get_reg(i_regs->regmap,dops[i].rt1);
3893 if(tl>=0&&dops[i].rt1!=0)
3894 cop2_get_dreg(copr,tl,temp);
3896 else if (dops[i].opcode2==4) { // MTC2
3897 signed char sl=get_reg(i_regs->regmap,dops[i].rs1);
3898 cop2_put_dreg(copr,sl,temp);
3900 else if (dops[i].opcode2==2) // CFC2
3902 signed char tl=get_reg(i_regs->regmap,dops[i].rt1);
3903 if(tl>=0&&dops[i].rt1!=0)
3904 emit_readword(®_cop2c[copr],tl);
3906 else if (dops[i].opcode2==6) // CTC2
3908 signed char sl=get_reg(i_regs->regmap,dops[i].rs1);
3917 emit_signextend16(sl,temp);
3920 c2op_ctc2_31_assemble(sl,temp);
3926 emit_writeword(temp,®_cop2c[copr]);
3931 static void do_unalignedwritestub(int n)
3933 assem_debug("do_unalignedwritestub %x\n",start+stubs[n].a*4);
3935 set_jump_target(stubs[n].addr, out);
3938 struct regstat *i_regs=(struct regstat *)stubs[n].c;
3939 int addr=stubs[n].b;
3940 u_int reglist=stubs[n].e;
3941 signed char *i_regmap=i_regs->regmap;
3942 int temp2=get_reg(i_regmap,FTEMP);
3944 rt=get_reg(i_regmap,dops[i].rs2);
3947 assert(dops[i].opcode==0x2a||dops[i].opcode==0x2e); // SWL/SWR only implemented
3949 reglist&=~(1<<temp2);
3951 // don't bother with it and call write handler
3954 int cc=get_reg(i_regmap,CCREG);
3956 emit_loadreg(CCREG,2);
3957 emit_addimm(cc<0?2:cc,(int)stubs[n].d+1,2);
3958 emit_far_call((dops[i].opcode==0x2a?jump_handle_swl:jump_handle_swr));
3959 emit_addimm(0,-((int)stubs[n].d+1),cc<0?2:cc);
3961 emit_storereg(CCREG,2);
3962 restore_regs(reglist);
3963 emit_jmp(stubs[n].retaddr); // return address
3966 #ifndef multdiv_assemble
3967 void multdiv_assemble(int i,struct regstat *i_regs)
3969 printf("Need multdiv_assemble for this architecture.\n");
3974 static void mov_assemble(int i, const struct regstat *i_regs)
3976 //if(dops[i].opcode2==0x10||dops[i].opcode2==0x12) { // MFHI/MFLO
3977 //if(dops[i].opcode2==0x11||dops[i].opcode2==0x13) { // MTHI/MTLO
3980 tl=get_reg(i_regs->regmap,dops[i].rt1);
3983 sl=get_reg(i_regs->regmap,dops[i].rs1);
3984 if(sl>=0) emit_mov(sl,tl);
3985 else emit_loadreg(dops[i].rs1,tl);
3988 if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) // MFHI/MFLO
3989 multdiv_do_stall(i, i_regs);
3992 // call interpreter, exception handler, things that change pc/regs/cycles ...
3993 static void call_c_cpu_handler(int i, const struct regstat *i_regs, int ccadj_, u_int pc, void *func)
3995 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3996 assert(ccreg==HOST_CCREG);
3997 assert(!is_delayslot);
4000 emit_movimm(pc,3); // Get PC
4001 emit_readword(&last_count,2);
4002 emit_writeword(3,&psxRegs.pc);
4003 emit_addimm(HOST_CCREG,ccadj_,HOST_CCREG);
4004 emit_add(2,HOST_CCREG,2);
4005 emit_writeword(2,&psxRegs.cycle);
4006 emit_far_call(func);
4007 emit_far_jump(jump_to_new_pc);
4010 static void syscall_assemble(int i, const struct regstat *i_regs, int ccadj_)
4012 // 'break' tends to be littered around to catch things like
4013 // division by 0 and is almost never executed, so don't emit much code here
4014 void *func = (dops[i].opcode2 == 0x0C)
4015 ? (is_delayslot ? jump_syscall_ds : jump_syscall)
4016 : (is_delayslot ? jump_break_ds : jump_break);
4017 assert(get_reg(i_regs->regmap, CCREG) == HOST_CCREG);
4018 emit_movimm(start + i*4, 2); // pc
4019 emit_addimm(HOST_CCREG, ccadj_ + CLOCK_ADJUST(1), HOST_CCREG);
4020 emit_far_jump(func);
4023 static void hlecall_assemble(int i, const struct regstat *i_regs, int ccadj_)
4025 void *hlefunc = psxNULL;
4026 uint32_t hleCode = source[i] & 0x03ffffff;
4027 if (hleCode < ARRAY_SIZE(psxHLEt))
4028 hlefunc = psxHLEt[hleCode];
4030 call_c_cpu_handler(i, i_regs, ccadj_, start + i*4+4, hlefunc);
4033 static void intcall_assemble(int i, const struct regstat *i_regs, int ccadj_)
4035 call_c_cpu_handler(i, i_regs, ccadj_, start + i*4, execI);
4038 static void speculate_mov(int rs,int rt)
4041 smrv_strong_next|=1<<rt;
4046 static void speculate_mov_weak(int rs,int rt)
4049 smrv_weak_next|=1<<rt;
4054 static void speculate_register_values(int i)
4057 memcpy(smrv,psxRegs.GPR.r,sizeof(smrv));
4058 // gp,sp are likely to stay the same throughout the block
4059 smrv_strong_next=(1<<28)|(1<<29)|(1<<30);
4060 smrv_weak_next=~smrv_strong_next;
4061 //printf(" llr %08x\n", smrv[4]);
4063 smrv_strong=smrv_strong_next;
4064 smrv_weak=smrv_weak_next;
4065 switch(dops[i].itype) {
4067 if ((smrv_strong>>dops[i].rs1)&1) speculate_mov(dops[i].rs1,dops[i].rt1);
4068 else if((smrv_strong>>dops[i].rs2)&1) speculate_mov(dops[i].rs2,dops[i].rt1);
4069 else if((smrv_weak>>dops[i].rs1)&1) speculate_mov_weak(dops[i].rs1,dops[i].rt1);
4070 else if((smrv_weak>>dops[i].rs2)&1) speculate_mov_weak(dops[i].rs2,dops[i].rt1);
4072 smrv_strong_next&=~(1<<dops[i].rt1);
4073 smrv_weak_next&=~(1<<dops[i].rt1);
4077 smrv_strong_next&=~(1<<dops[i].rt1);
4078 smrv_weak_next&=~(1<<dops[i].rt1);
4081 if(dops[i].rt1&&is_const(®s[i],dops[i].rt1)) {
4082 int value,hr=get_reg(regs[i].regmap,dops[i].rt1);
4084 if(get_final_value(hr,i,&value))
4085 smrv[dops[i].rt1]=value;
4086 else smrv[dops[i].rt1]=constmap[i][hr];
4087 smrv_strong_next|=1<<dops[i].rt1;
4091 if ((smrv_strong>>dops[i].rs1)&1) speculate_mov(dops[i].rs1,dops[i].rt1);
4092 else if((smrv_weak>>dops[i].rs1)&1) speculate_mov_weak(dops[i].rs1,dops[i].rt1);
4096 if(start<0x2000&&(dops[i].rt1==26||(smrv[dops[i].rt1]>>24)==0xa0)) {
4097 // special case for BIOS
4098 smrv[dops[i].rt1]=0xa0000000;
4099 smrv_strong_next|=1<<dops[i].rt1;
4106 smrv_strong_next&=~(1<<dops[i].rt1);
4107 smrv_weak_next&=~(1<<dops[i].rt1);
4111 if(dops[i].opcode2==0||dops[i].opcode2==2) { // MFC/CFC
4112 smrv_strong_next&=~(1<<dops[i].rt1);
4113 smrv_weak_next&=~(1<<dops[i].rt1);
4117 if (dops[i].opcode==0x32) { // LWC2
4118 smrv_strong_next&=~(1<<dops[i].rt1);
4119 smrv_weak_next&=~(1<<dops[i].rt1);
4125 printf("x %08x %08x %d %d c %08x %08x\n",smrv[r],start+i*4,
4126 ((smrv_strong>>r)&1),(smrv_weak>>r)&1,regs[i].isconst,regs[i].wasconst);
4130 static void ujump_assemble(int i, const struct regstat *i_regs);
4131 static void rjump_assemble(int i, const struct regstat *i_regs);
4132 static void cjump_assemble(int i, const struct regstat *i_regs);
4133 static void sjump_assemble(int i, const struct regstat *i_regs);
4135 static int assemble(int i, const struct regstat *i_regs, int ccadj_)
4138 switch (dops[i].itype) {
4140 alu_assemble(i, i_regs);
4143 imm16_assemble(i, i_regs);
4146 shift_assemble(i, i_regs);
4149 shiftimm_assemble(i, i_regs);
4152 load_assemble(i, i_regs, ccadj_);
4155 loadlr_assemble(i, i_regs, ccadj_);
4158 store_assemble(i, i_regs, ccadj_);
4161 storelr_assemble(i, i_regs, ccadj_);
4164 cop0_assemble(i, i_regs, ccadj_);
4167 cop1_assemble(i, i_regs);
4170 c1ls_assemble(i, i_regs);
4173 cop2_assemble(i, i_regs);
4176 c2ls_assemble(i, i_regs, ccadj_);
4179 c2op_assemble(i, i_regs);
4182 multdiv_assemble(i, i_regs);
4183 multdiv_prepare_stall(i, i_regs, ccadj_);
4186 mov_assemble(i, i_regs);
4189 syscall_assemble(i, i_regs, ccadj_);
4192 hlecall_assemble(i, i_regs, ccadj_);
4195 intcall_assemble(i, i_regs, ccadj_);
4198 ujump_assemble(i, i_regs);
4202 rjump_assemble(i, i_regs);
4206 cjump_assemble(i, i_regs);
4210 sjump_assemble(i, i_regs);
4216 // not handled, just skip
4224 static void ds_assemble(int i, const struct regstat *i_regs)
4226 speculate_register_values(i);
4228 switch (dops[i].itype) {
4236 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
4239 assemble(i, i_regs, ccadj[i]);
4244 // Is the branch target a valid internal jump?
4245 static int internal_branch(int addr)
4247 if(addr&1) return 0; // Indirect (register) jump
4248 if(addr>=start && addr<start+slen*4-4)
4255 static void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t u)
4258 for(hr=0;hr<HOST_REGS;hr++) {
4259 if(hr!=EXCLUDE_REG) {
4260 if(pre[hr]!=entry[hr]) {
4263 if(get_reg(entry,pre[hr])<0) {
4265 if(!((u>>pre[hr])&1))
4266 emit_storereg(pre[hr],hr);
4273 // Move from one register to another (no writeback)
4274 for(hr=0;hr<HOST_REGS;hr++) {
4275 if(hr!=EXCLUDE_REG) {
4276 if(pre[hr]!=entry[hr]) {
4277 if(pre[hr]>=0&&pre[hr]<TEMPREG) {
4279 if((nr=get_reg(entry,pre[hr]))>=0) {
4288 // Load the specified registers
4289 // This only loads the registers given as arguments because
4290 // we don't want to load things that will be overwritten
4291 static inline void load_reg(signed char entry[], signed char regmap[], int rs)
4293 int hr = get_reg(regmap, rs);
4294 if (hr >= 0 && entry[hr] != regmap[hr])
4295 emit_loadreg(regmap[hr], hr);
4298 static void load_regs(signed char entry[], signed char regmap[], int rs1, int rs2)
4300 load_reg(entry, regmap, rs1);
4302 load_reg(entry, regmap, rs2);
4305 // Load registers prior to the start of a loop
4306 // so that they are not loaded within the loop
4307 static void loop_preload(signed char pre[],signed char entry[])
4310 for (hr = 0; hr < HOST_REGS; hr++) {
4312 if (r >= 0 && pre[hr] != r && get_reg(pre, r) < 0) {
4313 assem_debug("loop preload:\n");
4315 emit_loadreg(r, hr);
4320 // Generate address for load/store instruction
4321 // goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
4322 static void address_generation(int i, const struct regstat *i_regs, signed char entry[])
4324 if (dops[i].is_load || dops[i].is_store) {
4326 int agr=AGEN1+(i&1);
4327 if(dops[i].itype==LOAD) {
4328 ra=get_reg(i_regs->regmap,dops[i].rt1);
4329 if(ra<0) ra=get_reg_temp(i_regs->regmap);
4332 if(dops[i].itype==LOADLR) {
4333 ra=get_reg(i_regs->regmap,FTEMP);
4335 if(dops[i].itype==STORE||dops[i].itype==STORELR) {
4336 ra=get_reg(i_regs->regmap,agr);
4337 if(ra<0) ra=get_reg_temp(i_regs->regmap);
4339 if(dops[i].itype==C2LS) {
4340 if ((dops[i].opcode&0x3b)==0x31||(dops[i].opcode&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
4341 ra=get_reg(i_regs->regmap,FTEMP);
4342 else { // SWC1/SDC1/SWC2/SDC2
4343 ra=get_reg(i_regs->regmap,agr);
4344 if(ra<0) ra=get_reg_temp(i_regs->regmap);
4347 int rs=get_reg(i_regs->regmap,dops[i].rs1);
4350 int c=(i_regs->wasconst>>rs)&1;
4351 if(dops[i].rs1==0) {
4352 // Using r0 as a base address
4353 if(!entry||entry[ra]!=agr) {
4354 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
4355 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4356 }else if (dops[i].opcode==0x1a||dops[i].opcode==0x1b) {
4357 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4359 emit_movimm(offset,ra);
4361 } // else did it in the previous cycle
4364 if(!entry||entry[ra]!=dops[i].rs1)
4365 emit_loadreg(dops[i].rs1,ra);
4366 //if(!entry||entry[ra]!=dops[i].rs1)
4367 // printf("poor load scheduling!\n");
4370 if(dops[i].rs1!=dops[i].rt1||dops[i].itype!=LOAD) {
4371 if(!entry||entry[ra]!=agr) {
4372 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
4373 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4374 }else if (dops[i].opcode==0x1a||dops[i].opcode==0x1b) {
4375 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4377 emit_movimm(constmap[i][rs]+offset,ra);
4378 regs[i].loadedconst|=1<<ra;
4380 } // else did it in the previous cycle
4381 } // else load_consts already did it
4383 if(offset&&!c&&dops[i].rs1) {
4385 emit_addimm(rs,offset,ra);
4387 emit_addimm(ra,offset,ra);
4392 // Preload constants for next instruction
4393 if (dops[i+1].is_load || dops[i+1].is_store) {
4396 agr=AGEN1+((i+1)&1);
4397 ra=get_reg(i_regs->regmap,agr);
4399 int rs=get_reg(regs[i+1].regmap,dops[i+1].rs1);
4400 int offset=imm[i+1];
4401 int c=(regs[i+1].wasconst>>rs)&1;
4402 if(c&&(dops[i+1].rs1!=dops[i+1].rt1||dops[i+1].itype!=LOAD)) {
4403 if (dops[i+1].opcode==0x22||dops[i+1].opcode==0x26) {
4404 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4405 }else if (dops[i+1].opcode==0x1a||dops[i+1].opcode==0x1b) {
4406 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4408 emit_movimm(constmap[i+1][rs]+offset,ra);
4409 regs[i+1].loadedconst|=1<<ra;
4412 else if(dops[i+1].rs1==0) {
4413 // Using r0 as a base address
4414 if (dops[i+1].opcode==0x22||dops[i+1].opcode==0x26) {
4415 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4416 }else if (dops[i+1].opcode==0x1a||dops[i+1].opcode==0x1b) {
4417 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4419 emit_movimm(offset,ra);
4426 static int get_final_value(int hr, int i, int *value)
4428 int reg=regs[i].regmap[hr];
4430 if(regs[i+1].regmap[hr]!=reg) break;
4431 if(!((regs[i+1].isconst>>hr)&1)) break;
4432 if(dops[i+1].bt) break;
4436 if (dops[i].is_jump) {
4437 *value=constmap[i][hr];
4441 if (dops[i+1].is_jump) {
4442 // Load in delay slot, out-of-order execution
4443 if(dops[i+2].itype==LOAD&&dops[i+2].rs1==reg&&dops[i+2].rt1==reg&&((regs[i+1].wasconst>>hr)&1))
4445 // Precompute load address
4446 *value=constmap[i][hr]+imm[i+2];
4450 if(dops[i+1].itype==LOAD&&dops[i+1].rs1==reg&&dops[i+1].rt1==reg)
4452 // Precompute load address
4453 *value=constmap[i][hr]+imm[i+1];
4454 //printf("c=%x imm=%lx\n",(long)constmap[i][hr],imm[i+1]);
4459 *value=constmap[i][hr];
4460 //printf("c=%lx\n",(long)constmap[i][hr]);
4461 if(i==slen-1) return 1;
4463 return !((unneeded_reg[i+1]>>reg)&1);
4466 // Load registers with known constants
4467 static void load_consts(signed char pre[],signed char regmap[],int i)
4470 // propagate loaded constant flags
4471 if(i==0||dops[i].bt)
4472 regs[i].loadedconst=0;
4474 for(hr=0;hr<HOST_REGS;hr++) {
4475 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((regs[i-1].isconst>>hr)&1)&&pre[hr]==regmap[hr]
4476 &®map[hr]==regs[i-1].regmap[hr]&&((regs[i-1].loadedconst>>hr)&1))
4478 regs[i].loadedconst|=1<<hr;
4483 for(hr=0;hr<HOST_REGS;hr++) {
4484 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4485 //if(entry[hr]!=regmap[hr]) {
4486 if(!((regs[i].loadedconst>>hr)&1)) {
4487 assert(regmap[hr]<64);
4488 if(((regs[i].isconst>>hr)&1)&®map[hr]>0) {
4489 int value,similar=0;
4490 if(get_final_value(hr,i,&value)) {
4491 // see if some other register has similar value
4492 for(hr2=0;hr2<HOST_REGS;hr2++) {
4493 if(hr2!=EXCLUDE_REG&&((regs[i].loadedconst>>hr2)&1)) {
4494 if(is_similar_value(value,constmap[i][hr2])) {
4502 if(get_final_value(hr2,i,&value2)) // is this needed?
4503 emit_movimm_from(value2,hr2,value,hr);
4505 emit_movimm(value,hr);
4511 emit_movimm(value,hr);
4514 regs[i].loadedconst|=1<<hr;
4521 static void load_all_consts(const signed char regmap[], u_int dirty, int i)
4525 for(hr=0;hr<HOST_REGS;hr++) {
4526 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) {
4527 assert(regmap[hr] < 64);
4528 if(((regs[i].isconst>>hr)&1)&®map[hr]>0) {
4529 int value=constmap[i][hr];
4534 emit_movimm(value,hr);
4541 // Write out all dirty registers (except cycle count)
4542 static void wb_dirtys(const signed char i_regmap[], uint64_t i_dirty)
4545 for(hr=0;hr<HOST_REGS;hr++) {
4546 if(hr!=EXCLUDE_REG) {
4547 if(i_regmap[hr]>0) {
4548 if(i_regmap[hr]!=CCREG) {
4549 if((i_dirty>>hr)&1) {
4550 assert(i_regmap[hr]<64);
4551 emit_storereg(i_regmap[hr],hr);
4559 // Write out dirty registers that we need to reload (pair with load_needed_regs)
4560 // This writes the registers not written by store_regs_bt
4561 static void wb_needed_dirtys(const signed char i_regmap[], uint64_t i_dirty, int addr)
4564 int t=(addr-start)>>2;
4565 for(hr=0;hr<HOST_REGS;hr++) {
4566 if(hr!=EXCLUDE_REG) {
4567 if(i_regmap[hr]>0) {
4568 if(i_regmap[hr]!=CCREG) {
4569 if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1)) {
4570 if((i_dirty>>hr)&1) {
4571 assert(i_regmap[hr]<64);
4572 emit_storereg(i_regmap[hr],hr);
4581 // Load all registers (except cycle count)
4582 static void load_all_regs(const signed char i_regmap[])
4585 for(hr=0;hr<HOST_REGS;hr++) {
4586 if(hr!=EXCLUDE_REG) {
4587 if(i_regmap[hr]==0) {
4591 if(i_regmap[hr]>0 && i_regmap[hr]<TEMPREG && i_regmap[hr]!=CCREG)
4593 emit_loadreg(i_regmap[hr],hr);
4599 // Load all current registers also needed by next instruction
4600 static void load_needed_regs(const signed char i_regmap[], const signed char next_regmap[])
4603 for(hr=0;hr<HOST_REGS;hr++) {
4604 if(hr!=EXCLUDE_REG) {
4605 if(get_reg(next_regmap,i_regmap[hr])>=0) {
4606 if(i_regmap[hr]==0) {
4610 if(i_regmap[hr]>0 && i_regmap[hr]<TEMPREG && i_regmap[hr]!=CCREG)
4612 emit_loadreg(i_regmap[hr],hr);
4619 // Load all regs, storing cycle count if necessary
4620 static void load_regs_entry(int t)
4623 if(dops[t].is_ds) emit_addimm(HOST_CCREG,CLOCK_ADJUST(1),HOST_CCREG);
4624 else if(ccadj[t]) emit_addimm(HOST_CCREG,-ccadj[t],HOST_CCREG);
4625 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4626 emit_storereg(CCREG,HOST_CCREG);
4629 for(hr=0;hr<HOST_REGS;hr++) {
4630 if(regs[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) {
4631 if(regs[t].regmap_entry[hr]==0) {
4634 else if(regs[t].regmap_entry[hr]!=CCREG)
4636 emit_loadreg(regs[t].regmap_entry[hr],hr);
4642 // Store dirty registers prior to branch
4643 static void store_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
4645 if(internal_branch(addr))
4647 int t=(addr-start)>>2;
4649 for(hr=0;hr<HOST_REGS;hr++) {
4650 if(hr!=EXCLUDE_REG) {
4651 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4652 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1)) {
4653 if((i_dirty>>hr)&1) {
4654 assert(i_regmap[hr]<64);
4655 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4656 emit_storereg(i_regmap[hr],hr);
4665 // Branch out of this block, write out all dirty regs
4666 wb_dirtys(i_regmap,i_dirty);
4670 // Load all needed registers for branch target
4671 static void load_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
4673 //if(addr>=start && addr<(start+slen*4))
4674 if(internal_branch(addr))
4676 int t=(addr-start)>>2;
4678 // Store the cycle count before loading something else
4679 if(i_regmap[HOST_CCREG]!=CCREG) {
4680 assert(i_regmap[HOST_CCREG]==-1);
4682 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4683 emit_storereg(CCREG,HOST_CCREG);
4686 for(hr=0;hr<HOST_REGS;hr++) {
4687 if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) {
4688 if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4689 if(regs[t].regmap_entry[hr]==0) {
4692 else if(regs[t].regmap_entry[hr]!=CCREG)
4694 emit_loadreg(regs[t].regmap_entry[hr],hr);
4702 static int match_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
4704 if(addr>=start && addr<start+slen*4-4)
4706 int t=(addr-start)>>2;
4708 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4709 for(hr=0;hr<HOST_REGS;hr++)
4713 if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4715 if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
4722 if(i_regmap[hr]<TEMPREG)
4724 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4727 else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
4733 else // Same register but is it 32-bit or dirty?
4736 if(!((regs[t].dirty>>hr)&1))
4740 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4742 //printf("%x: dirty no match\n",addr);
4750 // Delay slots are not valid branch targets
4751 //if(t>0&&(dops[t-1].is_jump) return 0;
4752 // Delay slots require additional processing, so do not match
4753 if(dops[t].is_ds) return 0;
4758 for(hr=0;hr<HOST_REGS;hr++)
4764 if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4779 static void drc_dbg_emit_do_cmp(int i, int ccadj_)
4781 extern void do_insn_cmp();
4783 u_int hr, reglist = get_host_reglist(regs[i].regmap);
4785 assem_debug("//do_insn_cmp %08x\n", start+i*4);
4787 // write out changed consts to match the interpreter
4788 if (i > 0 && !dops[i].bt) {
4789 for (hr = 0; hr < HOST_REGS; hr++) {
4790 int reg = regs[i].regmap_entry[hr]; // regs[i-1].regmap[hr];
4791 if (hr == EXCLUDE_REG || reg < 0)
4793 if (!((regs[i-1].isconst >> hr) & 1))
4795 if (i > 1 && reg == regs[i-2].regmap[hr] && constmap[i-1][hr] == constmap[i-2][hr])
4797 emit_movimm(constmap[i-1][hr],0);
4798 emit_storereg(reg, 0);
4801 emit_movimm(start+i*4,0);
4802 emit_writeword(0,&pcaddr);
4803 int cc = get_reg(regs[i].regmap_entry, CCREG);
4805 emit_loadreg(CCREG, cc = 0);
4806 emit_addimm(cc, ccadj_, 0);
4807 emit_writeword(0, &psxRegs.cycle);
4808 emit_far_call(do_insn_cmp);
4809 //emit_readword(&cycle,0);
4810 //emit_addimm(0,2,0);
4811 //emit_writeword(0,&cycle);
4813 restore_regs(reglist);
4814 assem_debug("\\\\do_insn_cmp\n");
4817 #define drc_dbg_emit_do_cmp(x,y)
4820 // Used when a branch jumps into the delay slot of another branch
4821 static void ds_assemble_entry(int i)
4823 int t = (ba[i] - start) >> 2;
4824 int ccadj_ = -CLOCK_ADJUST(1);
4826 instr_addr[t] = out;
4827 assem_debug("Assemble delay slot at %x\n",ba[i]);
4828 assem_debug("<->\n");
4829 drc_dbg_emit_do_cmp(t, ccadj_);
4830 if(regs[t].regmap_entry[HOST_CCREG]==CCREG&®s[t].regmap[HOST_CCREG]!=CCREG)
4831 wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty);
4832 load_regs(regs[t].regmap_entry,regs[t].regmap,dops[t].rs1,dops[t].rs2);
4833 address_generation(t,®s[t],regs[t].regmap_entry);
4834 if (ram_offset && (dops[t].is_load || dops[t].is_store))
4835 load_reg(regs[t].regmap_entry,regs[t].regmap,ROREG);
4836 if (dops[t].is_store)
4837 load_reg(regs[t].regmap_entry,regs[t].regmap,INVCP);
4839 switch (dops[t].itype) {
4847 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
4850 assemble(t, ®s[t], ccadj_);
4852 store_regs_bt(regs[t].regmap,regs[t].dirty,ba[i]+4);
4853 load_regs_bt(regs[t].regmap,regs[t].dirty,ba[i]+4);
4854 if(internal_branch(ba[i]+4))
4855 assem_debug("branch: internal\n");
4857 assem_debug("branch: external\n");
4858 assert(internal_branch(ba[i]+4));
4859 add_to_linker(out,ba[i]+4,internal_branch(ba[i]+4));
4863 // Load 2 immediates optimizing for small code size
4864 static void emit_mov2imm_compact(int imm1,u_int rt1,int imm2,u_int rt2)
4866 emit_movimm(imm1,rt1);
4867 emit_movimm_from(imm1,rt1,imm2,rt2);
4870 static void do_cc(int i, const signed char i_regmap[], int *adj,
4871 int addr, int taken, int invert)
4873 int count, count_plus2;
4877 if(dops[i].itype==RJUMP)
4881 //if(ba[i]>=start && ba[i]<(start+slen*4))
4882 if(internal_branch(ba[i]))
4885 if(dops[t].is_ds) *adj=-CLOCK_ADJUST(1); // Branch into delay slot adds an extra cycle
4893 count_plus2 = count + CLOCK_ADJUST(2);
4894 if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4896 if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
4898 //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4899 emit_andimm(HOST_CCREG,3,HOST_CCREG);
4903 else if(*adj==0||invert) {
4904 int cycles = count_plus2;
4909 if(-NO_CYCLE_PENALTY_THR<rel&&rel<0)
4910 cycles=*adj+count+2-*adj;
4913 emit_addimm_and_set_flags(cycles, HOST_CCREG);
4919 emit_cmpimm(HOST_CCREG, -count_plus2);
4923 add_stub(CC_STUB,jaddr,idle?idle:out,(*adj==0||invert||idle)?0:count_plus2,i,addr,taken,0);
4926 static void do_ccstub(int n)
4929 assem_debug("do_ccstub %x\n",start+(u_int)stubs[n].b*4);
4930 set_jump_target(stubs[n].addr, out);
4932 if(stubs[n].d==NULLDS) {
4933 // Delay slot instruction is nullified ("likely" branch)
4934 wb_dirtys(regs[i].regmap,regs[i].dirty);
4936 else if(stubs[n].d!=TAKEN) {
4937 wb_dirtys(branch_regs[i].regmap,branch_regs[i].dirty);
4940 if(internal_branch(ba[i]))
4941 wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
4945 // Save PC as return address
4946 emit_movimm(stubs[n].c,EAX);
4947 emit_writeword(EAX,&pcaddr);
4951 // Return address depends on which way the branch goes
4952 if(dops[i].itype==CJUMP||dops[i].itype==SJUMP)
4954 int s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
4955 int s2l=get_reg(branch_regs[i].regmap,dops[i].rs2);
4961 else if(dops[i].rs2==0)
4966 #ifdef DESTRUCTIVE_WRITEBACK
4968 if((branch_regs[i].dirty>>s1l)&&1)
4969 emit_loadreg(dops[i].rs1,s1l);
4972 if((branch_regs[i].dirty>>s1l)&1)
4973 emit_loadreg(dops[i].rs2,s1l);
4976 if((branch_regs[i].dirty>>s2l)&1)
4977 emit_loadreg(dops[i].rs2,s2l);
4980 int addr=-1,alt=-1,ntaddr=-1;
4983 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4984 branch_regs[i].regmap[hr]!=dops[i].rs1 &&
4985 branch_regs[i].regmap[hr]!=dops[i].rs2 )
4993 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4994 branch_regs[i].regmap[hr]!=dops[i].rs1 &&
4995 branch_regs[i].regmap[hr]!=dops[i].rs2 )
5001 if((dops[i].opcode&0x2E)==6) // BLEZ/BGTZ needs another register
5005 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5006 branch_regs[i].regmap[hr]!=dops[i].rs1 &&
5007 branch_regs[i].regmap[hr]!=dops[i].rs2 )
5013 assert(hr<HOST_REGS);
5015 if((dops[i].opcode&0x2f)==4) // BEQ
5017 #ifdef HAVE_CMOV_IMM
5018 if(s2l>=0) emit_cmp(s1l,s2l);
5019 else emit_test(s1l,s1l);
5020 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
5022 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5023 if(s2l>=0) emit_cmp(s1l,s2l);
5024 else emit_test(s1l,s1l);
5025 emit_cmovne_reg(alt,addr);
5028 if((dops[i].opcode&0x2f)==5) // BNE
5030 #ifdef HAVE_CMOV_IMM
5031 if(s2l>=0) emit_cmp(s1l,s2l);
5032 else emit_test(s1l,s1l);
5033 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
5035 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
5036 if(s2l>=0) emit_cmp(s1l,s2l);
5037 else emit_test(s1l,s1l);
5038 emit_cmovne_reg(alt,addr);
5041 if((dops[i].opcode&0x2f)==6) // BLEZ
5043 //emit_movimm(ba[i],alt);
5044 //emit_movimm(start+i*4+8,addr);
5045 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5047 emit_cmovl_reg(alt,addr);
5049 if((dops[i].opcode&0x2f)==7) // BGTZ
5051 //emit_movimm(ba[i],addr);
5052 //emit_movimm(start+i*4+8,ntaddr);
5053 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
5055 emit_cmovl_reg(ntaddr,addr);
5057 if((dops[i].opcode==1)&&(dops[i].opcode2&0x2D)==0) // BLTZ
5059 //emit_movimm(ba[i],alt);
5060 //emit_movimm(start+i*4+8,addr);
5061 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5063 emit_cmovs_reg(alt,addr);
5065 if((dops[i].opcode==1)&&(dops[i].opcode2&0x2D)==1) // BGEZ
5067 //emit_movimm(ba[i],addr);
5068 //emit_movimm(start+i*4+8,alt);
5069 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5071 emit_cmovs_reg(alt,addr);
5073 if(dops[i].opcode==0x11 && dops[i].opcode2==0x08 ) {
5074 if(source[i]&0x10000) // BC1T
5076 //emit_movimm(ba[i],alt);
5077 //emit_movimm(start+i*4+8,addr);
5078 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5079 emit_testimm(s1l,0x800000);
5080 emit_cmovne_reg(alt,addr);
5084 //emit_movimm(ba[i],addr);
5085 //emit_movimm(start+i*4+8,alt);
5086 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5087 emit_testimm(s1l,0x800000);
5088 emit_cmovne_reg(alt,addr);
5091 emit_writeword(addr,&pcaddr);
5094 if(dops[i].itype==RJUMP)
5096 int r=get_reg(branch_regs[i].regmap,dops[i].rs1);
5097 if (ds_writes_rjump_rs(i)) {
5098 r=get_reg(branch_regs[i].regmap,RTEMP);
5100 emit_writeword(r,&pcaddr);
5102 else {SysPrintf("Unknown branch type in do_ccstub\n");abort();}
5104 // Update cycle count
5105 assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
5106 if(stubs[n].a) emit_addimm(HOST_CCREG,(int)stubs[n].a,HOST_CCREG);
5107 emit_far_call(cc_interrupt);
5108 if(stubs[n].a) emit_addimm(HOST_CCREG,-(int)stubs[n].a,HOST_CCREG);
5109 if(stubs[n].d==TAKEN) {
5110 if(internal_branch(ba[i]))
5111 load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
5112 else if(dops[i].itype==RJUMP) {
5113 if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
5114 emit_readword(&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
5116 emit_loadreg(dops[i].rs1,get_reg(branch_regs[i].regmap,dops[i].rs1));
5118 }else if(stubs[n].d==NOTTAKEN) {
5119 if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5120 else load_all_regs(branch_regs[i].regmap);
5121 }else if(stubs[n].d==NULLDS) {
5122 // Delay slot instruction is nullified ("likely" branch)
5123 if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
5124 else load_all_regs(regs[i].regmap);
5126 load_all_regs(branch_regs[i].regmap);
5128 if (stubs[n].retaddr)
5129 emit_jmp(stubs[n].retaddr);
5131 do_jump_vaddr(stubs[n].e);
5134 static void add_to_linker(void *addr, u_int target, int is_internal)
5136 assert(linkcount < ARRAY_SIZE(link_addr));
5137 link_addr[linkcount].addr = addr;
5138 link_addr[linkcount].target = target;
5139 link_addr[linkcount].internal = is_internal;
5143 static void ujump_assemble_write_ra(int i)
5146 unsigned int return_address;
5147 rt=get_reg(branch_regs[i].regmap,31);
5148 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5150 return_address=start+i*4+8;
5153 if(internal_branch(return_address)&&dops[i+1].rt1!=31) {
5154 int temp=-1; // note: must be ds-safe
5158 if(temp>=0) do_miniht_insert(return_address,rt,temp);
5159 else emit_movimm(return_address,rt);
5167 if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
5170 emit_movimm(return_address,rt); // PC into link register
5172 emit_prefetch(hash_table_get(return_address));
5178 static void ujump_assemble(int i, const struct regstat *i_regs)
5181 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5182 address_generation(i+1,i_regs,regs[i].regmap_entry);
5184 int temp=get_reg(branch_regs[i].regmap,PTEMP);
5185 if(dops[i].rt1==31&&temp>=0)
5187 signed char *i_regmap=i_regs->regmap;
5188 int return_address=start+i*4+8;
5189 if(get_reg(branch_regs[i].regmap,31)>0)
5190 if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
5193 if(dops[i].rt1==31&&(dops[i].rt1==dops[i+1].rs1||dops[i].rt1==dops[i+1].rs2)) {
5194 ujump_assemble_write_ra(i); // writeback ra for DS
5197 ds_assemble(i+1,i_regs);
5198 uint64_t bc_unneeded=branch_regs[i].u;
5199 bc_unneeded|=1|(1LL<<dops[i].rt1);
5200 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
5201 load_reg(regs[i].regmap,branch_regs[i].regmap,CCREG);
5202 if(!ra_done&&dops[i].rt1==31)
5203 ujump_assemble_write_ra(i);
5205 cc=get_reg(branch_regs[i].regmap,CCREG);
5206 assert(cc==HOST_CCREG);
5207 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5209 if(dops[i].rt1==31&&temp>=0) emit_prefetchreg(temp);
5211 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5212 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
5213 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5214 if(internal_branch(ba[i]))
5215 assem_debug("branch: internal\n");
5217 assem_debug("branch: external\n");
5218 if (internal_branch(ba[i]) && dops[(ba[i]-start)>>2].is_ds) {
5219 ds_assemble_entry(i);
5222 add_to_linker(out,ba[i],internal_branch(ba[i]));
5227 static void rjump_assemble_write_ra(int i)
5229 int rt,return_address;
5230 assert(dops[i+1].rt1!=dops[i].rt1);
5231 assert(dops[i+1].rt2!=dops[i].rt1);
5232 rt=get_reg(branch_regs[i].regmap,dops[i].rt1);
5233 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5235 return_address=start+i*4+8;
5239 if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
5242 emit_movimm(return_address,rt); // PC into link register
5244 emit_prefetch(hash_table_get(return_address));
5248 static void rjump_assemble(int i, const struct regstat *i_regs)
5253 rs=get_reg(branch_regs[i].regmap,dops[i].rs1);
5255 if (ds_writes_rjump_rs(i)) {
5256 // Delay slot abuse, make a copy of the branch address register
5257 temp=get_reg(branch_regs[i].regmap,RTEMP);
5259 assert(regs[i].regmap[temp]==RTEMP);
5263 address_generation(i+1,i_regs,regs[i].regmap_entry);
5267 if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5268 signed char *i_regmap=i_regs->regmap;
5269 int return_address=start+i*4+8;
5270 if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
5275 if(dops[i].rs1==31) {
5276 int rh=get_reg(regs[i].regmap,RHASH);
5277 if(rh>=0) do_preload_rhash(rh);
5280 if(dops[i].rt1!=0&&(dops[i].rt1==dops[i+1].rs1||dops[i].rt1==dops[i+1].rs2)) {
5281 rjump_assemble_write_ra(i);
5284 ds_assemble(i+1,i_regs);
5285 uint64_t bc_unneeded=branch_regs[i].u;
5286 bc_unneeded|=1|(1LL<<dops[i].rt1);
5287 bc_unneeded&=~(1LL<<dops[i].rs1);
5288 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
5289 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,CCREG);
5290 if(!ra_done&&dops[i].rt1!=0)
5291 rjump_assemble_write_ra(i);
5292 cc=get_reg(branch_regs[i].regmap,CCREG);
5293 assert(cc==HOST_CCREG);
5296 int rh=get_reg(branch_regs[i].regmap,RHASH);
5297 int ht=get_reg(branch_regs[i].regmap,RHTBL);
5298 if(dops[i].rs1==31) {
5299 if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5300 do_preload_rhtbl(ht);
5304 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1);
5305 #ifdef DESTRUCTIVE_WRITEBACK
5306 if((branch_regs[i].dirty>>rs)&1) {
5307 if(dops[i].rs1!=dops[i+1].rt1&&dops[i].rs1!=dops[i+1].rt2) {
5308 emit_loadreg(dops[i].rs1,rs);
5313 if(dops[i].rt1==31&&temp>=0) emit_prefetchreg(temp);
5316 if(dops[i].rs1==31) {
5317 do_miniht_load(ht,rh);
5320 //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5321 //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5323 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG);
5324 add_stub(CC_STUB,out,NULL,0,i,-1,TAKEN,rs);
5325 if(dops[i+1].itype==COP0&&(source[i+1]&0x3f)==0x10)
5326 // special case for RFE
5330 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1);
5332 if(dops[i].rs1==31) {
5333 do_miniht_jump(rs,rh,ht);
5340 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5341 if(dops[i].rt1!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5345 static void cjump_assemble(int i, const struct regstat *i_regs)
5347 const signed char *i_regmap = i_regs->regmap;
5350 match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5351 assem_debug("match=%d\n",match);
5353 int unconditional=0,nop=0;
5355 int internal=internal_branch(ba[i]);
5356 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5357 if(!match) invert=1;
5358 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5359 if(i>(ba[i]-start)>>2) invert=1;
5362 invert=1; // because of near cond. branches
5366 s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
5367 s2l=get_reg(branch_regs[i].regmap,dops[i].rs2);
5370 s1l=get_reg(i_regmap,dops[i].rs1);
5371 s2l=get_reg(i_regmap,dops[i].rs2);
5373 if(dops[i].rs1==0&&dops[i].rs2==0)
5375 if(dops[i].opcode&1) nop=1;
5376 else unconditional=1;
5377 //assert(dops[i].opcode!=5);
5378 //assert(dops[i].opcode!=7);
5379 //assert(dops[i].opcode!=0x15);
5380 //assert(dops[i].opcode!=0x17);
5382 else if(dops[i].rs1==0)
5387 else if(dops[i].rs2==0)
5393 // Out of order execution (delay slot first)
5395 address_generation(i+1,i_regs,regs[i].regmap_entry);
5396 ds_assemble(i+1,i_regs);
5398 uint64_t bc_unneeded=branch_regs[i].u;
5399 bc_unneeded&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
5401 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
5402 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,dops[i].rs2);
5403 load_reg(regs[i].regmap,branch_regs[i].regmap,CCREG);
5404 cc=get_reg(branch_regs[i].regmap,CCREG);
5405 assert(cc==HOST_CCREG);
5407 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5408 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5409 //assem_debug("cycle count (adj)\n");
5411 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5412 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5413 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
5414 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5416 assem_debug("branch: internal\n");
5418 assem_debug("branch: external\n");
5419 if (internal && dops[(ba[i]-start)>>2].is_ds) {
5420 ds_assemble_entry(i);
5423 add_to_linker(out,ba[i],internal);
5426 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5427 if(((u_int)out)&7) emit_addnop(0);
5432 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc);
5435 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5438 void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL;
5439 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5440 if(adj&&!invert) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
5442 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5444 if(dops[i].opcode==4) // BEQ
5446 if(s2l>=0) emit_cmp(s1l,s2l);
5447 else emit_test(s1l,s1l);
5452 add_to_linker(out,ba[i],internal);
5456 if(dops[i].opcode==5) // BNE
5458 if(s2l>=0) emit_cmp(s1l,s2l);
5459 else emit_test(s1l,s1l);
5464 add_to_linker(out,ba[i],internal);
5468 if(dops[i].opcode==6) // BLEZ
5475 add_to_linker(out,ba[i],internal);
5479 if(dops[i].opcode==7) // BGTZ
5486 add_to_linker(out,ba[i],internal);
5491 if(taken) set_jump_target(taken, out);
5492 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5493 if (match && (!internal || !dops[(ba[i]-start)>>2].is_ds)) {
5495 emit_addimm(cc,-adj,cc);
5496 add_to_linker(out,ba[i],internal);
5499 add_to_linker(out,ba[i],internal*2);
5505 if(adj) emit_addimm(cc,-adj,cc);
5506 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5507 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5509 assem_debug("branch: internal\n");
5511 assem_debug("branch: external\n");
5512 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
5513 ds_assemble_entry(i);
5516 add_to_linker(out,ba[i],internal);
5520 set_jump_target(nottaken, out);
5523 if(nottaken1) set_jump_target(nottaken1, out);
5525 if(!invert) emit_addimm(cc,adj,cc);
5527 } // (!unconditional)
5531 // In-order execution (branch first)
5532 void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL;
5533 if(!unconditional&&!nop) {
5534 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5536 if((dops[i].opcode&0x2f)==4) // BEQ
5538 if(s2l>=0) emit_cmp(s1l,s2l);
5539 else emit_test(s1l,s1l);
5543 if((dops[i].opcode&0x2f)==5) // BNE
5545 if(s2l>=0) emit_cmp(s1l,s2l);
5546 else emit_test(s1l,s1l);
5550 if((dops[i].opcode&0x2f)==6) // BLEZ
5556 if((dops[i].opcode&0x2f)==7) // BGTZ
5562 } // if(!unconditional)
5564 uint64_t ds_unneeded=branch_regs[i].u;
5565 ds_unneeded&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
5569 if(taken) set_jump_target(taken, out);
5570 assem_debug("1:\n");
5571 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5573 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5574 address_generation(i+1,&branch_regs[i],0);
5576 load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG);
5577 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
5578 ds_assemble(i+1,&branch_regs[i]);
5579 cc=get_reg(branch_regs[i].regmap,CCREG);
5581 emit_loadreg(CCREG,cc=HOST_CCREG);
5582 // CHECK: Is the following instruction (fall thru) allocated ok?
5584 assert(cc==HOST_CCREG);
5585 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5586 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5587 assem_debug("cycle count (adj)\n");
5588 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
5589 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5591 assem_debug("branch: internal\n");
5593 assem_debug("branch: external\n");
5594 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
5595 ds_assemble_entry(i);
5598 add_to_linker(out,ba[i],internal);
5603 if(!unconditional) {
5604 if(nottaken1) set_jump_target(nottaken1, out);
5605 set_jump_target(nottaken, out);
5606 assem_debug("2:\n");
5607 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5609 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5610 address_generation(i+1,&branch_regs[i],0);
5612 load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG);
5613 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
5614 ds_assemble(i+1,&branch_regs[i]);
5615 cc=get_reg(branch_regs[i].regmap,CCREG);
5617 // Cycle count isn't in a register, temporarily load it then write it out
5618 emit_loadreg(CCREG,HOST_CCREG);
5619 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG);
5622 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5623 emit_storereg(CCREG,HOST_CCREG);
5626 cc=get_reg(i_regmap,CCREG);
5627 assert(cc==HOST_CCREG);
5628 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc);
5631 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5637 static void sjump_assemble(int i, const struct regstat *i_regs)
5639 const signed char *i_regmap = i_regs->regmap;
5642 match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5643 assem_debug("smatch=%d ooo=%d\n", match, dops[i].ooo);
5645 int unconditional=0,nevertaken=0;
5647 int internal=internal_branch(ba[i]);
5648 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5649 if(!match) invert=1;
5650 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5651 if(i>(ba[i]-start)>>2) invert=1;
5654 invert=1; // because of near cond. branches
5657 //if(dops[i].opcode2>=0x10) return; // FIXME (BxxZAL)
5658 //assert(dops[i].opcode2<0x10||dops[i].rs1==0); // FIXME (BxxZAL)
5661 s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
5664 s1l=get_reg(i_regmap,dops[i].rs1);
5668 if(dops[i].opcode2&1) unconditional=1;
5670 // These are never taken (r0 is never less than zero)
5671 //assert(dops[i].opcode2!=0);
5672 //assert(dops[i].opcode2!=2);
5673 //assert(dops[i].opcode2!=0x10);
5674 //assert(dops[i].opcode2!=0x12);
5678 // Out of order execution (delay slot first)
5680 address_generation(i+1,i_regs,regs[i].regmap_entry);
5681 ds_assemble(i+1,i_regs);
5683 uint64_t bc_unneeded=branch_regs[i].u;
5684 bc_unneeded&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
5686 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
5687 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,dops[i].rs1);
5688 load_reg(regs[i].regmap,branch_regs[i].regmap,CCREG);
5689 if(dops[i].rt1==31) {
5690 int rt,return_address;
5691 rt=get_reg(branch_regs[i].regmap,31);
5692 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5694 // Save the PC even if the branch is not taken
5695 return_address=start+i*4+8;
5696 emit_movimm(return_address,rt); // PC into link register
5698 if(!nevertaken) emit_prefetch(hash_table_get(return_address));
5702 cc=get_reg(branch_regs[i].regmap,CCREG);
5703 assert(cc==HOST_CCREG);
5705 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5706 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5707 assem_debug("cycle count (adj)\n");
5709 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5710 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5711 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
5712 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5714 assem_debug("branch: internal\n");
5716 assem_debug("branch: external\n");
5717 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
5718 ds_assemble_entry(i);
5721 add_to_linker(out,ba[i],internal);
5724 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5725 if(((u_int)out)&7) emit_addnop(0);
5729 else if(nevertaken) {
5730 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc);
5733 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5736 void *nottaken = NULL;
5737 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5738 if(adj&&!invert) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
5741 if((dops[i].opcode2&0xf)==0) // BLTZ/BLTZAL
5748 add_to_linker(out,ba[i],internal);
5752 if((dops[i].opcode2&0xf)==1) // BGEZ/BLTZAL
5759 add_to_linker(out,ba[i],internal);
5766 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5767 if (match && (!internal || !dops[(ba[i] - start) >> 2].is_ds)) {
5769 emit_addimm(cc,-adj,cc);
5770 add_to_linker(out,ba[i],internal);
5773 add_to_linker(out,ba[i],internal*2);
5779 if(adj) emit_addimm(cc,-adj,cc);
5780 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5781 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5783 assem_debug("branch: internal\n");
5785 assem_debug("branch: external\n");
5786 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
5787 ds_assemble_entry(i);
5790 add_to_linker(out,ba[i],internal);
5794 set_jump_target(nottaken, out);
5798 if(!invert) emit_addimm(cc,adj,cc);
5800 } // (!unconditional)
5804 // In-order execution (branch first)
5806 void *nottaken = NULL;
5807 if(dops[i].rt1==31) {
5808 int rt,return_address;
5809 rt=get_reg(branch_regs[i].regmap,31);
5811 // Save the PC even if the branch is not taken
5812 return_address=start+i*4+8;
5813 emit_movimm(return_address,rt); // PC into link register
5815 emit_prefetch(hash_table_get(return_address));
5819 if(!unconditional) {
5820 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5822 if((dops[i].opcode2&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
5828 if((dops[i].opcode2&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
5834 } // if(!unconditional)
5836 uint64_t ds_unneeded=branch_regs[i].u;
5837 ds_unneeded&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
5841 //assem_debug("1:\n");
5842 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5844 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5845 address_generation(i+1,&branch_regs[i],0);
5847 load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG);
5848 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
5849 ds_assemble(i+1,&branch_regs[i]);
5850 cc=get_reg(branch_regs[i].regmap,CCREG);
5852 emit_loadreg(CCREG,cc=HOST_CCREG);
5853 // CHECK: Is the following instruction (fall thru) allocated ok?
5855 assert(cc==HOST_CCREG);
5856 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5857 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5858 assem_debug("cycle count (adj)\n");
5859 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
5860 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5862 assem_debug("branch: internal\n");
5864 assem_debug("branch: external\n");
5865 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
5866 ds_assemble_entry(i);
5869 add_to_linker(out,ba[i],internal);
5874 if(!unconditional) {
5875 set_jump_target(nottaken, out);
5876 assem_debug("1:\n");
5877 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5878 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5879 address_generation(i+1,&branch_regs[i],0);
5881 load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG);
5882 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
5883 ds_assemble(i+1,&branch_regs[i]);
5884 cc=get_reg(branch_regs[i].regmap,CCREG);
5886 // Cycle count isn't in a register, temporarily load it then write it out
5887 emit_loadreg(CCREG,HOST_CCREG);
5888 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG);
5891 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5892 emit_storereg(CCREG,HOST_CCREG);
5895 cc=get_reg(i_regmap,CCREG);
5896 assert(cc==HOST_CCREG);
5897 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc);
5900 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5906 static void check_regmap(signed char *regmap)
5910 for (i = 0; i < HOST_REGS; i++) {
5913 for (j = i + 1; j < HOST_REGS; j++)
5914 assert(regmap[i] != regmap[j]);
5920 #include <inttypes.h>
5921 static char insn[MAXBLOCK][10];
5923 #define set_mnemonic(i_, n_) \
5924 strcpy(insn[i_], n_)
5926 void print_regmap(const char *name, const signed char *regmap)
5930 fputs(name, stdout);
5931 for (i = 0; i < HOST_REGS; i++) {
5934 l = snprintf(buf, sizeof(buf), "$%d", regmap[i]);
5938 printf(" r%d=%s", i, buf);
5940 fputs("\n", stdout);
5944 void disassemble_inst(int i)
5946 if (dops[i].bt) printf("*"); else printf(" ");
5947 switch(dops[i].itype) {
5949 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
5951 printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2,i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
5953 printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
5955 if (dops[i].opcode==0x9&&dops[i].rt1!=31)
5956 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1);
5958 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rs1);
5961 if(dops[i].opcode==0xf) //LUI
5962 printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],dops[i].rt1,imm[i]&0xffff);
5964 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,imm[i]);
5968 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,imm[i]);
5972 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],dops[i].rs2,dops[i].rs1,imm[i]);
5976 printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,dops[i].rs2);
5979 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2);
5982 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,imm[i]);
5985 if((dops[i].opcode2&0x1d)==0x10)
5986 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rt1);
5987 else if((dops[i].opcode2&0x1d)==0x11)
5988 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rs1);
5990 printf (" %x: %s\n",start+i*4,insn[i]);
5993 if(dops[i].opcode2==0)
5994 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC0
5995 else if(dops[i].opcode2==4)
5996 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC0
5997 else printf (" %x: %s\n",start+i*4,insn[i]);
6000 if(dops[i].opcode2<3)
6001 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC1
6002 else if(dops[i].opcode2>3)
6003 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC1
6004 else printf (" %x: %s\n",start+i*4,insn[i]);
6007 if(dops[i].opcode2<3)
6008 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC2
6009 else if(dops[i].opcode2>3)
6010 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC2
6011 else printf (" %x: %s\n",start+i*4,insn[i]);
6014 printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,dops[i].rs1,imm[i]);
6017 printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,dops[i].rs1,imm[i]);
6020 printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
6023 //printf (" %s %8x\n",insn[i],source[i]);
6024 printf (" %x: %s\n",start+i*4,insn[i]);
6027 printf("D: %"PRIu64" WD: %"PRIu64" U: %"PRIu64"\n",
6028 regs[i].dirty, regs[i].wasdirty, unneeded_reg[i]);
6029 print_regmap("pre: ", regmap_pre[i]);
6030 print_regmap("entry: ", regs[i].regmap_entry);
6031 print_regmap("map: ", regs[i].regmap);
6032 if (dops[i].is_jump) {
6033 print_regmap("bentry:", branch_regs[i].regmap_entry);
6034 print_regmap("bmap: ", branch_regs[i].regmap);
6038 #define set_mnemonic(i_, n_)
6039 static void disassemble_inst(int i) {}
6042 #define DRC_TEST_VAL 0x74657374
6044 static void new_dynarec_test(void)
6046 int (*testfunc)(void);
6051 // check structure linkage
6052 if ((u_char *)rcnts - (u_char *)&psxRegs != sizeof(psxRegs))
6054 SysPrintf("linkage_arm* miscompilation/breakage detected.\n");
6057 SysPrintf("testing if we can run recompiled code @%p...\n", out);
6058 ((volatile u_int *)out)[0]++; // make cache dirty
6060 for (i = 0; i < ARRAY_SIZE(ret); i++) {
6061 out = ndrc->translation_cache;
6062 beginning = start_block();
6063 emit_movimm(DRC_TEST_VAL + i, 0); // test
6066 end_block(beginning);
6067 testfunc = beginning;
6068 ret[i] = testfunc();
6071 if (ret[0] == DRC_TEST_VAL && ret[1] == DRC_TEST_VAL + 1)
6072 SysPrintf("test passed.\n");
6074 SysPrintf("test failed, will likely crash soon (r=%08x %08x)\n", ret[0], ret[1]);
6075 out = ndrc->translation_cache;
6078 // clear the state completely, instead of just marking
6079 // things invalid like invalidate_all_pages() does
6080 void new_dynarec_clear_full(void)
6083 out = ndrc->translation_cache;
6084 memset(invalid_code,1,sizeof(invalid_code));
6085 memset(hash_table,0xff,sizeof(hash_table));
6086 memset(mini_ht,-1,sizeof(mini_ht));
6087 memset(shadow,0,sizeof(shadow));
6089 expirep=16384; // Expiry pointer, +2 blocks
6090 pending_exception=0;
6093 inv_code_start=inv_code_end=~0;
6097 for(n=0;n<4096;n++) blocks_clear(&blocks[n]);
6098 for(n=0;n<4096;n++) ll_clear(jump_out+n);
6099 stat_clear(stat_blocks);
6100 stat_clear(stat_links);
6102 cycle_multiplier_old = cycle_multiplier;
6103 new_dynarec_hacks_old = new_dynarec_hacks;
6106 void new_dynarec_init(void)
6108 SysPrintf("Init new dynarec, ndrc size %x\n", (int)sizeof(*ndrc));
6113 #ifdef BASE_ADDR_DYNAMIC
6115 sceBlock = getVMBlock(); //sceKernelAllocMemBlockForVM("code", sizeof(*ndrc));
6117 SysPrintf("sceKernelAllocMemBlockForVM failed: %x\n", sceBlock);
6118 int ret = sceKernelGetMemBlockBase(sceBlock, (void **)&ndrc);
6120 SysPrintf("sceKernelGetMemBlockBase failed: %x\n", ret);
6121 sceKernelOpenVMDomain();
6122 sceClibPrintf("translation_cache = 0x%08lx\n ", (long)ndrc->translation_cache);
6123 #elif defined(_MSC_VER)
6124 ndrc = VirtualAlloc(NULL, sizeof(*ndrc), MEM_COMMIT | MEM_RESERVE,
6125 PAGE_EXECUTE_READWRITE);
6127 uintptr_t desired_addr = 0;
6130 desired_addr = ((uintptr_t)&_end + 0xffffff) & ~0xffffffl;
6132 ndrc = mmap((void *)desired_addr, sizeof(*ndrc),
6133 PROT_READ | PROT_WRITE | PROT_EXEC,
6134 MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
6135 if (ndrc == MAP_FAILED) {
6136 SysPrintf("mmap() failed: %s\n", strerror(errno));
6141 #ifndef NO_WRITE_EXEC
6142 // not all systems allow execute in data segment by default
6143 // size must be 4K aligned for 3DS?
6144 if (mprotect(ndrc, sizeof(*ndrc),
6145 PROT_READ | PROT_WRITE | PROT_EXEC) != 0)
6146 SysPrintf("mprotect() failed: %s\n", strerror(errno));
6149 out = ndrc->translation_cache;
6150 cycle_multiplier=200;
6151 new_dynarec_clear_full();
6153 // Copy this into local area so we don't have to put it in every literal pool
6154 invc_ptr=invalid_code;
6158 ram_offset=(uintptr_t)rdram-0x80000000;
6160 SysPrintf("warning: RAM is not directly mapped, performance will suffer\n");
6161 SysPrintf("Mapped (RAM/scrp/ROM/LUTs/TC):\n");
6162 SysPrintf("%p/%p/%p/%p/%p\n", psxM, psxH, psxR, mem_rtab, out);
6165 void new_dynarec_cleanup(void)
6168 #ifdef BASE_ADDR_DYNAMIC
6170 // sceBlock is managed by retroarch's bootstrap code
6171 //sceKernelFreeMemBlock(sceBlock);
6174 if (munmap(ndrc, sizeof(*ndrc)) < 0)
6175 SysPrintf("munmap() failed\n");
6178 for(n=0;n<4096;n++) blocks_clear(&blocks[n]);
6179 for(n=0;n<4096;n++) ll_clear(jump_out+n);
6180 stat_clear(stat_blocks);
6181 stat_clear(stat_links);
6183 if (munmap (ROM_COPY, 67108864) < 0) {SysPrintf("munmap() failed\n");}
6185 new_dynarec_print_stats();
6188 static u_int *get_source_start(u_int addr, u_int *limit)
6190 if (addr < 0x00200000 ||
6191 (0xa0000000 <= addr && addr < 0xa0200000))
6193 // used for BIOS calls mostly?
6194 *limit = (addr&0xa0000000)|0x00200000;
6195 return (u_int *)(rdram + (addr&0x1fffff));
6197 else if (!Config.HLE && (
6198 /* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
6199 (0xbfc00000 <= addr && addr < 0xbfc80000)))
6201 // BIOS. The multiplier should be much higher as it's uncached 8bit mem,
6202 // but timings in PCSX are too tied to the interpreter's BIAS
6203 if (!HACK_ENABLED(NDHACK_OVERRIDE_CYCLE_M))
6204 cycle_multiplier_active = 200;
6206 *limit = (addr & 0xfff00000) | 0x80000;
6207 return (u_int *)((u_char *)psxR + (addr&0x7ffff));
6209 else if (addr >= 0x80000000 && addr < 0x80000000+RAM_SIZE) {
6210 *limit = (addr & 0x80600000) + 0x00200000;
6211 return (u_int *)(rdram + (addr&0x1fffff));
6216 static u_int scan_for_ret(u_int addr)
6221 mem = get_source_start(addr, &limit);
6225 if (limit > addr + 0x1000)
6226 limit = addr + 0x1000;
6227 for (; addr < limit; addr += 4, mem++) {
6228 if (*mem == 0x03e00008) // jr $ra
6234 struct savestate_block {
6239 static int addr_cmp(const void *p1_, const void *p2_)
6241 const struct savestate_block *p1 = p1_, *p2 = p2_;
6242 return p1->addr - p2->addr;
6245 int new_dynarec_save_blocks(void *save, int size)
6247 struct savestate_block *sblocks = save;
6248 int maxcount = size / sizeof(sblocks[0]);
6249 struct savestate_block tmp_blocks[1024];
6250 struct block_info *block;
6251 int p, s, d, o, bcnt;
6255 for (p = 0; p < ARRAY_SIZE(blocks); p++) {
6257 for (block = blocks[p]; block != NULL; block = block->next) {
6258 if (block->is_dirty)
6260 tmp_blocks[bcnt].addr = block->start;
6261 tmp_blocks[bcnt].regflags = block->reg_sv_flags;
6266 qsort(tmp_blocks, bcnt, sizeof(tmp_blocks[0]), addr_cmp);
6268 addr = tmp_blocks[0].addr;
6269 for (s = d = 0; s < bcnt; s++) {
6270 if (tmp_blocks[s].addr < addr)
6272 if (d == 0 || tmp_blocks[d-1].addr != tmp_blocks[s].addr)
6273 tmp_blocks[d++] = tmp_blocks[s];
6274 addr = scan_for_ret(tmp_blocks[s].addr);
6277 if (o + d > maxcount)
6279 memcpy(&sblocks[o], tmp_blocks, d * sizeof(sblocks[0]));
6283 return o * sizeof(sblocks[0]);
6286 void new_dynarec_load_blocks(const void *save, int size)
6288 const struct savestate_block *sblocks = save;
6289 int count = size / sizeof(sblocks[0]);
6290 struct block_info *block;
6291 u_int regs_save[32];
6296 // restore clean blocks, if any
6297 for (page = 0, b = i = 0; page < ARRAY_SIZE(blocks); page++) {
6298 for (block = blocks[page]; block != NULL; block = block->next, b++) {
6299 if (!block->is_dirty)
6301 assert(block->source && block->copy);
6302 if (memcmp(block->source, block->copy, block->len))
6305 // see try_restore_block
6306 block->is_dirty = 0;
6307 mark_invalid_code(block->start, block->len, 0);
6311 inv_debug("load_blocks: %d/%d clean blocks\n", i, b);
6313 // change GPRs for speculation to at least partially work..
6314 memcpy(regs_save, &psxRegs.GPR, sizeof(regs_save));
6315 for (i = 1; i < 32; i++)
6316 psxRegs.GPR.r[i] = 0x80000000;
6318 for (b = 0; b < count; b++) {
6319 for (f = sblocks[b].regflags, i = 0; f; f >>= 1, i++) {
6321 psxRegs.GPR.r[i] = 0x1f800000;
6324 ndrc_get_addr_ht(sblocks[b].addr);
6326 for (f = sblocks[b].regflags, i = 0; f; f >>= 1, i++) {
6328 psxRegs.GPR.r[i] = 0x80000000;
6332 memcpy(&psxRegs.GPR, regs_save, sizeof(regs_save));
6335 void new_dynarec_print_stats(void)
6338 printf("cc %3d,%3d,%3d lu%6d,%3d,%3d c%3d inv%3d,%3d tc_offs %zu b %u,%u\n",
6339 stat_bc_pre, stat_bc_direct, stat_bc_restore,
6340 stat_ht_lookups, stat_jump_in_lookups, stat_restore_tries,
6341 stat_restore_compares, stat_inv_addr_calls, stat_inv_hits,
6342 out - ndrc->translation_cache, stat_blocks, stat_links);
6343 stat_bc_direct = stat_bc_pre = stat_bc_restore =
6344 stat_ht_lookups = stat_jump_in_lookups = stat_restore_tries =
6345 stat_restore_compares = stat_inv_addr_calls = stat_inv_hits = 0;
6349 static int apply_hacks(void)
6352 if (HACK_ENABLED(NDHACK_NO_COMPAT_HACKS))
6354 /* special hack(s) */
6355 for (i = 0; i < slen - 4; i++)
6357 // lui a4, 0xf200; jal <rcnt_read>; addu a0, 2; slti v0, 28224
6358 if (source[i] == 0x3c04f200 && dops[i+1].itype == UJUMP
6359 && source[i+2] == 0x34840002 && dops[i+3].opcode == 0x0a
6360 && imm[i+3] == 0x6e40 && dops[i+3].rs1 == 2)
6362 SysPrintf("PE2 hack @%08x\n", start + (i+3)*4);
6363 dops[i + 3].itype = NOP;
6367 if (i > 10 && source[i-1] == 0 && source[i-2] == 0x03e00008
6368 && source[i-4] == 0x8fbf0018 && source[i-6] == 0x00c0f809
6369 && dops[i-7].itype == STORE)
6372 if (dops[i].itype == IMM16)
6374 // swl r2, 15(r6); swr r2, 12(r6); sw r6, *; jalr r6
6375 if (dops[i].itype == STORELR && dops[i].rs1 == 6
6376 && dops[i-1].itype == STORELR && dops[i-1].rs1 == 6)
6378 SysPrintf("F1 hack from %08x, old dst %08x\n", start, hack_addr);
6386 static noinline void pass1_disassemble(u_int pagelimit)
6388 int i, j, done = 0, ni_count = 0;
6389 unsigned int type,op,op2;
6391 for (i = 0; !done; i++)
6393 memset(&dops[i], 0, sizeof(dops[i]));
6395 minimum_free_regs[i]=0;
6396 dops[i].opcode=op=source[i]>>26;
6399 case 0x00: set_mnemonic(i, "special"); type=NI;
6403 case 0x00: set_mnemonic(i, "SLL"); type=SHIFTIMM; break;
6404 case 0x02: set_mnemonic(i, "SRL"); type=SHIFTIMM; break;
6405 case 0x03: set_mnemonic(i, "SRA"); type=SHIFTIMM; break;
6406 case 0x04: set_mnemonic(i, "SLLV"); type=SHIFT; break;
6407 case 0x06: set_mnemonic(i, "SRLV"); type=SHIFT; break;
6408 case 0x07: set_mnemonic(i, "SRAV"); type=SHIFT; break;
6409 case 0x08: set_mnemonic(i, "JR"); type=RJUMP; break;
6410 case 0x09: set_mnemonic(i, "JALR"); type=RJUMP; break;
6411 case 0x0C: set_mnemonic(i, "SYSCALL"); type=SYSCALL; break;
6412 case 0x0D: set_mnemonic(i, "BREAK"); type=SYSCALL; break;
6413 case 0x0F: set_mnemonic(i, "SYNC"); type=OTHER; break;
6414 case 0x10: set_mnemonic(i, "MFHI"); type=MOV; break;
6415 case 0x11: set_mnemonic(i, "MTHI"); type=MOV; break;
6416 case 0x12: set_mnemonic(i, "MFLO"); type=MOV; break;
6417 case 0x13: set_mnemonic(i, "MTLO"); type=MOV; break;
6418 case 0x18: set_mnemonic(i, "MULT"); type=MULTDIV; break;
6419 case 0x19: set_mnemonic(i, "MULTU"); type=MULTDIV; break;
6420 case 0x1A: set_mnemonic(i, "DIV"); type=MULTDIV; break;
6421 case 0x1B: set_mnemonic(i, "DIVU"); type=MULTDIV; break;
6422 case 0x20: set_mnemonic(i, "ADD"); type=ALU; break;
6423 case 0x21: set_mnemonic(i, "ADDU"); type=ALU; break;
6424 case 0x22: set_mnemonic(i, "SUB"); type=ALU; break;
6425 case 0x23: set_mnemonic(i, "SUBU"); type=ALU; break;
6426 case 0x24: set_mnemonic(i, "AND"); type=ALU; break;
6427 case 0x25: set_mnemonic(i, "OR"); type=ALU; break;
6428 case 0x26: set_mnemonic(i, "XOR"); type=ALU; break;
6429 case 0x27: set_mnemonic(i, "NOR"); type=ALU; break;
6430 case 0x2A: set_mnemonic(i, "SLT"); type=ALU; break;
6431 case 0x2B: set_mnemonic(i, "SLTU"); type=ALU; break;
6432 case 0x30: set_mnemonic(i, "TGE"); type=NI; break;
6433 case 0x31: set_mnemonic(i, "TGEU"); type=NI; break;
6434 case 0x32: set_mnemonic(i, "TLT"); type=NI; break;
6435 case 0x33: set_mnemonic(i, "TLTU"); type=NI; break;
6436 case 0x34: set_mnemonic(i, "TEQ"); type=NI; break;
6437 case 0x36: set_mnemonic(i, "TNE"); type=NI; break;
6439 case 0x14: set_mnemonic(i, "DSLLV"); type=SHIFT; break;
6440 case 0x16: set_mnemonic(i, "DSRLV"); type=SHIFT; break;
6441 case 0x17: set_mnemonic(i, "DSRAV"); type=SHIFT; break;
6442 case 0x1C: set_mnemonic(i, "DMULT"); type=MULTDIV; break;
6443 case 0x1D: set_mnemonic(i, "DMULTU"); type=MULTDIV; break;
6444 case 0x1E: set_mnemonic(i, "DDIV"); type=MULTDIV; break;
6445 case 0x1F: set_mnemonic(i, "DDIVU"); type=MULTDIV; break;
6446 case 0x2C: set_mnemonic(i, "DADD"); type=ALU; break;
6447 case 0x2D: set_mnemonic(i, "DADDU"); type=ALU; break;
6448 case 0x2E: set_mnemonic(i, "DSUB"); type=ALU; break;
6449 case 0x2F: set_mnemonic(i, "DSUBU"); type=ALU; break;
6450 case 0x38: set_mnemonic(i, "DSLL"); type=SHIFTIMM; break;
6451 case 0x3A: set_mnemonic(i, "DSRL"); type=SHIFTIMM; break;
6452 case 0x3B: set_mnemonic(i, "DSRA"); type=SHIFTIMM; break;
6453 case 0x3C: set_mnemonic(i, "DSLL32"); type=SHIFTIMM; break;
6454 case 0x3E: set_mnemonic(i, "DSRL32"); type=SHIFTIMM; break;
6455 case 0x3F: set_mnemonic(i, "DSRA32"); type=SHIFTIMM; break;
6459 case 0x01: set_mnemonic(i, "regimm"); type=NI;
6460 op2=(source[i]>>16)&0x1f;
6463 case 0x00: set_mnemonic(i, "BLTZ"); type=SJUMP; break;
6464 case 0x01: set_mnemonic(i, "BGEZ"); type=SJUMP; break;
6465 //case 0x02: set_mnemonic(i, "BLTZL"); type=SJUMP; break;
6466 //case 0x03: set_mnemonic(i, "BGEZL"); type=SJUMP; break;
6467 //case 0x08: set_mnemonic(i, "TGEI"); type=NI; break;
6468 //case 0x09: set_mnemonic(i, "TGEIU"); type=NI; break;
6469 //case 0x0A: set_mnemonic(i, "TLTI"); type=NI; break;
6470 //case 0x0B: set_mnemonic(i, "TLTIU"); type=NI; break;
6471 //case 0x0C: set_mnemonic(i, "TEQI"); type=NI; break;
6472 //case 0x0E: set_mnemonic(i, "TNEI"); type=NI; break;
6473 case 0x10: set_mnemonic(i, "BLTZAL"); type=SJUMP; break;
6474 case 0x11: set_mnemonic(i, "BGEZAL"); type=SJUMP; break;
6475 //case 0x12: set_mnemonic(i, "BLTZALL"); type=SJUMP; break;
6476 //case 0x13: set_mnemonic(i, "BGEZALL"); type=SJUMP; break;
6479 case 0x02: set_mnemonic(i, "J"); type=UJUMP; break;
6480 case 0x03: set_mnemonic(i, "JAL"); type=UJUMP; break;
6481 case 0x04: set_mnemonic(i, "BEQ"); type=CJUMP; break;
6482 case 0x05: set_mnemonic(i, "BNE"); type=CJUMP; break;
6483 case 0x06: set_mnemonic(i, "BLEZ"); type=CJUMP; break;
6484 case 0x07: set_mnemonic(i, "BGTZ"); type=CJUMP; break;
6485 case 0x08: set_mnemonic(i, "ADDI"); type=IMM16; break;
6486 case 0x09: set_mnemonic(i, "ADDIU"); type=IMM16; break;
6487 case 0x0A: set_mnemonic(i, "SLTI"); type=IMM16; break;
6488 case 0x0B: set_mnemonic(i, "SLTIU"); type=IMM16; break;
6489 case 0x0C: set_mnemonic(i, "ANDI"); type=IMM16; break;
6490 case 0x0D: set_mnemonic(i, "ORI"); type=IMM16; break;
6491 case 0x0E: set_mnemonic(i, "XORI"); type=IMM16; break;
6492 case 0x0F: set_mnemonic(i, "LUI"); type=IMM16; break;
6493 case 0x10: set_mnemonic(i, "cop0"); type=NI;
6494 op2=(source[i]>>21)&0x1f;
6497 case 0x00: set_mnemonic(i, "MFC0"); type=COP0; break;
6498 case 0x02: set_mnemonic(i, "CFC0"); type=COP0; break;
6499 case 0x04: set_mnemonic(i, "MTC0"); type=COP0; break;
6500 case 0x06: set_mnemonic(i, "CTC0"); type=COP0; break;
6501 case 0x10: set_mnemonic(i, "RFE"); type=COP0; break;
6504 case 0x11: set_mnemonic(i, "cop1"); type=COP1;
6505 op2=(source[i]>>21)&0x1f;
6508 case 0x14: set_mnemonic(i, "BEQL"); type=CJUMP; break;
6509 case 0x15: set_mnemonic(i, "BNEL"); type=CJUMP; break;
6510 case 0x16: set_mnemonic(i, "BLEZL"); type=CJUMP; break;
6511 case 0x17: set_mnemonic(i, "BGTZL"); type=CJUMP; break;
6512 case 0x18: set_mnemonic(i, "DADDI"); type=IMM16; break;
6513 case 0x19: set_mnemonic(i, "DADDIU"); type=IMM16; break;
6514 case 0x1A: set_mnemonic(i, "LDL"); type=LOADLR; break;
6515 case 0x1B: set_mnemonic(i, "LDR"); type=LOADLR; break;
6517 case 0x20: set_mnemonic(i, "LB"); type=LOAD; break;
6518 case 0x21: set_mnemonic(i, "LH"); type=LOAD; break;
6519 case 0x22: set_mnemonic(i, "LWL"); type=LOADLR; break;
6520 case 0x23: set_mnemonic(i, "LW"); type=LOAD; break;
6521 case 0x24: set_mnemonic(i, "LBU"); type=LOAD; break;
6522 case 0x25: set_mnemonic(i, "LHU"); type=LOAD; break;
6523 case 0x26: set_mnemonic(i, "LWR"); type=LOADLR; break;
6525 case 0x27: set_mnemonic(i, "LWU"); type=LOAD; break;
6527 case 0x28: set_mnemonic(i, "SB"); type=STORE; break;
6528 case 0x29: set_mnemonic(i, "SH"); type=STORE; break;
6529 case 0x2A: set_mnemonic(i, "SWL"); type=STORELR; break;
6530 case 0x2B: set_mnemonic(i, "SW"); type=STORE; break;
6532 case 0x2C: set_mnemonic(i, "SDL"); type=STORELR; break;
6533 case 0x2D: set_mnemonic(i, "SDR"); type=STORELR; break;
6535 case 0x2E: set_mnemonic(i, "SWR"); type=STORELR; break;
6536 case 0x2F: set_mnemonic(i, "CACHE"); type=NOP; break;
6537 case 0x30: set_mnemonic(i, "LL"); type=NI; break;
6538 case 0x31: set_mnemonic(i, "LWC1"); type=C1LS; break;
6540 case 0x34: set_mnemonic(i, "LLD"); type=NI; break;
6541 case 0x35: set_mnemonic(i, "LDC1"); type=C1LS; break;
6542 case 0x37: set_mnemonic(i, "LD"); type=LOAD; break;
6544 case 0x38: set_mnemonic(i, "SC"); type=NI; break;
6545 case 0x39: set_mnemonic(i, "SWC1"); type=C1LS; break;
6547 case 0x3C: set_mnemonic(i, "SCD"); type=NI; break;
6548 case 0x3D: set_mnemonic(i, "SDC1"); type=C1LS; break;
6549 case 0x3F: set_mnemonic(i, "SD"); type=STORE; break;
6551 case 0x12: set_mnemonic(i, "COP2"); type=NI;
6552 op2=(source[i]>>21)&0x1f;
6554 if (source[i]&0x3f) { // use this hack to support old savestates with patched gte insns
6555 if (gte_handlers[source[i]&0x3f]!=NULL) {
6557 if (gte_regnames[source[i]&0x3f]!=NULL)
6558 strcpy(insn[i],gte_regnames[source[i]&0x3f]);
6560 snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
6567 case 0x00: set_mnemonic(i, "MFC2"); type=COP2; break;
6568 case 0x02: set_mnemonic(i, "CFC2"); type=COP2; break;
6569 case 0x04: set_mnemonic(i, "MTC2"); type=COP2; break;
6570 case 0x06: set_mnemonic(i, "CTC2"); type=COP2; break;
6573 case 0x32: set_mnemonic(i, "LWC2"); type=C2LS; break;
6574 case 0x3A: set_mnemonic(i, "SWC2"); type=C2LS; break;
6575 case 0x3B: set_mnemonic(i, "HLECALL"); type=HLECALL; break;
6576 default: set_mnemonic(i, "???"); type=NI;
6577 SysPrintf("NI %08x @%08x (%08x)\n", source[i], start + i*4, start);
6581 dops[i].opcode2=op2;
6582 /* Get registers/immediates */
6584 gte_rs[i]=gte_rt[i]=0;
6587 dops[i].rs1=(source[i]>>21)&0x1f;
6589 dops[i].rt1=(source[i]>>16)&0x1f;
6591 imm[i]=(short)source[i];
6595 dops[i].rs1=(source[i]>>21)&0x1f;
6596 dops[i].rs2=(source[i]>>16)&0x1f;
6599 imm[i]=(short)source[i];
6602 // LWL/LWR only load part of the register,
6603 // therefore the target register must be treated as a source too
6604 dops[i].rs1=(source[i]>>21)&0x1f;
6605 dops[i].rs2=(source[i]>>16)&0x1f;
6606 dops[i].rt1=(source[i]>>16)&0x1f;
6608 imm[i]=(short)source[i];
6611 if (op==0x0f) dops[i].rs1=0; // LUI instruction has no source register
6612 else dops[i].rs1=(source[i]>>21)&0x1f;
6614 dops[i].rt1=(source[i]>>16)&0x1f;
6616 if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
6617 imm[i]=(unsigned short)source[i];
6619 imm[i]=(short)source[i];
6627 // The JAL instruction writes to r31.
6634 dops[i].rs1=(source[i]>>21)&0x1f;
6638 // The JALR instruction writes to rd.
6640 dops[i].rt1=(source[i]>>11)&0x1f;
6645 dops[i].rs1=(source[i]>>21)&0x1f;
6646 dops[i].rs2=(source[i]>>16)&0x1f;
6649 if(op&2) { // BGTZ/BLEZ
6654 dops[i].rs1=(source[i]>>21)&0x1f;
6658 if(op2&0x10) { // BxxAL
6660 // NOTE: If the branch is not taken, r31 is still overwritten
6664 dops[i].rs1=(source[i]>>21)&0x1f; // source
6665 dops[i].rs2=(source[i]>>16)&0x1f; // subtract amount
6666 dops[i].rt1=(source[i]>>11)&0x1f; // destination
6670 dops[i].rs1=(source[i]>>21)&0x1f; // source
6671 dops[i].rs2=(source[i]>>16)&0x1f; // divisor
6680 if(op2==0x10) dops[i].rs1=HIREG; // MFHI
6681 if(op2==0x11) dops[i].rt1=HIREG; // MTHI
6682 if(op2==0x12) dops[i].rs1=LOREG; // MFLO
6683 if(op2==0x13) dops[i].rt1=LOREG; // MTLO
6684 if((op2&0x1d)==0x10) dops[i].rt1=(source[i]>>11)&0x1f; // MFxx
6685 if((op2&0x1d)==0x11) dops[i].rs1=(source[i]>>21)&0x1f; // MTxx
6688 dops[i].rs1=(source[i]>>16)&0x1f; // target of shift
6689 dops[i].rs2=(source[i]>>21)&0x1f; // shift amount
6690 dops[i].rt1=(source[i]>>11)&0x1f; // destination
6694 dops[i].rs1=(source[i]>>16)&0x1f;
6696 dops[i].rt1=(source[i]>>11)&0x1f;
6698 imm[i]=(source[i]>>6)&0x1f;
6699 // DSxx32 instructions
6700 if(op2>=0x3c) imm[i]|=0x20;
6707 if(op2==0||op2==2) dops[i].rt1=(source[i]>>16)&0x1F; // MFC0/CFC0
6708 if(op2==4||op2==6) dops[i].rs1=(source[i]>>16)&0x1F; // MTC0/CTC0
6709 if(op2==4&&((source[i]>>11)&0x1f)==12) dops[i].rt2=CSREG; // Status
6710 if(op2==16) if((source[i]&0x3f)==0x18) dops[i].rs2=CCREG; // ERET
6717 if(op2<3) dops[i].rt1=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
6718 if(op2>3) dops[i].rs1=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
6726 if(op2<3) dops[i].rt1=(source[i]>>16)&0x1F; // MFC2/CFC2
6727 if(op2>3) dops[i].rs1=(source[i]>>16)&0x1F; // MTC2/CTC2
6729 int gr=(source[i]>>11)&0x1F;
6732 case 0x00: gte_rs[i]=1ll<<gr; break; // MFC2
6733 case 0x04: gte_rt[i]=1ll<<gr; break; // MTC2
6734 case 0x02: gte_rs[i]=1ll<<(gr+32); break; // CFC2
6735 case 0x06: gte_rt[i]=1ll<<(gr+32); break; // CTC2
6739 dops[i].rs1=(source[i]>>21)&0x1F;
6743 imm[i]=(short)source[i];
6746 dops[i].rs1=(source[i]>>21)&0x1F;
6750 imm[i]=(short)source[i];
6751 if(op==0x32) gte_rt[i]=1ll<<((source[i]>>16)&0x1F); // LWC2
6752 else gte_rs[i]=1ll<<((source[i]>>16)&0x1F); // SWC2
6759 gte_rs[i]=gte_reg_reads[source[i]&0x3f];
6760 gte_rt[i]=gte_reg_writes[source[i]&0x3f];
6761 gte_rt[i]|=1ll<<63; // every op changes flags
6762 if((source[i]&0x3f)==GTE_MVMVA) {
6763 int v = (source[i] >> 15) & 3;
6764 gte_rs[i]&=~0xe3fll;
6765 if(v==3) gte_rs[i]|=0xe00ll;
6766 else gte_rs[i]|=3ll<<(v*2);
6783 /* Calculate branch target addresses */
6785 ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
6786 else if(type==CJUMP&&dops[i].rs1==dops[i].rs2&&(op&1))
6787 ba[i]=start+i*4+8; // Ignore never taken branch
6788 else if(type==SJUMP&&dops[i].rs1==0&&!(op2&1))
6789 ba[i]=start+i*4+8; // Ignore never taken branch
6790 else if(type==CJUMP||type==SJUMP)
6791 ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
6794 /* simplify always (not)taken branches */
6795 if (type == CJUMP && dops[i].rs1 == dops[i].rs2) {
6796 dops[i].rs1 = dops[i].rs2 = 0;
6798 dops[i].itype = type = UJUMP;
6799 dops[i].rs2 = CCREG;
6802 else if (type == SJUMP && dops[i].rs1 == 0 && (op2 & 1))
6803 dops[i].itype = type = UJUMP;
6805 dops[i].is_jump = (dops[i].itype == RJUMP || dops[i].itype == UJUMP || dops[i].itype == CJUMP || dops[i].itype == SJUMP);
6806 dops[i].is_ujump = (dops[i].itype == RJUMP || dops[i].itype == UJUMP); // || (source[i] >> 16) == 0x1000 // beq r0,r0
6807 dops[i].is_load = (dops[i].itype == LOAD || dops[i].itype == LOADLR || op == 0x32); // LWC2
6808 dops[i].is_store = (dops[i].itype == STORE || dops[i].itype == STORELR || op == 0x3a); // SWC2
6810 /* messy cases to just pass over to the interpreter */
6811 if (i > 0 && dops[i-1].is_jump) {
6813 // branch in delay slot?
6814 if (dops[i].is_jump) {
6815 // don't handle first branch and call interpreter if it's hit
6816 SysPrintf("branch in delay slot @%08x (%08x)\n", start + i*4, start);
6819 // basic load delay detection
6820 else if((type==LOAD||type==LOADLR||type==COP0||type==COP2||type==C2LS)&&dops[i].rt1!=0) {
6821 int t=(ba[i-1]-start)/4;
6822 if(0 <= t && t < i &&(dops[i].rt1==dops[t].rs1||dops[i].rt1==dops[t].rs2)&&dops[t].itype!=CJUMP&&dops[t].itype!=SJUMP) {
6823 // jump target wants DS result - potential load delay effect
6824 SysPrintf("load delay @%08x (%08x)\n", start + i*4, start);
6826 dops[t+1].bt=1; // expected return from interpreter
6828 else if(i>=2&&dops[i-2].rt1==2&&dops[i].rt1==2&&dops[i].rs1!=2&&dops[i].rs2!=2&&dops[i-1].rs1!=2&&dops[i-1].rs2!=2&&
6829 !(i>=3&&dops[i-3].is_jump)) {
6830 // v0 overwrite like this is a sign of trouble, bail out
6831 SysPrintf("v0 overwrite @%08x (%08x)\n", start + i*4, start);
6836 memset(&dops[i-1], 0, sizeof(dops[i-1]));
6837 dops[i-1].itype = INTCALL;
6838 dops[i-1].rs1 = CCREG;
6841 i--; // don't compile the DS
6845 /* Is this the end of the block? */
6846 if (i > 0 && dops[i-1].is_ujump) {
6847 if (dops[i-1].rt1 == 0) { // not jal
6848 int found_bbranch = 0, t = (ba[i-1] - start) / 4;
6849 if ((u_int)(t - i) < 64 && start + (t+64)*4 < pagelimit) {
6850 // scan for a branch back to i+1
6851 for (j = t; j < t + 64; j++) {
6852 int tmpop = source[j] >> 26;
6853 if (tmpop == 1 || ((tmpop & ~3) == 4)) {
6854 int t2 = j + 1 + (int)(signed short)source[j];
6856 //printf("blk expand %08x<-%08x\n", start + (i+1)*4, start + j*4);
6867 if(stop_after_jal) done=1;
6869 if((source[i+1]&0xfc00003f)==0x0d) done=1;
6871 // Don't recompile stuff that's already compiled
6872 if(check_addr(start+i*4+4)) done=1;
6873 // Don't get too close to the limit
6874 if(i>MAXBLOCK/2) done=1;
6876 if (dops[i].itype == SYSCALL || dops[i].itype == HLECALL || dops[i].itype == INTCALL)
6877 done = stop_after_jal ? 1 : 2;
6879 // Does the block continue due to a branch?
6882 if(ba[j]==start+i*4) done=j=0; // Branch into delay slot
6883 if(ba[j]==start+i*4+4) done=j=0;
6884 if(ba[j]==start+i*4+8) done=j=0;
6887 //assert(i<MAXBLOCK-1);
6888 if(start+i*4==pagelimit-4) done=1;
6889 assert(start+i*4<pagelimit);
6890 if (i==MAXBLOCK-1) done=1;
6891 // Stop if we're compiling junk
6892 if(dops[i].itype == NI && (++ni_count > 8 || dops[i].opcode == 0x11)) {
6893 done=stop_after_jal=1;
6894 SysPrintf("Disabled speculative precompilation\n");
6897 while (i > 0 && dops[i-1].is_jump)
6900 assert(!dops[i-1].is_jump);
6904 // Basic liveness analysis for MIPS registers
6905 static noinline void pass2_unneeded_regs(int istart,int iend,int r)
6908 uint64_t u,gte_u,b,gte_b;
6909 uint64_t temp_u,temp_gte_u=0;
6910 uint64_t gte_u_unknown=0;
6911 if (HACK_ENABLED(NDHACK_GTE_UNNEEDED))
6915 gte_u=gte_u_unknown;
6917 //u=unneeded_reg[iend+1];
6919 gte_u=gte_unneeded[iend+1];
6922 for (i=iend;i>=istart;i--)
6924 //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
6927 // If subroutine call, flag return address as a possible branch target
6928 if(dops[i].rt1==31 && i<slen-2) dops[i+2].bt=1;
6930 if(ba[i]<start || ba[i]>=(start+slen*4))
6932 // Branch out of this block, flush all regs
6934 gte_u=gte_u_unknown;
6935 branch_unneeded_reg[i]=u;
6936 // Merge in delay slot
6937 u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
6938 u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
6941 gte_u&=~gte_rs[i+1];
6945 // Internal branch, flag target
6946 dops[(ba[i]-start)>>2].bt=1;
6947 if(ba[i]<=start+i*4) {
6949 if(dops[i].is_ujump)
6951 // Unconditional branch
6955 // Conditional branch (not taken case)
6956 temp_u=unneeded_reg[i+2];
6957 temp_gte_u&=gte_unneeded[i+2];
6959 // Merge in delay slot
6960 temp_u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
6961 temp_u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
6963 temp_gte_u|=gte_rt[i+1];
6964 temp_gte_u&=~gte_rs[i+1];
6965 temp_u|=(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2);
6966 temp_u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
6968 temp_gte_u|=gte_rt[i];
6969 temp_gte_u&=~gte_rs[i];
6970 unneeded_reg[i]=temp_u;
6971 gte_unneeded[i]=temp_gte_u;
6972 // Only go three levels deep. This recursion can take an
6973 // excessive amount of time if there are a lot of nested loops.
6975 pass2_unneeded_regs((ba[i]-start)>>2,i-1,r+1);
6977 unneeded_reg[(ba[i]-start)>>2]=1;
6978 gte_unneeded[(ba[i]-start)>>2]=gte_u_unknown;
6981 if (dops[i].is_ujump)
6983 // Unconditional branch
6984 u=unneeded_reg[(ba[i]-start)>>2];
6985 gte_u=gte_unneeded[(ba[i]-start)>>2];
6986 branch_unneeded_reg[i]=u;
6987 // Merge in delay slot
6988 u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
6989 u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
6992 gte_u&=~gte_rs[i+1];
6994 // Conditional branch
6995 b=unneeded_reg[(ba[i]-start)>>2];
6996 gte_b=gte_unneeded[(ba[i]-start)>>2];
6997 branch_unneeded_reg[i]=b;
6998 // Branch delay slot
6999 b|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
7000 b&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7003 gte_b&=~gte_rs[i+1];
7007 branch_unneeded_reg[i]&=unneeded_reg[i+2];
7009 branch_unneeded_reg[i]=1;
7015 else if(dops[i].itype==SYSCALL||dops[i].itype==HLECALL||dops[i].itype==INTCALL)
7017 // SYSCALL instruction (software interrupt)
7020 else if(dops[i].itype==COP0 && (source[i]&0x3f)==0x18)
7022 // ERET instruction (return from interrupt)
7026 // Written registers are unneeded
7027 u|=1LL<<dops[i].rt1;
7028 u|=1LL<<dops[i].rt2;
7030 // Accessed registers are needed
7031 u&=~(1LL<<dops[i].rs1);
7032 u&=~(1LL<<dops[i].rs2);
7034 if(gte_rs[i]&&dops[i].rt1&&(unneeded_reg[i+1]&(1ll<<dops[i].rt1)))
7035 gte_u|=gte_rs[i]>e_unneeded[i+1]; // MFC2/CFC2 to dead register, unneeded
7036 // Source-target dependencies
7037 // R0 is always unneeded
7041 gte_unneeded[i]=gte_u;
7043 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
7046 for(r=1;r<=CCREG;r++) {
7047 if((unneeded_reg[i]>>r)&1) {
7048 if(r==HIREG) printf(" HI");
7049 else if(r==LOREG) printf(" LO");
7050 else printf(" r%d",r);
7058 static noinline void pass3_register_alloc(u_int addr)
7060 struct regstat current; // Current register allocations/status
7061 clear_all_regs(current.regmap_entry);
7062 clear_all_regs(current.regmap);
7063 current.wasdirty = current.dirty = 0;
7064 current.u = unneeded_reg[0];
7065 alloc_reg(¤t, 0, CCREG);
7066 dirty_reg(¤t, CCREG);
7067 current.wasconst = 0;
7068 current.isconst = 0;
7069 current.loadedconst = 0;
7070 current.waswritten = 0;
7077 // First instruction is delay slot
7082 current.regmap[HOST_BTREG]=BTREG;
7089 for(hr=0;hr<HOST_REGS;hr++)
7091 // Is this really necessary?
7092 if(current.regmap[hr]==0) current.regmap[hr]=-1;
7095 current.waswritten=0;
7098 memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
7099 regs[i].wasconst=current.isconst;
7100 regs[i].wasdirty=current.dirty;
7104 regs[i].loadedconst=0;
7105 if (!dops[i].is_jump) {
7107 current.u=unneeded_reg[i+1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7114 current.u=branch_unneeded_reg[i]&~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7115 current.u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7118 SysPrintf("oops, branch at end of block with no delay slot @%08x\n", start + i*4);
7124 ds=0; // Skip delay slot, already allocated as part of branch
7125 // ...but we need to alloc it in case something jumps here
7127 current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
7129 current.u=branch_unneeded_reg[i-1];
7131 current.u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7133 struct regstat temp;
7134 memcpy(&temp,¤t,sizeof(current));
7135 temp.wasdirty=temp.dirty;
7136 // TODO: Take into account unconditional branches, as below
7137 delayslot_alloc(&temp,i);
7138 memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
7139 regs[i].wasdirty=temp.wasdirty;
7140 regs[i].dirty=temp.dirty;
7144 // Create entry (branch target) regmap
7145 for(hr=0;hr<HOST_REGS;hr++)
7147 int r=temp.regmap[hr];
7149 if(r!=regmap_pre[i][hr]) {
7150 regs[i].regmap_entry[hr]=-1;
7155 if((current.u>>r)&1) {
7156 regs[i].regmap_entry[hr]=-1;
7157 regs[i].regmap[hr]=-1;
7158 //Don't clear regs in the delay slot as the branch might need them
7159 //current.regmap[hr]=-1;
7161 regs[i].regmap_entry[hr]=r;
7164 // First instruction expects CCREG to be allocated
7165 if(i==0&&hr==HOST_CCREG)
7166 regs[i].regmap_entry[hr]=CCREG;
7168 regs[i].regmap_entry[hr]=-1;
7172 else { // Not delay slot
7173 switch(dops[i].itype) {
7175 //current.isconst=0; // DEBUG
7176 //current.wasconst=0; // DEBUG
7177 //regs[i].wasconst=0; // DEBUG
7178 clear_const(¤t,dops[i].rt1);
7179 alloc_cc(¤t,i);
7180 dirty_reg(¤t,CCREG);
7181 if (dops[i].rt1==31) {
7182 alloc_reg(¤t,i,31);
7183 dirty_reg(¤t,31);
7184 //assert(dops[i+1].rs1!=31&&dops[i+1].rs2!=31);
7185 //assert(dops[i+1].rt1!=dops[i].rt1);
7187 alloc_reg(¤t,i,PTEMP);
7191 delayslot_alloc(¤t,i+1);
7192 //current.isconst=0; // DEBUG
7194 //printf("i=%d, isconst=%x\n",i,current.isconst);
7197 //current.isconst=0;
7198 //current.wasconst=0;
7199 //regs[i].wasconst=0;
7200 clear_const(¤t,dops[i].rs1);
7201 clear_const(¤t,dops[i].rt1);
7202 alloc_cc(¤t,i);
7203 dirty_reg(¤t,CCREG);
7204 if (!ds_writes_rjump_rs(i)) {
7205 alloc_reg(¤t,i,dops[i].rs1);
7206 if (dops[i].rt1!=0) {
7207 alloc_reg(¤t,i,dops[i].rt1);
7208 dirty_reg(¤t,dops[i].rt1);
7209 assert(dops[i+1].rs1!=dops[i].rt1&&dops[i+1].rs2!=dops[i].rt1);
7210 assert(dops[i+1].rt1!=dops[i].rt1);
7212 alloc_reg(¤t,i,PTEMP);
7216 if(dops[i].rs1==31) { // JALR
7217 alloc_reg(¤t,i,RHASH);
7218 alloc_reg(¤t,i,RHTBL);
7221 delayslot_alloc(¤t,i+1);
7223 // The delay slot overwrites our source register,
7224 // allocate a temporary register to hold the old value.
7228 delayslot_alloc(¤t,i+1);
7230 alloc_reg(¤t,i,RTEMP);
7232 //current.isconst=0; // DEBUG
7237 //current.isconst=0;
7238 //current.wasconst=0;
7239 //regs[i].wasconst=0;
7240 clear_const(¤t,dops[i].rs1);
7241 clear_const(¤t,dops[i].rs2);
7242 if((dops[i].opcode&0x3E)==4) // BEQ/BNE
7244 alloc_cc(¤t,i);
7245 dirty_reg(¤t,CCREG);
7246 if(dops[i].rs1) alloc_reg(¤t,i,dops[i].rs1);
7247 if(dops[i].rs2) alloc_reg(¤t,i,dops[i].rs2);
7248 if((dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2))||
7249 (dops[i].rs2&&(dops[i].rs2==dops[i+1].rt1||dops[i].rs2==dops[i+1].rt2))) {
7250 // The delay slot overwrites one of our conditions.
7251 // Allocate the branch condition registers instead.
7255 if(dops[i].rs1) alloc_reg(¤t,i,dops[i].rs1);
7256 if(dops[i].rs2) alloc_reg(¤t,i,dops[i].rs2);
7261 delayslot_alloc(¤t,i+1);
7265 if((dops[i].opcode&0x3E)==6) // BLEZ/BGTZ
7267 alloc_cc(¤t,i);
7268 dirty_reg(¤t,CCREG);
7269 alloc_reg(¤t,i,dops[i].rs1);
7270 if(dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2)) {
7271 // The delay slot overwrites one of our conditions.
7272 // Allocate the branch condition registers instead.
7276 if(dops[i].rs1) alloc_reg(¤t,i,dops[i].rs1);
7281 delayslot_alloc(¤t,i+1);
7285 // Don't alloc the delay slot yet because we might not execute it
7286 if((dops[i].opcode&0x3E)==0x14) // BEQL/BNEL
7291 alloc_cc(¤t,i);
7292 dirty_reg(¤t,CCREG);
7293 alloc_reg(¤t,i,dops[i].rs1);
7294 alloc_reg(¤t,i,dops[i].rs2);
7297 if((dops[i].opcode&0x3E)==0x16) // BLEZL/BGTZL
7302 alloc_cc(¤t,i);
7303 dirty_reg(¤t,CCREG);
7304 alloc_reg(¤t,i,dops[i].rs1);
7307 //current.isconst=0;
7310 //current.isconst=0;
7311 //current.wasconst=0;
7312 //regs[i].wasconst=0;
7313 clear_const(¤t,dops[i].rs1);
7314 clear_const(¤t,dops[i].rt1);
7315 //if((dops[i].opcode2&0x1E)==0x0) // BLTZ/BGEZ
7316 if((dops[i].opcode2&0x0E)==0x0) // BLTZ/BGEZ
7318 alloc_cc(¤t,i);
7319 dirty_reg(¤t,CCREG);
7320 alloc_reg(¤t,i,dops[i].rs1);
7321 if (dops[i].rt1==31) { // BLTZAL/BGEZAL
7322 alloc_reg(¤t,i,31);
7323 dirty_reg(¤t,31);
7324 //#ifdef REG_PREFETCH
7325 //alloc_reg(¤t,i,PTEMP);
7328 if((dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2)) // The delay slot overwrites the branch condition.
7329 ||(dops[i].rt1==31&&(dops[i+1].rs1==31||dops[i+1].rs2==31||dops[i+1].rt1==31||dops[i+1].rt2==31))) { // DS touches $ra
7330 // Allocate the branch condition registers instead.
7334 if(dops[i].rs1) alloc_reg(¤t,i,dops[i].rs1);
7339 delayslot_alloc(¤t,i+1);
7343 // Don't alloc the delay slot yet because we might not execute it
7344 if((dops[i].opcode2&0x1E)==0x2) // BLTZL/BGEZL
7349 alloc_cc(¤t,i);
7350 dirty_reg(¤t,CCREG);
7351 alloc_reg(¤t,i,dops[i].rs1);
7354 //current.isconst=0;
7357 imm16_alloc(¤t,i);
7361 load_alloc(¤t,i);
7365 store_alloc(¤t,i);
7368 alu_alloc(¤t,i);
7371 shift_alloc(¤t,i);
7374 multdiv_alloc(¤t,i);
7377 shiftimm_alloc(¤t,i);
7380 mov_alloc(¤t,i);
7383 cop0_alloc(¤t,i);
7388 cop2_alloc(¤t,i);
7391 c1ls_alloc(¤t,i);
7394 c2ls_alloc(¤t,i);
7397 c2op_alloc(¤t,i);
7402 syscall_alloc(¤t,i);
7406 // Create entry (branch target) regmap
7407 for(hr=0;hr<HOST_REGS;hr++)
7410 r=current.regmap[hr];
7412 if(r!=regmap_pre[i][hr]) {
7413 // TODO: delay slot (?)
7414 or=get_reg(regmap_pre[i],r); // Get old mapping for this register
7415 if(or<0||r>=TEMPREG){
7416 regs[i].regmap_entry[hr]=-1;
7420 // Just move it to a different register
7421 regs[i].regmap_entry[hr]=r;
7422 // If it was dirty before, it's still dirty
7423 if((regs[i].wasdirty>>or)&1) dirty_reg(¤t,r);
7430 regs[i].regmap_entry[hr]=0;
7435 if((current.u>>r)&1) {
7436 regs[i].regmap_entry[hr]=-1;
7437 //regs[i].regmap[hr]=-1;
7438 current.regmap[hr]=-1;
7440 regs[i].regmap_entry[hr]=r;
7444 // Branches expect CCREG to be allocated at the target
7445 if(regmap_pre[i][hr]==CCREG)
7446 regs[i].regmap_entry[hr]=CCREG;
7448 regs[i].regmap_entry[hr]=-1;
7451 memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
7454 if(i>0&&(dops[i-1].itype==STORE||dops[i-1].itype==STORELR||(dops[i-1].itype==C2LS&&dops[i-1].opcode==0x3a))&&(u_int)imm[i-1]<0x800)
7455 current.waswritten|=1<<dops[i-1].rs1;
7456 current.waswritten&=~(1<<dops[i].rt1);
7457 current.waswritten&=~(1<<dops[i].rt2);
7458 if((dops[i].itype==STORE||dops[i].itype==STORELR||(dops[i].itype==C2LS&&dops[i].opcode==0x3a))&&(u_int)imm[i]>=0x800)
7459 current.waswritten&=~(1<<dops[i].rs1);
7461 /* Branch post-alloc */
7464 current.wasdirty=current.dirty;
7465 switch(dops[i-1].itype) {
7467 memcpy(&branch_regs[i-1],¤t,sizeof(current));
7468 branch_regs[i-1].isconst=0;
7469 branch_regs[i-1].wasconst=0;
7470 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
7471 alloc_cc(&branch_regs[i-1],i-1);
7472 dirty_reg(&branch_regs[i-1],CCREG);
7473 if(dops[i-1].rt1==31) { // JAL
7474 alloc_reg(&branch_regs[i-1],i-1,31);
7475 dirty_reg(&branch_regs[i-1],31);
7477 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
7478 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
7481 memcpy(&branch_regs[i-1],¤t,sizeof(current));
7482 branch_regs[i-1].isconst=0;
7483 branch_regs[i-1].wasconst=0;
7484 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
7485 alloc_cc(&branch_regs[i-1],i-1);
7486 dirty_reg(&branch_regs[i-1],CCREG);
7487 alloc_reg(&branch_regs[i-1],i-1,dops[i-1].rs1);
7488 if(dops[i-1].rt1!=0) { // JALR
7489 alloc_reg(&branch_regs[i-1],i-1,dops[i-1].rt1);
7490 dirty_reg(&branch_regs[i-1],dops[i-1].rt1);
7493 if(dops[i-1].rs1==31) { // JALR
7494 alloc_reg(&branch_regs[i-1],i-1,RHASH);
7495 alloc_reg(&branch_regs[i-1],i-1,RHTBL);
7498 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
7499 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
7502 if((dops[i-1].opcode&0x3E)==4) // BEQ/BNE
7504 alloc_cc(¤t,i-1);
7505 dirty_reg(¤t,CCREG);
7506 if((dops[i-1].rs1&&(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2))||
7507 (dops[i-1].rs2&&(dops[i-1].rs2==dops[i].rt1||dops[i-1].rs2==dops[i].rt2))) {
7508 // The delay slot overwrote one of our conditions
7509 // Delay slot goes after the test (in order)
7510 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7512 delayslot_alloc(¤t,i);
7517 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
7518 // Alloc the branch condition registers
7519 if(dops[i-1].rs1) alloc_reg(¤t,i-1,dops[i-1].rs1);
7520 if(dops[i-1].rs2) alloc_reg(¤t,i-1,dops[i-1].rs2);
7522 memcpy(&branch_regs[i-1],¤t,sizeof(current));
7523 branch_regs[i-1].isconst=0;
7524 branch_regs[i-1].wasconst=0;
7525 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
7526 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
7529 if((dops[i-1].opcode&0x3E)==6) // BLEZ/BGTZ
7531 alloc_cc(¤t,i-1);
7532 dirty_reg(¤t,CCREG);
7533 if(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2) {
7534 // The delay slot overwrote the branch condition
7535 // Delay slot goes after the test (in order)
7536 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7538 delayslot_alloc(¤t,i);
7543 current.u=branch_unneeded_reg[i-1]&~(1LL<<dops[i-1].rs1);
7544 // Alloc the branch condition register
7545 alloc_reg(¤t,i-1,dops[i-1].rs1);
7547 memcpy(&branch_regs[i-1],¤t,sizeof(current));
7548 branch_regs[i-1].isconst=0;
7549 branch_regs[i-1].wasconst=0;
7550 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
7551 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
7554 // Alloc the delay slot in case the branch is taken
7555 if((dops[i-1].opcode&0x3E)==0x14) // BEQL/BNEL
7557 memcpy(&branch_regs[i-1],¤t,sizeof(current));
7558 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)|(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2)))|1;
7559 alloc_cc(&branch_regs[i-1],i);
7560 dirty_reg(&branch_regs[i-1],CCREG);
7561 delayslot_alloc(&branch_regs[i-1],i);
7562 branch_regs[i-1].isconst=0;
7563 alloc_reg(¤t,i,CCREG); // Not taken path
7564 dirty_reg(¤t,CCREG);
7565 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
7568 if((dops[i-1].opcode&0x3E)==0x16) // BLEZL/BGTZL
7570 memcpy(&branch_regs[i-1],¤t,sizeof(current));
7571 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)|(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2)))|1;
7572 alloc_cc(&branch_regs[i-1],i);
7573 dirty_reg(&branch_regs[i-1],CCREG);
7574 delayslot_alloc(&branch_regs[i-1],i);
7575 branch_regs[i-1].isconst=0;
7576 alloc_reg(¤t,i,CCREG); // Not taken path
7577 dirty_reg(¤t,CCREG);
7578 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
7582 //if((dops[i-1].opcode2&0x1E)==0) // BLTZ/BGEZ
7583 if((dops[i-1].opcode2&0x0E)==0) // BLTZ/BGEZ
7585 alloc_cc(¤t,i-1);
7586 dirty_reg(¤t,CCREG);
7587 if(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2) {
7588 // The delay slot overwrote the branch condition
7589 // Delay slot goes after the test (in order)
7590 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7592 delayslot_alloc(¤t,i);
7597 current.u=branch_unneeded_reg[i-1]&~(1LL<<dops[i-1].rs1);
7598 // Alloc the branch condition register
7599 alloc_reg(¤t,i-1,dops[i-1].rs1);
7601 memcpy(&branch_regs[i-1],¤t,sizeof(current));
7602 branch_regs[i-1].isconst=0;
7603 branch_regs[i-1].wasconst=0;
7604 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
7605 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
7608 // Alloc the delay slot in case the branch is taken
7609 if((dops[i-1].opcode2&0x1E)==2) // BLTZL/BGEZL
7611 memcpy(&branch_regs[i-1],¤t,sizeof(current));
7612 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)|(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2)))|1;
7613 alloc_cc(&branch_regs[i-1],i);
7614 dirty_reg(&branch_regs[i-1],CCREG);
7615 delayslot_alloc(&branch_regs[i-1],i);
7616 branch_regs[i-1].isconst=0;
7617 alloc_reg(¤t,i,CCREG); // Not taken path
7618 dirty_reg(¤t,CCREG);
7619 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
7621 // FIXME: BLTZAL/BGEZAL
7622 if(dops[i-1].opcode2&0x10) { // BxxZAL
7623 alloc_reg(&branch_regs[i-1],i-1,31);
7624 dirty_reg(&branch_regs[i-1],31);
7629 if (dops[i-1].is_ujump)
7631 if(dops[i-1].rt1==31) // JAL/JALR
7633 // Subroutine call will return here, don't alloc any registers
7635 clear_all_regs(current.regmap);
7636 alloc_reg(¤t,i,CCREG);
7637 dirty_reg(¤t,CCREG);
7641 // Internal branch will jump here, match registers to caller
7643 clear_all_regs(current.regmap);
7644 alloc_reg(¤t,i,CCREG);
7645 dirty_reg(¤t,CCREG);
7648 if(ba[j]==start+i*4+4) {
7649 memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
7650 current.dirty=branch_regs[j].dirty;
7655 if(ba[j]==start+i*4+4) {
7656 for(hr=0;hr<HOST_REGS;hr++) {
7657 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
7658 current.regmap[hr]=-1;
7660 current.dirty&=branch_regs[j].dirty;
7669 // Count cycles in between branches
7670 ccadj[i] = CLOCK_ADJUST(cc);
7671 if (i > 0 && (dops[i-1].is_jump || dops[i].itype == SYSCALL || dops[i].itype == HLECALL))
7675 #if !defined(DRC_DBG)
7676 else if(dops[i].itype==C2OP&>e_cycletab[source[i]&0x3f]>2)
7678 // this should really be removed since the real stalls have been implemented,
7679 // but doing so causes sizeable perf regression against the older version
7680 u_int gtec = gte_cycletab[source[i] & 0x3f];
7681 cc += HACK_ENABLED(NDHACK_NO_STALLS) ? gtec/2 : 2;
7683 else if(i>1&&dops[i].itype==STORE&&dops[i-1].itype==STORE&&dops[i-2].itype==STORE&&!dops[i].bt)
7687 else if(dops[i].itype==C2LS)
7689 // same as with C2OP
7690 cc += HACK_ENABLED(NDHACK_NO_STALLS) ? 4 : 2;
7698 if(!dops[i].is_ds) {
7699 regs[i].dirty=current.dirty;
7700 regs[i].isconst=current.isconst;
7701 memcpy(constmap[i],current_constmap,sizeof(constmap[i]));
7703 for(hr=0;hr<HOST_REGS;hr++) {
7704 if(hr!=EXCLUDE_REG&®s[i].regmap[hr]>=0) {
7705 if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
7706 regs[i].wasconst&=~(1<<hr);
7710 if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
7711 regs[i].waswritten=current.waswritten;
7715 static noinline void pass4_cull_unused_regs(void)
7717 u_int last_needed_regs[4] = {0,0,0,0};
7721 for (i=slen-1;i>=0;i--)
7724 __builtin_prefetch(regs[i-2].regmap);
7727 if(ba[i]<start || ba[i]>=(start+slen*4))
7729 // Branch out of this block, don't need anything
7735 // Need whatever matches the target
7737 int t=(ba[i]-start)>>2;
7738 for(hr=0;hr<HOST_REGS;hr++)
7740 if(regs[i].regmap_entry[hr]>=0) {
7741 if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
7745 // Conditional branch may need registers for following instructions
7746 if (!dops[i].is_ujump)
7749 nr |= last_needed_regs[(i+2) & 3];
7750 for(hr=0;hr<HOST_REGS;hr++)
7752 if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
7753 //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
7757 // Don't need stuff which is overwritten
7758 //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
7759 //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
7760 // Merge in delay slot
7761 if (dops[i+1].rt1) nr &= ~get_regm(regs[i].regmap, dops[i+1].rt1);
7762 if (dops[i+1].rt2) nr &= ~get_regm(regs[i].regmap, dops[i+1].rt2);
7763 nr |= get_regm(regmap_pre[i], dops[i+1].rs1);
7764 nr |= get_regm(regmap_pre[i], dops[i+1].rs2);
7765 nr |= get_regm(regs[i].regmap_entry, dops[i+1].rs1);
7766 nr |= get_regm(regs[i].regmap_entry, dops[i+1].rs2);
7767 if (ram_offset && (dops[i+1].is_load || dops[i+1].is_store)) {
7768 nr |= get_regm(regmap_pre[i], ROREG);
7769 nr |= get_regm(regs[i].regmap_entry, ROREG);
7771 if (dops[i+1].is_store) {
7772 nr |= get_regm(regmap_pre[i], INVCP);
7773 nr |= get_regm(regs[i].regmap_entry, INVCP);
7776 else if(dops[i].itype==SYSCALL||dops[i].itype==HLECALL||dops[i].itype==INTCALL)
7778 // SYSCALL instruction (software interrupt)
7781 else if(dops[i].itype==COP0 && (source[i]&0x3f)==0x18)
7783 // ERET instruction (return from interrupt)
7789 for(hr=0;hr<HOST_REGS;hr++) {
7790 if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
7791 if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
7792 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
7793 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
7797 // Overwritten registers are not needed
7798 if (dops[i].rt1) nr &= ~get_regm(regs[i].regmap, dops[i].rt1);
7799 if (dops[i].rt2) nr &= ~get_regm(regs[i].regmap, dops[i].rt2);
7800 nr &= ~get_regm(regs[i].regmap, FTEMP);
7801 // Source registers are needed
7802 nr |= get_regm(regmap_pre[i], dops[i].rs1);
7803 nr |= get_regm(regmap_pre[i], dops[i].rs2);
7804 nr |= get_regm(regs[i].regmap_entry, dops[i].rs1);
7805 nr |= get_regm(regs[i].regmap_entry, dops[i].rs2);
7806 if (ram_offset && (dops[i].is_load || dops[i].is_store)) {
7807 nr |= get_regm(regmap_pre[i], ROREG);
7808 nr |= get_regm(regs[i].regmap_entry, ROREG);
7810 if (dops[i].is_store) {
7811 nr |= get_regm(regmap_pre[i], INVCP);
7812 nr |= get_regm(regs[i].regmap_entry, INVCP);
7815 if (i > 0 && !dops[i].bt && regs[i].wasdirty)
7816 for(hr=0;hr<HOST_REGS;hr++)
7818 // Don't store a register immediately after writing it,
7819 // may prevent dual-issue.
7820 // But do so if this is a branch target, otherwise we
7821 // might have to load the register before the branch.
7822 if((regs[i].wasdirty>>hr)&1) {
7823 if((regmap_pre[i][hr]>0&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1))) {
7824 if(dops[i-1].rt1==regmap_pre[i][hr]) nr|=1<<hr;
7825 if(dops[i-1].rt2==regmap_pre[i][hr]) nr|=1<<hr;
7827 if((regs[i].regmap_entry[hr]>0&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1))) {
7828 if(dops[i-1].rt1==regs[i].regmap_entry[hr]) nr|=1<<hr;
7829 if(dops[i-1].rt2==regs[i].regmap_entry[hr]) nr|=1<<hr;
7833 // Cycle count is needed at branches. Assume it is needed at the target too.
7834 if(i==0||dops[i].bt||dops[i].itype==CJUMP) {
7835 if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
7836 if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
7839 last_needed_regs[i & 3] = nr;
7841 // Deallocate unneeded registers
7842 for(hr=0;hr<HOST_REGS;hr++)
7845 if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
7848 int map1 = 0, map2 = 0, temp = 0; // or -1 ??
7849 if (dops[i+1].is_load || dops[i+1].is_store)
7851 if (dops[i+1].is_store)
7853 if(dops[i+1].itype==LOADLR || dops[i+1].itype==STORELR || dops[i+1].itype==C2LS)
7855 if(regs[i].regmap[hr]!=dops[i].rs1 && regs[i].regmap[hr]!=dops[i].rs2 &&
7856 regs[i].regmap[hr]!=dops[i].rt1 && regs[i].regmap[hr]!=dops[i].rt2 &&
7857 regs[i].regmap[hr]!=dops[i+1].rt1 && regs[i].regmap[hr]!=dops[i+1].rt2 &&
7858 regs[i].regmap[hr]!=dops[i+1].rs1 && regs[i].regmap[hr]!=dops[i+1].rs2 &&
7859 regs[i].regmap[hr]!=temp && regs[i].regmap[hr]!=PTEMP &&
7860 regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
7861 regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
7862 regs[i].regmap[hr]!=map1 && regs[i].regmap[hr]!=map2)
7864 regs[i].regmap[hr]=-1;
7865 regs[i].isconst&=~(1<<hr);
7866 regs[i].dirty&=~(1<<hr);
7867 regs[i+1].wasdirty&=~(1<<hr);
7868 if(branch_regs[i].regmap[hr]!=dops[i].rs1 && branch_regs[i].regmap[hr]!=dops[i].rs2 &&
7869 branch_regs[i].regmap[hr]!=dops[i].rt1 && branch_regs[i].regmap[hr]!=dops[i].rt2 &&
7870 branch_regs[i].regmap[hr]!=dops[i+1].rt1 && branch_regs[i].regmap[hr]!=dops[i+1].rt2 &&
7871 branch_regs[i].regmap[hr]!=dops[i+1].rs1 && branch_regs[i].regmap[hr]!=dops[i+1].rs2 &&
7872 branch_regs[i].regmap[hr]!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
7873 branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
7874 branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
7875 branch_regs[i].regmap[hr]!=map1 && branch_regs[i].regmap[hr]!=map2)
7877 branch_regs[i].regmap[hr]=-1;
7878 branch_regs[i].regmap_entry[hr]=-1;
7879 if (!dops[i].is_ujump)
7882 regmap_pre[i+2][hr]=-1;
7883 regs[i+2].wasconst&=~(1<<hr);
7894 int map1 = -1, map2 = -1, temp=-1;
7895 if (dops[i].is_load || dops[i].is_store)
7897 if (dops[i].is_store)
7899 if (dops[i].itype==LOADLR || dops[i].itype==STORELR || dops[i].itype==C2LS)
7901 if(regs[i].regmap[hr]!=dops[i].rt1 && regs[i].regmap[hr]!=dops[i].rt2 &&
7902 regs[i].regmap[hr]!=dops[i].rs1 && regs[i].regmap[hr]!=dops[i].rs2 &&
7903 regs[i].regmap[hr]!=temp && regs[i].regmap[hr]!=map1 && regs[i].regmap[hr]!=map2 &&
7904 //(dops[i].itype!=SPAN||regs[i].regmap[hr]!=CCREG)
7905 regs[i].regmap[hr] != CCREG)
7907 if(i<slen-1&&!dops[i].is_ds) {
7908 assert(regs[i].regmap[hr]<64);
7909 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]>0)
7910 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
7912 SysPrintf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
7913 assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
7915 regmap_pre[i+1][hr]=-1;
7916 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
7917 regs[i+1].wasconst&=~(1<<hr);
7919 regs[i].regmap[hr]=-1;
7920 regs[i].isconst&=~(1<<hr);
7921 regs[i].dirty&=~(1<<hr);
7922 regs[i+1].wasdirty&=~(1<<hr);
7931 // If a register is allocated during a loop, try to allocate it for the
7932 // entire loop, if possible. This avoids loading/storing registers
7933 // inside of the loop.
7934 static noinline void pass5a_preallocate1(void)
7937 signed char f_regmap[HOST_REGS];
7938 clear_all_regs(f_regmap);
7939 for(i=0;i<slen-1;i++)
7941 if(dops[i].itype==UJUMP||dops[i].itype==CJUMP||dops[i].itype==SJUMP)
7943 if(ba[i]>=start && ba[i]<(start+i*4))
7944 if(dops[i+1].itype==NOP||dops[i+1].itype==MOV||dops[i+1].itype==ALU
7945 ||dops[i+1].itype==SHIFTIMM||dops[i+1].itype==IMM16||dops[i+1].itype==LOAD
7946 ||dops[i+1].itype==STORE||dops[i+1].itype==STORELR||dops[i+1].itype==C1LS
7947 ||dops[i+1].itype==SHIFT||dops[i+1].itype==COP1
7948 ||dops[i+1].itype==COP2||dops[i+1].itype==C2LS||dops[i+1].itype==C2OP)
7950 int t=(ba[i]-start)>>2;
7951 if(t > 0 && !dops[t-1].is_jump) // loop_preload can't handle jumps into delay slots
7952 if(t<2||(dops[t-2].itype!=UJUMP&&dops[t-2].itype!=RJUMP)||dops[t-2].rt1!=31) // call/ret assumes no registers allocated
7953 for(hr=0;hr<HOST_REGS;hr++)
7955 if(regs[i].regmap[hr]>=0) {
7956 if(f_regmap[hr]!=regs[i].regmap[hr]) {
7957 // dealloc old register
7959 for(n=0;n<HOST_REGS;n++)
7961 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
7963 // and alloc new one
7964 f_regmap[hr]=regs[i].regmap[hr];
7967 if(branch_regs[i].regmap[hr]>=0) {
7968 if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
7969 // dealloc old register
7971 for(n=0;n<HOST_REGS;n++)
7973 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
7975 // and alloc new one
7976 f_regmap[hr]=branch_regs[i].regmap[hr];
7980 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
7981 f_regmap[hr]=branch_regs[i].regmap[hr];
7983 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
7984 f_regmap[hr]=branch_regs[i].regmap[hr];
7986 // Avoid dirty->clean transition
7987 #ifdef DESTRUCTIVE_WRITEBACK
7988 if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
7990 // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
7991 // case above, however it's always a good idea. We can't hoist the
7992 // load if the register was already allocated, so there's no point
7993 // wasting time analyzing most of these cases. It only "succeeds"
7994 // when the mapping was different and the load can be replaced with
7995 // a mov, which is of negligible benefit. So such cases are
7997 if(f_regmap[hr]>0) {
7998 if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
8002 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
8003 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
8005 if(regs[j].regmap[hr]==f_regmap[hr]&&f_regmap[hr]<TEMPREG) {
8006 //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
8008 if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
8009 if(get_reg(regs[i].regmap,f_regmap[hr])>=0) break;
8010 if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
8012 while(k>1&®s[k-1].regmap[hr]==-1) {
8013 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
8014 //printf("no free regs for store %x\n",start+(k-1)*4);
8017 if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
8018 //printf("no-match due to different register\n");
8021 if (dops[k-2].is_jump) {
8022 //printf("no-match due to branch\n");
8025 // call/ret fast path assumes no registers allocated
8026 if(k>2&&(dops[k-3].itype==UJUMP||dops[k-3].itype==RJUMP)&&dops[k-3].rt1==31) {
8031 if(regs[k-1].regmap[hr]==f_regmap[hr]&®map_pre[k][hr]==f_regmap[hr]) {
8032 //printf("Extend r%d, %x ->\n",hr,start+k*4);
8034 regs[k].regmap_entry[hr]=f_regmap[hr];
8035 regs[k].regmap[hr]=f_regmap[hr];
8036 regmap_pre[k+1][hr]=f_regmap[hr];
8037 regs[k].wasdirty&=~(1<<hr);
8038 regs[k].dirty&=~(1<<hr);
8039 regs[k].wasdirty|=(1<<hr)®s[k-1].dirty;
8040 regs[k].dirty|=(1<<hr)®s[k].wasdirty;
8041 regs[k].wasconst&=~(1<<hr);
8042 regs[k].isconst&=~(1<<hr);
8047 //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
8050 assert(regs[i-1].regmap[hr]==f_regmap[hr]);
8051 if(regs[i-1].regmap[hr]==f_regmap[hr]&®map_pre[i][hr]==f_regmap[hr]) {
8052 //printf("OK fill %x (r%d)\n",start+i*4,hr);
8053 regs[i].regmap_entry[hr]=f_regmap[hr];
8054 regs[i].regmap[hr]=f_regmap[hr];
8055 regs[i].wasdirty&=~(1<<hr);
8056 regs[i].dirty&=~(1<<hr);
8057 regs[i].wasdirty|=(1<<hr)®s[i-1].dirty;
8058 regs[i].dirty|=(1<<hr)®s[i-1].dirty;
8059 regs[i].wasconst&=~(1<<hr);
8060 regs[i].isconst&=~(1<<hr);
8061 branch_regs[i].regmap_entry[hr]=f_regmap[hr];
8062 branch_regs[i].wasdirty&=~(1<<hr);
8063 branch_regs[i].wasdirty|=(1<<hr)®s[i].dirty;
8064 branch_regs[i].regmap[hr]=f_regmap[hr];
8065 branch_regs[i].dirty&=~(1<<hr);
8066 branch_regs[i].dirty|=(1<<hr)®s[i].dirty;
8067 branch_regs[i].wasconst&=~(1<<hr);
8068 branch_regs[i].isconst&=~(1<<hr);
8069 if (!dops[i].is_ujump) {
8070 regmap_pre[i+2][hr]=f_regmap[hr];
8071 regs[i+2].wasdirty&=~(1<<hr);
8072 regs[i+2].wasdirty|=(1<<hr)®s[i].dirty;
8077 // Alloc register clean at beginning of loop,
8078 // but may dirty it in pass 6
8079 regs[k].regmap_entry[hr]=f_regmap[hr];
8080 regs[k].regmap[hr]=f_regmap[hr];
8081 regs[k].dirty&=~(1<<hr);
8082 regs[k].wasconst&=~(1<<hr);
8083 regs[k].isconst&=~(1<<hr);
8084 if (dops[k].is_jump) {
8085 branch_regs[k].regmap_entry[hr]=f_regmap[hr];
8086 branch_regs[k].regmap[hr]=f_regmap[hr];
8087 branch_regs[k].dirty&=~(1<<hr);
8088 branch_regs[k].wasconst&=~(1<<hr);
8089 branch_regs[k].isconst&=~(1<<hr);
8090 if (!dops[k].is_ujump) {
8091 regmap_pre[k+2][hr]=f_regmap[hr];
8092 regs[k+2].wasdirty&=~(1<<hr);
8097 regmap_pre[k+1][hr]=f_regmap[hr];
8098 regs[k+1].wasdirty&=~(1<<hr);
8101 if(regs[j].regmap[hr]==f_regmap[hr])
8102 regs[j].regmap_entry[hr]=f_regmap[hr];
8106 if(regs[j].regmap[hr]>=0)
8108 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
8109 //printf("no-match due to different register\n");
8112 if (dops[j].is_ujump)
8114 // Stop on unconditional branch
8117 if(dops[j].itype==CJUMP||dops[j].itype==SJUMP)
8120 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
8123 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
8126 if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
8127 //printf("no-match due to different register (branch)\n");
8131 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
8132 //printf("No free regs for store %x\n",start+j*4);
8135 assert(f_regmap[hr]<64);
8142 // Non branch or undetermined branch target
8143 for(hr=0;hr<HOST_REGS;hr++)
8145 if(hr!=EXCLUDE_REG) {
8146 if(regs[i].regmap[hr]>=0) {
8147 if(f_regmap[hr]!=regs[i].regmap[hr]) {
8148 // dealloc old register
8150 for(n=0;n<HOST_REGS;n++)
8152 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
8154 // and alloc new one
8155 f_regmap[hr]=regs[i].regmap[hr];
8160 // Try to restore cycle count at branch targets
8162 for(j=i;j<slen-1;j++) {
8163 if(regs[j].regmap[HOST_CCREG]!=-1) break;
8164 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
8165 //printf("no free regs for store %x\n",start+j*4);
8169 if(regs[j].regmap[HOST_CCREG]==CCREG) {
8171 //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
8173 regs[k].regmap_entry[HOST_CCREG]=CCREG;
8174 regs[k].regmap[HOST_CCREG]=CCREG;
8175 regmap_pre[k+1][HOST_CCREG]=CCREG;
8176 regs[k+1].wasdirty|=1<<HOST_CCREG;
8177 regs[k].dirty|=1<<HOST_CCREG;
8178 regs[k].wasconst&=~(1<<HOST_CCREG);
8179 regs[k].isconst&=~(1<<HOST_CCREG);
8182 regs[j].regmap_entry[HOST_CCREG]=CCREG;
8184 // Work backwards from the branch target
8185 if(j>i&&f_regmap[HOST_CCREG]==CCREG)
8187 //printf("Extend backwards\n");
8190 while(regs[k-1].regmap[HOST_CCREG]==-1) {
8191 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
8192 //printf("no free regs for store %x\n",start+(k-1)*4);
8197 if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
8198 //printf("Extend CC, %x ->\n",start+k*4);
8200 regs[k].regmap_entry[HOST_CCREG]=CCREG;
8201 regs[k].regmap[HOST_CCREG]=CCREG;
8202 regmap_pre[k+1][HOST_CCREG]=CCREG;
8203 regs[k+1].wasdirty|=1<<HOST_CCREG;
8204 regs[k].dirty|=1<<HOST_CCREG;
8205 regs[k].wasconst&=~(1<<HOST_CCREG);
8206 regs[k].isconst&=~(1<<HOST_CCREG);
8211 //printf("Fail Extend CC, %x ->\n",start+k*4);
8215 if(dops[i].itype!=STORE&&dops[i].itype!=STORELR&&dops[i].itype!=C1LS&&dops[i].itype!=SHIFT&&
8216 dops[i].itype!=NOP&&dops[i].itype!=MOV&&dops[i].itype!=ALU&&dops[i].itype!=SHIFTIMM&&
8217 dops[i].itype!=IMM16&&dops[i].itype!=LOAD&&dops[i].itype!=COP1)
8219 memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
8225 // This allocates registers (if possible) one instruction prior
8226 // to use, which can avoid a load-use penalty on certain CPUs.
8227 static noinline void pass5b_preallocate2(void)
8230 for(i=0;i<slen-1;i++)
8232 if (!i || !dops[i-1].is_jump)
8236 if(dops[i].itype==ALU||dops[i].itype==MOV||dops[i].itype==LOAD||dops[i].itype==SHIFTIMM||dops[i].itype==IMM16
8237 ||((dops[i].itype==COP1||dops[i].itype==COP2)&&dops[i].opcode2<3))
8240 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rs1))>=0)
8242 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
8244 regs[i].regmap[hr]=regs[i+1].regmap[hr];
8245 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
8246 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
8247 regs[i].isconst&=~(1<<hr);
8248 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8249 constmap[i][hr]=constmap[i+1][hr];
8250 regs[i+1].wasdirty&=~(1<<hr);
8251 regs[i].dirty&=~(1<<hr);
8256 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rs2))>=0)
8258 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
8260 regs[i].regmap[hr]=regs[i+1].regmap[hr];
8261 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
8262 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
8263 regs[i].isconst&=~(1<<hr);
8264 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8265 constmap[i][hr]=constmap[i+1][hr];
8266 regs[i+1].wasdirty&=~(1<<hr);
8267 regs[i].dirty&=~(1<<hr);
8271 // Preload target address for load instruction (non-constant)
8272 if(dops[i+1].itype==LOAD&&dops[i+1].rs1&&get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8273 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rt1))>=0)
8275 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
8277 regs[i].regmap[hr]=dops[i+1].rs1;
8278 regmap_pre[i+1][hr]=dops[i+1].rs1;
8279 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8280 regs[i].isconst&=~(1<<hr);
8281 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8282 constmap[i][hr]=constmap[i+1][hr];
8283 regs[i+1].wasdirty&=~(1<<hr);
8284 regs[i].dirty&=~(1<<hr);
8288 // Load source into target register
8289 if(dops[i+1].use_lt1&&get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8290 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rt1))>=0)
8292 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
8294 regs[i].regmap[hr]=dops[i+1].rs1;
8295 regmap_pre[i+1][hr]=dops[i+1].rs1;
8296 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8297 regs[i].isconst&=~(1<<hr);
8298 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8299 constmap[i][hr]=constmap[i+1][hr];
8300 regs[i+1].wasdirty&=~(1<<hr);
8301 regs[i].dirty&=~(1<<hr);
8305 // Address for store instruction (non-constant)
8306 if(dops[i+1].itype==STORE||dops[i+1].itype==STORELR
8307 ||(dops[i+1].opcode&0x3b)==0x39||(dops[i+1].opcode&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
8308 if(get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8309 hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
8310 if(hr<0) hr=get_reg_temp(regs[i+1].regmap);
8312 regs[i+1].regmap[hr]=AGEN1+((i+1)&1);
8313 regs[i+1].isconst&=~(1<<hr);
8316 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
8318 regs[i].regmap[hr]=dops[i+1].rs1;
8319 regmap_pre[i+1][hr]=dops[i+1].rs1;
8320 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8321 regs[i].isconst&=~(1<<hr);
8322 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8323 constmap[i][hr]=constmap[i+1][hr];
8324 regs[i+1].wasdirty&=~(1<<hr);
8325 regs[i].dirty&=~(1<<hr);
8329 if(dops[i+1].itype==LOADLR||(dops[i+1].opcode&0x3b)==0x31||(dops[i+1].opcode&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
8330 if(get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8332 hr=get_reg(regs[i+1].regmap,FTEMP);
8334 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
8336 regs[i].regmap[hr]=dops[i+1].rs1;
8337 regmap_pre[i+1][hr]=dops[i+1].rs1;
8338 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8339 regs[i].isconst&=~(1<<hr);
8340 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8341 constmap[i][hr]=constmap[i+1][hr];
8342 regs[i+1].wasdirty&=~(1<<hr);
8343 regs[i].dirty&=~(1<<hr);
8345 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
8347 // move it to another register
8348 regs[i+1].regmap[hr]=-1;
8349 regmap_pre[i+2][hr]=-1;
8350 regs[i+1].regmap[nr]=FTEMP;
8351 regmap_pre[i+2][nr]=FTEMP;
8352 regs[i].regmap[nr]=dops[i+1].rs1;
8353 regmap_pre[i+1][nr]=dops[i+1].rs1;
8354 regs[i+1].regmap_entry[nr]=dops[i+1].rs1;
8355 regs[i].isconst&=~(1<<nr);
8356 regs[i+1].isconst&=~(1<<nr);
8357 regs[i].dirty&=~(1<<nr);
8358 regs[i+1].wasdirty&=~(1<<nr);
8359 regs[i+1].dirty&=~(1<<nr);
8360 regs[i+2].wasdirty&=~(1<<nr);
8364 if(dops[i+1].itype==LOAD||dops[i+1].itype==LOADLR||dops[i+1].itype==STORE||dops[i+1].itype==STORELR/*||dops[i+1].itype==C1LS||||dops[i+1].itype==C2LS*/) {
8366 if(dops[i+1].itype==LOAD)
8367 hr=get_reg(regs[i+1].regmap,dops[i+1].rt1);
8368 if(dops[i+1].itype==LOADLR||(dops[i+1].opcode&0x3b)==0x31||(dops[i+1].opcode&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
8369 hr=get_reg(regs[i+1].regmap,FTEMP);
8370 if(dops[i+1].itype==STORE||dops[i+1].itype==STORELR||(dops[i+1].opcode&0x3b)==0x39||(dops[i+1].opcode&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
8371 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
8372 if(hr<0) hr=get_reg_temp(regs[i+1].regmap);
8374 if(hr>=0&®s[i].regmap[hr]<0) {
8375 int rs=get_reg(regs[i+1].regmap,dops[i+1].rs1);
8376 if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
8377 regs[i].regmap[hr]=AGEN1+((i+1)&1);
8378 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
8379 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
8380 regs[i].isconst&=~(1<<hr);
8381 regs[i+1].wasdirty&=~(1<<hr);
8382 regs[i].dirty&=~(1<<hr);
8392 // Write back dirty registers as soon as we will no longer modify them,
8393 // so that we don't end up with lots of writes at the branches.
8394 static noinline void pass6_clean_registers(int istart, int iend, int wr)
8396 static u_int wont_dirty[MAXBLOCK];
8397 static u_int will_dirty[MAXBLOCK];
8400 u_int will_dirty_i,will_dirty_next,temp_will_dirty;
8401 u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
8403 will_dirty_i=will_dirty_next=0;
8404 wont_dirty_i=wont_dirty_next=0;
8406 will_dirty_i=will_dirty_next=will_dirty[iend+1];
8407 wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
8409 for (i=iend;i>=istart;i--)
8411 signed char rregmap_i[RRMAP_SIZE];
8412 u_int hr_candirty = 0;
8413 assert(HOST_REGS < 32);
8414 make_rregs(regs[i].regmap, rregmap_i, &hr_candirty);
8415 __builtin_prefetch(regs[i-1].regmap);
8418 signed char branch_rregmap_i[RRMAP_SIZE];
8419 u_int branch_hr_candirty = 0;
8420 make_rregs(branch_regs[i].regmap, branch_rregmap_i, &branch_hr_candirty);
8421 if(ba[i]<start || ba[i]>=(start+slen*4))
8423 // Branch out of this block, flush all regs
8425 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8426 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8427 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8428 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8429 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8430 will_dirty_i &= branch_hr_candirty;
8431 if (dops[i].is_ujump)
8433 // Unconditional branch
8435 // Merge in delay slot (will dirty)
8436 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8437 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8438 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8439 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8440 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8441 will_dirty_i &= hr_candirty;
8445 // Conditional branch
8446 wont_dirty_i = wont_dirty_next;
8447 // Merge in delay slot (will dirty)
8448 // (the original code had no explanation why these 2 are commented out)
8449 //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8450 //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8451 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8452 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8453 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8454 will_dirty_i &= hr_candirty;
8456 // Merge in delay slot (wont dirty)
8457 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8458 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8459 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8460 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8461 wont_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8462 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8463 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8464 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8465 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8466 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8467 wont_dirty_i &= ~(1u << 31);
8469 #ifndef DESTRUCTIVE_WRITEBACK
8470 branch_regs[i].dirty&=wont_dirty_i;
8472 branch_regs[i].dirty|=will_dirty_i;
8478 if(ba[i]<=start+i*4) {
8480 if (dops[i].is_ujump)
8482 // Unconditional branch
8485 // Merge in delay slot (will dirty)
8486 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8487 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8488 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8489 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8490 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8491 temp_will_dirty &= branch_hr_candirty;
8492 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8493 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8494 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8495 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8496 temp_will_dirty |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8497 temp_will_dirty &= hr_candirty;
8499 // Conditional branch (not taken case)
8500 temp_will_dirty=will_dirty_next;
8501 temp_wont_dirty=wont_dirty_next;
8502 // Merge in delay slot (will dirty)
8503 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8504 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8505 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8506 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8507 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8508 temp_will_dirty &= branch_hr_candirty;
8509 //temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8510 //temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8511 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8512 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8513 temp_will_dirty |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8514 temp_will_dirty &= hr_candirty;
8516 // Merge in delay slot (wont dirty)
8517 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8518 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8519 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8520 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8521 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8522 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8523 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8524 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8525 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8526 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8527 temp_wont_dirty &= ~(1u << 31);
8528 // Deal with changed mappings
8530 for(r=0;r<HOST_REGS;r++) {
8531 if(r!=EXCLUDE_REG) {
8532 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
8533 temp_will_dirty&=~(1<<r);
8534 temp_wont_dirty&=~(1<<r);
8535 if(regmap_pre[i][r]>0 && regmap_pre[i][r]<34) {
8536 temp_will_dirty|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r;
8537 temp_wont_dirty|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r;
8539 temp_will_dirty|=1<<r;
8540 temp_wont_dirty|=1<<r;
8547 will_dirty[i]=temp_will_dirty;
8548 wont_dirty[i]=temp_wont_dirty;
8549 pass6_clean_registers((ba[i]-start)>>2,i-1,0);
8551 // Limit recursion. It can take an excessive amount
8552 // of time if there are a lot of nested loops.
8553 will_dirty[(ba[i]-start)>>2]=0;
8554 wont_dirty[(ba[i]-start)>>2]=-1;
8559 if (dops[i].is_ujump)
8561 // Unconditional branch
8564 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
8565 for(r=0;r<HOST_REGS;r++) {
8566 if(r!=EXCLUDE_REG) {
8567 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
8568 will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
8569 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
8571 if(branch_regs[i].regmap[r]>=0) {
8572 will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>branch_regs[i].regmap[r])&1)<<r;
8573 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>branch_regs[i].regmap[r])&1)<<r;
8578 // Merge in delay slot
8579 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8580 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8581 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8582 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8583 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8584 will_dirty_i &= branch_hr_candirty;
8585 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8586 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8587 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8588 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8589 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8590 will_dirty_i &= hr_candirty;
8592 // Conditional branch
8593 will_dirty_i=will_dirty_next;
8594 wont_dirty_i=wont_dirty_next;
8595 //if(ba[i]>start+i*4) // Disable recursion (for debugging)
8596 for(r=0;r<HOST_REGS;r++) {
8597 if(r!=EXCLUDE_REG) {
8598 signed char target_reg=branch_regs[i].regmap[r];
8599 if(target_reg==regs[(ba[i]-start)>>2].regmap_entry[r]) {
8600 will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
8601 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
8603 else if(target_reg>=0) {
8604 will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>target_reg)&1)<<r;
8605 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>target_reg)&1)<<r;
8609 // Merge in delay slot
8610 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8611 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8612 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8613 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8614 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8615 will_dirty_i &= branch_hr_candirty;
8616 //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8617 //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8618 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8619 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8620 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8621 will_dirty_i &= hr_candirty;
8623 // Merge in delay slot (won't dirty)
8624 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8625 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8626 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8627 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8628 wont_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8629 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8630 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8631 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8632 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8633 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8634 wont_dirty_i &= ~(1u << 31);
8636 #ifndef DESTRUCTIVE_WRITEBACK
8637 branch_regs[i].dirty&=wont_dirty_i;
8639 branch_regs[i].dirty|=will_dirty_i;
8644 else if(dops[i].itype==SYSCALL||dops[i].itype==HLECALL||dops[i].itype==INTCALL)
8646 // SYSCALL instruction (software interrupt)
8650 else if(dops[i].itype==COP0 && (source[i]&0x3f)==0x18)
8652 // ERET instruction (return from interrupt)
8656 will_dirty_next=will_dirty_i;
8657 wont_dirty_next=wont_dirty_i;
8658 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8659 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8660 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8661 will_dirty_i &= hr_candirty;
8662 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8663 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8664 wont_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8665 wont_dirty_i &= ~(1u << 31);
8666 if (i > istart && !dops[i].is_jump) {
8667 // Don't store a register immediately after writing it,
8668 // may prevent dual-issue.
8669 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i-1].rt1) & 31);
8670 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i-1].rt2) & 31);
8673 will_dirty[i]=will_dirty_i;
8674 wont_dirty[i]=wont_dirty_i;
8675 // Mark registers that won't be dirtied as not dirty
8677 regs[i].dirty|=will_dirty_i;
8678 #ifndef DESTRUCTIVE_WRITEBACK
8679 regs[i].dirty&=wont_dirty_i;
8682 if (i < iend-1 && !dops[i].is_ujump) {
8683 for(r=0;r<HOST_REGS;r++) {
8684 if(r!=EXCLUDE_REG) {
8685 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
8686 regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
8687 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
8695 for(r=0;r<HOST_REGS;r++) {
8696 if(r!=EXCLUDE_REG) {
8697 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
8698 regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
8699 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
8706 // Deal with changed mappings
8707 temp_will_dirty=will_dirty_i;
8708 temp_wont_dirty=wont_dirty_i;
8709 for(r=0;r<HOST_REGS;r++) {
8710 if(r!=EXCLUDE_REG) {
8712 if(regs[i].regmap[r]==regmap_pre[i][r]) {
8714 #ifndef DESTRUCTIVE_WRITEBACK
8715 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
8717 regs[i].wasdirty|=will_dirty_i&(1<<r);
8720 else if(regmap_pre[i][r]>=0&&(nr=get_rreg(rregmap_i,regmap_pre[i][r]))>=0) {
8721 // Register moved to a different register
8722 will_dirty_i&=~(1<<r);
8723 wont_dirty_i&=~(1<<r);
8724 will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
8725 wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
8727 #ifndef DESTRUCTIVE_WRITEBACK
8728 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
8730 regs[i].wasdirty|=will_dirty_i&(1<<r);
8734 will_dirty_i&=~(1<<r);
8735 wont_dirty_i&=~(1<<r);
8736 if(regmap_pre[i][r]>0 && regmap_pre[i][r]<34) {
8737 will_dirty_i|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r;
8738 wont_dirty_i|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r;
8741 /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);assert(!((will_dirty>>r)&1));*/
8749 static noinline void pass10_expire_blocks(void)
8752 end = (((out-ndrc->translation_cache)>>(TARGET_SIZE_2-16)) + 16384) & 65535;
8753 while (expirep != end)
8755 int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
8756 uintptr_t base_offs = ((uintptr_t)(expirep >> 13) << shift); // Base offset of this block
8757 uintptr_t base_offs_s = base_offs >> shift;
8758 if (!(expirep & ((1 << 13) - 1)))
8759 inv_debug("EXP: base_offs %x\n", base_offs);
8760 switch((expirep>>11)&3)
8764 blocks_remove_matching_addrs(&blocks[expirep & 2047], base_offs_s, shift);
8765 blocks_remove_matching_addrs(&blocks[2048 + (expirep & 2047)], base_offs_s, shift);
8769 //ll_kill_pointers(jump_out[expirep&2047],base_offs_s,shift);
8770 //ll_kill_pointers(jump_out[(expirep&2047)+2048],base_offs_s,shift);
8775 struct ht_entry *ht_bin = &hash_table[((expirep&2047)<<5)+i];
8776 uintptr_t o1 = (u_char *)ht_bin->tcaddr[1] - ndrc->translation_cache;
8777 uintptr_t o2 = o1 - MAX_OUTPUT_BLOCK_SIZE;
8778 if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s) {
8779 inv_debug("EXP: Remove hash %x -> %p\n",ht_bin->vaddr[1],ht_bin->tcaddr[1]);
8780 ht_bin->vaddr[1] = -1;
8781 ht_bin->tcaddr[1] = NULL;
8783 o1 = (u_char *)ht_bin->tcaddr[0] - ndrc->translation_cache;
8784 o2 = o1 - MAX_OUTPUT_BLOCK_SIZE;
8785 if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s) {
8786 inv_debug("EXP: Remove hash %x -> %p\n",ht_bin->vaddr[0],ht_bin->tcaddr[0]);
8787 ht_bin->vaddr[0] = ht_bin->vaddr[1];
8788 ht_bin->tcaddr[0] = ht_bin->tcaddr[1];
8789 ht_bin->vaddr[1] = -1;
8790 ht_bin->tcaddr[1] = NULL;
8796 if((expirep&2047)==0)
8798 ll_remove_matching_addrs(jump_out+(expirep&2047),base_offs_s,shift);
8799 ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base_offs_s,shift);
8802 expirep=(expirep+1)&65535;
8806 static struct block_info *new_block_info(u_int start, u_int len,
8807 const void *source, const void *copy, u_char *beginning, u_short jump_in_count)
8809 struct block_info **b_pptr;
8810 struct block_info *block;
8811 u_int page = get_page(start);
8813 block = malloc(sizeof(*block) + jump_in_count * sizeof(block->jump_in[0]));
8815 assert(jump_in_count > 0);
8816 block->source = source;
8818 block->start = start;
8820 block->reg_sv_flags = 0;
8821 block->tc_offs = beginning - ndrc->translation_cache;
8822 //block->tc_len = out - beginning;
8823 block->is_dirty = 0;
8824 block->jump_in_cnt = jump_in_count;
8826 // insert sorted by start vaddr
8827 for (b_pptr = &blocks[page]; ; b_pptr = &((*b_pptr)->next)) {
8828 if (*b_pptr == NULL || (*b_pptr)->start >= start) {
8829 block->next = *b_pptr;
8834 stat_inc(stat_blocks);
8838 static int new_recompile_block(u_int addr)
8840 u_int pagelimit = 0;
8841 u_int state_rflags = 0;
8844 assem_debug("NOTCOMPILED: addr = %x -> %p\n", addr, out);
8846 // this is just for speculation
8847 for (i = 1; i < 32; i++) {
8848 if ((psxRegs.GPR.r[i] & 0xffff0000) == 0x1f800000)
8849 state_rflags |= 1 << i;
8852 assert(!(addr & 3));
8854 new_dynarec_did_compile=1;
8855 if (Config.HLE && start == 0x80001000) // hlecall
8857 // XXX: is this enough? Maybe check hleSoftCall?
8858 void *beginning = start_block();
8860 emit_movimm(start,0);
8861 emit_writeword(0,&pcaddr);
8862 emit_far_jump(new_dyna_leave);
8864 end_block(beginning);
8865 struct block_info *block = new_block_info(start, 4, NULL, NULL, beginning, 1);
8866 block->jump_in[0].vaddr = start;
8867 block->jump_in[0].addr = beginning;
8870 else if (f1_hack && hack_addr == 0) {
8871 void *beginning = start_block();
8872 emit_movimm(start, 0);
8873 emit_writeword(0, &hack_addr);
8874 emit_readword(&psxRegs.GPR.n.sp, 0);
8875 emit_readptr(&mem_rtab, 1);
8876 emit_shrimm(0, 12, 2);
8877 emit_readptr_dualindexedx_ptrlen(1, 2, 1);
8878 emit_addimm(0, 0x18, 0);
8879 emit_adds_ptr(1, 1, 1);
8880 emit_ldr_dualindexed(1, 0, 0);
8881 emit_writeword(0, &psxRegs.GPR.r[26]); // lw k0, 0x18(sp)
8882 emit_far_call(ndrc_get_addr_ht);
8883 emit_jmpreg(0); // jr k0
8885 end_block(beginning);
8887 struct block_info *block = new_block_info(start, 4, NULL, NULL, beginning, 1);
8888 block->jump_in[0].vaddr = start;
8889 block->jump_in[0].addr = beginning;
8890 SysPrintf("F1 hack to %08x\n", start);
8894 cycle_multiplier_active = cycle_multiplier_override && cycle_multiplier == CYCLE_MULT_DEFAULT
8895 ? cycle_multiplier_override : cycle_multiplier;
8897 source = get_source_start(start, &pagelimit);
8898 if (source == NULL) {
8899 if (addr != hack_addr) {
8900 SysPrintf("Compile at bogus memory address: %08x\n", addr);
8907 /* Pass 1: disassemble */
8908 /* Pass 2: register dependencies, branch targets */
8909 /* Pass 3: register allocation */
8910 /* Pass 4: branch dependencies */
8911 /* Pass 5: pre-alloc */
8912 /* Pass 6: optimize clean/dirty state */
8913 /* Pass 7: flag 32-bit registers */
8914 /* Pass 8: assembly */
8915 /* Pass 9: linker */
8916 /* Pass 10: garbage collection / free memory */
8918 /* Pass 1 disassembly */
8920 pass1_disassemble(pagelimit);
8922 int clear_hack_addr = apply_hacks();
8924 /* Pass 2 - Register dependencies and branch targets */
8926 pass2_unneeded_regs(0,slen-1,0);
8928 /* Pass 3 - Register allocation */
8930 pass3_register_alloc(addr);
8932 /* Pass 4 - Cull unused host registers */
8934 pass4_cull_unused_regs();
8936 /* Pass 5 - Pre-allocate registers */
8938 pass5a_preallocate1();
8939 pass5b_preallocate2();
8941 /* Pass 6 - Optimize clean/dirty state */
8942 pass6_clean_registers(0, slen-1, 1);
8944 /* Pass 7 - Identify 32-bit registers */
8945 for (i=slen-1;i>=0;i--)
8947 if(dops[i].itype==CJUMP||dops[i].itype==SJUMP)
8949 // Conditional branch
8950 if((source[i]>>16)!=0x1000&&i<slen-2) {
8951 // Mark this address as a branch target since it may be called
8952 // upon return from interrupt
8958 /* Pass 8 - Assembly */
8959 linkcount=0;stubcount=0;
8962 void *beginning=start_block();
8963 void *instr_addr0_override = NULL;
8966 if (start == 0x80030000) {
8967 // nasty hack for the fastbios thing
8968 // override block entry to this code
8969 instr_addr0_override = out;
8970 emit_movimm(start,0);
8971 // abuse io address var as a flag that we
8972 // have already returned here once
8973 emit_readword(&address,1);
8974 emit_writeword(0,&pcaddr);
8975 emit_writeword(0,&address);
8978 emit_jeq(out + 4*2);
8979 emit_far_jump(new_dyna_leave);
8981 emit_jne(new_dyna_leave);
8986 __builtin_prefetch(regs[i+1].regmap);
8987 check_regmap(regmap_pre[i]);
8988 check_regmap(regs[i].regmap_entry);
8989 check_regmap(regs[i].regmap);
8990 //if(ds) printf("ds: ");
8991 disassemble_inst(i);
8993 ds=0; // Skip delay slot
8994 if(dops[i].bt) assem_debug("OOPS - branch into delay slot\n");
8995 instr_addr[i] = NULL;
8997 speculate_register_values(i);
8998 #ifndef DESTRUCTIVE_WRITEBACK
8999 if (i < 2 || !dops[i-2].is_ujump)
9001 wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,unneeded_reg[i]);
9003 if((dops[i].itype==CJUMP||dops[i].itype==SJUMP)) {
9004 dirty_pre=branch_regs[i].dirty;
9006 dirty_pre=regs[i].dirty;
9010 if (i < 2 || !dops[i-2].is_ujump)
9012 wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,unneeded_reg[i]);
9013 loop_preload(regmap_pre[i],regs[i].regmap_entry);
9015 // branch target entry point
9016 instr_addr[i] = out;
9017 assem_debug("<->\n");
9018 drc_dbg_emit_do_cmp(i, ccadj[i]);
9019 if (clear_hack_addr) {
9021 emit_writeword(0, &hack_addr);
9022 clear_hack_addr = 0;
9026 if(regs[i].regmap_entry[HOST_CCREG]==CCREG&®s[i].regmap[HOST_CCREG]!=CCREG)
9027 wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty);
9028 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i].rs1,dops[i].rs2);
9029 address_generation(i,®s[i],regs[i].regmap_entry);
9030 load_consts(regmap_pre[i],regs[i].regmap,i);
9033 // Load the delay slot registers if necessary
9034 if(dops[i+1].rs1!=dops[i].rs1&&dops[i+1].rs1!=dops[i].rs2&&(dops[i+1].rs1!=dops[i].rt1||dops[i].rt1==0))
9035 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs1,dops[i+1].rs1);
9036 if(dops[i+1].rs2!=dops[i+1].rs1&&dops[i+1].rs2!=dops[i].rs1&&dops[i+1].rs2!=dops[i].rs2&&(dops[i+1].rs2!=dops[i].rt1||dops[i].rt1==0))
9037 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2);
9038 if (ram_offset && (dops[i+1].is_load || dops[i+1].is_store))
9039 load_reg(regs[i].regmap_entry,regs[i].regmap,ROREG);
9040 if (dops[i+1].is_store)
9041 load_reg(regs[i].regmap_entry,regs[i].regmap,INVCP);
9045 // Preload registers for following instruction
9046 if(dops[i+1].rs1!=dops[i].rs1&&dops[i+1].rs1!=dops[i].rs2)
9047 if(dops[i+1].rs1!=dops[i].rt1&&dops[i+1].rs1!=dops[i].rt2)
9048 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs1,dops[i+1].rs1);
9049 if(dops[i+1].rs2!=dops[i+1].rs1&&dops[i+1].rs2!=dops[i].rs1&&dops[i+1].rs2!=dops[i].rs2)
9050 if(dops[i+1].rs2!=dops[i].rt1&&dops[i+1].rs2!=dops[i].rt2)
9051 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2);
9053 // TODO: if(is_ooo(i)) address_generation(i+1);
9054 if (!dops[i].is_jump || dops[i].itype == CJUMP)
9055 load_reg(regs[i].regmap_entry,regs[i].regmap,CCREG);
9056 if (ram_offset && (dops[i].is_load || dops[i].is_store))
9057 load_reg(regs[i].regmap_entry,regs[i].regmap,ROREG);
9058 if (dops[i].is_store)
9059 load_reg(regs[i].regmap_entry,regs[i].regmap,INVCP);
9061 ds = assemble(i, ®s[i], ccadj[i]);
9063 if (dops[i].is_ujump)
9066 literal_pool_jumpover(256);
9071 if (slen > 0 && dops[slen-1].itype == INTCALL) {
9072 // no ending needed for this block since INTCALL never returns
9074 // If the block did not end with an unconditional branch,
9075 // add a jump to the next instruction.
9077 if (!dops[i-2].is_ujump) {
9078 assert(!dops[i-1].is_jump);
9080 if(dops[i-2].itype!=CJUMP&&dops[i-2].itype!=SJUMP) {
9081 store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4);
9082 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
9083 emit_loadreg(CCREG,HOST_CCREG);
9084 emit_addimm(HOST_CCREG, ccadj[i-1] + CLOCK_ADJUST(1), HOST_CCREG);
9088 store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].dirty,start+i*4);
9089 assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
9091 add_to_linker(out,start+i*4,0);
9098 assert(!dops[i-1].is_jump);
9099 store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4);
9100 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
9101 emit_loadreg(CCREG,HOST_CCREG);
9102 emit_addimm(HOST_CCREG, ccadj[i-1] + CLOCK_ADJUST(1), HOST_CCREG);
9103 add_to_linker(out,start+i*4,0);
9107 // TODO: delay slot stubs?
9109 for(i=0;i<stubcount;i++)
9111 switch(stubs[i].type)
9119 do_readstub(i);break;
9124 do_writestub(i);break;
9128 do_invstub(i);break;
9130 do_cop1stub(i);break;
9132 do_unalignedwritestub(i);break;
9136 if (instr_addr0_override)
9137 instr_addr[0] = instr_addr0_override;
9139 /* Pass 9 - Linker */
9140 for(i=0;i<linkcount;i++)
9142 assem_debug("%p -> %8x\n",link_addr[i].addr,link_addr[i].target);
9144 if (!link_addr[i].internal)
9147 void *addr = check_addr(link_addr[i].target);
9148 emit_extjump(link_addr[i].addr, link_addr[i].target);
9150 set_jump_target(link_addr[i].addr, addr);
9151 ndrc_add_jump_out(link_addr[i].target,stub);
9154 set_jump_target(link_addr[i].addr, stub);
9159 int target=(link_addr[i].target-start)>>2;
9160 assert(target>=0&&target<slen);
9161 assert(instr_addr[target]);
9162 //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
9163 //set_jump_target_fillslot(link_addr[i].addr,instr_addr[target],link_addr[i].ext>>1);
9165 set_jump_target(link_addr[i].addr, instr_addr[target]);
9170 u_int source_len = slen*4;
9171 if (dops[slen-1].itype == INTCALL && source_len > 4)
9172 // no need to treat the last instruction as compiled
9173 // as interpreter fully handles it
9176 if ((u_char *)copy + source_len > (u_char *)shadow + sizeof(shadow))
9179 // External Branch Targets (jump_in)
9180 int jump_in_count = 1;
9181 assert(instr_addr[0]);
9182 for (i = 1; i < slen; i++)
9184 if (dops[i].bt && instr_addr[i])
9188 struct block_info *block =
9189 new_block_info(start, slen * 4, source, copy, beginning, jump_in_count);
9190 block->reg_sv_flags = state_rflags;
9193 for (i = 0; i < slen; i++)
9195 if ((i == 0 || dops[i].bt) && instr_addr[i])
9197 assem_debug("%p (%d) <- %8x\n", instr_addr[i], i, start + i*4);
9198 u_int vaddr = start + i*4;
9204 entry = instr_addr[i];
9206 emit_jmp(instr_addr[i]);
9208 block->jump_in[jump_in_i].vaddr = vaddr;
9209 block->jump_in[jump_in_i].addr = entry;
9213 assert(jump_in_i == jump_in_count);
9214 hash_table_add(block->jump_in[0].vaddr, block->jump_in[0].addr);
9215 // Write out the literal pool if necessary
9217 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
9219 if(((u_int)out)&7) emit_addnop(13);
9221 assert(out - (u_char *)beginning < MAX_OUTPUT_BLOCK_SIZE);
9222 //printf("shadow buffer: %p-%p\n",copy,(u_char *)copy+slen*4);
9223 memcpy(copy, source, source_len);
9226 end_block(beginning);
9228 // If we're within 256K of the end of the buffer,
9229 // start over from the beginning. (Is 256K enough?)
9230 if (out > ndrc->translation_cache + sizeof(ndrc->translation_cache) - MAX_OUTPUT_BLOCK_SIZE)
9231 out = ndrc->translation_cache;
9233 // Trap writes to any of the pages we compiled
9234 mark_invalid_code(start, slen*4, 0);
9236 /* Pass 10 - Free memory by expiring oldest blocks */
9238 pass10_expire_blocks();
9243 stat_inc(stat_bc_direct);
9247 // vim:shiftwidth=2:expandtab