1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
3 * Copyright (C) 2009-2010 Ari64 *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
22 #include <stdint.h> //include for uint64_t
25 #include "emu_if.h" //emulator interface
30 #include "assem_x86.h"
33 #include "assem_x64.h"
36 #include "assem_arm.h"
40 #define MAX_OUTPUT_BLOCK_SIZE 262144
41 #define CLOCK_DIVIDER 2
45 signed char regmap_entry[HOST_REGS];
46 signed char regmap[HOST_REGS];
55 uint64_t constmap[HOST_REGS];
63 struct ll_entry *next;
69 char insn[MAXBLOCK][10];
70 u_char itype[MAXBLOCK];
71 u_char opcode[MAXBLOCK];
72 u_char opcode2[MAXBLOCK];
80 u_char dep1[MAXBLOCK];
81 u_char dep2[MAXBLOCK];
85 char likely[MAXBLOCK];
87 uint64_t unneeded_reg[MAXBLOCK];
88 uint64_t unneeded_reg_upper[MAXBLOCK];
89 uint64_t branch_unneeded_reg[MAXBLOCK];
90 uint64_t branch_unneeded_reg_upper[MAXBLOCK];
91 uint64_t p32[MAXBLOCK];
92 uint64_t pr32[MAXBLOCK];
93 signed char regmap_pre[MAXBLOCK][HOST_REGS];
94 signed char regmap[MAXBLOCK][HOST_REGS];
95 signed char regmap_entry[MAXBLOCK][HOST_REGS];
96 uint64_t constmap[MAXBLOCK][HOST_REGS];
97 uint64_t known_value[HOST_REGS];
99 struct regstat regs[MAXBLOCK];
100 struct regstat branch_regs[MAXBLOCK];
101 u_int needed_reg[MAXBLOCK];
102 uint64_t requires_32bit[MAXBLOCK];
103 u_int wont_dirty[MAXBLOCK];
104 u_int will_dirty[MAXBLOCK];
107 u_int instr_addr[MAXBLOCK];
108 u_int link_addr[MAXBLOCK][3];
110 u_int stubs[MAXBLOCK*3][8];
112 u_int literals[1024][2];
117 struct ll_entry *jump_in[4096];
118 struct ll_entry *jump_out[4096];
119 struct ll_entry *jump_dirty[4096];
120 u_int hash_table[65536][4] __attribute__((aligned(16)));
121 char shadow[1048576] __attribute__((aligned(16)));
125 u_int stop_after_jal;
126 extern u_char restore_candidate[512];
127 extern int cycle_count;
129 /* registers that may be allocated */
131 #define HIREG 32 // hi
132 #define LOREG 33 // lo
133 #define FSREG 34 // FPU status (FCSR)
134 #define CSREG 35 // Coprocessor status
135 #define CCREG 36 // Cycle count
136 #define INVCP 37 // Pointer to invalid_code
138 #define FTEMP 38 // FPU/LDL/LDR temporary register
139 #define PTEMP 39 // Prefetch temporary register
140 #define TLREG 40 // TLB mapping offset
141 #define RHASH 41 // Return address hash
142 #define RHTBL 42 // Return address hash table address
143 #define RTEMP 43 // JR/JALR address register
145 #define AGEN1 44 // Address generation temporary register
146 #define AGEN2 45 // Address generation temporary register
147 #define MGEN1 46 // Maptable address generation temporary register
148 #define MGEN2 47 // Maptable address generation temporary register
149 #define BTREG 48 // Branch target temporary register
151 /* instruction types */
152 #define NOP 0 // No operation
153 #define LOAD 1 // Load
154 #define STORE 2 // Store
155 #define LOADLR 3 // Unaligned load
156 #define STORELR 4 // Unaligned store
157 #define MOV 5 // Move
158 #define ALU 6 // Arithmetic/logic
159 #define MULTDIV 7 // Multiply/divide
160 #define SHIFT 8 // Shift by register
161 #define SHIFTIMM 9// Shift by immediate
162 #define IMM16 10 // 16-bit immediate
163 #define RJUMP 11 // Unconditional jump to register
164 #define UJUMP 12 // Unconditional jump
165 #define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
166 #define SJUMP 14 // Conditional branch (regimm format)
167 #define COP0 15 // Coprocessor 0
168 #define COP1 16 // Coprocessor 1
169 #define C1LS 17 // Coprocessor 1 load/store
170 #define FJUMP 18 // Conditional branch (floating point)
171 #define FLOAT 19 // Floating point unit
172 #define FCONV 20 // Convert integer to float
173 #define FCOMP 21 // Floating point compare (sets FSREG)
174 #define SYSCALL 22// SYSCALL
175 #define OTHER 23 // Other
176 #define SPAN 24 // Branch/delay slot spans 2 pages
177 #define NI 25 // Not implemented
178 #define HLECALL 26// PCSX fake opcodes for HLE
179 #define COP2 27 // Coprocessor 2 move
180 #define C2LS 28 // Coprocessor 2 load/store
181 #define C2OP 29 // Coprocessor 2 operation
182 #define INTCALL 30// Call interpreter to handle rare corner cases
191 #define LOADBU_STUB 7
192 #define LOADHU_STUB 8
193 #define STOREB_STUB 9
194 #define STOREH_STUB 10
195 #define STOREW_STUB 11
196 #define STORED_STUB 12
197 #define STORELR_STUB 13
198 #define INVCODE_STUB 14
206 int new_recompile_block(int addr);
207 void *get_addr_ht(u_int vaddr);
208 void invalidate_block(u_int block);
209 void invalidate_addr(u_int addr);
210 void remove_hash(int vaddr);
213 void dyna_linker_ds();
215 void verify_code_vm();
216 void verify_code_ds();
219 void fp_exception_ds();
221 void jump_syscall_hle();
225 void new_dyna_leave();
230 void read_nomem_new();
231 void read_nomemb_new();
232 void read_nomemh_new();
233 void read_nomemd_new();
234 void write_nomem_new();
235 void write_nomemb_new();
236 void write_nomemh_new();
237 void write_nomemd_new();
238 void write_rdram_new();
239 void write_rdramb_new();
240 void write_rdramh_new();
241 void write_rdramd_new();
242 extern u_int memory_map[1048576];
244 // Needed by assembler
245 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
246 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
247 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
248 void load_all_regs(signed char i_regmap[]);
249 void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
250 void load_regs_entry(int t);
251 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
255 //#define DEBUG_CYCLE_COUNT 1
258 //#define assem_debug printf
259 //#define inv_debug printf
260 #define assem_debug nullf
261 #define inv_debug nullf
263 static void tlb_hacks()
267 if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
271 switch (ROM_HEADER->Country_code&0xFF)
283 // Unknown country code
287 u_int rom_addr=(u_int)rom;
289 // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
290 // in the lower 4G of memory to use this hack. Copy it if necessary.
291 if((void *)rom>(void *)0xffffffff) {
292 munmap(ROM_COPY, 67108864);
293 if(mmap(ROM_COPY, 12582912,
294 PROT_READ | PROT_WRITE,
295 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
296 -1, 0) <= 0) {printf("mmap() failed\n");}
297 memcpy(ROM_COPY,rom,12582912);
298 rom_addr=(u_int)ROM_COPY;
302 for(n=0x7F000;n<0x80000;n++) {
303 memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
310 static u_int get_page(u_int vaddr)
312 u_int page=(vaddr^0x80000000)>>12;
314 if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
316 if(page>2048) page=2048+(page&2047);
320 static u_int get_vpage(u_int vaddr)
322 u_int vpage=(vaddr^0x80000000)>>12;
324 if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
326 if(vpage>2048) vpage=2048+(vpage&2047);
330 // Get address from virtual address
331 // This is called from the recompiled JR/JALR instructions
332 void *get_addr(u_int vaddr)
334 u_int page=get_page(vaddr);
335 u_int vpage=get_vpage(vaddr);
336 struct ll_entry *head;
337 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
340 if(head->vaddr==vaddr&&head->reg32==0) {
341 //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
342 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
345 ht_bin[1]=(int)head->addr;
351 head=jump_dirty[vpage];
353 if(head->vaddr==vaddr&&head->reg32==0) {
354 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
355 // Don't restore blocks which are about to expire from the cache
356 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
357 if(verify_dirty(head->addr)) {
358 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
359 invalid_code[vaddr>>12]=0;
360 memory_map[vaddr>>12]|=0x40000000;
363 if(tlb_LUT_r[vaddr>>12]) {
364 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
365 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
368 restore_candidate[vpage>>3]|=1<<(vpage&7);
370 else restore_candidate[page>>3]|=1<<(page&7);
371 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
372 if(ht_bin[0]==vaddr) {
373 ht_bin[1]=(int)head->addr; // Replace existing entry
379 ht_bin[1]=(int)head->addr;
387 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
388 int r=new_recompile_block(vaddr);
389 if(r==0) return get_addr(vaddr);
390 // Execute in unmapped page, generate pagefault execption
392 Cause=(vaddr<<31)|0x8;
393 EPC=(vaddr&1)?vaddr-5:vaddr;
395 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
396 EntryHi=BadVAddr&0xFFFFE000;
397 return get_addr_ht(0x80000000);
399 // Look up address in hash table first
400 void *get_addr_ht(u_int vaddr)
402 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
403 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
404 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
405 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
406 return get_addr(vaddr);
409 void *get_addr_32(u_int vaddr,u_int flags)
412 return get_addr(vaddr);
414 //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
415 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
416 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
417 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
418 u_int page=get_page(vaddr);
419 u_int vpage=get_vpage(vaddr);
420 struct ll_entry *head;
423 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
424 //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
426 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
428 ht_bin[1]=(int)head->addr;
430 }else if(ht_bin[2]==-1) {
431 ht_bin[3]=(int)head->addr;
434 //ht_bin[3]=ht_bin[1];
435 //ht_bin[2]=ht_bin[0];
436 //ht_bin[1]=(int)head->addr;
443 head=jump_dirty[vpage];
445 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
446 //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
447 // Don't restore blocks which are about to expire from the cache
448 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
449 if(verify_dirty(head->addr)) {
450 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
451 invalid_code[vaddr>>12]=0;
452 memory_map[vaddr>>12]|=0x40000000;
455 if(tlb_LUT_r[vaddr>>12]) {
456 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
457 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
460 restore_candidate[vpage>>3]|=1<<(vpage&7);
462 else restore_candidate[page>>3]|=1<<(page&7);
464 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
466 ht_bin[1]=(int)head->addr;
468 }else if(ht_bin[2]==-1) {
469 ht_bin[3]=(int)head->addr;
472 //ht_bin[3]=ht_bin[1];
473 //ht_bin[2]=ht_bin[0];
474 //ht_bin[1]=(int)head->addr;
482 //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
483 int r=new_recompile_block(vaddr);
484 if(r==0) return get_addr(vaddr);
485 // Execute in unmapped page, generate pagefault execption
487 Cause=(vaddr<<31)|0x8;
488 EPC=(vaddr&1)?vaddr-5:vaddr;
490 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
491 EntryHi=BadVAddr&0xFFFFE000;
492 return get_addr_ht(0x80000000);
496 void clear_all_regs(signed char regmap[])
499 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
502 signed char get_reg(signed char regmap[],int r)
505 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map[hr]==r) return hr;
509 // Find a register that is available for two consecutive cycles
510 signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
513 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map1[hr]==r&®map2[hr]==r) return hr;
517 int count_free_regs(signed char regmap[])
521 for(hr=0;hr<HOST_REGS;hr++)
523 if(hr!=EXCLUDE_REG) {
524 if(regmap[hr]<0) count++;
530 void dirty_reg(struct regstat *cur,signed char reg)
534 for (hr=0;hr<HOST_REGS;hr++) {
535 if((cur->regmap[hr]&63)==reg) {
541 // If we dirty the lower half of a 64 bit register which is now being
542 // sign-extended, we need to dump the upper half.
543 // Note: Do this only after completion of the instruction, because
544 // some instructions may need to read the full 64-bit value even if
545 // overwriting it (eg SLTI, DSRA32).
546 static void flush_dirty_uppers(struct regstat *cur)
549 for (hr=0;hr<HOST_REGS;hr++) {
550 if((cur->dirty>>hr)&1) {
553 if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
558 void set_const(struct regstat *cur,signed char reg,uint64_t value)
562 for (hr=0;hr<HOST_REGS;hr++) {
563 if(cur->regmap[hr]==reg) {
565 cur->constmap[hr]=value;
567 else if((cur->regmap[hr]^64)==reg) {
569 cur->constmap[hr]=value>>32;
574 void clear_const(struct regstat *cur,signed char reg)
578 for (hr=0;hr<HOST_REGS;hr++) {
579 if((cur->regmap[hr]&63)==reg) {
580 cur->isconst&=~(1<<hr);
585 int is_const(struct regstat *cur,signed char reg)
589 for (hr=0;hr<HOST_REGS;hr++) {
590 if((cur->regmap[hr]&63)==reg) {
591 return (cur->isconst>>hr)&1;
596 uint64_t get_const(struct regstat *cur,signed char reg)
600 for (hr=0;hr<HOST_REGS;hr++) {
601 if(cur->regmap[hr]==reg) {
602 return cur->constmap[hr];
605 printf("Unknown constant in r%d\n",reg);
609 // Least soon needed registers
610 // Look at the next ten instructions and see which registers
611 // will be used. Try not to reallocate these.
612 void lsn(u_char hsn[], int i, int *preferred_reg)
622 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
624 // Don't go past an unconditonal jump
631 if(rs1[i+j]) hsn[rs1[i+j]]=j;
632 if(rs2[i+j]) hsn[rs2[i+j]]=j;
633 if(rt1[i+j]) hsn[rt1[i+j]]=j;
634 if(rt2[i+j]) hsn[rt2[i+j]]=j;
635 if(itype[i+j]==STORE || itype[i+j]==STORELR) {
636 // Stores can allocate zero
640 // On some architectures stores need invc_ptr
641 #if defined(HOST_IMM8)
642 if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
646 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
654 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
656 // Follow first branch
657 int t=(ba[i+b]-start)>>2;
658 j=7-b;if(t+j>=slen) j=slen-t-1;
661 if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
662 if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
663 //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
664 //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
667 // TODO: preferred register based on backward branch
669 // Delay slot should preferably not overwrite branch conditions or cycle count
670 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
671 if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
672 if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
678 // Coprocessor load/store needs FTEMP, even if not declared
679 if(itype[i]==C1LS||itype[i]==C2LS) {
682 // Load L/R also uses FTEMP as a temporary register
683 if(itype[i]==LOADLR) {
686 // Also SWL/SWR/SDL/SDR
687 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
690 // Don't remove the TLB registers either
691 if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
694 // Don't remove the miniht registers
695 if(itype[i]==UJUMP||itype[i]==RJUMP)
702 // We only want to allocate registers if we're going to use them again soon
703 int needed_again(int r, int i)
709 u_char hsn[MAXREG+1];
712 memset(hsn,10,sizeof(hsn));
713 lsn(hsn,i,&preferred_reg);
715 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
717 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
718 return 0; // Don't need any registers if exiting the block
726 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
728 // Don't go past an unconditonal jump
732 if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
739 if(rs1[i+j]==r) rn=j;
740 if(rs2[i+j]==r) rn=j;
741 if((unneeded_reg[i+j]>>r)&1) rn=10;
742 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
750 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
752 // Follow first branch
754 int t=(ba[i+b]-start)>>2;
755 j=7-b;if(t+j>=slen) j=slen-t-1;
758 if(!((unneeded_reg[t+j]>>r)&1)) {
759 if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
760 if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
766 for(hr=0;hr<HOST_REGS;hr++) {
767 if(hr!=EXCLUDE_REG) {
768 if(rn<hsn[hr]) return 1;
774 // Try to match register allocations at the end of a loop with those
776 int loop_reg(int i, int r, int hr)
785 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
787 // Don't go past an unconditonal jump
794 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
799 if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
800 if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
801 if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
803 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
805 int t=(ba[i+k]-start)>>2;
806 int reg=get_reg(regs[t].regmap_entry,r);
807 if(reg>=0) return reg;
808 //reg=get_reg(regs[t+1].regmap_entry,r);
809 //if(reg>=0) return reg;
817 // Allocate every register, preserving source/target regs
818 void alloc_all(struct regstat *cur,int i)
822 for(hr=0;hr<HOST_REGS;hr++) {
823 if(hr!=EXCLUDE_REG) {
824 if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
825 ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
828 cur->dirty&=~(1<<hr);
831 if((cur->regmap[hr]&63)==0)
834 cur->dirty&=~(1<<hr);
841 void div64(int64_t dividend,int64_t divisor)
845 //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
846 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
848 void divu64(uint64_t dividend,uint64_t divisor)
852 //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
853 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
856 void mult64(uint64_t m1,uint64_t m2)
858 unsigned long long int op1, op2, op3, op4;
859 unsigned long long int result1, result2, result3, result4;
860 unsigned long long int temp1, temp2, temp3, temp4;
876 op1 = op2 & 0xFFFFFFFF;
877 op2 = (op2 >> 32) & 0xFFFFFFFF;
878 op3 = op4 & 0xFFFFFFFF;
879 op4 = (op4 >> 32) & 0xFFFFFFFF;
882 temp2 = (temp1 >> 32) + op1 * op4;
884 temp4 = (temp3 >> 32) + op2 * op4;
886 result1 = temp1 & 0xFFFFFFFF;
887 result2 = temp2 + (temp3 & 0xFFFFFFFF);
888 result3 = (result2 >> 32) + temp4;
889 result4 = (result3 >> 32);
891 lo = result1 | (result2 << 32);
892 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
901 void multu64(uint64_t m1,uint64_t m2)
903 unsigned long long int op1, op2, op3, op4;
904 unsigned long long int result1, result2, result3, result4;
905 unsigned long long int temp1, temp2, temp3, temp4;
907 op1 = m1 & 0xFFFFFFFF;
908 op2 = (m1 >> 32) & 0xFFFFFFFF;
909 op3 = m2 & 0xFFFFFFFF;
910 op4 = (m2 >> 32) & 0xFFFFFFFF;
913 temp2 = (temp1 >> 32) + op1 * op4;
915 temp4 = (temp3 >> 32) + op2 * op4;
917 result1 = temp1 & 0xFFFFFFFF;
918 result2 = temp2 + (temp3 & 0xFFFFFFFF);
919 result3 = (result2 >> 32) + temp4;
920 result4 = (result3 >> 32);
922 lo = result1 | (result2 << 32);
923 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
925 //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
926 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
929 uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
937 else original=loaded;
940 uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
943 original>>=64-(bits^56);
944 original<<=64-(bits^56);
948 else original=loaded;
953 #include "assem_x86.c"
956 #include "assem_x64.c"
959 #include "assem_arm.c"
962 // Add virtual address mapping to linked list
963 void ll_add(struct ll_entry **head,int vaddr,void *addr)
965 struct ll_entry *new_entry;
966 new_entry=malloc(sizeof(struct ll_entry));
967 assert(new_entry!=NULL);
968 new_entry->vaddr=vaddr;
970 new_entry->addr=addr;
971 new_entry->next=*head;
975 // Add virtual address mapping for 32-bit compiled block
976 void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
978 ll_add(head,vaddr,addr);
980 (*head)->reg32=reg32;
984 // Check if an address is already compiled
985 // but don't return addresses which are about to expire from the cache
986 void *check_addr(u_int vaddr)
988 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
989 if(ht_bin[0]==vaddr) {
990 if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
991 if(isclean(ht_bin[1])) return (void *)ht_bin[1];
993 if(ht_bin[2]==vaddr) {
994 if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
995 if(isclean(ht_bin[3])) return (void *)ht_bin[3];
997 u_int page=get_page(vaddr);
998 struct ll_entry *head;
1001 if(head->vaddr==vaddr&&head->reg32==0) {
1002 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1003 // Update existing entry with current address
1004 if(ht_bin[0]==vaddr) {
1005 ht_bin[1]=(int)head->addr;
1008 if(ht_bin[2]==vaddr) {
1009 ht_bin[3]=(int)head->addr;
1012 // Insert into hash table with low priority.
1013 // Don't evict existing entries, as they are probably
1014 // addresses that are being accessed frequently.
1016 ht_bin[1]=(int)head->addr;
1018 }else if(ht_bin[2]==-1) {
1019 ht_bin[3]=(int)head->addr;
1030 void remove_hash(int vaddr)
1032 //printf("remove hash: %x\n",vaddr);
1033 int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1034 if(ht_bin[2]==vaddr) {
1035 ht_bin[2]=ht_bin[3]=-1;
1037 if(ht_bin[0]==vaddr) {
1038 ht_bin[0]=ht_bin[2];
1039 ht_bin[1]=ht_bin[3];
1040 ht_bin[2]=ht_bin[3]=-1;
1044 void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1046 struct ll_entry *next;
1048 if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1049 ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1051 inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1052 remove_hash((*head)->vaddr);
1059 head=&((*head)->next);
1064 // Remove all entries from linked list
1065 void ll_clear(struct ll_entry **head)
1067 struct ll_entry *cur;
1068 struct ll_entry *next;
1079 // Dereference the pointers and remove if it matches
1080 void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1082 u_int old_host_addr=0;
1084 int ptr=get_pointer(head->addr);
1085 inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1086 if(((ptr>>shift)==(addr>>shift)) ||
1087 (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1089 inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1090 u_int host_addr=(u_int)kill_pointer(head->addr);
1092 if((host_addr>>12)!=(old_host_addr>>12)) {
1094 __clear_cache((void *)(old_host_addr&~0xfff),(void *)(old_host_addr|0xfff));
1096 old_host_addr=host_addr;
1103 __clear_cache((void *)(old_host_addr&~0xfff),(void *)(old_host_addr|0xfff));
1107 // This is called when we write to a compiled block (see do_invstub)
1108 void invalidate_page(u_int page)
1110 struct ll_entry *head;
1111 struct ll_entry *next;
1112 u_int old_host_addr=0;
1116 inv_debug("INVALIDATE: %x\n",head->vaddr);
1117 remove_hash(head->vaddr);
1122 head=jump_out[page];
1125 inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
1126 u_int host_addr=(u_int)kill_pointer(head->addr);
1128 if((host_addr>>12)!=(old_host_addr>>12)) {
1130 __clear_cache((void *)(old_host_addr&~0xfff),(void *)(old_host_addr|0xfff));
1132 old_host_addr=host_addr;
1140 __clear_cache((void *)(old_host_addr&~0xfff),(void *)(old_host_addr|0xfff));
1143 void invalidate_block(u_int block)
1145 u_int page=get_page(block<<12);
1146 u_int vpage=get_vpage(block<<12);
1147 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1148 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1151 struct ll_entry *head;
1152 head=jump_dirty[vpage];
1153 //printf("page=%d vpage=%d\n",page,vpage);
1156 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1157 get_bounds((int)head->addr,&start,&end);
1158 //printf("start: %x end: %x\n",start,end);
1159 if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) {
1160 if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1161 if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1162 if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1166 if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1167 if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1168 if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1169 if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1176 //printf("first=%d last=%d\n",first,last);
1177 invalidate_page(page);
1178 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1179 assert(last<page+5);
1180 // Invalidate the adjacent pages if a block crosses a 4K boundary
1182 invalidate_page(first);
1185 for(first=page+1;first<last;first++) {
1186 invalidate_page(first);
1189 // Don't trap writes
1190 invalid_code[block]=1;
1192 // If there is a valid TLB entry for this page, remove write protect
1193 if(tlb_LUT_w[block]) {
1194 assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1195 // CHECK: Is this right?
1196 memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1197 u_int real_block=tlb_LUT_w[block]>>12;
1198 invalid_code[real_block]=1;
1199 if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1201 else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
1205 memset(mini_ht,-1,sizeof(mini_ht));
1208 void invalidate_addr(u_int addr)
1210 invalidate_block(addr>>12);
1212 void invalidate_all_pages()
1215 for(page=0;page<4096;page++)
1216 invalidate_page(page);
1217 for(page=0;page<1048576;page++)
1218 if(!invalid_code[page]) {
1219 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1220 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1223 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1226 memset(mini_ht,-1,sizeof(mini_ht));
1230 for(page=0;page<0x100000;page++) {
1231 if(tlb_LUT_r[page]) {
1232 memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1233 if(!tlb_LUT_w[page]||!invalid_code[page])
1234 memory_map[page]|=0x40000000; // Write protect
1236 else memory_map[page]=-1;
1237 if(page==0x80000) page=0xC0000;
1243 // Add an entry to jump_out after making a link
1244 void add_link(u_int vaddr,void *src)
1246 u_int page=get_page(vaddr);
1247 inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1248 ll_add(jump_out+page,vaddr,src);
1249 //int ptr=get_pointer(src);
1250 //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1253 // If a code block was found to be unmodified (bit was set in
1254 // restore_candidate) and it remains unmodified (bit is clear
1255 // in invalid_code) then move the entries for that 4K page from
1256 // the dirty list to the clean list.
1257 void clean_blocks(u_int page)
1259 struct ll_entry *head;
1260 inv_debug("INV: clean_blocks page=%d\n",page);
1261 head=jump_dirty[page];
1263 if(!invalid_code[head->vaddr>>12]) {
1264 // Don't restore blocks which are about to expire from the cache
1265 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1267 if(verify_dirty((int)head->addr)) {
1268 //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1271 get_bounds((int)head->addr,&start,&end);
1272 if(start-(u_int)rdram<RAM_SIZE) {
1273 for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1274 inv|=invalid_code[i];
1277 if((signed int)head->vaddr>=(signed int)0xC0000000) {
1278 u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1279 //printf("addr=%x start=%x end=%x\n",addr,start,end);
1280 if(addr<start||addr>=end) inv=1;
1282 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
1286 void * clean_addr=(void *)get_clean_addr((int)head->addr);
1287 if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1290 if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
1292 inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1293 //printf("page=%x, addr=%x\n",page,head->vaddr);
1294 //assert(head->vaddr>>12==(page|0x80000));
1295 ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1296 int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1298 if(ht_bin[0]==head->vaddr) {
1299 ht_bin[1]=(int)clean_addr; // Replace existing entry
1301 if(ht_bin[2]==head->vaddr) {
1302 ht_bin[3]=(int)clean_addr; // Replace existing entry
1315 void mov_alloc(struct regstat *current,int i)
1317 // Note: Don't need to actually alloc the source registers
1318 if((~current->is32>>rs1[i])&1) {
1319 //alloc_reg64(current,i,rs1[i]);
1320 alloc_reg64(current,i,rt1[i]);
1321 current->is32&=~(1LL<<rt1[i]);
1323 //alloc_reg(current,i,rs1[i]);
1324 alloc_reg(current,i,rt1[i]);
1325 current->is32|=(1LL<<rt1[i]);
1327 clear_const(current,rs1[i]);
1328 clear_const(current,rt1[i]);
1329 dirty_reg(current,rt1[i]);
1332 void shiftimm_alloc(struct regstat *current,int i)
1334 clear_const(current,rs1[i]);
1335 clear_const(current,rt1[i]);
1336 if(opcode2[i]<=0x3) // SLL/SRL/SRA
1339 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1341 alloc_reg(current,i,rt1[i]);
1342 current->is32|=1LL<<rt1[i];
1343 dirty_reg(current,rt1[i]);
1346 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1349 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1350 alloc_reg64(current,i,rt1[i]);
1351 current->is32&=~(1LL<<rt1[i]);
1352 dirty_reg(current,rt1[i]);
1355 if(opcode2[i]==0x3c) // DSLL32
1358 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1359 alloc_reg64(current,i,rt1[i]);
1360 current->is32&=~(1LL<<rt1[i]);
1361 dirty_reg(current,rt1[i]);
1364 if(opcode2[i]==0x3e) // DSRL32
1367 alloc_reg64(current,i,rs1[i]);
1369 alloc_reg64(current,i,rt1[i]);
1370 current->is32&=~(1LL<<rt1[i]);
1372 alloc_reg(current,i,rt1[i]);
1373 current->is32|=1LL<<rt1[i];
1375 dirty_reg(current,rt1[i]);
1378 if(opcode2[i]==0x3f) // DSRA32
1381 alloc_reg64(current,i,rs1[i]);
1382 alloc_reg(current,i,rt1[i]);
1383 current->is32|=1LL<<rt1[i];
1384 dirty_reg(current,rt1[i]);
1389 void shift_alloc(struct regstat *current,int i)
1392 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1394 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1395 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1396 alloc_reg(current,i,rt1[i]);
1397 if(rt1[i]==rs2[i]) alloc_reg_temp(current,i,-1);
1398 current->is32|=1LL<<rt1[i];
1399 } else { // DSLLV/DSRLV/DSRAV
1400 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1401 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1402 alloc_reg64(current,i,rt1[i]);
1403 current->is32&=~(1LL<<rt1[i]);
1404 if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1405 alloc_reg_temp(current,i,-1);
1407 clear_const(current,rs1[i]);
1408 clear_const(current,rs2[i]);
1409 clear_const(current,rt1[i]);
1410 dirty_reg(current,rt1[i]);
1414 void alu_alloc(struct regstat *current,int i)
1416 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1418 if(rs1[i]&&rs2[i]) {
1419 alloc_reg(current,i,rs1[i]);
1420 alloc_reg(current,i,rs2[i]);
1423 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1424 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1426 alloc_reg(current,i,rt1[i]);
1428 current->is32|=1LL<<rt1[i];
1430 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1432 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1434 alloc_reg64(current,i,rs1[i]);
1435 alloc_reg64(current,i,rs2[i]);
1436 alloc_reg(current,i,rt1[i]);
1438 alloc_reg(current,i,rs1[i]);
1439 alloc_reg(current,i,rs2[i]);
1440 alloc_reg(current,i,rt1[i]);
1443 current->is32|=1LL<<rt1[i];
1445 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1447 if(rs1[i]&&rs2[i]) {
1448 alloc_reg(current,i,rs1[i]);
1449 alloc_reg(current,i,rs2[i]);
1453 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1454 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1456 alloc_reg(current,i,rt1[i]);
1457 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1459 if(!((current->uu>>rt1[i])&1)) {
1460 alloc_reg64(current,i,rt1[i]);
1462 if(get_reg(current->regmap,rt1[i]|64)>=0) {
1463 if(rs1[i]&&rs2[i]) {
1464 alloc_reg64(current,i,rs1[i]);
1465 alloc_reg64(current,i,rs2[i]);
1469 // Is is really worth it to keep 64-bit values in registers?
1471 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1472 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1476 current->is32&=~(1LL<<rt1[i]);
1478 current->is32|=1LL<<rt1[i];
1482 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1484 if(rs1[i]&&rs2[i]) {
1485 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1486 alloc_reg64(current,i,rs1[i]);
1487 alloc_reg64(current,i,rs2[i]);
1488 alloc_reg64(current,i,rt1[i]);
1490 alloc_reg(current,i,rs1[i]);
1491 alloc_reg(current,i,rs2[i]);
1492 alloc_reg(current,i,rt1[i]);
1496 alloc_reg(current,i,rt1[i]);
1497 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1498 // DADD used as move, or zeroing
1499 // If we have a 64-bit source, then make the target 64 bits too
1500 if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1501 if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1502 alloc_reg64(current,i,rt1[i]);
1503 } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1504 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1505 alloc_reg64(current,i,rt1[i]);
1507 if(opcode2[i]>=0x2e&&rs2[i]) {
1508 // DSUB used as negation - 64-bit result
1509 // If we have a 32-bit register, extend it to 64 bits
1510 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1511 alloc_reg64(current,i,rt1[i]);
1515 if(rs1[i]&&rs2[i]) {
1516 current->is32&=~(1LL<<rt1[i]);
1518 current->is32&=~(1LL<<rt1[i]);
1519 if((current->is32>>rs1[i])&1)
1520 current->is32|=1LL<<rt1[i];
1522 current->is32&=~(1LL<<rt1[i]);
1523 if((current->is32>>rs2[i])&1)
1524 current->is32|=1LL<<rt1[i];
1526 current->is32|=1LL<<rt1[i];
1530 clear_const(current,rs1[i]);
1531 clear_const(current,rs2[i]);
1532 clear_const(current,rt1[i]);
1533 dirty_reg(current,rt1[i]);
1536 void imm16_alloc(struct regstat *current,int i)
1538 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1540 if(rt1[i]) alloc_reg(current,i,rt1[i]);
1541 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1542 current->is32&=~(1LL<<rt1[i]);
1543 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1544 // TODO: Could preserve the 32-bit flag if the immediate is zero
1545 alloc_reg64(current,i,rt1[i]);
1546 alloc_reg64(current,i,rs1[i]);
1548 clear_const(current,rs1[i]);
1549 clear_const(current,rt1[i]);
1551 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1552 if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1553 current->is32|=1LL<<rt1[i];
1554 clear_const(current,rs1[i]);
1555 clear_const(current,rt1[i]);
1557 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1558 if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1559 if(rs1[i]!=rt1[i]) {
1560 if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1561 alloc_reg64(current,i,rt1[i]);
1562 current->is32&=~(1LL<<rt1[i]);
1565 else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1566 if(is_const(current,rs1[i])) {
1567 int v=get_const(current,rs1[i]);
1568 if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1569 if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1570 if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1572 else clear_const(current,rt1[i]);
1574 else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1575 if(is_const(current,rs1[i])) {
1576 int v=get_const(current,rs1[i]);
1577 set_const(current,rt1[i],v+imm[i]);
1579 else clear_const(current,rt1[i]);
1580 current->is32|=1LL<<rt1[i];
1583 set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1584 current->is32|=1LL<<rt1[i];
1586 dirty_reg(current,rt1[i]);
1589 void load_alloc(struct regstat *current,int i)
1591 clear_const(current,rt1[i]);
1592 //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1593 if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1594 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1596 alloc_reg(current,i,rt1[i]);
1597 if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1599 current->is32&=~(1LL<<rt1[i]);
1600 alloc_reg64(current,i,rt1[i]);
1602 else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1604 current->is32&=~(1LL<<rt1[i]);
1605 alloc_reg64(current,i,rt1[i]);
1606 alloc_all(current,i);
1607 alloc_reg64(current,i,FTEMP);
1609 else current->is32|=1LL<<rt1[i];
1610 dirty_reg(current,rt1[i]);
1611 // If using TLB, need a register for pointer to the mapping table
1612 if(using_tlb) alloc_reg(current,i,TLREG);
1613 // LWL/LWR need a temporary register for the old value
1614 if(opcode[i]==0x22||opcode[i]==0x26)
1616 alloc_reg(current,i,FTEMP);
1617 alloc_reg_temp(current,i,-1);
1622 // Load to r0 (dummy load)
1623 // but we still need a register to calculate the address
1624 alloc_reg_temp(current,i,-1);
1628 void store_alloc(struct regstat *current,int i)
1630 clear_const(current,rs2[i]);
1631 if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1632 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1633 alloc_reg(current,i,rs2[i]);
1634 if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1635 alloc_reg64(current,i,rs2[i]);
1636 if(rs2[i]) alloc_reg(current,i,FTEMP);
1638 // If using TLB, need a register for pointer to the mapping table
1639 if(using_tlb) alloc_reg(current,i,TLREG);
1640 #if defined(HOST_IMM8)
1641 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1642 else alloc_reg(current,i,INVCP);
1644 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
1645 alloc_reg(current,i,FTEMP);
1647 // We need a temporary register for address generation
1648 alloc_reg_temp(current,i,-1);
1651 void c1ls_alloc(struct regstat *current,int i)
1653 //clear_const(current,rs1[i]); // FIXME
1654 clear_const(current,rt1[i]);
1655 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1656 alloc_reg(current,i,CSREG); // Status
1657 alloc_reg(current,i,FTEMP);
1658 if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1659 alloc_reg64(current,i,FTEMP);
1661 // If using TLB, need a register for pointer to the mapping table
1662 if(using_tlb) alloc_reg(current,i,TLREG);
1663 #if defined(HOST_IMM8)
1664 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1665 else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1666 alloc_reg(current,i,INVCP);
1668 // We need a temporary register for address generation
1669 alloc_reg_temp(current,i,-1);
1672 void c2ls_alloc(struct regstat *current,int i)
1674 clear_const(current,rt1[i]);
1675 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1676 alloc_reg(current,i,FTEMP);
1677 // If using TLB, need a register for pointer to the mapping table
1678 if(using_tlb) alloc_reg(current,i,TLREG);
1679 #if defined(HOST_IMM8)
1680 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1681 else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1682 alloc_reg(current,i,INVCP);
1684 // We need a temporary register for address generation
1685 alloc_reg_temp(current,i,-1);
1688 #ifndef multdiv_alloc
1689 void multdiv_alloc(struct regstat *current,int i)
1696 // case 0x1D: DMULTU
1699 clear_const(current,rs1[i]);
1700 clear_const(current,rs2[i]);
1703 if((opcode2[i]&4)==0) // 32-bit
1705 current->u&=~(1LL<<HIREG);
1706 current->u&=~(1LL<<LOREG);
1707 alloc_reg(current,i,HIREG);
1708 alloc_reg(current,i,LOREG);
1709 alloc_reg(current,i,rs1[i]);
1710 alloc_reg(current,i,rs2[i]);
1711 current->is32|=1LL<<HIREG;
1712 current->is32|=1LL<<LOREG;
1713 dirty_reg(current,HIREG);
1714 dirty_reg(current,LOREG);
1718 current->u&=~(1LL<<HIREG);
1719 current->u&=~(1LL<<LOREG);
1720 current->uu&=~(1LL<<HIREG);
1721 current->uu&=~(1LL<<LOREG);
1722 alloc_reg64(current,i,HIREG);
1723 //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1724 alloc_reg64(current,i,rs1[i]);
1725 alloc_reg64(current,i,rs2[i]);
1726 alloc_all(current,i);
1727 current->is32&=~(1LL<<HIREG);
1728 current->is32&=~(1LL<<LOREG);
1729 dirty_reg(current,HIREG);
1730 dirty_reg(current,LOREG);
1735 // Multiply by zero is zero.
1736 // MIPS does not have a divide by zero exception.
1737 // The result is undefined, we return zero.
1738 alloc_reg(current,i,HIREG);
1739 alloc_reg(current,i,LOREG);
1740 current->is32|=1LL<<HIREG;
1741 current->is32|=1LL<<LOREG;
1742 dirty_reg(current,HIREG);
1743 dirty_reg(current,LOREG);
1748 void cop0_alloc(struct regstat *current,int i)
1750 if(opcode2[i]==0) // MFC0
1753 clear_const(current,rt1[i]);
1754 alloc_all(current,i);
1755 alloc_reg(current,i,rt1[i]);
1756 current->is32|=1LL<<rt1[i];
1757 dirty_reg(current,rt1[i]);
1760 else if(opcode2[i]==4) // MTC0
1763 clear_const(current,rs1[i]);
1764 alloc_reg(current,i,rs1[i]);
1765 alloc_all(current,i);
1768 alloc_all(current,i); // FIXME: Keep r0
1770 alloc_reg(current,i,0);
1775 // TLBR/TLBWI/TLBWR/TLBP/ERET
1776 assert(opcode2[i]==0x10);
1777 alloc_all(current,i);
1781 void cop1_alloc(struct regstat *current,int i)
1783 alloc_reg(current,i,CSREG); // Load status
1784 if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1787 clear_const(current,rt1[i]);
1789 alloc_reg64(current,i,rt1[i]); // DMFC1
1790 current->is32&=~(1LL<<rt1[i]);
1792 alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1793 current->is32|=1LL<<rt1[i];
1795 dirty_reg(current,rt1[i]);
1797 alloc_reg_temp(current,i,-1);
1799 else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1802 clear_const(current,rs1[i]);
1804 alloc_reg64(current,i,rs1[i]); // DMTC1
1806 alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1807 alloc_reg_temp(current,i,-1);
1811 alloc_reg(current,i,0);
1812 alloc_reg_temp(current,i,-1);
1816 void fconv_alloc(struct regstat *current,int i)
1818 alloc_reg(current,i,CSREG); // Load status
1819 alloc_reg_temp(current,i,-1);
1821 void float_alloc(struct regstat *current,int i)
1823 alloc_reg(current,i,CSREG); // Load status
1824 alloc_reg_temp(current,i,-1);
1826 void c2op_alloc(struct regstat *current,int i)
1828 alloc_reg_temp(current,i,-1);
1830 void fcomp_alloc(struct regstat *current,int i)
1832 alloc_reg(current,i,CSREG); // Load status
1833 alloc_reg(current,i,FSREG); // Load flags
1834 dirty_reg(current,FSREG); // Flag will be modified
1835 alloc_reg_temp(current,i,-1);
1838 void syscall_alloc(struct regstat *current,int i)
1840 alloc_cc(current,i);
1841 dirty_reg(current,CCREG);
1842 alloc_all(current,i);
1846 void delayslot_alloc(struct regstat *current,int i)
1857 assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1);
1858 printf("Disabled speculative precompilation\n");
1862 imm16_alloc(current,i);
1866 load_alloc(current,i);
1870 store_alloc(current,i);
1873 alu_alloc(current,i);
1876 shift_alloc(current,i);
1879 multdiv_alloc(current,i);
1882 shiftimm_alloc(current,i);
1885 mov_alloc(current,i);
1888 cop0_alloc(current,i);
1892 cop1_alloc(current,i);
1895 c1ls_alloc(current,i);
1898 c2ls_alloc(current,i);
1901 fconv_alloc(current,i);
1904 float_alloc(current,i);
1907 fcomp_alloc(current,i);
1910 c2op_alloc(current,i);
1915 // Special case where a branch and delay slot span two pages in virtual memory
1916 static void pagespan_alloc(struct regstat *current,int i)
1919 current->wasconst=0;
1921 alloc_all(current,i);
1922 alloc_cc(current,i);
1923 dirty_reg(current,CCREG);
1924 if(opcode[i]==3) // JAL
1926 alloc_reg(current,i,31);
1927 dirty_reg(current,31);
1929 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
1931 alloc_reg(current,i,rs1[i]);
1933 alloc_reg(current,i,rt1[i]);
1934 dirty_reg(current,rt1[i]);
1937 if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
1939 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1940 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1941 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1943 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1944 if(rs2[i]) alloc_reg64(current,i,rs2[i]);
1948 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
1950 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1951 if(!((current->is32>>rs1[i])&1))
1953 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1957 if(opcode[i]==0x11) // BC1
1959 alloc_reg(current,i,FSREG);
1960 alloc_reg(current,i,CSREG);
1965 add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
1967 stubs[stubcount][0]=type;
1968 stubs[stubcount][1]=addr;
1969 stubs[stubcount][2]=retaddr;
1970 stubs[stubcount][3]=a;
1971 stubs[stubcount][4]=b;
1972 stubs[stubcount][5]=c;
1973 stubs[stubcount][6]=d;
1974 stubs[stubcount][7]=e;
1978 // Write out a single register
1979 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
1982 for(hr=0;hr<HOST_REGS;hr++) {
1983 if(hr!=EXCLUDE_REG) {
1984 if((regmap[hr]&63)==r) {
1987 emit_storereg(r,hr);
1989 if((is32>>regmap[hr])&1) {
1990 emit_sarimm(hr,31,hr);
1991 emit_storereg(r|64,hr);
1995 emit_storereg(r|64,hr);
2005 //if(!tracedebug) return 0;
2008 for(i=0;i<2097152;i++) {
2009 unsigned int temp=sum;
2012 sum^=((u_int *)rdram)[i];
2021 sum^=((u_int *)reg)[i];
2029 printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2031 #ifndef DISABLE_COP1
2034 printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2044 void memdebug(int i)
2046 //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2047 //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2050 //if(Count>=-2084597794) {
2051 if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2053 printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2054 //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2055 //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2058 printf("TRACE: %x\n",(&i)[-1]);
2062 printf("TRACE: %x \n",(&j)[10]);
2063 printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2067 //printf("TRACE: %x\n",(&i)[-1]);
2070 void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2072 printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2075 void alu_assemble(int i,struct regstat *i_regs)
2077 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2079 signed char s1,s2,t;
2080 t=get_reg(i_regs->regmap,rt1[i]);
2082 s1=get_reg(i_regs->regmap,rs1[i]);
2083 s2=get_reg(i_regs->regmap,rs2[i]);
2084 if(rs1[i]&&rs2[i]) {
2087 if(opcode2[i]&2) emit_sub(s1,s2,t);
2088 else emit_add(s1,s2,t);
2091 if(s1>=0) emit_mov(s1,t);
2092 else emit_loadreg(rs1[i],t);
2096 if(opcode2[i]&2) emit_neg(s2,t);
2097 else emit_mov(s2,t);
2100 emit_loadreg(rs2[i],t);
2101 if(opcode2[i]&2) emit_neg(t,t);
2104 else emit_zeroreg(t);
2108 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2110 signed char s1l,s2l,s1h,s2h,tl,th;
2111 tl=get_reg(i_regs->regmap,rt1[i]);
2112 th=get_reg(i_regs->regmap,rt1[i]|64);
2114 s1l=get_reg(i_regs->regmap,rs1[i]);
2115 s2l=get_reg(i_regs->regmap,rs2[i]);
2116 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2117 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2118 if(rs1[i]&&rs2[i]) {
2121 if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2122 else emit_adds(s1l,s2l,tl);
2124 #ifdef INVERTED_CARRY
2125 if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2127 if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2129 else emit_add(s1h,s2h,th);
2133 if(s1l>=0) emit_mov(s1l,tl);
2134 else emit_loadreg(rs1[i],tl);
2136 if(s1h>=0) emit_mov(s1h,th);
2137 else emit_loadreg(rs1[i]|64,th);
2142 if(opcode2[i]&2) emit_negs(s2l,tl);
2143 else emit_mov(s2l,tl);
2146 emit_loadreg(rs2[i],tl);
2147 if(opcode2[i]&2) emit_negs(tl,tl);
2150 #ifdef INVERTED_CARRY
2151 if(s2h>=0) emit_mov(s2h,th);
2152 else emit_loadreg(rs2[i]|64,th);
2154 emit_adcimm(-1,th); // x86 has inverted carry flag
2159 if(s2h>=0) emit_rscimm(s2h,0,th);
2161 emit_loadreg(rs2[i]|64,th);
2162 emit_rscimm(th,0,th);
2165 if(s2h>=0) emit_mov(s2h,th);
2166 else emit_loadreg(rs2[i]|64,th);
2173 if(th>=0) emit_zeroreg(th);
2178 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2180 signed char s1l,s1h,s2l,s2h,t;
2181 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2183 t=get_reg(i_regs->regmap,rt1[i]);
2186 s1l=get_reg(i_regs->regmap,rs1[i]);
2187 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2188 s2l=get_reg(i_regs->regmap,rs2[i]);
2189 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2190 if(rs2[i]==0) // rx<r0
2193 if(opcode2[i]==0x2a) // SLT
2194 emit_shrimm(s1h,31,t);
2195 else // SLTU (unsigned can not be less than zero)
2198 else if(rs1[i]==0) // r0<rx
2201 if(opcode2[i]==0x2a) // SLT
2202 emit_set_gz64_32(s2h,s2l,t);
2203 else // SLTU (set if not zero)
2204 emit_set_nz64_32(s2h,s2l,t);
2207 assert(s1l>=0);assert(s1h>=0);
2208 assert(s2l>=0);assert(s2h>=0);
2209 if(opcode2[i]==0x2a) // SLT
2210 emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2212 emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2216 t=get_reg(i_regs->regmap,rt1[i]);
2219 s1l=get_reg(i_regs->regmap,rs1[i]);
2220 s2l=get_reg(i_regs->regmap,rs2[i]);
2221 if(rs2[i]==0) // rx<r0
2224 if(opcode2[i]==0x2a) // SLT
2225 emit_shrimm(s1l,31,t);
2226 else // SLTU (unsigned can not be less than zero)
2229 else if(rs1[i]==0) // r0<rx
2232 if(opcode2[i]==0x2a) // SLT
2233 emit_set_gz32(s2l,t);
2234 else // SLTU (set if not zero)
2235 emit_set_nz32(s2l,t);
2238 assert(s1l>=0);assert(s2l>=0);
2239 if(opcode2[i]==0x2a) // SLT
2240 emit_set_if_less32(s1l,s2l,t);
2242 emit_set_if_carry32(s1l,s2l,t);
2248 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2250 signed char s1l,s1h,s2l,s2h,th,tl;
2251 tl=get_reg(i_regs->regmap,rt1[i]);
2252 th=get_reg(i_regs->regmap,rt1[i]|64);
2253 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2257 s1l=get_reg(i_regs->regmap,rs1[i]);
2258 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2259 s2l=get_reg(i_regs->regmap,rs2[i]);
2260 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2261 if(rs1[i]&&rs2[i]) {
2262 assert(s1l>=0);assert(s1h>=0);
2263 assert(s2l>=0);assert(s2h>=0);
2264 if(opcode2[i]==0x24) { // AND
2265 emit_and(s1l,s2l,tl);
2266 emit_and(s1h,s2h,th);
2268 if(opcode2[i]==0x25) { // OR
2269 emit_or(s1l,s2l,tl);
2270 emit_or(s1h,s2h,th);
2272 if(opcode2[i]==0x26) { // XOR
2273 emit_xor(s1l,s2l,tl);
2274 emit_xor(s1h,s2h,th);
2276 if(opcode2[i]==0x27) { // NOR
2277 emit_or(s1l,s2l,tl);
2278 emit_or(s1h,s2h,th);
2285 if(opcode2[i]==0x24) { // AND
2289 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2291 if(s1l>=0) emit_mov(s1l,tl);
2292 else emit_loadreg(rs1[i],tl);
2293 if(s1h>=0) emit_mov(s1h,th);
2294 else emit_loadreg(rs1[i]|64,th);
2298 if(s2l>=0) emit_mov(s2l,tl);
2299 else emit_loadreg(rs2[i],tl);
2300 if(s2h>=0) emit_mov(s2h,th);
2301 else emit_loadreg(rs2[i]|64,th);
2308 if(opcode2[i]==0x27) { // NOR
2310 if(s1l>=0) emit_not(s1l,tl);
2312 emit_loadreg(rs1[i],tl);
2315 if(s1h>=0) emit_not(s1h,th);
2317 emit_loadreg(rs1[i]|64,th);
2323 if(s2l>=0) emit_not(s2l,tl);
2325 emit_loadreg(rs2[i],tl);
2328 if(s2h>=0) emit_not(s2h,th);
2330 emit_loadreg(rs2[i]|64,th);
2346 s1l=get_reg(i_regs->regmap,rs1[i]);
2347 s2l=get_reg(i_regs->regmap,rs2[i]);
2348 if(rs1[i]&&rs2[i]) {
2351 if(opcode2[i]==0x24) { // AND
2352 emit_and(s1l,s2l,tl);
2354 if(opcode2[i]==0x25) { // OR
2355 emit_or(s1l,s2l,tl);
2357 if(opcode2[i]==0x26) { // XOR
2358 emit_xor(s1l,s2l,tl);
2360 if(opcode2[i]==0x27) { // NOR
2361 emit_or(s1l,s2l,tl);
2367 if(opcode2[i]==0x24) { // AND
2370 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2372 if(s1l>=0) emit_mov(s1l,tl);
2373 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2377 if(s2l>=0) emit_mov(s2l,tl);
2378 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2380 else emit_zeroreg(tl);
2382 if(opcode2[i]==0x27) { // NOR
2384 if(s1l>=0) emit_not(s1l,tl);
2386 emit_loadreg(rs1[i],tl);
2392 if(s2l>=0) emit_not(s2l,tl);
2394 emit_loadreg(rs2[i],tl);
2398 else emit_movimm(-1,tl);
2407 void imm16_assemble(int i,struct regstat *i_regs)
2409 if (opcode[i]==0x0f) { // LUI
2412 t=get_reg(i_regs->regmap,rt1[i]);
2415 if(!((i_regs->isconst>>t)&1))
2416 emit_movimm(imm[i]<<16,t);
2420 if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2423 t=get_reg(i_regs->regmap,rt1[i]);
2424 s=get_reg(i_regs->regmap,rs1[i]);
2429 if(!((i_regs->isconst>>t)&1)) {
2431 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2432 emit_addimm(t,imm[i],t);
2434 if(!((i_regs->wasconst>>s)&1))
2435 emit_addimm(s,imm[i],t);
2437 emit_movimm(constmap[i][s]+imm[i],t);
2443 if(!((i_regs->isconst>>t)&1))
2444 emit_movimm(imm[i],t);
2449 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2451 signed char sh,sl,th,tl;
2452 th=get_reg(i_regs->regmap,rt1[i]|64);
2453 tl=get_reg(i_regs->regmap,rt1[i]);
2454 sh=get_reg(i_regs->regmap,rs1[i]|64);
2455 sl=get_reg(i_regs->regmap,rs1[i]);
2461 emit_addimm64_32(sh,sl,imm[i],th,tl);
2464 emit_addimm(sl,imm[i],tl);
2467 emit_movimm(imm[i],tl);
2468 if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2473 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2475 //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2476 signed char sh,sl,t;
2477 t=get_reg(i_regs->regmap,rt1[i]);
2478 sh=get_reg(i_regs->regmap,rs1[i]|64);
2479 sl=get_reg(i_regs->regmap,rs1[i]);
2483 if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2484 if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2485 if(opcode[i]==0x0a) { // SLTI
2487 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2488 emit_slti32(t,imm[i],t);
2490 emit_slti32(sl,imm[i],t);
2495 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2496 emit_sltiu32(t,imm[i],t);
2498 emit_sltiu32(sl,imm[i],t);
2503 if(opcode[i]==0x0a) // SLTI
2504 emit_slti64_32(sh,sl,imm[i],t);
2506 emit_sltiu64_32(sh,sl,imm[i],t);
2509 // SLTI(U) with r0 is just stupid,
2510 // nonetheless examples can be found
2511 if(opcode[i]==0x0a) // SLTI
2512 if(0<imm[i]) emit_movimm(1,t);
2513 else emit_zeroreg(t);
2516 if(imm[i]) emit_movimm(1,t);
2517 else emit_zeroreg(t);
2523 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2525 signed char sh,sl,th,tl;
2526 th=get_reg(i_regs->regmap,rt1[i]|64);
2527 tl=get_reg(i_regs->regmap,rt1[i]);
2528 sh=get_reg(i_regs->regmap,rs1[i]|64);
2529 sl=get_reg(i_regs->regmap,rs1[i]);
2530 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2531 if(opcode[i]==0x0c) //ANDI
2535 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2536 emit_andimm(tl,imm[i],tl);
2538 if(!((i_regs->wasconst>>sl)&1))
2539 emit_andimm(sl,imm[i],tl);
2541 emit_movimm(constmap[i][sl]&imm[i],tl);
2546 if(th>=0) emit_zeroreg(th);
2552 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2556 emit_loadreg(rs1[i]|64,th);
2561 if(opcode[i]==0x0d) //ORI
2563 emit_orimm(tl,imm[i],tl);
2565 if(!((i_regs->wasconst>>sl)&1))
2566 emit_orimm(sl,imm[i],tl);
2568 emit_movimm(constmap[i][sl]|imm[i],tl);
2570 if(opcode[i]==0x0e) //XORI
2572 emit_xorimm(tl,imm[i],tl);
2574 if(!((i_regs->wasconst>>sl)&1))
2575 emit_xorimm(sl,imm[i],tl);
2577 emit_movimm(constmap[i][sl]^imm[i],tl);
2581 emit_movimm(imm[i],tl);
2582 if(th>=0) emit_zeroreg(th);
2590 void shiftimm_assemble(int i,struct regstat *i_regs)
2592 if(opcode2[i]<=0x3) // SLL/SRL/SRA
2596 t=get_reg(i_regs->regmap,rt1[i]);
2597 s=get_reg(i_regs->regmap,rs1[i]);
2606 if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2608 if(opcode2[i]==0) // SLL
2610 emit_shlimm(s<0?t:s,imm[i],t);
2612 if(opcode2[i]==2) // SRL
2614 emit_shrimm(s<0?t:s,imm[i],t);
2616 if(opcode2[i]==3) // SRA
2618 emit_sarimm(s<0?t:s,imm[i],t);
2622 if(s>=0 && s!=t) emit_mov(s,t);
2626 //emit_storereg(rt1[i],t); //DEBUG
2629 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2632 signed char sh,sl,th,tl;
2633 th=get_reg(i_regs->regmap,rt1[i]|64);
2634 tl=get_reg(i_regs->regmap,rt1[i]);
2635 sh=get_reg(i_regs->regmap,rs1[i]|64);
2636 sl=get_reg(i_regs->regmap,rs1[i]);
2641 if(th>=0) emit_zeroreg(th);
2648 if(opcode2[i]==0x38) // DSLL
2650 if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2651 emit_shlimm(sl,imm[i],tl);
2653 if(opcode2[i]==0x3a) // DSRL
2655 emit_shrdimm(sl,sh,imm[i],tl);
2656 if(th>=0) emit_shrimm(sh,imm[i],th);
2658 if(opcode2[i]==0x3b) // DSRA
2660 emit_shrdimm(sl,sh,imm[i],tl);
2661 if(th>=0) emit_sarimm(sh,imm[i],th);
2665 if(sl!=tl) emit_mov(sl,tl);
2666 if(th>=0&&sh!=th) emit_mov(sh,th);
2672 if(opcode2[i]==0x3c) // DSLL32
2675 signed char sl,tl,th;
2676 tl=get_reg(i_regs->regmap,rt1[i]);
2677 th=get_reg(i_regs->regmap,rt1[i]|64);
2678 sl=get_reg(i_regs->regmap,rs1[i]);
2687 emit_shlimm(th,imm[i]&31,th);
2692 if(opcode2[i]==0x3e) // DSRL32
2695 signed char sh,tl,th;
2696 tl=get_reg(i_regs->regmap,rt1[i]);
2697 th=get_reg(i_regs->regmap,rt1[i]|64);
2698 sh=get_reg(i_regs->regmap,rs1[i]|64);
2702 if(th>=0) emit_zeroreg(th);
2705 emit_shrimm(tl,imm[i]&31,tl);
2710 if(opcode2[i]==0x3f) // DSRA32
2714 tl=get_reg(i_regs->regmap,rt1[i]);
2715 sh=get_reg(i_regs->regmap,rs1[i]|64);
2721 emit_sarimm(tl,imm[i]&31,tl);
2728 #ifndef shift_assemble
2729 void shift_assemble(int i,struct regstat *i_regs)
2731 printf("Need shift_assemble for this architecture.\n");
2736 void load_assemble(int i,struct regstat *i_regs)
2738 int s,th,tl,addr,map=-1;
2741 int memtarget=0,c=0;
2743 th=get_reg(i_regs->regmap,rt1[i]|64);
2744 tl=get_reg(i_regs->regmap,rt1[i]);
2745 s=get_reg(i_regs->regmap,rs1[i]);
2747 for(hr=0;hr<HOST_REGS;hr++) {
2748 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2750 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2752 c=(i_regs->wasconst>>s)&1;
2753 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2754 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2756 //printf("load_assemble: c=%d\n",c);
2757 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2758 // FIXME: Even if the load is a NOP, we should check for pagefaults...
2760 if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2762 // could be FIFO, must perform the read
2764 assem_debug("(forced read)\n");
2765 tl=get_reg(i_regs->regmap,-1);
2769 if(offset||s<0||c) addr=tl;
2775 if(th>=0) reglist&=~(1<<th);
2778 //#define R29_HACK 1
2780 // Strmnnrmn's speed hack
2781 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2784 emit_cmpimm(addr,RAM_SIZE);
2786 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2787 // Hint to branch predictor that the branch is unlikely to be taken
2789 emit_jno_unlikely(0);
2797 if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2798 if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2799 map=get_reg(i_regs->regmap,TLREG);
2801 map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2802 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2804 if (opcode[i]==0x20) { // LB
2806 #ifdef HOST_IMM_ADDR32
2808 emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2812 //emit_xorimm(addr,3,tl);
2813 //gen_tlb_addr_r(tl,map);
2814 //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2816 #ifdef BIG_ENDIAN_MIPS
2817 if(!c) emit_xorimm(addr,3,tl);
2818 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2820 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2821 else if (tl!=addr) emit_mov(addr,tl);
2823 emit_movsbl_indexed_tlb(x,tl,map,tl);
2826 add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2829 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2831 if (opcode[i]==0x21) { // LH
2833 #ifdef HOST_IMM_ADDR32
2835 emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2840 #ifdef BIG_ENDIAN_MIPS
2841 if(!c) emit_xorimm(addr,2,tl);
2842 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2844 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2845 else if (tl!=addr) emit_mov(addr,tl);
2848 //emit_movswl_indexed_tlb(x,tl,map,tl);
2851 gen_tlb_addr_r(tl,map);
2852 emit_movswl_indexed(x,tl,tl);
2854 emit_movswl_indexed((int)rdram-0x80000000+x,tl,tl);
2857 add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2860 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2862 if (opcode[i]==0x23) { // LW
2864 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2865 #ifdef HOST_IMM_ADDR32
2867 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2870 emit_readword_indexed_tlb(0,addr,map,tl);
2872 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2875 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2877 if (opcode[i]==0x24) { // LBU
2879 #ifdef HOST_IMM_ADDR32
2881 emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
2885 //emit_xorimm(addr,3,tl);
2886 //gen_tlb_addr_r(tl,map);
2887 //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
2889 #ifdef BIG_ENDIAN_MIPS
2890 if(!c) emit_xorimm(addr,3,tl);
2891 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2893 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2894 else if (tl!=addr) emit_mov(addr,tl);
2896 emit_movzbl_indexed_tlb(x,tl,map,tl);
2899 add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2902 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2904 if (opcode[i]==0x25) { // LHU
2906 #ifdef HOST_IMM_ADDR32
2908 emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
2913 #ifdef BIG_ENDIAN_MIPS
2914 if(!c) emit_xorimm(addr,2,tl);
2915 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2917 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2918 else if (tl!=addr) emit_mov(addr,tl);
2921 //emit_movzwl_indexed_tlb(x,tl,map,tl);
2924 gen_tlb_addr_r(tl,map);
2925 emit_movzwl_indexed(x,tl,tl);
2927 emit_movzwl_indexed((int)rdram-0x80000000+x,tl,tl);
2929 add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2933 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2935 if (opcode[i]==0x27) { // LWU
2938 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2939 #ifdef HOST_IMM_ADDR32
2941 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2944 emit_readword_indexed_tlb(0,addr,map,tl);
2946 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2949 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2953 if (opcode[i]==0x37) { // LD
2955 //gen_tlb_addr_r(tl,map);
2956 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
2957 //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
2958 #ifdef HOST_IMM_ADDR32
2960 emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
2963 emit_readdword_indexed_tlb(0,addr,map,th,tl);
2965 add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2968 inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2970 //emit_storereg(rt1[i],tl); // DEBUG
2972 //if(opcode[i]==0x23)
2973 //if(opcode[i]==0x24)
2974 //if(opcode[i]==0x23||opcode[i]==0x24)
2975 /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
2979 emit_readword((int)&last_count,ECX);
2981 if(get_reg(i_regs->regmap,CCREG)<0)
2982 emit_loadreg(CCREG,HOST_CCREG);
2983 emit_add(HOST_CCREG,ECX,HOST_CCREG);
2984 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
2985 emit_writeword(HOST_CCREG,(int)&Count);
2988 if(get_reg(i_regs->regmap,CCREG)<0)
2989 emit_loadreg(CCREG,0);
2991 emit_mov(HOST_CCREG,0);
2993 emit_addimm(0,2*ccadj[i],0);
2994 emit_writeword(0,(int)&Count);
2996 emit_call((int)memdebug);
2998 restore_regs(0x100f);
3002 #ifndef loadlr_assemble
3003 void loadlr_assemble(int i,struct regstat *i_regs)
3005 printf("Need loadlr_assemble for this architecture.\n");
3010 void store_assemble(int i,struct regstat *i_regs)
3015 int jaddr=0,jaddr2,type;
3016 int memtarget=0,c=0;
3017 int agr=AGEN1+(i&1);
3019 th=get_reg(i_regs->regmap,rs2[i]|64);
3020 tl=get_reg(i_regs->regmap,rs2[i]);
3021 s=get_reg(i_regs->regmap,rs1[i]);
3022 temp=get_reg(i_regs->regmap,agr);
3023 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3026 c=(i_regs->wasconst>>s)&1;
3027 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3028 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3032 for(hr=0;hr<HOST_REGS;hr++) {
3033 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3035 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3036 if(offset||s<0||c) addr=temp;
3041 // Strmnnrmn's speed hack
3043 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3045 emit_cmpimm(addr,RAM_SIZE);
3046 #ifdef DESTRUCTIVE_SHIFT
3047 if(s==addr) emit_mov(s,temp);
3050 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3054 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3055 // Hint to branch predictor that the branch is unlikely to be taken
3057 emit_jno_unlikely(0);
3065 if (opcode[i]==0x28) x=3; // SB
3066 if (opcode[i]==0x29) x=2; // SH
3067 map=get_reg(i_regs->regmap,TLREG);
3069 map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3070 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3073 if (opcode[i]==0x28) { // SB
3076 #ifdef BIG_ENDIAN_MIPS
3077 if(!c) emit_xorimm(addr,3,temp);
3078 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3080 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
3081 else if (addr!=temp) emit_mov(addr,temp);
3083 //gen_tlb_addr_w(temp,map);
3084 //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3085 emit_writebyte_indexed_tlb(tl,x,temp,map,temp);
3089 if (opcode[i]==0x29) { // SH
3092 #ifdef BIG_ENDIAN_MIPS
3093 if(!c) emit_xorimm(addr,2,temp);
3094 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3096 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
3097 else if (addr!=temp) emit_mov(addr,temp);
3100 //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3103 gen_tlb_addr_w(temp,map);
3104 emit_writehword_indexed(tl,x,temp);
3106 emit_writehword_indexed(tl,(int)rdram-0x80000000+x,temp);
3110 if (opcode[i]==0x2B) { // SW
3112 //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3113 emit_writeword_indexed_tlb(tl,0,addr,map,temp);
3116 if (opcode[i]==0x3F) { // SD
3120 //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3121 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3122 emit_writedword_indexed_tlb(th,tl,0,addr,map,temp);
3125 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3126 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3127 emit_writedword_indexed_tlb(tl,tl,0,addr,map,temp);
3132 if(!using_tlb&&(!c||memtarget))
3133 // addr could be a temp, make sure it survives STORE*_STUB
3136 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3137 } else if(!memtarget) {
3138 inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3142 #ifdef DESTRUCTIVE_SHIFT
3143 // The x86 shift operation is 'destructive'; it overwrites the
3144 // source register, so we need to make a copy first and use that.
3147 #if defined(HOST_IMM8)
3148 int ir=get_reg(i_regs->regmap,INVCP);
3150 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3152 emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3156 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3159 //if(opcode[i]==0x2B || opcode[i]==0x3F)
3160 //if(opcode[i]==0x2B || opcode[i]==0x28)
3161 //if(opcode[i]==0x2B || opcode[i]==0x29)
3162 //if(opcode[i]==0x2B)
3163 /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3167 emit_readword((int)&last_count,ECX);
3169 if(get_reg(i_regs->regmap,CCREG)<0)
3170 emit_loadreg(CCREG,HOST_CCREG);
3171 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3172 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3173 emit_writeword(HOST_CCREG,(int)&Count);
3176 if(get_reg(i_regs->regmap,CCREG)<0)
3177 emit_loadreg(CCREG,0);
3179 emit_mov(HOST_CCREG,0);
3181 emit_addimm(0,2*ccadj[i],0);
3182 emit_writeword(0,(int)&Count);
3184 emit_call((int)memdebug);
3186 restore_regs(0x100f);
3190 void storelr_assemble(int i,struct regstat *i_regs)
3197 int case1,case2,case3;
3198 int done0,done1,done2;
3200 int agr=AGEN1+(i&1);
3202 th=get_reg(i_regs->regmap,rs2[i]|64);
3203 tl=get_reg(i_regs->regmap,rs2[i]);
3204 s=get_reg(i_regs->regmap,rs1[i]);
3205 temp=get_reg(i_regs->regmap,agr);
3206 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3209 c=(i_regs->isconst>>s)&1;
3210 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3211 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3214 for(hr=0;hr<HOST_REGS;hr++) {
3215 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3221 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3222 if(!offset&&s!=temp) emit_mov(s,temp);
3228 if(!memtarget||!rs1[i]) {
3233 if((u_int)rdram!=0x80000000)
3234 emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3236 int map=get_reg(i_regs->regmap,TLREG);
3238 map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3239 if(!c&&!offset&&s>=0) emit_mov(s,temp);
3240 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3241 if(!jaddr&&!memtarget) {
3245 gen_tlb_addr_w(temp,map);
3248 if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3249 temp2=get_reg(i_regs->regmap,FTEMP);
3250 if(!rs2[i]) temp2=th=tl;
3253 #ifndef BIG_ENDIAN_MIPS
3254 emit_xorimm(temp,3,temp);
3256 emit_testimm(temp,2);
3259 emit_testimm(temp,1);
3263 if (opcode[i]==0x2A) { // SWL
3264 emit_writeword_indexed(tl,0,temp);
3266 if (opcode[i]==0x2E) { // SWR
3267 emit_writebyte_indexed(tl,3,temp);
3269 if (opcode[i]==0x2C) { // SDL
3270 emit_writeword_indexed(th,0,temp);
3271 if(rs2[i]) emit_mov(tl,temp2);
3273 if (opcode[i]==0x2D) { // SDR
3274 emit_writebyte_indexed(tl,3,temp);
3275 if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3280 set_jump_target(case1,(int)out);
3281 if (opcode[i]==0x2A) { // SWL
3282 // Write 3 msb into three least significant bytes
3283 if(rs2[i]) emit_rorimm(tl,8,tl);
3284 emit_writehword_indexed(tl,-1,temp);
3285 if(rs2[i]) emit_rorimm(tl,16,tl);
3286 emit_writebyte_indexed(tl,1,temp);
3287 if(rs2[i]) emit_rorimm(tl,8,tl);
3289 if (opcode[i]==0x2E) { // SWR
3290 // Write two lsb into two most significant bytes
3291 emit_writehword_indexed(tl,1,temp);
3293 if (opcode[i]==0x2C) { // SDL
3294 if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3295 // Write 3 msb into three least significant bytes
3296 if(rs2[i]) emit_rorimm(th,8,th);
3297 emit_writehword_indexed(th,-1,temp);
3298 if(rs2[i]) emit_rorimm(th,16,th);
3299 emit_writebyte_indexed(th,1,temp);
3300 if(rs2[i]) emit_rorimm(th,8,th);
3302 if (opcode[i]==0x2D) { // SDR
3303 if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3304 // Write two lsb into two most significant bytes
3305 emit_writehword_indexed(tl,1,temp);
3310 set_jump_target(case2,(int)out);
3311 emit_testimm(temp,1);
3314 if (opcode[i]==0x2A) { // SWL
3315 // Write two msb into two least significant bytes
3316 if(rs2[i]) emit_rorimm(tl,16,tl);
3317 emit_writehword_indexed(tl,-2,temp);
3318 if(rs2[i]) emit_rorimm(tl,16,tl);
3320 if (opcode[i]==0x2E) { // SWR
3321 // Write 3 lsb into three most significant bytes
3322 emit_writebyte_indexed(tl,-1,temp);
3323 if(rs2[i]) emit_rorimm(tl,8,tl);
3324 emit_writehword_indexed(tl,0,temp);
3325 if(rs2[i]) emit_rorimm(tl,24,tl);
3327 if (opcode[i]==0x2C) { // SDL
3328 if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3329 // Write two msb into two least significant bytes
3330 if(rs2[i]) emit_rorimm(th,16,th);
3331 emit_writehword_indexed(th,-2,temp);
3332 if(rs2[i]) emit_rorimm(th,16,th);
3334 if (opcode[i]==0x2D) { // SDR
3335 if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3336 // Write 3 lsb into three most significant bytes
3337 emit_writebyte_indexed(tl,-1,temp);
3338 if(rs2[i]) emit_rorimm(tl,8,tl);
3339 emit_writehword_indexed(tl,0,temp);
3340 if(rs2[i]) emit_rorimm(tl,24,tl);
3345 set_jump_target(case3,(int)out);
3346 if (opcode[i]==0x2A) { // SWL
3347 // Write msb into least significant byte
3348 if(rs2[i]) emit_rorimm(tl,24,tl);
3349 emit_writebyte_indexed(tl,-3,temp);
3350 if(rs2[i]) emit_rorimm(tl,8,tl);
3352 if (opcode[i]==0x2E) { // SWR
3353 // Write entire word
3354 emit_writeword_indexed(tl,-3,temp);
3356 if (opcode[i]==0x2C) { // SDL
3357 if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3358 // Write msb into least significant byte
3359 if(rs2[i]) emit_rorimm(th,24,th);
3360 emit_writebyte_indexed(th,-3,temp);
3361 if(rs2[i]) emit_rorimm(th,8,th);
3363 if (opcode[i]==0x2D) { // SDR
3364 if(rs2[i]) emit_mov(th,temp2);
3365 // Write entire word
3366 emit_writeword_indexed(tl,-3,temp);
3368 set_jump_target(done0,(int)out);
3369 set_jump_target(done1,(int)out);
3370 set_jump_target(done2,(int)out);
3371 if (opcode[i]==0x2C) { // SDL
3372 emit_testimm(temp,4);
3375 emit_andimm(temp,~3,temp);
3376 emit_writeword_indexed(temp2,4,temp);
3377 set_jump_target(done0,(int)out);
3379 if (opcode[i]==0x2D) { // SDR
3380 emit_testimm(temp,4);
3383 emit_andimm(temp,~3,temp);
3384 emit_writeword_indexed(temp2,-4,temp);
3385 set_jump_target(done0,(int)out);
3388 add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
3391 emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
3392 #if defined(HOST_IMM8)
3393 int ir=get_reg(i_regs->regmap,INVCP);
3395 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3397 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3401 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3405 //save_regs(0x100f);
3406 emit_readword((int)&last_count,ECX);
3407 if(get_reg(i_regs->regmap,CCREG)<0)
3408 emit_loadreg(CCREG,HOST_CCREG);
3409 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3410 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3411 emit_writeword(HOST_CCREG,(int)&Count);
3412 emit_call((int)memdebug);
3414 //restore_regs(0x100f);
3418 void c1ls_assemble(int i,struct regstat *i_regs)
3420 #ifndef DISABLE_COP1
3426 int jaddr,jaddr2=0,jaddr3,type;
3427 int agr=AGEN1+(i&1);
3429 th=get_reg(i_regs->regmap,FTEMP|64);
3430 tl=get_reg(i_regs->regmap,FTEMP);
3431 s=get_reg(i_regs->regmap,rs1[i]);
3432 temp=get_reg(i_regs->regmap,agr);
3433 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3438 for(hr=0;hr<HOST_REGS;hr++) {
3439 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3441 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3442 if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3444 // Loads use a temporary register which we need to save
3447 if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3451 //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3452 //else c=(i_regs->wasconst>>s)&1;
3453 if(s>=0) c=(i_regs->wasconst>>s)&1;
3454 // Check cop1 unusable
3456 signed char rs=get_reg(i_regs->regmap,CSREG);
3458 emit_testimm(rs,0x20000000);
3461 add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3464 if (opcode[i]==0x39) { // SWC1 (get float address)
3465 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],tl);
3467 if (opcode[i]==0x3D) { // SDC1 (get double address)
3468 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],tl);
3470 // Generate address + offset
3473 emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3477 map=get_reg(i_regs->regmap,TLREG);
3479 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3480 map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
3482 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3483 map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
3486 if (opcode[i]==0x39) { // SWC1 (read float)
3487 emit_readword_indexed(0,tl,tl);
3489 if (opcode[i]==0x3D) { // SDC1 (read double)
3490 emit_readword_indexed(4,tl,th);
3491 emit_readword_indexed(0,tl,tl);
3493 if (opcode[i]==0x31) { // LWC1 (get target address)
3494 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],temp);
3496 if (opcode[i]==0x35) { // LDC1 (get target address)
3497 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],temp);
3504 else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80000000+RAM_SIZE) {
3506 emit_jmp(0); // inline_readstub/inline_writestub? Very rare case
3508 #ifdef DESTRUCTIVE_SHIFT
3509 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3510 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3514 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3515 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3517 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3518 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3521 if (opcode[i]==0x31) { // LWC1
3522 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3523 //gen_tlb_addr_r(ar,map);
3524 //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3525 #ifdef HOST_IMM_ADDR32
3526 if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3529 emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3532 if (opcode[i]==0x35) { // LDC1
3534 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3535 //gen_tlb_addr_r(ar,map);
3536 //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3537 //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3538 #ifdef HOST_IMM_ADDR32
3539 if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3542 emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3545 if (opcode[i]==0x39) { // SWC1
3546 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3547 emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3550 if (opcode[i]==0x3D) { // SDC1
3552 //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3553 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3554 emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3558 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3559 #ifndef DESTRUCTIVE_SHIFT
3560 temp=offset||c||s<0?ar:s;
3562 #if defined(HOST_IMM8)
3563 int ir=get_reg(i_regs->regmap,INVCP);
3565 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3567 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3571 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3574 if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3575 if (opcode[i]==0x31) { // LWC1 (write float)
3576 emit_writeword_indexed(tl,0,temp);
3578 if (opcode[i]==0x35) { // LDC1 (write double)
3579 emit_writeword_indexed(th,4,temp);
3580 emit_writeword_indexed(tl,0,temp);
3582 //if(opcode[i]==0x39)
3583 /*if(opcode[i]==0x39||opcode[i]==0x31)
3586 emit_readword((int)&last_count,ECX);
3587 if(get_reg(i_regs->regmap,CCREG)<0)
3588 emit_loadreg(CCREG,HOST_CCREG);
3589 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3590 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3591 emit_writeword(HOST_CCREG,(int)&Count);
3592 emit_call((int)memdebug);
3596 cop1_unusable(i, i_regs);
3600 void c2ls_assemble(int i,struct regstat *i_regs)
3605 int memtarget=0,c=0;
3606 int jaddr,jaddr2=0,jaddr3,type;
3607 int agr=AGEN1+(i&1);
3609 u_int copr=(source[i]>>16)&0x1f;
3610 s=get_reg(i_regs->regmap,rs1[i]);
3611 tl=get_reg(i_regs->regmap,FTEMP);
3617 for(hr=0;hr<HOST_REGS;hr++) {
3618 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3620 if(i_regs->regmap[HOST_CCREG]==CCREG)
3621 reglist&=~(1<<HOST_CCREG);
3624 if (opcode[i]==0x3a) { // SWC2
3625 ar=get_reg(i_regs->regmap,agr);
3626 if(ar<0) ar=get_reg(i_regs->regmap,-1);
3631 if(s>=0) c=(i_regs->wasconst>>s)&1;
3632 memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
3633 if (!offset&&!c&&s>=0) ar=s;
3636 if (opcode[i]==0x3a) { // SWC2
3637 cop2_get_dreg(copr,tl,HOST_TEMPREG);
3645 emit_jmp(0); // inline_readstub/inline_writestub?
3649 emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3653 if (opcode[i]==0x32) { // LWC2
3654 #ifdef HOST_IMM_ADDR32
3655 if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
3658 emit_readword_indexed(0,ar,tl);
3660 if (opcode[i]==0x3a) { // SWC2
3661 #ifdef DESTRUCTIVE_SHIFT
3662 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3664 emit_writeword_indexed(tl,0,ar);
3668 add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist);
3669 if (opcode[i]==0x3a) { // SWC2
3670 #if defined(HOST_IMM8)
3671 int ir=get_reg(i_regs->regmap,INVCP);
3673 emit_cmpmem_indexedsr12_reg(ir,ar,1);
3675 emit_cmpmem_indexedsr12_imm((int)invalid_code,ar,1);
3679 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),ar,0,0,0);
3681 if (opcode[i]==0x32) { // LWC2
3682 cop2_put_dreg(copr,tl,HOST_TEMPREG);
3686 #ifndef multdiv_assemble
3687 void multdiv_assemble(int i,struct regstat *i_regs)
3689 printf("Need multdiv_assemble for this architecture.\n");
3694 void mov_assemble(int i,struct regstat *i_regs)
3696 //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3697 //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
3700 signed char sh,sl,th,tl;
3701 th=get_reg(i_regs->regmap,rt1[i]|64);
3702 tl=get_reg(i_regs->regmap,rt1[i]);
3705 sh=get_reg(i_regs->regmap,rs1[i]|64);
3706 sl=get_reg(i_regs->regmap,rs1[i]);
3707 if(sl>=0) emit_mov(sl,tl);
3708 else emit_loadreg(rs1[i],tl);
3710 if(sh>=0) emit_mov(sh,th);
3711 else emit_loadreg(rs1[i]|64,th);
3717 #ifndef fconv_assemble
3718 void fconv_assemble(int i,struct regstat *i_regs)
3720 printf("Need fconv_assemble for this architecture.\n");
3726 void float_assemble(int i,struct regstat *i_regs)
3728 printf("Need float_assemble for this architecture.\n");
3733 void syscall_assemble(int i,struct regstat *i_regs)
3735 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3736 assert(ccreg==HOST_CCREG);
3737 assert(!is_delayslot);
3738 emit_movimm(start+i*4,EAX); // Get PC
3739 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
3740 emit_jmp((int)jump_syscall_hle); // XXX
3743 void hlecall_assemble(int i,struct regstat *i_regs)
3745 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3746 assert(ccreg==HOST_CCREG);
3747 assert(!is_delayslot);
3748 emit_movimm(start+i*4+4,0); // Get PC
3749 emit_movimm((int)psxHLEt[source[i]&7],1);
3750 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // XXX
3751 emit_jmp((int)jump_hlecall);
3754 void intcall_assemble(int i,struct regstat *i_regs)
3756 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3757 assert(ccreg==HOST_CCREG);
3758 assert(!is_delayslot);
3759 emit_movimm(start+i*4,0); // Get PC
3760 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG);
3761 emit_jmp((int)jump_intcall);
3764 void ds_assemble(int i,struct regstat *i_regs)
3769 alu_assemble(i,i_regs);break;
3771 imm16_assemble(i,i_regs);break;
3773 shift_assemble(i,i_regs);break;
3775 shiftimm_assemble(i,i_regs);break;
3777 load_assemble(i,i_regs);break;
3779 loadlr_assemble(i,i_regs);break;
3781 store_assemble(i,i_regs);break;
3783 storelr_assemble(i,i_regs);break;
3785 cop0_assemble(i,i_regs);break;
3787 cop1_assemble(i,i_regs);break;
3789 c1ls_assemble(i,i_regs);break;
3791 cop2_assemble(i,i_regs);break;
3793 c2ls_assemble(i,i_regs);break;
3795 c2op_assemble(i,i_regs);break;
3797 fconv_assemble(i,i_regs);break;
3799 float_assemble(i,i_regs);break;
3801 fcomp_assemble(i,i_regs);break;
3803 multdiv_assemble(i,i_regs);break;
3805 mov_assemble(i,i_regs);break;
3815 printf("Jump in the delay slot. This is probably a bug.\n");
3820 // Is the branch target a valid internal jump?
3821 int internal_branch(uint64_t i_is32,int addr)
3823 if(addr&1) return 0; // Indirect (register) jump
3824 if(addr>=start && addr<start+slen*4-4)
3826 int t=(addr-start)>>2;
3827 // Delay slots are not valid branch targets
3828 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
3829 // 64 -> 32 bit transition requires a recompile
3830 /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
3832 if(requires_32bit[t]&~i_is32) printf("optimizable: no\n");
3833 else printf("optimizable: yes\n");
3835 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
3836 if(requires_32bit[t]&~i_is32) return 0;
3842 #ifndef wb_invalidate
3843 void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
3844 uint64_t u,uint64_t uu)
3847 for(hr=0;hr<HOST_REGS;hr++) {
3848 if(hr!=EXCLUDE_REG) {
3849 if(pre[hr]!=entry[hr]) {
3852 if(get_reg(entry,pre[hr])<0) {
3854 if(!((u>>pre[hr])&1)) {
3855 emit_storereg(pre[hr],hr);
3856 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
3857 emit_sarimm(hr,31,hr);
3858 emit_storereg(pre[hr]|64,hr);
3862 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
3863 emit_storereg(pre[hr],hr);
3872 // Move from one register to another (no writeback)
3873 for(hr=0;hr<HOST_REGS;hr++) {
3874 if(hr!=EXCLUDE_REG) {
3875 if(pre[hr]!=entry[hr]) {
3876 if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
3878 if((nr=get_reg(entry,pre[hr]))>=0) {
3888 // Load the specified registers
3889 // This only loads the registers given as arguments because
3890 // we don't want to load things that will be overwritten
3891 void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
3895 for(hr=0;hr<HOST_REGS;hr++) {
3896 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
3897 if(entry[hr]!=regmap[hr]) {
3898 if(regmap[hr]==rs1||regmap[hr]==rs2)
3905 emit_loadreg(regmap[hr],hr);
3912 for(hr=0;hr<HOST_REGS;hr++) {
3913 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
3914 if(entry[hr]!=regmap[hr]) {
3915 if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
3917 assert(regmap[hr]!=64);
3918 if((is32>>(regmap[hr]&63))&1) {
3919 int lr=get_reg(regmap,regmap[hr]-64);
3921 emit_sarimm(lr,31,hr);
3923 emit_loadreg(regmap[hr],hr);
3927 emit_loadreg(regmap[hr],hr);
3935 // Load registers prior to the start of a loop
3936 // so that they are not loaded within the loop
3937 static void loop_preload(signed char pre[],signed char entry[])
3940 for(hr=0;hr<HOST_REGS;hr++) {
3941 if(hr!=EXCLUDE_REG) {
3942 if(pre[hr]!=entry[hr]) {
3944 if(get_reg(pre,entry[hr])<0) {
3945 assem_debug("loop preload:\n");
3946 //printf("loop preload: %d\n",hr);
3950 else if(entry[hr]<TEMPREG)
3952 emit_loadreg(entry[hr],hr);
3954 else if(entry[hr]-64<TEMPREG)
3956 emit_loadreg(entry[hr],hr);
3965 // Generate address for load/store instruction
3966 // goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
3967 void address_generation(int i,struct regstat *i_regs,signed char entry[])
3969 if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS||itype[i]==C2LS) {
3971 int agr=AGEN1+(i&1);
3972 int mgr=MGEN1+(i&1);
3973 if(itype[i]==LOAD) {
3974 ra=get_reg(i_regs->regmap,rt1[i]);
3975 //if(rt1[i]) assert(ra>=0);
3977 if(itype[i]==LOADLR) {
3978 ra=get_reg(i_regs->regmap,FTEMP);
3980 if(itype[i]==STORE||itype[i]==STORELR) {
3981 ra=get_reg(i_regs->regmap,agr);
3982 if(ra<0) ra=get_reg(i_regs->regmap,-1);
3984 if(itype[i]==C1LS||itype[i]==C2LS) {
3985 if ((opcode[i]&0x3b)==0x31||(opcode[i]&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
3986 ra=get_reg(i_regs->regmap,FTEMP);
3987 else { // SWC1/SDC1/SWC2/SDC2
3988 ra=get_reg(i_regs->regmap,agr);
3989 if(ra<0) ra=get_reg(i_regs->regmap,-1);
3992 int rs=get_reg(i_regs->regmap,rs1[i]);
3993 int rm=get_reg(i_regs->regmap,TLREG);
3996 int c=(i_regs->wasconst>>rs)&1;
3998 // Using r0 as a base address
4000 if(!entry||entry[rm]!=mgr) {
4001 generate_map_const(offset,rm);
4002 } // else did it in the previous cycle
4004 if(!entry||entry[ra]!=agr) {
4005 if (opcode[i]==0x22||opcode[i]==0x26) {
4006 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4007 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4008 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4010 emit_movimm(offset,ra);
4012 } // else did it in the previous cycle
4015 if(!entry||entry[ra]!=rs1[i])
4016 emit_loadreg(rs1[i],ra);
4017 //if(!entry||entry[ra]!=rs1[i])
4018 // printf("poor load scheduling!\n");
4022 if(!entry||entry[rm]!=mgr) {
4023 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a) {
4024 // Stores to memory go thru the mapper to detect self-modifying
4025 // code, loads don't.
4026 if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
4027 (unsigned int)(constmap[i][rs]+offset)<0x80000000+RAM_SIZE )
4028 generate_map_const(constmap[i][rs]+offset,rm);
4030 if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
4031 generate_map_const(constmap[i][rs]+offset,rm);
4035 if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
4036 if(!entry||entry[ra]!=agr) {
4037 if (opcode[i]==0x22||opcode[i]==0x26) {
4038 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4039 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4040 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4042 #ifdef HOST_IMM_ADDR32
4043 if((itype[i]!=LOAD&&(opcode[i]&0x3b)!=0x31&&(opcode[i]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4044 (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
4046 emit_movimm(constmap[i][rs]+offset,ra);
4048 } // else did it in the previous cycle
4049 } // else load_consts already did it
4051 if(offset&&!c&&rs1[i]) {
4053 emit_addimm(rs,offset,ra);
4055 emit_addimm(ra,offset,ra);
4060 // Preload constants for next instruction
4061 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
4063 #ifndef HOST_IMM_ADDR32
4065 agr=MGEN1+((i+1)&1);
4066 ra=get_reg(i_regs->regmap,agr);
4068 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4069 int offset=imm[i+1];
4070 int c=(regs[i+1].wasconst>>rs)&1;
4072 if(itype[i+1]==STORE||itype[i+1]==STORELR
4073 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1, SWC2/SDC2
4074 // Stores to memory go thru the mapper to detect self-modifying
4075 // code, loads don't.
4076 if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
4077 (unsigned int)(constmap[i+1][rs]+offset)<0x80000000+RAM_SIZE )
4078 generate_map_const(constmap[i+1][rs]+offset,ra);
4080 if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
4081 generate_map_const(constmap[i+1][rs]+offset,ra);
4084 /*else if(rs1[i]==0) {
4085 generate_map_const(offset,ra);
4090 agr=AGEN1+((i+1)&1);
4091 ra=get_reg(i_regs->regmap,agr);
4093 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4094 int offset=imm[i+1];
4095 int c=(regs[i+1].wasconst>>rs)&1;
4096 if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
4097 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4098 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4099 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4100 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4102 #ifdef HOST_IMM_ADDR32
4103 if((itype[i+1]!=LOAD&&(opcode[i+1]&0x3b)!=0x31&&(opcode[i+1]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4104 (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000))
4106 emit_movimm(constmap[i+1][rs]+offset,ra);
4109 else if(rs1[i+1]==0) {
4110 // Using r0 as a base address
4111 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4112 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4113 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4114 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4116 emit_movimm(offset,ra);
4123 int get_final_value(int hr, int i, int *value)
4125 int reg=regs[i].regmap[hr];
4127 if(regs[i+1].regmap[hr]!=reg) break;
4128 if(!((regs[i+1].isconst>>hr)&1)) break;
4133 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
4134 *value=constmap[i][hr];
4138 if(itype[i+1]==UJUMP||itype[i+1]==RJUMP||itype[i+1]==CJUMP||itype[i+1]==SJUMP) {
4139 // Load in delay slot, out-of-order execution
4140 if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
4142 #ifdef HOST_IMM_ADDR32
4143 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+2])<(signed int)0xC0000000) return 0;
4145 // Precompute load address
4146 *value=constmap[i][hr]+imm[i+2];
4150 if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)
4152 #ifdef HOST_IMM_ADDR32
4153 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+1])<(signed int)0xC0000000) return 0;
4155 // Precompute load address
4156 *value=constmap[i][hr]+imm[i+1];
4157 //printf("c=%x imm=%x\n",(int)constmap[i][hr],imm[i+1]);
4162 *value=constmap[i][hr];
4163 //printf("c=%x\n",(int)constmap[i][hr]);
4164 if(i==slen-1) return 1;
4166 return !((unneeded_reg[i+1]>>reg)&1);
4168 return !((unneeded_reg_upper[i+1]>>reg)&1);
4172 // Load registers with known constants
4173 void load_consts(signed char pre[],signed char regmap[],int is32,int i)
4177 for(hr=0;hr<HOST_REGS;hr++) {
4178 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4179 //if(entry[hr]!=regmap[hr]) {
4180 if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4181 if(((regs[i].isconst>>hr)&1)&®map[hr]<64&®map[hr]>0) {
4183 if(get_final_value(hr,i,&value)) {
4188 emit_movimm(value,hr);
4196 for(hr=0;hr<HOST_REGS;hr++) {
4197 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4198 //if(entry[hr]!=regmap[hr]) {
4199 if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4200 if(((regs[i].isconst>>hr)&1)&®map[hr]>64) {
4201 if((is32>>(regmap[hr]&63))&1) {
4202 int lr=get_reg(regmap,regmap[hr]-64);
4204 emit_sarimm(lr,31,hr);
4209 if(get_final_value(hr,i,&value)) {
4214 emit_movimm(value,hr);
4223 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i)
4227 for(hr=0;hr<HOST_REGS;hr++) {
4228 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) {
4229 if(((regs[i].isconst>>hr)&1)&®map[hr]<64&®map[hr]>0) {
4230 int value=constmap[i][hr];
4235 emit_movimm(value,hr);
4241 for(hr=0;hr<HOST_REGS;hr++) {
4242 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) {
4243 if(((regs[i].isconst>>hr)&1)&®map[hr]>64) {
4244 if((is32>>(regmap[hr]&63))&1) {
4245 int lr=get_reg(regmap,regmap[hr]-64);
4247 emit_sarimm(lr,31,hr);
4251 int value=constmap[i][hr];
4256 emit_movimm(value,hr);
4264 // Write out all dirty registers (except cycle count)
4265 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty)
4268 for(hr=0;hr<HOST_REGS;hr++) {
4269 if(hr!=EXCLUDE_REG) {
4270 if(i_regmap[hr]>0) {
4271 if(i_regmap[hr]!=CCREG) {
4272 if((i_dirty>>hr)&1) {
4273 if(i_regmap[hr]<64) {
4274 emit_storereg(i_regmap[hr],hr);
4276 if( ((i_is32>>i_regmap[hr])&1) ) {
4277 #ifdef DESTRUCTIVE_WRITEBACK
4278 emit_sarimm(hr,31,hr);
4279 emit_storereg(i_regmap[hr]|64,hr);
4281 emit_sarimm(hr,31,HOST_TEMPREG);
4282 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4287 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4288 emit_storereg(i_regmap[hr],hr);
4297 // Write out dirty registers that we need to reload (pair with load_needed_regs)
4298 // This writes the registers not written by store_regs_bt
4299 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4302 int t=(addr-start)>>2;
4303 for(hr=0;hr<HOST_REGS;hr++) {
4304 if(hr!=EXCLUDE_REG) {
4305 if(i_regmap[hr]>0) {
4306 if(i_regmap[hr]!=CCREG) {
4307 if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1) && !(((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4308 if((i_dirty>>hr)&1) {
4309 if(i_regmap[hr]<64) {
4310 emit_storereg(i_regmap[hr],hr);
4312 if( ((i_is32>>i_regmap[hr])&1) ) {
4313 #ifdef DESTRUCTIVE_WRITEBACK
4314 emit_sarimm(hr,31,hr);
4315 emit_storereg(i_regmap[hr]|64,hr);
4317 emit_sarimm(hr,31,HOST_TEMPREG);
4318 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4323 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4324 emit_storereg(i_regmap[hr],hr);
4335 // Load all registers (except cycle count)
4336 void load_all_regs(signed char i_regmap[])
4339 for(hr=0;hr<HOST_REGS;hr++) {
4340 if(hr!=EXCLUDE_REG) {
4341 if(i_regmap[hr]==0) {
4345 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG)
4347 emit_loadreg(i_regmap[hr],hr);
4353 // Load all current registers also needed by next instruction
4354 void load_needed_regs(signed char i_regmap[],signed char next_regmap[])
4357 for(hr=0;hr<HOST_REGS;hr++) {
4358 if(hr!=EXCLUDE_REG) {
4359 if(get_reg(next_regmap,i_regmap[hr])>=0) {
4360 if(i_regmap[hr]==0) {
4364 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG)
4366 emit_loadreg(i_regmap[hr],hr);
4373 // Load all regs, storing cycle count if necessary
4374 void load_regs_entry(int t)
4377 if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER,HOST_CCREG);
4378 else if(ccadj[t]) emit_addimm(HOST_CCREG,-ccadj[t]*CLOCK_DIVIDER,HOST_CCREG);
4379 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4380 emit_storereg(CCREG,HOST_CCREG);
4383 for(hr=0;hr<HOST_REGS;hr++) {
4384 if(regs[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<64) {
4385 if(regs[t].regmap_entry[hr]==0) {
4388 else if(regs[t].regmap_entry[hr]!=CCREG)
4390 emit_loadreg(regs[t].regmap_entry[hr],hr);
4395 for(hr=0;hr<HOST_REGS;hr++) {
4396 if(regs[t].regmap_entry[hr]>=64) {
4397 assert(regs[t].regmap_entry[hr]!=64);
4398 if((regs[t].was32>>(regs[t].regmap_entry[hr]&63))&1) {
4399 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4401 emit_loadreg(regs[t].regmap_entry[hr],hr);
4405 emit_sarimm(lr,31,hr);
4410 emit_loadreg(regs[t].regmap_entry[hr],hr);
4416 // Store dirty registers prior to branch
4417 void store_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4419 if(internal_branch(i_is32,addr))
4421 int t=(addr-start)>>2;
4423 for(hr=0;hr<HOST_REGS;hr++) {
4424 if(hr!=EXCLUDE_REG) {
4425 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4426 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4427 if((i_dirty>>hr)&1) {
4428 if(i_regmap[hr]<64) {
4429 if(!((unneeded_reg[t]>>i_regmap[hr])&1)) {
4430 emit_storereg(i_regmap[hr],hr);
4431 if( ((i_is32>>i_regmap[hr])&1) && !((unneeded_reg_upper[t]>>i_regmap[hr])&1) ) {
4432 #ifdef DESTRUCTIVE_WRITEBACK
4433 emit_sarimm(hr,31,hr);
4434 emit_storereg(i_regmap[hr]|64,hr);
4436 emit_sarimm(hr,31,HOST_TEMPREG);
4437 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4442 if( !((i_is32>>(i_regmap[hr]&63))&1) && !((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1) ) {
4443 emit_storereg(i_regmap[hr],hr);
4454 // Branch out of this block, write out all dirty regs
4455 wb_dirtys(i_regmap,i_is32,i_dirty);
4459 // Load all needed registers for branch target
4460 void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4462 //if(addr>=start && addr<(start+slen*4))
4463 if(internal_branch(i_is32,addr))
4465 int t=(addr-start)>>2;
4467 // Store the cycle count before loading something else
4468 if(i_regmap[HOST_CCREG]!=CCREG) {
4469 assert(i_regmap[HOST_CCREG]==-1);
4471 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4472 emit_storereg(CCREG,HOST_CCREG);
4475 for(hr=0;hr<HOST_REGS;hr++) {
4476 if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<64) {
4477 #ifdef DESTRUCTIVE_WRITEBACK
4478 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || ( !((regs[t].dirty>>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4480 if(i_regmap[hr]!=regs[t].regmap_entry[hr] ) {
4482 if(regs[t].regmap_entry[hr]==0) {
4485 else if(regs[t].regmap_entry[hr]!=CCREG)
4487 emit_loadreg(regs[t].regmap_entry[hr],hr);
4493 for(hr=0;hr<HOST_REGS;hr++) {
4494 if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=64) {
4495 if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4496 assert(regs[t].regmap_entry[hr]!=64);
4497 if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4498 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4500 emit_loadreg(regs[t].regmap_entry[hr],hr);
4504 emit_sarimm(lr,31,hr);
4509 emit_loadreg(regs[t].regmap_entry[hr],hr);
4512 else if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4513 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4515 emit_sarimm(lr,31,hr);
4522 int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4524 if(addr>=start && addr<start+slen*4-4)
4526 int t=(addr-start)>>2;
4528 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4529 for(hr=0;hr<HOST_REGS;hr++)
4533 if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4535 if(regs[t].regmap_entry[hr]!=-1)
4544 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4549 if(!((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1))
4554 else // Same register but is it 32-bit or dirty?
4557 if(!((regs[t].dirty>>hr)&1))
4561 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4563 //printf("%x: dirty no match\n",addr);
4568 if((((regs[t].was32^i_is32)&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)
4570 //printf("%x: is32 no match\n",addr);
4576 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4577 if(requires_32bit[t]&~i_is32) return 0;
4578 // Delay slots are not valid branch targets
4579 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4580 // Delay slots require additional processing, so do not match
4581 if(is_ds[t]) return 0;
4586 for(hr=0;hr<HOST_REGS;hr++)
4592 if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4606 // Used when a branch jumps into the delay slot of another branch
4607 void ds_assemble_entry(int i)
4609 int t=(ba[i]-start)>>2;
4610 if(!instr_addr[t]) instr_addr[t]=(u_int)out;
4611 assem_debug("Assemble delay slot at %x\n",ba[i]);
4612 assem_debug("<->\n");
4613 if(regs[t].regmap_entry[HOST_CCREG]==CCREG&®s[t].regmap[HOST_CCREG]!=CCREG)
4614 wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty,regs[t].was32);
4615 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,rs1[t],rs2[t]);
4616 address_generation(t,®s[t],regs[t].regmap_entry);
4617 if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39||(opcode[t]&0x3b)==0x3a)
4618 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,INVCP,INVCP);
4623 alu_assemble(t,®s[t]);break;
4625 imm16_assemble(t,®s[t]);break;
4627 shift_assemble(t,®s[t]);break;
4629 shiftimm_assemble(t,®s[t]);break;
4631 load_assemble(t,®s[t]);break;
4633 loadlr_assemble(t,®s[t]);break;
4635 store_assemble(t,®s[t]);break;
4637 storelr_assemble(t,®s[t]);break;
4639 cop0_assemble(t,®s[t]);break;
4641 cop1_assemble(t,®s[t]);break;
4643 c1ls_assemble(t,®s[t]);break;
4645 cop2_assemble(t,®s[t]);break;
4647 c2ls_assemble(t,®s[t]);break;
4649 c2op_assemble(t,®s[t]);break;
4651 fconv_assemble(t,®s[t]);break;
4653 float_assemble(t,®s[t]);break;
4655 fcomp_assemble(t,®s[t]);break;
4657 multdiv_assemble(t,®s[t]);break;
4659 mov_assemble(t,®s[t]);break;
4669 printf("Jump in the delay slot. This is probably a bug.\n");
4671 store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4672 load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4673 if(internal_branch(regs[t].is32,ba[i]+4))
4674 assem_debug("branch: internal\n");
4676 assem_debug("branch: external\n");
4677 assert(internal_branch(regs[t].is32,ba[i]+4));
4678 add_to_linker((int)out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4));
4682 void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
4691 //if(ba[i]>=start && ba[i]<(start+slen*4))
4692 if(internal_branch(branch_regs[i].is32,ba[i]))
4694 int t=(ba[i]-start)>>2;
4695 if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
4703 if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4705 if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
4707 //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4708 emit_andimm(HOST_CCREG,3,HOST_CCREG);
4712 else if(*adj==0||invert) {
4713 emit_addimm_and_set_flags(CLOCK_DIVIDER*(count+2),HOST_CCREG);
4719 emit_cmpimm(HOST_CCREG,-2*(count+2));
4723 add_stub(CC_STUB,jaddr,idle?idle:(int)out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
4726 void do_ccstub(int n)
4729 assem_debug("do_ccstub %x\n",start+stubs[n][4]*4);
4730 set_jump_target(stubs[n][1],(int)out);
4732 if(stubs[n][6]==NULLDS) {
4733 // Delay slot instruction is nullified ("likely" branch)
4734 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
4736 else if(stubs[n][6]!=TAKEN) {
4737 wb_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty);
4740 if(internal_branch(branch_regs[i].is32,ba[i]))
4741 wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4745 // Save PC as return address
4746 emit_movimm(stubs[n][5],EAX);
4747 emit_writeword(EAX,(int)&pcaddr);
4751 // Return address depends on which way the branch goes
4752 if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
4754 int s1l=get_reg(branch_regs[i].regmap,rs1[i]);
4755 int s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
4756 int s2l=get_reg(branch_regs[i].regmap,rs2[i]);
4757 int s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
4767 if((branch_regs[i].is32>>rs1[i])&(branch_regs[i].is32>>rs2[i])&1) {
4771 #ifdef DESTRUCTIVE_WRITEBACK
4773 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1)
4774 emit_loadreg(rs1[i],s1l);
4777 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1)
4778 emit_loadreg(rs2[i],s1l);
4781 if((branch_regs[i].dirty>>s2l)&(branch_regs[i].is32>>rs2[i])&1)
4782 emit_loadreg(rs2[i],s2l);
4785 int addr,alt,ntaddr;
4788 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4789 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4790 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4798 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4799 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4800 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4806 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
4810 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4811 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4812 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4818 assert(hr<HOST_REGS);
4820 if((opcode[i]&0x2f)==4) // BEQ
4822 #ifdef HAVE_CMOV_IMM
4824 if(s2l>=0) emit_cmp(s1l,s2l);
4825 else emit_test(s1l,s1l);
4826 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
4831 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4833 if(s2h>=0) emit_cmp(s1h,s2h);
4834 else emit_test(s1h,s1h);
4835 emit_cmovne_reg(alt,addr);
4837 if(s2l>=0) emit_cmp(s1l,s2l);
4838 else emit_test(s1l,s1l);
4839 emit_cmovne_reg(alt,addr);
4842 if((opcode[i]&0x2f)==5) // BNE
4844 #ifdef HAVE_CMOV_IMM
4846 if(s2l>=0) emit_cmp(s1l,s2l);
4847 else emit_test(s1l,s1l);
4848 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
4853 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
4855 if(s2h>=0) emit_cmp(s1h,s2h);
4856 else emit_test(s1h,s1h);
4857 emit_cmovne_reg(alt,addr);
4859 if(s2l>=0) emit_cmp(s1l,s2l);
4860 else emit_test(s1l,s1l);
4861 emit_cmovne_reg(alt,addr);
4864 if((opcode[i]&0x2f)==6) // BLEZ
4866 //emit_movimm(ba[i],alt);
4867 //emit_movimm(start+i*4+8,addr);
4868 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4870 if(s1h>=0) emit_mov(addr,ntaddr);
4871 emit_cmovl_reg(alt,addr);
4874 emit_cmovne_reg(ntaddr,addr);
4875 emit_cmovs_reg(alt,addr);
4878 if((opcode[i]&0x2f)==7) // BGTZ
4880 //emit_movimm(ba[i],addr);
4881 //emit_movimm(start+i*4+8,ntaddr);
4882 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
4884 if(s1h>=0) emit_mov(addr,alt);
4885 emit_cmovl_reg(ntaddr,addr);
4888 emit_cmovne_reg(alt,addr);
4889 emit_cmovs_reg(ntaddr,addr);
4892 if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ
4894 //emit_movimm(ba[i],alt);
4895 //emit_movimm(start+i*4+8,addr);
4896 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4897 if(s1h>=0) emit_test(s1h,s1h);
4898 else emit_test(s1l,s1l);
4899 emit_cmovs_reg(alt,addr);
4901 if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ
4903 //emit_movimm(ba[i],addr);
4904 //emit_movimm(start+i*4+8,alt);
4905 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4906 if(s1h>=0) emit_test(s1h,s1h);
4907 else emit_test(s1l,s1l);
4908 emit_cmovs_reg(alt,addr);
4910 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
4911 if(source[i]&0x10000) // BC1T
4913 //emit_movimm(ba[i],alt);
4914 //emit_movimm(start+i*4+8,addr);
4915 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4916 emit_testimm(s1l,0x800000);
4917 emit_cmovne_reg(alt,addr);
4921 //emit_movimm(ba[i],addr);
4922 //emit_movimm(start+i*4+8,alt);
4923 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4924 emit_testimm(s1l,0x800000);
4925 emit_cmovne_reg(alt,addr);
4928 emit_writeword(addr,(int)&pcaddr);
4933 int r=get_reg(branch_regs[i].regmap,rs1[i]);
4934 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
4935 r=get_reg(branch_regs[i].regmap,RTEMP);
4937 emit_writeword(r,(int)&pcaddr);
4939 else {printf("Unknown branch type in do_ccstub\n");exit(1);}
4941 // Update cycle count
4942 assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
4943 if(stubs[n][3]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
4944 emit_call((int)cc_interrupt);
4945 if(stubs[n][3]) emit_addimm(HOST_CCREG,-CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
4946 if(stubs[n][6]==TAKEN) {
4947 if(internal_branch(branch_regs[i].is32,ba[i]))
4948 load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
4949 else if(itype[i]==RJUMP) {
4950 if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
4951 emit_readword((int)&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
4953 emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i]));
4955 }else if(stubs[n][6]==NOTTAKEN) {
4956 if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
4957 else load_all_regs(branch_regs[i].regmap);
4958 }else if(stubs[n][6]==NULLDS) {
4959 // Delay slot instruction is nullified ("likely" branch)
4960 if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
4961 else load_all_regs(regs[i].regmap);
4963 load_all_regs(branch_regs[i].regmap);
4965 emit_jmp(stubs[n][2]); // return address
4967 /* This works but uses a lot of memory...
4968 emit_readword((int)&last_count,ECX);
4969 emit_add(HOST_CCREG,ECX,EAX);
4970 emit_writeword(EAX,(int)&Count);
4971 emit_call((int)gen_interupt);
4972 emit_readword((int)&Count,HOST_CCREG);
4973 emit_readword((int)&next_interupt,EAX);
4974 emit_readword((int)&pending_exception,EBX);
4975 emit_writeword(EAX,(int)&last_count);
4976 emit_sub(HOST_CCREG,EAX,HOST_CCREG);
4978 int jne_instr=(int)out;
4980 if(stubs[n][3]) emit_addimm(HOST_CCREG,-2*stubs[n][3],HOST_CCREG);
4981 load_all_regs(branch_regs[i].regmap);
4982 emit_jmp(stubs[n][2]); // return address
4983 set_jump_target(jne_instr,(int)out);
4984 emit_readword((int)&pcaddr,EAX);
4985 // Call get_addr_ht instead of doing the hash table here.
4986 // This code is executed infrequently and takes up a lot of space
4987 // so smaller is better.
4988 emit_storereg(CCREG,HOST_CCREG);
4990 emit_call((int)get_addr_ht);
4991 emit_loadreg(CCREG,HOST_CCREG);
4992 emit_addimm(ESP,4,ESP);
4996 add_to_linker(int addr,int target,int ext)
4998 link_addr[linkcount][0]=addr;
4999 link_addr[linkcount][1]=target;
5000 link_addr[linkcount][2]=ext;
5004 void ujump_assemble(int i,struct regstat *i_regs)
5006 signed char *i_regmap=i_regs->regmap;
5007 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5008 address_generation(i+1,i_regs,regs[i].regmap_entry);
5010 int temp=get_reg(branch_regs[i].regmap,PTEMP);
5011 if(rt1[i]==31&&temp>=0)
5013 int return_address=start+i*4+8;
5014 if(get_reg(branch_regs[i].regmap,31)>0)
5015 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5018 ds_assemble(i+1,i_regs);
5019 uint64_t bc_unneeded=branch_regs[i].u;
5020 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5021 bc_unneeded|=1|(1LL<<rt1[i]);
5022 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5023 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5024 bc_unneeded,bc_unneeded_upper);
5025 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5028 unsigned int return_address;
5029 assert(rt1[i+1]!=31);
5030 assert(rt2[i+1]!=31);
5031 rt=get_reg(branch_regs[i].regmap,31);
5032 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5034 return_address=start+i*4+8;
5037 if(internal_branch(branch_regs[i].is32,return_address)) {
5039 if(temp==EXCLUDE_REG||temp>=HOST_REGS||
5040 branch_regs[i].regmap[temp]>=0)
5042 temp=get_reg(branch_regs[i].regmap,-1);
5045 if(temp<0) temp=HOST_TEMPREG;
5047 if(temp>=0) do_miniht_insert(return_address,rt,temp);
5048 else emit_movimm(return_address,rt);
5056 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5059 emit_movimm(return_address,rt); // PC into link register
5061 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5067 cc=get_reg(branch_regs[i].regmap,CCREG);
5068 assert(cc==HOST_CCREG);
5069 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5071 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5073 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5074 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5075 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5076 if(internal_branch(branch_regs[i].is32,ba[i]))
5077 assem_debug("branch: internal\n");
5079 assem_debug("branch: external\n");
5080 if(internal_branch(branch_regs[i].is32,ba[i])&&is_ds[(ba[i]-start)>>2]) {
5081 ds_assemble_entry(i);
5084 add_to_linker((int)out,ba[i],internal_branch(branch_regs[i].is32,ba[i]));
5089 void rjump_assemble(int i,struct regstat *i_regs)
5091 signed char *i_regmap=i_regs->regmap;
5094 rs=get_reg(branch_regs[i].regmap,rs1[i]);
5096 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5097 // Delay slot abuse, make a copy of the branch address register
5098 temp=get_reg(branch_regs[i].regmap,RTEMP);
5100 assert(regs[i].regmap[temp]==RTEMP);
5104 address_generation(i+1,i_regs,regs[i].regmap_entry);
5108 if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5109 int return_address=start+i*4+8;
5110 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5116 int rh=get_reg(regs[i].regmap,RHASH);
5117 if(rh>=0) do_preload_rhash(rh);
5120 ds_assemble(i+1,i_regs);
5121 uint64_t bc_unneeded=branch_regs[i].u;
5122 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5123 bc_unneeded|=1|(1LL<<rt1[i]);
5124 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5125 bc_unneeded&=~(1LL<<rs1[i]);
5126 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5127 bc_unneeded,bc_unneeded_upper);
5128 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
5130 int rt,return_address;
5131 assert(rt1[i+1]!=rt1[i]);
5132 assert(rt2[i+1]!=rt1[i]);
5133 rt=get_reg(branch_regs[i].regmap,rt1[i]);
5134 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5136 return_address=start+i*4+8;
5140 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5143 emit_movimm(return_address,rt); // PC into link register
5145 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5148 cc=get_reg(branch_regs[i].regmap,CCREG);
5149 assert(cc==HOST_CCREG);
5151 int rh=get_reg(branch_regs[i].regmap,RHASH);
5152 int ht=get_reg(branch_regs[i].regmap,RHTBL);
5154 if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5155 do_preload_rhtbl(ht);
5159 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5160 #ifdef DESTRUCTIVE_WRITEBACK
5161 if((branch_regs[i].dirty>>rs)&(branch_regs[i].is32>>rs1[i])&1) {
5162 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
5163 emit_loadreg(rs1[i],rs);
5168 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5172 do_miniht_load(ht,rh);
5175 //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5176 //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5178 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5179 add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
5181 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5184 do_miniht_jump(rs,rh,ht);
5189 //if(rs!=EAX) emit_mov(rs,EAX);
5190 //emit_jmp((int)jump_vaddr_eax);
5191 emit_jmp(jump_vaddr_reg[rs]);
5196 emit_shrimm(rs,16,rs);
5197 emit_xor(temp,rs,rs);
5198 emit_movzwl_reg(rs,rs);
5199 emit_shlimm(rs,4,rs);
5200 emit_cmpmem_indexed((int)hash_table,rs,temp);
5201 emit_jne((int)out+14);
5202 emit_readword_indexed((int)hash_table+4,rs,rs);
5204 emit_cmpmem_indexed((int)hash_table+8,rs,temp);
5205 emit_addimm_no_flags(8,rs);
5206 emit_jeq((int)out-17);
5207 // No hit on hash table, call compiler
5210 #ifdef DEBUG_CYCLE_COUNT
5211 emit_readword((int)&last_count,ECX);
5212 emit_add(HOST_CCREG,ECX,HOST_CCREG);
5213 emit_readword((int)&next_interupt,ECX);
5214 emit_writeword(HOST_CCREG,(int)&Count);
5215 emit_sub(HOST_CCREG,ECX,HOST_CCREG);
5216 emit_writeword(ECX,(int)&last_count);
5219 emit_storereg(CCREG,HOST_CCREG);
5220 emit_call((int)get_addr);
5221 emit_loadreg(CCREG,HOST_CCREG);
5222 emit_addimm(ESP,4,ESP);
5224 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5225 if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5229 void cjump_assemble(int i,struct regstat *i_regs)
5231 signed char *i_regmap=i_regs->regmap;
5234 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5235 assem_debug("match=%d\n",match);
5236 int s1h,s1l,s2h,s2l;
5237 int prev_cop1_usable=cop1_usable;
5238 int unconditional=0,nop=0;
5242 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5243 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5244 if(likely[i]) ooo=0;
5245 if(!match) invert=1;
5246 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5247 if(i>(ba[i]-start)>>2) invert=1;
5251 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
5252 (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1])))
5254 // Write-after-read dependency prevents out of order execution
5255 // First test branch condition, then execute delay slot, then branch
5260 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5261 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5262 s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5263 s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5266 s1l=get_reg(i_regmap,rs1[i]);
5267 s1h=get_reg(i_regmap,rs1[i]|64);
5268 s2l=get_reg(i_regmap,rs2[i]);
5269 s2h=get_reg(i_regmap,rs2[i]|64);
5271 if(rs1[i]==0&&rs2[i]==0)
5273 if(opcode[i]&1) nop=1;
5274 else unconditional=1;
5275 //assert(opcode[i]!=5);
5276 //assert(opcode[i]!=7);
5277 //assert(opcode[i]!=0x15);
5278 //assert(opcode[i]!=0x17);
5284 only32=(regs[i].was32>>rs2[i])&1;
5289 only32=(regs[i].was32>>rs1[i])&1;
5292 only32=(regs[i].was32>>rs1[i])&(regs[i].was32>>rs2[i])&1;
5296 // Out of order execution (delay slot first)
5298 address_generation(i+1,i_regs,regs[i].regmap_entry);
5299 ds_assemble(i+1,i_regs);
5301 uint64_t bc_unneeded=branch_regs[i].u;
5302 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5303 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5304 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5306 bc_unneeded_upper|=1;
5307 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5308 bc_unneeded,bc_unneeded_upper);
5309 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
5310 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5311 cc=get_reg(branch_regs[i].regmap,CCREG);
5312 assert(cc==HOST_CCREG);
5314 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5315 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5316 //assem_debug("cycle count (adj)\n");
5318 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5319 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5320 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5321 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5323 assem_debug("branch: internal\n");
5325 assem_debug("branch: external\n");
5326 if(internal&&is_ds[(ba[i]-start)>>2]) {
5327 ds_assemble_entry(i);
5330 add_to_linker((int)out,ba[i],internal);
5333 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5334 if(((u_int)out)&7) emit_addnop(0);
5339 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5342 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5345 int taken=0,nottaken=0,nottaken1=0;
5346 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5347 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5351 if(opcode[i]==4) // BEQ
5353 if(s2h>=0) emit_cmp(s1h,s2h);
5354 else emit_test(s1h,s1h);
5358 if(opcode[i]==5) // BNE
5360 if(s2h>=0) emit_cmp(s1h,s2h);
5361 else emit_test(s1h,s1h);
5362 if(invert) taken=(int)out;
5363 else add_to_linker((int)out,ba[i],internal);
5366 if(opcode[i]==6) // BLEZ
5369 if(invert) taken=(int)out;
5370 else add_to_linker((int)out,ba[i],internal);
5375 if(opcode[i]==7) // BGTZ
5380 if(invert) taken=(int)out;
5381 else add_to_linker((int)out,ba[i],internal);
5386 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5388 if(opcode[i]==4) // BEQ
5390 if(s2l>=0) emit_cmp(s1l,s2l);
5391 else emit_test(s1l,s1l);
5396 add_to_linker((int)out,ba[i],internal);
5400 if(opcode[i]==5) // BNE
5402 if(s2l>=0) emit_cmp(s1l,s2l);
5403 else emit_test(s1l,s1l);
5408 add_to_linker((int)out,ba[i],internal);
5412 if(opcode[i]==6) // BLEZ
5419 add_to_linker((int)out,ba[i],internal);
5423 if(opcode[i]==7) // BGTZ
5430 add_to_linker((int)out,ba[i],internal);
5435 if(taken) set_jump_target(taken,(int)out);
5436 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5437 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5439 emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5440 add_to_linker((int)out,ba[i],internal);
5443 add_to_linker((int)out,ba[i],internal*2);
5449 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5450 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5451 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5453 assem_debug("branch: internal\n");
5455 assem_debug("branch: external\n");
5456 if(internal&&is_ds[(ba[i]-start)>>2]) {
5457 ds_assemble_entry(i);
5460 add_to_linker((int)out,ba[i],internal);
5464 set_jump_target(nottaken,(int)out);
5467 if(nottaken1) set_jump_target(nottaken1,(int)out);
5469 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5471 } // (!unconditional)
5475 // In-order execution (branch first)
5476 //if(likely[i]) printf("IOL\n");
5479 int taken=0,nottaken=0,nottaken1=0;
5480 if(!unconditional&&!nop) {
5484 if((opcode[i]&0x2f)==4) // BEQ
5486 if(s2h>=0) emit_cmp(s1h,s2h);
5487 else emit_test(s1h,s1h);
5491 if((opcode[i]&0x2f)==5) // BNE
5493 if(s2h>=0) emit_cmp(s1h,s2h);
5494 else emit_test(s1h,s1h);
5498 if((opcode[i]&0x2f)==6) // BLEZ
5506 if((opcode[i]&0x2f)==7) // BGTZ
5516 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5518 if((opcode[i]&0x2f)==4) // BEQ
5520 if(s2l>=0) emit_cmp(s1l,s2l);
5521 else emit_test(s1l,s1l);
5525 if((opcode[i]&0x2f)==5) // BNE
5527 if(s2l>=0) emit_cmp(s1l,s2l);
5528 else emit_test(s1l,s1l);
5532 if((opcode[i]&0x2f)==6) // BLEZ
5538 if((opcode[i]&0x2f)==7) // BGTZ
5544 } // if(!unconditional)
5546 uint64_t ds_unneeded=branch_regs[i].u;
5547 uint64_t ds_unneeded_upper=branch_regs[i].uu;
5548 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5549 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5550 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5552 ds_unneeded_upper|=1;
5555 if(taken) set_jump_target(taken,(int)out);
5556 assem_debug("1:\n");
5557 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5558 ds_unneeded,ds_unneeded_upper);
5560 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5561 address_generation(i+1,&branch_regs[i],0);
5562 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5563 ds_assemble(i+1,&branch_regs[i]);
5564 cc=get_reg(branch_regs[i].regmap,CCREG);
5566 emit_loadreg(CCREG,cc=HOST_CCREG);
5567 // CHECK: Is the following instruction (fall thru) allocated ok?
5569 assert(cc==HOST_CCREG);
5570 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5571 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5572 assem_debug("cycle count (adj)\n");
5573 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5574 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5576 assem_debug("branch: internal\n");
5578 assem_debug("branch: external\n");
5579 if(internal&&is_ds[(ba[i]-start)>>2]) {
5580 ds_assemble_entry(i);
5583 add_to_linker((int)out,ba[i],internal);
5588 cop1_usable=prev_cop1_usable;
5589 if(!unconditional) {
5590 if(nottaken1) set_jump_target(nottaken1,(int)out);
5591 set_jump_target(nottaken,(int)out);
5592 assem_debug("2:\n");
5594 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5595 ds_unneeded,ds_unneeded_upper);
5596 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5597 address_generation(i+1,&branch_regs[i],0);
5598 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5599 ds_assemble(i+1,&branch_regs[i]);
5601 cc=get_reg(branch_regs[i].regmap,CCREG);
5602 if(cc==-1&&!likely[i]) {
5603 // Cycle count isn't in a register, temporarily load it then write it out
5604 emit_loadreg(CCREG,HOST_CCREG);
5605 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5608 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5609 emit_storereg(CCREG,HOST_CCREG);
5612 cc=get_reg(i_regmap,CCREG);
5613 assert(cc==HOST_CCREG);
5614 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5617 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5623 void sjump_assemble(int i,struct regstat *i_regs)
5625 signed char *i_regmap=i_regs->regmap;
5628 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5629 assem_debug("smatch=%d\n",match);
5631 int prev_cop1_usable=cop1_usable;
5632 int unconditional=0,nevertaken=0;
5636 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5637 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5638 if(likely[i]) ooo=0;
5639 if(!match) invert=1;
5640 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5641 if(i>(ba[i]-start)>>2) invert=1;
5644 //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
5645 //assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
5648 if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))
5650 // Write-after-read dependency prevents out of order execution
5651 // First test branch condition, then execute delay slot, then branch
5656 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5657 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5660 s1l=get_reg(i_regmap,rs1[i]);
5661 s1h=get_reg(i_regmap,rs1[i]|64);
5665 if(opcode2[i]&1) unconditional=1;
5667 // These are never taken (r0 is never less than zero)
5668 //assert(opcode2[i]!=0);
5669 //assert(opcode2[i]!=2);
5670 //assert(opcode2[i]!=0x10);
5671 //assert(opcode2[i]!=0x12);
5674 only32=(regs[i].was32>>rs1[i])&1;
5678 // Out of order execution (delay slot first)
5680 address_generation(i+1,i_regs,regs[i].regmap_entry);
5681 ds_assemble(i+1,i_regs);
5683 uint64_t bc_unneeded=branch_regs[i].u;
5684 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5685 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5686 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5688 bc_unneeded_upper|=1;
5689 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5690 bc_unneeded,bc_unneeded_upper);
5691 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5692 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5694 int rt,return_address;
5695 assert(rt1[i+1]!=31);
5696 assert(rt2[i+1]!=31);
5697 rt=get_reg(branch_regs[i].regmap,31);
5698 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5700 // Save the PC even if the branch is not taken
5701 return_address=start+i*4+8;
5702 emit_movimm(return_address,rt); // PC into link register
5704 if(!nevertaken) emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5708 cc=get_reg(branch_regs[i].regmap,CCREG);
5709 assert(cc==HOST_CCREG);
5711 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5712 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5713 assem_debug("cycle count (adj)\n");
5715 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5716 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5717 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5718 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5720 assem_debug("branch: internal\n");
5722 assem_debug("branch: external\n");
5723 if(internal&&is_ds[(ba[i]-start)>>2]) {
5724 ds_assemble_entry(i);
5727 add_to_linker((int)out,ba[i],internal);
5730 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5731 if(((u_int)out)&7) emit_addnop(0);
5735 else if(nevertaken) {
5736 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5739 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5743 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5744 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5748 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
5755 add_to_linker((int)out,ba[i],internal);
5759 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
5766 add_to_linker((int)out,ba[i],internal);
5774 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
5781 add_to_linker((int)out,ba[i],internal);
5785 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
5792 add_to_linker((int)out,ba[i],internal);
5799 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5800 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5802 emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5803 add_to_linker((int)out,ba[i],internal);
5806 add_to_linker((int)out,ba[i],internal*2);
5812 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5813 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5814 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5816 assem_debug("branch: internal\n");
5818 assem_debug("branch: external\n");
5819 if(internal&&is_ds[(ba[i]-start)>>2]) {
5820 ds_assemble_entry(i);
5823 add_to_linker((int)out,ba[i],internal);
5827 set_jump_target(nottaken,(int)out);
5831 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5833 } // (!unconditional)
5837 // In-order execution (branch first)
5841 int rt,return_address;
5842 assert(rt1[i+1]!=31);
5843 assert(rt2[i+1]!=31);
5844 rt=get_reg(branch_regs[i].regmap,31);
5846 // Save the PC even if the branch is not taken
5847 return_address=start+i*4+8;
5848 emit_movimm(return_address,rt); // PC into link register
5850 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5854 if(!unconditional) {
5855 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5859 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
5865 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
5875 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
5881 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
5888 } // if(!unconditional)
5890 uint64_t ds_unneeded=branch_regs[i].u;
5891 uint64_t ds_unneeded_upper=branch_regs[i].uu;
5892 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5893 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5894 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5896 ds_unneeded_upper|=1;
5899 //assem_debug("1:\n");
5900 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5901 ds_unneeded,ds_unneeded_upper);
5903 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5904 address_generation(i+1,&branch_regs[i],0);
5905 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5906 ds_assemble(i+1,&branch_regs[i]);
5907 cc=get_reg(branch_regs[i].regmap,CCREG);
5909 emit_loadreg(CCREG,cc=HOST_CCREG);
5910 // CHECK: Is the following instruction (fall thru) allocated ok?
5912 assert(cc==HOST_CCREG);
5913 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5914 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5915 assem_debug("cycle count (adj)\n");
5916 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5917 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5919 assem_debug("branch: internal\n");
5921 assem_debug("branch: external\n");
5922 if(internal&&is_ds[(ba[i]-start)>>2]) {
5923 ds_assemble_entry(i);
5926 add_to_linker((int)out,ba[i],internal);
5931 cop1_usable=prev_cop1_usable;
5932 if(!unconditional) {
5933 set_jump_target(nottaken,(int)out);
5934 assem_debug("1:\n");
5936 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5937 ds_unneeded,ds_unneeded_upper);
5938 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5939 address_generation(i+1,&branch_regs[i],0);
5940 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5941 ds_assemble(i+1,&branch_regs[i]);
5943 cc=get_reg(branch_regs[i].regmap,CCREG);
5944 if(cc==-1&&!likely[i]) {
5945 // Cycle count isn't in a register, temporarily load it then write it out
5946 emit_loadreg(CCREG,HOST_CCREG);
5947 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5950 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5951 emit_storereg(CCREG,HOST_CCREG);
5954 cc=get_reg(i_regmap,CCREG);
5955 assert(cc==HOST_CCREG);
5956 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5959 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5965 void fjump_assemble(int i,struct regstat *i_regs)
5967 signed char *i_regmap=i_regs->regmap;
5970 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5971 assem_debug("fmatch=%d\n",match);
5976 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5977 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5978 if(likely[i]) ooo=0;
5979 if(!match) invert=1;
5980 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5981 if(i>(ba[i]-start)>>2) invert=1;
5985 if(itype[i+1]==FCOMP)
5987 // Write-after-read dependency prevents out of order execution
5988 // First test branch condition, then execute delay slot, then branch
5993 fs=get_reg(branch_regs[i].regmap,FSREG);
5994 address_generation(i+1,i_regs,regs[i].regmap_entry); // Is this okay?
5997 fs=get_reg(i_regmap,FSREG);
6000 // Check cop1 unusable
6002 cs=get_reg(i_regmap,CSREG);
6004 emit_testimm(cs,0x20000000);
6007 add_stub(FP_STUB,eaddr,(int)out,i,cs,(int)i_regs,0,0);
6012 // Out of order execution (delay slot first)
6014 ds_assemble(i+1,i_regs);
6016 uint64_t bc_unneeded=branch_regs[i].u;
6017 uint64_t bc_unneeded_upper=branch_regs[i].uu;
6018 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6019 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
6021 bc_unneeded_upper|=1;
6022 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6023 bc_unneeded,bc_unneeded_upper);
6024 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
6025 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6026 cc=get_reg(branch_regs[i].regmap,CCREG);
6027 assert(cc==HOST_CCREG);
6028 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
6029 assem_debug("cycle count (adj)\n");
6032 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6035 emit_testimm(fs,0x800000);
6036 if(source[i]&0x10000) // BC1T
6042 add_to_linker((int)out,ba[i],internal);
6051 add_to_linker((int)out,ba[i],internal);
6059 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
6060 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6061 else if(match) emit_addnop(13);
6063 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6064 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6066 assem_debug("branch: internal\n");
6068 assem_debug("branch: external\n");
6069 if(internal&&is_ds[(ba[i]-start)>>2]) {
6070 ds_assemble_entry(i);
6073 add_to_linker((int)out,ba[i],internal);
6076 set_jump_target(nottaken,(int)out);
6080 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
6082 } // (!unconditional)
6086 // In-order execution (branch first)
6090 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6093 emit_testimm(fs,0x800000);
6094 if(source[i]&0x10000) // BC1T
6105 } // if(!unconditional)
6107 uint64_t ds_unneeded=branch_regs[i].u;
6108 uint64_t ds_unneeded_upper=branch_regs[i].uu;
6109 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6110 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6111 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6113 ds_unneeded_upper|=1;
6115 //assem_debug("1:\n");
6116 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6117 ds_unneeded,ds_unneeded_upper);
6119 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6120 address_generation(i+1,&branch_regs[i],0);
6121 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6122 ds_assemble(i+1,&branch_regs[i]);
6123 cc=get_reg(branch_regs[i].regmap,CCREG);
6125 emit_loadreg(CCREG,cc=HOST_CCREG);
6126 // CHECK: Is the following instruction (fall thru) allocated ok?
6128 assert(cc==HOST_CCREG);
6129 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6130 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6131 assem_debug("cycle count (adj)\n");
6132 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6133 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6135 assem_debug("branch: internal\n");
6137 assem_debug("branch: external\n");
6138 if(internal&&is_ds[(ba[i]-start)>>2]) {
6139 ds_assemble_entry(i);
6142 add_to_linker((int)out,ba[i],internal);
6147 if(1) { // <- FIXME (don't need this)
6148 set_jump_target(nottaken,(int)out);
6149 assem_debug("1:\n");
6151 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6152 ds_unneeded,ds_unneeded_upper);
6153 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6154 address_generation(i+1,&branch_regs[i],0);
6155 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6156 ds_assemble(i+1,&branch_regs[i]);
6158 cc=get_reg(branch_regs[i].regmap,CCREG);
6159 if(cc==-1&&!likely[i]) {
6160 // Cycle count isn't in a register, temporarily load it then write it out
6161 emit_loadreg(CCREG,HOST_CCREG);
6162 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6165 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6166 emit_storereg(CCREG,HOST_CCREG);
6169 cc=get_reg(i_regmap,CCREG);
6170 assert(cc==HOST_CCREG);
6171 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
6174 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6180 static void pagespan_assemble(int i,struct regstat *i_regs)
6182 int s1l=get_reg(i_regs->regmap,rs1[i]);
6183 int s1h=get_reg(i_regs->regmap,rs1[i]|64);
6184 int s2l=get_reg(i_regs->regmap,rs2[i]);
6185 int s2h=get_reg(i_regs->regmap,rs2[i]|64);
6186 void *nt_branch=NULL;
6189 int unconditional=0;
6199 if((i_regs->is32>>rs1[i])&(i_regs->is32>>rs2[i])&1) {
6203 int addr,alt,ntaddr;
6204 if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
6208 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
6209 (i_regs->regmap[hr]&63)!=rs1[i] &&
6210 (i_regs->regmap[hr]&63)!=rs2[i] )
6219 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6220 (i_regs->regmap[hr]&63)!=rs1[i] &&
6221 (i_regs->regmap[hr]&63)!=rs2[i] )
6227 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
6231 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6232 (i_regs->regmap[hr]&63)!=rs1[i] &&
6233 (i_regs->regmap[hr]&63)!=rs2[i] )
6240 assert(hr<HOST_REGS);
6241 if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
6242 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
6244 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6245 if(opcode[i]==2) // J
6249 if(opcode[i]==3) // JAL
6252 int rt=get_reg(i_regs->regmap,31);
6253 emit_movimm(start+i*4+8,rt);
6256 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
6259 if(opcode2[i]==9) // JALR
6261 int rt=get_reg(i_regs->regmap,rt1[i]);
6262 emit_movimm(start+i*4+8,rt);
6265 if((opcode[i]&0x3f)==4) // BEQ
6272 #ifdef HAVE_CMOV_IMM
6274 if(s2l>=0) emit_cmp(s1l,s2l);
6275 else emit_test(s1l,s1l);
6276 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
6282 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6284 if(s2h>=0) emit_cmp(s1h,s2h);
6285 else emit_test(s1h,s1h);
6286 emit_cmovne_reg(alt,addr);
6288 if(s2l>=0) emit_cmp(s1l,s2l);
6289 else emit_test(s1l,s1l);
6290 emit_cmovne_reg(alt,addr);
6293 if((opcode[i]&0x3f)==5) // BNE
6295 #ifdef HAVE_CMOV_IMM
6297 if(s2l>=0) emit_cmp(s1l,s2l);
6298 else emit_test(s1l,s1l);
6299 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
6305 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
6307 if(s2h>=0) emit_cmp(s1h,s2h);
6308 else emit_test(s1h,s1h);
6309 emit_cmovne_reg(alt,addr);
6311 if(s2l>=0) emit_cmp(s1l,s2l);
6312 else emit_test(s1l,s1l);
6313 emit_cmovne_reg(alt,addr);
6316 if((opcode[i]&0x3f)==0x14) // BEQL
6319 if(s2h>=0) emit_cmp(s1h,s2h);
6320 else emit_test(s1h,s1h);
6324 if(s2l>=0) emit_cmp(s1l,s2l);
6325 else emit_test(s1l,s1l);
6326 if(nottaken) set_jump_target(nottaken,(int)out);
6330 if((opcode[i]&0x3f)==0x15) // BNEL
6333 if(s2h>=0) emit_cmp(s1h,s2h);
6334 else emit_test(s1h,s1h);
6338 if(s2l>=0) emit_cmp(s1l,s2l);
6339 else emit_test(s1l,s1l);
6342 if(taken) set_jump_target(taken,(int)out);
6344 if((opcode[i]&0x3f)==6) // BLEZ
6346 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6348 if(s1h>=0) emit_mov(addr,ntaddr);
6349 emit_cmovl_reg(alt,addr);
6352 emit_cmovne_reg(ntaddr,addr);
6353 emit_cmovs_reg(alt,addr);
6356 if((opcode[i]&0x3f)==7) // BGTZ
6358 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
6360 if(s1h>=0) emit_mov(addr,alt);
6361 emit_cmovl_reg(ntaddr,addr);
6364 emit_cmovne_reg(alt,addr);
6365 emit_cmovs_reg(ntaddr,addr);
6368 if((opcode[i]&0x3f)==0x16) // BLEZL
6370 assert((opcode[i]&0x3f)!=0x16);
6372 if((opcode[i]&0x3f)==0x17) // BGTZL
6374 assert((opcode[i]&0x3f)!=0x17);
6376 assert(opcode[i]!=1); // BLTZ/BGEZ
6378 //FIXME: Check CSREG
6379 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
6380 if((source[i]&0x30000)==0) // BC1F
6382 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6383 emit_testimm(s1l,0x800000);
6384 emit_cmovne_reg(alt,addr);
6386 if((source[i]&0x30000)==0x10000) // BC1T
6388 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6389 emit_testimm(s1l,0x800000);
6390 emit_cmovne_reg(alt,addr);
6392 if((source[i]&0x30000)==0x20000) // BC1FL
6394 emit_testimm(s1l,0x800000);
6398 if((source[i]&0x30000)==0x30000) // BC1TL
6400 emit_testimm(s1l,0x800000);
6406 assert(i_regs->regmap[HOST_CCREG]==CCREG);
6407 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6408 if(likely[i]||unconditional)
6410 emit_movimm(ba[i],HOST_BTREG);
6412 else if(addr!=HOST_BTREG)
6414 emit_mov(addr,HOST_BTREG);
6416 void *branch_addr=out;
6418 int target_addr=start+i*4+5;
6420 void *compiled_target_addr=check_addr(target_addr);
6421 emit_extjump_ds((int)branch_addr,target_addr);
6422 if(compiled_target_addr) {
6423 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6424 add_link(target_addr,stub);
6426 else set_jump_target((int)branch_addr,(int)stub);
6429 set_jump_target((int)nottaken,(int)out);
6430 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6431 void *branch_addr=out;
6433 int target_addr=start+i*4+8;
6435 void *compiled_target_addr=check_addr(target_addr);
6436 emit_extjump_ds((int)branch_addr,target_addr);
6437 if(compiled_target_addr) {
6438 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6439 add_link(target_addr,stub);
6441 else set_jump_target((int)branch_addr,(int)stub);
6445 // Assemble the delay slot for the above
6446 static void pagespan_ds()
6448 assem_debug("initial delay slot:\n");
6449 u_int vaddr=start+1;
6450 u_int page=get_page(vaddr);
6451 u_int vpage=get_vpage(vaddr);
6452 ll_add(jump_dirty+vpage,vaddr,(void *)out);
6454 ll_add(jump_in+page,vaddr,(void *)out);
6455 assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6456 if(regs[0].regmap[HOST_CCREG]!=CCREG)
6457 wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty,regs[0].was32);
6458 if(regs[0].regmap[HOST_BTREG]!=BTREG)
6459 emit_writeword(HOST_BTREG,(int)&branch_target);
6460 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,rs1[0],rs2[0]);
6461 address_generation(0,®s[0],regs[0].regmap_entry);
6462 if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39||(opcode[0]&0x3b)==0x3a)
6463 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,INVCP,INVCP);
6468 alu_assemble(0,®s[0]);break;
6470 imm16_assemble(0,®s[0]);break;
6472 shift_assemble(0,®s[0]);break;
6474 shiftimm_assemble(0,®s[0]);break;
6476 load_assemble(0,®s[0]);break;
6478 loadlr_assemble(0,®s[0]);break;
6480 store_assemble(0,®s[0]);break;
6482 storelr_assemble(0,®s[0]);break;
6484 cop0_assemble(0,®s[0]);break;
6486 cop1_assemble(0,®s[0]);break;
6488 c1ls_assemble(0,®s[0]);break;
6490 cop2_assemble(0,®s[0]);break;
6492 c2ls_assemble(0,®s[0]);break;
6494 c2op_assemble(0,®s[0]);break;
6496 fconv_assemble(0,®s[0]);break;
6498 float_assemble(0,®s[0]);break;
6500 fcomp_assemble(0,®s[0]);break;
6502 multdiv_assemble(0,®s[0]);break;
6504 mov_assemble(0,®s[0]);break;
6514 printf("Jump in the delay slot. This is probably a bug.\n");
6516 int btaddr=get_reg(regs[0].regmap,BTREG);
6518 btaddr=get_reg(regs[0].regmap,-1);
6519 emit_readword((int)&branch_target,btaddr);
6521 assert(btaddr!=HOST_CCREG);
6522 if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6524 emit_movimm(start+4,HOST_TEMPREG);
6525 emit_cmp(btaddr,HOST_TEMPREG);
6527 emit_cmpimm(btaddr,start+4);
6529 int branch=(int)out;
6531 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,-1);
6532 emit_jmp(jump_vaddr_reg[btaddr]);
6533 set_jump_target(branch,(int)out);
6534 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6535 load_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6538 // Basic liveness analysis for MIPS registers
6539 void unneeded_registers(int istart,int iend,int r)
6543 uint64_t temp_u,temp_uu;
6548 u=unneeded_reg[iend+1];
6549 uu=unneeded_reg_upper[iend+1];
6552 for (i=iend;i>=istart;i--)
6554 //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
6555 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6557 // If subroutine call, flag return address as a possible branch target
6558 if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
6560 if(ba[i]<start || ba[i]>=(start+slen*4))
6562 // Branch out of this block, flush all regs
6566 if(itype[i]==UJUMP&&rt1[i]==31)
6568 uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
6570 if(itype[i]==RJUMP&&rs1[i]==31)
6572 uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9
6574 if(start>0x80000400&&start<0x80000000+RAM_SIZE) {
6575 if(itype[i]==UJUMP&&rt1[i]==31)
6577 //uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi
6578 uu=u=0x300FF0F; // Discard at, v0-v1, t0-t9
6580 if(itype[i]==RJUMP&&rs1[i]==31)
6582 //uu=u=0x30300FFF3LL; // Discard at, a0-a3, t0-t9, lo, hi
6583 uu=u=0x300FFF3; // Discard at, a0-a3, t0-t9
6586 branch_unneeded_reg[i]=u;
6587 branch_unneeded_reg_upper[i]=uu;
6588 // Merge in delay slot
6589 tdep=(~uu>>rt1[i+1])&1;
6590 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6591 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6592 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6593 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6594 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6596 // If branch is "likely" (and conditional)
6597 // then we skip the delay slot on the fall-thru path
6600 u&=unneeded_reg[i+2];
6601 uu&=unneeded_reg_upper[i+2];
6612 // Internal branch, flag target
6613 bt[(ba[i]-start)>>2]=1;
6614 if(ba[i]<=start+i*4) {
6616 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6618 // Unconditional branch
6621 // Conditional branch (not taken case)
6622 temp_u=unneeded_reg[i+2];
6623 temp_uu=unneeded_reg_upper[i+2];
6625 // Merge in delay slot
6626 tdep=(~temp_uu>>rt1[i+1])&1;
6627 temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6628 temp_uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6629 temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6630 temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6631 temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6632 temp_u|=1;temp_uu|=1;
6633 // If branch is "likely" (and conditional)
6634 // then we skip the delay slot on the fall-thru path
6637 temp_u&=unneeded_reg[i+2];
6638 temp_uu&=unneeded_reg_upper[i+2];
6646 tdep=(~temp_uu>>rt1[i])&1;
6647 temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6648 temp_uu|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6649 temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6650 temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
6651 temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i]));
6652 temp_u|=1;temp_uu|=1;
6653 unneeded_reg[i]=temp_u;
6654 unneeded_reg_upper[i]=temp_uu;
6655 // Only go three levels deep. This recursion can take an
6656 // excessive amount of time if there are a lot of nested loops.
6658 unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6660 unneeded_reg[(ba[i]-start)>>2]=1;
6661 unneeded_reg_upper[(ba[i]-start)>>2]=1;
6664 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6666 // Unconditional branch
6667 u=unneeded_reg[(ba[i]-start)>>2];
6668 uu=unneeded_reg_upper[(ba[i]-start)>>2];
6669 branch_unneeded_reg[i]=u;
6670 branch_unneeded_reg_upper[i]=uu;
6673 //branch_unneeded_reg[i]=u;
6674 //branch_unneeded_reg_upper[i]=uu;
6675 // Merge in delay slot
6676 tdep=(~uu>>rt1[i+1])&1;
6677 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6678 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6679 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6680 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6681 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6684 // Conditional branch
6685 b=unneeded_reg[(ba[i]-start)>>2];
6686 bu=unneeded_reg_upper[(ba[i]-start)>>2];
6687 branch_unneeded_reg[i]=b;
6688 branch_unneeded_reg_upper[i]=bu;
6691 //branch_unneeded_reg[i]=b;
6692 //branch_unneeded_reg_upper[i]=bu;
6693 // Branch delay slot
6694 tdep=(~uu>>rt1[i+1])&1;
6695 b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6696 bu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6697 b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6698 bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6699 bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6701 // If branch is "likely" then we skip the
6702 // delay slot on the fall-thru path
6707 u&=unneeded_reg[i+2];
6708 uu&=unneeded_reg_upper[i+2];
6719 branch_unneeded_reg[i]&=unneeded_reg[i+2];
6720 branch_unneeded_reg_upper[i]&=unneeded_reg_upper[i+2];
6721 //branch_unneeded_reg[i]=1;
6722 //branch_unneeded_reg_upper[i]=1;
6724 branch_unneeded_reg[i]=1;
6725 branch_unneeded_reg_upper[i]=1;
6731 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
6733 // SYSCALL instruction (software interrupt)
6737 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
6739 // ERET instruction (return from interrupt)
6744 tdep=(~uu>>rt1[i])&1;
6745 // Written registers are unneeded
6750 // Accessed registers are needed
6755 // Source-target dependencies
6756 uu&=~(tdep<<dep1[i]);
6757 uu&=~(tdep<<dep2[i]);
6758 // R0 is always unneeded
6762 unneeded_reg_upper[i]=uu;
6764 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
6767 for(r=1;r<=CCREG;r++) {
6768 if((unneeded_reg[i]>>r)&1) {
6769 if(r==HIREG) printf(" HI");
6770 else if(r==LOREG) printf(" LO");
6771 else printf(" r%d",r);
6775 for(r=1;r<=CCREG;r++) {
6776 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
6777 if(r==HIREG) printf(" HI");
6778 else if(r==LOREG) printf(" LO");
6779 else printf(" r%d",r);
6785 for (i=iend;i>=istart;i--)
6787 unneeded_reg_upper[i]=branch_unneeded_reg_upper[i]=-1LL;
6792 // Identify registers which are likely to contain 32-bit values
6793 // This is used to predict whether any branches will jump to a
6794 // location with 64-bit values in registers.
6795 static void provisional_32bit()
6799 uint64_t lastbranch=1;
6804 if(itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) {
6805 if(i>1) is32=lastbranch;
6811 if(itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP) {
6813 if(i>2) is32=lastbranch;
6817 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
6819 if(rs1[i-2]==0||rs2[i-2]==0)
6822 is32|=1LL<<rs1[i-2];
6825 is32|=1LL<<rs2[i-2];
6830 // If something jumps here with 64-bit values
6831 // then promote those registers to 64 bits
6834 uint64_t temp_is32=is32;
6837 if(ba[j]==start+i*4)
6838 //temp_is32&=branch_regs[j].is32;
6843 if(ba[j]==start+i*4)
6854 if(type==UJUMP||type==RJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
6855 // Branches don't write registers, consider the delay slot instead.
6866 if(opcode[i]==0x27||opcode[i]==0x37|| // LWU/LD
6867 opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
6876 if(op==0x1a||op==0x1b) is32&=~(1LL<<rt); // LDR/LDL
6877 if(op==0x22) is32|=1LL<<rt; // LWL
6880 if (op==0x08||op==0x09|| // ADDI/ADDIU
6881 op==0x0a||op==0x0b|| // SLTI/SLTIU
6887 if(op==0x18||op==0x19) { // DADDI/DADDIU
6890 // is32|=((is32>>s1)&1LL)<<rt;
6892 if(op==0x0d||op==0x0e) { // ORI/XORI
6893 uint64_t sr=((is32>>s1)&1LL);
6909 if(op2>=0x20&&op2<=0x23) { // ADD/ADDU/SUB/SUBU
6912 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
6915 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
6916 uint64_t sr=((is32>>s1)&(is32>>s2)&1LL);
6920 else if(op2>=0x2c&&op2<=0x2d) { // DADD/DADDU
6925 uint64_t sr=((is32>>s1)&1LL);
6930 uint64_t sr=((is32>>s2)&1LL);
6938 else if(op2>=0x2e&&op2<=0x2f) { // DSUB/DSUBU
6943 uint64_t sr=((is32>>s1)&1LL);
6953 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
6954 is32&=~((1LL<<HIREG)|(1LL<<LOREG));
6957 is32|=(1LL<<HIREG)|(1LL<<LOREG);
6962 uint64_t sr=((is32>>s1)&1LL);
6968 if(op2>=0x14&&op2<=0x17) is32&=~(1LL<<rt); // DSLLV/DSRLV/DSRAV
6969 else is32|=1LL<<rt; // SLLV/SRLV/SRAV
6973 // DSLL/DSRL/DSRA/DSLL32/DSRL32 but not DSRA32 have 64-bit result
6974 if(op2>=0x38&&op2<0x3f) is32&=~(1LL<<rt);
6977 if(op2==0) is32|=1LL<<rt; // MFC0
6981 if(op2==0) is32|=1LL<<rt; // MFC1
6982 if(op2==1) is32&=~(1LL<<rt); // DMFC1
6983 if(op2==2) is32|=1LL<<rt; // CFC1
7005 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
7007 if(rt1[i-1]==31) // JAL/JALR
7009 // Subroutine call will return here, don't alloc any registers
7014 // Internal branch will jump here, match registers to caller
7022 // Identify registers which may be assumed to contain 32-bit values
7023 // and where optimizations will rely on this.
7024 // This is used to determine whether backward branches can safely
7025 // jump to a location with 64-bit values in registers.
7026 static void provisional_r32()
7031 for (i=slen-1;i>=0;i--)
7034 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7036 if(ba[i]<start || ba[i]>=(start+slen*4))
7038 // Branch out of this block, don't need anything
7044 // Need whatever matches the target
7045 // (and doesn't get overwritten by the delay slot instruction)
7047 int t=(ba[i]-start)>>2;
7048 if(ba[i]>start+i*4) {
7050 //if(!(requires_32bit[t]&~regs[i].was32))
7051 // r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7052 if(!(pr32[t]&~regs[i].was32))
7053 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7056 if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
7057 r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7060 // Conditional branch may need registers for following instructions
7061 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
7064 //r32|=requires_32bit[i+2];
7067 // Mark this address as a branch target since it may be called
7068 // upon return from interrupt
7072 // Merge in delay slot
7074 // These are overwritten unless the branch is "likely"
7075 // and the delay slot is nullified if not taken
7076 r32&=~(1LL<<rt1[i+1]);
7077 r32&=~(1LL<<rt2[i+1]);
7079 // Assume these are needed (delay slot)
7082 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
7086 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
7088 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
7090 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
7092 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
7094 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
7097 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7099 // SYSCALL instruction (software interrupt)
7102 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7104 // ERET instruction (return from interrupt)
7108 r32&=~(1LL<<rt1[i]);
7109 r32&=~(1LL<<rt2[i]);
7112 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
7116 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
7118 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
7120 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
7122 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
7124 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
7126 //requires_32bit[i]=r32;
7129 // Dirty registers which are 32-bit, require 32-bit input
7130 // as they will be written as 32-bit values
7131 for(hr=0;hr<HOST_REGS;hr++)
7133 if(regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64) {
7134 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
7135 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
7136 pr32[i]|=1LL<<regs[i].regmap_entry[hr];
7137 //requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
7144 // Write back dirty registers as soon as we will no longer modify them,
7145 // so that we don't end up with lots of writes at the branches.
7146 void clean_registers(int istart,int iend,int wr)
7150 u_int will_dirty_i,will_dirty_next,temp_will_dirty;
7151 u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
7153 will_dirty_i=will_dirty_next=0;
7154 wont_dirty_i=wont_dirty_next=0;
7156 will_dirty_i=will_dirty_next=will_dirty[iend+1];
7157 wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
7159 for (i=iend;i>=istart;i--)
7161 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7163 if(ba[i]<start || ba[i]>=(start+slen*4))
7165 // Branch out of this block, flush all regs
7166 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7168 // Unconditional branch
7171 // Merge in delay slot (will dirty)
7172 for(r=0;r<HOST_REGS;r++) {
7173 if(r!=EXCLUDE_REG) {
7174 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7175 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7176 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7177 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7178 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7179 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7180 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7181 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7182 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7183 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7184 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7185 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7186 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7187 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7193 // Conditional branch
7195 wont_dirty_i=wont_dirty_next;
7196 // Merge in delay slot (will dirty)
7197 for(r=0;r<HOST_REGS;r++) {
7198 if(r!=EXCLUDE_REG) {
7200 // Might not dirty if likely branch is not taken
7201 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7202 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7203 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7204 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7205 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7206 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
7207 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7208 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7209 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7210 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7211 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7212 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7213 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7214 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7219 // Merge in delay slot (wont dirty)
7220 for(r=0;r<HOST_REGS;r++) {
7221 if(r!=EXCLUDE_REG) {
7222 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7223 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7224 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7225 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7226 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7227 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7228 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7229 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7230 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7231 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7235 #ifndef DESTRUCTIVE_WRITEBACK
7236 branch_regs[i].dirty&=wont_dirty_i;
7238 branch_regs[i].dirty|=will_dirty_i;
7244 if(ba[i]<=start+i*4) {
7246 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7248 // Unconditional branch
7251 // Merge in delay slot (will dirty)
7252 for(r=0;r<HOST_REGS;r++) {
7253 if(r!=EXCLUDE_REG) {
7254 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7255 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7256 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7257 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7258 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7259 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7260 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7261 if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7262 if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7263 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7264 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7265 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7266 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7267 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7271 // Conditional branch (not taken case)
7272 temp_will_dirty=will_dirty_next;
7273 temp_wont_dirty=wont_dirty_next;
7274 // Merge in delay slot (will dirty)
7275 for(r=0;r<HOST_REGS;r++) {
7276 if(r!=EXCLUDE_REG) {
7278 // Will not dirty if likely branch is not taken
7279 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7280 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7281 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7282 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7283 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7284 if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
7285 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7286 //if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7287 //if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7288 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7289 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7290 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7291 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7292 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7297 // Merge in delay slot (wont dirty)
7298 for(r=0;r<HOST_REGS;r++) {
7299 if(r!=EXCLUDE_REG) {
7300 if((regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7301 if((regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7302 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7303 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7304 if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7305 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7306 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7307 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7308 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7309 if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7312 // Deal with changed mappings
7314 for(r=0;r<HOST_REGS;r++) {
7315 if(r!=EXCLUDE_REG) {
7316 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
7317 temp_will_dirty&=~(1<<r);
7318 temp_wont_dirty&=~(1<<r);
7319 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7320 temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7321 temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7323 temp_will_dirty|=1<<r;
7324 temp_wont_dirty|=1<<r;
7331 will_dirty[i]=temp_will_dirty;
7332 wont_dirty[i]=temp_wont_dirty;
7333 clean_registers((ba[i]-start)>>2,i-1,0);
7335 // Limit recursion. It can take an excessive amount
7336 // of time if there are a lot of nested loops.
7337 will_dirty[(ba[i]-start)>>2]=0;
7338 wont_dirty[(ba[i]-start)>>2]=-1;
7343 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7345 // Unconditional branch
7348 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7349 for(r=0;r<HOST_REGS;r++) {
7350 if(r!=EXCLUDE_REG) {
7351 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7352 will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
7353 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7358 // Merge in delay slot
7359 for(r=0;r<HOST_REGS;r++) {
7360 if(r!=EXCLUDE_REG) {
7361 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7362 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7363 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7364 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7365 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7366 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7367 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7368 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7369 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7370 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7371 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7372 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7373 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7374 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7378 // Conditional branch
7379 will_dirty_i=will_dirty_next;
7380 wont_dirty_i=wont_dirty_next;
7381 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7382 for(r=0;r<HOST_REGS;r++) {
7383 if(r!=EXCLUDE_REG) {
7384 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7385 will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7386 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7390 will_dirty_i&=~(1<<r);
7392 // Treat delay slot as part of branch too
7393 /*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7394 will_dirty[i+1]&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7395 wont_dirty[i+1]|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7399 will_dirty[i+1]&=~(1<<r);
7404 // Merge in delay slot
7405 for(r=0;r<HOST_REGS;r++) {
7406 if(r!=EXCLUDE_REG) {
7408 // Might not dirty if likely branch is not taken
7409 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7410 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7411 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7412 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7413 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7414 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7415 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7416 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7417 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7418 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7419 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7420 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7421 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7422 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7427 // Merge in delay slot
7428 for(r=0;r<HOST_REGS;r++) {
7429 if(r!=EXCLUDE_REG) {
7430 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7431 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7432 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7433 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7434 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7435 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7436 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7437 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7438 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7439 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7443 #ifndef DESTRUCTIVE_WRITEBACK
7444 branch_regs[i].dirty&=wont_dirty_i;
7446 branch_regs[i].dirty|=will_dirty_i;
7451 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7453 // SYSCALL instruction (software interrupt)
7457 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7459 // ERET instruction (return from interrupt)
7463 will_dirty_next=will_dirty_i;
7464 wont_dirty_next=wont_dirty_i;
7465 for(r=0;r<HOST_REGS;r++) {
7466 if(r!=EXCLUDE_REG) {
7467 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7468 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7469 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7470 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7471 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7472 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7473 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7474 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7476 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
7478 // Don't store a register immediately after writing it,
7479 // may prevent dual-issue.
7480 if((regs[i].regmap[r]&63)==rt1[i-1]) wont_dirty_i|=1<<r;
7481 if((regs[i].regmap[r]&63)==rt2[i-1]) wont_dirty_i|=1<<r;
7487 will_dirty[i]=will_dirty_i;
7488 wont_dirty[i]=wont_dirty_i;
7489 // Mark registers that won't be dirtied as not dirty
7491 /*printf("wr (%d,%d) %x will:",istart,iend,start+i*4);
7492 for(r=0;r<HOST_REGS;r++) {
7493 if((will_dirty_i>>r)&1) {
7499 //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=FJUMP)) {
7500 regs[i].dirty|=will_dirty_i;
7501 #ifndef DESTRUCTIVE_WRITEBACK
7502 regs[i].dirty&=wont_dirty_i;
7503 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7505 if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
7506 for(r=0;r<HOST_REGS;r++) {
7507 if(r!=EXCLUDE_REG) {
7508 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
7509 regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
7510 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7518 for(r=0;r<HOST_REGS;r++) {
7519 if(r!=EXCLUDE_REG) {
7520 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
7521 regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
7522 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7530 // Deal with changed mappings
7531 temp_will_dirty=will_dirty_i;
7532 temp_wont_dirty=wont_dirty_i;
7533 for(r=0;r<HOST_REGS;r++) {
7534 if(r!=EXCLUDE_REG) {
7536 if(regs[i].regmap[r]==regmap_pre[i][r]) {
7538 #ifndef DESTRUCTIVE_WRITEBACK
7539 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7541 regs[i].wasdirty|=will_dirty_i&(1<<r);
7544 else if((nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
7545 // Register moved to a different register
7546 will_dirty_i&=~(1<<r);
7547 wont_dirty_i&=~(1<<r);
7548 will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
7549 wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
7551 #ifndef DESTRUCTIVE_WRITEBACK
7552 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7554 regs[i].wasdirty|=will_dirty_i&(1<<r);
7558 will_dirty_i&=~(1<<r);
7559 wont_dirty_i&=~(1<<r);
7560 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7561 will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7562 wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7565 /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);/*assert(!((will_dirty>>r)&1));*/
7574 void disassemble_inst(int i)
7576 if (bt[i]) printf("*"); else printf(" ");
7579 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7581 printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
7583 printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
7585 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7587 if (opcode[i]==0x9&&rt1[i]!=31)
7588 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i]);
7590 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7593 printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break;
7595 if(opcode[i]==0xf) //LUI
7596 printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],rt1[i],imm[i]&0xffff);
7598 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7602 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7606 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rs2[i],rs1[i],imm[i]);
7610 printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i],rs2[i]);
7613 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rs1[i],rs2[i]);
7616 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7619 if((opcode2[i]&0x1d)==0x10)
7620 printf (" %x: %s r%d\n",start+i*4,insn[i],rt1[i]);
7621 else if((opcode2[i]&0x1d)==0x11)
7622 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7624 printf (" %x: %s\n",start+i*4,insn[i]);
7628 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC0
7629 else if(opcode2[i]==4)
7630 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC0
7631 else printf (" %x: %s\n",start+i*4,insn[i]);
7635 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC1
7636 else if(opcode2[i]>3)
7637 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC1
7638 else printf (" %x: %s\n",start+i*4,insn[i]);
7642 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC2
7643 else if(opcode2[i]>3)
7644 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC2
7645 else printf (" %x: %s\n",start+i*4,insn[i]);
7648 printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7651 printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7654 printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
7657 //printf (" %s %8x\n",insn[i],source[i]);
7658 printf (" %x: %s\n",start+i*4,insn[i]);
7662 void new_dynarec_init()
7664 printf("Init new dynarec\n");
7665 out=(u_char *)BASE_ADDR;
7666 if (mmap (out, 1<<TARGET_SIZE_2,
7667 PROT_READ | PROT_WRITE | PROT_EXEC,
7668 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
7669 -1, 0) <= 0) {printf("mmap() failed\n");}
7671 rdword=&readmem_dword;
7672 fake_pc.f.r.rs=&readmem_dword;
7673 fake_pc.f.r.rt=&readmem_dword;
7674 fake_pc.f.r.rd=&readmem_dword;
7677 for(n=0x80000;n<0x80800;n++)
7679 for(n=0;n<65536;n++)
7680 hash_table[n][0]=hash_table[n][2]=-1;
7681 memset(mini_ht,-1,sizeof(mini_ht));
7682 memset(restore_candidate,0,sizeof(restore_candidate));
7684 expirep=16384; // Expiry pointer, +2 blocks
7685 pending_exception=0;
7688 // Copy this into local area so we don't have to put it in every literal pool
7689 invc_ptr=invalid_code;
7694 for(n=0;n<524288;n++) // 0 .. 0x7FFFFFFF
7696 for(n=524288;n<526336;n++) // 0x80000000 .. 0x807FFFFF
7697 memory_map[n]=((u_int)rdram-0x80000000)>>2;
7698 for(n=526336;n<1048576;n++) // 0x80800000 .. 0xFFFFFFFF
7701 for(n=0;n<0x8000;n++) { // 0 .. 0x7FFFFFFF
7702 writemem[n] = write_nomem_new;
7703 writememb[n] = write_nomemb_new;
7704 writememh[n] = write_nomemh_new;
7706 writememd[n] = write_nomemd_new;
7708 readmem[n] = read_nomem_new;
7709 readmemb[n] = read_nomemb_new;
7710 readmemh[n] = read_nomemh_new;
7712 readmemd[n] = read_nomemd_new;
7715 for(n=0x8000;n<0x8080;n++) { // 0x80000000 .. 0x807FFFFF
7716 writemem[n] = write_rdram_new;
7717 writememb[n] = write_rdramb_new;
7718 writememh[n] = write_rdramh_new;
7720 writememd[n] = write_rdramd_new;
7723 for(n=0xC000;n<0x10000;n++) { // 0xC0000000 .. 0xFFFFFFFF
7724 writemem[n] = write_nomem_new;
7725 writememb[n] = write_nomemb_new;
7726 writememh[n] = write_nomemh_new;
7728 writememd[n] = write_nomemd_new;
7730 readmem[n] = read_nomem_new;
7731 readmemb[n] = read_nomemb_new;
7732 readmemh[n] = read_nomemh_new;
7734 readmemd[n] = read_nomemd_new;
7742 void new_dynarec_cleanup()
7745 if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0) {printf("munmap() failed\n");}
7746 for(n=0;n<4096;n++) ll_clear(jump_in+n);
7747 for(n=0;n<4096;n++) ll_clear(jump_out+n);
7748 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7750 if (munmap (ROM_COPY, 67108864) < 0) {printf("munmap() failed\n");}
7754 int new_recompile_block(int addr)
7757 if(addr==0x800cd050) {
7759 for(block=0x80000;block<0x80800;block++) invalidate_block(block);
7761 for(n=0;n<=2048;n++) ll_clear(jump_dirty+n);
7764 //if(Count==365117028) tracedebug=1;
7765 assem_debug("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7766 //printf("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7767 //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
7769 //printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
7770 //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
7771 /*if(Count>=312978186) {
7775 start = (u_int)addr&~3;
7776 //assert(((u_int)addr&1)==0);
7778 if (Config.HLE && start == 0x80001000) // hlecall
7780 // XXX: is this enough? Maybe check hleSoftCall?
7781 u_int beginning=(u_int)out;
7782 u_int page=get_page(start);
7783 invalid_code[start>>12]=0;
7784 emit_movimm(start,0);
7785 emit_writeword(0,(int)&pcaddr);
7786 emit_jmp((int)new_dyna_leave);
7788 __clear_cache((void *)beginning,out);
7790 ll_add(jump_in+page,start,(void *)beginning);
7793 else if ((u_int)addr < 0x00200000 ||
7794 (0xa0000000 <= addr && addr < 0xa0200000)) {
7795 // used for BIOS calls mostly?
7796 source = (u_int *)((u_int)rdram+(start&0x1fffff));
7797 pagelimit = (addr&0xa0000000)|0x00200000;
7799 else if (!Config.HLE && (
7800 /* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
7801 (0xbfc00000 <= addr && addr < 0xbfc80000))) {
7803 source = (u_int *)((u_int)psxR+(start&0x7ffff));
7804 pagelimit = (addr&0xfff00000)|0x80000;
7809 if ((int)addr >= 0xa4000000 && (int)addr < 0xa4001000) {
7810 source = (u_int *)((u_int)SP_DMEM+start-0xa4000000);
7811 pagelimit = 0xa4001000;
7815 if ((int)addr >= 0x80000000 && (int)addr < 0x80000000+RAM_SIZE) {
7816 source = (u_int *)((u_int)rdram+start-0x80000000);
7817 pagelimit = 0x80000000+RAM_SIZE;
7820 else if ((signed int)addr >= (signed int)0xC0000000) {
7821 //printf("addr=%x mm=%x\n",(u_int)addr,(memory_map[start>>12]<<2));
7822 //if(tlb_LUT_r[start>>12])
7823 //source = (u_int *)(((int)rdram)+(tlb_LUT_r[start>>12]&0xFFFFF000)+(((int)addr)&0xFFF)-0x80000000);
7824 if((signed int)memory_map[start>>12]>=0) {
7825 source = (u_int *)((u_int)(start+(memory_map[start>>12]<<2)));
7826 pagelimit=(start+4096)&0xFFFFF000;
7827 int map=memory_map[start>>12];
7830 //printf("start: %x next: %x\n",map,memory_map[pagelimit>>12]);
7831 if((map&0xBFFFFFFF)==(memory_map[pagelimit>>12]&0xBFFFFFFF)) pagelimit+=4096;
7833 assem_debug("pagelimit=%x\n",pagelimit);
7834 assem_debug("mapping=%x (%x)\n",memory_map[start>>12],(memory_map[start>>12]<<2)+start);
7837 assem_debug("Compile at unmapped memory address: %x \n", (int)addr);
7838 //assem_debug("start: %x next: %x\n",memory_map[start>>12],memory_map[(start+4096)>>12]);
7839 return -1; // Caller will invoke exception handler
7841 //printf("source= %x\n",(int)source);
7845 printf("Compile at bogus memory address: %x \n", (int)addr);
7849 /* Pass 1: disassemble */
7850 /* Pass 2: register dependencies, branch targets */
7851 /* Pass 3: register allocation */
7852 /* Pass 4: branch dependencies */
7853 /* Pass 5: pre-alloc */
7854 /* Pass 6: optimize clean/dirty state */
7855 /* Pass 7: flag 32-bit registers */
7856 /* Pass 8: assembly */
7857 /* Pass 9: linker */
7858 /* Pass 10: garbage collection / free memory */
7862 unsigned int type,op,op2;
7864 //printf("addr = %x source = %x %x\n", addr,source,source[0]);
7866 /* Pass 1 disassembly */
7868 for(i=0;!done;i++) {
7869 bt[i]=0;likely[i]=0;op2=0;
7870 opcode[i]=op=source[i]>>26;
7873 case 0x00: strcpy(insn[i],"special"); type=NI;
7877 case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
7878 case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
7879 case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
7880 case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
7881 case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
7882 case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
7883 case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
7884 case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
7885 case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
7886 case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
7887 case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
7888 case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
7889 case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
7890 case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
7891 case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
7892 case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
7893 case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
7894 case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
7895 case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
7896 case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
7897 case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
7898 case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
7899 case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
7900 case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
7901 case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
7902 case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
7903 case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
7904 case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
7905 case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
7906 case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
7907 case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
7908 case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
7909 case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
7910 case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
7911 case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
7912 case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
7913 case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
7914 case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
7915 case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
7916 case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
7917 case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
7918 case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
7919 case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
7920 case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
7921 case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
7922 case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
7923 case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
7924 case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
7925 case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
7926 case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
7927 case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
7928 case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
7931 case 0x01: strcpy(insn[i],"regimm"); type=NI;
7932 op2=(source[i]>>16)&0x1f;
7935 case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
7936 case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
7937 case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
7938 case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
7939 case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
7940 case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
7941 case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
7942 case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
7943 case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
7944 case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
7945 case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
7946 case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
7947 case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
7948 case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
7951 case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
7952 case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
7953 case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
7954 case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
7955 case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
7956 case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
7957 case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
7958 case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
7959 case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
7960 case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
7961 case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
7962 case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
7963 case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
7964 case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
7965 case 0x10: strcpy(insn[i],"cop0"); type=NI;
7966 op2=(source[i]>>21)&0x1f;
7969 case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
7970 case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
7971 case 0x10: strcpy(insn[i],"tlb"); type=NI;
7972 switch(source[i]&0x3f)
7974 case 0x01: strcpy(insn[i],"TLBR"); type=COP0; break;
7975 case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break;
7976 case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break;
7977 case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break;
7979 case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
7981 case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
7986 case 0x11: strcpy(insn[i],"cop1"); type=NI;
7987 op2=(source[i]>>21)&0x1f;
7990 case 0x00: strcpy(insn[i],"MFC1"); type=COP1; break;
7991 case 0x01: strcpy(insn[i],"DMFC1"); type=COP1; break;
7992 case 0x02: strcpy(insn[i],"CFC1"); type=COP1; break;
7993 case 0x04: strcpy(insn[i],"MTC1"); type=COP1; break;
7994 case 0x05: strcpy(insn[i],"DMTC1"); type=COP1; break;
7995 case 0x06: strcpy(insn[i],"CTC1"); type=COP1; break;
7996 case 0x08: strcpy(insn[i],"BC1"); type=FJUMP;
7997 switch((source[i]>>16)&0x3)
7999 case 0x00: strcpy(insn[i],"BC1F"); break;
8000 case 0x01: strcpy(insn[i],"BC1T"); break;
8001 case 0x02: strcpy(insn[i],"BC1FL"); break;
8002 case 0x03: strcpy(insn[i],"BC1TL"); break;
8005 case 0x10: strcpy(insn[i],"C1.S"); type=NI;
8006 switch(source[i]&0x3f)
8008 case 0x00: strcpy(insn[i],"ADD.S"); type=FLOAT; break;
8009 case 0x01: strcpy(insn[i],"SUB.S"); type=FLOAT; break;
8010 case 0x02: strcpy(insn[i],"MUL.S"); type=FLOAT; break;
8011 case 0x03: strcpy(insn[i],"DIV.S"); type=FLOAT; break;
8012 case 0x04: strcpy(insn[i],"SQRT.S"); type=FLOAT; break;
8013 case 0x05: strcpy(insn[i],"ABS.S"); type=FLOAT; break;
8014 case 0x06: strcpy(insn[i],"MOV.S"); type=FLOAT; break;
8015 case 0x07: strcpy(insn[i],"NEG.S"); type=FLOAT; break;
8016 case 0x08: strcpy(insn[i],"ROUND.L.S"); type=FCONV; break;
8017 case 0x09: strcpy(insn[i],"TRUNC.L.S"); type=FCONV; break;
8018 case 0x0A: strcpy(insn[i],"CEIL.L.S"); type=FCONV; break;
8019 case 0x0B: strcpy(insn[i],"FLOOR.L.S"); type=FCONV; break;
8020 case 0x0C: strcpy(insn[i],"ROUND.W.S"); type=FCONV; break;
8021 case 0x0D: strcpy(insn[i],"TRUNC.W.S"); type=FCONV; break;
8022 case 0x0E: strcpy(insn[i],"CEIL.W.S"); type=FCONV; break;
8023 case 0x0F: strcpy(insn[i],"FLOOR.W.S"); type=FCONV; break;
8024 case 0x21: strcpy(insn[i],"CVT.D.S"); type=FCONV; break;
8025 case 0x24: strcpy(insn[i],"CVT.W.S"); type=FCONV; break;
8026 case 0x25: strcpy(insn[i],"CVT.L.S"); type=FCONV; break;
8027 case 0x30: strcpy(insn[i],"C.F.S"); type=FCOMP; break;
8028 case 0x31: strcpy(insn[i],"C.UN.S"); type=FCOMP; break;
8029 case 0x32: strcpy(insn[i],"C.EQ.S"); type=FCOMP; break;
8030 case 0x33: strcpy(insn[i],"C.UEQ.S"); type=FCOMP; break;
8031 case 0x34: strcpy(insn[i],"C.OLT.S"); type=FCOMP; break;
8032 case 0x35: strcpy(insn[i],"C.ULT.S"); type=FCOMP; break;
8033 case 0x36: strcpy(insn[i],"C.OLE.S"); type=FCOMP; break;
8034 case 0x37: strcpy(insn[i],"C.ULE.S"); type=FCOMP; break;
8035 case 0x38: strcpy(insn[i],"C.SF.S"); type=FCOMP; break;
8036 case 0x39: strcpy(insn[i],"C.NGLE.S"); type=FCOMP; break;
8037 case 0x3A: strcpy(insn[i],"C.SEQ.S"); type=FCOMP; break;
8038 case 0x3B: strcpy(insn[i],"C.NGL.S"); type=FCOMP; break;
8039 case 0x3C: strcpy(insn[i],"C.LT.S"); type=FCOMP; break;
8040 case 0x3D: strcpy(insn[i],"C.NGE.S"); type=FCOMP; break;
8041 case 0x3E: strcpy(insn[i],"C.LE.S"); type=FCOMP; break;
8042 case 0x3F: strcpy(insn[i],"C.NGT.S"); type=FCOMP; break;
8045 case 0x11: strcpy(insn[i],"C1.D"); type=NI;
8046 switch(source[i]&0x3f)
8048 case 0x00: strcpy(insn[i],"ADD.D"); type=FLOAT; break;
8049 case 0x01: strcpy(insn[i],"SUB.D"); type=FLOAT; break;
8050 case 0x02: strcpy(insn[i],"MUL.D"); type=FLOAT; break;
8051 case 0x03: strcpy(insn[i],"DIV.D"); type=FLOAT; break;
8052 case 0x04: strcpy(insn[i],"SQRT.D"); type=FLOAT; break;
8053 case 0x05: strcpy(insn[i],"ABS.D"); type=FLOAT; break;
8054 case 0x06: strcpy(insn[i],"MOV.D"); type=FLOAT; break;
8055 case 0x07: strcpy(insn[i],"NEG.D"); type=FLOAT; break;
8056 case 0x08: strcpy(insn[i],"ROUND.L.D"); type=FCONV; break;
8057 case 0x09: strcpy(insn[i],"TRUNC.L.D"); type=FCONV; break;
8058 case 0x0A: strcpy(insn[i],"CEIL.L.D"); type=FCONV; break;
8059 case 0x0B: strcpy(insn[i],"FLOOR.L.D"); type=FCONV; break;
8060 case 0x0C: strcpy(insn[i],"ROUND.W.D"); type=FCONV; break;
8061 case 0x0D: strcpy(insn[i],"TRUNC.W.D"); type=FCONV; break;
8062 case 0x0E: strcpy(insn[i],"CEIL.W.D"); type=FCONV; break;
8063 case 0x0F: strcpy(insn[i],"FLOOR.W.D"); type=FCONV; break;
8064 case 0x20: strcpy(insn[i],"CVT.S.D"); type=FCONV; break;
8065 case 0x24: strcpy(insn[i],"CVT.W.D"); type=FCONV; break;
8066 case 0x25: strcpy(insn[i],"CVT.L.D"); type=FCONV; break;
8067 case 0x30: strcpy(insn[i],"C.F.D"); type=FCOMP; break;
8068 case 0x31: strcpy(insn[i],"C.UN.D"); type=FCOMP; break;
8069 case 0x32: strcpy(insn[i],"C.EQ.D"); type=FCOMP; break;
8070 case 0x33: strcpy(insn[i],"C.UEQ.D"); type=FCOMP; break;
8071 case 0x34: strcpy(insn[i],"C.OLT.D"); type=FCOMP; break;
8072 case 0x35: strcpy(insn[i],"C.ULT.D"); type=FCOMP; break;
8073 case 0x36: strcpy(insn[i],"C.OLE.D"); type=FCOMP; break;
8074 case 0x37: strcpy(insn[i],"C.ULE.D"); type=FCOMP; break;
8075 case 0x38: strcpy(insn[i],"C.SF.D"); type=FCOMP; break;
8076 case 0x39: strcpy(insn[i],"C.NGLE.D"); type=FCOMP; break;
8077 case 0x3A: strcpy(insn[i],"C.SEQ.D"); type=FCOMP; break;
8078 case 0x3B: strcpy(insn[i],"C.NGL.D"); type=FCOMP; break;
8079 case 0x3C: strcpy(insn[i],"C.LT.D"); type=FCOMP; break;
8080 case 0x3D: strcpy(insn[i],"C.NGE.D"); type=FCOMP; break;
8081 case 0x3E: strcpy(insn[i],"C.LE.D"); type=FCOMP; break;
8082 case 0x3F: strcpy(insn[i],"C.NGT.D"); type=FCOMP; break;
8085 case 0x14: strcpy(insn[i],"C1.W"); type=NI;
8086 switch(source[i]&0x3f)
8088 case 0x20: strcpy(insn[i],"CVT.S.W"); type=FCONV; break;
8089 case 0x21: strcpy(insn[i],"CVT.D.W"); type=FCONV; break;
8092 case 0x15: strcpy(insn[i],"C1.L"); type=NI;
8093 switch(source[i]&0x3f)
8095 case 0x20: strcpy(insn[i],"CVT.S.L"); type=FCONV; break;
8096 case 0x21: strcpy(insn[i],"CVT.D.L"); type=FCONV; break;
8102 case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
8103 case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
8104 case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
8105 case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
8106 case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
8107 case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
8108 case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
8109 case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
8111 case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
8112 case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
8113 case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
8114 case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
8115 case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
8116 case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
8117 case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
8118 case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
8119 case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
8120 case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
8121 case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
8122 case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
8124 case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
8125 case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
8127 case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
8128 case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
8129 case 0x30: strcpy(insn[i],"LL"); type=NI; break;
8130 case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
8132 case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
8133 case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
8134 case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
8136 case 0x38: strcpy(insn[i],"SC"); type=NI; break;
8137 case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
8139 case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
8140 case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
8141 case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
8144 case 0x12: strcpy(insn[i],"COP2"); type=NI;
8145 // note: COP MIPS-1 encoding differs from MIPS32
8146 op2=(source[i]>>21)&0x1f;
8147 if (source[i]&0x3f) {
8148 if (gte_handlers[source[i]&0x3f]!=NULL) {
8149 snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
8155 case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
8156 case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
8157 case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
8158 case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
8161 case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
8162 case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
8163 case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
8165 default: strcpy(insn[i],"???"); type=NI;
8166 printf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
8170 /* detect branch in delay slot early */
8171 if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
8172 opcode[i+1]=source[i+1]>>26;
8173 opcode2[i+1]=source[i+1]&0x3f;
8174 if((0<opcode[i+1]&&opcode[i+1]<8)||(opcode[i+1]==0&&(opcode2[i+1]==8||opcode2[i+1]==9))) {
8175 printf("branch in delay slot @%08x (%08x)\n", addr + i*4+4, addr);
8176 // don't handle first branch and call interpreter if it's hit
8183 /* Get registers/immediates */
8191 rs1[i]=(source[i]>>21)&0x1f;
8193 rt1[i]=(source[i]>>16)&0x1f;
8195 imm[i]=(short)source[i];
8199 rs1[i]=(source[i]>>21)&0x1f;
8200 rs2[i]=(source[i]>>16)&0x1f;
8203 imm[i]=(short)source[i];
8204 if(op==0x2c||op==0x2d||op==0x3f) us1[i]=rs2[i]; // 64-bit SDL/SDR/SD
8207 // LWL/LWR only load part of the register,
8208 // therefore the target register must be treated as a source too
8209 rs1[i]=(source[i]>>21)&0x1f;
8210 rs2[i]=(source[i]>>16)&0x1f;
8211 rt1[i]=(source[i]>>16)&0x1f;
8213 imm[i]=(short)source[i];
8214 if(op==0x1a||op==0x1b) us1[i]=rs2[i]; // LDR/LDL
8215 if(op==0x26) dep1[i]=rt1[i]; // LWR
8218 if (op==0x0f) rs1[i]=0; // LUI instruction has no source register
8219 else rs1[i]=(source[i]>>21)&0x1f;
8221 rt1[i]=(source[i]>>16)&0x1f;
8223 if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
8224 imm[i]=(unsigned short)source[i];
8226 imm[i]=(short)source[i];
8228 if(op==0x18||op==0x19) us1[i]=rs1[i]; // DADDI/DADDIU
8229 if(op==0x0a||op==0x0b) us1[i]=rs1[i]; // SLTI/SLTIU
8230 if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI
8237 // The JAL instruction writes to r31.
8244 rs1[i]=(source[i]>>21)&0x1f;
8248 // The JALR instruction writes to rd.
8250 rt1[i]=(source[i]>>11)&0x1f;
8255 rs1[i]=(source[i]>>21)&0x1f;
8256 rs2[i]=(source[i]>>16)&0x1f;
8259 if(op&2) { // BGTZ/BLEZ
8267 rs1[i]=(source[i]>>21)&0x1f;
8272 if(op2&0x10) { // BxxAL
8274 // NOTE: If the branch is not taken, r31 is still overwritten
8276 likely[i]=(op2&2)>>1;
8283 likely[i]=((source[i])>>17)&1;
8286 rs1[i]=(source[i]>>21)&0x1f; // source
8287 rs2[i]=(source[i]>>16)&0x1f; // subtract amount
8288 rt1[i]=(source[i]>>11)&0x1f; // destination
8290 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
8291 us1[i]=rs1[i];us2[i]=rs2[i];
8293 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
8294 dep1[i]=rs1[i];dep2[i]=rs2[i];
8296 else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB
8297 dep1[i]=rs1[i];dep2[i]=rs2[i];
8301 rs1[i]=(source[i]>>21)&0x1f; // source
8302 rs2[i]=(source[i]>>16)&0x1f; // divisor
8305 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
8306 us1[i]=rs1[i];us2[i]=rs2[i];
8314 if(op2==0x10) rs1[i]=HIREG; // MFHI
8315 if(op2==0x11) rt1[i]=HIREG; // MTHI
8316 if(op2==0x12) rs1[i]=LOREG; // MFLO
8317 if(op2==0x13) rt1[i]=LOREG; // MTLO
8318 if((op2&0x1d)==0x10) rt1[i]=(source[i]>>11)&0x1f; // MFxx
8319 if((op2&0x1d)==0x11) rs1[i]=(source[i]>>21)&0x1f; // MTxx
8323 rs1[i]=(source[i]>>16)&0x1f; // target of shift
8324 rs2[i]=(source[i]>>21)&0x1f; // shift amount
8325 rt1[i]=(source[i]>>11)&0x1f; // destination
8327 // DSLLV/DSRLV/DSRAV are 64-bit
8328 if(op2>=0x14&&op2<=0x17) us1[i]=rs1[i];
8331 rs1[i]=(source[i]>>16)&0x1f;
8333 rt1[i]=(source[i]>>11)&0x1f;
8335 imm[i]=(source[i]>>6)&0x1f;
8336 // DSxx32 instructions
8337 if(op2>=0x3c) imm[i]|=0x20;
8338 // DSLL/DSRL/DSRA/DSRA32/DSRL32 but not DSLL32 require 64-bit source
8339 if(op2>=0x38&&op2!=0x3c) us1[i]=rs1[i];
8346 if(op2==0) rt1[i]=(source[i]>>16)&0x1F; // MFC0
8347 if(op2==4) rs1[i]=(source[i]>>16)&0x1F; // MTC0
8348 if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status
8349 if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET
8357 if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
8358 if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
8359 if(op2==5) us1[i]=rs1[i]; // DMTC1
8363 rs1[i]=(source[i]>>21)&0x1F;
8367 imm[i]=(short)source[i];
8370 rs1[i]=(source[i]>>21)&0x1F;
8374 imm[i]=(short)source[i];
8403 /* Calculate branch target addresses */
8405 ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
8406 else if(type==CJUMP&&rs1[i]==rs2[i]&&(op&1))
8407 ba[i]=start+i*4+8; // Ignore never taken branch
8408 else if(type==SJUMP&&rs1[i]==0&&!(op2&1))
8409 ba[i]=start+i*4+8; // Ignore never taken branch
8410 else if(type==CJUMP||type==SJUMP||type==FJUMP)
8411 ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
8413 /* Is this the end of the block? */
8414 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
8415 if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
8419 if(stop_after_jal) done=1;
8421 if((source[i+1]&0xfc00003f)==0x0d) done=1;
8423 // Don't recompile stuff that's already compiled
8424 if(check_addr(start+i*4+4)) done=1;
8425 // Don't get too close to the limit
8426 if(i>MAXBLOCK/2) done=1;
8428 if(itype[i]==SYSCALL&&stop_after_jal) done=1;
8429 if(itype[i]==HLECALL||itype[i]==INTCALL) done=2;
8431 // Does the block continue due to a branch?
8434 if(ba[j]==start+i*4+4) done=j=0;
8435 if(ba[j]==start+i*4+8) done=j=0;
8438 //assert(i<MAXBLOCK-1);
8439 if(start+i*4==pagelimit-4) done=1;
8440 assert(start+i*4<pagelimit);
8441 if (i==MAXBLOCK-1) done=1;
8442 // Stop if we're compiling junk
8443 if(itype[i]==NI&&opcode[i]==0x11) {
8444 done=stop_after_jal=1;
8445 printf("Disabled speculative precompilation\n");
8449 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP||itype[i-1]==FJUMP) {
8450 if(start+i*4==pagelimit) {
8456 /* Pass 2 - Register dependencies and branch targets */
8458 unneeded_registers(0,slen-1,0);
8460 /* Pass 3 - Register allocation */
8462 struct regstat current; // Current register allocations/status
8465 current.u=unneeded_reg[0];
8466 current.uu=unneeded_reg_upper[0];
8467 clear_all_regs(current.regmap);
8468 alloc_reg(¤t,0,CCREG);
8469 dirty_reg(¤t,CCREG);
8476 provisional_32bit();
8479 // First instruction is delay slot
8484 unneeded_reg_upper[0]=1;
8485 current.regmap[HOST_BTREG]=BTREG;
8493 for(hr=0;hr<HOST_REGS;hr++)
8495 // Is this really necessary?
8496 if(current.regmap[hr]==0) current.regmap[hr]=-1;
8502 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
8504 if(rs1[i-2]==0||rs2[i-2]==0)
8507 current.is32|=1LL<<rs1[i-2];
8508 int hr=get_reg(current.regmap,rs1[i-2]|64);
8509 if(hr>=0) current.regmap[hr]=-1;
8512 current.is32|=1LL<<rs2[i-2];
8513 int hr=get_reg(current.regmap,rs2[i-2]|64);
8514 if(hr>=0) current.regmap[hr]=-1;
8519 // If something jumps here with 64-bit values
8520 // then promote those registers to 64 bits
8523 uint64_t temp_is32=current.is32;
8526 if(ba[j]==start+i*4)
8527 temp_is32&=branch_regs[j].is32;
8531 if(ba[j]==start+i*4)
8535 if(temp_is32!=current.is32) {
8536 //printf("dumping 32-bit regs (%x)\n",start+i*4);
8537 #ifdef DESTRUCTIVE_WRITEBACK
8538 for(hr=0;hr<HOST_REGS;hr++)
8540 int r=current.regmap[hr];
8543 if((current.dirty>>hr)&((current.is32&~temp_is32)>>r)&1) {
8545 //printf("restore %d\n",r);
8550 current.is32=temp_is32;
8554 memset(p32, 0xff, sizeof(p32));
8558 memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
8559 regs[i].wasconst=current.isconst;
8560 regs[i].was32=current.is32;
8561 regs[i].wasdirty=current.dirty;
8562 #ifdef DESTRUCTIVE_WRITEBACK
8563 // To change a dirty register from 32 to 64 bits, we must write
8564 // it out during the previous cycle (for branches, 2 cycles)
8565 if(i<slen-1&&bt[i+1]&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP)
8567 uint64_t temp_is32=current.is32;
8570 if(ba[j]==start+i*4+4)
8571 temp_is32&=branch_regs[j].is32;
8575 if(ba[j]==start+i*4+4)
8579 if(temp_is32!=current.is32) {
8580 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8581 for(hr=0;hr<HOST_REGS;hr++)
8583 int r=current.regmap[hr];
8586 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8587 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP)
8589 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63))
8591 //printf("dump %d/r%d\n",hr,r);
8592 current.regmap[hr]=-1;
8593 if(get_reg(current.regmap,r|64)>=0)
8594 current.regmap[get_reg(current.regmap,r|64)]=-1;
8602 else if(i<slen-2&&bt[i+2]&&(source[i-1]>>16)!=0x1000&&(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP))
8604 uint64_t temp_is32=current.is32;
8607 if(ba[j]==start+i*4+8)
8608 temp_is32&=branch_regs[j].is32;
8612 if(ba[j]==start+i*4+8)
8616 if(temp_is32!=current.is32) {
8617 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8618 for(hr=0;hr<HOST_REGS;hr++)
8620 int r=current.regmap[hr];
8623 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8624 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63)&&rs1[i+1]!=(r&63)&&rs2[i+1]!=(r&63))
8626 //printf("dump %d/r%d\n",hr,r);
8627 current.regmap[hr]=-1;
8628 if(get_reg(current.regmap,r|64)>=0)
8629 current.regmap[get_reg(current.regmap,r|64)]=-1;
8637 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
8639 current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
8640 current.uu=unneeded_reg_upper[i+1]&~((1LL<<us1[i])|(1LL<<us2[i]));
8641 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8650 current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
8651 current.uu=branch_unneeded_reg_upper[i]&~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
8652 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
8653 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8654 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8657 } else { printf("oops, branch at end of block with no delay slot\n");exit(1); }
8661 ds=0; // Skip delay slot, already allocated as part of branch
8662 // ...but we need to alloc it in case something jumps here
8664 current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
8665 current.uu=branch_unneeded_reg_upper[i-1]&unneeded_reg_upper[i+1];
8667 current.u=branch_unneeded_reg[i-1];
8668 current.uu=branch_unneeded_reg_upper[i-1];
8670 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8671 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8672 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8675 struct regstat temp;
8676 memcpy(&temp,¤t,sizeof(current));
8677 temp.wasdirty=temp.dirty;
8678 temp.was32=temp.is32;
8679 // TODO: Take into account unconditional branches, as below
8680 delayslot_alloc(&temp,i);
8681 memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
8682 regs[i].wasdirty=temp.wasdirty;
8683 regs[i].was32=temp.was32;
8684 regs[i].dirty=temp.dirty;
8685 regs[i].is32=temp.is32;
8689 // Create entry (branch target) regmap
8690 for(hr=0;hr<HOST_REGS;hr++)
8692 int r=temp.regmap[hr];
8694 if(r!=regmap_pre[i][hr]) {
8695 regs[i].regmap_entry[hr]=-1;
8700 if((current.u>>r)&1) {
8701 regs[i].regmap_entry[hr]=-1;
8702 regs[i].regmap[hr]=-1;
8703 //Don't clear regs in the delay slot as the branch might need them
8704 //current.regmap[hr]=-1;
8706 regs[i].regmap_entry[hr]=r;
8709 if((current.uu>>(r&63))&1) {
8710 regs[i].regmap_entry[hr]=-1;
8711 regs[i].regmap[hr]=-1;
8712 //Don't clear regs in the delay slot as the branch might need them
8713 //current.regmap[hr]=-1;
8715 regs[i].regmap_entry[hr]=r;
8719 // First instruction expects CCREG to be allocated
8720 if(i==0&&hr==HOST_CCREG)
8721 regs[i].regmap_entry[hr]=CCREG;
8723 regs[i].regmap_entry[hr]=-1;
8727 else { // Not delay slot
8730 //current.isconst=0; // DEBUG
8731 //current.wasconst=0; // DEBUG
8732 //regs[i].wasconst=0; // DEBUG
8733 clear_const(¤t,rt1[i]);
8734 alloc_cc(¤t,i);
8735 dirty_reg(¤t,CCREG);
8737 alloc_reg(¤t,i,31);
8738 dirty_reg(¤t,31);
8739 //assert(rs1[i+1]!=31&&rs2[i+1]!=31);
8740 assert(rt1[i+1]!=rt1[i]);
8742 alloc_reg(¤t,i,PTEMP);
8744 //current.is32|=1LL<<rt1[i];
8746 delayslot_alloc(¤t,i+1);
8747 //current.isconst=0; // DEBUG
8749 //printf("i=%d, isconst=%x\n",i,current.isconst);
8752 //current.isconst=0;
8753 //current.wasconst=0;
8754 //regs[i].wasconst=0;
8755 clear_const(¤t,rs1[i]);
8756 clear_const(¤t,rt1[i]);
8757 alloc_cc(¤t,i);
8758 dirty_reg(¤t,CCREG);
8759 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
8760 alloc_reg(¤t,i,rs1[i]);
8762 alloc_reg(¤t,i,rt1[i]);
8763 dirty_reg(¤t,rt1[i]);
8764 //assert(rs1[i+1]!=31&&rs2[i+1]!=31);
8765 assert(rt1[i+1]!=rt1[i]);
8767 alloc_reg(¤t,i,PTEMP);
8771 if(rs1[i]==31) { // JALR
8772 alloc_reg(¤t,i,RHASH);
8773 #ifndef HOST_IMM_ADDR32
8774 alloc_reg(¤t,i,RHTBL);
8778 delayslot_alloc(¤t,i+1);
8780 // The delay slot overwrites our source register,
8781 // allocate a temporary register to hold the old value.
8785 delayslot_alloc(¤t,i+1);
8787 alloc_reg(¤t,i,RTEMP);
8789 //current.isconst=0; // DEBUG
8793 //current.isconst=0;
8794 //current.wasconst=0;
8795 //regs[i].wasconst=0;
8796 clear_const(¤t,rs1[i]);
8797 clear_const(¤t,rs2[i]);
8798 if((opcode[i]&0x3E)==4) // BEQ/BNE
8800 alloc_cc(¤t,i);
8801 dirty_reg(¤t,CCREG);
8802 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
8803 if(rs2[i]) alloc_reg(¤t,i,rs2[i]);
8804 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8806 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
8807 if(rs2[i]) alloc_reg64(¤t,i,rs2[i]);
8809 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
8810 (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) {
8811 // The delay slot overwrites one of our conditions.
8812 // Allocate the branch condition registers instead.
8813 // Note that such a sequence of instructions could
8814 // be considered a bug since the branch can not be
8815 // re-executed if an exception occurs.
8819 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
8820 if(rs2[i]) alloc_reg(¤t,i,rs2[i]);
8821 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8823 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
8824 if(rs2[i]) alloc_reg64(¤t,i,rs2[i]);
8827 else delayslot_alloc(¤t,i+1);
8830 if((opcode[i]&0x3E)==6) // BLEZ/BGTZ
8832 alloc_cc(¤t,i);
8833 dirty_reg(¤t,CCREG);
8834 alloc_reg(¤t,i,rs1[i]);
8835 if(!(current.is32>>rs1[i]&1))
8837 alloc_reg64(¤t,i,rs1[i]);
8839 if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
8840 // The delay slot overwrites one of our conditions.
8841 // Allocate the branch condition registers instead.
8842 // Note that such a sequence of instructions could
8843 // be considered a bug since the branch can not be
8844 // re-executed if an exception occurs.
8848 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
8849 if(!((current.is32>>rs1[i])&1))
8851 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
8854 else delayslot_alloc(¤t,i+1);
8857 // Don't alloc the delay slot yet because we might not execute it
8858 if((opcode[i]&0x3E)==0x14) // BEQL/BNEL
8863 alloc_cc(¤t,i);
8864 dirty_reg(¤t,CCREG);
8865 alloc_reg(¤t,i,rs1[i]);
8866 alloc_reg(¤t,i,rs2[i]);
8867 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8869 alloc_reg64(¤t,i,rs1[i]);
8870 alloc_reg64(¤t,i,rs2[i]);
8874 if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL
8879 alloc_cc(¤t,i);
8880 dirty_reg(¤t,CCREG);
8881 alloc_reg(¤t,i,rs1[i]);
8882 if(!(current.is32>>rs1[i]&1))
8884 alloc_reg64(¤t,i,rs1[i]);
8888 //current.isconst=0;
8891 //current.isconst=0;
8892 //current.wasconst=0;
8893 //regs[i].wasconst=0;
8894 clear_const(¤t,rs1[i]);
8895 clear_const(¤t,rt1[i]);
8896 //if((opcode2[i]&0x1E)==0x0) // BLTZ/BGEZ
8897 if((opcode2[i]&0x0E)==0x0) // BLTZ/BGEZ
8899 alloc_cc(¤t,i);
8900 dirty_reg(¤t,CCREG);
8901 alloc_reg(¤t,i,rs1[i]);
8902 if(!(current.is32>>rs1[i]&1))
8904 alloc_reg64(¤t,i,rs1[i]);
8906 if (rt1[i]==31) { // BLTZAL/BGEZAL
8907 alloc_reg(¤t,i,31);
8908 dirty_reg(¤t,31);
8909 assert(rs1[i+1]!=31&&rs2[i+1]!=31);
8910 //#ifdef REG_PREFETCH
8911 //alloc_reg(¤t,i,PTEMP);
8913 //current.is32|=1LL<<rt1[i];
8915 if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
8916 // The delay slot overwrites the branch condition.
8917 // Allocate the branch condition registers instead.
8918 // Note that such a sequence of instructions could
8919 // be considered a bug since the branch can not be
8920 // re-executed if an exception occurs.
8924 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
8925 if(!((current.is32>>rs1[i])&1))
8927 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
8930 else delayslot_alloc(¤t,i+1);
8933 // Don't alloc the delay slot yet because we might not execute it
8934 if((opcode2[i]&0x1E)==0x2) // BLTZL/BGEZL
8939 alloc_cc(¤t,i);
8940 dirty_reg(¤t,CCREG);
8941 alloc_reg(¤t,i,rs1[i]);
8942 if(!(current.is32>>rs1[i]&1))
8944 alloc_reg64(¤t,i,rs1[i]);
8948 //current.isconst=0;
8954 if(likely[i]==0) // BC1F/BC1T
8956 // TODO: Theoretically we can run out of registers here on x86.
8957 // The delay slot can allocate up to six, and we need to check
8958 // CSREG before executing the delay slot. Possibly we can drop
8959 // the cycle count and then reload it after checking that the
8960 // FPU is in a usable state, or don't do out-of-order execution.
8961 alloc_cc(¤t,i);
8962 dirty_reg(¤t,CCREG);
8963 alloc_reg(¤t,i,FSREG);
8964 alloc_reg(¤t,i,CSREG);
8965 if(itype[i+1]==FCOMP) {
8966 // The delay slot overwrites the branch condition.
8967 // Allocate the branch condition registers instead.
8968 // Note that such a sequence of instructions could
8969 // be considered a bug since the branch can not be
8970 // re-executed if an exception occurs.
8971 alloc_cc(¤t,i);
8972 dirty_reg(¤t,CCREG);
8973 alloc_reg(¤t,i,CSREG);
8974 alloc_reg(¤t,i,FSREG);
8977 delayslot_alloc(¤t,i+1);
8978 alloc_reg(¤t,i+1,CSREG);
8982 // Don't alloc the delay slot yet because we might not execute it
8983 if(likely[i]) // BC1FL/BC1TL
8985 alloc_cc(¤t,i);
8986 dirty_reg(¤t,CCREG);
8987 alloc_reg(¤t,i,CSREG);
8988 alloc_reg(¤t,i,FSREG);
8994 imm16_alloc(¤t,i);
8998 load_alloc(¤t,i);
9002 store_alloc(¤t,i);
9005 alu_alloc(¤t,i);
9008 shift_alloc(¤t,i);
9011 multdiv_alloc(¤t,i);
9014 shiftimm_alloc(¤t,i);
9017 mov_alloc(¤t,i);
9020 cop0_alloc(¤t,i);
9024 cop1_alloc(¤t,i);
9027 c1ls_alloc(¤t,i);
9030 c2ls_alloc(¤t,i);
9033 c2op_alloc(¤t,i);
9036 fconv_alloc(¤t,i);
9039 float_alloc(¤t,i);
9042 fcomp_alloc(¤t,i);
9047 syscall_alloc(¤t,i);
9050 pagespan_alloc(¤t,i);
9054 // Drop the upper half of registers that have become 32-bit
9055 current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i]));
9056 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
9057 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9058 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9061 current.uu|=current.is32&((1LL<<rt1[i+1])|(1LL<<rt2[i+1]));
9062 current.uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
9063 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
9064 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9068 // Create entry (branch target) regmap
9069 for(hr=0;hr<HOST_REGS;hr++)
9072 r=current.regmap[hr];
9074 if(r!=regmap_pre[i][hr]) {
9075 // TODO: delay slot (?)
9076 or=get_reg(regmap_pre[i],r); // Get old mapping for this register
9077 if(or<0||(r&63)>=TEMPREG){
9078 regs[i].regmap_entry[hr]=-1;
9082 // Just move it to a different register
9083 regs[i].regmap_entry[hr]=r;
9084 // If it was dirty before, it's still dirty
9085 if((regs[i].wasdirty>>or)&1) dirty_reg(¤t,r&63);
9092 regs[i].regmap_entry[hr]=0;
9096 if((current.u>>r)&1) {
9097 regs[i].regmap_entry[hr]=-1;
9098 //regs[i].regmap[hr]=-1;
9099 current.regmap[hr]=-1;
9101 regs[i].regmap_entry[hr]=r;
9104 if((current.uu>>(r&63))&1) {
9105 regs[i].regmap_entry[hr]=-1;
9106 //regs[i].regmap[hr]=-1;
9107 current.regmap[hr]=-1;
9109 regs[i].regmap_entry[hr]=r;
9113 // Branches expect CCREG to be allocated at the target
9114 if(regmap_pre[i][hr]==CCREG)
9115 regs[i].regmap_entry[hr]=CCREG;
9117 regs[i].regmap_entry[hr]=-1;
9120 memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
9122 /* Branch post-alloc */
9125 current.was32=current.is32;
9126 current.wasdirty=current.dirty;
9127 switch(itype[i-1]) {
9129 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9130 branch_regs[i-1].isconst=0;
9131 branch_regs[i-1].wasconst=0;
9132 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9133 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9134 alloc_cc(&branch_regs[i-1],i-1);
9135 dirty_reg(&branch_regs[i-1],CCREG);
9136 if(rt1[i-1]==31) { // JAL
9137 alloc_reg(&branch_regs[i-1],i-1,31);
9138 dirty_reg(&branch_regs[i-1],31);
9139 branch_regs[i-1].is32|=1LL<<31;
9141 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9142 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9145 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9146 branch_regs[i-1].isconst=0;
9147 branch_regs[i-1].wasconst=0;
9148 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9149 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9150 alloc_cc(&branch_regs[i-1],i-1);
9151 dirty_reg(&branch_regs[i-1],CCREG);
9152 alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]);
9153 if(rt1[i-1]!=0) { // JALR
9154 alloc_reg(&branch_regs[i-1],i-1,rt1[i-1]);
9155 dirty_reg(&branch_regs[i-1],rt1[i-1]);
9156 branch_regs[i-1].is32|=1LL<<rt1[i-1];
9159 if(rs1[i-1]==31) { // JALR
9160 alloc_reg(&branch_regs[i-1],i-1,RHASH);
9161 #ifndef HOST_IMM_ADDR32
9162 alloc_reg(&branch_regs[i-1],i-1,RHTBL);
9166 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9167 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9170 if((opcode[i-1]&0x3E)==4) // BEQ/BNE
9172 alloc_cc(¤t,i-1);
9173 dirty_reg(¤t,CCREG);
9174 if((rs1[i-1]&&(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]))||
9175 (rs2[i-1]&&(rs2[i-1]==rt1[i]||rs2[i-1]==rt2[i]))) {
9176 // The delay slot overwrote one of our conditions
9177 // Delay slot goes after the test (in order)
9178 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9179 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9180 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9183 delayslot_alloc(¤t,i);
9188 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9189 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9190 // Alloc the branch condition registers
9191 if(rs1[i-1]) alloc_reg(¤t,i-1,rs1[i-1]);
9192 if(rs2[i-1]) alloc_reg(¤t,i-1,rs2[i-1]);
9193 if(!((current.is32>>rs1[i-1])&(current.is32>>rs2[i-1])&1))
9195 if(rs1[i-1]) alloc_reg64(¤t,i-1,rs1[i-1]);
9196 if(rs2[i-1]) alloc_reg64(¤t,i-1,rs2[i-1]);
9199 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9200 branch_regs[i-1].isconst=0;
9201 branch_regs[i-1].wasconst=0;
9202 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9203 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9206 if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ
9208 alloc_cc(¤t,i-1);
9209 dirty_reg(¤t,CCREG);
9210 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9211 // The delay slot overwrote the branch condition
9212 // Delay slot goes after the test (in order)
9213 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9214 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9215 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9218 delayslot_alloc(¤t,i);
9223 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9224 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9225 // Alloc the branch condition register
9226 alloc_reg(¤t,i-1,rs1[i-1]);
9227 if(!(current.is32>>rs1[i-1]&1))
9229 alloc_reg64(¤t,i-1,rs1[i-1]);
9232 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9233 branch_regs[i-1].isconst=0;
9234 branch_regs[i-1].wasconst=0;
9235 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9236 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9239 // Alloc the delay slot in case the branch is taken
9240 if((opcode[i-1]&0x3E)==0x14) // BEQL/BNEL
9242 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9243 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9244 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9245 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9246 alloc_cc(&branch_regs[i-1],i);
9247 dirty_reg(&branch_regs[i-1],CCREG);
9248 delayslot_alloc(&branch_regs[i-1],i);
9249 branch_regs[i-1].isconst=0;
9250 alloc_reg(¤t,i,CCREG); // Not taken path
9251 dirty_reg(¤t,CCREG);
9252 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9255 if((opcode[i-1]&0x3E)==0x16) // BLEZL/BGTZL
9257 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9258 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9259 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9260 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9261 alloc_cc(&branch_regs[i-1],i);
9262 dirty_reg(&branch_regs[i-1],CCREG);
9263 delayslot_alloc(&branch_regs[i-1],i);
9264 branch_regs[i-1].isconst=0;
9265 alloc_reg(¤t,i,CCREG); // Not taken path
9266 dirty_reg(¤t,CCREG);
9267 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9271 //if((opcode2[i-1]&0x1E)==0) // BLTZ/BGEZ
9272 if((opcode2[i-1]&0x0E)==0) // BLTZ/BGEZ
9274 alloc_cc(¤t,i-1);
9275 dirty_reg(¤t,CCREG);
9276 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9277 // The delay slot overwrote the branch condition
9278 // Delay slot goes after the test (in order)
9279 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9280 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9281 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9284 delayslot_alloc(¤t,i);
9289 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9290 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9291 // Alloc the branch condition register
9292 alloc_reg(¤t,i-1,rs1[i-1]);
9293 if(!(current.is32>>rs1[i-1]&1))
9295 alloc_reg64(¤t,i-1,rs1[i-1]);
9298 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9299 branch_regs[i-1].isconst=0;
9300 branch_regs[i-1].wasconst=0;
9301 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9302 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9305 // Alloc the delay slot in case the branch is taken
9306 if((opcode2[i-1]&0x1E)==2) // BLTZL/BGEZL
9308 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9309 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9310 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9311 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9312 alloc_cc(&branch_regs[i-1],i);
9313 dirty_reg(&branch_regs[i-1],CCREG);
9314 delayslot_alloc(&branch_regs[i-1],i);
9315 branch_regs[i-1].isconst=0;
9316 alloc_reg(¤t,i,CCREG); // Not taken path
9317 dirty_reg(¤t,CCREG);
9318 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9320 // FIXME: BLTZAL/BGEZAL
9321 if(opcode2[i-1]&0x10) { // BxxZAL
9322 alloc_reg(&branch_regs[i-1],i-1,31);
9323 dirty_reg(&branch_regs[i-1],31);
9324 branch_regs[i-1].is32|=1LL<<31;
9328 if(likely[i-1]==0) // BC1F/BC1T
9330 alloc_cc(¤t,i-1);
9331 dirty_reg(¤t,CCREG);
9332 if(itype[i]==FCOMP) {
9333 // The delay slot overwrote the branch condition
9334 // Delay slot goes after the test (in order)
9335 delayslot_alloc(¤t,i);
9340 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9341 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9342 // Alloc the branch condition register
9343 alloc_reg(¤t,i-1,FSREG);
9345 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9346 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9350 // Alloc the delay slot in case the branch is taken
9351 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9352 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9353 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9354 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9355 alloc_cc(&branch_regs[i-1],i);
9356 dirty_reg(&branch_regs[i-1],CCREG);
9357 delayslot_alloc(&branch_regs[i-1],i);
9358 branch_regs[i-1].isconst=0;
9359 alloc_reg(¤t,i,CCREG); // Not taken path
9360 dirty_reg(¤t,CCREG);
9361 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9366 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
9368 if(rt1[i-1]==31) // JAL/JALR
9370 // Subroutine call will return here, don't alloc any registers
9373 clear_all_regs(current.regmap);
9374 alloc_reg(¤t,i,CCREG);
9375 dirty_reg(¤t,CCREG);
9379 // Internal branch will jump here, match registers to caller
9380 current.is32=0x3FFFFFFFFLL;
9382 clear_all_regs(current.regmap);
9383 alloc_reg(¤t,i,CCREG);
9384 dirty_reg(¤t,CCREG);
9387 if(ba[j]==start+i*4+4) {
9388 memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
9389 current.is32=branch_regs[j].is32;
9390 current.dirty=branch_regs[j].dirty;
9395 if(ba[j]==start+i*4+4) {
9396 for(hr=0;hr<HOST_REGS;hr++) {
9397 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
9398 current.regmap[hr]=-1;
9400 current.is32&=branch_regs[j].is32;
9401 current.dirty&=branch_regs[j].dirty;
9410 // Count cycles in between branches
9412 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP||itype[i]==SYSCALL||itype[i]==HLECALL))
9421 flush_dirty_uppers(¤t);
9423 regs[i].is32=current.is32;
9424 regs[i].dirty=current.dirty;
9425 regs[i].isconst=current.isconst;
9426 memcpy(constmap[i],current.constmap,sizeof(current.constmap));
9428 for(hr=0;hr<HOST_REGS;hr++) {
9429 if(hr!=EXCLUDE_REG&®s[i].regmap[hr]>=0) {
9430 if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
9431 regs[i].wasconst&=~(1<<hr);
9435 if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
9438 /* Pass 4 - Cull unused host registers */
9442 for (i=slen-1;i>=0;i--)
9445 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9447 if(ba[i]<start || ba[i]>=(start+slen*4))
9449 // Branch out of this block, don't need anything
9455 // Need whatever matches the target
9457 int t=(ba[i]-start)>>2;
9458 for(hr=0;hr<HOST_REGS;hr++)
9460 if(regs[i].regmap_entry[hr]>=0) {
9461 if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
9465 // Conditional branch may need registers for following instructions
9466 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9469 nr|=needed_reg[i+2];
9470 for(hr=0;hr<HOST_REGS;hr++)
9472 if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
9473 //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
9477 // Don't need stuff which is overwritten
9478 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9479 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9480 // Merge in delay slot
9481 for(hr=0;hr<HOST_REGS;hr++)
9484 // These are overwritten unless the branch is "likely"
9485 // and the delay slot is nullified if not taken
9486 if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9487 if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9489 if(us1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9490 if(us2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9491 if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9492 if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9493 if(us1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9494 if(us2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9495 if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9496 if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9497 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1)) {
9498 if(dep1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9499 if(dep2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9501 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1)) {
9502 if(dep1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9503 if(dep2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9505 if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) {
9506 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9507 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9511 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
9513 // SYSCALL instruction (software interrupt)
9516 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
9518 // ERET instruction (return from interrupt)
9524 for(hr=0;hr<HOST_REGS;hr++) {
9525 if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
9526 if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
9527 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9528 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9532 for(hr=0;hr<HOST_REGS;hr++)
9534 // Overwritten registers are not needed
9535 if(rt1[i]&&rt1[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9536 if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9537 if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9538 // Source registers are needed
9539 if(us1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9540 if(us2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9541 if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr;
9542 if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr;
9543 if(us1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9544 if(us2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9545 if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9546 if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9547 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1)) {
9548 if(dep1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9549 if(dep1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9551 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1)) {
9552 if(dep2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9553 if(dep2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9555 if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) {
9556 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9557 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9559 // Don't store a register immediately after writing it,
9560 // may prevent dual-issue.
9561 // But do so if this is a branch target, otherwise we
9562 // might have to load the register before the branch.
9563 if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) {
9564 if((regmap_pre[i][hr]>0&®map_pre[i][hr]<64&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1)) ||
9565 (regmap_pre[i][hr]>64&&!((unneeded_reg_upper[i]>>(regmap_pre[i][hr]&63))&1)) ) {
9566 if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9567 if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9569 if((regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1)) ||
9570 (regs[i].regmap_entry[hr]>64&&!((unneeded_reg_upper[i]>>(regs[i].regmap_entry[hr]&63))&1)) ) {
9571 if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9572 if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9576 // Cycle count is needed at branches. Assume it is needed at the target too.
9577 if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==FJUMP||itype[i]==SPAN) {
9578 if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9579 if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9584 // Deallocate unneeded registers
9585 for(hr=0;hr<HOST_REGS;hr++)
9588 if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
9589 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9590 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9591 (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG)
9593 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9596 regs[i].regmap[hr]=-1;
9597 regs[i].isconst&=~(1<<hr);
9598 if(i<slen-2) regmap_pre[i+2][hr]=-1;
9602 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9604 int d1=0,d2=0,map=0,temp=0;
9605 if(get_reg(regs[i].regmap,rt1[i+1]|64)>=0||get_reg(branch_regs[i].regmap,rt1[i+1]|64)>=0)
9611 if(itype[i+1]==LOAD || itype[i+1]==LOADLR ||
9612 itype[i+1]==STORE || itype[i+1]==STORELR ||
9613 itype[i+1]==C1LS || itype[i+1]==C2LS)
9616 if(itype[i+1]==STORE || itype[i+1]==STORELR ||
9617 (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
9620 if(itype[i+1]==LOADLR || itype[i+1]==STORELR ||
9621 itype[i+1]==C1LS || itype[i+1]==C2LS)
9623 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9624 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9625 (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] &&
9626 (regs[i].regmap[hr]^64)!=us1[i+1] && (regs[i].regmap[hr]^64)!=us2[i+1] &&
9627 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9628 regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] &&
9629 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
9630 regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
9631 regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
9632 regs[i].regmap[hr]!=map )
9634 regs[i].regmap[hr]=-1;
9635 regs[i].isconst&=~(1<<hr);
9636 if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] &&
9637 (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] &&
9638 (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] &&
9639 (branch_regs[i].regmap[hr]^64)!=us1[i+1] && (branch_regs[i].regmap[hr]^64)!=us2[i+1] &&
9640 (branch_regs[i].regmap[hr]^64)!=d1 && (branch_regs[i].regmap[hr]^64)!=d2 &&
9641 branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] &&
9642 (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
9643 branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
9644 branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
9645 branch_regs[i].regmap[hr]!=map)
9647 branch_regs[i].regmap[hr]=-1;
9648 branch_regs[i].regmap_entry[hr]=-1;
9649 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9651 if(!likely[i]&&i<slen-2) {
9652 regmap_pre[i+2][hr]=-1;
9663 int d1=0,d2=0,map=-1,temp=-1;
9664 if(get_reg(regs[i].regmap,rt1[i]|64)>=0)
9670 if(itype[i]==LOAD || itype[i]==LOADLR ||
9671 itype[i]==STORE || itype[i]==STORELR ||
9672 itype[i]==C1LS || itype[i]==C2LS)
9674 } else if(itype[i]==STORE || itype[i]==STORELR ||
9675 (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
9678 if(itype[i]==LOADLR || itype[i]==STORELR ||
9679 itype[i]==C1LS || itype[i]==C2LS)
9681 if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9682 (regs[i].regmap[hr]^64)!=us1[i] && (regs[i].regmap[hr]^64)!=us2[i] &&
9683 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9684 regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] &&
9685 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map &&
9686 (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG))
9688 if(i<slen-1&&!is_ds[i]) {
9689 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]!=-1)
9690 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
9691 if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
9693 printf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
9694 assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
9696 regmap_pre[i+1][hr]=-1;
9697 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
9699 regs[i].regmap[hr]=-1;
9700 regs[i].isconst&=~(1<<hr);
9708 /* Pass 5 - Pre-allocate registers */
9710 // If a register is allocated during a loop, try to allocate it for the
9711 // entire loop, if possible. This avoids loading/storing registers
9712 // inside of the loop.
9714 signed char f_regmap[HOST_REGS];
9715 clear_all_regs(f_regmap);
9716 for(i=0;i<slen-1;i++)
9718 if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9720 if(ba[i]>=start && ba[i]<(start+i*4))
9721 if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
9722 ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
9723 ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
9724 ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
9725 ||itype[i+1]==FCOMP||itype[i+1]==FCONV
9726 ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
9728 int t=(ba[i]-start)>>2;
9729 if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots
9730 if(t<2||(itype[t-2]!=UJUMP)) // call/ret assumes no registers allocated
9731 for(hr=0;hr<HOST_REGS;hr++)
9733 if(regs[i].regmap[hr]>64) {
9734 if(!((regs[i].dirty>>hr)&1))
9735 f_regmap[hr]=regs[i].regmap[hr];
9736 else f_regmap[hr]=-1;
9738 else if(regs[i].regmap[hr]>=0) {
9739 if(f_regmap[hr]!=regs[i].regmap[hr]) {
9740 // dealloc old register
9742 for(n=0;n<HOST_REGS;n++)
9744 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
9746 // and alloc new one
9747 f_regmap[hr]=regs[i].regmap[hr];
9750 if(branch_regs[i].regmap[hr]>64) {
9751 if(!((branch_regs[i].dirty>>hr)&1))
9752 f_regmap[hr]=branch_regs[i].regmap[hr];
9753 else f_regmap[hr]=-1;
9755 else if(branch_regs[i].regmap[hr]>=0) {
9756 if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
9757 // dealloc old register
9759 for(n=0;n<HOST_REGS;n++)
9761 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
9763 // and alloc new one
9764 f_regmap[hr]=branch_regs[i].regmap[hr];
9767 if(itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
9768 ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
9769 ||itype[i+1]==FCOMP||itype[i+1]==FCONV
9770 ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
9772 // Test both in case the delay slot is ooo,
9773 // could be done better...
9774 if(count_free_regs(branch_regs[i].regmap)<2
9775 ||count_free_regs(regs[i].regmap)<2)
9776 f_regmap[hr]=branch_regs[i].regmap[hr];
9778 // Avoid dirty->clean transition
9779 // #ifdef DESTRUCTIVE_WRITEBACK here?
9780 if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
9781 if(f_regmap[hr]>0) {
9782 if(regs[t].regmap_entry[hr]<0) {
9786 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
9787 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
9788 if(r>63&&((unneeded_reg_upper[j]>>(r&63))&1)) break;
9790 // NB This can exclude the case where the upper-half
9791 // register is lower numbered than the lower-half
9792 // register. Not sure if it's worth fixing...
9793 if(get_reg(regs[j].regmap,r&63)<0) break;
9794 if(regs[j].is32&(1LL<<(r&63))) break;
9796 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
9797 //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
9799 if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
9800 if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
9802 if(get_reg(regs[i].regmap,r&63)<0) break;
9803 if(get_reg(branch_regs[i].regmap,r&63)<0) break;
9806 while(k>1&®s[k-1].regmap[hr]==-1) {
9807 if(itype[k-1]==STORE||itype[k-1]==STORELR
9808 ||itype[k-1]==C1LS||itype[k-1]==SHIFT||itype[k-1]==COP1
9809 ||itype[k-1]==FLOAT||itype[k-1]==FCONV||itype[k-1]==FCOMP
9810 ||itype[k-1]==COP2||itype[k-1]==C2LS||itype[k-1]==C2OP) {
9811 if(count_free_regs(regs[k-1].regmap)<2) {
9812 //printf("no free regs for store %x\n",start+(k-1)*4);
9817 if(itype[k-1]!=NOP&&itype[k-1]!=MOV&&itype[k-1]!=ALU&&itype[k-1]!=SHIFTIMM&&itype[k-1]!=IMM16&&itype[k-1]!=LOAD) break;
9818 if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
9819 //printf("no-match due to different register\n");
9822 if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP||itype[k-2]==FJUMP) {
9823 //printf("no-match due to branch\n");
9826 // call/ret fast path assumes no registers allocated
9827 if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)) {
9831 // NB This can exclude the case where the upper-half
9832 // register is lower numbered than the lower-half
9833 // register. Not sure if it's worth fixing...
9834 if(get_reg(regs[k-1].regmap,r&63)<0) break;
9835 if(regs[k-1].is32&(1LL<<(r&63))) break;
9840 if((regs[k].is32&(1LL<<f_regmap[hr]))!=
9841 (regs[i+2].was32&(1LL<<f_regmap[hr]))) {
9842 //printf("bad match after branch\n");
9846 if(regs[k-1].regmap[hr]==f_regmap[hr]&®map_pre[k][hr]==f_regmap[hr]) {
9847 //printf("Extend r%d, %x ->\n",hr,start+k*4);
9849 regs[k].regmap_entry[hr]=f_regmap[hr];
9850 regs[k].regmap[hr]=f_regmap[hr];
9851 regmap_pre[k+1][hr]=f_regmap[hr];
9852 regs[k].wasdirty&=~(1<<hr);
9853 regs[k].dirty&=~(1<<hr);
9854 regs[k].wasdirty|=(1<<hr)®s[k-1].dirty;
9855 regs[k].dirty|=(1<<hr)®s[k].wasdirty;
9856 regs[k].wasconst&=~(1<<hr);
9857 regs[k].isconst&=~(1<<hr);
9862 //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
9865 assert(regs[i-1].regmap[hr]==f_regmap[hr]);
9866 if(regs[i-1].regmap[hr]==f_regmap[hr]&®map_pre[i][hr]==f_regmap[hr]) {
9867 //printf("OK fill %x (r%d)\n",start+i*4,hr);
9868 regs[i].regmap_entry[hr]=f_regmap[hr];
9869 regs[i].regmap[hr]=f_regmap[hr];
9870 regs[i].wasdirty&=~(1<<hr);
9871 regs[i].dirty&=~(1<<hr);
9872 regs[i].wasdirty|=(1<<hr)®s[i-1].dirty;
9873 regs[i].dirty|=(1<<hr)®s[i-1].dirty;
9874 regs[i].wasconst&=~(1<<hr);
9875 regs[i].isconst&=~(1<<hr);
9876 branch_regs[i].regmap_entry[hr]=f_regmap[hr];
9877 branch_regs[i].wasdirty&=~(1<<hr);
9878 branch_regs[i].wasdirty|=(1<<hr)®s[i].dirty;
9879 branch_regs[i].regmap[hr]=f_regmap[hr];
9880 branch_regs[i].dirty&=~(1<<hr);
9881 branch_regs[i].dirty|=(1<<hr)®s[i].dirty;
9882 branch_regs[i].wasconst&=~(1<<hr);
9883 branch_regs[i].isconst&=~(1<<hr);
9884 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
9885 regmap_pre[i+2][hr]=f_regmap[hr];
9886 regs[i+2].wasdirty&=~(1<<hr);
9887 regs[i+2].wasdirty|=(1<<hr)®s[i].dirty;
9888 assert((branch_regs[i].is32&(1LL<<f_regmap[hr]))==
9889 (regs[i+2].was32&(1LL<<f_regmap[hr])));
9894 regs[k].regmap_entry[hr]=f_regmap[hr];
9895 regs[k].regmap[hr]=f_regmap[hr];
9896 regmap_pre[k+1][hr]=f_regmap[hr];
9897 regs[k+1].wasdirty&=~(1<<hr);
9898 regs[k].dirty&=~(1<<hr);
9899 regs[k].wasconst&=~(1<<hr);
9900 regs[k].isconst&=~(1<<hr);
9902 if(regs[j].regmap[hr]==f_regmap[hr])
9903 regs[j].regmap_entry[hr]=f_regmap[hr];
9907 if(regs[j].regmap[hr]>=0)
9909 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
9910 //printf("no-match due to different register\n");
9913 if((regs[j+1].is32&(1LL<<f_regmap[hr]))!=(regs[j].is32&(1LL<<f_regmap[hr]))) {
9914 //printf("32/64 mismatch %x %d\n",start+j*4,hr);
9917 if(itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS
9918 ||itype[j]==SHIFT||itype[j]==COP1||itype[j]==FLOAT
9919 ||itype[j]==FCOMP||itype[j]==FCONV
9920 ||itype[j]==COP2||itype[j]==C2LS||itype[j]==C2OP) {
9921 if(count_free_regs(regs[j].regmap)<2) {
9922 //printf("No free regs for store %x\n",start+j*4);
9926 else if(itype[j]!=NOP&&itype[j]!=MOV&&itype[j]!=ALU&&itype[j]!=SHIFTIMM&&itype[j]!=IMM16&&itype[j]!=LOAD) break;
9927 if(f_regmap[hr]>=64) {
9928 if(regs[j].is32&(1LL<<(f_regmap[hr]&63))) {
9933 if(get_reg(regs[j].regmap,f_regmap[hr]&63)<0) {
9945 for(hr=0;hr<HOST_REGS;hr++)
9947 if(hr!=EXCLUDE_REG) {
9948 if(regs[i].regmap[hr]>64) {
9949 if(!((regs[i].dirty>>hr)&1))
9950 f_regmap[hr]=regs[i].regmap[hr];
9952 else if(regs[i].regmap[hr]>=0) {
9953 if(f_regmap[hr]!=regs[i].regmap[hr]) {
9954 // dealloc old register
9956 for(n=0;n<HOST_REGS;n++)
9958 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
9960 // and alloc new one
9961 f_regmap[hr]=regs[i].regmap[hr];
9964 else if(regs[i].regmap[hr]<0) count++;
9967 // Try to restore cycle count at branch targets
9969 for(j=i;j<slen-1;j++) {
9970 if(regs[j].regmap[HOST_CCREG]!=-1) break;
9971 if(itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS
9972 ||itype[j]==SHIFT||itype[j]==COP1||itype[j]==FLOAT
9973 ||itype[j]==FCOMP||itype[j]==FCONV
9974 ||itype[j]==COP2||itype[j]==C2LS||itype[j]==C2OP) {
9975 if(count_free_regs(regs[j].regmap)<2) {
9976 //printf("no free regs for store %x\n",start+j*4);
9981 if(itype[j]!=NOP&&itype[j]!=MOV&&itype[j]!=ALU&&itype[j]!=SHIFTIMM&&itype[j]!=IMM16&&itype[j]!=LOAD) break;
9983 if(regs[j].regmap[HOST_CCREG]==CCREG) {
9985 //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
9987 regs[k].regmap_entry[HOST_CCREG]=CCREG;
9988 regs[k].regmap[HOST_CCREG]=CCREG;
9989 regmap_pre[k+1][HOST_CCREG]=CCREG;
9990 regs[k+1].wasdirty|=1<<HOST_CCREG;
9991 regs[k].dirty|=1<<HOST_CCREG;
9992 regs[k].wasconst&=~(1<<HOST_CCREG);
9993 regs[k].isconst&=~(1<<HOST_CCREG);
9996 regs[j].regmap_entry[HOST_CCREG]=CCREG;
9998 // Work backwards from the branch target
9999 if(j>i&&f_regmap[HOST_CCREG]==CCREG)
10001 //printf("Extend backwards\n");
10004 while(regs[k-1].regmap[HOST_CCREG]==-1) {
10005 if(itype[k-1]==STORE||itype[k-1]==STORELR||itype[k-1]==C1LS
10006 ||itype[k-1]==SHIFT||itype[k-1]==COP1||itype[k-1]==FLOAT
10007 ||itype[k-1]==FCONV||itype[k-1]==FCOMP
10008 ||itype[k-1]==COP2||itype[k-1]==C2LS||itype[k-1]==C2OP) {
10009 if(count_free_regs(regs[k-1].regmap)<2) {
10010 //printf("no free regs for store %x\n",start+(k-1)*4);
10015 if(itype[k-1]!=NOP&&itype[k-1]!=MOV&&itype[k-1]!=ALU&&itype[k-1]!=SHIFTIMM&&itype[k-1]!=IMM16&&itype[k-1]!=LOAD) break;
10018 if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
10019 //printf("Extend CC, %x ->\n",start+k*4);
10021 regs[k].regmap_entry[HOST_CCREG]=CCREG;
10022 regs[k].regmap[HOST_CCREG]=CCREG;
10023 regmap_pre[k+1][HOST_CCREG]=CCREG;
10024 regs[k+1].wasdirty|=1<<HOST_CCREG;
10025 regs[k].dirty|=1<<HOST_CCREG;
10026 regs[k].wasconst&=~(1<<HOST_CCREG);
10027 regs[k].isconst&=~(1<<HOST_CCREG);
10032 //printf("Fail Extend CC, %x ->\n",start+k*4);
10036 if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&&
10037 itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&&
10038 itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1&&itype[i]!=FLOAT&&
10039 itype[i]!=FCONV&&itype[i]!=FCOMP&&
10040 itype[i]!=COP2&&itype[i]!=C2LS&&itype[i]!=C2OP)
10042 memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
10047 // This allocates registers (if possible) one instruction prior
10048 // to use, which can avoid a load-use penalty on certain CPUs.
10049 for(i=0;i<slen-1;i++)
10051 if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP))
10055 if(itype[i]==ALU||itype[i]==MOV||itype[i]==LOAD||itype[i]==SHIFTIMM||itype[i]==IMM16
10056 ||((itype[i]==COP1||itype[i]==COP2)&&opcode2[i]<3))
10059 if((hr=get_reg(regs[i+1].regmap,rs1[i+1]))>=0)
10061 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10063 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10064 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10065 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10066 regs[i].isconst&=~(1<<hr);
10067 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10068 constmap[i][hr]=constmap[i+1][hr];
10069 regs[i+1].wasdirty&=~(1<<hr);
10070 regs[i].dirty&=~(1<<hr);
10075 if((hr=get_reg(regs[i+1].regmap,rs2[i+1]))>=0)
10077 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10079 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10080 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10081 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10082 regs[i].isconst&=~(1<<hr);
10083 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10084 constmap[i][hr]=constmap[i+1][hr];
10085 regs[i+1].wasdirty&=~(1<<hr);
10086 regs[i].dirty&=~(1<<hr);
10090 if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10091 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10093 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10095 regs[i].regmap[hr]=rs1[i+1];
10096 regmap_pre[i+1][hr]=rs1[i+1];
10097 regs[i+1].regmap_entry[hr]=rs1[i+1];
10098 regs[i].isconst&=~(1<<hr);
10099 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10100 constmap[i][hr]=constmap[i+1][hr];
10101 regs[i+1].wasdirty&=~(1<<hr);
10102 regs[i].dirty&=~(1<<hr);
10106 if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10107 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10109 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10111 regs[i].regmap[hr]=rs1[i+1];
10112 regmap_pre[i+1][hr]=rs1[i+1];
10113 regs[i+1].regmap_entry[hr]=rs1[i+1];
10114 regs[i].isconst&=~(1<<hr);
10115 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10116 constmap[i][hr]=constmap[i+1][hr];
10117 regs[i+1].wasdirty&=~(1<<hr);
10118 regs[i].dirty&=~(1<<hr);
10122 #ifndef HOST_IMM_ADDR32
10123 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
10124 hr=get_reg(regs[i+1].regmap,TLREG);
10126 int sr=get_reg(regs[i+1].regmap,rs1[i+1]);
10127 if(sr>=0&&((regs[i+1].wasconst>>sr)&1)) {
10129 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10131 regs[i].regmap[hr]=MGEN1+((i+1)&1);
10132 regmap_pre[i+1][hr]=MGEN1+((i+1)&1);
10133 regs[i+1].regmap_entry[hr]=MGEN1+((i+1)&1);
10134 regs[i].isconst&=~(1<<hr);
10135 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10136 constmap[i][hr]=constmap[i+1][hr];
10137 regs[i+1].wasdirty&=~(1<<hr);
10138 regs[i].dirty&=~(1<<hr);
10140 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10142 // move it to another register
10143 regs[i+1].regmap[hr]=-1;
10144 regmap_pre[i+2][hr]=-1;
10145 regs[i+1].regmap[nr]=TLREG;
10146 regmap_pre[i+2][nr]=TLREG;
10147 regs[i].regmap[nr]=MGEN1+((i+1)&1);
10148 regmap_pre[i+1][nr]=MGEN1+((i+1)&1);
10149 regs[i+1].regmap_entry[nr]=MGEN1+((i+1)&1);
10150 regs[i].isconst&=~(1<<nr);
10151 regs[i+1].isconst&=~(1<<nr);
10152 regs[i].dirty&=~(1<<nr);
10153 regs[i+1].wasdirty&=~(1<<nr);
10154 regs[i+1].dirty&=~(1<<nr);
10155 regs[i+2].wasdirty&=~(1<<nr);
10161 if(itype[i+1]==STORE||itype[i+1]==STORELR
10162 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
10163 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10164 hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
10165 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10166 else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
10168 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10170 regs[i].regmap[hr]=rs1[i+1];
10171 regmap_pre[i+1][hr]=rs1[i+1];
10172 regs[i+1].regmap_entry[hr]=rs1[i+1];
10173 regs[i].isconst&=~(1<<hr);
10174 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10175 constmap[i][hr]=constmap[i+1][hr];
10176 regs[i+1].wasdirty&=~(1<<hr);
10177 regs[i].dirty&=~(1<<hr);
10181 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
10182 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10184 hr=get_reg(regs[i+1].regmap,FTEMP);
10186 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10188 regs[i].regmap[hr]=rs1[i+1];
10189 regmap_pre[i+1][hr]=rs1[i+1];
10190 regs[i+1].regmap_entry[hr]=rs1[i+1];
10191 regs[i].isconst&=~(1<<hr);
10192 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10193 constmap[i][hr]=constmap[i+1][hr];
10194 regs[i+1].wasdirty&=~(1<<hr);
10195 regs[i].dirty&=~(1<<hr);
10197 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10199 // move it to another register
10200 regs[i+1].regmap[hr]=-1;
10201 regmap_pre[i+2][hr]=-1;
10202 regs[i+1].regmap[nr]=FTEMP;
10203 regmap_pre[i+2][nr]=FTEMP;
10204 regs[i].regmap[nr]=rs1[i+1];
10205 regmap_pre[i+1][nr]=rs1[i+1];
10206 regs[i+1].regmap_entry[nr]=rs1[i+1];
10207 regs[i].isconst&=~(1<<nr);
10208 regs[i+1].isconst&=~(1<<nr);
10209 regs[i].dirty&=~(1<<nr);
10210 regs[i+1].wasdirty&=~(1<<nr);
10211 regs[i+1].dirty&=~(1<<nr);
10212 regs[i+2].wasdirty&=~(1<<nr);
10216 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS||||itype[i+1]==C2LS*/) {
10217 if(itype[i+1]==LOAD)
10218 hr=get_reg(regs[i+1].regmap,rt1[i+1]);
10219 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
10220 hr=get_reg(regs[i+1].regmap,FTEMP);
10221 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
10222 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
10223 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10225 if(hr>=0&®s[i].regmap[hr]<0) {
10226 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
10227 if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
10228 regs[i].regmap[hr]=AGEN1+((i+1)&1);
10229 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
10230 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
10231 regs[i].isconst&=~(1<<hr);
10232 regs[i+1].wasdirty&=~(1<<hr);
10233 regs[i].dirty&=~(1<<hr);
10242 /* Pass 6 - Optimize clean/dirty state */
10243 clean_registers(0,slen-1,1);
10245 /* Pass 7 - Identify 32-bit registers */
10251 for (i=slen-1;i>=0;i--)
10254 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10256 if(ba[i]<start || ba[i]>=(start+slen*4))
10258 // Branch out of this block, don't need anything
10264 // Need whatever matches the target
10265 // (and doesn't get overwritten by the delay slot instruction)
10267 int t=(ba[i]-start)>>2;
10268 if(ba[i]>start+i*4) {
10270 if(!(requires_32bit[t]&~regs[i].was32))
10271 r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10274 //if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
10275 // r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10276 if(!(pr32[t]&~regs[i].was32))
10277 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10280 // Conditional branch may need registers for following instructions
10281 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10284 r32|=requires_32bit[i+2];
10285 r32&=regs[i].was32;
10286 // Mark this address as a branch target since it may be called
10287 // upon return from interrupt
10291 // Merge in delay slot
10293 // These are overwritten unless the branch is "likely"
10294 // and the delay slot is nullified if not taken
10295 r32&=~(1LL<<rt1[i+1]);
10296 r32&=~(1LL<<rt2[i+1]);
10298 // Assume these are needed (delay slot)
10301 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
10305 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
10307 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
10309 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
10311 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
10313 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
10316 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
10318 // SYSCALL instruction (software interrupt)
10321 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
10323 // ERET instruction (return from interrupt)
10327 r32&=~(1LL<<rt1[i]);
10328 r32&=~(1LL<<rt2[i]);
10331 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
10335 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
10337 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
10339 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
10341 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
10343 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
10345 requires_32bit[i]=r32;
10347 // Dirty registers which are 32-bit, require 32-bit input
10348 // as they will be written as 32-bit values
10349 for(hr=0;hr<HOST_REGS;hr++)
10351 if(regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64) {
10352 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
10353 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
10354 requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
10358 //requires_32bit[i]=is32[i]&~unneeded_reg_upper[i]; // DEBUG
10361 if(itype[slen-1]==SPAN) {
10362 bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
10365 /* Debug/disassembly */
10366 if((void*)assem_debug==(void*)printf)
10367 for(i=0;i<slen;i++)
10371 for(r=1;r<=CCREG;r++) {
10372 if((unneeded_reg[i]>>r)&1) {
10373 if(r==HIREG) printf(" HI");
10374 else if(r==LOREG) printf(" LO");
10375 else printf(" r%d",r);
10380 for(r=1;r<=CCREG;r++) {
10381 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
10382 if(r==HIREG) printf(" HI");
10383 else if(r==LOREG) printf(" LO");
10384 else printf(" r%d",r);
10388 for(r=0;r<=CCREG;r++) {
10389 //if(((is32[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10390 if((regs[i].was32>>r)&1) {
10391 if(r==CCREG) printf(" CC");
10392 else if(r==HIREG) printf(" HI");
10393 else if(r==LOREG) printf(" LO");
10394 else printf(" r%d",r);
10399 #if defined(__i386__) || defined(__x86_64__)
10400 printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
10403 printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
10406 if(needed_reg[i]&1) printf("eax ");
10407 if((needed_reg[i]>>1)&1) printf("ecx ");
10408 if((needed_reg[i]>>2)&1) printf("edx ");
10409 if((needed_reg[i]>>3)&1) printf("ebx ");
10410 if((needed_reg[i]>>5)&1) printf("ebp ");
10411 if((needed_reg[i]>>6)&1) printf("esi ");
10412 if((needed_reg[i]>>7)&1) printf("edi ");
10414 for(r=0;r<=CCREG;r++) {
10415 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10416 if((requires_32bit[i]>>r)&1) {
10417 if(r==CCREG) printf(" CC");
10418 else if(r==HIREG) printf(" HI");
10419 else if(r==LOREG) printf(" LO");
10420 else printf(" r%d",r);
10425 for(r=0;r<=CCREG;r++) {
10426 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10427 if((pr32[i]>>r)&1) {
10428 if(r==CCREG) printf(" CC");
10429 else if(r==HIREG) printf(" HI");
10430 else if(r==LOREG) printf(" LO");
10431 else printf(" r%d",r);
10434 if(pr32[i]!=requires_32bit[i]) printf(" OOPS");
10436 #if defined(__i386__) || defined(__x86_64__)
10437 printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
10439 if(regs[i].wasdirty&1) printf("eax ");
10440 if((regs[i].wasdirty>>1)&1) printf("ecx ");
10441 if((regs[i].wasdirty>>2)&1) printf("edx ");
10442 if((regs[i].wasdirty>>3)&1) printf("ebx ");
10443 if((regs[i].wasdirty>>5)&1) printf("ebp ");
10444 if((regs[i].wasdirty>>6)&1) printf("esi ");
10445 if((regs[i].wasdirty>>7)&1) printf("edi ");
10448 printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
10450 if(regs[i].wasdirty&1) printf("r0 ");
10451 if((regs[i].wasdirty>>1)&1) printf("r1 ");
10452 if((regs[i].wasdirty>>2)&1) printf("r2 ");
10453 if((regs[i].wasdirty>>3)&1) printf("r3 ");
10454 if((regs[i].wasdirty>>4)&1) printf("r4 ");
10455 if((regs[i].wasdirty>>5)&1) printf("r5 ");
10456 if((regs[i].wasdirty>>6)&1) printf("r6 ");
10457 if((regs[i].wasdirty>>7)&1) printf("r7 ");
10458 if((regs[i].wasdirty>>8)&1) printf("r8 ");
10459 if((regs[i].wasdirty>>9)&1) printf("r9 ");
10460 if((regs[i].wasdirty>>10)&1) printf("r10 ");
10461 if((regs[i].wasdirty>>12)&1) printf("r12 ");
10464 disassemble_inst(i);
10465 //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
10466 #if defined(__i386__) || defined(__x86_64__)
10467 printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
10468 if(regs[i].dirty&1) printf("eax ");
10469 if((regs[i].dirty>>1)&1) printf("ecx ");
10470 if((regs[i].dirty>>2)&1) printf("edx ");
10471 if((regs[i].dirty>>3)&1) printf("ebx ");
10472 if((regs[i].dirty>>5)&1) printf("ebp ");
10473 if((regs[i].dirty>>6)&1) printf("esi ");
10474 if((regs[i].dirty>>7)&1) printf("edi ");
10477 printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
10478 if(regs[i].dirty&1) printf("r0 ");
10479 if((regs[i].dirty>>1)&1) printf("r1 ");
10480 if((regs[i].dirty>>2)&1) printf("r2 ");
10481 if((regs[i].dirty>>3)&1) printf("r3 ");
10482 if((regs[i].dirty>>4)&1) printf("r4 ");
10483 if((regs[i].dirty>>5)&1) printf("r5 ");
10484 if((regs[i].dirty>>6)&1) printf("r6 ");
10485 if((regs[i].dirty>>7)&1) printf("r7 ");
10486 if((regs[i].dirty>>8)&1) printf("r8 ");
10487 if((regs[i].dirty>>9)&1) printf("r9 ");
10488 if((regs[i].dirty>>10)&1) printf("r10 ");
10489 if((regs[i].dirty>>12)&1) printf("r12 ");
10492 if(regs[i].isconst) {
10493 printf("constants: ");
10494 #if defined(__i386__) || defined(__x86_64__)
10495 if(regs[i].isconst&1) printf("eax=%x ",(int)constmap[i][0]);
10496 if((regs[i].isconst>>1)&1) printf("ecx=%x ",(int)constmap[i][1]);
10497 if((regs[i].isconst>>2)&1) printf("edx=%x ",(int)constmap[i][2]);
10498 if((regs[i].isconst>>3)&1) printf("ebx=%x ",(int)constmap[i][3]);
10499 if((regs[i].isconst>>5)&1) printf("ebp=%x ",(int)constmap[i][5]);
10500 if((regs[i].isconst>>6)&1) printf("esi=%x ",(int)constmap[i][6]);
10501 if((regs[i].isconst>>7)&1) printf("edi=%x ",(int)constmap[i][7]);
10504 if(regs[i].isconst&1) printf("r0=%x ",(int)constmap[i][0]);
10505 if((regs[i].isconst>>1)&1) printf("r1=%x ",(int)constmap[i][1]);
10506 if((regs[i].isconst>>2)&1) printf("r2=%x ",(int)constmap[i][2]);
10507 if((regs[i].isconst>>3)&1) printf("r3=%x ",(int)constmap[i][3]);
10508 if((regs[i].isconst>>4)&1) printf("r4=%x ",(int)constmap[i][4]);
10509 if((regs[i].isconst>>5)&1) printf("r5=%x ",(int)constmap[i][5]);
10510 if((regs[i].isconst>>6)&1) printf("r6=%x ",(int)constmap[i][6]);
10511 if((regs[i].isconst>>7)&1) printf("r7=%x ",(int)constmap[i][7]);
10512 if((regs[i].isconst>>8)&1) printf("r8=%x ",(int)constmap[i][8]);
10513 if((regs[i].isconst>>9)&1) printf("r9=%x ",(int)constmap[i][9]);
10514 if((regs[i].isconst>>10)&1) printf("r10=%x ",(int)constmap[i][10]);
10515 if((regs[i].isconst>>12)&1) printf("r12=%x ",(int)constmap[i][12]);
10521 for(r=0;r<=CCREG;r++) {
10522 if((regs[i].is32>>r)&1) {
10523 if(r==CCREG) printf(" CC");
10524 else if(r==HIREG) printf(" HI");
10525 else if(r==LOREG) printf(" LO");
10526 else printf(" r%d",r);
10532 for(r=0;r<=CCREG;r++) {
10533 if((p32[i]>>r)&1) {
10534 if(r==CCREG) printf(" CC");
10535 else if(r==HIREG) printf(" HI");
10536 else if(r==LOREG) printf(" LO");
10537 else printf(" r%d",r);
10540 if(p32[i]!=regs[i].is32) printf(" NO MATCH\n");
10541 else printf("\n");*/
10542 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10543 #if defined(__i386__) || defined(__x86_64__)
10544 printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
10545 if(branch_regs[i].dirty&1) printf("eax ");
10546 if((branch_regs[i].dirty>>1)&1) printf("ecx ");
10547 if((branch_regs[i].dirty>>2)&1) printf("edx ");
10548 if((branch_regs[i].dirty>>3)&1) printf("ebx ");
10549 if((branch_regs[i].dirty>>5)&1) printf("ebp ");
10550 if((branch_regs[i].dirty>>6)&1) printf("esi ");
10551 if((branch_regs[i].dirty>>7)&1) printf("edi ");
10554 printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
10555 if(branch_regs[i].dirty&1) printf("r0 ");
10556 if((branch_regs[i].dirty>>1)&1) printf("r1 ");
10557 if((branch_regs[i].dirty>>2)&1) printf("r2 ");
10558 if((branch_regs[i].dirty>>3)&1) printf("r3 ");
10559 if((branch_regs[i].dirty>>4)&1) printf("r4 ");
10560 if((branch_regs[i].dirty>>5)&1) printf("r5 ");
10561 if((branch_regs[i].dirty>>6)&1) printf("r6 ");
10562 if((branch_regs[i].dirty>>7)&1) printf("r7 ");
10563 if((branch_regs[i].dirty>>8)&1) printf("r8 ");
10564 if((branch_regs[i].dirty>>9)&1) printf("r9 ");
10565 if((branch_regs[i].dirty>>10)&1) printf("r10 ");
10566 if((branch_regs[i].dirty>>12)&1) printf("r12 ");
10570 for(r=0;r<=CCREG;r++) {
10571 if((branch_regs[i].is32>>r)&1) {
10572 if(r==CCREG) printf(" CC");
10573 else if(r==HIREG) printf(" HI");
10574 else if(r==LOREG) printf(" LO");
10575 else printf(" r%d",r);
10583 /* Pass 8 - Assembly */
10584 linkcount=0;stubcount=0;
10585 ds=0;is_delayslot=0;
10587 uint64_t is32_pre=0;
10589 u_int beginning=(u_int)out;
10590 if((u_int)addr&1) {
10594 u_int instr_addr0_override=0;
10597 if (start == 0x80030000) {
10598 // nasty hack for fastbios thing
10599 instr_addr0_override=(u_int)out;
10600 emit_movimm(start,0);
10601 emit_readword((int)&pcaddr,1);
10602 emit_writeword(0,(int)&pcaddr);
10604 emit_jne((int)new_dyna_leave);
10607 for(i=0;i<slen;i++)
10609 //if(ds) printf("ds: ");
10610 if((void*)assem_debug==(void*)printf) disassemble_inst(i);
10612 ds=0; // Skip delay slot
10613 if(bt[i]) assem_debug("OOPS - branch into delay slot\n");
10616 #ifndef DESTRUCTIVE_WRITEBACK
10617 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
10619 wb_sx(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,is32_pre,regs[i].was32,
10620 unneeded_reg[i],unneeded_reg_upper[i]);
10621 wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre,
10622 unneeded_reg[i],unneeded_reg_upper[i]);
10624 is32_pre=regs[i].is32;
10625 dirty_pre=regs[i].dirty;
10628 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
10630 wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32,
10631 unneeded_reg[i],unneeded_reg_upper[i]);
10632 loop_preload(regmap_pre[i],regs[i].regmap_entry);
10634 // branch target entry point
10635 instr_addr[i]=(u_int)out;
10636 assem_debug("<->\n");
10638 if(regs[i].regmap_entry[HOST_CCREG]==CCREG&®s[i].regmap[HOST_CCREG]!=CCREG)
10639 wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32);
10640 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
10641 address_generation(i,®s[i],regs[i].regmap_entry);
10642 load_consts(regmap_pre[i],regs[i].regmap,regs[i].was32,i);
10643 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10645 // Load the delay slot registers if necessary
10646 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
10647 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
10648 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
10649 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
10650 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a)
10651 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
10655 // Preload registers for following instruction
10656 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
10657 if(rs1[i+1]!=rt1[i]&&rs1[i+1]!=rt2[i])
10658 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
10659 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
10660 if(rs2[i+1]!=rt1[i]&&rs2[i+1]!=rt2[i])
10661 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
10663 // TODO: if(is_ooo(i)) address_generation(i+1);
10664 if(itype[i]==CJUMP||itype[i]==FJUMP)
10665 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
10666 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a)
10667 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
10668 if(bt[i]) cop1_usable=0;
10672 alu_assemble(i,®s[i]);break;
10674 imm16_assemble(i,®s[i]);break;
10676 shift_assemble(i,®s[i]);break;
10678 shiftimm_assemble(i,®s[i]);break;
10680 load_assemble(i,®s[i]);break;
10682 loadlr_assemble(i,®s[i]);break;
10684 store_assemble(i,®s[i]);break;
10686 storelr_assemble(i,®s[i]);break;
10688 cop0_assemble(i,®s[i]);break;
10690 cop1_assemble(i,®s[i]);break;
10692 c1ls_assemble(i,®s[i]);break;
10694 cop2_assemble(i,®s[i]);break;
10696 c2ls_assemble(i,®s[i]);break;
10698 c2op_assemble(i,®s[i]);break;
10700 fconv_assemble(i,®s[i]);break;
10702 float_assemble(i,®s[i]);break;
10704 fcomp_assemble(i,®s[i]);break;
10706 multdiv_assemble(i,®s[i]);break;
10708 mov_assemble(i,®s[i]);break;
10710 syscall_assemble(i,®s[i]);break;
10712 hlecall_assemble(i,®s[i]);break;
10714 intcall_assemble(i,®s[i]);break;
10716 ujump_assemble(i,®s[i]);ds=1;break;
10718 rjump_assemble(i,®s[i]);ds=1;break;
10720 cjump_assemble(i,®s[i]);ds=1;break;
10722 sjump_assemble(i,®s[i]);ds=1;break;
10724 fjump_assemble(i,®s[i]);ds=1;break;
10726 pagespan_assemble(i,®s[i]);break;
10728 if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
10729 literal_pool(1024);
10731 literal_pool_jumpover(256);
10734 //assert(itype[i-2]==UJUMP||itype[i-2]==RJUMP||(source[i-2]>>16)==0x1000);
10735 // If the block did not end with an unconditional branch,
10736 // add a jump to the next instruction.
10738 if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) {
10739 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
10741 if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP&&itype[i-2]!=FJUMP) {
10742 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
10743 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
10744 emit_loadreg(CCREG,HOST_CCREG);
10745 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
10747 else if(!likely[i-2])
10749 store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].is32,branch_regs[i-2].dirty,start+i*4);
10750 assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
10754 store_regs_bt(regs[i-2].regmap,regs[i-2].is32,regs[i-2].dirty,start+i*4);
10755 assert(regs[i-2].regmap[HOST_CCREG]==CCREG);
10757 add_to_linker((int)out,start+i*4,0);
10764 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
10765 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
10766 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
10767 emit_loadreg(CCREG,HOST_CCREG);
10768 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
10769 add_to_linker((int)out,start+i*4,0);
10773 // TODO: delay slot stubs?
10775 for(i=0;i<stubcount;i++)
10777 switch(stubs[i][0])
10785 do_readstub(i);break;
10790 do_writestub(i);break;
10792 do_ccstub(i);break;
10794 do_invstub(i);break;
10796 do_cop1stub(i);break;
10798 do_unalignedwritestub(i);break;
10802 if (instr_addr0_override)
10803 instr_addr[0] = instr_addr0_override;
10805 /* Pass 9 - Linker */
10806 for(i=0;i<linkcount;i++)
10808 assem_debug("%8x -> %8x\n",link_addr[i][0],link_addr[i][1]);
10810 if(!link_addr[i][2])
10813 void *addr=check_addr(link_addr[i][1]);
10814 emit_extjump(link_addr[i][0],link_addr[i][1]);
10816 set_jump_target(link_addr[i][0],(int)addr);
10817 add_link(link_addr[i][1],stub);
10819 else set_jump_target(link_addr[i][0],(int)stub);
10824 int target=(link_addr[i][1]-start)>>2;
10825 assert(target>=0&&target<slen);
10826 assert(instr_addr[target]);
10827 //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
10828 //set_jump_target_fillslot(link_addr[i][0],instr_addr[target],link_addr[i][2]>>1);
10830 set_jump_target(link_addr[i][0],instr_addr[target]);
10834 // External Branch Targets (jump_in)
10835 if(copy+slen*4>(void *)shadow+sizeof(shadow)) copy=shadow;
10836 for(i=0;i<slen;i++)
10840 if(instr_addr[i]) // TODO - delay slots (=null)
10842 u_int vaddr=start+i*4;
10843 u_int page=get_page(vaddr);
10844 u_int vpage=get_vpage(vaddr);
10846 //if(!(is32[i]&(~unneeded_reg_upper[i])&~(1LL<<CCREG)))
10847 if(!requires_32bit[i])
10849 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
10850 assem_debug("jump_in: %x\n",start+i*4);
10851 ll_add(jump_dirty+vpage,vaddr,(void *)out);
10852 int entry_point=do_dirty_stub(i);
10853 ll_add(jump_in+page,vaddr,(void *)entry_point);
10854 // If there was an existing entry in the hash table,
10855 // replace it with the new address.
10856 // Don't add new entries. We'll insert the
10857 // ones that actually get used in check_addr().
10858 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
10859 if(ht_bin[0]==vaddr) {
10860 ht_bin[1]=entry_point;
10862 if(ht_bin[2]==vaddr) {
10863 ht_bin[3]=entry_point;
10868 u_int r=requires_32bit[i]|!!(requires_32bit[i]>>32);
10869 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
10870 assem_debug("jump_in: %x (restricted - %x)\n",start+i*4,r);
10871 //int entry_point=(int)out;
10872 ////assem_debug("entry_point: %x\n",entry_point);
10873 //load_regs_entry(i);
10874 //if(entry_point==(int)out)
10875 // entry_point=instr_addr[i];
10877 // emit_jmp(instr_addr[i]);
10878 //ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
10879 ll_add_32(jump_dirty+vpage,vaddr,r,(void *)out);
10880 int entry_point=do_dirty_stub(i);
10881 ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
10886 // Write out the literal pool if necessary
10888 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
10890 if(((u_int)out)&7) emit_addnop(13);
10892 assert((u_int)out-beginning<MAX_OUTPUT_BLOCK_SIZE);
10893 //printf("shadow buffer: %x-%x\n",(int)copy,(int)copy+slen*4);
10894 memcpy(copy,source,slen*4);
10898 __clear_cache((void *)beginning,out);
10901 // If we're within 256K of the end of the buffer,
10902 // start over from the beginning. (Is 256K enough?)
10903 if((int)out>BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR;
10905 // Trap writes to any of the pages we compiled
10906 for(i=start>>12;i<=(start+slen*4)>>12;i++) {
10908 #ifndef DISABLE_TLB
10909 memory_map[i]|=0x40000000;
10910 if((signed int)start>=(signed int)0xC0000000) {
10912 j=(((u_int)i<<12)+(memory_map[i]<<2)-(u_int)rdram+(u_int)0x80000000)>>12;
10914 memory_map[j]|=0x40000000;
10915 //printf("write protect physical page: %x (virtual %x)\n",j<<12,start);
10920 /* Pass 10 - Free memory by expiring oldest blocks */
10922 int end=((((int)out-BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535;
10923 while(expirep!=end)
10925 int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
10926 int base=BASE_ADDR+((expirep>>13)<<shift); // Base address of this block
10927 inv_debug("EXP: Phase %d\n",expirep);
10928 switch((expirep>>11)&3)
10931 // Clear jump_in and jump_dirty
10932 ll_remove_matching_addrs(jump_in+(expirep&2047),base,shift);
10933 ll_remove_matching_addrs(jump_dirty+(expirep&2047),base,shift);
10934 ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base,shift);
10935 ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base,shift);
10939 ll_kill_pointers(jump_out[expirep&2047],base,shift);
10940 ll_kill_pointers(jump_out[(expirep&2047)+2048],base,shift);
10943 // Clear hash table
10944 for(i=0;i<32;i++) {
10945 int *ht_bin=hash_table[((expirep&2047)<<5)+i];
10946 if((ht_bin[3]>>shift)==(base>>shift) ||
10947 ((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
10948 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[2],ht_bin[3]);
10949 ht_bin[2]=ht_bin[3]=-1;
10951 if((ht_bin[1]>>shift)==(base>>shift) ||
10952 ((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
10953 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[0],ht_bin[1]);
10954 ht_bin[0]=ht_bin[2];
10955 ht_bin[1]=ht_bin[3];
10956 ht_bin[2]=ht_bin[3]=-1;
10962 ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);
10963 ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base,shift);
10966 expirep=(expirep+1)&65535;
10971 // vim:shiftwidth=2:expandtab