1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
3 * Copyright (C) 2009-2011 Ari64 *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
22 #include <stdint.h> //include for uint64_t
25 #include "emu_if.h" //emulator interface
30 #include "assem_x86.h"
33 #include "assem_x64.h"
36 #include "assem_arm.h"
40 #define MAX_OUTPUT_BLOCK_SIZE 262144
41 #define CLOCK_DIVIDER 2
45 signed char regmap_entry[HOST_REGS];
46 signed char regmap[HOST_REGS];
55 uint64_t constmap[HOST_REGS];
63 struct ll_entry *next;
69 char insn[MAXBLOCK][10];
70 u_char itype[MAXBLOCK];
71 u_char opcode[MAXBLOCK];
72 u_char opcode2[MAXBLOCK];
80 u_char dep1[MAXBLOCK];
81 u_char dep2[MAXBLOCK];
83 static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
84 static uint64_t gte_rt[MAXBLOCK];
85 static uint64_t gte_unneeded[MAXBLOCK];
86 static int gte_reads_flags; // gte flag read encountered
89 char likely[MAXBLOCK];
92 uint64_t unneeded_reg[MAXBLOCK];
93 uint64_t unneeded_reg_upper[MAXBLOCK];
94 uint64_t branch_unneeded_reg[MAXBLOCK];
95 uint64_t branch_unneeded_reg_upper[MAXBLOCK];
96 uint64_t p32[MAXBLOCK];
97 uint64_t pr32[MAXBLOCK];
98 signed char regmap_pre[MAXBLOCK][HOST_REGS];
99 signed char regmap[MAXBLOCK][HOST_REGS];
100 signed char regmap_entry[MAXBLOCK][HOST_REGS];
101 uint64_t constmap[MAXBLOCK][HOST_REGS];
102 struct regstat regs[MAXBLOCK];
103 struct regstat branch_regs[MAXBLOCK];
104 signed char minimum_free_regs[MAXBLOCK];
105 u_int needed_reg[MAXBLOCK];
106 uint64_t requires_32bit[MAXBLOCK];
107 u_int wont_dirty[MAXBLOCK];
108 u_int will_dirty[MAXBLOCK];
111 u_int instr_addr[MAXBLOCK];
112 u_int link_addr[MAXBLOCK][3];
114 u_int stubs[MAXBLOCK*3][8];
116 u_int literals[1024][2];
121 struct ll_entry *jump_in[4096];
122 struct ll_entry *jump_out[4096];
123 struct ll_entry *jump_dirty[4096];
124 u_int hash_table[65536][4] __attribute__((aligned(16)));
125 char shadow[1048576] __attribute__((aligned(16)));
131 static const u_int using_tlb=0;
133 static u_int sp_in_mirror;
134 u_int stop_after_jal;
135 extern u_char restore_candidate[512];
136 extern int cycle_count;
138 /* registers that may be allocated */
140 #define HIREG 32 // hi
141 #define LOREG 33 // lo
142 #define FSREG 34 // FPU status (FCSR)
143 #define CSREG 35 // Coprocessor status
144 #define CCREG 36 // Cycle count
145 #define INVCP 37 // Pointer to invalid_code
146 #define MMREG 38 // Pointer to memory_map
147 #define ROREG 39 // ram offset (if rdram!=0x80000000)
149 #define FTEMP 40 // FPU temporary register
150 #define PTEMP 41 // Prefetch temporary register
151 #define TLREG 42 // TLB mapping offset
152 #define RHASH 43 // Return address hash
153 #define RHTBL 44 // Return address hash table address
154 #define RTEMP 45 // JR/JALR address register
156 #define AGEN1 46 // Address generation temporary register
157 #define AGEN2 47 // Address generation temporary register
158 #define MGEN1 48 // Maptable address generation temporary register
159 #define MGEN2 49 // Maptable address generation temporary register
160 #define BTREG 50 // Branch target temporary register
162 /* instruction types */
163 #define NOP 0 // No operation
164 #define LOAD 1 // Load
165 #define STORE 2 // Store
166 #define LOADLR 3 // Unaligned load
167 #define STORELR 4 // Unaligned store
168 #define MOV 5 // Move
169 #define ALU 6 // Arithmetic/logic
170 #define MULTDIV 7 // Multiply/divide
171 #define SHIFT 8 // Shift by register
172 #define SHIFTIMM 9// Shift by immediate
173 #define IMM16 10 // 16-bit immediate
174 #define RJUMP 11 // Unconditional jump to register
175 #define UJUMP 12 // Unconditional jump
176 #define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
177 #define SJUMP 14 // Conditional branch (regimm format)
178 #define COP0 15 // Coprocessor 0
179 #define COP1 16 // Coprocessor 1
180 #define C1LS 17 // Coprocessor 1 load/store
181 #define FJUMP 18 // Conditional branch (floating point)
182 #define FLOAT 19 // Floating point unit
183 #define FCONV 20 // Convert integer to float
184 #define FCOMP 21 // Floating point compare (sets FSREG)
185 #define SYSCALL 22// SYSCALL
186 #define OTHER 23 // Other
187 #define SPAN 24 // Branch/delay slot spans 2 pages
188 #define NI 25 // Not implemented
189 #define HLECALL 26// PCSX fake opcodes for HLE
190 #define COP2 27 // Coprocessor 2 move
191 #define C2LS 28 // Coprocessor 2 load/store
192 #define C2OP 29 // Coprocessor 2 operation
193 #define INTCALL 30// Call interpreter to handle rare corner cases
202 #define LOADBU_STUB 7
203 #define LOADHU_STUB 8
204 #define STOREB_STUB 9
205 #define STOREH_STUB 10
206 #define STOREW_STUB 11
207 #define STORED_STUB 12
208 #define STORELR_STUB 13
209 #define INVCODE_STUB 14
217 int new_recompile_block(int addr);
218 void *get_addr_ht(u_int vaddr);
219 void invalidate_block(u_int block);
220 void invalidate_addr(u_int addr);
221 void remove_hash(int vaddr);
224 void dyna_linker_ds();
226 void verify_code_vm();
227 void verify_code_ds();
230 void fp_exception_ds();
232 void jump_syscall_hle();
236 void new_dyna_leave();
241 void read_nomem_new();
242 void read_nomemb_new();
243 void read_nomemh_new();
244 void read_nomemd_new();
245 void write_nomem_new();
246 void write_nomemb_new();
247 void write_nomemh_new();
248 void write_nomemd_new();
249 void write_rdram_new();
250 void write_rdramb_new();
251 void write_rdramh_new();
252 void write_rdramd_new();
253 extern u_int memory_map[1048576];
255 // Needed by assembler
256 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
257 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
258 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
259 void load_all_regs(signed char i_regmap[]);
260 void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
261 void load_regs_entry(int t);
262 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
266 //#define DEBUG_CYCLE_COUNT 1
269 //#define assem_debug printf
270 //#define inv_debug printf
271 #define assem_debug nullf
272 #define inv_debug nullf
274 static void tlb_hacks()
278 if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
282 switch (ROM_HEADER->Country_code&0xFF)
294 // Unknown country code
298 u_int rom_addr=(u_int)rom;
300 // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
301 // in the lower 4G of memory to use this hack. Copy it if necessary.
302 if((void *)rom>(void *)0xffffffff) {
303 munmap(ROM_COPY, 67108864);
304 if(mmap(ROM_COPY, 12582912,
305 PROT_READ | PROT_WRITE,
306 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
307 -1, 0) <= 0) {printf("mmap() failed\n");}
308 memcpy(ROM_COPY,rom,12582912);
309 rom_addr=(u_int)ROM_COPY;
313 for(n=0x7F000;n<0x80000;n++) {
314 memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
321 static u_int get_page(u_int vaddr)
324 u_int page=(vaddr^0x80000000)>>12;
326 u_int page=vaddr&~0xe0000000;
327 if (page < 0x1000000)
328 page &= ~0x0e00000; // RAM mirrors
332 if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
334 if(page>2048) page=2048+(page&2047);
338 static u_int get_vpage(u_int vaddr)
340 u_int vpage=(vaddr^0x80000000)>>12;
342 if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
344 if(vpage>2048) vpage=2048+(vpage&2047);
348 // Get address from virtual address
349 // This is called from the recompiled JR/JALR instructions
350 void *get_addr(u_int vaddr)
352 u_int page=get_page(vaddr);
353 u_int vpage=get_vpage(vaddr);
354 struct ll_entry *head;
355 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
358 if(head->vaddr==vaddr&&head->reg32==0) {
359 //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
360 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
363 ht_bin[1]=(int)head->addr;
369 head=jump_dirty[vpage];
371 if(head->vaddr==vaddr&&head->reg32==0) {
372 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
373 // Don't restore blocks which are about to expire from the cache
374 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
375 if(verify_dirty(head->addr)) {
376 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
377 invalid_code[vaddr>>12]=0;
378 inv_code_start=inv_code_end=~0;
379 memory_map[vaddr>>12]|=0x40000000;
382 if(tlb_LUT_r[vaddr>>12]) {
383 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
384 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
387 restore_candidate[vpage>>3]|=1<<(vpage&7);
389 else restore_candidate[page>>3]|=1<<(page&7);
390 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
391 if(ht_bin[0]==vaddr) {
392 ht_bin[1]=(int)head->addr; // Replace existing entry
398 ht_bin[1]=(int)head->addr;
406 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
407 int r=new_recompile_block(vaddr);
408 if(r==0) return get_addr(vaddr);
409 // Execute in unmapped page, generate pagefault execption
411 Cause=(vaddr<<31)|0x8;
412 EPC=(vaddr&1)?vaddr-5:vaddr;
414 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
415 EntryHi=BadVAddr&0xFFFFE000;
416 return get_addr_ht(0x80000000);
418 // Look up address in hash table first
419 void *get_addr_ht(u_int vaddr)
421 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
422 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
423 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
424 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
425 return get_addr(vaddr);
428 void *get_addr_32(u_int vaddr,u_int flags)
431 return get_addr(vaddr);
433 //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
434 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
435 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
436 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
437 u_int page=get_page(vaddr);
438 u_int vpage=get_vpage(vaddr);
439 struct ll_entry *head;
442 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
443 //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
445 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
447 ht_bin[1]=(int)head->addr;
449 }else if(ht_bin[2]==-1) {
450 ht_bin[3]=(int)head->addr;
453 //ht_bin[3]=ht_bin[1];
454 //ht_bin[2]=ht_bin[0];
455 //ht_bin[1]=(int)head->addr;
462 head=jump_dirty[vpage];
464 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
465 //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
466 // Don't restore blocks which are about to expire from the cache
467 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
468 if(verify_dirty(head->addr)) {
469 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
470 invalid_code[vaddr>>12]=0;
471 inv_code_start=inv_code_end=~0;
472 memory_map[vaddr>>12]|=0x40000000;
475 if(tlb_LUT_r[vaddr>>12]) {
476 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
477 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
480 restore_candidate[vpage>>3]|=1<<(vpage&7);
482 else restore_candidate[page>>3]|=1<<(page&7);
484 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
486 ht_bin[1]=(int)head->addr;
488 }else if(ht_bin[2]==-1) {
489 ht_bin[3]=(int)head->addr;
492 //ht_bin[3]=ht_bin[1];
493 //ht_bin[2]=ht_bin[0];
494 //ht_bin[1]=(int)head->addr;
502 //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
503 int r=new_recompile_block(vaddr);
504 if(r==0) return get_addr(vaddr);
505 // Execute in unmapped page, generate pagefault execption
507 Cause=(vaddr<<31)|0x8;
508 EPC=(vaddr&1)?vaddr-5:vaddr;
510 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
511 EntryHi=BadVAddr&0xFFFFE000;
512 return get_addr_ht(0x80000000);
516 void clear_all_regs(signed char regmap[])
519 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
522 signed char get_reg(signed char regmap[],int r)
525 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map[hr]==r) return hr;
529 // Find a register that is available for two consecutive cycles
530 signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
533 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map1[hr]==r&®map2[hr]==r) return hr;
537 int count_free_regs(signed char regmap[])
541 for(hr=0;hr<HOST_REGS;hr++)
543 if(hr!=EXCLUDE_REG) {
544 if(regmap[hr]<0) count++;
550 void dirty_reg(struct regstat *cur,signed char reg)
554 for (hr=0;hr<HOST_REGS;hr++) {
555 if((cur->regmap[hr]&63)==reg) {
561 // If we dirty the lower half of a 64 bit register which is now being
562 // sign-extended, we need to dump the upper half.
563 // Note: Do this only after completion of the instruction, because
564 // some instructions may need to read the full 64-bit value even if
565 // overwriting it (eg SLTI, DSRA32).
566 static void flush_dirty_uppers(struct regstat *cur)
569 for (hr=0;hr<HOST_REGS;hr++) {
570 if((cur->dirty>>hr)&1) {
573 if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
578 void set_const(struct regstat *cur,signed char reg,uint64_t value)
582 for (hr=0;hr<HOST_REGS;hr++) {
583 if(cur->regmap[hr]==reg) {
585 cur->constmap[hr]=value;
587 else if((cur->regmap[hr]^64)==reg) {
589 cur->constmap[hr]=value>>32;
594 void clear_const(struct regstat *cur,signed char reg)
598 for (hr=0;hr<HOST_REGS;hr++) {
599 if((cur->regmap[hr]&63)==reg) {
600 cur->isconst&=~(1<<hr);
605 int is_const(struct regstat *cur,signed char reg)
610 for (hr=0;hr<HOST_REGS;hr++) {
611 if((cur->regmap[hr]&63)==reg) {
612 return (cur->isconst>>hr)&1;
617 uint64_t get_const(struct regstat *cur,signed char reg)
621 for (hr=0;hr<HOST_REGS;hr++) {
622 if(cur->regmap[hr]==reg) {
623 return cur->constmap[hr];
626 printf("Unknown constant in r%d\n",reg);
630 // Least soon needed registers
631 // Look at the next ten instructions and see which registers
632 // will be used. Try not to reallocate these.
633 void lsn(u_char hsn[], int i, int *preferred_reg)
643 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
645 // Don't go past an unconditonal jump
652 if(rs1[i+j]) hsn[rs1[i+j]]=j;
653 if(rs2[i+j]) hsn[rs2[i+j]]=j;
654 if(rt1[i+j]) hsn[rt1[i+j]]=j;
655 if(rt2[i+j]) hsn[rt2[i+j]]=j;
656 if(itype[i+j]==STORE || itype[i+j]==STORELR) {
657 // Stores can allocate zero
661 // On some architectures stores need invc_ptr
662 #if defined(HOST_IMM8)
663 if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
667 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
675 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
677 // Follow first branch
678 int t=(ba[i+b]-start)>>2;
679 j=7-b;if(t+j>=slen) j=slen-t-1;
682 if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
683 if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
684 //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
685 //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
688 // TODO: preferred register based on backward branch
690 // Delay slot should preferably not overwrite branch conditions or cycle count
691 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
692 if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
693 if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
699 // Coprocessor load/store needs FTEMP, even if not declared
700 if(itype[i]==C1LS||itype[i]==C2LS) {
703 // Load L/R also uses FTEMP as a temporary register
704 if(itype[i]==LOADLR) {
707 // Also SWL/SWR/SDL/SDR
708 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
711 // Don't remove the TLB registers either
712 if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
715 // Don't remove the miniht registers
716 if(itype[i]==UJUMP||itype[i]==RJUMP)
723 // We only want to allocate registers if we're going to use them again soon
724 int needed_again(int r, int i)
730 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
732 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
733 return 0; // Don't need any registers if exiting the block
741 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
743 // Don't go past an unconditonal jump
747 if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
754 if(rs1[i+j]==r) rn=j;
755 if(rs2[i+j]==r) rn=j;
756 if((unneeded_reg[i+j]>>r)&1) rn=10;
757 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
765 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
767 // Follow first branch
769 int t=(ba[i+b]-start)>>2;
770 j=7-b;if(t+j>=slen) j=slen-t-1;
773 if(!((unneeded_reg[t+j]>>r)&1)) {
774 if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
775 if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
785 // Try to match register allocations at the end of a loop with those
787 int loop_reg(int i, int r, int hr)
796 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
798 // Don't go past an unconditonal jump
805 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
810 if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
811 if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
812 if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
814 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
816 int t=(ba[i+k]-start)>>2;
817 int reg=get_reg(regs[t].regmap_entry,r);
818 if(reg>=0) return reg;
819 //reg=get_reg(regs[t+1].regmap_entry,r);
820 //if(reg>=0) return reg;
828 // Allocate every register, preserving source/target regs
829 void alloc_all(struct regstat *cur,int i)
833 for(hr=0;hr<HOST_REGS;hr++) {
834 if(hr!=EXCLUDE_REG) {
835 if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
836 ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
839 cur->dirty&=~(1<<hr);
842 if((cur->regmap[hr]&63)==0)
845 cur->dirty&=~(1<<hr);
852 void div64(int64_t dividend,int64_t divisor)
856 //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
857 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
859 void divu64(uint64_t dividend,uint64_t divisor)
863 //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
864 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
867 void mult64(uint64_t m1,uint64_t m2)
869 unsigned long long int op1, op2, op3, op4;
870 unsigned long long int result1, result2, result3, result4;
871 unsigned long long int temp1, temp2, temp3, temp4;
887 op1 = op2 & 0xFFFFFFFF;
888 op2 = (op2 >> 32) & 0xFFFFFFFF;
889 op3 = op4 & 0xFFFFFFFF;
890 op4 = (op4 >> 32) & 0xFFFFFFFF;
893 temp2 = (temp1 >> 32) + op1 * op4;
895 temp4 = (temp3 >> 32) + op2 * op4;
897 result1 = temp1 & 0xFFFFFFFF;
898 result2 = temp2 + (temp3 & 0xFFFFFFFF);
899 result3 = (result2 >> 32) + temp4;
900 result4 = (result3 >> 32);
902 lo = result1 | (result2 << 32);
903 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
912 void multu64(uint64_t m1,uint64_t m2)
914 unsigned long long int op1, op2, op3, op4;
915 unsigned long long int result1, result2, result3, result4;
916 unsigned long long int temp1, temp2, temp3, temp4;
918 op1 = m1 & 0xFFFFFFFF;
919 op2 = (m1 >> 32) & 0xFFFFFFFF;
920 op3 = m2 & 0xFFFFFFFF;
921 op4 = (m2 >> 32) & 0xFFFFFFFF;
924 temp2 = (temp1 >> 32) + op1 * op4;
926 temp4 = (temp3 >> 32) + op2 * op4;
928 result1 = temp1 & 0xFFFFFFFF;
929 result2 = temp2 + (temp3 & 0xFFFFFFFF);
930 result3 = (result2 >> 32) + temp4;
931 result4 = (result3 >> 32);
933 lo = result1 | (result2 << 32);
934 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
936 //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
937 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
940 uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
948 else original=loaded;
951 uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
954 original>>=64-(bits^56);
955 original<<=64-(bits^56);
959 else original=loaded;
964 #include "assem_x86.c"
967 #include "assem_x64.c"
970 #include "assem_arm.c"
973 // Add virtual address mapping to linked list
974 void ll_add(struct ll_entry **head,int vaddr,void *addr)
976 struct ll_entry *new_entry;
977 new_entry=malloc(sizeof(struct ll_entry));
978 assert(new_entry!=NULL);
979 new_entry->vaddr=vaddr;
981 new_entry->addr=addr;
982 new_entry->next=*head;
986 // Add virtual address mapping for 32-bit compiled block
987 void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
989 ll_add(head,vaddr,addr);
991 (*head)->reg32=reg32;
995 // Check if an address is already compiled
996 // but don't return addresses which are about to expire from the cache
997 void *check_addr(u_int vaddr)
999 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
1000 if(ht_bin[0]==vaddr) {
1001 if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1002 if(isclean(ht_bin[1])) return (void *)ht_bin[1];
1004 if(ht_bin[2]==vaddr) {
1005 if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1006 if(isclean(ht_bin[3])) return (void *)ht_bin[3];
1008 u_int page=get_page(vaddr);
1009 struct ll_entry *head;
1012 if(head->vaddr==vaddr&&head->reg32==0) {
1013 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1014 // Update existing entry with current address
1015 if(ht_bin[0]==vaddr) {
1016 ht_bin[1]=(int)head->addr;
1019 if(ht_bin[2]==vaddr) {
1020 ht_bin[3]=(int)head->addr;
1023 // Insert into hash table with low priority.
1024 // Don't evict existing entries, as they are probably
1025 // addresses that are being accessed frequently.
1027 ht_bin[1]=(int)head->addr;
1029 }else if(ht_bin[2]==-1) {
1030 ht_bin[3]=(int)head->addr;
1041 void remove_hash(int vaddr)
1043 //printf("remove hash: %x\n",vaddr);
1044 int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1045 if(ht_bin[2]==vaddr) {
1046 ht_bin[2]=ht_bin[3]=-1;
1048 if(ht_bin[0]==vaddr) {
1049 ht_bin[0]=ht_bin[2];
1050 ht_bin[1]=ht_bin[3];
1051 ht_bin[2]=ht_bin[3]=-1;
1055 void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1057 struct ll_entry *next;
1059 if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1060 ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1062 inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1063 remove_hash((*head)->vaddr);
1070 head=&((*head)->next);
1075 // Remove all entries from linked list
1076 void ll_clear(struct ll_entry **head)
1078 struct ll_entry *cur;
1079 struct ll_entry *next;
1090 // Dereference the pointers and remove if it matches
1091 void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1094 int ptr=get_pointer(head->addr);
1095 inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1096 if(((ptr>>shift)==(addr>>shift)) ||
1097 (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1099 inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1100 u_int host_addr=(u_int)kill_pointer(head->addr);
1102 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1109 // This is called when we write to a compiled block (see do_invstub)
1110 void invalidate_page(u_int page)
1112 struct ll_entry *head;
1113 struct ll_entry *next;
1117 inv_debug("INVALIDATE: %x\n",head->vaddr);
1118 remove_hash(head->vaddr);
1123 head=jump_out[page];
1126 inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
1127 u_int host_addr=(u_int)kill_pointer(head->addr);
1129 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1137 static void invalidate_block_range(u_int block, u_int first, u_int last)
1139 u_int page=get_page(block<<12);
1140 //printf("first=%d last=%d\n",first,last);
1141 invalidate_page(page);
1142 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1143 assert(last<page+5);
1144 // Invalidate the adjacent pages if a block crosses a 4K boundary
1146 invalidate_page(first);
1149 for(first=page+1;first<last;first++) {
1150 invalidate_page(first);
1156 // Don't trap writes
1157 invalid_code[block]=1;
1159 // If there is a valid TLB entry for this page, remove write protect
1160 if(tlb_LUT_w[block]) {
1161 assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1162 // CHECK: Is this right?
1163 memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1164 u_int real_block=tlb_LUT_w[block]>>12;
1165 invalid_code[real_block]=1;
1166 if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1168 else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
1172 memset(mini_ht,-1,sizeof(mini_ht));
1176 void invalidate_block(u_int block)
1178 u_int page=get_page(block<<12);
1179 u_int vpage=get_vpage(block<<12);
1180 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1181 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1184 struct ll_entry *head;
1185 head=jump_dirty[vpage];
1186 //printf("page=%d vpage=%d\n",page,vpage);
1189 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1190 get_bounds((int)head->addr,&start,&end);
1191 //printf("start: %x end: %x\n",start,end);
1192 if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) {
1193 if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1194 if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1195 if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1199 if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1200 if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1201 if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1202 if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1209 invalidate_block_range(block,first,last);
1212 void invalidate_addr(u_int addr)
1216 // this check is done by the caller
1217 //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
1218 u_int page=get_page(addr);
1219 if(page<2048) { // RAM
1220 struct ll_entry *head;
1221 u_int addr_min=~0, addr_max=0;
1222 int mask=RAM_SIZE-1;
1224 inv_code_start=addr&~0xfff;
1225 inv_code_end=addr|0xfff;
1228 // must check previous page too because of spans..
1230 inv_code_start-=0x1000;
1232 for(;pg1<=page;pg1++) {
1233 for(head=jump_dirty[pg1];head!=NULL;head=head->next) {
1235 get_bounds((int)head->addr,&start,&end);
1236 if((start&mask)<=(addr&mask)&&(addr&mask)<(end&mask)) {
1237 if(start<addr_min) addr_min=start;
1238 if(end>addr_max) addr_max=end;
1240 else if(addr<start) {
1241 if(start<inv_code_end)
1242 inv_code_end=start-1;
1245 if(end>inv_code_start)
1251 inv_debug("INV ADDR: %08x hit %08x-%08x\n", addr, addr_min, addr_max);
1252 inv_code_start=inv_code_end=~0;
1253 invalidate_block_range(addr>>12,(addr_min&mask)>>12,(addr_max&mask)>>12);
1257 inv_debug("INV ADDR: %08x miss, inv %08x-%08x, sk %d\n", addr, inv_code_start, inv_code_end, 0);//rhits);
1260 if(page!=0) // FIXME: don't know what's up with page 0 (Klonoa)
1264 invalidate_block(addr>>12);
1267 // This is called when loading a save state.
1268 // Anything could have changed, so invalidate everything.
1269 void invalidate_all_pages()
1272 for(page=0;page<4096;page++)
1273 invalidate_page(page);
1274 for(page=0;page<1048576;page++)
1275 if(!invalid_code[page]) {
1276 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1277 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1280 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1283 memset(mini_ht,-1,sizeof(mini_ht));
1287 for(page=0;page<0x100000;page++) {
1288 if(tlb_LUT_r[page]) {
1289 memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1290 if(!tlb_LUT_w[page]||!invalid_code[page])
1291 memory_map[page]|=0x40000000; // Write protect
1293 else memory_map[page]=-1;
1294 if(page==0x80000) page=0xC0000;
1300 // Add an entry to jump_out after making a link
1301 void add_link(u_int vaddr,void *src)
1303 u_int page=get_page(vaddr);
1304 inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1305 int *ptr=(int *)(src+4);
1306 assert((*ptr&0x0fff0000)==0x059f0000);
1307 ll_add(jump_out+page,vaddr,src);
1308 //int ptr=get_pointer(src);
1309 //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1312 // If a code block was found to be unmodified (bit was set in
1313 // restore_candidate) and it remains unmodified (bit is clear
1314 // in invalid_code) then move the entries for that 4K page from
1315 // the dirty list to the clean list.
1316 void clean_blocks(u_int page)
1318 struct ll_entry *head;
1319 inv_debug("INV: clean_blocks page=%d\n",page);
1320 head=jump_dirty[page];
1322 if(!invalid_code[head->vaddr>>12]) {
1323 // Don't restore blocks which are about to expire from the cache
1324 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1326 if(verify_dirty((int)head->addr)) {
1327 //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1330 get_bounds((int)head->addr,&start,&end);
1331 if(start-(u_int)rdram<RAM_SIZE) {
1332 for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1333 inv|=invalid_code[i];
1336 if((signed int)head->vaddr>=(signed int)0xC0000000) {
1337 u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1338 //printf("addr=%x start=%x end=%x\n",addr,start,end);
1339 if(addr<start||addr>=end) inv=1;
1341 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
1345 void * clean_addr=(void *)get_clean_addr((int)head->addr);
1346 if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1349 if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
1351 inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1352 //printf("page=%x, addr=%x\n",page,head->vaddr);
1353 //assert(head->vaddr>>12==(page|0x80000));
1354 ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1355 int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1357 if(ht_bin[0]==head->vaddr) {
1358 ht_bin[1]=(int)clean_addr; // Replace existing entry
1360 if(ht_bin[2]==head->vaddr) {
1361 ht_bin[3]=(int)clean_addr; // Replace existing entry
1374 void mov_alloc(struct regstat *current,int i)
1376 // Note: Don't need to actually alloc the source registers
1377 if((~current->is32>>rs1[i])&1) {
1378 //alloc_reg64(current,i,rs1[i]);
1379 alloc_reg64(current,i,rt1[i]);
1380 current->is32&=~(1LL<<rt1[i]);
1382 //alloc_reg(current,i,rs1[i]);
1383 alloc_reg(current,i,rt1[i]);
1384 current->is32|=(1LL<<rt1[i]);
1386 clear_const(current,rs1[i]);
1387 clear_const(current,rt1[i]);
1388 dirty_reg(current,rt1[i]);
1391 void shiftimm_alloc(struct regstat *current,int i)
1393 clear_const(current,rs1[i]);
1394 clear_const(current,rt1[i]);
1395 if(opcode2[i]<=0x3) // SLL/SRL/SRA
1398 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1400 alloc_reg(current,i,rt1[i]);
1401 current->is32|=1LL<<rt1[i];
1402 dirty_reg(current,rt1[i]);
1405 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1408 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1409 alloc_reg64(current,i,rt1[i]);
1410 current->is32&=~(1LL<<rt1[i]);
1411 dirty_reg(current,rt1[i]);
1414 if(opcode2[i]==0x3c) // DSLL32
1417 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1418 alloc_reg64(current,i,rt1[i]);
1419 current->is32&=~(1LL<<rt1[i]);
1420 dirty_reg(current,rt1[i]);
1423 if(opcode2[i]==0x3e) // DSRL32
1426 alloc_reg64(current,i,rs1[i]);
1428 alloc_reg64(current,i,rt1[i]);
1429 current->is32&=~(1LL<<rt1[i]);
1431 alloc_reg(current,i,rt1[i]);
1432 current->is32|=1LL<<rt1[i];
1434 dirty_reg(current,rt1[i]);
1437 if(opcode2[i]==0x3f) // DSRA32
1440 alloc_reg64(current,i,rs1[i]);
1441 alloc_reg(current,i,rt1[i]);
1442 current->is32|=1LL<<rt1[i];
1443 dirty_reg(current,rt1[i]);
1448 void shift_alloc(struct regstat *current,int i)
1451 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1453 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1454 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1455 alloc_reg(current,i,rt1[i]);
1456 if(rt1[i]==rs2[i]) {
1457 alloc_reg_temp(current,i,-1);
1458 minimum_free_regs[i]=1;
1460 current->is32|=1LL<<rt1[i];
1461 } else { // DSLLV/DSRLV/DSRAV
1462 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1463 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1464 alloc_reg64(current,i,rt1[i]);
1465 current->is32&=~(1LL<<rt1[i]);
1466 if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1468 alloc_reg_temp(current,i,-1);
1469 minimum_free_regs[i]=1;
1472 clear_const(current,rs1[i]);
1473 clear_const(current,rs2[i]);
1474 clear_const(current,rt1[i]);
1475 dirty_reg(current,rt1[i]);
1479 void alu_alloc(struct regstat *current,int i)
1481 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1483 if(rs1[i]&&rs2[i]) {
1484 alloc_reg(current,i,rs1[i]);
1485 alloc_reg(current,i,rs2[i]);
1488 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1489 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1491 alloc_reg(current,i,rt1[i]);
1493 current->is32|=1LL<<rt1[i];
1495 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1497 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1499 alloc_reg64(current,i,rs1[i]);
1500 alloc_reg64(current,i,rs2[i]);
1501 alloc_reg(current,i,rt1[i]);
1503 alloc_reg(current,i,rs1[i]);
1504 alloc_reg(current,i,rs2[i]);
1505 alloc_reg(current,i,rt1[i]);
1508 current->is32|=1LL<<rt1[i];
1510 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1512 if(rs1[i]&&rs2[i]) {
1513 alloc_reg(current,i,rs1[i]);
1514 alloc_reg(current,i,rs2[i]);
1518 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1519 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1521 alloc_reg(current,i,rt1[i]);
1522 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1524 if(!((current->uu>>rt1[i])&1)) {
1525 alloc_reg64(current,i,rt1[i]);
1527 if(get_reg(current->regmap,rt1[i]|64)>=0) {
1528 if(rs1[i]&&rs2[i]) {
1529 alloc_reg64(current,i,rs1[i]);
1530 alloc_reg64(current,i,rs2[i]);
1534 // Is is really worth it to keep 64-bit values in registers?
1536 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1537 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1541 current->is32&=~(1LL<<rt1[i]);
1543 current->is32|=1LL<<rt1[i];
1547 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1549 if(rs1[i]&&rs2[i]) {
1550 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1551 alloc_reg64(current,i,rs1[i]);
1552 alloc_reg64(current,i,rs2[i]);
1553 alloc_reg64(current,i,rt1[i]);
1555 alloc_reg(current,i,rs1[i]);
1556 alloc_reg(current,i,rs2[i]);
1557 alloc_reg(current,i,rt1[i]);
1561 alloc_reg(current,i,rt1[i]);
1562 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1563 // DADD used as move, or zeroing
1564 // If we have a 64-bit source, then make the target 64 bits too
1565 if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1566 if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1567 alloc_reg64(current,i,rt1[i]);
1568 } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1569 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1570 alloc_reg64(current,i,rt1[i]);
1572 if(opcode2[i]>=0x2e&&rs2[i]) {
1573 // DSUB used as negation - 64-bit result
1574 // If we have a 32-bit register, extend it to 64 bits
1575 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1576 alloc_reg64(current,i,rt1[i]);
1580 if(rs1[i]&&rs2[i]) {
1581 current->is32&=~(1LL<<rt1[i]);
1583 current->is32&=~(1LL<<rt1[i]);
1584 if((current->is32>>rs1[i])&1)
1585 current->is32|=1LL<<rt1[i];
1587 current->is32&=~(1LL<<rt1[i]);
1588 if((current->is32>>rs2[i])&1)
1589 current->is32|=1LL<<rt1[i];
1591 current->is32|=1LL<<rt1[i];
1595 clear_const(current,rs1[i]);
1596 clear_const(current,rs2[i]);
1597 clear_const(current,rt1[i]);
1598 dirty_reg(current,rt1[i]);
1601 void imm16_alloc(struct regstat *current,int i)
1603 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1605 if(rt1[i]) alloc_reg(current,i,rt1[i]);
1606 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1607 current->is32&=~(1LL<<rt1[i]);
1608 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1609 // TODO: Could preserve the 32-bit flag if the immediate is zero
1610 alloc_reg64(current,i,rt1[i]);
1611 alloc_reg64(current,i,rs1[i]);
1613 clear_const(current,rs1[i]);
1614 clear_const(current,rt1[i]);
1616 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1617 if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1618 current->is32|=1LL<<rt1[i];
1619 clear_const(current,rs1[i]);
1620 clear_const(current,rt1[i]);
1622 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1623 if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1624 if(rs1[i]!=rt1[i]) {
1625 if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1626 alloc_reg64(current,i,rt1[i]);
1627 current->is32&=~(1LL<<rt1[i]);
1630 else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1631 if(is_const(current,rs1[i])) {
1632 int v=get_const(current,rs1[i]);
1633 if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1634 if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1635 if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1637 else clear_const(current,rt1[i]);
1639 else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1640 if(is_const(current,rs1[i])) {
1641 int v=get_const(current,rs1[i]);
1642 set_const(current,rt1[i],v+imm[i]);
1644 else clear_const(current,rt1[i]);
1645 current->is32|=1LL<<rt1[i];
1648 set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1649 current->is32|=1LL<<rt1[i];
1651 dirty_reg(current,rt1[i]);
1654 void load_alloc(struct regstat *current,int i)
1656 clear_const(current,rt1[i]);
1657 //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1658 if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1659 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1660 if(rt1[i]&&!((current->u>>rt1[i])&1)) {
1661 alloc_reg(current,i,rt1[i]);
1662 assert(get_reg(current->regmap,rt1[i])>=0);
1663 if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1665 current->is32&=~(1LL<<rt1[i]);
1666 alloc_reg64(current,i,rt1[i]);
1668 else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1670 current->is32&=~(1LL<<rt1[i]);
1671 alloc_reg64(current,i,rt1[i]);
1672 alloc_all(current,i);
1673 alloc_reg64(current,i,FTEMP);
1674 minimum_free_regs[i]=HOST_REGS;
1676 else current->is32|=1LL<<rt1[i];
1677 dirty_reg(current,rt1[i]);
1678 // If using TLB, need a register for pointer to the mapping table
1679 if(using_tlb) alloc_reg(current,i,TLREG);
1680 // LWL/LWR need a temporary register for the old value
1681 if(opcode[i]==0x22||opcode[i]==0x26)
1683 alloc_reg(current,i,FTEMP);
1684 alloc_reg_temp(current,i,-1);
1685 minimum_free_regs[i]=1;
1690 // Load to r0 or unneeded register (dummy load)
1691 // but we still need a register to calculate the address
1692 if(opcode[i]==0x22||opcode[i]==0x26)
1694 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1696 // If using TLB, need a register for pointer to the mapping table
1697 if(using_tlb) alloc_reg(current,i,TLREG);
1698 alloc_reg_temp(current,i,-1);
1699 minimum_free_regs[i]=1;
1700 if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1702 alloc_all(current,i);
1703 alloc_reg64(current,i,FTEMP);
1704 minimum_free_regs[i]=HOST_REGS;
1709 void store_alloc(struct regstat *current,int i)
1711 clear_const(current,rs2[i]);
1712 if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1713 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1714 alloc_reg(current,i,rs2[i]);
1715 if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1716 alloc_reg64(current,i,rs2[i]);
1717 if(rs2[i]) alloc_reg(current,i,FTEMP);
1719 // If using TLB, need a register for pointer to the mapping table
1720 if(using_tlb) alloc_reg(current,i,TLREG);
1721 #if defined(HOST_IMM8)
1722 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1723 else alloc_reg(current,i,INVCP);
1725 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
1726 alloc_reg(current,i,FTEMP);
1728 // We need a temporary register for address generation
1729 alloc_reg_temp(current,i,-1);
1730 minimum_free_regs[i]=1;
1733 void c1ls_alloc(struct regstat *current,int i)
1735 //clear_const(current,rs1[i]); // FIXME
1736 clear_const(current,rt1[i]);
1737 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1738 alloc_reg(current,i,CSREG); // Status
1739 alloc_reg(current,i,FTEMP);
1740 if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1741 alloc_reg64(current,i,FTEMP);
1743 // If using TLB, need a register for pointer to the mapping table
1744 if(using_tlb) alloc_reg(current,i,TLREG);
1745 #if defined(HOST_IMM8)
1746 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1747 else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1748 alloc_reg(current,i,INVCP);
1750 // We need a temporary register for address generation
1751 alloc_reg_temp(current,i,-1);
1754 void c2ls_alloc(struct regstat *current,int i)
1756 clear_const(current,rt1[i]);
1757 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1758 alloc_reg(current,i,FTEMP);
1759 // If using TLB, need a register for pointer to the mapping table
1760 if(using_tlb) alloc_reg(current,i,TLREG);
1761 #if defined(HOST_IMM8)
1762 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1763 else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1764 alloc_reg(current,i,INVCP);
1766 // We need a temporary register for address generation
1767 alloc_reg_temp(current,i,-1);
1768 minimum_free_regs[i]=1;
1771 #ifndef multdiv_alloc
1772 void multdiv_alloc(struct regstat *current,int i)
1779 // case 0x1D: DMULTU
1782 clear_const(current,rs1[i]);
1783 clear_const(current,rs2[i]);
1786 if((opcode2[i]&4)==0) // 32-bit
1788 current->u&=~(1LL<<HIREG);
1789 current->u&=~(1LL<<LOREG);
1790 alloc_reg(current,i,HIREG);
1791 alloc_reg(current,i,LOREG);
1792 alloc_reg(current,i,rs1[i]);
1793 alloc_reg(current,i,rs2[i]);
1794 current->is32|=1LL<<HIREG;
1795 current->is32|=1LL<<LOREG;
1796 dirty_reg(current,HIREG);
1797 dirty_reg(current,LOREG);
1801 current->u&=~(1LL<<HIREG);
1802 current->u&=~(1LL<<LOREG);
1803 current->uu&=~(1LL<<HIREG);
1804 current->uu&=~(1LL<<LOREG);
1805 alloc_reg64(current,i,HIREG);
1806 //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1807 alloc_reg64(current,i,rs1[i]);
1808 alloc_reg64(current,i,rs2[i]);
1809 alloc_all(current,i);
1810 current->is32&=~(1LL<<HIREG);
1811 current->is32&=~(1LL<<LOREG);
1812 dirty_reg(current,HIREG);
1813 dirty_reg(current,LOREG);
1814 minimum_free_regs[i]=HOST_REGS;
1819 // Multiply by zero is zero.
1820 // MIPS does not have a divide by zero exception.
1821 // The result is undefined, we return zero.
1822 alloc_reg(current,i,HIREG);
1823 alloc_reg(current,i,LOREG);
1824 current->is32|=1LL<<HIREG;
1825 current->is32|=1LL<<LOREG;
1826 dirty_reg(current,HIREG);
1827 dirty_reg(current,LOREG);
1832 void cop0_alloc(struct regstat *current,int i)
1834 if(opcode2[i]==0) // MFC0
1837 clear_const(current,rt1[i]);
1838 alloc_all(current,i);
1839 alloc_reg(current,i,rt1[i]);
1840 current->is32|=1LL<<rt1[i];
1841 dirty_reg(current,rt1[i]);
1844 else if(opcode2[i]==4) // MTC0
1847 clear_const(current,rs1[i]);
1848 alloc_reg(current,i,rs1[i]);
1849 alloc_all(current,i);
1852 alloc_all(current,i); // FIXME: Keep r0
1854 alloc_reg(current,i,0);
1859 // TLBR/TLBWI/TLBWR/TLBP/ERET
1860 assert(opcode2[i]==0x10);
1861 alloc_all(current,i);
1863 minimum_free_regs[i]=HOST_REGS;
1866 void cop1_alloc(struct regstat *current,int i)
1868 alloc_reg(current,i,CSREG); // Load status
1869 if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1872 clear_const(current,rt1[i]);
1874 alloc_reg64(current,i,rt1[i]); // DMFC1
1875 current->is32&=~(1LL<<rt1[i]);
1877 alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1878 current->is32|=1LL<<rt1[i];
1880 dirty_reg(current,rt1[i]);
1882 alloc_reg_temp(current,i,-1);
1884 else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1887 clear_const(current,rs1[i]);
1889 alloc_reg64(current,i,rs1[i]); // DMTC1
1891 alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1892 alloc_reg_temp(current,i,-1);
1896 alloc_reg(current,i,0);
1897 alloc_reg_temp(current,i,-1);
1900 minimum_free_regs[i]=1;
1902 void fconv_alloc(struct regstat *current,int i)
1904 alloc_reg(current,i,CSREG); // Load status
1905 alloc_reg_temp(current,i,-1);
1906 minimum_free_regs[i]=1;
1908 void float_alloc(struct regstat *current,int i)
1910 alloc_reg(current,i,CSREG); // Load status
1911 alloc_reg_temp(current,i,-1);
1912 minimum_free_regs[i]=1;
1914 void c2op_alloc(struct regstat *current,int i)
1916 alloc_reg_temp(current,i,-1);
1918 void fcomp_alloc(struct regstat *current,int i)
1920 alloc_reg(current,i,CSREG); // Load status
1921 alloc_reg(current,i,FSREG); // Load flags
1922 dirty_reg(current,FSREG); // Flag will be modified
1923 alloc_reg_temp(current,i,-1);
1924 minimum_free_regs[i]=1;
1927 void syscall_alloc(struct regstat *current,int i)
1929 alloc_cc(current,i);
1930 dirty_reg(current,CCREG);
1931 alloc_all(current,i);
1932 minimum_free_regs[i]=HOST_REGS;
1936 void delayslot_alloc(struct regstat *current,int i)
1947 assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1);
1948 printf("Disabled speculative precompilation\n");
1952 imm16_alloc(current,i);
1956 load_alloc(current,i);
1960 store_alloc(current,i);
1963 alu_alloc(current,i);
1966 shift_alloc(current,i);
1969 multdiv_alloc(current,i);
1972 shiftimm_alloc(current,i);
1975 mov_alloc(current,i);
1978 cop0_alloc(current,i);
1982 cop1_alloc(current,i);
1985 c1ls_alloc(current,i);
1988 c2ls_alloc(current,i);
1991 fconv_alloc(current,i);
1994 float_alloc(current,i);
1997 fcomp_alloc(current,i);
2000 c2op_alloc(current,i);
2005 // Special case where a branch and delay slot span two pages in virtual memory
2006 static void pagespan_alloc(struct regstat *current,int i)
2009 current->wasconst=0;
2011 minimum_free_regs[i]=HOST_REGS;
2012 alloc_all(current,i);
2013 alloc_cc(current,i);
2014 dirty_reg(current,CCREG);
2015 if(opcode[i]==3) // JAL
2017 alloc_reg(current,i,31);
2018 dirty_reg(current,31);
2020 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
2022 alloc_reg(current,i,rs1[i]);
2024 alloc_reg(current,i,rt1[i]);
2025 dirty_reg(current,rt1[i]);
2028 if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
2030 if(rs1[i]) alloc_reg(current,i,rs1[i]);
2031 if(rs2[i]) alloc_reg(current,i,rs2[i]);
2032 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
2034 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2035 if(rs2[i]) alloc_reg64(current,i,rs2[i]);
2039 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
2041 if(rs1[i]) alloc_reg(current,i,rs1[i]);
2042 if(!((current->is32>>rs1[i])&1))
2044 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2048 if(opcode[i]==0x11) // BC1
2050 alloc_reg(current,i,FSREG);
2051 alloc_reg(current,i,CSREG);
2056 add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
2058 stubs[stubcount][0]=type;
2059 stubs[stubcount][1]=addr;
2060 stubs[stubcount][2]=retaddr;
2061 stubs[stubcount][3]=a;
2062 stubs[stubcount][4]=b;
2063 stubs[stubcount][5]=c;
2064 stubs[stubcount][6]=d;
2065 stubs[stubcount][7]=e;
2069 // Write out a single register
2070 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
2073 for(hr=0;hr<HOST_REGS;hr++) {
2074 if(hr!=EXCLUDE_REG) {
2075 if((regmap[hr]&63)==r) {
2078 emit_storereg(r,hr);
2080 if((is32>>regmap[hr])&1) {
2081 emit_sarimm(hr,31,hr);
2082 emit_storereg(r|64,hr);
2086 emit_storereg(r|64,hr);
2096 //if(!tracedebug) return 0;
2099 for(i=0;i<2097152;i++) {
2100 unsigned int temp=sum;
2103 sum^=((u_int *)rdram)[i];
2112 sum^=((u_int *)reg)[i];
2120 printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2122 #ifndef DISABLE_COP1
2125 printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2135 void memdebug(int i)
2137 //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2138 //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2141 //if(Count>=-2084597794) {
2142 if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2144 printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2145 //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2146 //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2149 printf("TRACE: %x\n",(&i)[-1]);
2153 printf("TRACE: %x \n",(&j)[10]);
2154 printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2158 //printf("TRACE: %x\n",(&i)[-1]);
2161 void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2163 printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2166 void alu_assemble(int i,struct regstat *i_regs)
2168 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2170 signed char s1,s2,t;
2171 t=get_reg(i_regs->regmap,rt1[i]);
2173 s1=get_reg(i_regs->regmap,rs1[i]);
2174 s2=get_reg(i_regs->regmap,rs2[i]);
2175 if(rs1[i]&&rs2[i]) {
2178 if(opcode2[i]&2) emit_sub(s1,s2,t);
2179 else emit_add(s1,s2,t);
2182 if(s1>=0) emit_mov(s1,t);
2183 else emit_loadreg(rs1[i],t);
2187 if(opcode2[i]&2) emit_neg(s2,t);
2188 else emit_mov(s2,t);
2191 emit_loadreg(rs2[i],t);
2192 if(opcode2[i]&2) emit_neg(t,t);
2195 else emit_zeroreg(t);
2199 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2201 signed char s1l,s2l,s1h,s2h,tl,th;
2202 tl=get_reg(i_regs->regmap,rt1[i]);
2203 th=get_reg(i_regs->regmap,rt1[i]|64);
2205 s1l=get_reg(i_regs->regmap,rs1[i]);
2206 s2l=get_reg(i_regs->regmap,rs2[i]);
2207 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2208 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2209 if(rs1[i]&&rs2[i]) {
2212 if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2213 else emit_adds(s1l,s2l,tl);
2215 #ifdef INVERTED_CARRY
2216 if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2218 if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2220 else emit_add(s1h,s2h,th);
2224 if(s1l>=0) emit_mov(s1l,tl);
2225 else emit_loadreg(rs1[i],tl);
2227 if(s1h>=0) emit_mov(s1h,th);
2228 else emit_loadreg(rs1[i]|64,th);
2233 if(opcode2[i]&2) emit_negs(s2l,tl);
2234 else emit_mov(s2l,tl);
2237 emit_loadreg(rs2[i],tl);
2238 if(opcode2[i]&2) emit_negs(tl,tl);
2241 #ifdef INVERTED_CARRY
2242 if(s2h>=0) emit_mov(s2h,th);
2243 else emit_loadreg(rs2[i]|64,th);
2245 emit_adcimm(-1,th); // x86 has inverted carry flag
2250 if(s2h>=0) emit_rscimm(s2h,0,th);
2252 emit_loadreg(rs2[i]|64,th);
2253 emit_rscimm(th,0,th);
2256 if(s2h>=0) emit_mov(s2h,th);
2257 else emit_loadreg(rs2[i]|64,th);
2264 if(th>=0) emit_zeroreg(th);
2269 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2271 signed char s1l,s1h,s2l,s2h,t;
2272 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2274 t=get_reg(i_regs->regmap,rt1[i]);
2277 s1l=get_reg(i_regs->regmap,rs1[i]);
2278 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2279 s2l=get_reg(i_regs->regmap,rs2[i]);
2280 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2281 if(rs2[i]==0) // rx<r0
2284 if(opcode2[i]==0x2a) // SLT
2285 emit_shrimm(s1h,31,t);
2286 else // SLTU (unsigned can not be less than zero)
2289 else if(rs1[i]==0) // r0<rx
2292 if(opcode2[i]==0x2a) // SLT
2293 emit_set_gz64_32(s2h,s2l,t);
2294 else // SLTU (set if not zero)
2295 emit_set_nz64_32(s2h,s2l,t);
2298 assert(s1l>=0);assert(s1h>=0);
2299 assert(s2l>=0);assert(s2h>=0);
2300 if(opcode2[i]==0x2a) // SLT
2301 emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2303 emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2307 t=get_reg(i_regs->regmap,rt1[i]);
2310 s1l=get_reg(i_regs->regmap,rs1[i]);
2311 s2l=get_reg(i_regs->regmap,rs2[i]);
2312 if(rs2[i]==0) // rx<r0
2315 if(opcode2[i]==0x2a) // SLT
2316 emit_shrimm(s1l,31,t);
2317 else // SLTU (unsigned can not be less than zero)
2320 else if(rs1[i]==0) // r0<rx
2323 if(opcode2[i]==0x2a) // SLT
2324 emit_set_gz32(s2l,t);
2325 else // SLTU (set if not zero)
2326 emit_set_nz32(s2l,t);
2329 assert(s1l>=0);assert(s2l>=0);
2330 if(opcode2[i]==0x2a) // SLT
2331 emit_set_if_less32(s1l,s2l,t);
2333 emit_set_if_carry32(s1l,s2l,t);
2339 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2341 signed char s1l,s1h,s2l,s2h,th,tl;
2342 tl=get_reg(i_regs->regmap,rt1[i]);
2343 th=get_reg(i_regs->regmap,rt1[i]|64);
2344 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2348 s1l=get_reg(i_regs->regmap,rs1[i]);
2349 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2350 s2l=get_reg(i_regs->regmap,rs2[i]);
2351 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2352 if(rs1[i]&&rs2[i]) {
2353 assert(s1l>=0);assert(s1h>=0);
2354 assert(s2l>=0);assert(s2h>=0);
2355 if(opcode2[i]==0x24) { // AND
2356 emit_and(s1l,s2l,tl);
2357 emit_and(s1h,s2h,th);
2359 if(opcode2[i]==0x25) { // OR
2360 emit_or(s1l,s2l,tl);
2361 emit_or(s1h,s2h,th);
2363 if(opcode2[i]==0x26) { // XOR
2364 emit_xor(s1l,s2l,tl);
2365 emit_xor(s1h,s2h,th);
2367 if(opcode2[i]==0x27) { // NOR
2368 emit_or(s1l,s2l,tl);
2369 emit_or(s1h,s2h,th);
2376 if(opcode2[i]==0x24) { // AND
2380 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2382 if(s1l>=0) emit_mov(s1l,tl);
2383 else emit_loadreg(rs1[i],tl);
2384 if(s1h>=0) emit_mov(s1h,th);
2385 else emit_loadreg(rs1[i]|64,th);
2389 if(s2l>=0) emit_mov(s2l,tl);
2390 else emit_loadreg(rs2[i],tl);
2391 if(s2h>=0) emit_mov(s2h,th);
2392 else emit_loadreg(rs2[i]|64,th);
2399 if(opcode2[i]==0x27) { // NOR
2401 if(s1l>=0) emit_not(s1l,tl);
2403 emit_loadreg(rs1[i],tl);
2406 if(s1h>=0) emit_not(s1h,th);
2408 emit_loadreg(rs1[i]|64,th);
2414 if(s2l>=0) emit_not(s2l,tl);
2416 emit_loadreg(rs2[i],tl);
2419 if(s2h>=0) emit_not(s2h,th);
2421 emit_loadreg(rs2[i]|64,th);
2437 s1l=get_reg(i_regs->regmap,rs1[i]);
2438 s2l=get_reg(i_regs->regmap,rs2[i]);
2439 if(rs1[i]&&rs2[i]) {
2442 if(opcode2[i]==0x24) { // AND
2443 emit_and(s1l,s2l,tl);
2445 if(opcode2[i]==0x25) { // OR
2446 emit_or(s1l,s2l,tl);
2448 if(opcode2[i]==0x26) { // XOR
2449 emit_xor(s1l,s2l,tl);
2451 if(opcode2[i]==0x27) { // NOR
2452 emit_or(s1l,s2l,tl);
2458 if(opcode2[i]==0x24) { // AND
2461 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2463 if(s1l>=0) emit_mov(s1l,tl);
2464 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2468 if(s2l>=0) emit_mov(s2l,tl);
2469 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2471 else emit_zeroreg(tl);
2473 if(opcode2[i]==0x27) { // NOR
2475 if(s1l>=0) emit_not(s1l,tl);
2477 emit_loadreg(rs1[i],tl);
2483 if(s2l>=0) emit_not(s2l,tl);
2485 emit_loadreg(rs2[i],tl);
2489 else emit_movimm(-1,tl);
2498 void imm16_assemble(int i,struct regstat *i_regs)
2500 if (opcode[i]==0x0f) { // LUI
2503 t=get_reg(i_regs->regmap,rt1[i]);
2506 if(!((i_regs->isconst>>t)&1))
2507 emit_movimm(imm[i]<<16,t);
2511 if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2514 t=get_reg(i_regs->regmap,rt1[i]);
2515 s=get_reg(i_regs->regmap,rs1[i]);
2520 if(!((i_regs->isconst>>t)&1)) {
2522 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2523 emit_addimm(t,imm[i],t);
2525 if(!((i_regs->wasconst>>s)&1))
2526 emit_addimm(s,imm[i],t);
2528 emit_movimm(constmap[i][s]+imm[i],t);
2534 if(!((i_regs->isconst>>t)&1))
2535 emit_movimm(imm[i],t);
2540 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2542 signed char sh,sl,th,tl;
2543 th=get_reg(i_regs->regmap,rt1[i]|64);
2544 tl=get_reg(i_regs->regmap,rt1[i]);
2545 sh=get_reg(i_regs->regmap,rs1[i]|64);
2546 sl=get_reg(i_regs->regmap,rs1[i]);
2552 emit_addimm64_32(sh,sl,imm[i],th,tl);
2555 emit_addimm(sl,imm[i],tl);
2558 emit_movimm(imm[i],tl);
2559 if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2564 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2566 //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2567 signed char sh,sl,t;
2568 t=get_reg(i_regs->regmap,rt1[i]);
2569 sh=get_reg(i_regs->regmap,rs1[i]|64);
2570 sl=get_reg(i_regs->regmap,rs1[i]);
2574 if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2575 if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2576 if(opcode[i]==0x0a) { // SLTI
2578 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2579 emit_slti32(t,imm[i],t);
2581 emit_slti32(sl,imm[i],t);
2586 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2587 emit_sltiu32(t,imm[i],t);
2589 emit_sltiu32(sl,imm[i],t);
2594 if(opcode[i]==0x0a) // SLTI
2595 emit_slti64_32(sh,sl,imm[i],t);
2597 emit_sltiu64_32(sh,sl,imm[i],t);
2600 // SLTI(U) with r0 is just stupid,
2601 // nonetheless examples can be found
2602 if(opcode[i]==0x0a) // SLTI
2603 if(0<imm[i]) emit_movimm(1,t);
2604 else emit_zeroreg(t);
2607 if(imm[i]) emit_movimm(1,t);
2608 else emit_zeroreg(t);
2614 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2616 signed char sh,sl,th,tl;
2617 th=get_reg(i_regs->regmap,rt1[i]|64);
2618 tl=get_reg(i_regs->regmap,rt1[i]);
2619 sh=get_reg(i_regs->regmap,rs1[i]|64);
2620 sl=get_reg(i_regs->regmap,rs1[i]);
2621 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2622 if(opcode[i]==0x0c) //ANDI
2626 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2627 emit_andimm(tl,imm[i],tl);
2629 if(!((i_regs->wasconst>>sl)&1))
2630 emit_andimm(sl,imm[i],tl);
2632 emit_movimm(constmap[i][sl]&imm[i],tl);
2637 if(th>=0) emit_zeroreg(th);
2643 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2647 emit_loadreg(rs1[i]|64,th);
2652 if(opcode[i]==0x0d) //ORI
2654 emit_orimm(tl,imm[i],tl);
2656 if(!((i_regs->wasconst>>sl)&1))
2657 emit_orimm(sl,imm[i],tl);
2659 emit_movimm(constmap[i][sl]|imm[i],tl);
2661 if(opcode[i]==0x0e) //XORI
2663 emit_xorimm(tl,imm[i],tl);
2665 if(!((i_regs->wasconst>>sl)&1))
2666 emit_xorimm(sl,imm[i],tl);
2668 emit_movimm(constmap[i][sl]^imm[i],tl);
2672 emit_movimm(imm[i],tl);
2673 if(th>=0) emit_zeroreg(th);
2681 void shiftimm_assemble(int i,struct regstat *i_regs)
2683 if(opcode2[i]<=0x3) // SLL/SRL/SRA
2687 t=get_reg(i_regs->regmap,rt1[i]);
2688 s=get_reg(i_regs->regmap,rs1[i]);
2697 if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2699 if(opcode2[i]==0) // SLL
2701 emit_shlimm(s<0?t:s,imm[i],t);
2703 if(opcode2[i]==2) // SRL
2705 emit_shrimm(s<0?t:s,imm[i],t);
2707 if(opcode2[i]==3) // SRA
2709 emit_sarimm(s<0?t:s,imm[i],t);
2713 if(s>=0 && s!=t) emit_mov(s,t);
2717 //emit_storereg(rt1[i],t); //DEBUG
2720 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2723 signed char sh,sl,th,tl;
2724 th=get_reg(i_regs->regmap,rt1[i]|64);
2725 tl=get_reg(i_regs->regmap,rt1[i]);
2726 sh=get_reg(i_regs->regmap,rs1[i]|64);
2727 sl=get_reg(i_regs->regmap,rs1[i]);
2732 if(th>=0) emit_zeroreg(th);
2739 if(opcode2[i]==0x38) // DSLL
2741 if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2742 emit_shlimm(sl,imm[i],tl);
2744 if(opcode2[i]==0x3a) // DSRL
2746 emit_shrdimm(sl,sh,imm[i],tl);
2747 if(th>=0) emit_shrimm(sh,imm[i],th);
2749 if(opcode2[i]==0x3b) // DSRA
2751 emit_shrdimm(sl,sh,imm[i],tl);
2752 if(th>=0) emit_sarimm(sh,imm[i],th);
2756 if(sl!=tl) emit_mov(sl,tl);
2757 if(th>=0&&sh!=th) emit_mov(sh,th);
2763 if(opcode2[i]==0x3c) // DSLL32
2766 signed char sl,tl,th;
2767 tl=get_reg(i_regs->regmap,rt1[i]);
2768 th=get_reg(i_regs->regmap,rt1[i]|64);
2769 sl=get_reg(i_regs->regmap,rs1[i]);
2778 emit_shlimm(th,imm[i]&31,th);
2783 if(opcode2[i]==0x3e) // DSRL32
2786 signed char sh,tl,th;
2787 tl=get_reg(i_regs->regmap,rt1[i]);
2788 th=get_reg(i_regs->regmap,rt1[i]|64);
2789 sh=get_reg(i_regs->regmap,rs1[i]|64);
2793 if(th>=0) emit_zeroreg(th);
2796 emit_shrimm(tl,imm[i]&31,tl);
2801 if(opcode2[i]==0x3f) // DSRA32
2805 tl=get_reg(i_regs->regmap,rt1[i]);
2806 sh=get_reg(i_regs->regmap,rs1[i]|64);
2812 emit_sarimm(tl,imm[i]&31,tl);
2819 #ifndef shift_assemble
2820 void shift_assemble(int i,struct regstat *i_regs)
2822 printf("Need shift_assemble for this architecture.\n");
2827 void load_assemble(int i,struct regstat *i_regs)
2829 int s,th,tl,addr,map=-1;
2832 int memtarget=0,c=0;
2833 int fastload_reg_override=0;
2835 th=get_reg(i_regs->regmap,rt1[i]|64);
2836 tl=get_reg(i_regs->regmap,rt1[i]);
2837 s=get_reg(i_regs->regmap,rs1[i]);
2839 for(hr=0;hr<HOST_REGS;hr++) {
2840 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2842 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2844 c=(i_regs->wasconst>>s)&1;
2846 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2847 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2850 //printf("load_assemble: c=%d\n",c);
2851 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2852 // FIXME: Even if the load is a NOP, we should check for pagefaults...
2854 if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2856 // could be FIFO, must perform the read
2858 assem_debug("(forced read)\n");
2859 tl=get_reg(i_regs->regmap,-1);
2863 if(offset||s<0||c) addr=tl;
2865 //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2867 //printf("load_assemble: c=%d\n",c);
2868 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2869 assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2871 if(th>=0) reglist&=~(1<<th);
2875 map=get_reg(i_regs->regmap,ROREG);
2876 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2878 //#define R29_HACK 1
2880 // Strmnnrmn's speed hack
2881 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2885 if(sp_in_mirror&&rs1[i]==29) {
2886 emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
2887 emit_cmpimm(HOST_TEMPREG,RAM_SIZE);
2888 fastload_reg_override=HOST_TEMPREG;
2892 emit_cmpimm(addr,RAM_SIZE);
2894 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2895 // Hint to branch predictor that the branch is unlikely to be taken
2897 emit_jno_unlikely(0);
2905 if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2906 if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2907 map=get_reg(i_regs->regmap,TLREG);
2910 map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2911 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2913 int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2914 if (opcode[i]==0x20) { // LB
2917 #ifdef HOST_IMM_ADDR32
2919 emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2923 //emit_xorimm(addr,3,tl);
2924 //gen_tlb_addr_r(tl,map);
2925 //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2927 #ifdef BIG_ENDIAN_MIPS
2928 if(!c) emit_xorimm(addr,3,tl);
2929 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2933 if(fastload_reg_override) a=fastload_reg_override;
2935 emit_movsbl_indexed_tlb(x,a,map,tl);
2939 add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2942 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2944 if (opcode[i]==0x21) { // LH
2947 #ifdef HOST_IMM_ADDR32
2949 emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2954 #ifdef BIG_ENDIAN_MIPS
2955 if(!c) emit_xorimm(addr,2,tl);
2956 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2960 if(fastload_reg_override) a=fastload_reg_override;
2962 //emit_movswl_indexed_tlb(x,tl,map,tl);
2965 gen_tlb_addr_r(a,map);
2966 emit_movswl_indexed(x,a,tl);
2969 emit_movswl_indexed(x,a,tl);
2971 emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
2977 add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2980 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2982 if (opcode[i]==0x23) { // LW
2986 if(fastload_reg_override) a=fastload_reg_override;
2987 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2988 #ifdef HOST_IMM_ADDR32
2990 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2993 emit_readword_indexed_tlb(0,a,map,tl);
2996 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2999 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3001 if (opcode[i]==0x24) { // LBU
3004 #ifdef HOST_IMM_ADDR32
3006 emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
3010 //emit_xorimm(addr,3,tl);
3011 //gen_tlb_addr_r(tl,map);
3012 //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
3014 #ifdef BIG_ENDIAN_MIPS
3015 if(!c) emit_xorimm(addr,3,tl);
3016 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3020 if(fastload_reg_override) a=fastload_reg_override;
3022 emit_movzbl_indexed_tlb(x,a,map,tl);
3026 add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3029 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3031 if (opcode[i]==0x25) { // LHU
3034 #ifdef HOST_IMM_ADDR32
3036 emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
3041 #ifdef BIG_ENDIAN_MIPS
3042 if(!c) emit_xorimm(addr,2,tl);
3043 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3047 if(fastload_reg_override) a=fastload_reg_override;
3049 //emit_movzwl_indexed_tlb(x,tl,map,tl);
3052 gen_tlb_addr_r(a,map);
3053 emit_movzwl_indexed(x,a,tl);
3056 emit_movzwl_indexed(x,a,tl);
3058 emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
3064 add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3067 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3069 if (opcode[i]==0x27) { // LWU
3074 if(fastload_reg_override) a=fastload_reg_override;
3075 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
3076 #ifdef HOST_IMM_ADDR32
3078 emit_readword_tlb(constmap[i][s]+offset,map,tl);
3081 emit_readword_indexed_tlb(0,a,map,tl);
3084 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3087 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3091 if (opcode[i]==0x37) { // LD
3095 if(fastload_reg_override) a=fastload_reg_override;
3096 //gen_tlb_addr_r(tl,map);
3097 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
3098 //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
3099 #ifdef HOST_IMM_ADDR32
3101 emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3104 emit_readdword_indexed_tlb(0,a,map,th,tl);
3107 add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3110 inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3113 //emit_storereg(rt1[i],tl); // DEBUG
3114 //if(opcode[i]==0x23)
3115 //if(opcode[i]==0x24)
3116 //if(opcode[i]==0x23||opcode[i]==0x24)
3117 /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
3121 emit_readword((int)&last_count,ECX);
3123 if(get_reg(i_regs->regmap,CCREG)<0)
3124 emit_loadreg(CCREG,HOST_CCREG);
3125 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3126 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3127 emit_writeword(HOST_CCREG,(int)&Count);
3130 if(get_reg(i_regs->regmap,CCREG)<0)
3131 emit_loadreg(CCREG,0);
3133 emit_mov(HOST_CCREG,0);
3135 emit_addimm(0,2*ccadj[i],0);
3136 emit_writeword(0,(int)&Count);
3138 emit_call((int)memdebug);
3140 restore_regs(0x100f);
3144 #ifndef loadlr_assemble
3145 void loadlr_assemble(int i,struct regstat *i_regs)
3147 printf("Need loadlr_assemble for this architecture.\n");
3152 void store_assemble(int i,struct regstat *i_regs)
3157 int jaddr=0,jaddr2,type;
3158 int memtarget=0,c=0;
3159 int agr=AGEN1+(i&1);
3160 int faststore_reg_override=0;
3162 th=get_reg(i_regs->regmap,rs2[i]|64);
3163 tl=get_reg(i_regs->regmap,rs2[i]);
3164 s=get_reg(i_regs->regmap,rs1[i]);
3165 temp=get_reg(i_regs->regmap,agr);
3166 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3169 c=(i_regs->wasconst>>s)&1;
3171 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3172 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3177 for(hr=0;hr<HOST_REGS;hr++) {
3178 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3180 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3181 if(offset||s<0||c) addr=temp;
3186 if(sp_in_mirror&&rs1[i]==29) {
3187 emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
3188 emit_cmpimm(HOST_TEMPREG,RAM_SIZE);
3189 faststore_reg_override=HOST_TEMPREG;
3194 // Strmnnrmn's speed hack
3195 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3197 emit_cmpimm(addr,RAM_SIZE);
3198 #ifdef DESTRUCTIVE_SHIFT
3199 if(s==addr) emit_mov(s,temp);
3203 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3207 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3208 // Hint to branch predictor that the branch is unlikely to be taken
3210 emit_jno_unlikely(0);
3218 if (opcode[i]==0x28) x=3; // SB
3219 if (opcode[i]==0x29) x=2; // SH
3220 map=get_reg(i_regs->regmap,TLREG);
3223 map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3224 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3227 if (opcode[i]==0x28) { // SB
3230 #ifdef BIG_ENDIAN_MIPS
3231 if(!c) emit_xorimm(addr,3,temp);
3232 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3236 if(faststore_reg_override) a=faststore_reg_override;
3237 //gen_tlb_addr_w(temp,map);
3238 //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3239 emit_writebyte_indexed_tlb(tl,x,a,map,a);
3243 if (opcode[i]==0x29) { // SH
3246 #ifdef BIG_ENDIAN_MIPS
3247 if(!c) emit_xorimm(addr,2,temp);
3248 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3252 if(faststore_reg_override) a=faststore_reg_override;
3254 //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3257 gen_tlb_addr_w(a,map);
3258 emit_writehword_indexed(tl,x,a);
3260 emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a);
3264 if (opcode[i]==0x2B) { // SW
3267 if(faststore_reg_override) a=faststore_reg_override;
3268 //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3269 emit_writeword_indexed_tlb(tl,0,a,map,temp);
3273 if (opcode[i]==0x3F) { // SD
3276 if(faststore_reg_override) a=faststore_reg_override;
3279 //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3280 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3281 emit_writedword_indexed_tlb(th,tl,0,a,map,temp);
3284 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3285 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3286 emit_writedword_indexed_tlb(tl,tl,0,a,map,temp);
3293 #ifdef DESTRUCTIVE_SHIFT
3294 // The x86 shift operation is 'destructive'; it overwrites the
3295 // source register, so we need to make a copy first and use that.
3298 #if defined(HOST_IMM8)
3299 int ir=get_reg(i_regs->regmap,INVCP);
3301 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3303 emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3305 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3306 emit_callne(invalidate_addr_reg[addr]);
3310 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3315 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3316 } else if(c&&!memtarget) {
3317 inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3319 //if(opcode[i]==0x2B || opcode[i]==0x3F)
3320 //if(opcode[i]==0x2B || opcode[i]==0x28)
3321 //if(opcode[i]==0x2B || opcode[i]==0x29)
3322 //if(opcode[i]==0x2B)
3323 /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3331 emit_readword((int)&last_count,ECX);
3333 if(get_reg(i_regs->regmap,CCREG)<0)
3334 emit_loadreg(CCREG,HOST_CCREG);
3335 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3336 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3337 emit_writeword(HOST_CCREG,(int)&Count);
3340 if(get_reg(i_regs->regmap,CCREG)<0)
3341 emit_loadreg(CCREG,0);
3343 emit_mov(HOST_CCREG,0);
3345 emit_addimm(0,2*ccadj[i],0);
3346 emit_writeword(0,(int)&Count);
3348 emit_call((int)memdebug);
3353 restore_regs(0x100f);
3358 void storelr_assemble(int i,struct regstat *i_regs)
3365 int case1,case2,case3;
3366 int done0,done1,done2;
3367 int memtarget=0,c=0;
3368 int agr=AGEN1+(i&1);
3370 th=get_reg(i_regs->regmap,rs2[i]|64);
3371 tl=get_reg(i_regs->regmap,rs2[i]);
3372 s=get_reg(i_regs->regmap,rs1[i]);
3373 temp=get_reg(i_regs->regmap,agr);
3374 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3377 c=(i_regs->isconst>>s)&1;
3379 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3380 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3384 for(hr=0;hr<HOST_REGS;hr++) {
3385 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3390 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3391 if(!offset&&s!=temp) emit_mov(s,temp);
3397 if(!memtarget||!rs1[i]) {
3403 int map=get_reg(i_regs->regmap,ROREG);
3404 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3405 gen_tlb_addr_w(temp,map);
3407 if((u_int)rdram!=0x80000000)
3408 emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3411 int map=get_reg(i_regs->regmap,TLREG);
3414 map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3415 if(!c&&!offset&&s>=0) emit_mov(s,temp);
3416 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3417 if(!jaddr&&!memtarget) {
3421 gen_tlb_addr_w(temp,map);
3424 if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3425 temp2=get_reg(i_regs->regmap,FTEMP);
3426 if(!rs2[i]) temp2=th=tl;
3429 #ifndef BIG_ENDIAN_MIPS
3430 emit_xorimm(temp,3,temp);
3432 emit_testimm(temp,2);
3435 emit_testimm(temp,1);
3439 if (opcode[i]==0x2A) { // SWL
3440 emit_writeword_indexed(tl,0,temp);
3442 if (opcode[i]==0x2E) { // SWR
3443 emit_writebyte_indexed(tl,3,temp);
3445 if (opcode[i]==0x2C) { // SDL
3446 emit_writeword_indexed(th,0,temp);
3447 if(rs2[i]) emit_mov(tl,temp2);
3449 if (opcode[i]==0x2D) { // SDR
3450 emit_writebyte_indexed(tl,3,temp);
3451 if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3456 set_jump_target(case1,(int)out);
3457 if (opcode[i]==0x2A) { // SWL
3458 // Write 3 msb into three least significant bytes
3459 if(rs2[i]) emit_rorimm(tl,8,tl);
3460 emit_writehword_indexed(tl,-1,temp);
3461 if(rs2[i]) emit_rorimm(tl,16,tl);
3462 emit_writebyte_indexed(tl,1,temp);
3463 if(rs2[i]) emit_rorimm(tl,8,tl);
3465 if (opcode[i]==0x2E) { // SWR
3466 // Write two lsb into two most significant bytes
3467 emit_writehword_indexed(tl,1,temp);
3469 if (opcode[i]==0x2C) { // SDL
3470 if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3471 // Write 3 msb into three least significant bytes
3472 if(rs2[i]) emit_rorimm(th,8,th);
3473 emit_writehword_indexed(th,-1,temp);
3474 if(rs2[i]) emit_rorimm(th,16,th);
3475 emit_writebyte_indexed(th,1,temp);
3476 if(rs2[i]) emit_rorimm(th,8,th);
3478 if (opcode[i]==0x2D) { // SDR
3479 if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3480 // Write two lsb into two most significant bytes
3481 emit_writehword_indexed(tl,1,temp);
3486 set_jump_target(case2,(int)out);
3487 emit_testimm(temp,1);
3490 if (opcode[i]==0x2A) { // SWL
3491 // Write two msb into two least significant bytes
3492 if(rs2[i]) emit_rorimm(tl,16,tl);
3493 emit_writehword_indexed(tl,-2,temp);
3494 if(rs2[i]) emit_rorimm(tl,16,tl);
3496 if (opcode[i]==0x2E) { // SWR
3497 // Write 3 lsb into three most significant bytes
3498 emit_writebyte_indexed(tl,-1,temp);
3499 if(rs2[i]) emit_rorimm(tl,8,tl);
3500 emit_writehword_indexed(tl,0,temp);
3501 if(rs2[i]) emit_rorimm(tl,24,tl);
3503 if (opcode[i]==0x2C) { // SDL
3504 if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3505 // Write two msb into two least significant bytes
3506 if(rs2[i]) emit_rorimm(th,16,th);
3507 emit_writehword_indexed(th,-2,temp);
3508 if(rs2[i]) emit_rorimm(th,16,th);
3510 if (opcode[i]==0x2D) { // SDR
3511 if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3512 // Write 3 lsb into three most significant bytes
3513 emit_writebyte_indexed(tl,-1,temp);
3514 if(rs2[i]) emit_rorimm(tl,8,tl);
3515 emit_writehword_indexed(tl,0,temp);
3516 if(rs2[i]) emit_rorimm(tl,24,tl);
3521 set_jump_target(case3,(int)out);
3522 if (opcode[i]==0x2A) { // SWL
3523 // Write msb into least significant byte
3524 if(rs2[i]) emit_rorimm(tl,24,tl);
3525 emit_writebyte_indexed(tl,-3,temp);
3526 if(rs2[i]) emit_rorimm(tl,8,tl);
3528 if (opcode[i]==0x2E) { // SWR
3529 // Write entire word
3530 emit_writeword_indexed(tl,-3,temp);
3532 if (opcode[i]==0x2C) { // SDL
3533 if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3534 // Write msb into least significant byte
3535 if(rs2[i]) emit_rorimm(th,24,th);
3536 emit_writebyte_indexed(th,-3,temp);
3537 if(rs2[i]) emit_rorimm(th,8,th);
3539 if (opcode[i]==0x2D) { // SDR
3540 if(rs2[i]) emit_mov(th,temp2);
3541 // Write entire word
3542 emit_writeword_indexed(tl,-3,temp);
3544 set_jump_target(done0,(int)out);
3545 set_jump_target(done1,(int)out);
3546 set_jump_target(done2,(int)out);
3547 if (opcode[i]==0x2C) { // SDL
3548 emit_testimm(temp,4);
3551 emit_andimm(temp,~3,temp);
3552 emit_writeword_indexed(temp2,4,temp);
3553 set_jump_target(done0,(int)out);
3555 if (opcode[i]==0x2D) { // SDR
3556 emit_testimm(temp,4);
3559 emit_andimm(temp,~3,temp);
3560 emit_writeword_indexed(temp2,-4,temp);
3561 set_jump_target(done0,(int)out);
3564 add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
3567 int map=get_reg(i_regs->regmap,ROREG);
3568 if(map<0) map=HOST_TEMPREG;
3569 gen_orig_addr_w(temp,map);
3571 emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
3573 #if defined(HOST_IMM8)
3574 int ir=get_reg(i_regs->regmap,INVCP);
3576 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3578 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3580 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3581 emit_callne(invalidate_addr_reg[temp]);
3585 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3590 //save_regs(0x100f);
3591 emit_readword((int)&last_count,ECX);
3592 if(get_reg(i_regs->regmap,CCREG)<0)
3593 emit_loadreg(CCREG,HOST_CCREG);
3594 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3595 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3596 emit_writeword(HOST_CCREG,(int)&Count);
3597 emit_call((int)memdebug);
3599 //restore_regs(0x100f);
3603 void c1ls_assemble(int i,struct regstat *i_regs)
3605 #ifndef DISABLE_COP1
3611 int jaddr,jaddr2=0,jaddr3,type;
3612 int agr=AGEN1+(i&1);
3614 th=get_reg(i_regs->regmap,FTEMP|64);
3615 tl=get_reg(i_regs->regmap,FTEMP);
3616 s=get_reg(i_regs->regmap,rs1[i]);
3617 temp=get_reg(i_regs->regmap,agr);
3618 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3623 for(hr=0;hr<HOST_REGS;hr++) {
3624 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3626 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3627 if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3629 // Loads use a temporary register which we need to save
3632 if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3636 //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3637 //else c=(i_regs->wasconst>>s)&1;
3638 if(s>=0) c=(i_regs->wasconst>>s)&1;
3639 // Check cop1 unusable
3641 signed char rs=get_reg(i_regs->regmap,CSREG);
3643 emit_testimm(rs,0x20000000);
3646 add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3649 if (opcode[i]==0x39) { // SWC1 (get float address)
3650 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],tl);
3652 if (opcode[i]==0x3D) { // SDC1 (get double address)
3653 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],tl);
3655 // Generate address + offset
3658 emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3662 map=get_reg(i_regs->regmap,TLREG);
3665 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3666 map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
3668 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3669 map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
3672 if (opcode[i]==0x39) { // SWC1 (read float)
3673 emit_readword_indexed(0,tl,tl);
3675 if (opcode[i]==0x3D) { // SDC1 (read double)
3676 emit_readword_indexed(4,tl,th);
3677 emit_readword_indexed(0,tl,tl);
3679 if (opcode[i]==0x31) { // LWC1 (get target address)
3680 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],temp);
3682 if (opcode[i]==0x35) { // LDC1 (get target address)
3683 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],temp);
3690 else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80000000+RAM_SIZE) {
3692 emit_jmp(0); // inline_readstub/inline_writestub? Very rare case
3694 #ifdef DESTRUCTIVE_SHIFT
3695 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3696 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3700 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3701 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3703 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3704 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3707 if (opcode[i]==0x31) { // LWC1
3708 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3709 //gen_tlb_addr_r(ar,map);
3710 //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3711 #ifdef HOST_IMM_ADDR32
3712 if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3715 emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3718 if (opcode[i]==0x35) { // LDC1
3720 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3721 //gen_tlb_addr_r(ar,map);
3722 //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3723 //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3724 #ifdef HOST_IMM_ADDR32
3725 if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3728 emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3731 if (opcode[i]==0x39) { // SWC1
3732 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3733 emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3736 if (opcode[i]==0x3D) { // SDC1
3738 //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3739 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3740 emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3744 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3745 #ifndef DESTRUCTIVE_SHIFT
3746 temp=offset||c||s<0?ar:s;
3748 #if defined(HOST_IMM8)
3749 int ir=get_reg(i_regs->regmap,INVCP);
3751 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3753 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3755 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3756 emit_callne(invalidate_addr_reg[temp]);
3760 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3764 if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3765 if (opcode[i]==0x31) { // LWC1 (write float)
3766 emit_writeword_indexed(tl,0,temp);
3768 if (opcode[i]==0x35) { // LDC1 (write double)
3769 emit_writeword_indexed(th,4,temp);
3770 emit_writeword_indexed(tl,0,temp);
3772 //if(opcode[i]==0x39)
3773 /*if(opcode[i]==0x39||opcode[i]==0x31)
3776 emit_readword((int)&last_count,ECX);
3777 if(get_reg(i_regs->regmap,CCREG)<0)
3778 emit_loadreg(CCREG,HOST_CCREG);
3779 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3780 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3781 emit_writeword(HOST_CCREG,(int)&Count);
3782 emit_call((int)memdebug);
3786 cop1_unusable(i, i_regs);
3790 void c2ls_assemble(int i,struct regstat *i_regs)
3795 int memtarget=0,c=0;
3796 int jaddr2=0,jaddr3,type;
3797 int agr=AGEN1+(i&1);
3799 u_int copr=(source[i]>>16)&0x1f;
3800 s=get_reg(i_regs->regmap,rs1[i]);
3801 tl=get_reg(i_regs->regmap,FTEMP);
3807 for(hr=0;hr<HOST_REGS;hr++) {
3808 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3810 if(i_regs->regmap[HOST_CCREG]==CCREG)
3811 reglist&=~(1<<HOST_CCREG);
3814 if (opcode[i]==0x3a) { // SWC2
3815 ar=get_reg(i_regs->regmap,agr);
3816 if(ar<0) ar=get_reg(i_regs->regmap,-1);
3821 if(s>=0) c=(i_regs->wasconst>>s)&1;
3822 memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
3823 if (!offset&&!c&&s>=0) ar=s;
3826 if (opcode[i]==0x3a) { // SWC2
3827 cop2_get_dreg(copr,tl,HOST_TEMPREG);
3835 emit_jmp(0); // inline_readstub/inline_writestub?
3839 emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3843 if (opcode[i]==0x32) { // LWC2
3844 #ifdef HOST_IMM_ADDR32
3845 if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
3848 emit_readword_indexed(0,ar,tl);
3850 if (opcode[i]==0x3a) { // SWC2
3851 #ifdef DESTRUCTIVE_SHIFT
3852 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3854 emit_writeword_indexed(tl,0,ar);
3858 add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist);
3859 if (opcode[i]==0x3a) { // SWC2
3860 #if defined(HOST_IMM8)
3861 int ir=get_reg(i_regs->regmap,INVCP);
3863 emit_cmpmem_indexedsr12_reg(ir,ar,1);
3865 emit_cmpmem_indexedsr12_imm((int)invalid_code,ar,1);
3867 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3868 emit_callne(invalidate_addr_reg[ar]);
3872 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),ar,0,0,0);
3875 if (opcode[i]==0x32) { // LWC2
3876 cop2_put_dreg(copr,tl,HOST_TEMPREG);
3880 #ifndef multdiv_assemble
3881 void multdiv_assemble(int i,struct regstat *i_regs)
3883 printf("Need multdiv_assemble for this architecture.\n");
3888 void mov_assemble(int i,struct regstat *i_regs)
3890 //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3891 //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
3893 signed char sh,sl,th,tl;
3894 th=get_reg(i_regs->regmap,rt1[i]|64);
3895 tl=get_reg(i_regs->regmap,rt1[i]);
3898 sh=get_reg(i_regs->regmap,rs1[i]|64);
3899 sl=get_reg(i_regs->regmap,rs1[i]);
3900 if(sl>=0) emit_mov(sl,tl);
3901 else emit_loadreg(rs1[i],tl);
3903 if(sh>=0) emit_mov(sh,th);
3904 else emit_loadreg(rs1[i]|64,th);
3910 #ifndef fconv_assemble
3911 void fconv_assemble(int i,struct regstat *i_regs)
3913 printf("Need fconv_assemble for this architecture.\n");
3919 void float_assemble(int i,struct regstat *i_regs)
3921 printf("Need float_assemble for this architecture.\n");
3926 void syscall_assemble(int i,struct regstat *i_regs)
3928 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3929 assert(ccreg==HOST_CCREG);
3930 assert(!is_delayslot);
3931 emit_movimm(start+i*4,EAX); // Get PC
3932 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
3933 emit_jmp((int)jump_syscall_hle); // XXX
3936 void hlecall_assemble(int i,struct regstat *i_regs)
3938 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3939 assert(ccreg==HOST_CCREG);
3940 assert(!is_delayslot);
3941 emit_movimm(start+i*4+4,0); // Get PC
3942 emit_movimm((int)psxHLEt[source[i]&7],1);
3943 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // XXX
3944 emit_jmp((int)jump_hlecall);
3947 void intcall_assemble(int i,struct regstat *i_regs)
3949 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3950 assert(ccreg==HOST_CCREG);
3951 assert(!is_delayslot);
3952 emit_movimm(start+i*4,0); // Get PC
3953 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG);
3954 emit_jmp((int)jump_intcall);
3957 void ds_assemble(int i,struct regstat *i_regs)
3962 alu_assemble(i,i_regs);break;
3964 imm16_assemble(i,i_regs);break;
3966 shift_assemble(i,i_regs);break;
3968 shiftimm_assemble(i,i_regs);break;
3970 load_assemble(i,i_regs);break;
3972 loadlr_assemble(i,i_regs);break;
3974 store_assemble(i,i_regs);break;
3976 storelr_assemble(i,i_regs);break;
3978 cop0_assemble(i,i_regs);break;
3980 cop1_assemble(i,i_regs);break;
3982 c1ls_assemble(i,i_regs);break;
3984 cop2_assemble(i,i_regs);break;
3986 c2ls_assemble(i,i_regs);break;
3988 c2op_assemble(i,i_regs);break;
3990 fconv_assemble(i,i_regs);break;
3992 float_assemble(i,i_regs);break;
3994 fcomp_assemble(i,i_regs);break;
3996 multdiv_assemble(i,i_regs);break;
3998 mov_assemble(i,i_regs);break;
4008 printf("Jump in the delay slot. This is probably a bug.\n");
4013 // Is the branch target a valid internal jump?
4014 int internal_branch(uint64_t i_is32,int addr)
4016 if(addr&1) return 0; // Indirect (register) jump
4017 if(addr>=start && addr<start+slen*4-4)
4019 int t=(addr-start)>>2;
4020 // Delay slots are not valid branch targets
4021 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4022 // 64 -> 32 bit transition requires a recompile
4023 /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
4025 if(requires_32bit[t]&~i_is32) printf("optimizable: no\n");
4026 else printf("optimizable: yes\n");
4028 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4030 if(requires_32bit[t]&~i_is32) return 0;
4038 #ifndef wb_invalidate
4039 void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
4040 uint64_t u,uint64_t uu)
4043 for(hr=0;hr<HOST_REGS;hr++) {
4044 if(hr!=EXCLUDE_REG) {
4045 if(pre[hr]!=entry[hr]) {
4048 if(get_reg(entry,pre[hr])<0) {
4050 if(!((u>>pre[hr])&1)) {
4051 emit_storereg(pre[hr],hr);
4052 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
4053 emit_sarimm(hr,31,hr);
4054 emit_storereg(pre[hr]|64,hr);
4058 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
4059 emit_storereg(pre[hr],hr);
4068 // Move from one register to another (no writeback)
4069 for(hr=0;hr<HOST_REGS;hr++) {
4070 if(hr!=EXCLUDE_REG) {
4071 if(pre[hr]!=entry[hr]) {
4072 if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
4074 if((nr=get_reg(entry,pre[hr]))>=0) {
4084 // Load the specified registers
4085 // This only loads the registers given as arguments because
4086 // we don't want to load things that will be overwritten
4087 void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
4091 for(hr=0;hr<HOST_REGS;hr++) {
4092 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4093 if(entry[hr]!=regmap[hr]) {
4094 if(regmap[hr]==rs1||regmap[hr]==rs2)
4101 emit_loadreg(regmap[hr],hr);
4108 for(hr=0;hr<HOST_REGS;hr++) {
4109 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4110 if(entry[hr]!=regmap[hr]) {
4111 if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
4113 assert(regmap[hr]!=64);
4114 if((is32>>(regmap[hr]&63))&1) {
4115 int lr=get_reg(regmap,regmap[hr]-64);
4117 emit_sarimm(lr,31,hr);
4119 emit_loadreg(regmap[hr],hr);
4123 emit_loadreg(regmap[hr],hr);
4131 // Load registers prior to the start of a loop
4132 // so that they are not loaded within the loop
4133 static void loop_preload(signed char pre[],signed char entry[])
4136 for(hr=0;hr<HOST_REGS;hr++) {
4137 if(hr!=EXCLUDE_REG) {
4138 if(pre[hr]!=entry[hr]) {
4140 if(get_reg(pre,entry[hr])<0) {
4141 assem_debug("loop preload:\n");
4142 //printf("loop preload: %d\n",hr);
4146 else if(entry[hr]<TEMPREG)
4148 emit_loadreg(entry[hr],hr);
4150 else if(entry[hr]-64<TEMPREG)
4152 emit_loadreg(entry[hr],hr);
4161 // Generate address for load/store instruction
4162 // goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
4163 void address_generation(int i,struct regstat *i_regs,signed char entry[])
4165 if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS||itype[i]==C2LS) {
4167 int agr=AGEN1+(i&1);
4168 int mgr=MGEN1+(i&1);
4169 if(itype[i]==LOAD) {
4170 ra=get_reg(i_regs->regmap,rt1[i]);
4171 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4174 if(itype[i]==LOADLR) {
4175 ra=get_reg(i_regs->regmap,FTEMP);
4177 if(itype[i]==STORE||itype[i]==STORELR) {
4178 ra=get_reg(i_regs->regmap,agr);
4179 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4181 if(itype[i]==C1LS||itype[i]==C2LS) {
4182 if ((opcode[i]&0x3b)==0x31||(opcode[i]&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
4183 ra=get_reg(i_regs->regmap,FTEMP);
4184 else { // SWC1/SDC1/SWC2/SDC2
4185 ra=get_reg(i_regs->regmap,agr);
4186 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4189 int rs=get_reg(i_regs->regmap,rs1[i]);
4190 int rm=get_reg(i_regs->regmap,TLREG);
4193 int c=(i_regs->wasconst>>rs)&1;
4195 // Using r0 as a base address
4197 if(!entry||entry[rm]!=mgr) {
4198 generate_map_const(offset,rm);
4199 } // else did it in the previous cycle
4201 if(!entry||entry[ra]!=agr) {
4202 if (opcode[i]==0x22||opcode[i]==0x26) {
4203 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4204 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4205 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4207 emit_movimm(offset,ra);
4209 } // else did it in the previous cycle
4212 if(!entry||entry[ra]!=rs1[i])
4213 emit_loadreg(rs1[i],ra);
4214 //if(!entry||entry[ra]!=rs1[i])
4215 // printf("poor load scheduling!\n");
4219 if(!entry||entry[rm]!=mgr) {
4220 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a) {
4221 // Stores to memory go thru the mapper to detect self-modifying
4222 // code, loads don't.
4223 if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
4224 (unsigned int)(constmap[i][rs]+offset)<0x80000000+RAM_SIZE )
4225 generate_map_const(constmap[i][rs]+offset,rm);
4227 if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
4228 generate_map_const(constmap[i][rs]+offset,rm);
4232 if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
4233 if(!entry||entry[ra]!=agr) {
4234 if (opcode[i]==0x22||opcode[i]==0x26) {
4235 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4236 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4237 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4239 #ifdef HOST_IMM_ADDR32
4240 if((itype[i]!=LOAD&&(opcode[i]&0x3b)!=0x31&&(opcode[i]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4241 (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
4243 emit_movimm(constmap[i][rs]+offset,ra);
4245 } // else did it in the previous cycle
4246 } // else load_consts already did it
4248 if(offset&&!c&&rs1[i]) {
4250 emit_addimm(rs,offset,ra);
4252 emit_addimm(ra,offset,ra);
4257 // Preload constants for next instruction
4258 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
4260 #ifndef HOST_IMM_ADDR32
4262 agr=MGEN1+((i+1)&1);
4263 ra=get_reg(i_regs->regmap,agr);
4265 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4266 int offset=imm[i+1];
4267 int c=(regs[i+1].wasconst>>rs)&1;
4269 if(itype[i+1]==STORE||itype[i+1]==STORELR
4270 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1, SWC2/SDC2
4271 // Stores to memory go thru the mapper to detect self-modifying
4272 // code, loads don't.
4273 if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
4274 (unsigned int)(constmap[i+1][rs]+offset)<0x80000000+RAM_SIZE )
4275 generate_map_const(constmap[i+1][rs]+offset,ra);
4277 if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
4278 generate_map_const(constmap[i+1][rs]+offset,ra);
4281 /*else if(rs1[i]==0) {
4282 generate_map_const(offset,ra);
4287 agr=AGEN1+((i+1)&1);
4288 ra=get_reg(i_regs->regmap,agr);
4290 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4291 int offset=imm[i+1];
4292 int c=(regs[i+1].wasconst>>rs)&1;
4293 if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
4294 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4295 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4296 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4297 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4299 #ifdef HOST_IMM_ADDR32
4300 if((itype[i+1]!=LOAD&&(opcode[i+1]&0x3b)!=0x31&&(opcode[i+1]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4301 (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000))
4303 emit_movimm(constmap[i+1][rs]+offset,ra);
4306 else if(rs1[i+1]==0) {
4307 // Using r0 as a base address
4308 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4309 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4310 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4311 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4313 emit_movimm(offset,ra);
4320 int get_final_value(int hr, int i, int *value)
4322 int reg=regs[i].regmap[hr];
4324 if(regs[i+1].regmap[hr]!=reg) break;
4325 if(!((regs[i+1].isconst>>hr)&1)) break;
4330 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
4331 *value=constmap[i][hr];
4335 if(itype[i+1]==UJUMP||itype[i+1]==RJUMP||itype[i+1]==CJUMP||itype[i+1]==SJUMP) {
4336 // Load in delay slot, out-of-order execution
4337 if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
4339 #ifdef HOST_IMM_ADDR32
4340 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+2])<(signed int)0xC0000000) return 0;
4342 // Precompute load address
4343 *value=constmap[i][hr]+imm[i+2];
4347 if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)
4349 #ifdef HOST_IMM_ADDR32
4350 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+1])<(signed int)0xC0000000) return 0;
4352 // Precompute load address
4353 *value=constmap[i][hr]+imm[i+1];
4354 //printf("c=%x imm=%x\n",(int)constmap[i][hr],imm[i+1]);
4359 *value=constmap[i][hr];
4360 //printf("c=%x\n",(int)constmap[i][hr]);
4361 if(i==slen-1) return 1;
4363 return !((unneeded_reg[i+1]>>reg)&1);
4365 return !((unneeded_reg_upper[i+1]>>reg)&1);
4369 // Load registers with known constants
4370 void load_consts(signed char pre[],signed char regmap[],int is32,int i)
4374 for(hr=0;hr<HOST_REGS;hr++) {
4375 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4376 //if(entry[hr]!=regmap[hr]) {
4377 if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4378 if(((regs[i].isconst>>hr)&1)&®map[hr]<64&®map[hr]>0) {
4380 if(get_final_value(hr,i,&value)) {
4385 emit_movimm(value,hr);
4393 for(hr=0;hr<HOST_REGS;hr++) {
4394 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4395 //if(entry[hr]!=regmap[hr]) {
4396 if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4397 if(((regs[i].isconst>>hr)&1)&®map[hr]>64) {
4398 if((is32>>(regmap[hr]&63))&1) {
4399 int lr=get_reg(regmap,regmap[hr]-64);
4401 emit_sarimm(lr,31,hr);
4406 if(get_final_value(hr,i,&value)) {
4411 emit_movimm(value,hr);
4420 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i)
4424 for(hr=0;hr<HOST_REGS;hr++) {
4425 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) {
4426 if(((regs[i].isconst>>hr)&1)&®map[hr]<64&®map[hr]>0) {
4427 int value=constmap[i][hr];
4432 emit_movimm(value,hr);
4438 for(hr=0;hr<HOST_REGS;hr++) {
4439 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) {
4440 if(((regs[i].isconst>>hr)&1)&®map[hr]>64) {
4441 if((is32>>(regmap[hr]&63))&1) {
4442 int lr=get_reg(regmap,regmap[hr]-64);
4444 emit_sarimm(lr,31,hr);
4448 int value=constmap[i][hr];
4453 emit_movimm(value,hr);
4461 // Write out all dirty registers (except cycle count)
4462 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty)
4465 for(hr=0;hr<HOST_REGS;hr++) {
4466 if(hr!=EXCLUDE_REG) {
4467 if(i_regmap[hr]>0) {
4468 if(i_regmap[hr]!=CCREG) {
4469 if((i_dirty>>hr)&1) {
4470 if(i_regmap[hr]<64) {
4471 emit_storereg(i_regmap[hr],hr);
4473 if( ((i_is32>>i_regmap[hr])&1) ) {
4474 #ifdef DESTRUCTIVE_WRITEBACK
4475 emit_sarimm(hr,31,hr);
4476 emit_storereg(i_regmap[hr]|64,hr);
4478 emit_sarimm(hr,31,HOST_TEMPREG);
4479 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4484 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4485 emit_storereg(i_regmap[hr],hr);
4494 // Write out dirty registers that we need to reload (pair with load_needed_regs)
4495 // This writes the registers not written by store_regs_bt
4496 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4499 int t=(addr-start)>>2;
4500 for(hr=0;hr<HOST_REGS;hr++) {
4501 if(hr!=EXCLUDE_REG) {
4502 if(i_regmap[hr]>0) {
4503 if(i_regmap[hr]!=CCREG) {
4504 if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1) && !(((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4505 if((i_dirty>>hr)&1) {
4506 if(i_regmap[hr]<64) {
4507 emit_storereg(i_regmap[hr],hr);
4509 if( ((i_is32>>i_regmap[hr])&1) ) {
4510 #ifdef DESTRUCTIVE_WRITEBACK
4511 emit_sarimm(hr,31,hr);
4512 emit_storereg(i_regmap[hr]|64,hr);
4514 emit_sarimm(hr,31,HOST_TEMPREG);
4515 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4520 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4521 emit_storereg(i_regmap[hr],hr);
4532 // Load all registers (except cycle count)
4533 void load_all_regs(signed char i_regmap[])
4536 for(hr=0;hr<HOST_REGS;hr++) {
4537 if(hr!=EXCLUDE_REG) {
4538 if(i_regmap[hr]==0) {
4542 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4544 emit_loadreg(i_regmap[hr],hr);
4550 // Load all current registers also needed by next instruction
4551 void load_needed_regs(signed char i_regmap[],signed char next_regmap[])
4554 for(hr=0;hr<HOST_REGS;hr++) {
4555 if(hr!=EXCLUDE_REG) {
4556 if(get_reg(next_regmap,i_regmap[hr])>=0) {
4557 if(i_regmap[hr]==0) {
4561 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4563 emit_loadreg(i_regmap[hr],hr);
4570 // Load all regs, storing cycle count if necessary
4571 void load_regs_entry(int t)
4574 if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER,HOST_CCREG);
4575 else if(ccadj[t]) emit_addimm(HOST_CCREG,-ccadj[t]*CLOCK_DIVIDER,HOST_CCREG);
4576 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4577 emit_storereg(CCREG,HOST_CCREG);
4580 for(hr=0;hr<HOST_REGS;hr++) {
4581 if(regs[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) {
4582 if(regs[t].regmap_entry[hr]==0) {
4585 else if(regs[t].regmap_entry[hr]!=CCREG)
4587 emit_loadreg(regs[t].regmap_entry[hr],hr);
4592 for(hr=0;hr<HOST_REGS;hr++) {
4593 if(regs[t].regmap_entry[hr]>=64&®s[t].regmap_entry[hr]<TEMPREG+64) {
4594 assert(regs[t].regmap_entry[hr]!=64);
4595 if((regs[t].was32>>(regs[t].regmap_entry[hr]&63))&1) {
4596 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4598 emit_loadreg(regs[t].regmap_entry[hr],hr);
4602 emit_sarimm(lr,31,hr);
4607 emit_loadreg(regs[t].regmap_entry[hr],hr);
4613 // Store dirty registers prior to branch
4614 void store_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4616 if(internal_branch(i_is32,addr))
4618 int t=(addr-start)>>2;
4620 for(hr=0;hr<HOST_REGS;hr++) {
4621 if(hr!=EXCLUDE_REG) {
4622 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4623 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4624 if((i_dirty>>hr)&1) {
4625 if(i_regmap[hr]<64) {
4626 if(!((unneeded_reg[t]>>i_regmap[hr])&1)) {
4627 emit_storereg(i_regmap[hr],hr);
4628 if( ((i_is32>>i_regmap[hr])&1) && !((unneeded_reg_upper[t]>>i_regmap[hr])&1) ) {
4629 #ifdef DESTRUCTIVE_WRITEBACK
4630 emit_sarimm(hr,31,hr);
4631 emit_storereg(i_regmap[hr]|64,hr);
4633 emit_sarimm(hr,31,HOST_TEMPREG);
4634 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4639 if( !((i_is32>>(i_regmap[hr]&63))&1) && !((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1) ) {
4640 emit_storereg(i_regmap[hr],hr);
4651 // Branch out of this block, write out all dirty regs
4652 wb_dirtys(i_regmap,i_is32,i_dirty);
4656 // Load all needed registers for branch target
4657 void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4659 //if(addr>=start && addr<(start+slen*4))
4660 if(internal_branch(i_is32,addr))
4662 int t=(addr-start)>>2;
4664 // Store the cycle count before loading something else
4665 if(i_regmap[HOST_CCREG]!=CCREG) {
4666 assert(i_regmap[HOST_CCREG]==-1);
4668 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4669 emit_storereg(CCREG,HOST_CCREG);
4672 for(hr=0;hr<HOST_REGS;hr++) {
4673 if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) {
4674 #ifdef DESTRUCTIVE_WRITEBACK
4675 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || ( !((regs[t].dirty>>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4677 if(i_regmap[hr]!=regs[t].regmap_entry[hr] ) {
4679 if(regs[t].regmap_entry[hr]==0) {
4682 else if(regs[t].regmap_entry[hr]!=CCREG)
4684 emit_loadreg(regs[t].regmap_entry[hr],hr);
4690 for(hr=0;hr<HOST_REGS;hr++) {
4691 if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=64&®s[t].regmap_entry[hr]<TEMPREG+64) {
4692 if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4693 assert(regs[t].regmap_entry[hr]!=64);
4694 if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4695 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4697 emit_loadreg(regs[t].regmap_entry[hr],hr);
4701 emit_sarimm(lr,31,hr);
4706 emit_loadreg(regs[t].regmap_entry[hr],hr);
4709 else if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4710 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4712 emit_sarimm(lr,31,hr);
4719 int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4721 if(addr>=start && addr<start+slen*4-4)
4723 int t=(addr-start)>>2;
4725 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4726 for(hr=0;hr<HOST_REGS;hr++)
4730 if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4732 if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
4739 if(i_regmap[hr]<TEMPREG)
4741 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4744 else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
4746 if(!((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1))
4751 else // Same register but is it 32-bit or dirty?
4754 if(!((regs[t].dirty>>hr)&1))
4758 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4760 //printf("%x: dirty no match\n",addr);
4765 if((((regs[t].was32^i_is32)&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)
4767 //printf("%x: is32 no match\n",addr);
4773 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4775 if(requires_32bit[t]&~i_is32) return 0;
4777 // Delay slots are not valid branch targets
4778 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4779 // Delay slots require additional processing, so do not match
4780 if(is_ds[t]) return 0;
4785 for(hr=0;hr<HOST_REGS;hr++)
4791 if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4805 // Used when a branch jumps into the delay slot of another branch
4806 void ds_assemble_entry(int i)
4808 int t=(ba[i]-start)>>2;
4809 if(!instr_addr[t]) instr_addr[t]=(u_int)out;
4810 assem_debug("Assemble delay slot at %x\n",ba[i]);
4811 assem_debug("<->\n");
4812 if(regs[t].regmap_entry[HOST_CCREG]==CCREG&®s[t].regmap[HOST_CCREG]!=CCREG)
4813 wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty,regs[t].was32);
4814 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,rs1[t],rs2[t]);
4815 address_generation(t,®s[t],regs[t].regmap_entry);
4816 if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39||(opcode[t]&0x3b)==0x3a)
4817 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,INVCP,INVCP);
4822 alu_assemble(t,®s[t]);break;
4824 imm16_assemble(t,®s[t]);break;
4826 shift_assemble(t,®s[t]);break;
4828 shiftimm_assemble(t,®s[t]);break;
4830 load_assemble(t,®s[t]);break;
4832 loadlr_assemble(t,®s[t]);break;
4834 store_assemble(t,®s[t]);break;
4836 storelr_assemble(t,®s[t]);break;
4838 cop0_assemble(t,®s[t]);break;
4840 cop1_assemble(t,®s[t]);break;
4842 c1ls_assemble(t,®s[t]);break;
4844 cop2_assemble(t,®s[t]);break;
4846 c2ls_assemble(t,®s[t]);break;
4848 c2op_assemble(t,®s[t]);break;
4850 fconv_assemble(t,®s[t]);break;
4852 float_assemble(t,®s[t]);break;
4854 fcomp_assemble(t,®s[t]);break;
4856 multdiv_assemble(t,®s[t]);break;
4858 mov_assemble(t,®s[t]);break;
4868 printf("Jump in the delay slot. This is probably a bug.\n");
4870 store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4871 load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4872 if(internal_branch(regs[t].is32,ba[i]+4))
4873 assem_debug("branch: internal\n");
4875 assem_debug("branch: external\n");
4876 assert(internal_branch(regs[t].is32,ba[i]+4));
4877 add_to_linker((int)out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4));
4881 void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
4890 //if(ba[i]>=start && ba[i]<(start+slen*4))
4891 if(internal_branch(branch_regs[i].is32,ba[i]))
4893 int t=(ba[i]-start)>>2;
4894 if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
4902 if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4904 if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
4906 //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4907 emit_andimm(HOST_CCREG,3,HOST_CCREG);
4911 else if(*adj==0||invert) {
4912 emit_addimm_and_set_flags(CLOCK_DIVIDER*(count+2),HOST_CCREG);
4918 emit_cmpimm(HOST_CCREG,-CLOCK_DIVIDER*(count+2));
4922 add_stub(CC_STUB,jaddr,idle?idle:(int)out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
4925 void do_ccstub(int n)
4928 assem_debug("do_ccstub %x\n",start+stubs[n][4]*4);
4929 set_jump_target(stubs[n][1],(int)out);
4931 if(stubs[n][6]==NULLDS) {
4932 // Delay slot instruction is nullified ("likely" branch)
4933 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
4935 else if(stubs[n][6]!=TAKEN) {
4936 wb_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty);
4939 if(internal_branch(branch_regs[i].is32,ba[i]))
4940 wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4944 // Save PC as return address
4945 emit_movimm(stubs[n][5],EAX);
4946 emit_writeword(EAX,(int)&pcaddr);
4950 // Return address depends on which way the branch goes
4951 if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
4953 int s1l=get_reg(branch_regs[i].regmap,rs1[i]);
4954 int s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
4955 int s2l=get_reg(branch_regs[i].regmap,rs2[i]);
4956 int s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
4966 if((branch_regs[i].is32>>rs1[i])&(branch_regs[i].is32>>rs2[i])&1) {
4970 #ifdef DESTRUCTIVE_WRITEBACK
4972 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1)
4973 emit_loadreg(rs1[i],s1l);
4976 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1)
4977 emit_loadreg(rs2[i],s1l);
4980 if((branch_regs[i].dirty>>s2l)&(branch_regs[i].is32>>rs2[i])&1)
4981 emit_loadreg(rs2[i],s2l);
4984 int addr=-1,alt=-1,ntaddr=-1;
4987 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4988 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4989 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4997 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4998 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4999 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5005 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
5009 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5010 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5011 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5017 assert(hr<HOST_REGS);
5019 if((opcode[i]&0x2f)==4) // BEQ
5021 #ifdef HAVE_CMOV_IMM
5023 if(s2l>=0) emit_cmp(s1l,s2l);
5024 else emit_test(s1l,s1l);
5025 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
5030 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5032 if(s2h>=0) emit_cmp(s1h,s2h);
5033 else emit_test(s1h,s1h);
5034 emit_cmovne_reg(alt,addr);
5036 if(s2l>=0) emit_cmp(s1l,s2l);
5037 else emit_test(s1l,s1l);
5038 emit_cmovne_reg(alt,addr);
5041 if((opcode[i]&0x2f)==5) // BNE
5043 #ifdef HAVE_CMOV_IMM
5045 if(s2l>=0) emit_cmp(s1l,s2l);
5046 else emit_test(s1l,s1l);
5047 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
5052 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
5054 if(s2h>=0) emit_cmp(s1h,s2h);
5055 else emit_test(s1h,s1h);
5056 emit_cmovne_reg(alt,addr);
5058 if(s2l>=0) emit_cmp(s1l,s2l);
5059 else emit_test(s1l,s1l);
5060 emit_cmovne_reg(alt,addr);
5063 if((opcode[i]&0x2f)==6) // BLEZ
5065 //emit_movimm(ba[i],alt);
5066 //emit_movimm(start+i*4+8,addr);
5067 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5069 if(s1h>=0) emit_mov(addr,ntaddr);
5070 emit_cmovl_reg(alt,addr);
5073 emit_cmovne_reg(ntaddr,addr);
5074 emit_cmovs_reg(alt,addr);
5077 if((opcode[i]&0x2f)==7) // BGTZ
5079 //emit_movimm(ba[i],addr);
5080 //emit_movimm(start+i*4+8,ntaddr);
5081 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
5083 if(s1h>=0) emit_mov(addr,alt);
5084 emit_cmovl_reg(ntaddr,addr);
5087 emit_cmovne_reg(alt,addr);
5088 emit_cmovs_reg(ntaddr,addr);
5091 if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ
5093 //emit_movimm(ba[i],alt);
5094 //emit_movimm(start+i*4+8,addr);
5095 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5096 if(s1h>=0) emit_test(s1h,s1h);
5097 else emit_test(s1l,s1l);
5098 emit_cmovs_reg(alt,addr);
5100 if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ
5102 //emit_movimm(ba[i],addr);
5103 //emit_movimm(start+i*4+8,alt);
5104 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5105 if(s1h>=0) emit_test(s1h,s1h);
5106 else emit_test(s1l,s1l);
5107 emit_cmovs_reg(alt,addr);
5109 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
5110 if(source[i]&0x10000) // BC1T
5112 //emit_movimm(ba[i],alt);
5113 //emit_movimm(start+i*4+8,addr);
5114 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5115 emit_testimm(s1l,0x800000);
5116 emit_cmovne_reg(alt,addr);
5120 //emit_movimm(ba[i],addr);
5121 //emit_movimm(start+i*4+8,alt);
5122 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5123 emit_testimm(s1l,0x800000);
5124 emit_cmovne_reg(alt,addr);
5127 emit_writeword(addr,(int)&pcaddr);
5132 int r=get_reg(branch_regs[i].regmap,rs1[i]);
5133 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5134 r=get_reg(branch_regs[i].regmap,RTEMP);
5136 emit_writeword(r,(int)&pcaddr);
5138 else {printf("Unknown branch type in do_ccstub\n");exit(1);}
5140 // Update cycle count
5141 assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
5142 if(stubs[n][3]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
5143 emit_call((int)cc_interrupt);
5144 if(stubs[n][3]) emit_addimm(HOST_CCREG,-CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
5145 if(stubs[n][6]==TAKEN) {
5146 if(internal_branch(branch_regs[i].is32,ba[i]))
5147 load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
5148 else if(itype[i]==RJUMP) {
5149 if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
5150 emit_readword((int)&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
5152 emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i]));
5154 }else if(stubs[n][6]==NOTTAKEN) {
5155 if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5156 else load_all_regs(branch_regs[i].regmap);
5157 }else if(stubs[n][6]==NULLDS) {
5158 // Delay slot instruction is nullified ("likely" branch)
5159 if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
5160 else load_all_regs(regs[i].regmap);
5162 load_all_regs(branch_regs[i].regmap);
5164 emit_jmp(stubs[n][2]); // return address
5166 /* This works but uses a lot of memory...
5167 emit_readword((int)&last_count,ECX);
5168 emit_add(HOST_CCREG,ECX,EAX);
5169 emit_writeword(EAX,(int)&Count);
5170 emit_call((int)gen_interupt);
5171 emit_readword((int)&Count,HOST_CCREG);
5172 emit_readword((int)&next_interupt,EAX);
5173 emit_readword((int)&pending_exception,EBX);
5174 emit_writeword(EAX,(int)&last_count);
5175 emit_sub(HOST_CCREG,EAX,HOST_CCREG);
5177 int jne_instr=(int)out;
5179 if(stubs[n][3]) emit_addimm(HOST_CCREG,-2*stubs[n][3],HOST_CCREG);
5180 load_all_regs(branch_regs[i].regmap);
5181 emit_jmp(stubs[n][2]); // return address
5182 set_jump_target(jne_instr,(int)out);
5183 emit_readword((int)&pcaddr,EAX);
5184 // Call get_addr_ht instead of doing the hash table here.
5185 // This code is executed infrequently and takes up a lot of space
5186 // so smaller is better.
5187 emit_storereg(CCREG,HOST_CCREG);
5189 emit_call((int)get_addr_ht);
5190 emit_loadreg(CCREG,HOST_CCREG);
5191 emit_addimm(ESP,4,ESP);
5195 add_to_linker(int addr,int target,int ext)
5197 link_addr[linkcount][0]=addr;
5198 link_addr[linkcount][1]=target;
5199 link_addr[linkcount][2]=ext;
5203 static void ujump_assemble_write_ra(int i)
5206 unsigned int return_address;
5207 rt=get_reg(branch_regs[i].regmap,31);
5208 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5210 return_address=start+i*4+8;
5213 if(internal_branch(branch_regs[i].is32,return_address)&&rt1[i+1]!=31) {
5214 int temp=-1; // note: must be ds-safe
5218 if(temp>=0) do_miniht_insert(return_address,rt,temp);
5219 else emit_movimm(return_address,rt);
5227 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5230 emit_movimm(return_address,rt); // PC into link register
5232 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5238 void ujump_assemble(int i,struct regstat *i_regs)
5240 signed char *i_regmap=i_regs->regmap;
5242 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5243 address_generation(i+1,i_regs,regs[i].regmap_entry);
5245 int temp=get_reg(branch_regs[i].regmap,PTEMP);
5246 if(rt1[i]==31&&temp>=0)
5248 int return_address=start+i*4+8;
5249 if(get_reg(branch_regs[i].regmap,31)>0)
5250 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5253 if(rt1[i]==31&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
5254 ujump_assemble_write_ra(i); // writeback ra for DS
5257 ds_assemble(i+1,i_regs);
5258 uint64_t bc_unneeded=branch_regs[i].u;
5259 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5260 bc_unneeded|=1|(1LL<<rt1[i]);
5261 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5262 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5263 bc_unneeded,bc_unneeded_upper);
5264 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5265 if(!ra_done&&rt1[i]==31)
5266 ujump_assemble_write_ra(i);
5268 cc=get_reg(branch_regs[i].regmap,CCREG);
5269 assert(cc==HOST_CCREG);
5270 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5272 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5274 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5275 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5276 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5277 if(internal_branch(branch_regs[i].is32,ba[i]))
5278 assem_debug("branch: internal\n");
5280 assem_debug("branch: external\n");
5281 if(internal_branch(branch_regs[i].is32,ba[i])&&is_ds[(ba[i]-start)>>2]) {
5282 ds_assemble_entry(i);
5285 add_to_linker((int)out,ba[i],internal_branch(branch_regs[i].is32,ba[i]));
5290 static void rjump_assemble_write_ra(int i)
5292 int rt,return_address;
5293 assert(rt1[i+1]!=rt1[i]);
5294 assert(rt2[i+1]!=rt1[i]);
5295 rt=get_reg(branch_regs[i].regmap,rt1[i]);
5296 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5298 return_address=start+i*4+8;
5302 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5305 emit_movimm(return_address,rt); // PC into link register
5307 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5311 void rjump_assemble(int i,struct regstat *i_regs)
5313 signed char *i_regmap=i_regs->regmap;
5317 rs=get_reg(branch_regs[i].regmap,rs1[i]);
5319 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5320 // Delay slot abuse, make a copy of the branch address register
5321 temp=get_reg(branch_regs[i].regmap,RTEMP);
5323 assert(regs[i].regmap[temp]==RTEMP);
5327 address_generation(i+1,i_regs,regs[i].regmap_entry);
5331 if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5332 int return_address=start+i*4+8;
5333 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5339 int rh=get_reg(regs[i].regmap,RHASH);
5340 if(rh>=0) do_preload_rhash(rh);
5343 if(rt1[i]!=0&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
5344 rjump_assemble_write_ra(i);
5347 ds_assemble(i+1,i_regs);
5348 uint64_t bc_unneeded=branch_regs[i].u;
5349 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5350 bc_unneeded|=1|(1LL<<rt1[i]);
5351 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5352 bc_unneeded&=~(1LL<<rs1[i]);
5353 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5354 bc_unneeded,bc_unneeded_upper);
5355 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
5356 if(!ra_done&&rt1[i]!=0)
5357 rjump_assemble_write_ra(i);
5358 cc=get_reg(branch_regs[i].regmap,CCREG);
5359 assert(cc==HOST_CCREG);
5361 int rh=get_reg(branch_regs[i].regmap,RHASH);
5362 int ht=get_reg(branch_regs[i].regmap,RHTBL);
5364 if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5365 do_preload_rhtbl(ht);
5369 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5370 #ifdef DESTRUCTIVE_WRITEBACK
5371 if((branch_regs[i].dirty>>rs)&(branch_regs[i].is32>>rs1[i])&1) {
5372 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
5373 emit_loadreg(rs1[i],rs);
5378 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5382 do_miniht_load(ht,rh);
5385 //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5386 //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5388 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5389 add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
5391 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5394 do_miniht_jump(rs,rh,ht);
5399 //if(rs!=EAX) emit_mov(rs,EAX);
5400 //emit_jmp((int)jump_vaddr_eax);
5401 emit_jmp(jump_vaddr_reg[rs]);
5406 emit_shrimm(rs,16,rs);
5407 emit_xor(temp,rs,rs);
5408 emit_movzwl_reg(rs,rs);
5409 emit_shlimm(rs,4,rs);
5410 emit_cmpmem_indexed((int)hash_table,rs,temp);
5411 emit_jne((int)out+14);
5412 emit_readword_indexed((int)hash_table+4,rs,rs);
5414 emit_cmpmem_indexed((int)hash_table+8,rs,temp);
5415 emit_addimm_no_flags(8,rs);
5416 emit_jeq((int)out-17);
5417 // No hit on hash table, call compiler
5420 #ifdef DEBUG_CYCLE_COUNT
5421 emit_readword((int)&last_count,ECX);
5422 emit_add(HOST_CCREG,ECX,HOST_CCREG);
5423 emit_readword((int)&next_interupt,ECX);
5424 emit_writeword(HOST_CCREG,(int)&Count);
5425 emit_sub(HOST_CCREG,ECX,HOST_CCREG);
5426 emit_writeword(ECX,(int)&last_count);
5429 emit_storereg(CCREG,HOST_CCREG);
5430 emit_call((int)get_addr);
5431 emit_loadreg(CCREG,HOST_CCREG);
5432 emit_addimm(ESP,4,ESP);
5434 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5435 if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5439 void cjump_assemble(int i,struct regstat *i_regs)
5441 signed char *i_regmap=i_regs->regmap;
5444 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5445 assem_debug("match=%d\n",match);
5446 int s1h,s1l,s2h,s2l;
5447 int prev_cop1_usable=cop1_usable;
5448 int unconditional=0,nop=0;
5451 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5452 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5453 if(!match) invert=1;
5454 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5455 if(i>(ba[i]-start)>>2) invert=1;
5459 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5460 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5461 s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5462 s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5465 s1l=get_reg(i_regmap,rs1[i]);
5466 s1h=get_reg(i_regmap,rs1[i]|64);
5467 s2l=get_reg(i_regmap,rs2[i]);
5468 s2h=get_reg(i_regmap,rs2[i]|64);
5470 if(rs1[i]==0&&rs2[i]==0)
5472 if(opcode[i]&1) nop=1;
5473 else unconditional=1;
5474 //assert(opcode[i]!=5);
5475 //assert(opcode[i]!=7);
5476 //assert(opcode[i]!=0x15);
5477 //assert(opcode[i]!=0x17);
5483 only32=(regs[i].was32>>rs2[i])&1;
5488 only32=(regs[i].was32>>rs1[i])&1;
5491 only32=(regs[i].was32>>rs1[i])&(regs[i].was32>>rs2[i])&1;
5495 // Out of order execution (delay slot first)
5497 address_generation(i+1,i_regs,regs[i].regmap_entry);
5498 ds_assemble(i+1,i_regs);
5500 uint64_t bc_unneeded=branch_regs[i].u;
5501 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5502 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5503 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5505 bc_unneeded_upper|=1;
5506 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5507 bc_unneeded,bc_unneeded_upper);
5508 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
5509 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5510 cc=get_reg(branch_regs[i].regmap,CCREG);
5511 assert(cc==HOST_CCREG);
5513 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5514 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5515 //assem_debug("cycle count (adj)\n");
5517 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5518 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5519 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5520 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5522 assem_debug("branch: internal\n");
5524 assem_debug("branch: external\n");
5525 if(internal&&is_ds[(ba[i]-start)>>2]) {
5526 ds_assemble_entry(i);
5529 add_to_linker((int)out,ba[i],internal);
5532 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5533 if(((u_int)out)&7) emit_addnop(0);
5538 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5541 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5544 int taken=0,nottaken=0,nottaken1=0;
5545 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5546 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5550 if(opcode[i]==4) // BEQ
5552 if(s2h>=0) emit_cmp(s1h,s2h);
5553 else emit_test(s1h,s1h);
5557 if(opcode[i]==5) // BNE
5559 if(s2h>=0) emit_cmp(s1h,s2h);
5560 else emit_test(s1h,s1h);
5561 if(invert) taken=(int)out;
5562 else add_to_linker((int)out,ba[i],internal);
5565 if(opcode[i]==6) // BLEZ
5568 if(invert) taken=(int)out;
5569 else add_to_linker((int)out,ba[i],internal);
5574 if(opcode[i]==7) // BGTZ
5579 if(invert) taken=(int)out;
5580 else add_to_linker((int)out,ba[i],internal);
5585 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5587 if(opcode[i]==4) // BEQ
5589 if(s2l>=0) emit_cmp(s1l,s2l);
5590 else emit_test(s1l,s1l);
5595 add_to_linker((int)out,ba[i],internal);
5599 if(opcode[i]==5) // BNE
5601 if(s2l>=0) emit_cmp(s1l,s2l);
5602 else emit_test(s1l,s1l);
5607 add_to_linker((int)out,ba[i],internal);
5611 if(opcode[i]==6) // BLEZ
5618 add_to_linker((int)out,ba[i],internal);
5622 if(opcode[i]==7) // BGTZ
5629 add_to_linker((int)out,ba[i],internal);
5634 if(taken) set_jump_target(taken,(int)out);
5635 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5636 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5638 emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5639 add_to_linker((int)out,ba[i],internal);
5642 add_to_linker((int)out,ba[i],internal*2);
5648 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5649 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5650 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5652 assem_debug("branch: internal\n");
5654 assem_debug("branch: external\n");
5655 if(internal&&is_ds[(ba[i]-start)>>2]) {
5656 ds_assemble_entry(i);
5659 add_to_linker((int)out,ba[i],internal);
5663 set_jump_target(nottaken,(int)out);
5666 if(nottaken1) set_jump_target(nottaken1,(int)out);
5668 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5670 } // (!unconditional)
5674 // In-order execution (branch first)
5675 //if(likely[i]) printf("IOL\n");
5678 int taken=0,nottaken=0,nottaken1=0;
5679 if(!unconditional&&!nop) {
5683 if((opcode[i]&0x2f)==4) // BEQ
5685 if(s2h>=0) emit_cmp(s1h,s2h);
5686 else emit_test(s1h,s1h);
5690 if((opcode[i]&0x2f)==5) // BNE
5692 if(s2h>=0) emit_cmp(s1h,s2h);
5693 else emit_test(s1h,s1h);
5697 if((opcode[i]&0x2f)==6) // BLEZ
5705 if((opcode[i]&0x2f)==7) // BGTZ
5715 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5717 if((opcode[i]&0x2f)==4) // BEQ
5719 if(s2l>=0) emit_cmp(s1l,s2l);
5720 else emit_test(s1l,s1l);
5724 if((opcode[i]&0x2f)==5) // BNE
5726 if(s2l>=0) emit_cmp(s1l,s2l);
5727 else emit_test(s1l,s1l);
5731 if((opcode[i]&0x2f)==6) // BLEZ
5737 if((opcode[i]&0x2f)==7) // BGTZ
5743 } // if(!unconditional)
5745 uint64_t ds_unneeded=branch_regs[i].u;
5746 uint64_t ds_unneeded_upper=branch_regs[i].uu;
5747 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5748 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5749 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5751 ds_unneeded_upper|=1;
5754 if(taken) set_jump_target(taken,(int)out);
5755 assem_debug("1:\n");
5756 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5757 ds_unneeded,ds_unneeded_upper);
5759 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5760 address_generation(i+1,&branch_regs[i],0);
5761 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5762 ds_assemble(i+1,&branch_regs[i]);
5763 cc=get_reg(branch_regs[i].regmap,CCREG);
5765 emit_loadreg(CCREG,cc=HOST_CCREG);
5766 // CHECK: Is the following instruction (fall thru) allocated ok?
5768 assert(cc==HOST_CCREG);
5769 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5770 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5771 assem_debug("cycle count (adj)\n");
5772 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5773 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5775 assem_debug("branch: internal\n");
5777 assem_debug("branch: external\n");
5778 if(internal&&is_ds[(ba[i]-start)>>2]) {
5779 ds_assemble_entry(i);
5782 add_to_linker((int)out,ba[i],internal);
5787 cop1_usable=prev_cop1_usable;
5788 if(!unconditional) {
5789 if(nottaken1) set_jump_target(nottaken1,(int)out);
5790 set_jump_target(nottaken,(int)out);
5791 assem_debug("2:\n");
5793 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5794 ds_unneeded,ds_unneeded_upper);
5795 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5796 address_generation(i+1,&branch_regs[i],0);
5797 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5798 ds_assemble(i+1,&branch_regs[i]);
5800 cc=get_reg(branch_regs[i].regmap,CCREG);
5801 if(cc==-1&&!likely[i]) {
5802 // Cycle count isn't in a register, temporarily load it then write it out
5803 emit_loadreg(CCREG,HOST_CCREG);
5804 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5807 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5808 emit_storereg(CCREG,HOST_CCREG);
5811 cc=get_reg(i_regmap,CCREG);
5812 assert(cc==HOST_CCREG);
5813 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5816 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5822 void sjump_assemble(int i,struct regstat *i_regs)
5824 signed char *i_regmap=i_regs->regmap;
5827 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5828 assem_debug("smatch=%d\n",match);
5830 int prev_cop1_usable=cop1_usable;
5831 int unconditional=0,nevertaken=0;
5834 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5835 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5836 if(!match) invert=1;
5837 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5838 if(i>(ba[i]-start)>>2) invert=1;
5841 //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
5842 //assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
5845 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5846 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5849 s1l=get_reg(i_regmap,rs1[i]);
5850 s1h=get_reg(i_regmap,rs1[i]|64);
5854 if(opcode2[i]&1) unconditional=1;
5856 // These are never taken (r0 is never less than zero)
5857 //assert(opcode2[i]!=0);
5858 //assert(opcode2[i]!=2);
5859 //assert(opcode2[i]!=0x10);
5860 //assert(opcode2[i]!=0x12);
5863 only32=(regs[i].was32>>rs1[i])&1;
5867 // Out of order execution (delay slot first)
5869 address_generation(i+1,i_regs,regs[i].regmap_entry);
5870 ds_assemble(i+1,i_regs);
5872 uint64_t bc_unneeded=branch_regs[i].u;
5873 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5874 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5875 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5877 bc_unneeded_upper|=1;
5878 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5879 bc_unneeded,bc_unneeded_upper);
5880 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5881 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5883 int rt,return_address;
5884 rt=get_reg(branch_regs[i].regmap,31);
5885 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5887 // Save the PC even if the branch is not taken
5888 return_address=start+i*4+8;
5889 emit_movimm(return_address,rt); // PC into link register
5891 if(!nevertaken) emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5895 cc=get_reg(branch_regs[i].regmap,CCREG);
5896 assert(cc==HOST_CCREG);
5898 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5899 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5900 assem_debug("cycle count (adj)\n");
5902 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5903 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5904 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5905 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5907 assem_debug("branch: internal\n");
5909 assem_debug("branch: external\n");
5910 if(internal&&is_ds[(ba[i]-start)>>2]) {
5911 ds_assemble_entry(i);
5914 add_to_linker((int)out,ba[i],internal);
5917 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5918 if(((u_int)out)&7) emit_addnop(0);
5922 else if(nevertaken) {
5923 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5926 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5930 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5931 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5935 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
5942 add_to_linker((int)out,ba[i],internal);
5946 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
5953 add_to_linker((int)out,ba[i],internal);
5961 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
5968 add_to_linker((int)out,ba[i],internal);
5972 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
5979 add_to_linker((int)out,ba[i],internal);
5986 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5987 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5989 emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5990 add_to_linker((int)out,ba[i],internal);
5993 add_to_linker((int)out,ba[i],internal*2);
5999 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
6000 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6001 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6003 assem_debug("branch: internal\n");
6005 assem_debug("branch: external\n");
6006 if(internal&&is_ds[(ba[i]-start)>>2]) {
6007 ds_assemble_entry(i);
6010 add_to_linker((int)out,ba[i],internal);
6014 set_jump_target(nottaken,(int)out);
6018 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
6020 } // (!unconditional)
6024 // In-order execution (branch first)
6028 int rt,return_address;
6029 rt=get_reg(branch_regs[i].regmap,31);
6031 // Save the PC even if the branch is not taken
6032 return_address=start+i*4+8;
6033 emit_movimm(return_address,rt); // PC into link register
6035 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
6039 if(!unconditional) {
6040 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6044 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
6050 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
6060 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
6066 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
6073 } // if(!unconditional)
6075 uint64_t ds_unneeded=branch_regs[i].u;
6076 uint64_t ds_unneeded_upper=branch_regs[i].uu;
6077 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6078 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6079 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6081 ds_unneeded_upper|=1;
6084 //assem_debug("1:\n");
6085 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6086 ds_unneeded,ds_unneeded_upper);
6088 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6089 address_generation(i+1,&branch_regs[i],0);
6090 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6091 ds_assemble(i+1,&branch_regs[i]);
6092 cc=get_reg(branch_regs[i].regmap,CCREG);
6094 emit_loadreg(CCREG,cc=HOST_CCREG);
6095 // CHECK: Is the following instruction (fall thru) allocated ok?
6097 assert(cc==HOST_CCREG);
6098 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6099 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6100 assem_debug("cycle count (adj)\n");
6101 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6102 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6104 assem_debug("branch: internal\n");
6106 assem_debug("branch: external\n");
6107 if(internal&&is_ds[(ba[i]-start)>>2]) {
6108 ds_assemble_entry(i);
6111 add_to_linker((int)out,ba[i],internal);
6116 cop1_usable=prev_cop1_usable;
6117 if(!unconditional) {
6118 set_jump_target(nottaken,(int)out);
6119 assem_debug("1:\n");
6121 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6122 ds_unneeded,ds_unneeded_upper);
6123 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6124 address_generation(i+1,&branch_regs[i],0);
6125 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6126 ds_assemble(i+1,&branch_regs[i]);
6128 cc=get_reg(branch_regs[i].regmap,CCREG);
6129 if(cc==-1&&!likely[i]) {
6130 // Cycle count isn't in a register, temporarily load it then write it out
6131 emit_loadreg(CCREG,HOST_CCREG);
6132 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6135 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6136 emit_storereg(CCREG,HOST_CCREG);
6139 cc=get_reg(i_regmap,CCREG);
6140 assert(cc==HOST_CCREG);
6141 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
6144 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6150 void fjump_assemble(int i,struct regstat *i_regs)
6152 signed char *i_regmap=i_regs->regmap;
6155 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6156 assem_debug("fmatch=%d\n",match);
6160 int internal=internal_branch(branch_regs[i].is32,ba[i]);
6161 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
6162 if(!match) invert=1;
6163 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6164 if(i>(ba[i]-start)>>2) invert=1;
6168 fs=get_reg(branch_regs[i].regmap,FSREG);
6169 address_generation(i+1,i_regs,regs[i].regmap_entry); // Is this okay?
6172 fs=get_reg(i_regmap,FSREG);
6175 // Check cop1 unusable
6177 cs=get_reg(i_regmap,CSREG);
6179 emit_testimm(cs,0x20000000);
6182 add_stub(FP_STUB,eaddr,(int)out,i,cs,(int)i_regs,0,0);
6187 // Out of order execution (delay slot first)
6189 ds_assemble(i+1,i_regs);
6191 uint64_t bc_unneeded=branch_regs[i].u;
6192 uint64_t bc_unneeded_upper=branch_regs[i].uu;
6193 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6194 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
6196 bc_unneeded_upper|=1;
6197 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6198 bc_unneeded,bc_unneeded_upper);
6199 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
6200 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6201 cc=get_reg(branch_regs[i].regmap,CCREG);
6202 assert(cc==HOST_CCREG);
6203 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
6204 assem_debug("cycle count (adj)\n");
6207 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6210 emit_testimm(fs,0x800000);
6211 if(source[i]&0x10000) // BC1T
6217 add_to_linker((int)out,ba[i],internal);
6226 add_to_linker((int)out,ba[i],internal);
6234 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
6235 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6236 else if(match) emit_addnop(13);
6238 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6239 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6241 assem_debug("branch: internal\n");
6243 assem_debug("branch: external\n");
6244 if(internal&&is_ds[(ba[i]-start)>>2]) {
6245 ds_assemble_entry(i);
6248 add_to_linker((int)out,ba[i],internal);
6251 set_jump_target(nottaken,(int)out);
6255 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
6257 } // (!unconditional)
6261 // In-order execution (branch first)
6265 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6268 emit_testimm(fs,0x800000);
6269 if(source[i]&0x10000) // BC1T
6280 } // if(!unconditional)
6282 uint64_t ds_unneeded=branch_regs[i].u;
6283 uint64_t ds_unneeded_upper=branch_regs[i].uu;
6284 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6285 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6286 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6288 ds_unneeded_upper|=1;
6290 //assem_debug("1:\n");
6291 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6292 ds_unneeded,ds_unneeded_upper);
6294 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6295 address_generation(i+1,&branch_regs[i],0);
6296 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6297 ds_assemble(i+1,&branch_regs[i]);
6298 cc=get_reg(branch_regs[i].regmap,CCREG);
6300 emit_loadreg(CCREG,cc=HOST_CCREG);
6301 // CHECK: Is the following instruction (fall thru) allocated ok?
6303 assert(cc==HOST_CCREG);
6304 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6305 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6306 assem_debug("cycle count (adj)\n");
6307 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6308 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6310 assem_debug("branch: internal\n");
6312 assem_debug("branch: external\n");
6313 if(internal&&is_ds[(ba[i]-start)>>2]) {
6314 ds_assemble_entry(i);
6317 add_to_linker((int)out,ba[i],internal);
6322 if(1) { // <- FIXME (don't need this)
6323 set_jump_target(nottaken,(int)out);
6324 assem_debug("1:\n");
6326 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6327 ds_unneeded,ds_unneeded_upper);
6328 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6329 address_generation(i+1,&branch_regs[i],0);
6330 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6331 ds_assemble(i+1,&branch_regs[i]);
6333 cc=get_reg(branch_regs[i].regmap,CCREG);
6334 if(cc==-1&&!likely[i]) {
6335 // Cycle count isn't in a register, temporarily load it then write it out
6336 emit_loadreg(CCREG,HOST_CCREG);
6337 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6340 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6341 emit_storereg(CCREG,HOST_CCREG);
6344 cc=get_reg(i_regmap,CCREG);
6345 assert(cc==HOST_CCREG);
6346 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
6349 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6355 static void pagespan_assemble(int i,struct regstat *i_regs)
6357 int s1l=get_reg(i_regs->regmap,rs1[i]);
6358 int s1h=get_reg(i_regs->regmap,rs1[i]|64);
6359 int s2l=get_reg(i_regs->regmap,rs2[i]);
6360 int s2h=get_reg(i_regs->regmap,rs2[i]|64);
6361 void *nt_branch=NULL;
6364 int unconditional=0;
6374 if((i_regs->is32>>rs1[i])&(i_regs->is32>>rs2[i])&1) {
6378 int addr,alt,ntaddr;
6379 if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
6383 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
6384 (i_regs->regmap[hr]&63)!=rs1[i] &&
6385 (i_regs->regmap[hr]&63)!=rs2[i] )
6394 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6395 (i_regs->regmap[hr]&63)!=rs1[i] &&
6396 (i_regs->regmap[hr]&63)!=rs2[i] )
6402 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
6406 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6407 (i_regs->regmap[hr]&63)!=rs1[i] &&
6408 (i_regs->regmap[hr]&63)!=rs2[i] )
6415 assert(hr<HOST_REGS);
6416 if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
6417 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
6419 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6420 if(opcode[i]==2) // J
6424 if(opcode[i]==3) // JAL
6427 int rt=get_reg(i_regs->regmap,31);
6428 emit_movimm(start+i*4+8,rt);
6431 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
6434 if(opcode2[i]==9) // JALR
6436 int rt=get_reg(i_regs->regmap,rt1[i]);
6437 emit_movimm(start+i*4+8,rt);
6440 if((opcode[i]&0x3f)==4) // BEQ
6447 #ifdef HAVE_CMOV_IMM
6449 if(s2l>=0) emit_cmp(s1l,s2l);
6450 else emit_test(s1l,s1l);
6451 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
6457 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6459 if(s2h>=0) emit_cmp(s1h,s2h);
6460 else emit_test(s1h,s1h);
6461 emit_cmovne_reg(alt,addr);
6463 if(s2l>=0) emit_cmp(s1l,s2l);
6464 else emit_test(s1l,s1l);
6465 emit_cmovne_reg(alt,addr);
6468 if((opcode[i]&0x3f)==5) // BNE
6470 #ifdef HAVE_CMOV_IMM
6472 if(s2l>=0) emit_cmp(s1l,s2l);
6473 else emit_test(s1l,s1l);
6474 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
6480 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
6482 if(s2h>=0) emit_cmp(s1h,s2h);
6483 else emit_test(s1h,s1h);
6484 emit_cmovne_reg(alt,addr);
6486 if(s2l>=0) emit_cmp(s1l,s2l);
6487 else emit_test(s1l,s1l);
6488 emit_cmovne_reg(alt,addr);
6491 if((opcode[i]&0x3f)==0x14) // BEQL
6494 if(s2h>=0) emit_cmp(s1h,s2h);
6495 else emit_test(s1h,s1h);
6499 if(s2l>=0) emit_cmp(s1l,s2l);
6500 else emit_test(s1l,s1l);
6501 if(nottaken) set_jump_target(nottaken,(int)out);
6505 if((opcode[i]&0x3f)==0x15) // BNEL
6508 if(s2h>=0) emit_cmp(s1h,s2h);
6509 else emit_test(s1h,s1h);
6513 if(s2l>=0) emit_cmp(s1l,s2l);
6514 else emit_test(s1l,s1l);
6517 if(taken) set_jump_target(taken,(int)out);
6519 if((opcode[i]&0x3f)==6) // BLEZ
6521 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6523 if(s1h>=0) emit_mov(addr,ntaddr);
6524 emit_cmovl_reg(alt,addr);
6527 emit_cmovne_reg(ntaddr,addr);
6528 emit_cmovs_reg(alt,addr);
6531 if((opcode[i]&0x3f)==7) // BGTZ
6533 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
6535 if(s1h>=0) emit_mov(addr,alt);
6536 emit_cmovl_reg(ntaddr,addr);
6539 emit_cmovne_reg(alt,addr);
6540 emit_cmovs_reg(ntaddr,addr);
6543 if((opcode[i]&0x3f)==0x16) // BLEZL
6545 assert((opcode[i]&0x3f)!=0x16);
6547 if((opcode[i]&0x3f)==0x17) // BGTZL
6549 assert((opcode[i]&0x3f)!=0x17);
6551 assert(opcode[i]!=1); // BLTZ/BGEZ
6553 //FIXME: Check CSREG
6554 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
6555 if((source[i]&0x30000)==0) // BC1F
6557 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6558 emit_testimm(s1l,0x800000);
6559 emit_cmovne_reg(alt,addr);
6561 if((source[i]&0x30000)==0x10000) // BC1T
6563 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6564 emit_testimm(s1l,0x800000);
6565 emit_cmovne_reg(alt,addr);
6567 if((source[i]&0x30000)==0x20000) // BC1FL
6569 emit_testimm(s1l,0x800000);
6573 if((source[i]&0x30000)==0x30000) // BC1TL
6575 emit_testimm(s1l,0x800000);
6581 assert(i_regs->regmap[HOST_CCREG]==CCREG);
6582 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6583 if(likely[i]||unconditional)
6585 emit_movimm(ba[i],HOST_BTREG);
6587 else if(addr!=HOST_BTREG)
6589 emit_mov(addr,HOST_BTREG);
6591 void *branch_addr=out;
6593 int target_addr=start+i*4+5;
6595 void *compiled_target_addr=check_addr(target_addr);
6596 emit_extjump_ds((int)branch_addr,target_addr);
6597 if(compiled_target_addr) {
6598 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6599 add_link(target_addr,stub);
6601 else set_jump_target((int)branch_addr,(int)stub);
6604 set_jump_target((int)nottaken,(int)out);
6605 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6606 void *branch_addr=out;
6608 int target_addr=start+i*4+8;
6610 void *compiled_target_addr=check_addr(target_addr);
6611 emit_extjump_ds((int)branch_addr,target_addr);
6612 if(compiled_target_addr) {
6613 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6614 add_link(target_addr,stub);
6616 else set_jump_target((int)branch_addr,(int)stub);
6620 // Assemble the delay slot for the above
6621 static void pagespan_ds()
6623 assem_debug("initial delay slot:\n");
6624 u_int vaddr=start+1;
6625 u_int page=get_page(vaddr);
6626 u_int vpage=get_vpage(vaddr);
6627 ll_add(jump_dirty+vpage,vaddr,(void *)out);
6629 ll_add(jump_in+page,vaddr,(void *)out);
6630 assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6631 if(regs[0].regmap[HOST_CCREG]!=CCREG)
6632 wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty,regs[0].was32);
6633 if(regs[0].regmap[HOST_BTREG]!=BTREG)
6634 emit_writeword(HOST_BTREG,(int)&branch_target);
6635 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,rs1[0],rs2[0]);
6636 address_generation(0,®s[0],regs[0].regmap_entry);
6637 if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39||(opcode[0]&0x3b)==0x3a)
6638 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,INVCP,INVCP);
6643 alu_assemble(0,®s[0]);break;
6645 imm16_assemble(0,®s[0]);break;
6647 shift_assemble(0,®s[0]);break;
6649 shiftimm_assemble(0,®s[0]);break;
6651 load_assemble(0,®s[0]);break;
6653 loadlr_assemble(0,®s[0]);break;
6655 store_assemble(0,®s[0]);break;
6657 storelr_assemble(0,®s[0]);break;
6659 cop0_assemble(0,®s[0]);break;
6661 cop1_assemble(0,®s[0]);break;
6663 c1ls_assemble(0,®s[0]);break;
6665 cop2_assemble(0,®s[0]);break;
6667 c2ls_assemble(0,®s[0]);break;
6669 c2op_assemble(0,®s[0]);break;
6671 fconv_assemble(0,®s[0]);break;
6673 float_assemble(0,®s[0]);break;
6675 fcomp_assemble(0,®s[0]);break;
6677 multdiv_assemble(0,®s[0]);break;
6679 mov_assemble(0,®s[0]);break;
6689 printf("Jump in the delay slot. This is probably a bug.\n");
6691 int btaddr=get_reg(regs[0].regmap,BTREG);
6693 btaddr=get_reg(regs[0].regmap,-1);
6694 emit_readword((int)&branch_target,btaddr);
6696 assert(btaddr!=HOST_CCREG);
6697 if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6699 emit_movimm(start+4,HOST_TEMPREG);
6700 emit_cmp(btaddr,HOST_TEMPREG);
6702 emit_cmpimm(btaddr,start+4);
6704 int branch=(int)out;
6706 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,-1);
6707 emit_jmp(jump_vaddr_reg[btaddr]);
6708 set_jump_target(branch,(int)out);
6709 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6710 load_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6713 // Basic liveness analysis for MIPS registers
6714 void unneeded_registers(int istart,int iend,int r)
6717 uint64_t u,uu,gte_u,b,bu,gte_bu;
6718 uint64_t temp_u,temp_uu,temp_gte_u;
6723 u=unneeded_reg[iend+1];
6724 uu=unneeded_reg_upper[iend+1];
6729 for (i=iend;i>=istart;i--)
6731 //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
6732 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6734 // If subroutine call, flag return address as a possible branch target
6735 if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
6737 if(ba[i]<start || ba[i]>=(start+slen*4))
6739 // Branch out of this block, flush all regs
6744 if(itype[i]==UJUMP&&rt1[i]==31)
6746 uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
6748 if(itype[i]==RJUMP&&rs1[i]==31)
6750 uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9
6752 if(start>0x80000400&&start<0x80000000+RAM_SIZE) {
6753 if(itype[i]==UJUMP&&rt1[i]==31)
6755 //uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi
6756 uu=u=0x300FF0F; // Discard at, v0-v1, t0-t9
6758 if(itype[i]==RJUMP&&rs1[i]==31)
6760 //uu=u=0x30300FFF3LL; // Discard at, a0-a3, t0-t9, lo, hi
6761 uu=u=0x300FFF3; // Discard at, a0-a3, t0-t9
6764 branch_unneeded_reg[i]=u;
6765 branch_unneeded_reg_upper[i]=uu;
6766 // Merge in delay slot
6767 tdep=(~uu>>rt1[i+1])&1;
6768 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6769 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6770 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6771 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6772 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6775 gte_u&=~gte_rs[i+1];
6776 // If branch is "likely" (and conditional)
6777 // then we skip the delay slot on the fall-thru path
6780 u&=unneeded_reg[i+2];
6781 uu&=unneeded_reg_upper[i+2];
6782 gte_u&=gte_unneeded[i+2];
6794 // Internal branch, flag target
6795 bt[(ba[i]-start)>>2]=1;
6796 if(ba[i]<=start+i*4) {
6798 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6800 // Unconditional branch
6804 // Conditional branch (not taken case)
6805 temp_u=unneeded_reg[i+2];
6806 temp_uu=unneeded_reg_upper[i+2];
6807 temp_gte_u&=gte_unneeded[i+2];
6809 // Merge in delay slot
6810 tdep=(~temp_uu>>rt1[i+1])&1;
6811 temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6812 temp_uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6813 temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6814 temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6815 temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6816 temp_u|=1;temp_uu|=1;
6817 temp_gte_u|=gte_rt[i+1];
6818 temp_gte_u&=~gte_rs[i+1];
6819 // If branch is "likely" (and conditional)
6820 // then we skip the delay slot on the fall-thru path
6823 temp_u&=unneeded_reg[i+2];
6824 temp_uu&=unneeded_reg_upper[i+2];
6825 temp_gte_u&=gte_unneeded[i+2];
6834 tdep=(~temp_uu>>rt1[i])&1;
6835 temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6836 temp_uu|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6837 temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6838 temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
6839 temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i]));
6840 temp_u|=1;temp_uu|=1;
6841 temp_gte_u|=gte_rt[i];
6842 temp_gte_u&=~gte_rs[i];
6843 unneeded_reg[i]=temp_u;
6844 unneeded_reg_upper[i]=temp_uu;
6845 gte_unneeded[i]=temp_gte_u;
6846 // Only go three levels deep. This recursion can take an
6847 // excessive amount of time if there are a lot of nested loops.
6849 unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6851 unneeded_reg[(ba[i]-start)>>2]=1;
6852 unneeded_reg_upper[(ba[i]-start)>>2]=1;
6853 gte_unneeded[(ba[i]-start)>>2]=0;
6856 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6858 // Unconditional branch
6859 u=unneeded_reg[(ba[i]-start)>>2];
6860 uu=unneeded_reg_upper[(ba[i]-start)>>2];
6861 gte_u=gte_unneeded[(ba[i]-start)>>2];
6862 branch_unneeded_reg[i]=u;
6863 branch_unneeded_reg_upper[i]=uu;
6866 //branch_unneeded_reg[i]=u;
6867 //branch_unneeded_reg_upper[i]=uu;
6868 // Merge in delay slot
6869 tdep=(~uu>>rt1[i+1])&1;
6870 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6871 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6872 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6873 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6874 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6877 gte_u&=~gte_rs[i+1];
6879 // Conditional branch
6880 b=unneeded_reg[(ba[i]-start)>>2];
6881 bu=unneeded_reg_upper[(ba[i]-start)>>2];
6882 gte_bu=gte_unneeded[(ba[i]-start)>>2];
6883 branch_unneeded_reg[i]=b;
6884 branch_unneeded_reg_upper[i]=bu;
6887 //branch_unneeded_reg[i]=b;
6888 //branch_unneeded_reg_upper[i]=bu;
6889 // Branch delay slot
6890 tdep=(~uu>>rt1[i+1])&1;
6891 b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6892 bu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6893 b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6894 bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6895 bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6897 gte_bu|=gte_rt[i+1];
6898 gte_bu&=~gte_rs[i+1];
6899 // If branch is "likely" then we skip the
6900 // delay slot on the fall-thru path
6906 u&=unneeded_reg[i+2];
6907 uu&=unneeded_reg_upper[i+2];
6908 gte_u&=gte_unneeded[i+2];
6920 branch_unneeded_reg[i]&=unneeded_reg[i+2];
6921 branch_unneeded_reg_upper[i]&=unneeded_reg_upper[i+2];
6922 //branch_unneeded_reg[i]=1;
6923 //branch_unneeded_reg_upper[i]=1;
6925 branch_unneeded_reg[i]=1;
6926 branch_unneeded_reg_upper[i]=1;
6932 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
6934 // SYSCALL instruction (software interrupt)
6938 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
6940 // ERET instruction (return from interrupt)
6945 tdep=(~uu>>rt1[i])&1;
6946 // Written registers are unneeded
6952 // Accessed registers are needed
6958 // Source-target dependencies
6959 uu&=~(tdep<<dep1[i]);
6960 uu&=~(tdep<<dep2[i]);
6961 // R0 is always unneeded
6965 unneeded_reg_upper[i]=uu;
6966 gte_unneeded[i]=gte_u;
6968 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
6971 for(r=1;r<=CCREG;r++) {
6972 if((unneeded_reg[i]>>r)&1) {
6973 if(r==HIREG) printf(" HI");
6974 else if(r==LOREG) printf(" LO");
6975 else printf(" r%d",r);
6979 for(r=1;r<=CCREG;r++) {
6980 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
6981 if(r==HIREG) printf(" HI");
6982 else if(r==LOREG) printf(" LO");
6983 else printf(" r%d",r);
6989 for (i=iend;i>=istart;i--)
6991 unneeded_reg_upper[i]=branch_unneeded_reg_upper[i]=-1LL;
6996 // Identify registers which are likely to contain 32-bit values
6997 // This is used to predict whether any branches will jump to a
6998 // location with 64-bit values in registers.
6999 static void provisional_32bit()
7003 uint64_t lastbranch=1;
7008 if(itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) {
7009 if(i>1) is32=lastbranch;
7015 if(itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP) {
7017 if(i>2) is32=lastbranch;
7021 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
7023 if(rs1[i-2]==0||rs2[i-2]==0)
7026 is32|=1LL<<rs1[i-2];
7029 is32|=1LL<<rs2[i-2];
7034 // If something jumps here with 64-bit values
7035 // then promote those registers to 64 bits
7038 uint64_t temp_is32=is32;
7041 if(ba[j]==start+i*4)
7042 //temp_is32&=branch_regs[j].is32;
7047 if(ba[j]==start+i*4)
7058 if(type==UJUMP||type==RJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
7059 // Branches don't write registers, consider the delay slot instead.
7070 if(opcode[i]==0x27||opcode[i]==0x37|| // LWU/LD
7071 opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
7080 if(op==0x1a||op==0x1b) is32&=~(1LL<<rt); // LDR/LDL
7081 if(op==0x22) is32|=1LL<<rt; // LWL
7084 if (op==0x08||op==0x09|| // ADDI/ADDIU
7085 op==0x0a||op==0x0b|| // SLTI/SLTIU
7091 if(op==0x18||op==0x19) { // DADDI/DADDIU
7094 // is32|=((is32>>s1)&1LL)<<rt;
7096 if(op==0x0d||op==0x0e) { // ORI/XORI
7097 uint64_t sr=((is32>>s1)&1LL);
7113 if(op2>=0x20&&op2<=0x23) { // ADD/ADDU/SUB/SUBU
7116 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
7119 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
7120 uint64_t sr=((is32>>s1)&(is32>>s2)&1LL);
7124 else if(op2>=0x2c&&op2<=0x2d) { // DADD/DADDU
7129 uint64_t sr=((is32>>s1)&1LL);
7134 uint64_t sr=((is32>>s2)&1LL);
7142 else if(op2>=0x2e&&op2<=0x2f) { // DSUB/DSUBU
7147 uint64_t sr=((is32>>s1)&1LL);
7157 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
7158 is32&=~((1LL<<HIREG)|(1LL<<LOREG));
7161 is32|=(1LL<<HIREG)|(1LL<<LOREG);
7166 uint64_t sr=((is32>>s1)&1LL);
7172 if(op2>=0x14&&op2<=0x17) is32&=~(1LL<<rt); // DSLLV/DSRLV/DSRAV
7173 else is32|=1LL<<rt; // SLLV/SRLV/SRAV
7177 // DSLL/DSRL/DSRA/DSLL32/DSRL32 but not DSRA32 have 64-bit result
7178 if(op2>=0x38&&op2<0x3f) is32&=~(1LL<<rt);
7181 if(op2==0) is32|=1LL<<rt; // MFC0
7185 if(op2==0) is32|=1LL<<rt; // MFC1
7186 if(op2==1) is32&=~(1LL<<rt); // DMFC1
7187 if(op2==2) is32|=1LL<<rt; // CFC1
7209 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
7211 if(rt1[i-1]==31) // JAL/JALR
7213 // Subroutine call will return here, don't alloc any registers
7218 // Internal branch will jump here, match registers to caller
7226 // Identify registers which may be assumed to contain 32-bit values
7227 // and where optimizations will rely on this.
7228 // This is used to determine whether backward branches can safely
7229 // jump to a location with 64-bit values in registers.
7230 static void provisional_r32()
7235 for (i=slen-1;i>=0;i--)
7238 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7240 if(ba[i]<start || ba[i]>=(start+slen*4))
7242 // Branch out of this block, don't need anything
7248 // Need whatever matches the target
7249 // (and doesn't get overwritten by the delay slot instruction)
7251 int t=(ba[i]-start)>>2;
7252 if(ba[i]>start+i*4) {
7254 //if(!(requires_32bit[t]&~regs[i].was32))
7255 // r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7256 if(!(pr32[t]&~regs[i].was32))
7257 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7260 if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
7261 r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7264 // Conditional branch may need registers for following instructions
7265 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
7268 //r32|=requires_32bit[i+2];
7271 // Mark this address as a branch target since it may be called
7272 // upon return from interrupt
7276 // Merge in delay slot
7278 // These are overwritten unless the branch is "likely"
7279 // and the delay slot is nullified if not taken
7280 r32&=~(1LL<<rt1[i+1]);
7281 r32&=~(1LL<<rt2[i+1]);
7283 // Assume these are needed (delay slot)
7286 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
7290 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
7292 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
7294 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
7296 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
7298 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
7301 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7303 // SYSCALL instruction (software interrupt)
7306 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7308 // ERET instruction (return from interrupt)
7312 r32&=~(1LL<<rt1[i]);
7313 r32&=~(1LL<<rt2[i]);
7316 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
7320 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
7322 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
7324 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
7326 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
7328 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
7330 //requires_32bit[i]=r32;
7333 // Dirty registers which are 32-bit, require 32-bit input
7334 // as they will be written as 32-bit values
7335 for(hr=0;hr<HOST_REGS;hr++)
7337 if(regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64) {
7338 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
7339 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
7340 pr32[i]|=1LL<<regs[i].regmap_entry[hr];
7341 //requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
7348 // Write back dirty registers as soon as we will no longer modify them,
7349 // so that we don't end up with lots of writes at the branches.
7350 void clean_registers(int istart,int iend,int wr)
7354 u_int will_dirty_i,will_dirty_next,temp_will_dirty;
7355 u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
7357 will_dirty_i=will_dirty_next=0;
7358 wont_dirty_i=wont_dirty_next=0;
7360 will_dirty_i=will_dirty_next=will_dirty[iend+1];
7361 wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
7363 for (i=iend;i>=istart;i--)
7365 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7367 if(ba[i]<start || ba[i]>=(start+slen*4))
7369 // Branch out of this block, flush all regs
7370 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7372 // Unconditional branch
7375 // Merge in delay slot (will dirty)
7376 for(r=0;r<HOST_REGS;r++) {
7377 if(r!=EXCLUDE_REG) {
7378 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7379 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7380 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7381 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7382 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7383 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7384 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7385 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7386 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7387 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7388 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7389 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7390 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7391 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7397 // Conditional branch
7399 wont_dirty_i=wont_dirty_next;
7400 // Merge in delay slot (will dirty)
7401 for(r=0;r<HOST_REGS;r++) {
7402 if(r!=EXCLUDE_REG) {
7404 // Might not dirty if likely branch is not taken
7405 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7406 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7407 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7408 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7409 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7410 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
7411 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7412 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7413 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7414 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7415 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7416 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7417 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7418 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7423 // Merge in delay slot (wont dirty)
7424 for(r=0;r<HOST_REGS;r++) {
7425 if(r!=EXCLUDE_REG) {
7426 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7427 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7428 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7429 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7430 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7431 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7432 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7433 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7434 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7435 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7439 #ifndef DESTRUCTIVE_WRITEBACK
7440 branch_regs[i].dirty&=wont_dirty_i;
7442 branch_regs[i].dirty|=will_dirty_i;
7448 if(ba[i]<=start+i*4) {
7450 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7452 // Unconditional branch
7455 // Merge in delay slot (will dirty)
7456 for(r=0;r<HOST_REGS;r++) {
7457 if(r!=EXCLUDE_REG) {
7458 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7459 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7460 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7461 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7462 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7463 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7464 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7465 if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7466 if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7467 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7468 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7469 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7470 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7471 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7475 // Conditional branch (not taken case)
7476 temp_will_dirty=will_dirty_next;
7477 temp_wont_dirty=wont_dirty_next;
7478 // Merge in delay slot (will dirty)
7479 for(r=0;r<HOST_REGS;r++) {
7480 if(r!=EXCLUDE_REG) {
7482 // Will not dirty if likely branch is not taken
7483 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7484 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7485 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7486 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7487 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7488 if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
7489 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7490 //if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7491 //if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7492 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7493 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7494 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7495 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7496 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7501 // Merge in delay slot (wont dirty)
7502 for(r=0;r<HOST_REGS;r++) {
7503 if(r!=EXCLUDE_REG) {
7504 if((regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7505 if((regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7506 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7507 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7508 if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7509 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7510 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7511 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7512 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7513 if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7516 // Deal with changed mappings
7518 for(r=0;r<HOST_REGS;r++) {
7519 if(r!=EXCLUDE_REG) {
7520 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
7521 temp_will_dirty&=~(1<<r);
7522 temp_wont_dirty&=~(1<<r);
7523 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7524 temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7525 temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7527 temp_will_dirty|=1<<r;
7528 temp_wont_dirty|=1<<r;
7535 will_dirty[i]=temp_will_dirty;
7536 wont_dirty[i]=temp_wont_dirty;
7537 clean_registers((ba[i]-start)>>2,i-1,0);
7539 // Limit recursion. It can take an excessive amount
7540 // of time if there are a lot of nested loops.
7541 will_dirty[(ba[i]-start)>>2]=0;
7542 wont_dirty[(ba[i]-start)>>2]=-1;
7547 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7549 // Unconditional branch
7552 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7553 for(r=0;r<HOST_REGS;r++) {
7554 if(r!=EXCLUDE_REG) {
7555 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7556 will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
7557 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7559 if(branch_regs[i].regmap[r]>=0) {
7560 will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7561 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7566 // Merge in delay slot
7567 for(r=0;r<HOST_REGS;r++) {
7568 if(r!=EXCLUDE_REG) {
7569 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7570 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7571 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7572 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7573 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7574 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7575 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7576 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7577 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7578 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7579 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7580 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7581 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7582 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7586 // Conditional branch
7587 will_dirty_i=will_dirty_next;
7588 wont_dirty_i=wont_dirty_next;
7589 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7590 for(r=0;r<HOST_REGS;r++) {
7591 if(r!=EXCLUDE_REG) {
7592 signed char target_reg=branch_regs[i].regmap[r];
7593 if(target_reg==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7594 will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7595 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7597 else if(target_reg>=0) {
7598 will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
7599 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
7601 // Treat delay slot as part of branch too
7602 /*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7603 will_dirty[i+1]&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7604 wont_dirty[i+1]|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7608 will_dirty[i+1]&=~(1<<r);
7613 // Merge in delay slot
7614 for(r=0;r<HOST_REGS;r++) {
7615 if(r!=EXCLUDE_REG) {
7617 // Might not dirty if likely branch is not taken
7618 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7619 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7620 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7621 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7622 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7623 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7624 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7625 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7626 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7627 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7628 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7629 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7630 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7631 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7636 // Merge in delay slot (won't dirty)
7637 for(r=0;r<HOST_REGS;r++) {
7638 if(r!=EXCLUDE_REG) {
7639 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7640 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7641 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7642 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7643 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7644 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7645 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7646 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7647 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7648 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7652 #ifndef DESTRUCTIVE_WRITEBACK
7653 branch_regs[i].dirty&=wont_dirty_i;
7655 branch_regs[i].dirty|=will_dirty_i;
7660 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7662 // SYSCALL instruction (software interrupt)
7666 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7668 // ERET instruction (return from interrupt)
7672 will_dirty_next=will_dirty_i;
7673 wont_dirty_next=wont_dirty_i;
7674 for(r=0;r<HOST_REGS;r++) {
7675 if(r!=EXCLUDE_REG) {
7676 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7677 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7678 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7679 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7680 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7681 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7682 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7683 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7685 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
7687 // Don't store a register immediately after writing it,
7688 // may prevent dual-issue.
7689 if((regs[i].regmap[r]&63)==rt1[i-1]) wont_dirty_i|=1<<r;
7690 if((regs[i].regmap[r]&63)==rt2[i-1]) wont_dirty_i|=1<<r;
7696 will_dirty[i]=will_dirty_i;
7697 wont_dirty[i]=wont_dirty_i;
7698 // Mark registers that won't be dirtied as not dirty
7700 /*printf("wr (%d,%d) %x will:",istart,iend,start+i*4);
7701 for(r=0;r<HOST_REGS;r++) {
7702 if((will_dirty_i>>r)&1) {
7708 //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=FJUMP)) {
7709 regs[i].dirty|=will_dirty_i;
7710 #ifndef DESTRUCTIVE_WRITEBACK
7711 regs[i].dirty&=wont_dirty_i;
7712 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7714 if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
7715 for(r=0;r<HOST_REGS;r++) {
7716 if(r!=EXCLUDE_REG) {
7717 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
7718 regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
7719 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7727 for(r=0;r<HOST_REGS;r++) {
7728 if(r!=EXCLUDE_REG) {
7729 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
7730 regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
7731 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7739 // Deal with changed mappings
7740 temp_will_dirty=will_dirty_i;
7741 temp_wont_dirty=wont_dirty_i;
7742 for(r=0;r<HOST_REGS;r++) {
7743 if(r!=EXCLUDE_REG) {
7745 if(regs[i].regmap[r]==regmap_pre[i][r]) {
7747 #ifndef DESTRUCTIVE_WRITEBACK
7748 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7750 regs[i].wasdirty|=will_dirty_i&(1<<r);
7753 else if(regmap_pre[i][r]>=0&&(nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
7754 // Register moved to a different register
7755 will_dirty_i&=~(1<<r);
7756 wont_dirty_i&=~(1<<r);
7757 will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
7758 wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
7760 #ifndef DESTRUCTIVE_WRITEBACK
7761 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7763 regs[i].wasdirty|=will_dirty_i&(1<<r);
7767 will_dirty_i&=~(1<<r);
7768 wont_dirty_i&=~(1<<r);
7769 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7770 will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7771 wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7774 /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);/*assert(!((will_dirty>>r)&1));*/
7783 void disassemble_inst(int i)
7785 if (bt[i]) printf("*"); else printf(" ");
7788 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7790 printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
7792 printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
7794 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7796 if (opcode[i]==0x9&&rt1[i]!=31)
7797 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i]);
7799 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7802 printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break;
7804 if(opcode[i]==0xf) //LUI
7805 printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],rt1[i],imm[i]&0xffff);
7807 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7811 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7815 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rs2[i],rs1[i],imm[i]);
7819 printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i],rs2[i]);
7822 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rs1[i],rs2[i]);
7825 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7828 if((opcode2[i]&0x1d)==0x10)
7829 printf (" %x: %s r%d\n",start+i*4,insn[i],rt1[i]);
7830 else if((opcode2[i]&0x1d)==0x11)
7831 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7833 printf (" %x: %s\n",start+i*4,insn[i]);
7837 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC0
7838 else if(opcode2[i]==4)
7839 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC0
7840 else printf (" %x: %s\n",start+i*4,insn[i]);
7844 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC1
7845 else if(opcode2[i]>3)
7846 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC1
7847 else printf (" %x: %s\n",start+i*4,insn[i]);
7851 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC2
7852 else if(opcode2[i]>3)
7853 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC2
7854 else printf (" %x: %s\n",start+i*4,insn[i]);
7857 printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7860 printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7863 printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
7866 //printf (" %s %8x\n",insn[i],source[i]);
7867 printf (" %x: %s\n",start+i*4,insn[i]);
7871 // clear the state completely, instead of just marking
7872 // things invalid like invalidate_all_pages() does
7873 void new_dynarec_clear_full()
7876 out=(u_char *)BASE_ADDR;
7877 memset(invalid_code,1,sizeof(invalid_code));
7878 memset(hash_table,0xff,sizeof(hash_table));
7879 memset(mini_ht,-1,sizeof(mini_ht));
7880 memset(restore_candidate,0,sizeof(restore_candidate));
7881 memset(shadow,0,sizeof(shadow));
7883 expirep=16384; // Expiry pointer, +2 blocks
7884 pending_exception=0;
7887 inv_code_start=inv_code_end=~0;
7894 for(n=0;n<524288;n++) // 0 .. 0x7FFFFFFF
7896 for(n=524288;n<526336;n++) // 0x80000000 .. 0x807FFFFF
7897 memory_map[n]=((u_int)rdram-0x80000000)>>2;
7898 for(n=526336;n<1048576;n++) // 0x80800000 .. 0xFFFFFFFF
7900 for(n=0;n<4096;n++) ll_clear(jump_in+n);
7901 for(n=0;n<4096;n++) ll_clear(jump_out+n);
7902 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7905 void new_dynarec_init()
7907 printf("Init new dynarec\n");
7908 out=(u_char *)BASE_ADDR;
7909 if (mmap (out, 1<<TARGET_SIZE_2,
7910 PROT_READ | PROT_WRITE | PROT_EXEC,
7911 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
7912 -1, 0) <= 0) {printf("mmap() failed\n");}
7914 rdword=&readmem_dword;
7915 fake_pc.f.r.rs=&readmem_dword;
7916 fake_pc.f.r.rt=&readmem_dword;
7917 fake_pc.f.r.rd=&readmem_dword;
7920 new_dynarec_clear_full();
7922 // Copy this into local area so we don't have to put it in every literal pool
7923 invc_ptr=invalid_code;
7926 for(n=0;n<0x8000;n++) { // 0 .. 0x7FFFFFFF
7927 writemem[n] = write_nomem_new;
7928 writememb[n] = write_nomemb_new;
7929 writememh[n] = write_nomemh_new;
7931 writememd[n] = write_nomemd_new;
7933 readmem[n] = read_nomem_new;
7934 readmemb[n] = read_nomemb_new;
7935 readmemh[n] = read_nomemh_new;
7937 readmemd[n] = read_nomemd_new;
7940 for(n=0x8000;n<0x8080;n++) { // 0x80000000 .. 0x807FFFFF
7941 writemem[n] = write_rdram_new;
7942 writememb[n] = write_rdramb_new;
7943 writememh[n] = write_rdramh_new;
7945 writememd[n] = write_rdramd_new;
7948 for(n=0xC000;n<0x10000;n++) { // 0xC0000000 .. 0xFFFFFFFF
7949 writemem[n] = write_nomem_new;
7950 writememb[n] = write_nomemb_new;
7951 writememh[n] = write_nomemh_new;
7953 writememd[n] = write_nomemd_new;
7955 readmem[n] = read_nomem_new;
7956 readmemb[n] = read_nomemb_new;
7957 readmemh[n] = read_nomemh_new;
7959 readmemd[n] = read_nomemd_new;
7967 void new_dynarec_cleanup()
7970 if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0) {printf("munmap() failed\n");}
7971 for(n=0;n<4096;n++) ll_clear(jump_in+n);
7972 for(n=0;n<4096;n++) ll_clear(jump_out+n);
7973 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7975 if (munmap (ROM_COPY, 67108864) < 0) {printf("munmap() failed\n");}
7979 int new_recompile_block(int addr)
7982 if(addr==0x800cd050) {
7984 for(block=0x80000;block<0x80800;block++) invalidate_block(block);
7986 for(n=0;n<=2048;n++) ll_clear(jump_dirty+n);
7989 //if(Count==365117028) tracedebug=1;
7990 assem_debug("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7991 //printf("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7992 //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
7994 //printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
7995 //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
7996 /*if(Count>=312978186) {
8000 start = (u_int)addr&~3;
8001 //assert(((u_int)addr&1)==0);
8003 if(!sp_in_mirror&&(signed int)(psxRegs.GPR.n.sp&0xffe00000)>0x80200000&&
8004 0x10000<=psxRegs.GPR.n.sp&&(psxRegs.GPR.n.sp&~0xe0e00000)<RAM_SIZE) {
8005 printf("SP hack enabled (%08x), @%08x\n", psxRegs.GPR.n.sp, psxRegs.pc);
8008 if (Config.HLE && start == 0x80001000) // hlecall
8010 // XXX: is this enough? Maybe check hleSoftCall?
8011 u_int beginning=(u_int)out;
8012 u_int page=get_page(start);
8013 invalid_code[start>>12]=0;
8014 emit_movimm(start,0);
8015 emit_writeword(0,(int)&pcaddr);
8016 emit_jmp((int)new_dyna_leave);
8019 __clear_cache((void *)beginning,out);
8021 ll_add(jump_in+page,start,(void *)beginning);
8024 else if ((u_int)addr < 0x00200000 ||
8025 (0xa0000000 <= addr && addr < 0xa0200000)) {
8026 // used for BIOS calls mostly?
8027 source = (u_int *)((u_int)rdram+(start&0x1fffff));
8028 pagelimit = (addr&0xa0000000)|0x00200000;
8030 else if (!Config.HLE && (
8031 /* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
8032 (0xbfc00000 <= addr && addr < 0xbfc80000))) {
8034 source = (u_int *)((u_int)psxR+(start&0x7ffff));
8035 pagelimit = (addr&0xfff00000)|0x80000;
8040 if ((int)addr >= 0xa4000000 && (int)addr < 0xa4001000) {
8041 source = (u_int *)((u_int)SP_DMEM+start-0xa4000000);
8042 pagelimit = 0xa4001000;
8046 if ((int)addr >= 0x80000000 && (int)addr < 0x80000000+RAM_SIZE) {
8047 source = (u_int *)((u_int)rdram+start-0x80000000);
8048 pagelimit = 0x80000000+RAM_SIZE;
8051 else if ((signed int)addr >= (signed int)0xC0000000) {
8052 //printf("addr=%x mm=%x\n",(u_int)addr,(memory_map[start>>12]<<2));
8053 //if(tlb_LUT_r[start>>12])
8054 //source = (u_int *)(((int)rdram)+(tlb_LUT_r[start>>12]&0xFFFFF000)+(((int)addr)&0xFFF)-0x80000000);
8055 if((signed int)memory_map[start>>12]>=0) {
8056 source = (u_int *)((u_int)(start+(memory_map[start>>12]<<2)));
8057 pagelimit=(start+4096)&0xFFFFF000;
8058 int map=memory_map[start>>12];
8061 //printf("start: %x next: %x\n",map,memory_map[pagelimit>>12]);
8062 if((map&0xBFFFFFFF)==(memory_map[pagelimit>>12]&0xBFFFFFFF)) pagelimit+=4096;
8064 assem_debug("pagelimit=%x\n",pagelimit);
8065 assem_debug("mapping=%x (%x)\n",memory_map[start>>12],(memory_map[start>>12]<<2)+start);
8068 assem_debug("Compile at unmapped memory address: %x \n", (int)addr);
8069 //assem_debug("start: %x next: %x\n",memory_map[start>>12],memory_map[(start+4096)>>12]);
8070 return -1; // Caller will invoke exception handler
8072 //printf("source= %x\n",(int)source);
8076 printf("Compile at bogus memory address: %x \n", (int)addr);
8080 /* Pass 1: disassemble */
8081 /* Pass 2: register dependencies, branch targets */
8082 /* Pass 3: register allocation */
8083 /* Pass 4: branch dependencies */
8084 /* Pass 5: pre-alloc */
8085 /* Pass 6: optimize clean/dirty state */
8086 /* Pass 7: flag 32-bit registers */
8087 /* Pass 8: assembly */
8088 /* Pass 9: linker */
8089 /* Pass 10: garbage collection / free memory */
8093 unsigned int type,op,op2;
8095 //printf("addr = %x source = %x %x\n", addr,source,source[0]);
8097 /* Pass 1 disassembly */
8099 for(i=0;!done;i++) {
8100 bt[i]=0;likely[i]=0;ooo[i]=0;op2=0;
8101 minimum_free_regs[i]=0;
8102 opcode[i]=op=source[i]>>26;
8105 case 0x00: strcpy(insn[i],"special"); type=NI;
8109 case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
8110 case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
8111 case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
8112 case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
8113 case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
8114 case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
8115 case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
8116 case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
8117 case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
8118 case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
8119 case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
8120 case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
8121 case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
8122 case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
8123 case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
8124 case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
8125 case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
8126 case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
8127 case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
8128 case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
8129 case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
8130 case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
8131 case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
8132 case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
8133 case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
8134 case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
8135 case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
8136 case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
8137 case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
8138 case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
8139 case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
8140 case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
8141 case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
8142 case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
8143 case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
8145 case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
8146 case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
8147 case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
8148 case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
8149 case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
8150 case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
8151 case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
8152 case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
8153 case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
8154 case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
8155 case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
8156 case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
8157 case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
8158 case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
8159 case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
8160 case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
8161 case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
8165 case 0x01: strcpy(insn[i],"regimm"); type=NI;
8166 op2=(source[i]>>16)&0x1f;
8169 case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
8170 case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
8171 case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
8172 case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
8173 case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
8174 case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
8175 case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
8176 case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
8177 case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
8178 case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
8179 case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
8180 case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
8181 case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
8182 case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
8185 case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
8186 case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
8187 case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
8188 case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
8189 case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
8190 case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
8191 case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
8192 case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
8193 case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
8194 case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
8195 case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
8196 case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
8197 case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
8198 case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
8199 case 0x10: strcpy(insn[i],"cop0"); type=NI;
8200 op2=(source[i]>>21)&0x1f;
8203 case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
8204 case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
8205 case 0x10: strcpy(insn[i],"tlb"); type=NI;
8206 switch(source[i]&0x3f)
8208 case 0x01: strcpy(insn[i],"TLBR"); type=COP0; break;
8209 case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break;
8210 case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break;
8211 case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break;
8213 case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
8215 case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
8220 case 0x11: strcpy(insn[i],"cop1"); type=NI;
8221 op2=(source[i]>>21)&0x1f;
8224 case 0x00: strcpy(insn[i],"MFC1"); type=COP1; break;
8225 case 0x01: strcpy(insn[i],"DMFC1"); type=COP1; break;
8226 case 0x02: strcpy(insn[i],"CFC1"); type=COP1; break;
8227 case 0x04: strcpy(insn[i],"MTC1"); type=COP1; break;
8228 case 0x05: strcpy(insn[i],"DMTC1"); type=COP1; break;
8229 case 0x06: strcpy(insn[i],"CTC1"); type=COP1; break;
8230 case 0x08: strcpy(insn[i],"BC1"); type=FJUMP;
8231 switch((source[i]>>16)&0x3)
8233 case 0x00: strcpy(insn[i],"BC1F"); break;
8234 case 0x01: strcpy(insn[i],"BC1T"); break;
8235 case 0x02: strcpy(insn[i],"BC1FL"); break;
8236 case 0x03: strcpy(insn[i],"BC1TL"); break;
8239 case 0x10: strcpy(insn[i],"C1.S"); type=NI;
8240 switch(source[i]&0x3f)
8242 case 0x00: strcpy(insn[i],"ADD.S"); type=FLOAT; break;
8243 case 0x01: strcpy(insn[i],"SUB.S"); type=FLOAT; break;
8244 case 0x02: strcpy(insn[i],"MUL.S"); type=FLOAT; break;
8245 case 0x03: strcpy(insn[i],"DIV.S"); type=FLOAT; break;
8246 case 0x04: strcpy(insn[i],"SQRT.S"); type=FLOAT; break;
8247 case 0x05: strcpy(insn[i],"ABS.S"); type=FLOAT; break;
8248 case 0x06: strcpy(insn[i],"MOV.S"); type=FLOAT; break;
8249 case 0x07: strcpy(insn[i],"NEG.S"); type=FLOAT; break;
8250 case 0x08: strcpy(insn[i],"ROUND.L.S"); type=FCONV; break;
8251 case 0x09: strcpy(insn[i],"TRUNC.L.S"); type=FCONV; break;
8252 case 0x0A: strcpy(insn[i],"CEIL.L.S"); type=FCONV; break;
8253 case 0x0B: strcpy(insn[i],"FLOOR.L.S"); type=FCONV; break;
8254 case 0x0C: strcpy(insn[i],"ROUND.W.S"); type=FCONV; break;
8255 case 0x0D: strcpy(insn[i],"TRUNC.W.S"); type=FCONV; break;
8256 case 0x0E: strcpy(insn[i],"CEIL.W.S"); type=FCONV; break;
8257 case 0x0F: strcpy(insn[i],"FLOOR.W.S"); type=FCONV; break;
8258 case 0x21: strcpy(insn[i],"CVT.D.S"); type=FCONV; break;
8259 case 0x24: strcpy(insn[i],"CVT.W.S"); type=FCONV; break;
8260 case 0x25: strcpy(insn[i],"CVT.L.S"); type=FCONV; break;
8261 case 0x30: strcpy(insn[i],"C.F.S"); type=FCOMP; break;
8262 case 0x31: strcpy(insn[i],"C.UN.S"); type=FCOMP; break;
8263 case 0x32: strcpy(insn[i],"C.EQ.S"); type=FCOMP; break;
8264 case 0x33: strcpy(insn[i],"C.UEQ.S"); type=FCOMP; break;
8265 case 0x34: strcpy(insn[i],"C.OLT.S"); type=FCOMP; break;
8266 case 0x35: strcpy(insn[i],"C.ULT.S"); type=FCOMP; break;
8267 case 0x36: strcpy(insn[i],"C.OLE.S"); type=FCOMP; break;
8268 case 0x37: strcpy(insn[i],"C.ULE.S"); type=FCOMP; break;
8269 case 0x38: strcpy(insn[i],"C.SF.S"); type=FCOMP; break;
8270 case 0x39: strcpy(insn[i],"C.NGLE.S"); type=FCOMP; break;
8271 case 0x3A: strcpy(insn[i],"C.SEQ.S"); type=FCOMP; break;
8272 case 0x3B: strcpy(insn[i],"C.NGL.S"); type=FCOMP; break;
8273 case 0x3C: strcpy(insn[i],"C.LT.S"); type=FCOMP; break;
8274 case 0x3D: strcpy(insn[i],"C.NGE.S"); type=FCOMP; break;
8275 case 0x3E: strcpy(insn[i],"C.LE.S"); type=FCOMP; break;
8276 case 0x3F: strcpy(insn[i],"C.NGT.S"); type=FCOMP; break;
8279 case 0x11: strcpy(insn[i],"C1.D"); type=NI;
8280 switch(source[i]&0x3f)
8282 case 0x00: strcpy(insn[i],"ADD.D"); type=FLOAT; break;
8283 case 0x01: strcpy(insn[i],"SUB.D"); type=FLOAT; break;
8284 case 0x02: strcpy(insn[i],"MUL.D"); type=FLOAT; break;
8285 case 0x03: strcpy(insn[i],"DIV.D"); type=FLOAT; break;
8286 case 0x04: strcpy(insn[i],"SQRT.D"); type=FLOAT; break;
8287 case 0x05: strcpy(insn[i],"ABS.D"); type=FLOAT; break;
8288 case 0x06: strcpy(insn[i],"MOV.D"); type=FLOAT; break;
8289 case 0x07: strcpy(insn[i],"NEG.D"); type=FLOAT; break;
8290 case 0x08: strcpy(insn[i],"ROUND.L.D"); type=FCONV; break;
8291 case 0x09: strcpy(insn[i],"TRUNC.L.D"); type=FCONV; break;
8292 case 0x0A: strcpy(insn[i],"CEIL.L.D"); type=FCONV; break;
8293 case 0x0B: strcpy(insn[i],"FLOOR.L.D"); type=FCONV; break;
8294 case 0x0C: strcpy(insn[i],"ROUND.W.D"); type=FCONV; break;
8295 case 0x0D: strcpy(insn[i],"TRUNC.W.D"); type=FCONV; break;
8296 case 0x0E: strcpy(insn[i],"CEIL.W.D"); type=FCONV; break;
8297 case 0x0F: strcpy(insn[i],"FLOOR.W.D"); type=FCONV; break;
8298 case 0x20: strcpy(insn[i],"CVT.S.D"); type=FCONV; break;
8299 case 0x24: strcpy(insn[i],"CVT.W.D"); type=FCONV; break;
8300 case 0x25: strcpy(insn[i],"CVT.L.D"); type=FCONV; break;
8301 case 0x30: strcpy(insn[i],"C.F.D"); type=FCOMP; break;
8302 case 0x31: strcpy(insn[i],"C.UN.D"); type=FCOMP; break;
8303 case 0x32: strcpy(insn[i],"C.EQ.D"); type=FCOMP; break;
8304 case 0x33: strcpy(insn[i],"C.UEQ.D"); type=FCOMP; break;
8305 case 0x34: strcpy(insn[i],"C.OLT.D"); type=FCOMP; break;
8306 case 0x35: strcpy(insn[i],"C.ULT.D"); type=FCOMP; break;
8307 case 0x36: strcpy(insn[i],"C.OLE.D"); type=FCOMP; break;
8308 case 0x37: strcpy(insn[i],"C.ULE.D"); type=FCOMP; break;
8309 case 0x38: strcpy(insn[i],"C.SF.D"); type=FCOMP; break;
8310 case 0x39: strcpy(insn[i],"C.NGLE.D"); type=FCOMP; break;
8311 case 0x3A: strcpy(insn[i],"C.SEQ.D"); type=FCOMP; break;
8312 case 0x3B: strcpy(insn[i],"C.NGL.D"); type=FCOMP; break;
8313 case 0x3C: strcpy(insn[i],"C.LT.D"); type=FCOMP; break;
8314 case 0x3D: strcpy(insn[i],"C.NGE.D"); type=FCOMP; break;
8315 case 0x3E: strcpy(insn[i],"C.LE.D"); type=FCOMP; break;
8316 case 0x3F: strcpy(insn[i],"C.NGT.D"); type=FCOMP; break;
8319 case 0x14: strcpy(insn[i],"C1.W"); type=NI;
8320 switch(source[i]&0x3f)
8322 case 0x20: strcpy(insn[i],"CVT.S.W"); type=FCONV; break;
8323 case 0x21: strcpy(insn[i],"CVT.D.W"); type=FCONV; break;
8326 case 0x15: strcpy(insn[i],"C1.L"); type=NI;
8327 switch(source[i]&0x3f)
8329 case 0x20: strcpy(insn[i],"CVT.S.L"); type=FCONV; break;
8330 case 0x21: strcpy(insn[i],"CVT.D.L"); type=FCONV; break;
8336 case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
8337 case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
8338 case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
8339 case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
8340 case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
8341 case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
8342 case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
8343 case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
8345 case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
8346 case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
8347 case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
8348 case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
8349 case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
8350 case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
8351 case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
8353 case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
8355 case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
8356 case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
8357 case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
8358 case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
8360 case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
8361 case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
8363 case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
8364 case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
8365 case 0x30: strcpy(insn[i],"LL"); type=NI; break;
8366 case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
8368 case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
8369 case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
8370 case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
8372 case 0x38: strcpy(insn[i],"SC"); type=NI; break;
8373 case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
8375 case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
8376 case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
8377 case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
8380 case 0x12: strcpy(insn[i],"COP2"); type=NI;
8381 op2=(source[i]>>21)&0x1f;
8383 if (source[i]&0x3f) { // use this hack to support old savestates with patched gte insns
8384 if (gte_handlers[source[i]&0x3f]!=NULL) {
8385 if (gte_regnames[source[i]&0x3f]!=NULL)
8386 strcpy(insn[i],gte_regnames[source[i]&0x3f]);
8388 snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
8394 case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
8395 case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
8396 case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
8397 case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
8400 case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
8401 case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
8402 case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
8404 default: strcpy(insn[i],"???"); type=NI;
8405 printf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
8410 /* Get registers/immediates */
8416 gte_rs[i]=gte_rt[i]=0;
8419 rs1[i]=(source[i]>>21)&0x1f;
8421 rt1[i]=(source[i]>>16)&0x1f;
8423 imm[i]=(short)source[i];
8427 rs1[i]=(source[i]>>21)&0x1f;
8428 rs2[i]=(source[i]>>16)&0x1f;
8431 imm[i]=(short)source[i];
8432 if(op==0x2c||op==0x2d||op==0x3f) us1[i]=rs2[i]; // 64-bit SDL/SDR/SD
8435 // LWL/LWR only load part of the register,
8436 // therefore the target register must be treated as a source too
8437 rs1[i]=(source[i]>>21)&0x1f;
8438 rs2[i]=(source[i]>>16)&0x1f;
8439 rt1[i]=(source[i]>>16)&0x1f;
8441 imm[i]=(short)source[i];
8442 if(op==0x1a||op==0x1b) us1[i]=rs2[i]; // LDR/LDL
8443 if(op==0x26) dep1[i]=rt1[i]; // LWR
8446 if (op==0x0f) rs1[i]=0; // LUI instruction has no source register
8447 else rs1[i]=(source[i]>>21)&0x1f;
8449 rt1[i]=(source[i]>>16)&0x1f;
8451 if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
8452 imm[i]=(unsigned short)source[i];
8454 imm[i]=(short)source[i];
8456 if(op==0x18||op==0x19) us1[i]=rs1[i]; // DADDI/DADDIU
8457 if(op==0x0a||op==0x0b) us1[i]=rs1[i]; // SLTI/SLTIU
8458 if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI
8465 // The JAL instruction writes to r31.
8472 rs1[i]=(source[i]>>21)&0x1f;
8476 // The JALR instruction writes to rd.
8478 rt1[i]=(source[i]>>11)&0x1f;
8483 rs1[i]=(source[i]>>21)&0x1f;
8484 rs2[i]=(source[i]>>16)&0x1f;
8487 if(op&2) { // BGTZ/BLEZ
8495 rs1[i]=(source[i]>>21)&0x1f;
8500 if(op2&0x10) { // BxxAL
8502 // NOTE: If the branch is not taken, r31 is still overwritten
8504 likely[i]=(op2&2)>>1;
8511 likely[i]=((source[i])>>17)&1;
8514 rs1[i]=(source[i]>>21)&0x1f; // source
8515 rs2[i]=(source[i]>>16)&0x1f; // subtract amount
8516 rt1[i]=(source[i]>>11)&0x1f; // destination
8518 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
8519 us1[i]=rs1[i];us2[i]=rs2[i];
8521 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
8522 dep1[i]=rs1[i];dep2[i]=rs2[i];
8524 else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB
8525 dep1[i]=rs1[i];dep2[i]=rs2[i];
8529 rs1[i]=(source[i]>>21)&0x1f; // source
8530 rs2[i]=(source[i]>>16)&0x1f; // divisor
8533 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
8534 us1[i]=rs1[i];us2[i]=rs2[i];
8542 if(op2==0x10) rs1[i]=HIREG; // MFHI
8543 if(op2==0x11) rt1[i]=HIREG; // MTHI
8544 if(op2==0x12) rs1[i]=LOREG; // MFLO
8545 if(op2==0x13) rt1[i]=LOREG; // MTLO
8546 if((op2&0x1d)==0x10) rt1[i]=(source[i]>>11)&0x1f; // MFxx
8547 if((op2&0x1d)==0x11) rs1[i]=(source[i]>>21)&0x1f; // MTxx
8551 rs1[i]=(source[i]>>16)&0x1f; // target of shift
8552 rs2[i]=(source[i]>>21)&0x1f; // shift amount
8553 rt1[i]=(source[i]>>11)&0x1f; // destination
8555 // DSLLV/DSRLV/DSRAV are 64-bit
8556 if(op2>=0x14&&op2<=0x17) us1[i]=rs1[i];
8559 rs1[i]=(source[i]>>16)&0x1f;
8561 rt1[i]=(source[i]>>11)&0x1f;
8563 imm[i]=(source[i]>>6)&0x1f;
8564 // DSxx32 instructions
8565 if(op2>=0x3c) imm[i]|=0x20;
8566 // DSLL/DSRL/DSRA/DSRA32/DSRL32 but not DSLL32 require 64-bit source
8567 if(op2>=0x38&&op2!=0x3c) us1[i]=rs1[i];
8574 if(op2==0) rt1[i]=(source[i]>>16)&0x1F; // MFC0
8575 if(op2==4) rs1[i]=(source[i]>>16)&0x1F; // MTC0
8576 if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status
8577 if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET
8584 if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
8585 if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
8586 if(op2==5) us1[i]=rs1[i]; // DMTC1
8594 if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC2/CFC2
8595 if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC2/CTC2
8597 int gr=(source[i]>>11)&0x1F;
8600 case 0x00: gte_rs[i]=1ll<<gr; break; // MFC2
8601 case 0x04: gte_rt[i]=1ll<<gr; break; // MTC2
8602 case 0x02: gte_rs[i]=1ll<<(gr+32); // CFC2
8603 if(gr==31&&!gte_reads_flags) {
8604 assem_debug("gte flag read encountered @%08x\n",addr + i*4);
8608 case 0x06: gte_rt[i]=1ll<<(gr+32); break; // CTC2
8612 rs1[i]=(source[i]>>21)&0x1F;
8616 imm[i]=(short)source[i];
8619 rs1[i]=(source[i]>>21)&0x1F;
8623 imm[i]=(short)source[i];
8624 if(op==0x32) gte_rt[i]=1ll<<((source[i]>>16)&0x1F); // LWC2
8625 else gte_rs[i]=1ll<<((source[i]>>16)&0x1F); // SWC2
8632 gte_rt[i]=1ll<<63; // every op changes flags
8633 // TODO: other regs?
8662 /* Calculate branch target addresses */
8664 ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
8665 else if(type==CJUMP&&rs1[i]==rs2[i]&&(op&1))
8666 ba[i]=start+i*4+8; // Ignore never taken branch
8667 else if(type==SJUMP&&rs1[i]==0&&!(op2&1))
8668 ba[i]=start+i*4+8; // Ignore never taken branch
8669 else if(type==CJUMP||type==SJUMP||type==FJUMP)
8670 ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
8673 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
8675 // branch in delay slot?
8676 if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
8677 // don't handle first branch and call interpreter if it's hit
8678 printf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr);
8681 // basic load delay detection
8682 else if((type==LOAD||type==LOADLR||type==COP0||type==COP2||type==C2LS)&&rt1[i]!=0) {
8683 int t=(ba[i-1]-start)/4;
8684 if(0 <= t && t < i &&(rt1[i]==rs1[t]||rt1[i]==rs2[t])&&itype[t]!=CJUMP&&itype[t]!=SJUMP) {
8685 // jump target wants DS result - potential load delay effect
8686 printf("load delay @%08x (%08x)\n", addr + i*4, addr);
8688 bt[t+1]=1; // expected return from interpreter
8690 else if(i>=2&&rt1[i-2]==2&&rt1[i]==2&&rs1[i]!=2&&rs2[i]!=2&&rs1[i-1]!=2&&rs2[i-1]!=2&&
8691 !(i>=3&&(itype[i-3]==RJUMP||itype[i-3]==UJUMP||itype[i-3]==CJUMP||itype[i-3]==SJUMP))) {
8692 // v0 overwrite like this is a sign of trouble, bail out
8693 printf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr);
8699 rs2[i-1]=rt1[i-1]=rt2[i-1]=0;
8703 i--; // don't compile the DS
8707 /* Is this the end of the block? */
8708 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
8709 if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
8713 if(stop_after_jal) done=1;
8715 if((source[i+1]&0xfc00003f)==0x0d) done=1;
8717 // Don't recompile stuff that's already compiled
8718 if(check_addr(start+i*4+4)) done=1;
8719 // Don't get too close to the limit
8720 if(i>MAXBLOCK/2) done=1;
8722 if(itype[i]==SYSCALL&&stop_after_jal) done=1;
8723 if(itype[i]==HLECALL||itype[i]==INTCALL) done=2;
8725 // Does the block continue due to a branch?
8728 if(ba[j]==start+i*4) done=j=0; // Branch into delay slot
8729 if(ba[j]==start+i*4+4) done=j=0;
8730 if(ba[j]==start+i*4+8) done=j=0;
8733 //assert(i<MAXBLOCK-1);
8734 if(start+i*4==pagelimit-4) done=1;
8735 assert(start+i*4<pagelimit);
8736 if (i==MAXBLOCK-1) done=1;
8737 // Stop if we're compiling junk
8738 if(itype[i]==NI&&opcode[i]==0x11) {
8739 done=stop_after_jal=1;
8740 printf("Disabled speculative precompilation\n");
8744 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP||itype[i-1]==FJUMP) {
8745 if(start+i*4==pagelimit) {
8751 /* Pass 2 - Register dependencies and branch targets */
8753 unneeded_registers(0,slen-1,0);
8755 /* Pass 3 - Register allocation */
8757 struct regstat current; // Current register allocations/status
8760 current.u=unneeded_reg[0];
8761 current.uu=unneeded_reg_upper[0];
8762 clear_all_regs(current.regmap);
8763 alloc_reg(¤t,0,CCREG);
8764 dirty_reg(¤t,CCREG);
8772 provisional_32bit();
8775 // First instruction is delay slot
8780 unneeded_reg_upper[0]=1;
8781 current.regmap[HOST_BTREG]=BTREG;
8789 for(hr=0;hr<HOST_REGS;hr++)
8791 // Is this really necessary?
8792 if(current.regmap[hr]==0) current.regmap[hr]=-1;
8798 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
8800 if(rs1[i-2]==0||rs2[i-2]==0)
8803 current.is32|=1LL<<rs1[i-2];
8804 int hr=get_reg(current.regmap,rs1[i-2]|64);
8805 if(hr>=0) current.regmap[hr]=-1;
8808 current.is32|=1LL<<rs2[i-2];
8809 int hr=get_reg(current.regmap,rs2[i-2]|64);
8810 if(hr>=0) current.regmap[hr]=-1;
8816 // If something jumps here with 64-bit values
8817 // then promote those registers to 64 bits
8820 uint64_t temp_is32=current.is32;
8823 if(ba[j]==start+i*4)
8824 temp_is32&=branch_regs[j].is32;
8828 if(ba[j]==start+i*4)
8832 if(temp_is32!=current.is32) {
8833 //printf("dumping 32-bit regs (%x)\n",start+i*4);
8834 #ifndef DESTRUCTIVE_WRITEBACK
8837 for(hr=0;hr<HOST_REGS;hr++)
8839 int r=current.regmap[hr];
8842 if((current.dirty>>hr)&((current.is32&~temp_is32)>>r)&1) {
8844 //printf("restore %d\n",r);
8848 current.is32=temp_is32;
8855 memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
8856 regs[i].wasconst=current.isconst;
8857 regs[i].was32=current.is32;
8858 regs[i].wasdirty=current.dirty;
8859 #if defined(DESTRUCTIVE_WRITEBACK) && !defined(FORCE32)
8860 // To change a dirty register from 32 to 64 bits, we must write
8861 // it out during the previous cycle (for branches, 2 cycles)
8862 if(i<slen-1&&bt[i+1]&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP)
8864 uint64_t temp_is32=current.is32;
8867 if(ba[j]==start+i*4+4)
8868 temp_is32&=branch_regs[j].is32;
8872 if(ba[j]==start+i*4+4)
8876 if(temp_is32!=current.is32) {
8877 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8878 for(hr=0;hr<HOST_REGS;hr++)
8880 int r=current.regmap[hr];
8883 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8884 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP)
8886 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63))
8888 //printf("dump %d/r%d\n",hr,r);
8889 current.regmap[hr]=-1;
8890 if(get_reg(current.regmap,r|64)>=0)
8891 current.regmap[get_reg(current.regmap,r|64)]=-1;
8899 else if(i<slen-2&&bt[i+2]&&(source[i-1]>>16)!=0x1000&&(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP))
8901 uint64_t temp_is32=current.is32;
8904 if(ba[j]==start+i*4+8)
8905 temp_is32&=branch_regs[j].is32;
8909 if(ba[j]==start+i*4+8)
8913 if(temp_is32!=current.is32) {
8914 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8915 for(hr=0;hr<HOST_REGS;hr++)
8917 int r=current.regmap[hr];
8920 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8921 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63)&&rs1[i+1]!=(r&63)&&rs2[i+1]!=(r&63))
8923 //printf("dump %d/r%d\n",hr,r);
8924 current.regmap[hr]=-1;
8925 if(get_reg(current.regmap,r|64)>=0)
8926 current.regmap[get_reg(current.regmap,r|64)]=-1;
8934 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
8936 current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
8937 current.uu=unneeded_reg_upper[i+1]&~((1LL<<us1[i])|(1LL<<us2[i]));
8938 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8947 current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
8948 current.uu=branch_unneeded_reg_upper[i]&~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
8949 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
8950 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8951 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8954 } else { printf("oops, branch at end of block with no delay slot\n");exit(1); }
8958 ds=0; // Skip delay slot, already allocated as part of branch
8959 // ...but we need to alloc it in case something jumps here
8961 current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
8962 current.uu=branch_unneeded_reg_upper[i-1]&unneeded_reg_upper[i+1];
8964 current.u=branch_unneeded_reg[i-1];
8965 current.uu=branch_unneeded_reg_upper[i-1];
8967 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8968 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8969 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8972 struct regstat temp;
8973 memcpy(&temp,¤t,sizeof(current));
8974 temp.wasdirty=temp.dirty;
8975 temp.was32=temp.is32;
8976 // TODO: Take into account unconditional branches, as below
8977 delayslot_alloc(&temp,i);
8978 memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
8979 regs[i].wasdirty=temp.wasdirty;
8980 regs[i].was32=temp.was32;
8981 regs[i].dirty=temp.dirty;
8982 regs[i].is32=temp.is32;
8986 // Create entry (branch target) regmap
8987 for(hr=0;hr<HOST_REGS;hr++)
8989 int r=temp.regmap[hr];
8991 if(r!=regmap_pre[i][hr]) {
8992 regs[i].regmap_entry[hr]=-1;
8997 if((current.u>>r)&1) {
8998 regs[i].regmap_entry[hr]=-1;
8999 regs[i].regmap[hr]=-1;
9000 //Don't clear regs in the delay slot as the branch might need them
9001 //current.regmap[hr]=-1;
9003 regs[i].regmap_entry[hr]=r;
9006 if((current.uu>>(r&63))&1) {
9007 regs[i].regmap_entry[hr]=-1;
9008 regs[i].regmap[hr]=-1;
9009 //Don't clear regs in the delay slot as the branch might need them
9010 //current.regmap[hr]=-1;
9012 regs[i].regmap_entry[hr]=r;
9016 // First instruction expects CCREG to be allocated
9017 if(i==0&&hr==HOST_CCREG)
9018 regs[i].regmap_entry[hr]=CCREG;
9020 regs[i].regmap_entry[hr]=-1;
9024 else { // Not delay slot
9027 //current.isconst=0; // DEBUG
9028 //current.wasconst=0; // DEBUG
9029 //regs[i].wasconst=0; // DEBUG
9030 clear_const(¤t,rt1[i]);
9031 alloc_cc(¤t,i);
9032 dirty_reg(¤t,CCREG);
9034 alloc_reg(¤t,i,31);
9035 dirty_reg(¤t,31);
9036 //assert(rs1[i+1]!=31&&rs2[i+1]!=31);
9037 //assert(rt1[i+1]!=rt1[i]);
9039 alloc_reg(¤t,i,PTEMP);
9041 //current.is32|=1LL<<rt1[i];
9044 delayslot_alloc(¤t,i+1);
9045 //current.isconst=0; // DEBUG
9047 //printf("i=%d, isconst=%x\n",i,current.isconst);
9050 //current.isconst=0;
9051 //current.wasconst=0;
9052 //regs[i].wasconst=0;
9053 clear_const(¤t,rs1[i]);
9054 clear_const(¤t,rt1[i]);
9055 alloc_cc(¤t,i);
9056 dirty_reg(¤t,CCREG);
9057 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
9058 alloc_reg(¤t,i,rs1[i]);
9060 alloc_reg(¤t,i,rt1[i]);
9061 dirty_reg(¤t,rt1[i]);
9062 assert(rs1[i+1]!=rt1[i]&&rs2[i+1]!=rt1[i]);
9063 assert(rt1[i+1]!=rt1[i]);
9065 alloc_reg(¤t,i,PTEMP);
9069 if(rs1[i]==31) { // JALR
9070 alloc_reg(¤t,i,RHASH);
9071 #ifndef HOST_IMM_ADDR32
9072 alloc_reg(¤t,i,RHTBL);
9076 delayslot_alloc(¤t,i+1);
9078 // The delay slot overwrites our source register,
9079 // allocate a temporary register to hold the old value.
9083 delayslot_alloc(¤t,i+1);
9085 alloc_reg(¤t,i,RTEMP);
9087 //current.isconst=0; // DEBUG
9092 //current.isconst=0;
9093 //current.wasconst=0;
9094 //regs[i].wasconst=0;
9095 clear_const(¤t,rs1[i]);
9096 clear_const(¤t,rs2[i]);
9097 if((opcode[i]&0x3E)==4) // BEQ/BNE
9099 alloc_cc(¤t,i);
9100 dirty_reg(¤t,CCREG);
9101 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
9102 if(rs2[i]) alloc_reg(¤t,i,rs2[i]);
9103 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9105 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
9106 if(rs2[i]) alloc_reg64(¤t,i,rs2[i]);
9108 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
9109 (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) {
9110 // The delay slot overwrites one of our conditions.
9111 // Allocate the branch condition registers instead.
9115 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
9116 if(rs2[i]) alloc_reg(¤t,i,rs2[i]);
9117 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9119 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
9120 if(rs2[i]) alloc_reg64(¤t,i,rs2[i]);
9126 delayslot_alloc(¤t,i+1);
9130 if((opcode[i]&0x3E)==6) // BLEZ/BGTZ
9132 alloc_cc(¤t,i);
9133 dirty_reg(¤t,CCREG);
9134 alloc_reg(¤t,i,rs1[i]);
9135 if(!(current.is32>>rs1[i]&1))
9137 alloc_reg64(¤t,i,rs1[i]);
9139 if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
9140 // The delay slot overwrites one of our conditions.
9141 // Allocate the branch condition registers instead.
9145 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
9146 if(!((current.is32>>rs1[i])&1))
9148 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
9154 delayslot_alloc(¤t,i+1);
9158 // Don't alloc the delay slot yet because we might not execute it
9159 if((opcode[i]&0x3E)==0x14) // BEQL/BNEL
9164 alloc_cc(¤t,i);
9165 dirty_reg(¤t,CCREG);
9166 alloc_reg(¤t,i,rs1[i]);
9167 alloc_reg(¤t,i,rs2[i]);
9168 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9170 alloc_reg64(¤t,i,rs1[i]);
9171 alloc_reg64(¤t,i,rs2[i]);
9175 if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL
9180 alloc_cc(¤t,i);
9181 dirty_reg(¤t,CCREG);
9182 alloc_reg(¤t,i,rs1[i]);
9183 if(!(current.is32>>rs1[i]&1))
9185 alloc_reg64(¤t,i,rs1[i]);
9189 //current.isconst=0;
9192 //current.isconst=0;
9193 //current.wasconst=0;
9194 //regs[i].wasconst=0;
9195 clear_const(¤t,rs1[i]);
9196 clear_const(¤t,rt1[i]);
9197 //if((opcode2[i]&0x1E)==0x0) // BLTZ/BGEZ
9198 if((opcode2[i]&0x0E)==0x0) // BLTZ/BGEZ
9200 alloc_cc(¤t,i);
9201 dirty_reg(¤t,CCREG);
9202 alloc_reg(¤t,i,rs1[i]);
9203 if(!(current.is32>>rs1[i]&1))
9205 alloc_reg64(¤t,i,rs1[i]);
9207 if (rt1[i]==31) { // BLTZAL/BGEZAL
9208 alloc_reg(¤t,i,31);
9209 dirty_reg(¤t,31);
9210 //#ifdef REG_PREFETCH
9211 //alloc_reg(¤t,i,PTEMP);
9213 //current.is32|=1LL<<rt1[i];
9215 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) // The delay slot overwrites the branch condition.
9216 ||(rt1[i]==31&&(rs1[i+1]==31||rs2[i+1]==31||rt1[i+1]==31||rt2[i+1]==31))) { // DS touches $ra
9217 // Allocate the branch condition registers instead.
9221 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
9222 if(!((current.is32>>rs1[i])&1))
9224 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
9230 delayslot_alloc(¤t,i+1);
9234 // Don't alloc the delay slot yet because we might not execute it
9235 if((opcode2[i]&0x1E)==0x2) // BLTZL/BGEZL
9240 alloc_cc(¤t,i);
9241 dirty_reg(¤t,CCREG);
9242 alloc_reg(¤t,i,rs1[i]);
9243 if(!(current.is32>>rs1[i]&1))
9245 alloc_reg64(¤t,i,rs1[i]);
9249 //current.isconst=0;
9255 if(likely[i]==0) // BC1F/BC1T
9257 // TODO: Theoretically we can run out of registers here on x86.
9258 // The delay slot can allocate up to six, and we need to check
9259 // CSREG before executing the delay slot. Possibly we can drop
9260 // the cycle count and then reload it after checking that the
9261 // FPU is in a usable state, or don't do out-of-order execution.
9262 alloc_cc(¤t,i);
9263 dirty_reg(¤t,CCREG);
9264 alloc_reg(¤t,i,FSREG);
9265 alloc_reg(¤t,i,CSREG);
9266 if(itype[i+1]==FCOMP) {
9267 // The delay slot overwrites the branch condition.
9268 // Allocate the branch condition registers instead.
9269 alloc_cc(¤t,i);
9270 dirty_reg(¤t,CCREG);
9271 alloc_reg(¤t,i,CSREG);
9272 alloc_reg(¤t,i,FSREG);
9276 delayslot_alloc(¤t,i+1);
9277 alloc_reg(¤t,i+1,CSREG);
9281 // Don't alloc the delay slot yet because we might not execute it
9282 if(likely[i]) // BC1FL/BC1TL
9284 alloc_cc(¤t,i);
9285 dirty_reg(¤t,CCREG);
9286 alloc_reg(¤t,i,CSREG);
9287 alloc_reg(¤t,i,FSREG);
9293 imm16_alloc(¤t,i);
9297 load_alloc(¤t,i);
9301 store_alloc(¤t,i);
9304 alu_alloc(¤t,i);
9307 shift_alloc(¤t,i);
9310 multdiv_alloc(¤t,i);
9313 shiftimm_alloc(¤t,i);
9316 mov_alloc(¤t,i);
9319 cop0_alloc(¤t,i);
9323 cop1_alloc(¤t,i);
9326 c1ls_alloc(¤t,i);
9329 c2ls_alloc(¤t,i);
9332 c2op_alloc(¤t,i);
9335 fconv_alloc(¤t,i);
9338 float_alloc(¤t,i);
9341 fcomp_alloc(¤t,i);
9346 syscall_alloc(¤t,i);
9349 pagespan_alloc(¤t,i);
9353 // Drop the upper half of registers that have become 32-bit
9354 current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i]));
9355 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
9356 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9357 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9360 current.uu|=current.is32&((1LL<<rt1[i+1])|(1LL<<rt2[i+1]));
9361 current.uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
9362 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
9363 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9367 // Create entry (branch target) regmap
9368 for(hr=0;hr<HOST_REGS;hr++)
9371 r=current.regmap[hr];
9373 if(r!=regmap_pre[i][hr]) {
9374 // TODO: delay slot (?)
9375 or=get_reg(regmap_pre[i],r); // Get old mapping for this register
9376 if(or<0||(r&63)>=TEMPREG){
9377 regs[i].regmap_entry[hr]=-1;
9381 // Just move it to a different register
9382 regs[i].regmap_entry[hr]=r;
9383 // If it was dirty before, it's still dirty
9384 if((regs[i].wasdirty>>or)&1) dirty_reg(¤t,r&63);
9391 regs[i].regmap_entry[hr]=0;
9395 if((current.u>>r)&1) {
9396 regs[i].regmap_entry[hr]=-1;
9397 //regs[i].regmap[hr]=-1;
9398 current.regmap[hr]=-1;
9400 regs[i].regmap_entry[hr]=r;
9403 if((current.uu>>(r&63))&1) {
9404 regs[i].regmap_entry[hr]=-1;
9405 //regs[i].regmap[hr]=-1;
9406 current.regmap[hr]=-1;
9408 regs[i].regmap_entry[hr]=r;
9412 // Branches expect CCREG to be allocated at the target
9413 if(regmap_pre[i][hr]==CCREG)
9414 regs[i].regmap_entry[hr]=CCREG;
9416 regs[i].regmap_entry[hr]=-1;
9419 memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
9421 /* Branch post-alloc */
9424 current.was32=current.is32;
9425 current.wasdirty=current.dirty;
9426 switch(itype[i-1]) {
9428 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9429 branch_regs[i-1].isconst=0;
9430 branch_regs[i-1].wasconst=0;
9431 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9432 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9433 alloc_cc(&branch_regs[i-1],i-1);
9434 dirty_reg(&branch_regs[i-1],CCREG);
9435 if(rt1[i-1]==31) { // JAL
9436 alloc_reg(&branch_regs[i-1],i-1,31);
9437 dirty_reg(&branch_regs[i-1],31);
9438 branch_regs[i-1].is32|=1LL<<31;
9440 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9441 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9444 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9445 branch_regs[i-1].isconst=0;
9446 branch_regs[i-1].wasconst=0;
9447 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9448 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9449 alloc_cc(&branch_regs[i-1],i-1);
9450 dirty_reg(&branch_regs[i-1],CCREG);
9451 alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]);
9452 if(rt1[i-1]!=0) { // JALR
9453 alloc_reg(&branch_regs[i-1],i-1,rt1[i-1]);
9454 dirty_reg(&branch_regs[i-1],rt1[i-1]);
9455 branch_regs[i-1].is32|=1LL<<rt1[i-1];
9458 if(rs1[i-1]==31) { // JALR
9459 alloc_reg(&branch_regs[i-1],i-1,RHASH);
9460 #ifndef HOST_IMM_ADDR32
9461 alloc_reg(&branch_regs[i-1],i-1,RHTBL);
9465 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9466 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9469 if((opcode[i-1]&0x3E)==4) // BEQ/BNE
9471 alloc_cc(¤t,i-1);
9472 dirty_reg(¤t,CCREG);
9473 if((rs1[i-1]&&(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]))||
9474 (rs2[i-1]&&(rs2[i-1]==rt1[i]||rs2[i-1]==rt2[i]))) {
9475 // The delay slot overwrote one of our conditions
9476 // Delay slot goes after the test (in order)
9477 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9478 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9479 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9482 delayslot_alloc(¤t,i);
9487 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9488 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9489 // Alloc the branch condition registers
9490 if(rs1[i-1]) alloc_reg(¤t,i-1,rs1[i-1]);
9491 if(rs2[i-1]) alloc_reg(¤t,i-1,rs2[i-1]);
9492 if(!((current.is32>>rs1[i-1])&(current.is32>>rs2[i-1])&1))
9494 if(rs1[i-1]) alloc_reg64(¤t,i-1,rs1[i-1]);
9495 if(rs2[i-1]) alloc_reg64(¤t,i-1,rs2[i-1]);
9498 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9499 branch_regs[i-1].isconst=0;
9500 branch_regs[i-1].wasconst=0;
9501 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9502 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9505 if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ
9507 alloc_cc(¤t,i-1);
9508 dirty_reg(¤t,CCREG);
9509 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9510 // The delay slot overwrote the branch condition
9511 // Delay slot goes after the test (in order)
9512 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9513 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9514 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9517 delayslot_alloc(¤t,i);
9522 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9523 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9524 // Alloc the branch condition register
9525 alloc_reg(¤t,i-1,rs1[i-1]);
9526 if(!(current.is32>>rs1[i-1]&1))
9528 alloc_reg64(¤t,i-1,rs1[i-1]);
9531 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9532 branch_regs[i-1].isconst=0;
9533 branch_regs[i-1].wasconst=0;
9534 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9535 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9538 // Alloc the delay slot in case the branch is taken
9539 if((opcode[i-1]&0x3E)==0x14) // BEQL/BNEL
9541 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9542 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9543 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9544 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9545 alloc_cc(&branch_regs[i-1],i);
9546 dirty_reg(&branch_regs[i-1],CCREG);
9547 delayslot_alloc(&branch_regs[i-1],i);
9548 branch_regs[i-1].isconst=0;
9549 alloc_reg(¤t,i,CCREG); // Not taken path
9550 dirty_reg(¤t,CCREG);
9551 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9554 if((opcode[i-1]&0x3E)==0x16) // BLEZL/BGTZL
9556 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9557 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9558 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9559 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9560 alloc_cc(&branch_regs[i-1],i);
9561 dirty_reg(&branch_regs[i-1],CCREG);
9562 delayslot_alloc(&branch_regs[i-1],i);
9563 branch_regs[i-1].isconst=0;
9564 alloc_reg(¤t,i,CCREG); // Not taken path
9565 dirty_reg(¤t,CCREG);
9566 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9570 //if((opcode2[i-1]&0x1E)==0) // BLTZ/BGEZ
9571 if((opcode2[i-1]&0x0E)==0) // BLTZ/BGEZ
9573 alloc_cc(¤t,i-1);
9574 dirty_reg(¤t,CCREG);
9575 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9576 // The delay slot overwrote the branch condition
9577 // Delay slot goes after the test (in order)
9578 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9579 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9580 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9583 delayslot_alloc(¤t,i);
9588 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9589 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9590 // Alloc the branch condition register
9591 alloc_reg(¤t,i-1,rs1[i-1]);
9592 if(!(current.is32>>rs1[i-1]&1))
9594 alloc_reg64(¤t,i-1,rs1[i-1]);
9597 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9598 branch_regs[i-1].isconst=0;
9599 branch_regs[i-1].wasconst=0;
9600 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9601 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9604 // Alloc the delay slot in case the branch is taken
9605 if((opcode2[i-1]&0x1E)==2) // BLTZL/BGEZL
9607 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9608 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9609 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9610 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9611 alloc_cc(&branch_regs[i-1],i);
9612 dirty_reg(&branch_regs[i-1],CCREG);
9613 delayslot_alloc(&branch_regs[i-1],i);
9614 branch_regs[i-1].isconst=0;
9615 alloc_reg(¤t,i,CCREG); // Not taken path
9616 dirty_reg(¤t,CCREG);
9617 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9619 // FIXME: BLTZAL/BGEZAL
9620 if(opcode2[i-1]&0x10) { // BxxZAL
9621 alloc_reg(&branch_regs[i-1],i-1,31);
9622 dirty_reg(&branch_regs[i-1],31);
9623 branch_regs[i-1].is32|=1LL<<31;
9627 if(likely[i-1]==0) // BC1F/BC1T
9629 alloc_cc(¤t,i-1);
9630 dirty_reg(¤t,CCREG);
9631 if(itype[i]==FCOMP) {
9632 // The delay slot overwrote the branch condition
9633 // Delay slot goes after the test (in order)
9634 delayslot_alloc(¤t,i);
9639 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9640 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9641 // Alloc the branch condition register
9642 alloc_reg(¤t,i-1,FSREG);
9644 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9645 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9649 // Alloc the delay slot in case the branch is taken
9650 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9651 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9652 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9653 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9654 alloc_cc(&branch_regs[i-1],i);
9655 dirty_reg(&branch_regs[i-1],CCREG);
9656 delayslot_alloc(&branch_regs[i-1],i);
9657 branch_regs[i-1].isconst=0;
9658 alloc_reg(¤t,i,CCREG); // Not taken path
9659 dirty_reg(¤t,CCREG);
9660 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9665 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
9667 if(rt1[i-1]==31) // JAL/JALR
9669 // Subroutine call will return here, don't alloc any registers
9672 clear_all_regs(current.regmap);
9673 alloc_reg(¤t,i,CCREG);
9674 dirty_reg(¤t,CCREG);
9678 // Internal branch will jump here, match registers to caller
9679 current.is32=0x3FFFFFFFFLL;
9681 clear_all_regs(current.regmap);
9682 alloc_reg(¤t,i,CCREG);
9683 dirty_reg(¤t,CCREG);
9686 if(ba[j]==start+i*4+4) {
9687 memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
9688 current.is32=branch_regs[j].is32;
9689 current.dirty=branch_regs[j].dirty;
9694 if(ba[j]==start+i*4+4) {
9695 for(hr=0;hr<HOST_REGS;hr++) {
9696 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
9697 current.regmap[hr]=-1;
9699 current.is32&=branch_regs[j].is32;
9700 current.dirty&=branch_regs[j].dirty;
9709 // Count cycles in between branches
9711 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP||itype[i]==SYSCALL||itype[i]==HLECALL))
9716 else if(/*itype[i]==LOAD||*/itype[i]==STORE||itype[i]==C1LS) // load causes weird timing issues
9718 cc+=2; // 2 cycle penalty (after CLOCK_DIVIDER)
9720 else if(itype[i]==C2LS)
9730 flush_dirty_uppers(¤t);
9732 regs[i].is32=current.is32;
9733 regs[i].dirty=current.dirty;
9734 regs[i].isconst=current.isconst;
9735 memcpy(constmap[i],current.constmap,sizeof(current.constmap));
9737 for(hr=0;hr<HOST_REGS;hr++) {
9738 if(hr!=EXCLUDE_REG&®s[i].regmap[hr]>=0) {
9739 if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
9740 regs[i].wasconst&=~(1<<hr);
9744 if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
9747 /* Pass 4 - Cull unused host registers */
9751 for (i=slen-1;i>=0;i--)
9754 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9756 if(ba[i]<start || ba[i]>=(start+slen*4))
9758 // Branch out of this block, don't need anything
9764 // Need whatever matches the target
9766 int t=(ba[i]-start)>>2;
9767 for(hr=0;hr<HOST_REGS;hr++)
9769 if(regs[i].regmap_entry[hr]>=0) {
9770 if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
9774 // Conditional branch may need registers for following instructions
9775 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9778 nr|=needed_reg[i+2];
9779 for(hr=0;hr<HOST_REGS;hr++)
9781 if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
9782 //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
9786 // Don't need stuff which is overwritten
9787 //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9788 //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9789 // Merge in delay slot
9790 for(hr=0;hr<HOST_REGS;hr++)
9793 // These are overwritten unless the branch is "likely"
9794 // and the delay slot is nullified if not taken
9795 if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9796 if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9798 if(us1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9799 if(us2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9800 if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9801 if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9802 if(us1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9803 if(us2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9804 if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9805 if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9806 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1)) {
9807 if(dep1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9808 if(dep2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9810 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1)) {
9811 if(dep1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9812 if(dep2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9814 if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) {
9815 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9816 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9820 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
9822 // SYSCALL instruction (software interrupt)
9825 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
9827 // ERET instruction (return from interrupt)
9833 for(hr=0;hr<HOST_REGS;hr++) {
9834 if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
9835 if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
9836 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9837 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9841 for(hr=0;hr<HOST_REGS;hr++)
9843 // Overwritten registers are not needed
9844 if(rt1[i]&&rt1[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9845 if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9846 if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9847 // Source registers are needed
9848 if(us1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9849 if(us2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9850 if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr;
9851 if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr;
9852 if(us1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9853 if(us2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9854 if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9855 if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9856 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1)) {
9857 if(dep1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9858 if(dep1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9860 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1)) {
9861 if(dep2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9862 if(dep2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9864 if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) {
9865 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9866 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9868 // Don't store a register immediately after writing it,
9869 // may prevent dual-issue.
9870 // But do so if this is a branch target, otherwise we
9871 // might have to load the register before the branch.
9872 if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) {
9873 if((regmap_pre[i][hr]>0&®map_pre[i][hr]<64&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1)) ||
9874 (regmap_pre[i][hr]>64&&!((unneeded_reg_upper[i]>>(regmap_pre[i][hr]&63))&1)) ) {
9875 if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9876 if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9878 if((regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1)) ||
9879 (regs[i].regmap_entry[hr]>64&&!((unneeded_reg_upper[i]>>(regs[i].regmap_entry[hr]&63))&1)) ) {
9880 if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9881 if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9885 // Cycle count is needed at branches. Assume it is needed at the target too.
9886 if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==FJUMP||itype[i]==SPAN) {
9887 if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9888 if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9893 // Deallocate unneeded registers
9894 for(hr=0;hr<HOST_REGS;hr++)
9897 if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
9898 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9899 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9900 (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG)
9902 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9905 regs[i].regmap[hr]=-1;
9906 regs[i].isconst&=~(1<<hr);
9908 regmap_pre[i+2][hr]=-1;
9909 regs[i+2].wasconst&=~(1<<hr);
9914 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9916 int d1=0,d2=0,map=0,temp=0;
9917 if(get_reg(regs[i].regmap,rt1[i+1]|64)>=0||get_reg(branch_regs[i].regmap,rt1[i+1]|64)>=0)
9923 if(itype[i+1]==LOAD || itype[i+1]==LOADLR ||
9924 itype[i+1]==STORE || itype[i+1]==STORELR ||
9925 itype[i+1]==C1LS || itype[i+1]==C2LS)
9928 if(itype[i+1]==STORE || itype[i+1]==STORELR ||
9929 (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
9932 if(itype[i+1]==LOADLR || itype[i+1]==STORELR ||
9933 itype[i+1]==C1LS || itype[i+1]==C2LS)
9935 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9936 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9937 (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] &&
9938 (regs[i].regmap[hr]^64)!=us1[i+1] && (regs[i].regmap[hr]^64)!=us2[i+1] &&
9939 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9940 regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] &&
9941 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
9942 regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
9943 regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
9944 regs[i].regmap[hr]!=map )
9946 regs[i].regmap[hr]=-1;
9947 regs[i].isconst&=~(1<<hr);
9948 if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] &&
9949 (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] &&
9950 (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] &&
9951 (branch_regs[i].regmap[hr]^64)!=us1[i+1] && (branch_regs[i].regmap[hr]^64)!=us2[i+1] &&
9952 (branch_regs[i].regmap[hr]^64)!=d1 && (branch_regs[i].regmap[hr]^64)!=d2 &&
9953 branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] &&
9954 (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
9955 branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
9956 branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
9957 branch_regs[i].regmap[hr]!=map)
9959 branch_regs[i].regmap[hr]=-1;
9960 branch_regs[i].regmap_entry[hr]=-1;
9961 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9963 if(!likely[i]&&i<slen-2) {
9964 regmap_pre[i+2][hr]=-1;
9965 regs[i+2].wasconst&=~(1<<hr);
9976 int d1=0,d2=0,map=-1,temp=-1;
9977 if(get_reg(regs[i].regmap,rt1[i]|64)>=0)
9983 if(itype[i]==LOAD || itype[i]==LOADLR ||
9984 itype[i]==STORE || itype[i]==STORELR ||
9985 itype[i]==C1LS || itype[i]==C2LS)
9987 } else if(itype[i]==STORE || itype[i]==STORELR ||
9988 (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
9991 if(itype[i]==LOADLR || itype[i]==STORELR ||
9992 itype[i]==C1LS || itype[i]==C2LS)
9994 if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9995 (regs[i].regmap[hr]^64)!=us1[i] && (regs[i].regmap[hr]^64)!=us2[i] &&
9996 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9997 regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] &&
9998 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map &&
9999 (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG))
10001 if(i<slen-1&&!is_ds[i]) {
10002 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]!=-1)
10003 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
10004 if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
10006 printf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
10007 assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
10009 regmap_pre[i+1][hr]=-1;
10010 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
10011 regs[i+1].wasconst&=~(1<<hr);
10013 regs[i].regmap[hr]=-1;
10014 regs[i].isconst&=~(1<<hr);
10022 /* Pass 5 - Pre-allocate registers */
10024 // If a register is allocated during a loop, try to allocate it for the
10025 // entire loop, if possible. This avoids loading/storing registers
10026 // inside of the loop.
10028 signed char f_regmap[HOST_REGS];
10029 clear_all_regs(f_regmap);
10030 for(i=0;i<slen-1;i++)
10032 if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10034 if(ba[i]>=start && ba[i]<(start+i*4))
10035 if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
10036 ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
10037 ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
10038 ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
10039 ||itype[i+1]==FCOMP||itype[i+1]==FCONV
10040 ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
10042 int t=(ba[i]-start)>>2;
10043 if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots
10044 if(t<2||(itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||rt1[t-2]!=31) // call/ret assumes no registers allocated
10045 for(hr=0;hr<HOST_REGS;hr++)
10047 if(regs[i].regmap[hr]>64) {
10048 if(!((regs[i].dirty>>hr)&1))
10049 f_regmap[hr]=regs[i].regmap[hr];
10050 else f_regmap[hr]=-1;
10052 else if(regs[i].regmap[hr]>=0) {
10053 if(f_regmap[hr]!=regs[i].regmap[hr]) {
10054 // dealloc old register
10056 for(n=0;n<HOST_REGS;n++)
10058 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
10060 // and alloc new one
10061 f_regmap[hr]=regs[i].regmap[hr];
10064 if(branch_regs[i].regmap[hr]>64) {
10065 if(!((branch_regs[i].dirty>>hr)&1))
10066 f_regmap[hr]=branch_regs[i].regmap[hr];
10067 else f_regmap[hr]=-1;
10069 else if(branch_regs[i].regmap[hr]>=0) {
10070 if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
10071 // dealloc old register
10073 for(n=0;n<HOST_REGS;n++)
10075 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
10077 // and alloc new one
10078 f_regmap[hr]=branch_regs[i].regmap[hr];
10082 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
10083 f_regmap[hr]=branch_regs[i].regmap[hr];
10085 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
10086 f_regmap[hr]=branch_regs[i].regmap[hr];
10088 // Avoid dirty->clean transition
10089 #ifdef DESTRUCTIVE_WRITEBACK
10090 if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
10092 // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
10093 // case above, however it's always a good idea. We can't hoist the
10094 // load if the register was already allocated, so there's no point
10095 // wasting time analyzing most of these cases. It only "succeeds"
10096 // when the mapping was different and the load can be replaced with
10097 // a mov, which is of negligible benefit. So such cases are
10099 if(f_regmap[hr]>0) {
10100 if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
10101 int r=f_regmap[hr];
10104 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
10105 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
10106 if(r>63&&((unneeded_reg_upper[j]>>(r&63))&1)) break;
10108 // NB This can exclude the case where the upper-half
10109 // register is lower numbered than the lower-half
10110 // register. Not sure if it's worth fixing...
10111 if(get_reg(regs[j].regmap,r&63)<0) break;
10112 if(get_reg(regs[j].regmap_entry,r&63)<0) break;
10113 if(regs[j].is32&(1LL<<(r&63))) break;
10115 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
10116 //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
10118 if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
10119 if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
10121 if(get_reg(regs[i].regmap,r&63)<0) break;
10122 if(get_reg(branch_regs[i].regmap,r&63)<0) break;
10125 while(k>1&®s[k-1].regmap[hr]==-1) {
10126 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10127 //printf("no free regs for store %x\n",start+(k-1)*4);
10130 if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
10131 //printf("no-match due to different register\n");
10134 if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP||itype[k-2]==FJUMP) {
10135 //printf("no-match due to branch\n");
10138 // call/ret fast path assumes no registers allocated
10139 if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)&&rt1[k-3]==31) {
10143 // NB This can exclude the case where the upper-half
10144 // register is lower numbered than the lower-half
10145 // register. Not sure if it's worth fixing...
10146 if(get_reg(regs[k-1].regmap,r&63)<0) break;
10147 if(regs[k-1].is32&(1LL<<(r&63))) break;
10152 if((regs[k].is32&(1LL<<f_regmap[hr]))!=
10153 (regs[i+2].was32&(1LL<<f_regmap[hr]))) {
10154 //printf("bad match after branch\n");
10158 if(regs[k-1].regmap[hr]==f_regmap[hr]&®map_pre[k][hr]==f_regmap[hr]) {
10159 //printf("Extend r%d, %x ->\n",hr,start+k*4);
10161 regs[k].regmap_entry[hr]=f_regmap[hr];
10162 regs[k].regmap[hr]=f_regmap[hr];
10163 regmap_pre[k+1][hr]=f_regmap[hr];
10164 regs[k].wasdirty&=~(1<<hr);
10165 regs[k].dirty&=~(1<<hr);
10166 regs[k].wasdirty|=(1<<hr)®s[k-1].dirty;
10167 regs[k].dirty|=(1<<hr)®s[k].wasdirty;
10168 regs[k].wasconst&=~(1<<hr);
10169 regs[k].isconst&=~(1<<hr);
10174 //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
10177 assert(regs[i-1].regmap[hr]==f_regmap[hr]);
10178 if(regs[i-1].regmap[hr]==f_regmap[hr]&®map_pre[i][hr]==f_regmap[hr]) {
10179 //printf("OK fill %x (r%d)\n",start+i*4,hr);
10180 regs[i].regmap_entry[hr]=f_regmap[hr];
10181 regs[i].regmap[hr]=f_regmap[hr];
10182 regs[i].wasdirty&=~(1<<hr);
10183 regs[i].dirty&=~(1<<hr);
10184 regs[i].wasdirty|=(1<<hr)®s[i-1].dirty;
10185 regs[i].dirty|=(1<<hr)®s[i-1].dirty;
10186 regs[i].wasconst&=~(1<<hr);
10187 regs[i].isconst&=~(1<<hr);
10188 branch_regs[i].regmap_entry[hr]=f_regmap[hr];
10189 branch_regs[i].wasdirty&=~(1<<hr);
10190 branch_regs[i].wasdirty|=(1<<hr)®s[i].dirty;
10191 branch_regs[i].regmap[hr]=f_regmap[hr];
10192 branch_regs[i].dirty&=~(1<<hr);
10193 branch_regs[i].dirty|=(1<<hr)®s[i].dirty;
10194 branch_regs[i].wasconst&=~(1<<hr);
10195 branch_regs[i].isconst&=~(1<<hr);
10196 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
10197 regmap_pre[i+2][hr]=f_regmap[hr];
10198 regs[i+2].wasdirty&=~(1<<hr);
10199 regs[i+2].wasdirty|=(1<<hr)®s[i].dirty;
10200 assert((branch_regs[i].is32&(1LL<<f_regmap[hr]))==
10201 (regs[i+2].was32&(1LL<<f_regmap[hr])));
10206 // Alloc register clean at beginning of loop,
10207 // but may dirty it in pass 6
10208 regs[k].regmap_entry[hr]=f_regmap[hr];
10209 regs[k].regmap[hr]=f_regmap[hr];
10210 regs[k].dirty&=~(1<<hr);
10211 regs[k].wasconst&=~(1<<hr);
10212 regs[k].isconst&=~(1<<hr);
10213 if(itype[k]==UJUMP||itype[k]==RJUMP||itype[k]==CJUMP||itype[k]==SJUMP||itype[k]==FJUMP) {
10214 branch_regs[k].regmap_entry[hr]=f_regmap[hr];
10215 branch_regs[k].regmap[hr]=f_regmap[hr];
10216 branch_regs[k].dirty&=~(1<<hr);
10217 branch_regs[k].wasconst&=~(1<<hr);
10218 branch_regs[k].isconst&=~(1<<hr);
10219 if(itype[k]!=RJUMP&&itype[k]!=UJUMP&&(source[k]>>16)!=0x1000) {
10220 regmap_pre[k+2][hr]=f_regmap[hr];
10221 regs[k+2].wasdirty&=~(1<<hr);
10222 assert((branch_regs[k].is32&(1LL<<f_regmap[hr]))==
10223 (regs[k+2].was32&(1LL<<f_regmap[hr])));
10228 regmap_pre[k+1][hr]=f_regmap[hr];
10229 regs[k+1].wasdirty&=~(1<<hr);
10232 if(regs[j].regmap[hr]==f_regmap[hr])
10233 regs[j].regmap_entry[hr]=f_regmap[hr];
10237 if(regs[j].regmap[hr]>=0)
10239 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
10240 //printf("no-match due to different register\n");
10243 if((regs[j+1].is32&(1LL<<f_regmap[hr]))!=(regs[j].is32&(1LL<<f_regmap[hr]))) {
10244 //printf("32/64 mismatch %x %d\n",start+j*4,hr);
10247 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10249 // Stop on unconditional branch
10252 if(itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP)
10255 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
10258 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
10261 if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
10262 //printf("no-match due to different register (branch)\n");
10266 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10267 //printf("No free regs for store %x\n",start+j*4);
10270 if(f_regmap[hr]>=64) {
10271 if(regs[j].is32&(1LL<<(f_regmap[hr]&63))) {
10276 if(get_reg(regs[j].regmap,f_regmap[hr]&63)<0) {
10287 // Non branch or undetermined branch target
10288 for(hr=0;hr<HOST_REGS;hr++)
10290 if(hr!=EXCLUDE_REG) {
10291 if(regs[i].regmap[hr]>64) {
10292 if(!((regs[i].dirty>>hr)&1))
10293 f_regmap[hr]=regs[i].regmap[hr];
10295 else if(regs[i].regmap[hr]>=0) {
10296 if(f_regmap[hr]!=regs[i].regmap[hr]) {
10297 // dealloc old register
10299 for(n=0;n<HOST_REGS;n++)
10301 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
10303 // and alloc new one
10304 f_regmap[hr]=regs[i].regmap[hr];
10309 // Try to restore cycle count at branch targets
10311 for(j=i;j<slen-1;j++) {
10312 if(regs[j].regmap[HOST_CCREG]!=-1) break;
10313 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10314 //printf("no free regs for store %x\n",start+j*4);
10318 if(regs[j].regmap[HOST_CCREG]==CCREG) {
10320 //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
10322 regs[k].regmap_entry[HOST_CCREG]=CCREG;
10323 regs[k].regmap[HOST_CCREG]=CCREG;
10324 regmap_pre[k+1][HOST_CCREG]=CCREG;
10325 regs[k+1].wasdirty|=1<<HOST_CCREG;
10326 regs[k].dirty|=1<<HOST_CCREG;
10327 regs[k].wasconst&=~(1<<HOST_CCREG);
10328 regs[k].isconst&=~(1<<HOST_CCREG);
10331 regs[j].regmap_entry[HOST_CCREG]=CCREG;
10333 // Work backwards from the branch target
10334 if(j>i&&f_regmap[HOST_CCREG]==CCREG)
10336 //printf("Extend backwards\n");
10339 while(regs[k-1].regmap[HOST_CCREG]==-1) {
10340 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10341 //printf("no free regs for store %x\n",start+(k-1)*4);
10346 if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
10347 //printf("Extend CC, %x ->\n",start+k*4);
10349 regs[k].regmap_entry[HOST_CCREG]=CCREG;
10350 regs[k].regmap[HOST_CCREG]=CCREG;
10351 regmap_pre[k+1][HOST_CCREG]=CCREG;
10352 regs[k+1].wasdirty|=1<<HOST_CCREG;
10353 regs[k].dirty|=1<<HOST_CCREG;
10354 regs[k].wasconst&=~(1<<HOST_CCREG);
10355 regs[k].isconst&=~(1<<HOST_CCREG);
10360 //printf("Fail Extend CC, %x ->\n",start+k*4);
10364 if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&&
10365 itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&&
10366 itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1&&itype[i]!=FLOAT&&
10367 itype[i]!=FCONV&&itype[i]!=FCOMP)
10369 memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
10374 // Cache memory offset or tlb map pointer if a register is available
10375 #ifndef HOST_IMM_ADDR32
10380 int earliest_available[HOST_REGS];
10381 int loop_start[HOST_REGS];
10382 int score[HOST_REGS];
10383 int end[HOST_REGS];
10384 int reg=using_tlb?MMREG:ROREG;
10387 for(hr=0;hr<HOST_REGS;hr++) {
10388 score[hr]=0;earliest_available[hr]=0;
10389 loop_start[hr]=MAXBLOCK;
10391 for(i=0;i<slen-1;i++)
10393 // Can't do anything if no registers are available
10394 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i]) {
10395 for(hr=0;hr<HOST_REGS;hr++) {
10396 score[hr]=0;earliest_available[hr]=i+1;
10397 loop_start[hr]=MAXBLOCK;
10400 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10402 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1]) {
10403 for(hr=0;hr<HOST_REGS;hr++) {
10404 score[hr]=0;earliest_available[hr]=i+1;
10405 loop_start[hr]=MAXBLOCK;
10409 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1]) {
10410 for(hr=0;hr<HOST_REGS;hr++) {
10411 score[hr]=0;earliest_available[hr]=i+1;
10412 loop_start[hr]=MAXBLOCK;
10417 // Mark unavailable registers
10418 for(hr=0;hr<HOST_REGS;hr++) {
10419 if(regs[i].regmap[hr]>=0) {
10420 score[hr]=0;earliest_available[hr]=i+1;
10421 loop_start[hr]=MAXBLOCK;
10423 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10424 if(branch_regs[i].regmap[hr]>=0) {
10425 score[hr]=0;earliest_available[hr]=i+2;
10426 loop_start[hr]=MAXBLOCK;
10430 // No register allocations after unconditional jumps
10431 if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
10433 for(hr=0;hr<HOST_REGS;hr++) {
10434 score[hr]=0;earliest_available[hr]=i+2;
10435 loop_start[hr]=MAXBLOCK;
10437 i++; // Skip delay slot too
10438 //printf("skip delay slot: %x\n",start+i*4);
10442 if(itype[i]==LOAD||itype[i]==LOADLR||
10443 itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS) {
10444 for(hr=0;hr<HOST_REGS;hr++) {
10445 if(hr!=EXCLUDE_REG) {
10447 for(j=i;j<slen-1;j++) {
10448 if(regs[j].regmap[hr]>=0) break;
10449 if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10450 if(branch_regs[j].regmap[hr]>=0) break;
10452 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1]) break;
10454 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1]) break;
10457 else if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) break;
10458 if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10459 int t=(ba[j]-start)>>2;
10460 if(t<j&&t>=earliest_available[hr]) {
10461 if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) { // call/ret assumes no registers allocated
10462 // Score a point for hoisting loop invariant
10463 if(t<loop_start[hr]) loop_start[hr]=t;
10464 //printf("set loop_start: i=%x j=%x (%x)\n",start+i*4,start+j*4,start+t*4);
10470 if(regs[t].regmap[hr]==reg) {
10471 // Score a point if the branch target matches this register
10476 if(itype[j+1]==LOAD||itype[j+1]==LOADLR||
10477 itype[j+1]==STORE||itype[j+1]==STORELR||itype[j+1]==C1LS) {
10482 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10484 // Stop on unconditional branch
10488 if(itype[j]==LOAD||itype[j]==LOADLR||
10489 itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS) {
10496 // Find highest score and allocate that register
10498 for(hr=0;hr<HOST_REGS;hr++) {
10499 if(hr!=EXCLUDE_REG) {
10500 if(score[hr]>score[maxscore]) {
10502 //printf("highest score: %d %d (%x->%x)\n",score[hr],hr,start+i*4,start+end[hr]*4);
10506 if(score[maxscore]>1)
10508 if(i<loop_start[maxscore]) loop_start[maxscore]=i;
10509 for(j=loop_start[maxscore];j<slen&&j<=end[maxscore];j++) {
10510 //if(regs[j].regmap[maxscore]>=0) {printf("oops: %x %x was %d=%d\n",loop_start[maxscore]*4+start,j*4+start,maxscore,regs[j].regmap[maxscore]);}
10511 assert(regs[j].regmap[maxscore]<0);
10512 if(j>loop_start[maxscore]) regs[j].regmap_entry[maxscore]=reg;
10513 regs[j].regmap[maxscore]=reg;
10514 regs[j].dirty&=~(1<<maxscore);
10515 regs[j].wasconst&=~(1<<maxscore);
10516 regs[j].isconst&=~(1<<maxscore);
10517 if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10518 branch_regs[j].regmap[maxscore]=reg;
10519 branch_regs[j].wasdirty&=~(1<<maxscore);
10520 branch_regs[j].dirty&=~(1<<maxscore);
10521 branch_regs[j].wasconst&=~(1<<maxscore);
10522 branch_regs[j].isconst&=~(1<<maxscore);
10523 if(itype[j]!=RJUMP&&itype[j]!=UJUMP&&(source[j]>>16)!=0x1000) {
10524 regmap_pre[j+2][maxscore]=reg;
10525 regs[j+2].wasdirty&=~(1<<maxscore);
10527 // loop optimization (loop_preload)
10528 int t=(ba[j]-start)>>2;
10529 if(t==loop_start[maxscore]) {
10530 if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) // call/ret assumes no registers allocated
10531 regs[t].regmap_entry[maxscore]=reg;
10536 if(j<1||(itype[j-1]!=RJUMP&&itype[j-1]!=UJUMP&&itype[j-1]!=CJUMP&&itype[j-1]!=SJUMP&&itype[j-1]!=FJUMP)) {
10537 regmap_pre[j+1][maxscore]=reg;
10538 regs[j+1].wasdirty&=~(1<<maxscore);
10543 if(itype[j-1]==RJUMP||itype[j-1]==UJUMP||itype[j-1]==CJUMP||itype[j-1]==SJUMP||itype[j-1]==FJUMP) i++; // skip delay slot
10544 for(hr=0;hr<HOST_REGS;hr++) {
10545 score[hr]=0;earliest_available[hr]=i+i;
10546 loop_start[hr]=MAXBLOCK;
10554 // This allocates registers (if possible) one instruction prior
10555 // to use, which can avoid a load-use penalty on certain CPUs.
10556 for(i=0;i<slen-1;i++)
10558 if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP))
10562 if(itype[i]==ALU||itype[i]==MOV||itype[i]==LOAD||itype[i]==SHIFTIMM||itype[i]==IMM16
10563 ||((itype[i]==COP1||itype[i]==COP2)&&opcode2[i]<3))
10566 if((hr=get_reg(regs[i+1].regmap,rs1[i+1]))>=0)
10568 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10570 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10571 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10572 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10573 regs[i].isconst&=~(1<<hr);
10574 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10575 constmap[i][hr]=constmap[i+1][hr];
10576 regs[i+1].wasdirty&=~(1<<hr);
10577 regs[i].dirty&=~(1<<hr);
10582 if((hr=get_reg(regs[i+1].regmap,rs2[i+1]))>=0)
10584 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10586 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10587 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10588 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10589 regs[i].isconst&=~(1<<hr);
10590 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10591 constmap[i][hr]=constmap[i+1][hr];
10592 regs[i+1].wasdirty&=~(1<<hr);
10593 regs[i].dirty&=~(1<<hr);
10597 // Preload target address for load instruction (non-constant)
10598 if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10599 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10601 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10603 regs[i].regmap[hr]=rs1[i+1];
10604 regmap_pre[i+1][hr]=rs1[i+1];
10605 regs[i+1].regmap_entry[hr]=rs1[i+1];
10606 regs[i].isconst&=~(1<<hr);
10607 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10608 constmap[i][hr]=constmap[i+1][hr];
10609 regs[i+1].wasdirty&=~(1<<hr);
10610 regs[i].dirty&=~(1<<hr);
10614 // Load source into target register
10615 if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10616 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10618 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10620 regs[i].regmap[hr]=rs1[i+1];
10621 regmap_pre[i+1][hr]=rs1[i+1];
10622 regs[i+1].regmap_entry[hr]=rs1[i+1];
10623 regs[i].isconst&=~(1<<hr);
10624 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10625 constmap[i][hr]=constmap[i+1][hr];
10626 regs[i+1].wasdirty&=~(1<<hr);
10627 regs[i].dirty&=~(1<<hr);
10631 // Preload map address
10632 #ifndef HOST_IMM_ADDR32
10633 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
10634 hr=get_reg(regs[i+1].regmap,TLREG);
10636 int sr=get_reg(regs[i+1].regmap,rs1[i+1]);
10637 if(sr>=0&&((regs[i+1].wasconst>>sr)&1)) {
10639 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10641 regs[i].regmap[hr]=MGEN1+((i+1)&1);
10642 regmap_pre[i+1][hr]=MGEN1+((i+1)&1);
10643 regs[i+1].regmap_entry[hr]=MGEN1+((i+1)&1);
10644 regs[i].isconst&=~(1<<hr);
10645 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10646 constmap[i][hr]=constmap[i+1][hr];
10647 regs[i+1].wasdirty&=~(1<<hr);
10648 regs[i].dirty&=~(1<<hr);
10650 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10652 // move it to another register
10653 regs[i+1].regmap[hr]=-1;
10654 regmap_pre[i+2][hr]=-1;
10655 regs[i+1].regmap[nr]=TLREG;
10656 regmap_pre[i+2][nr]=TLREG;
10657 regs[i].regmap[nr]=MGEN1+((i+1)&1);
10658 regmap_pre[i+1][nr]=MGEN1+((i+1)&1);
10659 regs[i+1].regmap_entry[nr]=MGEN1+((i+1)&1);
10660 regs[i].isconst&=~(1<<nr);
10661 regs[i+1].isconst&=~(1<<nr);
10662 regs[i].dirty&=~(1<<nr);
10663 regs[i+1].wasdirty&=~(1<<nr);
10664 regs[i+1].dirty&=~(1<<nr);
10665 regs[i+2].wasdirty&=~(1<<nr);
10671 // Address for store instruction (non-constant)
10672 if(itype[i+1]==STORE||itype[i+1]==STORELR
10673 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
10674 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10675 hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
10676 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10677 else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
10679 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10681 regs[i].regmap[hr]=rs1[i+1];
10682 regmap_pre[i+1][hr]=rs1[i+1];
10683 regs[i+1].regmap_entry[hr]=rs1[i+1];
10684 regs[i].isconst&=~(1<<hr);
10685 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10686 constmap[i][hr]=constmap[i+1][hr];
10687 regs[i+1].wasdirty&=~(1<<hr);
10688 regs[i].dirty&=~(1<<hr);
10692 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
10693 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10695 hr=get_reg(regs[i+1].regmap,FTEMP);
10697 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10699 regs[i].regmap[hr]=rs1[i+1];
10700 regmap_pre[i+1][hr]=rs1[i+1];
10701 regs[i+1].regmap_entry[hr]=rs1[i+1];
10702 regs[i].isconst&=~(1<<hr);
10703 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10704 constmap[i][hr]=constmap[i+1][hr];
10705 regs[i+1].wasdirty&=~(1<<hr);
10706 regs[i].dirty&=~(1<<hr);
10708 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10710 // move it to another register
10711 regs[i+1].regmap[hr]=-1;
10712 regmap_pre[i+2][hr]=-1;
10713 regs[i+1].regmap[nr]=FTEMP;
10714 regmap_pre[i+2][nr]=FTEMP;
10715 regs[i].regmap[nr]=rs1[i+1];
10716 regmap_pre[i+1][nr]=rs1[i+1];
10717 regs[i+1].regmap_entry[nr]=rs1[i+1];
10718 regs[i].isconst&=~(1<<nr);
10719 regs[i+1].isconst&=~(1<<nr);
10720 regs[i].dirty&=~(1<<nr);
10721 regs[i+1].wasdirty&=~(1<<nr);
10722 regs[i+1].dirty&=~(1<<nr);
10723 regs[i+2].wasdirty&=~(1<<nr);
10727 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS||||itype[i+1]==C2LS*/) {
10728 if(itype[i+1]==LOAD)
10729 hr=get_reg(regs[i+1].regmap,rt1[i+1]);
10730 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
10731 hr=get_reg(regs[i+1].regmap,FTEMP);
10732 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
10733 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
10734 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10736 if(hr>=0&®s[i].regmap[hr]<0) {
10737 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
10738 if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
10739 regs[i].regmap[hr]=AGEN1+((i+1)&1);
10740 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
10741 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
10742 regs[i].isconst&=~(1<<hr);
10743 regs[i+1].wasdirty&=~(1<<hr);
10744 regs[i].dirty&=~(1<<hr);
10753 /* Pass 6 - Optimize clean/dirty state */
10754 clean_registers(0,slen-1,1);
10756 /* Pass 7 - Identify 32-bit registers */
10762 for (i=slen-1;i>=0;i--)
10765 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10767 if(ba[i]<start || ba[i]>=(start+slen*4))
10769 // Branch out of this block, don't need anything
10775 // Need whatever matches the target
10776 // (and doesn't get overwritten by the delay slot instruction)
10778 int t=(ba[i]-start)>>2;
10779 if(ba[i]>start+i*4) {
10781 if(!(requires_32bit[t]&~regs[i].was32))
10782 r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10785 //if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
10786 // r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10787 if(!(pr32[t]&~regs[i].was32))
10788 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10791 // Conditional branch may need registers for following instructions
10792 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10795 r32|=requires_32bit[i+2];
10796 r32&=regs[i].was32;
10797 // Mark this address as a branch target since it may be called
10798 // upon return from interrupt
10802 // Merge in delay slot
10804 // These are overwritten unless the branch is "likely"
10805 // and the delay slot is nullified if not taken
10806 r32&=~(1LL<<rt1[i+1]);
10807 r32&=~(1LL<<rt2[i+1]);
10809 // Assume these are needed (delay slot)
10812 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
10816 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
10818 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
10820 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
10822 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
10824 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
10827 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
10829 // SYSCALL instruction (software interrupt)
10832 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
10834 // ERET instruction (return from interrupt)
10838 r32&=~(1LL<<rt1[i]);
10839 r32&=~(1LL<<rt2[i]);
10842 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
10846 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
10848 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
10850 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
10852 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
10854 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
10856 requires_32bit[i]=r32;
10858 // Dirty registers which are 32-bit, require 32-bit input
10859 // as they will be written as 32-bit values
10860 for(hr=0;hr<HOST_REGS;hr++)
10862 if(regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64) {
10863 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
10864 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
10865 requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
10869 //requires_32bit[i]=is32[i]&~unneeded_reg_upper[i]; // DEBUG
10872 for (i=slen-1;i>=0;i--)
10874 if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10876 // Conditional branch
10877 if((source[i]>>16)!=0x1000&&i<slen-2) {
10878 // Mark this address as a branch target since it may be called
10879 // upon return from interrupt
10886 if(itype[slen-1]==SPAN) {
10887 bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
10890 /* Debug/disassembly */
10891 if((void*)assem_debug==(void*)printf)
10892 for(i=0;i<slen;i++)
10896 for(r=1;r<=CCREG;r++) {
10897 if((unneeded_reg[i]>>r)&1) {
10898 if(r==HIREG) printf(" HI");
10899 else if(r==LOREG) printf(" LO");
10900 else printf(" r%d",r);
10905 for(r=1;r<=CCREG;r++) {
10906 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
10907 if(r==HIREG) printf(" HI");
10908 else if(r==LOREG) printf(" LO");
10909 else printf(" r%d",r);
10913 for(r=0;r<=CCREG;r++) {
10914 //if(((is32[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10915 if((regs[i].was32>>r)&1) {
10916 if(r==CCREG) printf(" CC");
10917 else if(r==HIREG) printf(" HI");
10918 else if(r==LOREG) printf(" LO");
10919 else printf(" r%d",r);
10924 #if defined(__i386__) || defined(__x86_64__)
10925 printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
10928 printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
10931 if(needed_reg[i]&1) printf("eax ");
10932 if((needed_reg[i]>>1)&1) printf("ecx ");
10933 if((needed_reg[i]>>2)&1) printf("edx ");
10934 if((needed_reg[i]>>3)&1) printf("ebx ");
10935 if((needed_reg[i]>>5)&1) printf("ebp ");
10936 if((needed_reg[i]>>6)&1) printf("esi ");
10937 if((needed_reg[i]>>7)&1) printf("edi ");
10939 for(r=0;r<=CCREG;r++) {
10940 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10941 if((requires_32bit[i]>>r)&1) {
10942 if(r==CCREG) printf(" CC");
10943 else if(r==HIREG) printf(" HI");
10944 else if(r==LOREG) printf(" LO");
10945 else printf(" r%d",r);
10950 for(r=0;r<=CCREG;r++) {
10951 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10952 if((pr32[i]>>r)&1) {
10953 if(r==CCREG) printf(" CC");
10954 else if(r==HIREG) printf(" HI");
10955 else if(r==LOREG) printf(" LO");
10956 else printf(" r%d",r);
10959 if(pr32[i]!=requires_32bit[i]) printf(" OOPS");
10961 #if defined(__i386__) || defined(__x86_64__)
10962 printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
10964 if(regs[i].wasdirty&1) printf("eax ");
10965 if((regs[i].wasdirty>>1)&1) printf("ecx ");
10966 if((regs[i].wasdirty>>2)&1) printf("edx ");
10967 if((regs[i].wasdirty>>3)&1) printf("ebx ");
10968 if((regs[i].wasdirty>>5)&1) printf("ebp ");
10969 if((regs[i].wasdirty>>6)&1) printf("esi ");
10970 if((regs[i].wasdirty>>7)&1) printf("edi ");
10973 printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
10975 if(regs[i].wasdirty&1) printf("r0 ");
10976 if((regs[i].wasdirty>>1)&1) printf("r1 ");
10977 if((regs[i].wasdirty>>2)&1) printf("r2 ");
10978 if((regs[i].wasdirty>>3)&1) printf("r3 ");
10979 if((regs[i].wasdirty>>4)&1) printf("r4 ");
10980 if((regs[i].wasdirty>>5)&1) printf("r5 ");
10981 if((regs[i].wasdirty>>6)&1) printf("r6 ");
10982 if((regs[i].wasdirty>>7)&1) printf("r7 ");
10983 if((regs[i].wasdirty>>8)&1) printf("r8 ");
10984 if((regs[i].wasdirty>>9)&1) printf("r9 ");
10985 if((regs[i].wasdirty>>10)&1) printf("r10 ");
10986 if((regs[i].wasdirty>>12)&1) printf("r12 ");
10989 disassemble_inst(i);
10990 //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
10991 #if defined(__i386__) || defined(__x86_64__)
10992 printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
10993 if(regs[i].dirty&1) printf("eax ");
10994 if((regs[i].dirty>>1)&1) printf("ecx ");
10995 if((regs[i].dirty>>2)&1) printf("edx ");
10996 if((regs[i].dirty>>3)&1) printf("ebx ");
10997 if((regs[i].dirty>>5)&1) printf("ebp ");
10998 if((regs[i].dirty>>6)&1) printf("esi ");
10999 if((regs[i].dirty>>7)&1) printf("edi ");
11002 printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
11003 if(regs[i].dirty&1) printf("r0 ");
11004 if((regs[i].dirty>>1)&1) printf("r1 ");
11005 if((regs[i].dirty>>2)&1) printf("r2 ");
11006 if((regs[i].dirty>>3)&1) printf("r3 ");
11007 if((regs[i].dirty>>4)&1) printf("r4 ");
11008 if((regs[i].dirty>>5)&1) printf("r5 ");
11009 if((regs[i].dirty>>6)&1) printf("r6 ");
11010 if((regs[i].dirty>>7)&1) printf("r7 ");
11011 if((regs[i].dirty>>8)&1) printf("r8 ");
11012 if((regs[i].dirty>>9)&1) printf("r9 ");
11013 if((regs[i].dirty>>10)&1) printf("r10 ");
11014 if((regs[i].dirty>>12)&1) printf("r12 ");
11017 if(regs[i].isconst) {
11018 printf("constants: ");
11019 #if defined(__i386__) || defined(__x86_64__)
11020 if(regs[i].isconst&1) printf("eax=%x ",(int)constmap[i][0]);
11021 if((regs[i].isconst>>1)&1) printf("ecx=%x ",(int)constmap[i][1]);
11022 if((regs[i].isconst>>2)&1) printf("edx=%x ",(int)constmap[i][2]);
11023 if((regs[i].isconst>>3)&1) printf("ebx=%x ",(int)constmap[i][3]);
11024 if((regs[i].isconst>>5)&1) printf("ebp=%x ",(int)constmap[i][5]);
11025 if((regs[i].isconst>>6)&1) printf("esi=%x ",(int)constmap[i][6]);
11026 if((regs[i].isconst>>7)&1) printf("edi=%x ",(int)constmap[i][7]);
11029 if(regs[i].isconst&1) printf("r0=%x ",(int)constmap[i][0]);
11030 if((regs[i].isconst>>1)&1) printf("r1=%x ",(int)constmap[i][1]);
11031 if((regs[i].isconst>>2)&1) printf("r2=%x ",(int)constmap[i][2]);
11032 if((regs[i].isconst>>3)&1) printf("r3=%x ",(int)constmap[i][3]);
11033 if((regs[i].isconst>>4)&1) printf("r4=%x ",(int)constmap[i][4]);
11034 if((regs[i].isconst>>5)&1) printf("r5=%x ",(int)constmap[i][5]);
11035 if((regs[i].isconst>>6)&1) printf("r6=%x ",(int)constmap[i][6]);
11036 if((regs[i].isconst>>7)&1) printf("r7=%x ",(int)constmap[i][7]);
11037 if((regs[i].isconst>>8)&1) printf("r8=%x ",(int)constmap[i][8]);
11038 if((regs[i].isconst>>9)&1) printf("r9=%x ",(int)constmap[i][9]);
11039 if((regs[i].isconst>>10)&1) printf("r10=%x ",(int)constmap[i][10]);
11040 if((regs[i].isconst>>12)&1) printf("r12=%x ",(int)constmap[i][12]);
11046 for(r=0;r<=CCREG;r++) {
11047 if((regs[i].is32>>r)&1) {
11048 if(r==CCREG) printf(" CC");
11049 else if(r==HIREG) printf(" HI");
11050 else if(r==LOREG) printf(" LO");
11051 else printf(" r%d",r);
11057 for(r=0;r<=CCREG;r++) {
11058 if((p32[i]>>r)&1) {
11059 if(r==CCREG) printf(" CC");
11060 else if(r==HIREG) printf(" HI");
11061 else if(r==LOREG) printf(" LO");
11062 else printf(" r%d",r);
11065 if(p32[i]!=regs[i].is32) printf(" NO MATCH\n");
11066 else printf("\n");*/
11067 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
11068 #if defined(__i386__) || defined(__x86_64__)
11069 printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
11070 if(branch_regs[i].dirty&1) printf("eax ");
11071 if((branch_regs[i].dirty>>1)&1) printf("ecx ");
11072 if((branch_regs[i].dirty>>2)&1) printf("edx ");
11073 if((branch_regs[i].dirty>>3)&1) printf("ebx ");
11074 if((branch_regs[i].dirty>>5)&1) printf("ebp ");
11075 if((branch_regs[i].dirty>>6)&1) printf("esi ");
11076 if((branch_regs[i].dirty>>7)&1) printf("edi ");
11079 printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
11080 if(branch_regs[i].dirty&1) printf("r0 ");
11081 if((branch_regs[i].dirty>>1)&1) printf("r1 ");
11082 if((branch_regs[i].dirty>>2)&1) printf("r2 ");
11083 if((branch_regs[i].dirty>>3)&1) printf("r3 ");
11084 if((branch_regs[i].dirty>>4)&1) printf("r4 ");
11085 if((branch_regs[i].dirty>>5)&1) printf("r5 ");
11086 if((branch_regs[i].dirty>>6)&1) printf("r6 ");
11087 if((branch_regs[i].dirty>>7)&1) printf("r7 ");
11088 if((branch_regs[i].dirty>>8)&1) printf("r8 ");
11089 if((branch_regs[i].dirty>>9)&1) printf("r9 ");
11090 if((branch_regs[i].dirty>>10)&1) printf("r10 ");
11091 if((branch_regs[i].dirty>>12)&1) printf("r12 ");
11095 for(r=0;r<=CCREG;r++) {
11096 if((branch_regs[i].is32>>r)&1) {
11097 if(r==CCREG) printf(" CC");
11098 else if(r==HIREG) printf(" HI");
11099 else if(r==LOREG) printf(" LO");
11100 else printf(" r%d",r);
11108 /* Pass 8 - Assembly */
11109 linkcount=0;stubcount=0;
11110 ds=0;is_delayslot=0;
11112 uint64_t is32_pre=0;
11114 u_int beginning=(u_int)out;
11115 if((u_int)addr&1) {
11119 u_int instr_addr0_override=0;
11122 if (start == 0x80030000) {
11123 // nasty hack for fastbios thing
11124 // override block entry to this code
11125 instr_addr0_override=(u_int)out;
11126 emit_movimm(start,0);
11127 // abuse io address var as a flag that we
11128 // have already returned here once
11129 emit_readword((int)&address,1);
11130 emit_writeword(0,(int)&pcaddr);
11131 emit_writeword(0,(int)&address);
11133 emit_jne((int)new_dyna_leave);
11136 for(i=0;i<slen;i++)
11138 //if(ds) printf("ds: ");
11139 if((void*)assem_debug==(void*)printf) disassemble_inst(i);
11141 ds=0; // Skip delay slot
11142 if(bt[i]) assem_debug("OOPS - branch into delay slot\n");
11145 #ifndef DESTRUCTIVE_WRITEBACK
11146 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
11148 wb_sx(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,is32_pre,regs[i].was32,
11149 unneeded_reg[i],unneeded_reg_upper[i]);
11150 wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre,
11151 unneeded_reg[i],unneeded_reg_upper[i]);
11153 if((itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)&&!likely[i]) {
11154 is32_pre=branch_regs[i].is32;
11155 dirty_pre=branch_regs[i].dirty;
11157 is32_pre=regs[i].is32;
11158 dirty_pre=regs[i].dirty;
11162 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
11164 wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32,
11165 unneeded_reg[i],unneeded_reg_upper[i]);
11166 loop_preload(regmap_pre[i],regs[i].regmap_entry);
11168 // branch target entry point
11169 instr_addr[i]=(u_int)out;
11170 assem_debug("<->\n");
11172 if(regs[i].regmap_entry[HOST_CCREG]==CCREG&®s[i].regmap[HOST_CCREG]!=CCREG)
11173 wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32);
11174 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
11175 address_generation(i,®s[i],regs[i].regmap_entry);
11176 load_consts(regmap_pre[i],regs[i].regmap,regs[i].was32,i);
11177 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
11179 // Load the delay slot registers if necessary
11180 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i]&&(rs1[i+1]!=rt1[i]||rt1[i]==0))
11181 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
11182 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i]&&(rs2[i+1]!=rt1[i]||rt1[i]==0))
11183 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
11184 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a)
11185 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
11189 // Preload registers for following instruction
11190 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
11191 if(rs1[i+1]!=rt1[i]&&rs1[i+1]!=rt2[i])
11192 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
11193 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
11194 if(rs2[i+1]!=rt1[i]&&rs2[i+1]!=rt2[i])
11195 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
11197 // TODO: if(is_ooo(i)) address_generation(i+1);
11198 if(itype[i]==CJUMP||itype[i]==FJUMP)
11199 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
11200 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a)
11201 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
11202 if(bt[i]) cop1_usable=0;
11206 alu_assemble(i,®s[i]);break;
11208 imm16_assemble(i,®s[i]);break;
11210 shift_assemble(i,®s[i]);break;
11212 shiftimm_assemble(i,®s[i]);break;
11214 load_assemble(i,®s[i]);break;
11216 loadlr_assemble(i,®s[i]);break;
11218 store_assemble(i,®s[i]);break;
11220 storelr_assemble(i,®s[i]);break;
11222 cop0_assemble(i,®s[i]);break;
11224 cop1_assemble(i,®s[i]);break;
11226 c1ls_assemble(i,®s[i]);break;
11228 cop2_assemble(i,®s[i]);break;
11230 c2ls_assemble(i,®s[i]);break;
11232 c2op_assemble(i,®s[i]);break;
11234 fconv_assemble(i,®s[i]);break;
11236 float_assemble(i,®s[i]);break;
11238 fcomp_assemble(i,®s[i]);break;
11240 multdiv_assemble(i,®s[i]);break;
11242 mov_assemble(i,®s[i]);break;
11244 syscall_assemble(i,®s[i]);break;
11246 hlecall_assemble(i,®s[i]);break;
11248 intcall_assemble(i,®s[i]);break;
11250 ujump_assemble(i,®s[i]);ds=1;break;
11252 rjump_assemble(i,®s[i]);ds=1;break;
11254 cjump_assemble(i,®s[i]);ds=1;break;
11256 sjump_assemble(i,®s[i]);ds=1;break;
11258 fjump_assemble(i,®s[i]);ds=1;break;
11260 pagespan_assemble(i,®s[i]);break;
11262 if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
11263 literal_pool(1024);
11265 literal_pool_jumpover(256);
11268 //assert(itype[i-2]==UJUMP||itype[i-2]==RJUMP||(source[i-2]>>16)==0x1000);
11269 // If the block did not end with an unconditional branch,
11270 // add a jump to the next instruction.
11272 if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) {
11273 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
11275 if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP&&itype[i-2]!=FJUMP) {
11276 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
11277 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
11278 emit_loadreg(CCREG,HOST_CCREG);
11279 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
11281 else if(!likely[i-2])
11283 store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].is32,branch_regs[i-2].dirty,start+i*4);
11284 assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
11288 store_regs_bt(regs[i-2].regmap,regs[i-2].is32,regs[i-2].dirty,start+i*4);
11289 assert(regs[i-2].regmap[HOST_CCREG]==CCREG);
11291 add_to_linker((int)out,start+i*4,0);
11298 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
11299 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
11300 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
11301 emit_loadreg(CCREG,HOST_CCREG);
11302 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
11303 add_to_linker((int)out,start+i*4,0);
11307 // TODO: delay slot stubs?
11309 for(i=0;i<stubcount;i++)
11311 switch(stubs[i][0])
11319 do_readstub(i);break;
11324 do_writestub(i);break;
11326 do_ccstub(i);break;
11328 do_invstub(i);break;
11330 do_cop1stub(i);break;
11332 do_unalignedwritestub(i);break;
11336 if (instr_addr0_override)
11337 instr_addr[0] = instr_addr0_override;
11339 /* Pass 9 - Linker */
11340 for(i=0;i<linkcount;i++)
11342 assem_debug("%8x -> %8x\n",link_addr[i][0],link_addr[i][1]);
11344 if(!link_addr[i][2])
11347 void *addr=check_addr(link_addr[i][1]);
11348 emit_extjump(link_addr[i][0],link_addr[i][1]);
11350 set_jump_target(link_addr[i][0],(int)addr);
11351 add_link(link_addr[i][1],stub);
11353 else set_jump_target(link_addr[i][0],(int)stub);
11358 int target=(link_addr[i][1]-start)>>2;
11359 assert(target>=0&&target<slen);
11360 assert(instr_addr[target]);
11361 //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11362 //set_jump_target_fillslot(link_addr[i][0],instr_addr[target],link_addr[i][2]>>1);
11364 set_jump_target(link_addr[i][0],instr_addr[target]);
11368 // External Branch Targets (jump_in)
11369 if(copy+slen*4>(void *)shadow+sizeof(shadow)) copy=shadow;
11370 for(i=0;i<slen;i++)
11374 if(instr_addr[i]) // TODO - delay slots (=null)
11376 u_int vaddr=start+i*4;
11377 u_int page=get_page(vaddr);
11378 u_int vpage=get_vpage(vaddr);
11380 //if(!(is32[i]&(~unneeded_reg_upper[i])&~(1LL<<CCREG)))
11382 if(!requires_32bit[i])
11387 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
11388 assem_debug("jump_in: %x\n",start+i*4);
11389 ll_add(jump_dirty+vpage,vaddr,(void *)out);
11390 int entry_point=do_dirty_stub(i);
11391 ll_add(jump_in+page,vaddr,(void *)entry_point);
11392 // If there was an existing entry in the hash table,
11393 // replace it with the new address.
11394 // Don't add new entries. We'll insert the
11395 // ones that actually get used in check_addr().
11396 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
11397 if(ht_bin[0]==vaddr) {
11398 ht_bin[1]=entry_point;
11400 if(ht_bin[2]==vaddr) {
11401 ht_bin[3]=entry_point;
11406 u_int r=requires_32bit[i]|!!(requires_32bit[i]>>32);
11407 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
11408 assem_debug("jump_in: %x (restricted - %x)\n",start+i*4,r);
11409 //int entry_point=(int)out;
11410 ////assem_debug("entry_point: %x\n",entry_point);
11411 //load_regs_entry(i);
11412 //if(entry_point==(int)out)
11413 // entry_point=instr_addr[i];
11415 // emit_jmp(instr_addr[i]);
11416 //ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11417 ll_add_32(jump_dirty+vpage,vaddr,r,(void *)out);
11418 int entry_point=do_dirty_stub(i);
11419 ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11424 // Write out the literal pool if necessary
11426 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11428 if(((u_int)out)&7) emit_addnop(13);
11430 assert((u_int)out-beginning<MAX_OUTPUT_BLOCK_SIZE);
11431 //printf("shadow buffer: %x-%x\n",(int)copy,(int)copy+slen*4);
11432 memcpy(copy,source,slen*4);
11436 __clear_cache((void *)beginning,out);
11439 // If we're within 256K of the end of the buffer,
11440 // start over from the beginning. (Is 256K enough?)
11441 if((int)out>BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR;
11443 // Trap writes to any of the pages we compiled
11444 for(i=start>>12;i<=(start+slen*4)>>12;i++) {
11446 #ifndef DISABLE_TLB
11447 memory_map[i]|=0x40000000;
11448 if((signed int)start>=(signed int)0xC0000000) {
11450 j=(((u_int)i<<12)+(memory_map[i]<<2)-(u_int)rdram+(u_int)0x80000000)>>12;
11452 memory_map[j]|=0x40000000;
11453 //printf("write protect physical page: %x (virtual %x)\n",j<<12,start);
11457 inv_code_start=inv_code_end=~0;
11459 // PCSX maps all RAM mirror invalid_code tests to 0x80000000..0x80000000+RAM_SIZE
11460 if(get_page(start)<(RAM_SIZE>>12))
11461 for(i=start>>12;i<=(start+slen*4)>>12;i++)
11462 invalid_code[((u_int)0x80000000>>12)|i]=0;
11465 /* Pass 10 - Free memory by expiring oldest blocks */
11467 int end=((((int)out-BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535;
11468 while(expirep!=end)
11470 int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
11471 int base=BASE_ADDR+((expirep>>13)<<shift); // Base address of this block
11472 inv_debug("EXP: Phase %d\n",expirep);
11473 switch((expirep>>11)&3)
11476 // Clear jump_in and jump_dirty
11477 ll_remove_matching_addrs(jump_in+(expirep&2047),base,shift);
11478 ll_remove_matching_addrs(jump_dirty+(expirep&2047),base,shift);
11479 ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base,shift);
11480 ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base,shift);
11484 ll_kill_pointers(jump_out[expirep&2047],base,shift);
11485 ll_kill_pointers(jump_out[(expirep&2047)+2048],base,shift);
11488 // Clear hash table
11489 for(i=0;i<32;i++) {
11490 int *ht_bin=hash_table[((expirep&2047)<<5)+i];
11491 if((ht_bin[3]>>shift)==(base>>shift) ||
11492 ((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11493 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[2],ht_bin[3]);
11494 ht_bin[2]=ht_bin[3]=-1;
11496 if((ht_bin[1]>>shift)==(base>>shift) ||
11497 ((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11498 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[0],ht_bin[1]);
11499 ht_bin[0]=ht_bin[2];
11500 ht_bin[1]=ht_bin[3];
11501 ht_bin[2]=ht_bin[3]=-1;
11508 if((expirep&2047)==0)
11511 ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);
11512 ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base,shift);
11515 expirep=(expirep+1)&65535;
11520 // vim:shiftwidth=2:expandtab