1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
3 * Copyright (C) 2009-2011 Ari64 *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
22 #include <stdint.h> //include for uint64_t
28 #include <libkern/OSCacheControl.h>
31 #include <3ds_utils.h>
38 #include "new_dynarec_config.h"
39 #include "../psxhle.h"
40 #include "../psxinterpreter.h"
41 #include "../psxcounters.h"
43 #include "emu_if.h" // emulator interface
44 #include "linkage_offsets.h"
45 #include "compiler_features.h"
46 #include "arm_features.h"
49 #define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
52 #define min(a, b) ((b) < (a) ? (b) : (a))
55 #define max(a, b) ((b) > (a) ? (b) : (a))
60 //#define REGMAP_PRINT // with DISASM only
65 #define assem_debug printf
67 #define assem_debug(...)
69 //#define inv_debug printf
70 #define inv_debug(...)
73 #include "assem_x86.h"
76 #include "assem_x64.h"
79 #include "assem_arm.h"
82 #include "assem_arm64.h"
85 #define RAM_SIZE 0x200000
87 #define MAX_OUTPUT_BLOCK_SIZE 262144
88 #define EXPIRITY_OFFSET (MAX_OUTPUT_BLOCK_SIZE * 2)
89 #define PAGE_COUNT 1024
91 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
92 #define INVALIDATE_USE_COND_CALL
96 // apparently Vita has a 16MB limit, so either we cut tc in half,
97 // or use this hack (it's a hack because tc size was designed to be power-of-2)
98 #define TC_REDUCE_BYTES 4096
100 #define TC_REDUCE_BYTES 0
105 struct tramp_insns ops[2048 / sizeof(struct tramp_insns)];
106 const void *f[2048 / sizeof(void *)];
111 u_char translation_cache[(1 << TARGET_SIZE_2) - TC_REDUCE_BYTES];
112 struct ndrc_tramp tramp;
115 static struct ndrc_mem *ndrc;
116 #ifndef BASE_ADDR_DYNAMIC
117 // reserve .bss space with upto 64k page size in mind
118 static char ndrc_bss[((sizeof(*ndrc) + 65535) & ~65535) + 65536];
120 #ifdef TC_WRITE_OFFSET
122 # include <sys/types.h>
123 # include <sys/stat.h>
126 static long ndrc_write_ofs;
127 #define NDRC_WRITE_OFFSET(x) (void *)((char *)(x) + ndrc_write_ofs)
129 #define NDRC_WRITE_OFFSET(x) (x)
152 // regmap_pre[i] - regs before [i] insn starts; dirty things here that
153 // don't match .regmap will be written back
154 // [i].regmap_entry - regs that must be set up if someone jumps here
155 // [i].regmap - regs [i] insn will read/(over)write
156 // branch_regs[i].* - same as above but for branches, takes delay slot into account
159 signed char regmap_entry[HOST_REGS];
160 signed char regmap[HOST_REGS];
163 u_int wasconst; // before; for example 'lw r2, (r2)' wasconst is true
164 u_int isconst; // ... but isconst is false when r2 is known (hr)
165 u_int loadedconst; // host regs that have constants loaded
166 u_int noevict; // can't evict this hr (alloced by current op)
167 //u_int waswritten; // MIPS regs that were used as store base before
198 struct block_info *next;
201 u_int start; // vaddr of the block start
202 u_int len; // of the whole block source
207 u_char inv_near_misses;
225 static struct decoded_insn
228 u_char opcode; // bits 31-26
229 u_char opcode2; // (depends on opcode)
242 u_char is_delay_load:1; // is_load + MFC/CFC
243 u_char is_exception:1; // unconditional, also interp. fallback
244 u_char may_except:1; // might generate an exception
245 u_char ls_type:2; // load/store type (ls_width_type)
249 LS_8 = 0, LS_16, LS_32, LS_LR
252 static struct compile_info
257 signed char min_free_regs;
259 signed char reserved[2];
263 static char invalid_code[0x100000];
264 static struct ht_entry hash_table[65536];
265 static struct block_info *blocks[PAGE_COUNT];
266 static struct jump_info *jumps[PAGE_COUNT];
268 static u_int *source;
269 static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
270 static uint64_t gte_rt[MAXBLOCK];
271 static uint64_t gte_unneeded[MAXBLOCK];
272 static u_int smrv[32]; // speculated MIPS register values
273 static u_int smrv_strong; // mask or regs that are likely to have correct values
274 static u_int smrv_weak; // same, but somewhat less likely
275 static u_int smrv_strong_next; // same, but after current insn executes
276 static u_int smrv_weak_next;
277 static uint64_t unneeded_reg[MAXBLOCK];
278 static uint64_t branch_unneeded_reg[MAXBLOCK];
279 // see 'struct regstat' for a description
280 static signed char regmap_pre[MAXBLOCK][HOST_REGS];
281 // contains 'real' consts at [i] insn, but may differ from what's actually
282 // loaded in host reg as 'final' value is always loaded, see get_final_value()
283 static uint32_t current_constmap[HOST_REGS];
284 static uint32_t constmap[MAXBLOCK][HOST_REGS];
285 static struct regstat regs[MAXBLOCK];
286 static struct regstat branch_regs[MAXBLOCK];
288 static void *instr_addr[MAXBLOCK];
289 static struct link_entry link_addr[MAXBLOCK];
290 static int linkcount;
291 static struct code_stub stubs[MAXBLOCK*3];
292 static int stubcount;
293 static u_int literals[1024][2];
294 static int literalcount;
295 static int is_delayslot;
296 static char shadow[1048576] __attribute__((aligned(16)));
298 static u_int expirep;
299 static u_int stop_after_jal;
300 static u_int f1_hack;
302 static int stat_bc_direct;
303 static int stat_bc_pre;
304 static int stat_bc_restore;
305 static int stat_ht_lookups;
306 static int stat_jump_in_lookups;
307 static int stat_restore_tries;
308 static int stat_restore_compares;
309 static int stat_inv_addr_calls;
310 static int stat_inv_hits;
311 static int stat_blocks;
312 static int stat_links;
313 #define stat_inc(s) s++
314 #define stat_dec(s) s--
315 #define stat_clear(s) s = 0
319 #define stat_clear(s)
322 int new_dynarec_hacks;
323 int new_dynarec_hacks_pergame;
324 int new_dynarec_hacks_old;
325 int new_dynarec_did_compile;
327 #define HACK_ENABLED(x) ((new_dynarec_hacks | new_dynarec_hacks_pergame) & (x))
329 extern int cycle_count; // ... until end of the timeslice, counts -N -> 0 (CCREG)
330 extern int last_count; // last absolute target, often = next_interupt
332 extern int pending_exception;
333 extern int branch_target;
334 extern uintptr_t ram_offset;
335 extern uintptr_t mini_ht[32][2];
337 /* registers that may be allocated */
339 #define LOREG 32 // lo
340 #define HIREG 33 // hi
341 //#define FSREG 34 // FPU status (FCSR)
342 //#define CSREG 35 // Coprocessor status
343 #define CCREG 36 // Cycle count
344 #define INVCP 37 // Pointer to invalid_code
345 //#define MMREG 38 // Pointer to memory_map
346 #define ROREG 39 // ram offset (if psxM != 0x80000000)
348 #define FTEMP 40 // Load/store temporary register (was fpu)
349 #define PTEMP 41 // Prefetch temporary register
350 //#define TLREG 42 // TLB mapping offset
351 #define RHASH 43 // Return address hash
352 #define RHTBL 44 // Return address hash table address
353 #define RTEMP 45 // JR/JALR address register
355 #define AGEN1 46 // Address generation temporary register (pass5b_preallocate2)
356 //#define AGEN2 47 // Address generation temporary register
358 /* instruction types */
359 #define NOP 0 // No operation
360 #define LOAD 1 // Load
361 #define STORE 2 // Store
362 #define LOADLR 3 // Unaligned load
363 #define STORELR 4 // Unaligned store
364 #define MOV 5 // Move (hi/lo only)
365 #define ALU 6 // Arithmetic/logic
366 #define MULTDIV 7 // Multiply/divide
367 #define SHIFT 8 // Shift by register
368 #define SHIFTIMM 9// Shift by immediate
369 #define IMM16 10 // 16-bit immediate
370 #define RJUMP 11 // Unconditional jump to register
371 #define UJUMP 12 // Unconditional jump
372 #define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
373 #define SJUMP 14 // Conditional branch (regimm format)
374 #define COP0 15 // Coprocessor 0
376 #define SYSCALL 22// SYSCALL,BREAK
377 #define OTHER 23 // Other/unknown - do nothing
378 #define HLECALL 26// PCSX fake opcodes for HLE
379 #define COP2 27 // Coprocessor 2 move
380 #define C2LS 28 // Coprocessor 2 load/store
381 #define C2OP 29 // Coprocessor 2 operation
382 #define INTCALL 30// Call interpreter to handle rare corner cases
388 #define DJT_1 (void *)1l // no function, just a label in assem_debug log
389 #define DJT_2 (void *)2l
394 void jump_syscall (u_int u0, u_int u1, u_int pc);
395 void jump_syscall_ds(u_int u0, u_int u1, u_int pc);
396 void jump_break (u_int u0, u_int u1, u_int pc);
397 void jump_break_ds(u_int u0, u_int u1, u_int pc);
398 void jump_overflow (u_int u0, u_int u1, u_int pc);
399 void jump_overflow_ds(u_int u0, u_int u1, u_int pc);
400 void jump_addrerror (u_int cause, u_int addr, u_int pc);
401 void jump_addrerror_ds(u_int cause, u_int addr, u_int pc);
402 void jump_to_new_pc();
403 void call_gteStall();
404 void new_dyna_leave();
406 void *ndrc_get_addr_ht_param(u_int vaddr, int can_compile);
407 void *ndrc_get_addr_ht(u_int vaddr);
408 void ndrc_add_jump_out(u_int vaddr, void *src);
409 void ndrc_write_invalidate_one(u_int addr);
410 static void ndrc_write_invalidate_many(u_int addr, u_int end);
412 static int new_recompile_block(u_int addr);
413 static void invalidate_block(struct block_info *block);
414 static void exception_assemble(int i, const struct regstat *i_regs, int ccadj_);
416 // Needed by assembler
417 static void wb_register(signed char r, const signed char regmap[], u_int dirty);
418 static void wb_dirtys(const signed char i_regmap[], u_int i_dirty);
419 static void wb_needed_dirtys(const signed char i_regmap[], u_int i_dirty, int addr);
420 static void load_all_regs(const signed char i_regmap[]);
421 static void load_needed_regs(const signed char i_regmap[], const signed char next_regmap[]);
422 static void load_regs_entry(int t);
423 static void load_all_consts(const signed char regmap[], u_int dirty, int i);
424 static u_int get_host_reglist(const signed char *regmap);
426 static int get_final_value(int hr, int i, u_int *value);
427 static void add_stub(enum stub_type type, void *addr, void *retaddr,
428 u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e);
429 static void add_stub_r(enum stub_type type, void *addr, void *retaddr,
430 int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist);
431 static void add_to_linker(void *addr, u_int target, int ext);
432 static void *get_direct_memhandler(void *table, u_int addr,
433 enum stub_type type, uintptr_t *addr_host);
434 static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist);
435 static void pass_args(int a0, int a1);
436 static void emit_far_jump(const void *f);
437 static void emit_far_call(const void *f);
440 #include <psp2/kernel/sysmem.h>
442 // note: this interacts with RetroArch's Vita bootstrap code: bootstrap/vita/sbrk.c
443 extern int getVMBlock();
444 int _newlib_vm_size_user = sizeof(*ndrc);
447 static void mprotect_w_x(void *start, void *end, int is_x)
451 // *Open* enables write on all memory that was
452 // allocated by sceKernelAllocMemBlockForVM()?
454 sceKernelCloseVMDomain();
456 sceKernelOpenVMDomain();
457 #elif defined(HAVE_LIBNX)
459 // check to avoid the full flush in jitTransitionToExecutable()
460 if (g_jit.type != JitType_CodeMemory) {
462 rc = jitTransitionToExecutable(&g_jit);
464 rc = jitTransitionToWritable(&g_jit);
466 ;//SysPrintf("jitTransition %d %08x\n", is_x, rc);
468 #elif defined(TC_WRITE_OFFSET)
469 // separated rx and rw areas are always available
471 u_long mstart = (u_long)start & ~4095ul;
472 u_long mend = (u_long)end;
473 if (mprotect((void *)mstart, mend - mstart,
474 PROT_READ | (is_x ? PROT_EXEC : PROT_WRITE)) != 0)
475 SysPrintf("mprotect(%c) failed: %s\n", is_x ? 'x' : 'w', strerror(errno));
480 static void start_tcache_write(void *start, void *end)
482 mprotect_w_x(start, end, 0);
485 static void end_tcache_write(void *start, void *end)
487 #if defined(__arm__) || defined(__aarch64__)
488 size_t len = (char *)end - (char *)start;
489 #if defined(__BLACKBERRY_QNX__)
490 msync(start, len, MS_SYNC | MS_CACHE_ONLY | MS_INVALIDATE_ICACHE);
491 #elif defined(__MACH__)
492 sys_cache_control(kCacheFunctionPrepareForExecution, start, len);
494 sceKernelSyncVMDomain(sceBlock, start, len);
496 ctr_flush_invalidate_cache();
497 #elif defined(HAVE_LIBNX)
498 if (g_jit.type == JitType_CodeMemory) {
499 armDCacheClean(start, len);
500 armICacheInvalidate((char *)start - ndrc_write_ofs, len);
501 // as of v4.2.1 libnx lacks isb
502 __asm__ volatile("isb" ::: "memory");
504 #elif defined(__aarch64__)
505 // as of 2021, __clear_cache() is still broken on arm64
506 // so here is a custom one :(
507 clear_cache_arm64(start, end);
509 __clear_cache(start, end);
514 mprotect_w_x(start, end, 1);
517 static void *start_block(void)
519 u_char *end = out + MAX_OUTPUT_BLOCK_SIZE;
520 if (end > ndrc->translation_cache + sizeof(ndrc->translation_cache))
521 end = ndrc->translation_cache + sizeof(ndrc->translation_cache);
522 start_tcache_write(NDRC_WRITE_OFFSET(out), NDRC_WRITE_OFFSET(end));
526 static void end_block(void *start)
528 end_tcache_write(NDRC_WRITE_OFFSET(start), NDRC_WRITE_OFFSET(out));
531 #ifdef NDRC_CACHE_FLUSH_ALL
533 static int needs_clear_cache;
535 static void mark_clear_cache(void *target)
537 if (!needs_clear_cache) {
538 start_tcache_write(NDRC_WRITE_OFFSET(ndrc), NDRC_WRITE_OFFSET(ndrc + 1));
539 needs_clear_cache = 1;
543 static void do_clear_cache(void)
545 if (needs_clear_cache) {
546 end_tcache_write(NDRC_WRITE_OFFSET(ndrc), NDRC_WRITE_OFFSET(ndrc + 1));
547 needs_clear_cache = 0;
553 // also takes care of w^x mappings when patching code
554 static u_int needs_clear_cache[1<<(TARGET_SIZE_2-17)];
556 static void mark_clear_cache(void *target)
558 uintptr_t offset = (u_char *)target - ndrc->translation_cache;
559 u_int mask = 1u << ((offset >> 12) & 31);
560 if (!(needs_clear_cache[offset >> 17] & mask)) {
561 char *start = (char *)NDRC_WRITE_OFFSET((uintptr_t)target & ~4095l);
562 start_tcache_write(start, start + 4095);
563 needs_clear_cache[offset >> 17] |= mask;
567 // Clearing the cache is rather slow on ARM Linux, so mark the areas
568 // that need to be cleared, and then only clear these areas once.
569 static void do_clear_cache(void)
572 for (i = 0; i < (1<<(TARGET_SIZE_2-17)); i++)
574 u_int bitmap = needs_clear_cache[i];
577 for (j = 0; j < 32; j++)
580 if (!(bitmap & (1u << j)))
583 start = ndrc->translation_cache + i*131072 + j*4096;
585 for (j++; j < 32; j++) {
586 if (!(bitmap & (1u << j)))
590 end_tcache_write(NDRC_WRITE_OFFSET(start), NDRC_WRITE_OFFSET(end));
592 needs_clear_cache[i] = 0;
596 #endif // NDRC_CACHE_FLUSH_ALL
598 #define NO_CYCLE_PENALTY_THR 12
600 int cycle_multiplier_old;
601 static int cycle_multiplier_active;
603 static int CLOCK_ADJUST(int x)
605 int m = cycle_multiplier_active;
606 int s = (x >> 31) | 1;
607 return (x * m + s * 50) / 100;
610 static int ds_writes_rjump_rs(int i)
612 return dops[i].rs1 != 0
613 && (dops[i].rs1 == dops[i+1].rt1 || dops[i].rs1 == dops[i+1].rt2
614 || dops[i].rs1 == dops[i].rt1); // overwrites itself - same effect
617 // psx addr mirror masking (for invalidation)
618 static u_int pmmask(u_int vaddr)
620 vaddr &= ~0xe0000000;
621 if (vaddr < 0x01000000)
622 vaddr &= ~0x00e00000; // RAM mirrors
626 static u_int get_page(u_int vaddr)
628 u_int page = pmmask(vaddr) >> 12;
629 if (page >= PAGE_COUNT / 2)
630 page = PAGE_COUNT / 2 + (page & (PAGE_COUNT / 2 - 1));
634 // get a page for looking for a block that has vaddr
635 // (needed because the block may start in previous page)
636 static u_int get_page_prev(u_int vaddr)
638 assert(MAXBLOCK <= (1 << 12));
639 u_int page = get_page(vaddr);
645 static struct ht_entry *hash_table_get(u_int vaddr)
647 return &hash_table[((vaddr>>16)^vaddr)&0xFFFF];
650 #define HASH_TABLE_BAD 0xbac
652 static void hash_table_clear(void)
654 struct ht_entry *ht_bin;
656 for (i = 0; i < ARRAY_SIZE(hash_table); i++) {
657 for (j = 0; j < ARRAY_SIZE(hash_table[i].vaddr); j++) {
658 hash_table[i].vaddr[j] = ~0;
659 hash_table[i].tcaddr[j] = (void *)(uintptr_t)HASH_TABLE_BAD;
662 // don't allow ~0 to hit
663 ht_bin = hash_table_get(~0);
664 for (j = 0; j < ARRAY_SIZE(ht_bin->vaddr); j++)
665 ht_bin->vaddr[j] = 1;
668 static void hash_table_add(u_int vaddr, void *tcaddr)
670 struct ht_entry *ht_bin = hash_table_get(vaddr);
672 ht_bin->vaddr[1] = ht_bin->vaddr[0];
673 ht_bin->tcaddr[1] = ht_bin->tcaddr[0];
674 ht_bin->vaddr[0] = vaddr;
675 ht_bin->tcaddr[0] = tcaddr;
678 static void hash_table_remove(int vaddr)
680 //printf("remove hash: %x\n",vaddr);
681 struct ht_entry *ht_bin = hash_table_get(vaddr);
682 if (ht_bin->vaddr[1] == vaddr) {
683 ht_bin->vaddr[1] = ~0;
684 ht_bin->tcaddr[1] = (void *)(uintptr_t)HASH_TABLE_BAD;
686 if (ht_bin->vaddr[0] == vaddr) {
687 ht_bin->vaddr[0] = ht_bin->vaddr[1];
688 ht_bin->tcaddr[0] = ht_bin->tcaddr[1];
689 ht_bin->vaddr[1] = ~0;
690 ht_bin->tcaddr[1] = (void *)(uintptr_t)HASH_TABLE_BAD;
694 static void mini_ht_clear(void)
698 for (i = 0; i < ARRAY_SIZE(mini_ht) - 1; i++) {
700 mini_ht[i][1] = HASH_TABLE_BAD;
703 mini_ht[i][1] = HASH_TABLE_BAD;
707 static void mark_invalid_code(u_int vaddr, u_int len, char invalid)
709 u_int vaddr_m = vaddr & 0x1fffffff;
711 for (i = vaddr_m & ~0xfff; i < vaddr_m + len; i += 0x1000) {
712 // ram mirrors, but should not hurt bios
713 for (j = 0; j < 0x800000; j += 0x200000) {
714 invalid_code[(i|j) >> 12] =
715 invalid_code[(i|j|0x80000000u) >> 12] =
716 invalid_code[(i|j|0xa0000000u) >> 12] = invalid;
719 if (!invalid && vaddr + len > inv_code_start && vaddr <= inv_code_end)
720 inv_code_start = inv_code_end = ~0;
723 static int doesnt_expire_soon(u_char *tcaddr)
725 u_int diff = (u_int)(tcaddr - out) & ((1u << TARGET_SIZE_2) - 1u);
726 return diff > EXPIRITY_OFFSET + MAX_OUTPUT_BLOCK_SIZE;
729 static unused void check_for_block_changes(u_int start, u_int end)
731 u_int start_page = get_page_prev(start);
732 u_int end_page = get_page(end - 1);
735 for (page = start_page; page <= end_page; page++) {
736 struct block_info *block;
737 for (block = blocks[page]; block != NULL; block = block->next) {
740 if (memcmp(block->source, block->copy, block->len)) {
741 printf("bad block %08x-%08x %016llx %016llx @%08x\n",
742 block->start, block->start + block->len,
743 *(long long *)block->source, *(long long *)block->copy, psxRegs.pc);
751 static void *try_restore_block(u_int vaddr, u_int start_page, u_int end_page)
753 void *found_clean = NULL;
756 stat_inc(stat_restore_tries);
757 for (page = start_page; page <= end_page; page++) {
758 struct block_info *block;
759 for (block = blocks[page]; block != NULL; block = block->next) {
760 if (vaddr < block->start)
762 if (!block->is_dirty || vaddr >= block->start + block->len)
764 for (i = 0; i < block->jump_in_cnt; i++)
765 if (block->jump_in[i].vaddr == vaddr)
767 if (i == block->jump_in_cnt)
769 assert(block->source && block->copy);
770 stat_inc(stat_restore_compares);
771 if (memcmp(block->source, block->copy, block->len))
774 block->is_dirty = block->inv_near_misses = 0;
775 found_clean = block->jump_in[i].addr;
776 hash_table_add(vaddr, found_clean);
777 mark_invalid_code(block->start, block->len, 0);
778 stat_inc(stat_bc_restore);
779 inv_debug("INV: restored %08x %p (%d)\n", vaddr, found_clean, block->jump_in_cnt);
786 // this doesn't normally happen
787 static noinline u_int generate_exception(u_int pc)
789 //if (execBreakCheck(&psxRegs, pc))
790 // return psxRegs.pc;
792 // generate an address or bus error
793 psxRegs.CP0.n.Cause &= 0x300;
794 psxRegs.CP0.n.EPC = pc;
796 psxRegs.CP0.n.Cause |= R3000E_AdEL << 2;
797 psxRegs.CP0.n.BadVAddr = pc;
802 psxRegs.CP0.n.Cause |= R3000E_IBE << 2;
803 return (psxRegs.pc = 0x80000080);
806 // Get address from virtual address
807 // This is called from the recompiled JR/JALR instructions
808 static void noinline *get_addr(u_int vaddr, int can_compile)
810 u_int start_page = get_page_prev(vaddr);
811 u_int i, page, end_page = get_page(vaddr);
812 void *found_clean = NULL;
814 stat_inc(stat_jump_in_lookups);
815 for (page = start_page; page <= end_page; page++) {
816 const struct block_info *block;
817 for (block = blocks[page]; block != NULL; block = block->next) {
818 if (vaddr < block->start)
820 if (block->is_dirty || vaddr >= block->start + block->len)
822 for (i = 0; i < block->jump_in_cnt; i++)
823 if (block->jump_in[i].vaddr == vaddr)
825 if (i == block->jump_in_cnt)
827 found_clean = block->jump_in[i].addr;
828 hash_table_add(vaddr, found_clean);
832 found_clean = try_restore_block(vaddr, start_page, end_page);
839 int r = new_recompile_block(vaddr);
841 return ndrc_get_addr_ht(vaddr);
843 return ndrc_get_addr_ht(generate_exception(vaddr));
846 // Look up address in hash table first
847 void *ndrc_get_addr_ht_param(u_int vaddr, int can_compile)
849 //check_for_block_changes(vaddr, vaddr + MAXBLOCK);
850 const struct ht_entry *ht_bin = hash_table_get(vaddr);
851 u_int vaddr_a = vaddr & ~3;
852 stat_inc(stat_ht_lookups);
853 if (ht_bin->vaddr[0] == vaddr_a) return ht_bin->tcaddr[0];
854 if (ht_bin->vaddr[1] == vaddr_a) return ht_bin->tcaddr[1];
855 return get_addr(vaddr, can_compile);
858 void *ndrc_get_addr_ht(u_int vaddr)
860 return ndrc_get_addr_ht_param(vaddr, 1);
863 static void clear_all_regs(signed char regmap[])
865 memset(regmap, -1, sizeof(regmap[0]) * HOST_REGS);
868 // get_reg: get allocated host reg from mips reg
869 // returns -1 if no such mips reg was allocated
870 #if defined(__arm__) && defined(HAVE_ARMV6) && HOST_REGS == 13 && EXCLUDE_REG == 11
872 extern signed char get_reg(const signed char regmap[], signed char r);
876 static signed char get_reg(const signed char regmap[], signed char r)
879 for (hr = 0; hr < HOST_REGS; hr++) {
880 if (hr == EXCLUDE_REG)
890 // get reg suitable for writing
891 static signed char get_reg_w(const signed char regmap[], signed char r)
893 return r == 0 ? -1 : get_reg(regmap, r);
896 // get reg as mask bit (1 << hr)
897 static u_int get_regm(const signed char regmap[], signed char r)
899 return (1u << (get_reg(regmap, r) & 31)) & ~(1u << 31);
902 static signed char get_reg_temp(const signed char regmap[])
905 for (hr = 0; hr < HOST_REGS; hr++) {
906 if (hr == EXCLUDE_REG)
908 if (regmap[hr] == (signed char)-1)
914 // Find a register that is available for two consecutive cycles
915 static signed char get_reg2(signed char regmap1[], const signed char regmap2[], int r)
918 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map1[hr]==r&®map2[hr]==r) return hr;
922 // reverse reg map: mips -> host
923 #define RRMAP_SIZE 64
924 static void make_rregs(const signed char regmap[], signed char rrmap[RRMAP_SIZE],
925 u_int *regs_can_change)
927 u_int r, hr, hr_can_change = 0;
928 memset(rrmap, -1, RRMAP_SIZE);
929 for (hr = 0; hr < HOST_REGS; )
932 rrmap[r & (RRMAP_SIZE - 1)] = hr;
933 // only add mips $1-$31+$lo, others shifted out
934 hr_can_change |= (uint64_t)1 << (hr + ((r - 1) & 32));
936 if (hr == EXCLUDE_REG)
939 hr_can_change |= 1u << (rrmap[33] & 31);
940 hr_can_change |= 1u << (rrmap[CCREG] & 31);
941 hr_can_change &= ~(1u << 31);
942 *regs_can_change = hr_can_change;
945 // same as get_reg, but takes rrmap
946 static signed char get_rreg(signed char rrmap[RRMAP_SIZE], signed char r)
948 assert(0 <= r && r < RRMAP_SIZE);
952 static int count_free_regs(const signed char regmap[])
956 for(hr=0;hr<HOST_REGS;hr++)
958 if(hr!=EXCLUDE_REG) {
959 if(regmap[hr]<0) count++;
965 static void dirty_reg(struct regstat *cur, signed char reg)
969 hr = get_reg(cur->regmap, reg);
974 static void set_const(struct regstat *cur, signed char reg, uint32_t value)
978 hr = get_reg(cur->regmap, reg);
980 cur->isconst |= 1<<hr;
981 current_constmap[hr] = value;
985 static void clear_const(struct regstat *cur, signed char reg)
989 hr = get_reg(cur->regmap, reg);
991 cur->isconst &= ~(1<<hr);
994 static int is_const(const struct regstat *cur, signed char reg)
997 if (reg < 0) return 0;
999 hr = get_reg(cur->regmap, reg);
1001 return (cur->isconst>>hr)&1;
1005 static uint32_t get_const(const struct regstat *cur, signed char reg)
1009 hr = get_reg(cur->regmap, reg);
1011 return current_constmap[hr];
1013 SysPrintf("Unknown constant in r%d\n", reg);
1017 // Least soon needed registers
1018 // Look at the next ten instructions and see which registers
1019 // will be used. Try not to reallocate these.
1020 static void lsn(u_char hsn[], int i)
1030 if (dops[i+j].is_ujump)
1032 // Don't go past an unconditonal jump
1039 if(dops[i+j].rs1) hsn[dops[i+j].rs1]=j;
1040 if(dops[i+j].rs2) hsn[dops[i+j].rs2]=j;
1041 if(dops[i+j].rt1) hsn[dops[i+j].rt1]=j;
1042 if(dops[i+j].rt2) hsn[dops[i+j].rt2]=j;
1043 if(dops[i+j].itype==STORE || dops[i+j].itype==STORELR) {
1044 // Stores can allocate zero
1045 hsn[dops[i+j].rs1]=j;
1046 hsn[dops[i+j].rs2]=j;
1048 if (ram_offset && (dops[i+j].is_load || dops[i+j].is_store))
1050 // On some architectures stores need invc_ptr
1051 #if defined(HOST_IMM8)
1052 if (dops[i+j].is_store)
1055 if(i+j>=0&&(dops[i+j].itype==UJUMP||dops[i+j].itype==CJUMP||dops[i+j].itype==SJUMP))
1063 if(cinfo[i+b].ba>=start && cinfo[i+b].ba<(start+slen*4))
1065 // Follow first branch
1066 int t=(cinfo[i+b].ba-start)>>2;
1067 j=7-b;if(t+j>=slen) j=slen-t-1;
1070 if(dops[t+j].rs1) if(hsn[dops[t+j].rs1]>j+b+2) hsn[dops[t+j].rs1]=j+b+2;
1071 if(dops[t+j].rs2) if(hsn[dops[t+j].rs2]>j+b+2) hsn[dops[t+j].rs2]=j+b+2;
1072 //if(dops[t+j].rt1) if(hsn[dops[t+j].rt1]>j+b+2) hsn[dops[t+j].rt1]=j+b+2;
1073 //if(dops[t+j].rt2) if(hsn[dops[t+j].rt2]>j+b+2) hsn[dops[t+j].rt2]=j+b+2;
1076 // TODO: preferred register based on backward branch
1078 // Delay slot should preferably not overwrite branch conditions or cycle count
1079 if (i > 0 && dops[i-1].is_jump) {
1080 if(dops[i-1].rs1) if(hsn[dops[i-1].rs1]>1) hsn[dops[i-1].rs1]=1;
1081 if(dops[i-1].rs2) if(hsn[dops[i-1].rs2]>1) hsn[dops[i-1].rs2]=1;
1083 // ...or hash tables
1087 // Coprocessor load/store needs FTEMP, even if not declared
1088 if(dops[i].itype==C2LS) {
1091 // Load/store L/R also uses FTEMP as a temporary register
1092 if (dops[i].itype == LOADLR || dops[i].itype == STORELR) {
1095 // Don't remove the miniht registers
1096 if(dops[i].itype==UJUMP||dops[i].itype==RJUMP)
1103 // We only want to allocate registers if we're going to use them again soon
1104 static int needed_again(int r, int i)
1110 if (i > 0 && dops[i-1].is_ujump)
1112 if(cinfo[i-1].ba<start || cinfo[i-1].ba>start+slen*4-4)
1113 return 0; // Don't need any registers if exiting the block
1121 if (dops[i+j].is_ujump)
1123 // Don't go past an unconditonal jump
1127 if (dops[i+j].is_exception)
1134 if(dops[i+j].rs1==r) rn=j;
1135 if(dops[i+j].rs2==r) rn=j;
1136 if((unneeded_reg[i+j]>>r)&1) rn=10;
1137 if(i+j>=0&&(dops[i+j].itype==UJUMP||dops[i+j].itype==CJUMP||dops[i+j].itype==SJUMP))
1147 // Try to match register allocations at the end of a loop with those
1149 static int loop_reg(int i, int r, int hr)
1158 if (dops[i+j].is_ujump)
1160 // Don't go past an unconditonal jump
1167 if(dops[i-1].itype==UJUMP||dops[i-1].itype==CJUMP||dops[i-1].itype==SJUMP)
1173 if((unneeded_reg[i+k]>>r)&1) return hr;
1174 if(i+k>=0&&(dops[i+k].itype==UJUMP||dops[i+k].itype==CJUMP||dops[i+k].itype==SJUMP))
1176 if(cinfo[i+k].ba>=start && cinfo[i+k].ba<(start+i*4))
1178 int t=(cinfo[i+k].ba-start)>>2;
1179 int reg=get_reg(regs[t].regmap_entry,r);
1180 if(reg>=0) return reg;
1181 //reg=get_reg(regs[t+1].regmap_entry,r);
1182 //if(reg>=0) return reg;
1190 // Allocate every register, preserving source/target regs
1191 static void alloc_all(struct regstat *cur,int i)
1195 for(hr=0;hr<HOST_REGS;hr++) {
1196 if(hr!=EXCLUDE_REG) {
1197 if((cur->regmap[hr]!=dops[i].rs1)&&(cur->regmap[hr]!=dops[i].rs2)&&
1198 (cur->regmap[hr]!=dops[i].rt1)&&(cur->regmap[hr]!=dops[i].rt2))
1201 cur->dirty&=~(1<<hr);
1204 if(cur->regmap[hr]==0)
1207 cur->dirty&=~(1<<hr);
1214 static int host_tempreg_in_use;
1216 static void host_tempreg_acquire(void)
1218 assert(!host_tempreg_in_use);
1219 host_tempreg_in_use = 1;
1222 static void host_tempreg_release(void)
1224 host_tempreg_in_use = 0;
1227 static void host_tempreg_acquire(void) {}
1228 static void host_tempreg_release(void) {}
1232 extern void gen_interupt();
1233 extern void do_insn_cmp();
1234 #define FUNCNAME(f) { f, " " #f }
1235 static const struct {
1238 } function_names[] = {
1239 FUNCNAME(cc_interrupt),
1240 FUNCNAME(gen_interupt),
1241 FUNCNAME(ndrc_get_addr_ht),
1242 FUNCNAME(jump_handler_read8),
1243 FUNCNAME(jump_handler_read16),
1244 FUNCNAME(jump_handler_read32),
1245 FUNCNAME(jump_handler_write8),
1246 FUNCNAME(jump_handler_write16),
1247 FUNCNAME(jump_handler_write32),
1248 FUNCNAME(ndrc_write_invalidate_one),
1249 FUNCNAME(ndrc_write_invalidate_many),
1250 FUNCNAME(jump_to_new_pc),
1251 FUNCNAME(jump_break),
1252 FUNCNAME(jump_break_ds),
1253 FUNCNAME(jump_syscall),
1254 FUNCNAME(jump_syscall_ds),
1255 FUNCNAME(jump_overflow),
1256 FUNCNAME(jump_overflow_ds),
1257 FUNCNAME(jump_addrerror),
1258 FUNCNAME(jump_addrerror_ds),
1259 FUNCNAME(call_gteStall),
1260 FUNCNAME(new_dyna_leave),
1261 FUNCNAME(pcsx_mtc0),
1262 FUNCNAME(pcsx_mtc0_ds),
1265 FUNCNAME(do_memhandler_pre),
1266 FUNCNAME(do_memhandler_post),
1270 FUNCNAME(do_insn_cmp_arm64),
1272 FUNCNAME(do_insn_cmp),
1277 static const char *func_name(const void *a)
1280 for (i = 0; i < sizeof(function_names)/sizeof(function_names[0]); i++)
1281 if (function_names[i].addr == a)
1282 return function_names[i].name;
1286 static const char *fpofs_name(u_int ofs)
1288 u_int *p = (u_int *)&dynarec_local + ofs/sizeof(u_int);
1289 static char buf[64];
1291 #define ofscase(x) case LO_##x: return " ; " #x
1292 ofscase(next_interupt);
1293 ofscase(cycle_count);
1294 ofscase(last_count);
1295 ofscase(pending_exception);
1306 ofscase(ram_offset);
1310 if (psxRegs.GPR.r <= p && p < &psxRegs.GPR.r[32])
1311 snprintf(buf, sizeof(buf), " ; r%d", (int)(p - psxRegs.GPR.r));
1312 else if (psxRegs.CP0.r <= p && p < &psxRegs.CP0.r[32])
1313 snprintf(buf, sizeof(buf), " ; cp0 $%d", (int)(p - psxRegs.CP0.r));
1314 else if (psxRegs.CP2D.r <= p && p < &psxRegs.CP2D.r[32])
1315 snprintf(buf, sizeof(buf), " ; cp2d $%d", (int)(p - psxRegs.CP2D.r));
1316 else if (psxRegs.CP2C.r <= p && p < &psxRegs.CP2C.r[32])
1317 snprintf(buf, sizeof(buf), " ; cp2c $%d", (int)(p - psxRegs.CP2C.r));
1321 #define func_name(x) ""
1322 #define fpofs_name(x) ""
1326 #include "assem_x86.c"
1329 #include "assem_x64.c"
1332 #include "assem_arm.c"
1335 #include "assem_arm64.c"
1338 static void *get_trampoline(const void *f)
1340 struct ndrc_tramp *tramp = NDRC_WRITE_OFFSET(&ndrc->tramp);
1343 for (i = 0; i < ARRAY_SIZE(tramp->f); i++) {
1344 if (tramp->f[i] == f || tramp->f[i] == NULL)
1347 if (i == ARRAY_SIZE(tramp->f)) {
1348 SysPrintf("trampoline table is full, last func %p\n", f);
1351 if (tramp->f[i] == NULL) {
1352 start_tcache_write(&tramp->f[i], &tramp->f[i + 1]);
1354 end_tcache_write(&tramp->f[i], &tramp->f[i + 1]);
1356 // invalidate the RX mirror (unsure if necessary, but just in case...)
1357 armDCacheFlush(&ndrc->tramp.f[i], sizeof(ndrc->tramp.f[i]));
1360 return &ndrc->tramp.ops[i];
1363 static void emit_far_jump(const void *f)
1365 if (can_jump_or_call(f)) {
1370 f = get_trampoline(f);
1374 static void emit_far_call(const void *f)
1376 if (can_jump_or_call(f)) {
1381 f = get_trampoline(f);
1385 // Check if an address is already compiled
1386 // but don't return addresses which are about to expire from the cache
1387 static void *check_addr(u_int vaddr)
1389 struct ht_entry *ht_bin = hash_table_get(vaddr);
1391 for (i = 0; i < ARRAY_SIZE(ht_bin->vaddr); i++) {
1392 if (ht_bin->vaddr[i] == vaddr)
1393 if (doesnt_expire_soon(ht_bin->tcaddr[i]))
1394 return ht_bin->tcaddr[i];
1397 // refactor to get_addr_nocompile?
1398 u_int start_page = get_page_prev(vaddr);
1399 u_int page, end_page = get_page(vaddr);
1401 stat_inc(stat_jump_in_lookups);
1402 for (page = start_page; page <= end_page; page++) {
1403 const struct block_info *block;
1404 for (block = blocks[page]; block != NULL; block = block->next) {
1405 if (vaddr < block->start)
1407 if (block->is_dirty || vaddr >= block->start + block->len)
1409 if (!doesnt_expire_soon(ndrc->translation_cache + block->tc_offs))
1411 for (i = 0; i < block->jump_in_cnt; i++)
1412 if (block->jump_in[i].vaddr == vaddr)
1414 if (i == block->jump_in_cnt)
1417 // Update existing entry with current address
1418 void *addr = block->jump_in[i].addr;
1419 if (ht_bin->vaddr[0] == vaddr) {
1420 ht_bin->tcaddr[0] = addr;
1423 if (ht_bin->vaddr[1] == vaddr) {
1424 ht_bin->tcaddr[1] = addr;
1427 // Insert into hash table with low priority.
1428 // Don't evict existing entries, as they are probably
1429 // addresses that are being accessed frequently.
1430 if (ht_bin->vaddr[0] == -1) {
1431 ht_bin->vaddr[0] = vaddr;
1432 ht_bin->tcaddr[0] = addr;
1434 else if (ht_bin->vaddr[1] == -1) {
1435 ht_bin->vaddr[1] = vaddr;
1436 ht_bin->tcaddr[1] = addr;
1444 static void blocks_clear(struct block_info **head)
1446 struct block_info *cur, *next;
1448 if ((cur = *head)) {
1458 static int blocks_remove_matching_addrs(struct block_info **head,
1459 u_int base_offs, int shift)
1461 struct block_info *next;
1464 if ((((*head)->tc_offs ^ base_offs) >> shift) == 0) {
1465 inv_debug("EXP: rm block %08x (tc_offs %x)\n", (*head)->start, (*head)->tc_offs);
1466 invalidate_block(*head);
1467 next = (*head)->next;
1470 stat_dec(stat_blocks);
1475 head = &((*head)->next);
1481 // This is called when we write to a compiled block (see do_invstub)
1482 static void unlink_jumps_vaddr_range(u_int start, u_int end)
1484 u_int page, start_page = get_page(start), end_page = get_page(end - 1);
1487 for (page = start_page; page <= end_page; page++) {
1488 struct jump_info *ji = jumps[page];
1491 for (i = 0; i < ji->count; ) {
1492 if (ji->e[i].target_vaddr < start || ji->e[i].target_vaddr >= end) {
1497 inv_debug("INV: rm link to %08x (tc_offs %zx)\n", ji->e[i].target_vaddr,
1498 (u_char *)ji->e[i].stub - ndrc->translation_cache);
1499 void *host_addr = find_extjump_insn(ji->e[i].stub);
1500 mark_clear_cache(host_addr);
1501 set_jump_target(host_addr, ji->e[i].stub); // point back to dyna_linker stub
1503 stat_dec(stat_links);
1505 if (i < ji->count) {
1506 ji->e[i] = ji->e[ji->count];
1514 static void unlink_jumps_tc_range(struct jump_info *ji, u_int base_offs, int shift)
1519 for (i = 0; i < ji->count; ) {
1520 u_int tc_offs = (u_char *)ji->e[i].stub - ndrc->translation_cache;
1521 if (((tc_offs ^ base_offs) >> shift) != 0) {
1526 inv_debug("EXP: rm link to %08x (tc_offs %x)\n", ji->e[i].target_vaddr, tc_offs);
1527 stat_dec(stat_links);
1529 if (i < ji->count) {
1530 ji->e[i] = ji->e[ji->count];
1537 static void invalidate_block(struct block_info *block)
1541 block->is_dirty = 1;
1542 unlink_jumps_vaddr_range(block->start, block->start + block->len);
1543 for (i = 0; i < block->jump_in_cnt; i++)
1544 hash_table_remove(block->jump_in[i].vaddr);
1547 static int invalidate_range(u_int start, u_int end,
1548 u32 *inv_start_ret, u32 *inv_end_ret)
1550 struct block_info *last_block = NULL;
1551 u_int start_page = get_page_prev(start);
1552 u_int end_page = get_page(end - 1);
1553 u_int start_m = pmmask(start);
1554 u_int end_m = pmmask(end - 1);
1555 u_int inv_start, inv_end;
1556 u_int blk_start_m, blk_end_m;
1560 // additional area without code (to supplement invalid_code[]), [start, end)
1561 // avoids excessive ndrc_write_invalidate*() calls
1562 inv_start = start_m & ~0xfff;
1563 inv_end = end_m | 0xfff;
1565 for (page = start_page; page <= end_page; page++) {
1566 struct block_info *block;
1567 for (block = blocks[page]; block != NULL; block = block->next) {
1568 if (block->is_dirty)
1571 blk_end_m = pmmask(block->start + block->len);
1572 if (blk_end_m <= start_m) {
1573 inv_start = max(inv_start, blk_end_m);
1576 blk_start_m = pmmask(block->start);
1577 if (end_m <= blk_start_m) {
1578 inv_end = min(inv_end, blk_start_m - 1);
1581 if (!block->source) // "hack" block - leave it alone
1585 invalidate_block(block);
1586 stat_inc(stat_inv_hits);
1590 if (!hit && last_block && last_block->source) {
1591 // could be some leftover unused block, uselessly trapping writes
1592 last_block->inv_near_misses++;
1593 if (last_block->inv_near_misses > 128) {
1594 invalidate_block(last_block);
1595 stat_inc(stat_inv_hits);
1604 if (inv_start <= (start_m & ~0xfff) && inv_end >= (start_m | 0xfff))
1605 // the whole page is empty now
1606 mark_invalid_code(start, 1, 1);
1608 if (inv_start_ret) *inv_start_ret = inv_start | (start & 0xe0000000);
1609 if (inv_end_ret) *inv_end_ret = inv_end | (end & 0xe0000000);
1613 void new_dynarec_invalidate_range(unsigned int start, unsigned int end)
1615 invalidate_range(start, end, NULL, NULL);
1618 static void ndrc_write_invalidate_many(u_int start, u_int end)
1620 // this check is done by the caller
1621 //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
1622 int ret = invalidate_range(start, end, &inv_code_start, &inv_code_end);
1624 int invc = invalid_code[start >> 12];
1625 u_int len = end - start;
1627 printf("INV ADDR: %08x/%02x hit %d blocks\n", start, len, ret);
1629 printf("INV ADDR: %08x/%02x miss, inv %08x-%08x invc %d->%d\n", start, len,
1630 inv_code_start, inv_code_end, invc, invalid_code[start >> 12]);
1631 check_for_block_changes(start, end);
1633 stat_inc(stat_inv_addr_calls);
1637 void ndrc_write_invalidate_one(u_int addr)
1639 ndrc_write_invalidate_many(addr, addr + 4);
1642 // This is called when loading a save state.
1643 // Anything could have changed, so invalidate everything.
1644 void new_dynarec_invalidate_all_pages(void)
1646 struct block_info *block;
1648 for (page = 0; page < ARRAY_SIZE(blocks); page++) {
1649 for (block = blocks[page]; block != NULL; block = block->next) {
1650 if (block->is_dirty)
1652 if (!block->source) // hack block?
1654 invalidate_block(block);
1662 // Add an entry to jump_out after making a link
1663 // src should point to code by emit_extjump()
1664 void ndrc_add_jump_out(u_int vaddr, void *src)
1666 inv_debug("ndrc_add_jump_out: %p -> %x\n", src, vaddr);
1667 u_int page = get_page(vaddr);
1668 struct jump_info *ji;
1670 stat_inc(stat_links);
1671 check_extjump2(src);
1674 ji = malloc(sizeof(*ji) + sizeof(ji->e[0]) * 16);
1678 else if (ji->count >= ji->alloc) {
1680 ji = realloc(ji, sizeof(*ji) + sizeof(ji->e[0]) * ji->alloc);
1683 ji->e[ji->count].target_vaddr = vaddr;
1684 ji->e[ji->count].stub = src;
1688 /* Register allocation */
1690 static void alloc_set(struct regstat *cur, int reg, int hr)
1692 cur->regmap[hr] = reg;
1693 cur->dirty &= ~(1u << hr);
1694 cur->isconst &= ~(1u << hr);
1695 cur->noevict |= 1u << hr;
1698 static void evict_alloc_reg(struct regstat *cur, int i, int reg, int preferred_hr)
1700 u_char hsn[MAXREG+1];
1702 memset(hsn, 10, sizeof(hsn));
1704 //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
1706 // Don't evict the cycle count at entry points, otherwise the entry
1707 // stub will have to write it.
1708 if(dops[i].bt&&hsn[CCREG]>2) hsn[CCREG]=2;
1709 if (i>1 && hsn[CCREG] > 2 && dops[i-2].is_jump) hsn[CCREG]=2;
1712 // Alloc preferred register if available
1713 if (!((cur->noevict >> preferred_hr) & 1)
1714 && hsn[cur->regmap[preferred_hr]] == j)
1716 alloc_set(cur, reg, preferred_hr);
1719 for(r=1;r<=MAXREG;r++)
1721 if(hsn[r]==j&&r!=dops[i-1].rs1&&r!=dops[i-1].rs2&&r!=dops[i-1].rt1&&r!=dops[i-1].rt2) {
1722 for(hr=0;hr<HOST_REGS;hr++) {
1723 if (hr == EXCLUDE_REG || ((cur->noevict >> hr) & 1))
1725 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
1726 if(cur->regmap[hr]==r) {
1727 alloc_set(cur, reg, hr);
1738 for(r=1;r<=MAXREG;r++)
1741 for(hr=0;hr<HOST_REGS;hr++) {
1742 if (hr == EXCLUDE_REG || ((cur->noevict >> hr) & 1))
1744 if(cur->regmap[hr]==r) {
1745 alloc_set(cur, reg, hr);
1752 SysPrintf("This shouldn't happen (evict_alloc_reg)\n");
1756 // Note: registers are allocated clean (unmodified state)
1757 // if you intend to modify the register, you must call dirty_reg().
1758 static void alloc_reg(struct regstat *cur,int i,signed char reg)
1761 int preferred_reg = PREFERRED_REG_FIRST
1762 + reg % (PREFERRED_REG_LAST - PREFERRED_REG_FIRST + 1);
1763 if (reg == CCREG) preferred_reg = HOST_CCREG;
1764 if (reg == PTEMP || reg == FTEMP) preferred_reg = 12;
1765 assert(PREFERRED_REG_FIRST != EXCLUDE_REG && EXCLUDE_REG != HOST_REGS);
1768 // Don't allocate unused registers
1769 if((cur->u>>reg)&1) return;
1771 // see if it's already allocated
1772 if ((hr = get_reg(cur->regmap, reg)) >= 0) {
1773 cur->noevict |= 1u << hr;
1777 // Keep the same mapping if the register was already allocated in a loop
1778 preferred_reg = loop_reg(i,reg,preferred_reg);
1780 // Try to allocate the preferred register
1781 if (cur->regmap[preferred_reg] == -1) {
1782 alloc_set(cur, reg, preferred_reg);
1785 r=cur->regmap[preferred_reg];
1788 alloc_set(cur, reg, preferred_reg);
1792 // Clear any unneeded registers
1793 // We try to keep the mapping consistent, if possible, because it
1794 // makes branches easier (especially loops). So we try to allocate
1795 // first (see above) before removing old mappings. If this is not
1796 // possible then go ahead and clear out the registers that are no
1798 for(hr=0;hr<HOST_REGS;hr++)
1803 if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
1807 // Try to allocate any available register, but prefer
1808 // registers that have not been used recently.
1810 for (hr = PREFERRED_REG_FIRST; ; ) {
1811 if (cur->regmap[hr] < 0) {
1812 int oldreg = regs[i-1].regmap[hr];
1813 if (oldreg < 0 || (oldreg != dops[i-1].rs1 && oldreg != dops[i-1].rs2
1814 && oldreg != dops[i-1].rt1 && oldreg != dops[i-1].rt2))
1816 alloc_set(cur, reg, hr);
1821 if (hr == EXCLUDE_REG)
1823 if (hr == HOST_REGS)
1825 if (hr == PREFERRED_REG_FIRST)
1830 // Try to allocate any available register
1831 for (hr = PREFERRED_REG_FIRST; ; ) {
1832 if (cur->regmap[hr] < 0) {
1833 alloc_set(cur, reg, hr);
1837 if (hr == EXCLUDE_REG)
1839 if (hr == HOST_REGS)
1841 if (hr == PREFERRED_REG_FIRST)
1845 // Ok, now we have to evict someone
1846 // Pick a register we hopefully won't need soon
1847 evict_alloc_reg(cur, i, reg, preferred_reg);
1850 // Allocate a temporary register. This is done without regard to
1851 // dirty status or whether the register we request is on the unneeded list
1852 // Note: This will only allocate one register, even if called multiple times
1853 static void alloc_reg_temp(struct regstat *cur,int i,signed char reg)
1857 // see if it's already allocated
1858 for (hr = 0; hr < HOST_REGS; hr++)
1860 if (hr != EXCLUDE_REG && cur->regmap[hr] == reg) {
1861 cur->noevict |= 1u << hr;
1866 // Try to allocate any available register
1867 for(hr=HOST_REGS-1;hr>=0;hr--) {
1868 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
1869 alloc_set(cur, reg, hr);
1874 // Find an unneeded register
1875 for(hr=HOST_REGS-1;hr>=0;hr--)
1881 if(i==0||((unneeded_reg[i-1]>>r)&1)) {
1882 alloc_set(cur, reg, hr);
1889 // Ok, now we have to evict someone
1890 // Pick a register we hopefully won't need soon
1891 evict_alloc_reg(cur, i, reg, 0);
1894 static void mov_alloc(struct regstat *current,int i)
1896 if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) {
1897 alloc_cc(current,i); // for stalls
1898 dirty_reg(current,CCREG);
1901 // Note: Don't need to actually alloc the source registers
1902 //alloc_reg(current,i,dops[i].rs1);
1903 alloc_reg(current,i,dops[i].rt1);
1905 clear_const(current,dops[i].rs1);
1906 clear_const(current,dops[i].rt1);
1907 dirty_reg(current,dops[i].rt1);
1910 static void shiftimm_alloc(struct regstat *current,int i)
1912 if(dops[i].opcode2<=0x3) // SLL/SRL/SRA
1915 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1916 else dops[i].use_lt1=!!dops[i].rs1;
1917 alloc_reg(current,i,dops[i].rt1);
1918 dirty_reg(current,dops[i].rt1);
1919 if(is_const(current,dops[i].rs1)) {
1920 int v=get_const(current,dops[i].rs1);
1921 if(dops[i].opcode2==0x00) set_const(current,dops[i].rt1,v<<cinfo[i].imm);
1922 if(dops[i].opcode2==0x02) set_const(current,dops[i].rt1,(u_int)v>>cinfo[i].imm);
1923 if(dops[i].opcode2==0x03) set_const(current,dops[i].rt1,v>>cinfo[i].imm);
1925 else clear_const(current,dops[i].rt1);
1930 clear_const(current,dops[i].rs1);
1931 clear_const(current,dops[i].rt1);
1934 if(dops[i].opcode2>=0x38&&dops[i].opcode2<=0x3b) // DSLL/DSRL/DSRA
1938 if(dops[i].opcode2==0x3c) // DSLL32
1942 if(dops[i].opcode2==0x3e) // DSRL32
1946 if(dops[i].opcode2==0x3f) // DSRA32
1952 static void shift_alloc(struct regstat *current,int i)
1955 if(dops[i].rs1) alloc_reg(current,i,dops[i].rs1);
1956 if(dops[i].rs2) alloc_reg(current,i,dops[i].rs2);
1957 alloc_reg(current,i,dops[i].rt1);
1958 if(dops[i].rt1==dops[i].rs2) {
1959 alloc_reg_temp(current,i,-1);
1960 cinfo[i].min_free_regs=1;
1962 clear_const(current,dops[i].rs1);
1963 clear_const(current,dops[i].rs2);
1964 clear_const(current,dops[i].rt1);
1965 dirty_reg(current,dops[i].rt1);
1969 static void alu_alloc(struct regstat *current,int i)
1971 if(dops[i].opcode2>=0x20&&dops[i].opcode2<=0x23) { // ADD/ADDU/SUB/SUBU
1973 if(dops[i].rs1&&dops[i].rs2) {
1974 alloc_reg(current,i,dops[i].rs1);
1975 alloc_reg(current,i,dops[i].rs2);
1978 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1979 if(dops[i].rs2&&needed_again(dops[i].rs2,i)) alloc_reg(current,i,dops[i].rs2);
1981 alloc_reg(current,i,dops[i].rt1);
1983 if (dops[i].may_except) {
1984 alloc_cc_optional(current, i); // for exceptions
1985 alloc_reg_temp(current, i, -1);
1986 cinfo[i].min_free_regs = 1;
1989 else if(dops[i].opcode2==0x2a||dops[i].opcode2==0x2b) { // SLT/SLTU
1991 alloc_reg(current,i,dops[i].rs1);
1992 alloc_reg(current,i,dops[i].rs2);
1993 alloc_reg(current,i,dops[i].rt1);
1996 else if(dops[i].opcode2>=0x24&&dops[i].opcode2<=0x27) { // AND/OR/XOR/NOR
1998 if(dops[i].rs1&&dops[i].rs2) {
1999 alloc_reg(current,i,dops[i].rs1);
2000 alloc_reg(current,i,dops[i].rs2);
2004 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
2005 if(dops[i].rs2&&needed_again(dops[i].rs2,i)) alloc_reg(current,i,dops[i].rs2);
2007 alloc_reg(current,i,dops[i].rt1);
2010 clear_const(current,dops[i].rs1);
2011 clear_const(current,dops[i].rs2);
2012 clear_const(current,dops[i].rt1);
2013 dirty_reg(current,dops[i].rt1);
2016 static void imm16_alloc(struct regstat *current,int i)
2018 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
2019 else dops[i].use_lt1=!!dops[i].rs1;
2020 if(dops[i].rt1) alloc_reg(current,i,dops[i].rt1);
2021 if(dops[i].opcode==0x0a||dops[i].opcode==0x0b) { // SLTI/SLTIU
2022 clear_const(current,dops[i].rs1);
2023 clear_const(current,dops[i].rt1);
2025 else if(dops[i].opcode>=0x0c&&dops[i].opcode<=0x0e) { // ANDI/ORI/XORI
2026 if(is_const(current,dops[i].rs1)) {
2027 int v=get_const(current,dops[i].rs1);
2028 if(dops[i].opcode==0x0c) set_const(current,dops[i].rt1,v&cinfo[i].imm);
2029 if(dops[i].opcode==0x0d) set_const(current,dops[i].rt1,v|cinfo[i].imm);
2030 if(dops[i].opcode==0x0e) set_const(current,dops[i].rt1,v^cinfo[i].imm);
2032 else clear_const(current,dops[i].rt1);
2034 else if(dops[i].opcode==0x08||dops[i].opcode==0x09) { // ADDI/ADDIU
2035 if(is_const(current,dops[i].rs1)) {
2036 int v=get_const(current,dops[i].rs1);
2037 set_const(current,dops[i].rt1,v+cinfo[i].imm);
2039 else clear_const(current,dops[i].rt1);
2040 if (dops[i].may_except) {
2041 alloc_cc_optional(current, i); // for exceptions
2042 alloc_reg_temp(current, i, -1);
2043 cinfo[i].min_free_regs = 1;
2047 set_const(current,dops[i].rt1,cinfo[i].imm<<16); // LUI
2049 dirty_reg(current,dops[i].rt1);
2052 static void load_alloc(struct regstat *current,int i)
2055 clear_const(current,dops[i].rt1);
2056 //if(dops[i].rs1!=dops[i].rt1&&needed_again(dops[i].rs1,i)) clear_const(current,dops[i].rs1); // Does this help or hurt?
2057 if(!dops[i].rs1) current->u&=~1LL; // Allow allocating r0 if it's the source register
2058 if (needed_again(dops[i].rs1, i))
2059 alloc_reg(current, i, dops[i].rs1);
2061 alloc_reg(current, i, ROREG);
2062 if (dops[i].may_except) {
2063 alloc_cc_optional(current, i); // for exceptions
2066 if(dops[i].rt1&&!((current->u>>dops[i].rt1)&1)) {
2067 alloc_reg(current,i,dops[i].rt1);
2068 assert(get_reg_w(current->regmap, dops[i].rt1)>=0);
2069 dirty_reg(current,dops[i].rt1);
2070 // LWL/LWR need a temporary register for the old value
2071 if(dops[i].opcode==0x22||dops[i].opcode==0x26)
2073 alloc_reg(current,i,FTEMP);
2079 // Load to r0 or unneeded register (dummy load)
2080 // but we still need a register to calculate the address
2081 if(dops[i].opcode==0x22||dops[i].opcode==0x26)
2082 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
2086 alloc_reg_temp(current, i, -1);
2087 cinfo[i].min_free_regs = 1;
2091 // this may eat up to 7 registers
2092 static void store_alloc(struct regstat *current, int i)
2094 clear_const(current,dops[i].rs2);
2095 if(!(dops[i].rs2)) current->u&=~1LL; // Allow allocating r0 if necessary
2096 if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
2097 alloc_reg(current,i,dops[i].rs2);
2099 alloc_reg(current, i, ROREG);
2100 #if defined(HOST_IMM8)
2101 // On CPUs without 32-bit immediates we need a pointer to invalid_code
2102 alloc_reg(current, i, INVCP);
2104 if (dops[i].opcode == 0x2a || dops[i].opcode == 0x2e) { // SWL/SWL
2105 alloc_reg(current,i,FTEMP);
2107 if (dops[i].may_except)
2108 alloc_cc_optional(current, i); // for exceptions
2109 // We need a temporary register for address generation
2110 alloc_reg_temp(current,i,-1);
2111 cinfo[i].min_free_regs=1;
2114 static void c2ls_alloc(struct regstat *current, int i)
2116 clear_const(current,dops[i].rt1);
2117 if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
2118 alloc_reg(current,i,FTEMP);
2120 alloc_reg(current, i, ROREG);
2121 #if defined(HOST_IMM8)
2122 // On CPUs without 32-bit immediates we need a pointer to invalid_code
2123 if (dops[i].opcode == 0x3a) // SWC2
2124 alloc_reg(current,i,INVCP);
2126 if (dops[i].may_except)
2127 alloc_cc_optional(current, i); // for exceptions
2128 // We need a temporary register for address generation
2129 alloc_reg_temp(current,i,-1);
2130 cinfo[i].min_free_regs=1;
2133 #ifndef multdiv_alloc
2134 static void multdiv_alloc(struct regstat *current,int i)
2140 clear_const(current,dops[i].rs1);
2141 clear_const(current,dops[i].rs2);
2142 alloc_cc(current,i); // for stalls
2143 dirty_reg(current,CCREG);
2144 current->u &= ~(1ull << HIREG);
2145 current->u &= ~(1ull << LOREG);
2146 alloc_reg(current, i, HIREG);
2147 alloc_reg(current, i, LOREG);
2148 dirty_reg(current, HIREG);
2149 dirty_reg(current, LOREG);
2150 if ((dops[i].opcode2 & 0x3e) == 0x1a || (dops[i].rs1 && dops[i].rs2)) // div(u)
2152 alloc_reg(current, i, dops[i].rs1);
2153 alloc_reg(current, i, dops[i].rs2);
2155 // else multiply by zero is zero
2159 static void cop0_alloc(struct regstat *current,int i)
2161 if(dops[i].opcode2==0) // MFC0
2164 clear_const(current,dops[i].rt1);
2165 alloc_reg(current,i,dops[i].rt1);
2166 dirty_reg(current,dops[i].rt1);
2169 else if(dops[i].opcode2==4) // MTC0
2171 if (((source[i]>>11)&0x1e) == 12) {
2172 alloc_cc(current, i);
2173 dirty_reg(current, CCREG);
2176 clear_const(current,dops[i].rs1);
2177 alloc_reg(current,i,dops[i].rs1);
2178 alloc_all(current,i);
2181 alloc_all(current,i); // FIXME: Keep r0
2183 alloc_reg(current,i,0);
2185 cinfo[i].min_free_regs = HOST_REGS;
2189 static void rfe_alloc(struct regstat *current, int i)
2191 alloc_all(current, i);
2192 cinfo[i].min_free_regs = HOST_REGS;
2195 static void cop2_alloc(struct regstat *current,int i)
2197 if (dops[i].opcode2 < 3) // MFC2/CFC2
2199 alloc_cc(current,i); // for stalls
2200 dirty_reg(current,CCREG);
2202 clear_const(current,dops[i].rt1);
2203 alloc_reg(current,i,dops[i].rt1);
2204 dirty_reg(current,dops[i].rt1);
2207 else if (dops[i].opcode2 > 3) // MTC2/CTC2
2210 clear_const(current,dops[i].rs1);
2211 alloc_reg(current,i,dops[i].rs1);
2215 alloc_reg(current,i,0);
2218 alloc_reg_temp(current,i,-1);
2219 cinfo[i].min_free_regs=1;
2222 static void c2op_alloc(struct regstat *current,int i)
2224 alloc_cc(current,i); // for stalls
2225 dirty_reg(current,CCREG);
2226 alloc_reg_temp(current,i,-1);
2229 static void syscall_alloc(struct regstat *current,int i)
2231 alloc_cc(current,i);
2232 dirty_reg(current,CCREG);
2233 alloc_all(current,i);
2234 cinfo[i].min_free_regs=HOST_REGS;
2238 static void delayslot_alloc(struct regstat *current,int i)
2240 switch(dops[i].itype) {
2248 imm16_alloc(current,i);
2252 load_alloc(current,i);
2256 store_alloc(current,i);
2259 alu_alloc(current,i);
2262 shift_alloc(current,i);
2265 multdiv_alloc(current,i);
2268 shiftimm_alloc(current,i);
2271 mov_alloc(current,i);
2274 cop0_alloc(current,i);
2277 rfe_alloc(current,i);
2280 cop2_alloc(current,i);
2283 c2ls_alloc(current,i);
2286 c2op_alloc(current,i);
2291 static void add_stub(enum stub_type type, void *addr, void *retaddr,
2292 u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e)
2294 assert(stubcount < ARRAY_SIZE(stubs));
2295 stubs[stubcount].type = type;
2296 stubs[stubcount].addr = addr;
2297 stubs[stubcount].retaddr = retaddr;
2298 stubs[stubcount].a = a;
2299 stubs[stubcount].b = b;
2300 stubs[stubcount].c = c;
2301 stubs[stubcount].d = d;
2302 stubs[stubcount].e = e;
2306 static void add_stub_r(enum stub_type type, void *addr, void *retaddr,
2307 int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist)
2309 add_stub(type, addr, retaddr, i, addr_reg, (uintptr_t)i_regs, ccadj, reglist);
2312 // Write out a single register
2313 static void wb_register(signed char r, const signed char regmap[], u_int dirty)
2316 for(hr=0;hr<HOST_REGS;hr++) {
2317 if(hr!=EXCLUDE_REG) {
2320 assert(regmap[hr]<64);
2321 emit_storereg(r,hr);
2329 static void wb_valid(signed char pre[],signed char entry[],u_int dirty_pre,u_int dirty,uint64_t u)
2331 //if(dirty_pre==dirty) return;
2333 for (hr = 0; hr < HOST_REGS; hr++) {
2335 if (r < 1 || r > 33 || ((u >> r) & 1))
2337 if (((dirty_pre & ~dirty) >> hr) & 1)
2338 emit_storereg(r, hr);
2343 static void pass_args(int a0, int a1)
2347 emit_mov(a0,2); emit_mov(a1,1); emit_mov(2,0);
2349 else if(a0!=0&&a1==0) {
2351 if (a0>=0) emit_mov(a0,0);
2354 if(a0>=0&&a0!=0) emit_mov(a0,0);
2355 if(a1>=0&&a1!=1) emit_mov(a1,1);
2359 static void alu_assemble(int i, const struct regstat *i_regs, int ccadj_)
2361 if(dops[i].opcode2>=0x20&&dops[i].opcode2<=0x23) { // ADD/ADDU/SUB/SUBU
2362 int do_oflow = dops[i].may_except; // ADD/SUB with exceptions enabled
2363 if (dops[i].rt1 || do_oflow) {
2364 int do_exception_check = 0;
2365 signed char s1, s2, t, tmp;
2366 t = get_reg_w(i_regs->regmap, dops[i].rt1);
2367 tmp = get_reg_temp(i_regs->regmap);
2370 if (t < 0 && do_oflow)
2373 s1 = get_reg(i_regs->regmap, dops[i].rs1);
2374 s2 = get_reg(i_regs->regmap, dops[i].rs2);
2375 if (dops[i].rs1 && dops[i].rs2) {
2378 if (dops[i].opcode2 & 2) {
2380 emit_subs(s1, s2, tmp);
2381 do_exception_check = 1;
2388 emit_adds(s1, s2, tmp);
2389 do_exception_check = 1;
2395 else if(dops[i].rs1) {
2396 if(s1>=0) emit_mov(s1,t);
2397 else emit_loadreg(dops[i].rs1,t);
2399 else if(dops[i].rs2) {
2401 emit_loadreg(dops[i].rs2, t);
2404 if (dops[i].opcode2 & 2) {
2407 do_exception_check = 1;
2418 if (do_exception_check) {
2421 if (t >= 0 && tmp != t)
2423 add_stub_r(OVERFLOW_STUB, jaddr, out, i, 0, i_regs, ccadj_, 0);
2427 else if(dops[i].opcode2==0x2a||dops[i].opcode2==0x2b) { // SLT/SLTU
2429 signed char s1l,s2l,t;
2431 t=get_reg_w(i_regs->regmap, dops[i].rt1);
2434 s1l=get_reg(i_regs->regmap,dops[i].rs1);
2435 s2l=get_reg(i_regs->regmap,dops[i].rs2);
2436 if(dops[i].rs2==0) // rx<r0
2438 if(dops[i].opcode2==0x2a&&dops[i].rs1!=0) { // SLT
2440 emit_shrimm(s1l,31,t);
2442 else // SLTU (unsigned can not be less than zero, 0<0)
2445 else if(dops[i].rs1==0) // r0<rx
2448 if(dops[i].opcode2==0x2a) // SLT
2449 emit_set_gz32(s2l,t);
2450 else // SLTU (set if not zero)
2451 emit_set_nz32(s2l,t);
2454 assert(s1l>=0);assert(s2l>=0);
2455 if(dops[i].opcode2==0x2a) // SLT
2456 emit_set_if_less32(s1l,s2l,t);
2458 emit_set_if_carry32(s1l,s2l,t);
2464 else if(dops[i].opcode2>=0x24&&dops[i].opcode2<=0x27) { // AND/OR/XOR/NOR
2466 signed char s1l,s2l,tl;
2467 tl=get_reg_w(i_regs->regmap, dops[i].rt1);
2470 s1l=get_reg(i_regs->regmap,dops[i].rs1);
2471 s2l=get_reg(i_regs->regmap,dops[i].rs2);
2472 if(dops[i].rs1&&dops[i].rs2) {
2475 if(dops[i].opcode2==0x24) { // AND
2476 emit_and(s1l,s2l,tl);
2478 if(dops[i].opcode2==0x25) { // OR
2479 emit_or(s1l,s2l,tl);
2481 if(dops[i].opcode2==0x26) { // XOR
2482 emit_xor(s1l,s2l,tl);
2484 if(dops[i].opcode2==0x27) { // NOR
2485 emit_or(s1l,s2l,tl);
2491 if(dops[i].opcode2==0x24) { // AND
2494 if(dops[i].opcode2==0x25||dops[i].opcode2==0x26) { // OR/XOR
2496 if(s1l>=0) emit_mov(s1l,tl);
2497 else emit_loadreg(dops[i].rs1,tl); // CHECK: regmap_entry?
2501 if(s2l>=0) emit_mov(s2l,tl);
2502 else emit_loadreg(dops[i].rs2,tl); // CHECK: regmap_entry?
2504 else emit_zeroreg(tl);
2506 if(dops[i].opcode2==0x27) { // NOR
2508 if(s1l>=0) emit_not(s1l,tl);
2510 emit_loadreg(dops[i].rs1,tl);
2516 if(s2l>=0) emit_not(s2l,tl);
2518 emit_loadreg(dops[i].rs2,tl);
2522 else emit_movimm(-1,tl);
2531 static void imm16_assemble(int i, const struct regstat *i_regs, int ccadj_)
2533 if (dops[i].opcode==0x0f) { // LUI
2536 t=get_reg_w(i_regs->regmap, dops[i].rt1);
2539 if(!((i_regs->isconst>>t)&1))
2540 emit_movimm(cinfo[i].imm<<16,t);
2544 if(dops[i].opcode==0x08||dops[i].opcode==0x09) { // ADDI/ADDIU
2545 int is_addi = dops[i].may_except;
2546 if (dops[i].rt1 || is_addi) {
2547 signed char s, t, tmp;
2548 t=get_reg_w(i_regs->regmap, dops[i].rt1);
2549 s=get_reg(i_regs->regmap,dops[i].rs1);
2551 tmp = get_reg_temp(i_regs->regmap);
2557 if(!((i_regs->isconst>>t)&1)) {
2558 int sum, do_exception_check = 0;
2560 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
2562 emit_addimm_and_set_flags3(t, cinfo[i].imm, tmp);
2563 do_exception_check = 1;
2566 emit_addimm(t, cinfo[i].imm, t);
2568 if (!((i_regs->wasconst >> s) & 1)) {
2570 emit_addimm_and_set_flags3(s, cinfo[i].imm, tmp);
2571 do_exception_check = 1;
2574 emit_addimm(s, cinfo[i].imm, t);
2577 int oflow = add_overflow(constmap[i][s], cinfo[i].imm, sum);
2578 if (is_addi && oflow)
2579 do_exception_check = 2;
2581 emit_movimm(sum, t);
2584 if (do_exception_check) {
2586 if (do_exception_check == 2)
2593 add_stub_r(OVERFLOW_STUB, jaddr, out, i, 0, i_regs, ccadj_, 0);
2599 if(!((i_regs->isconst>>t)&1))
2600 emit_movimm(cinfo[i].imm,t);
2605 else if(dops[i].opcode==0x0a||dops[i].opcode==0x0b) { // SLTI/SLTIU
2607 //assert(dops[i].rs1!=0); // r0 might be valid, but it's probably a bug
2609 t=get_reg_w(i_regs->regmap, dops[i].rt1);
2610 sl=get_reg(i_regs->regmap,dops[i].rs1);
2614 if(dops[i].opcode==0x0a) { // SLTI
2616 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
2617 emit_slti32(t,cinfo[i].imm,t);
2619 emit_slti32(sl,cinfo[i].imm,t);
2624 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
2625 emit_sltiu32(t,cinfo[i].imm,t);
2627 emit_sltiu32(sl,cinfo[i].imm,t);
2631 // SLTI(U) with r0 is just stupid,
2632 // nonetheless examples can be found
2633 if(dops[i].opcode==0x0a) // SLTI
2634 if(0<cinfo[i].imm) emit_movimm(1,t);
2635 else emit_zeroreg(t);
2638 if(cinfo[i].imm) emit_movimm(1,t);
2639 else emit_zeroreg(t);
2645 else if(dops[i].opcode>=0x0c&&dops[i].opcode<=0x0e) { // ANDI/ORI/XORI
2648 tl=get_reg_w(i_regs->regmap, dops[i].rt1);
2649 sl=get_reg(i_regs->regmap,dops[i].rs1);
2650 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2651 if(dops[i].opcode==0x0c) //ANDI
2655 if(i_regs->regmap_entry[tl]!=dops[i].rs1) emit_loadreg(dops[i].rs1,tl);
2656 emit_andimm(tl,cinfo[i].imm,tl);
2658 if(!((i_regs->wasconst>>sl)&1))
2659 emit_andimm(sl,cinfo[i].imm,tl);
2661 emit_movimm(constmap[i][sl]&cinfo[i].imm,tl);
2671 if(i_regs->regmap_entry[tl]!=dops[i].rs1) emit_loadreg(dops[i].rs1,tl);
2673 if(dops[i].opcode==0x0d) { // ORI
2675 emit_orimm(tl,cinfo[i].imm,tl);
2677 if(!((i_regs->wasconst>>sl)&1))
2678 emit_orimm(sl,cinfo[i].imm,tl);
2680 emit_movimm(constmap[i][sl]|cinfo[i].imm,tl);
2683 if(dops[i].opcode==0x0e) { // XORI
2685 emit_xorimm(tl,cinfo[i].imm,tl);
2687 if(!((i_regs->wasconst>>sl)&1))
2688 emit_xorimm(sl,cinfo[i].imm,tl);
2690 emit_movimm(constmap[i][sl]^cinfo[i].imm,tl);
2695 emit_movimm(cinfo[i].imm,tl);
2703 static void shiftimm_assemble(int i, const struct regstat *i_regs)
2705 if(dops[i].opcode2<=0x3) // SLL/SRL/SRA
2709 t=get_reg_w(i_regs->regmap, dops[i].rt1);
2710 s=get_reg(i_regs->regmap,dops[i].rs1);
2712 if(t>=0&&!((i_regs->isconst>>t)&1)){
2719 if(s<0&&i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
2721 if(dops[i].opcode2==0) // SLL
2723 emit_shlimm(s<0?t:s,cinfo[i].imm,t);
2725 if(dops[i].opcode2==2) // SRL
2727 emit_shrimm(s<0?t:s,cinfo[i].imm,t);
2729 if(dops[i].opcode2==3) // SRA
2731 emit_sarimm(s<0?t:s,cinfo[i].imm,t);
2735 if(s>=0 && s!=t) emit_mov(s,t);
2739 //emit_storereg(dops[i].rt1,t); //DEBUG
2742 if(dops[i].opcode2>=0x38&&dops[i].opcode2<=0x3b) // DSLL/DSRL/DSRA
2746 if(dops[i].opcode2==0x3c) // DSLL32
2750 if(dops[i].opcode2==0x3e) // DSRL32
2754 if(dops[i].opcode2==0x3f) // DSRA32
2760 #ifndef shift_assemble
2761 static void shift_assemble(int i, const struct regstat *i_regs)
2763 signed char s,t,shift;
2764 if (dops[i].rt1 == 0)
2766 assert(dops[i].opcode2<=0x07); // SLLV/SRLV/SRAV
2767 t = get_reg(i_regs->regmap, dops[i].rt1);
2768 s = get_reg(i_regs->regmap, dops[i].rs1);
2769 shift = get_reg(i_regs->regmap, dops[i].rs2);
2775 else if(dops[i].rs2==0) {
2777 if(s!=t) emit_mov(s,t);
2780 host_tempreg_acquire();
2781 emit_andimm(shift,31,HOST_TEMPREG);
2782 switch(dops[i].opcode2) {
2784 emit_shl(s,HOST_TEMPREG,t);
2787 emit_shr(s,HOST_TEMPREG,t);
2790 emit_sar(s,HOST_TEMPREG,t);
2795 host_tempreg_release();
2809 static int get_ptr_mem_type(u_int a)
2811 if(a < 0x00200000) {
2812 if(a<0x1000&&((start>>20)==0xbfc||(start>>24)==0xa0))
2813 // return wrong, must use memhandler for BIOS self-test to pass
2814 // 007 does similar stuff from a00 mirror, weird stuff
2818 if(0x1f800000 <= a && a < 0x1f801000)
2820 if(0x80200000 <= a && a < 0x80800000)
2822 if(0xa0000000 <= a && a < 0xa0200000)
2827 static int get_ro_reg(const struct regstat *i_regs, int host_tempreg_free)
2829 int r = get_reg(i_regs->regmap, ROREG);
2830 if (r < 0 && host_tempreg_free) {
2831 host_tempreg_acquire();
2832 emit_loadreg(ROREG, r = HOST_TEMPREG);
2839 static void *emit_fastpath_cmp_jump(int i, const struct regstat *i_regs,
2840 int addr, int *offset_reg, int *addr_reg_override, int ccadj_)
2844 int mr = dops[i].rs1;
2847 if(((smrv_strong|smrv_weak)>>mr)&1) {
2848 type=get_ptr_mem_type(smrv[mr]);
2849 //printf("set %08x @%08x r%d %d\n", smrv[mr], start+i*4, mr, type);
2852 // use the mirror we are running on
2853 type=get_ptr_mem_type(start);
2854 //printf("set nospec @%08x r%d %d\n", start+i*4, mr, type);
2857 if (dops[i].may_except) {
2859 u_int op = dops[i].opcode;
2860 int mask = ((op & 0x37) == 0x21 || op == 0x25) ? 1 : 3; // LH/SH/LHU
2862 emit_testimm(addr, mask);
2865 add_stub_r(ALIGNMENT_STUB, jaddr2, out, i, addr, i_regs, ccadj_, 0);
2868 if(type==MTYPE_8020) { // RAM 80200000+ mirror
2869 host_tempreg_acquire();
2870 emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
2871 addr=*addr_reg_override=HOST_TEMPREG;
2874 else if(type==MTYPE_0000) { // RAM 0 mirror
2875 host_tempreg_acquire();
2876 emit_orimm(addr,0x80000000,HOST_TEMPREG);
2877 addr=*addr_reg_override=HOST_TEMPREG;
2880 else if(type==MTYPE_A000) { // RAM A mirror
2881 host_tempreg_acquire();
2882 emit_andimm(addr,~0x20000000,HOST_TEMPREG);
2883 addr=*addr_reg_override=HOST_TEMPREG;
2886 else if(type==MTYPE_1F80) { // scratchpad
2887 if (psxH == (void *)0x1f800000) {
2888 host_tempreg_acquire();
2889 emit_xorimm(addr,0x1f800000,HOST_TEMPREG);
2890 emit_cmpimm(HOST_TEMPREG,0x1000);
2891 host_tempreg_release();
2896 // do the usual RAM check, jump will go to the right handler
2901 if (type == 0) // need ram check
2903 emit_cmpimm(addr,RAM_SIZE);
2905 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2906 // Hint to branch predictor that the branch is unlikely to be taken
2907 if (dops[i].rs1 >= 28)
2908 emit_jno_unlikely(0);
2912 if (ram_offset != 0)
2913 *offset_reg = get_ro_reg(i_regs, 0);
2919 // return memhandler, or get directly accessable address and return 0
2920 static void *get_direct_memhandler(void *table, u_int addr,
2921 enum stub_type type, uintptr_t *addr_host)
2923 uintptr_t msb = 1ull << (sizeof(uintptr_t)*8 - 1);
2924 uintptr_t l1, l2 = 0;
2925 l1 = ((uintptr_t *)table)[addr>>12];
2927 uintptr_t v = l1 << 1;
2928 *addr_host = v + addr;
2933 if (type == LOADB_STUB || type == LOADBU_STUB || type == STOREB_STUB)
2934 l2 = ((uintptr_t *)l1)[0x1000/4 + 0x1000/2 + (addr&0xfff)];
2935 else if (type == LOADH_STUB || type == LOADHU_STUB || type == STOREH_STUB)
2936 l2 = ((uintptr_t *)l1)[0x1000/4 + (addr&0xfff)/2];
2938 l2 = ((uintptr_t *)l1)[(addr&0xfff)/4];
2940 uintptr_t v = l2 << 1;
2941 *addr_host = v + (addr&0xfff);
2944 return (void *)(l2 << 1);
2948 static u_int get_host_reglist(const signed char *regmap)
2950 u_int reglist = 0, hr;
2951 for (hr = 0; hr < HOST_REGS; hr++) {
2952 if (hr != EXCLUDE_REG && regmap[hr] >= 0)
2958 static u_int reglist_exclude(u_int reglist, int r1, int r2)
2961 reglist &= ~(1u << r1);
2963 reglist &= ~(1u << r2);
2967 // find a temp caller-saved register not in reglist (so assumed to be free)
2968 static int reglist_find_free(u_int reglist)
2970 u_int free_regs = ~reglist & CALLER_SAVE_REGS;
2973 return __builtin_ctz(free_regs);
2976 static void do_load_word(int a, int rt, int offset_reg)
2978 if (offset_reg >= 0)
2979 emit_ldr_dualindexed(offset_reg, a, rt);
2981 emit_readword_indexed(0, a, rt);
2984 static void do_store_word(int a, int ofs, int rt, int offset_reg, int preseve_a)
2986 if (offset_reg < 0) {
2987 emit_writeword_indexed(rt, ofs, a);
2991 emit_addimm(a, ofs, a);
2992 emit_str_dualindexed(offset_reg, a, rt);
2993 if (ofs != 0 && preseve_a)
2994 emit_addimm(a, -ofs, a);
2997 static void do_store_hword(int a, int ofs, int rt, int offset_reg, int preseve_a)
2999 if (offset_reg < 0) {
3000 emit_writehword_indexed(rt, ofs, a);
3004 emit_addimm(a, ofs, a);
3005 emit_strh_dualindexed(offset_reg, a, rt);
3006 if (ofs != 0 && preseve_a)
3007 emit_addimm(a, -ofs, a);
3010 static void do_store_byte(int a, int rt, int offset_reg)
3012 if (offset_reg >= 0)
3013 emit_strb_dualindexed(offset_reg, a, rt);
3015 emit_writebyte_indexed(rt, 0, a);
3018 static void load_assemble(int i, const struct regstat *i_regs, int ccadj_)
3020 int addr = cinfo[i].addr;
3024 int memtarget=0,c=0;
3025 int offset_reg = -1;
3026 int fastio_reg_override = -1;
3027 u_int reglist=get_host_reglist(i_regs->regmap);
3028 tl=get_reg_w(i_regs->regmap, dops[i].rt1);
3029 s=get_reg(i_regs->regmap,dops[i].rs1);
3030 offset=cinfo[i].imm;
3031 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3033 c=(i_regs->wasconst>>s)&1;
3035 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3038 //printf("load_assemble: c=%d\n",c);
3039 //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset);
3040 if(tl<0 && ((!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80) || dops[i].rt1==0)) {
3041 // could be FIFO, must perform the read
3043 assem_debug("(forced read)\n");
3044 tl = get_reg_temp(i_regs->regmap); // may be == addr
3049 //printf("load_assemble: c=%d\n",c);
3050 //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset);
3054 // Strmnnrmn's speed hack
3055 if(dops[i].rs1!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3058 jaddr = emit_fastpath_cmp_jump(i, i_regs, addr,
3059 &offset_reg, &fastio_reg_override, ccadj_);
3062 else if (ram_offset && memtarget) {
3063 offset_reg = get_ro_reg(i_regs, 0);
3065 int dummy=(dops[i].rt1==0)||(tl!=get_reg_w(i_regs->regmap, dops[i].rt1)); // ignore loads to r0 and unneeded reg
3066 switch (dops[i].opcode) {
3071 if (fastio_reg_override >= 0)
3072 a = fastio_reg_override;
3074 if (offset_reg >= 0)
3075 emit_ldrsb_dualindexed(offset_reg, a, tl);
3077 emit_movsbl_indexed(0, a, tl);
3080 add_stub_r(LOADB_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
3083 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
3089 if (fastio_reg_override >= 0)
3090 a = fastio_reg_override;
3091 if (offset_reg >= 0)
3092 emit_ldrsh_dualindexed(offset_reg, a, tl);
3094 emit_movswl_indexed(0, a, tl);
3097 add_stub_r(LOADH_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
3100 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
3106 if (fastio_reg_override >= 0)
3107 a = fastio_reg_override;
3108 do_load_word(a, tl, offset_reg);
3111 add_stub_r(LOADW_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
3114 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
3120 if (fastio_reg_override >= 0)
3121 a = fastio_reg_override;
3123 if (offset_reg >= 0)
3124 emit_ldrb_dualindexed(offset_reg, a, tl);
3126 emit_movzbl_indexed(0, a, tl);
3129 add_stub_r(LOADBU_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
3132 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
3138 if (fastio_reg_override >= 0)
3139 a = fastio_reg_override;
3140 if (offset_reg >= 0)
3141 emit_ldrh_dualindexed(offset_reg, a, tl);
3143 emit_movzwl_indexed(0, a, tl);
3146 add_stub_r(LOADHU_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
3149 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
3155 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
3156 host_tempreg_release();
3159 #ifndef loadlr_assemble
3160 static void loadlr_assemble(int i, const struct regstat *i_regs, int ccadj_)
3162 int addr = cinfo[i].addr;
3163 int s,tl,temp,temp2;
3166 int memtarget=0,c=0;
3167 int offset_reg = -1;
3168 int fastio_reg_override = -1;
3169 u_int reglist=get_host_reglist(i_regs->regmap);
3170 tl=get_reg_w(i_regs->regmap, dops[i].rt1);
3171 s=get_reg(i_regs->regmap,dops[i].rs1);
3172 temp=get_reg_temp(i_regs->regmap);
3173 temp2=get_reg(i_regs->regmap,FTEMP);
3174 offset=cinfo[i].imm;
3178 c=(i_regs->wasconst>>s)&1;
3180 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3184 emit_shlimm(addr,3,temp);
3185 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
3186 emit_andimm(addr,0xFFFFFFFC,temp2); // LWL/LWR
3188 emit_andimm(addr,0xFFFFFFF8,temp2); // LDL/LDR
3190 jaddr = emit_fastpath_cmp_jump(i, i_regs, temp2,
3191 &offset_reg, &fastio_reg_override, ccadj_);
3194 if (ram_offset && memtarget) {
3195 offset_reg = get_ro_reg(i_regs, 0);
3197 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
3198 emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR
3200 emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR
3203 if (dops[i].opcode==0x22||dops[i].opcode==0x26) { // LWL/LWR
3206 if (fastio_reg_override >= 0)
3207 a = fastio_reg_override;
3208 do_load_word(a, temp2, offset_reg);
3209 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
3210 host_tempreg_release();
3211 if(jaddr) add_stub_r(LOADW_STUB,jaddr,out,i,temp2,i_regs,ccadj_,reglist);
3214 inline_readstub(LOADW_STUB,i,(constmap[i][s]+offset)&0xFFFFFFFC,i_regs->regmap,FTEMP,ccadj_,reglist);
3217 emit_andimm(temp,24,temp);
3218 if (dops[i].opcode==0x22) // LWL
3219 emit_xorimm(temp,24,temp);
3220 host_tempreg_acquire();
3221 emit_movimm(-1,HOST_TEMPREG);
3222 if (dops[i].opcode==0x26) {
3223 emit_shr(temp2,temp,temp2);
3224 emit_bic_lsr(tl,HOST_TEMPREG,temp,tl);
3226 emit_shl(temp2,temp,temp2);
3227 emit_bic_lsl(tl,HOST_TEMPREG,temp,tl);
3229 host_tempreg_release();
3230 emit_or(temp2,tl,tl);
3232 //emit_storereg(dops[i].rt1,tl); // DEBUG
3234 if (dops[i].opcode==0x1A||dops[i].opcode==0x1B) { // LDL/LDR
3240 static void do_invstub(int n)
3243 assem_debug("do_invstub %x\n", start + stubs[n].e*4);
3244 u_int reglist = stubs[n].a;
3245 u_int addrr = stubs[n].b;
3246 int ofs_start = stubs[n].c;
3247 int ofs_end = stubs[n].d;
3248 int len = ofs_end - ofs_start;
3251 set_jump_target(stubs[n].addr, out);
3253 if (addrr != 0 || ofs_start != 0)
3254 emit_addimm(addrr, ofs_start, 0);
3255 emit_readword(&inv_code_start, 2);
3256 emit_readword(&inv_code_end, 3);
3258 emit_addimm(0, len + 4, (rightr = 1));
3260 emit_cmpcs(3, rightr);
3263 void *func = (len != 0)
3264 ? (void *)ndrc_write_invalidate_many
3265 : (void *)ndrc_write_invalidate_one;
3266 emit_far_call(func);
3267 set_jump_target(jaddr, out);
3268 restore_regs(reglist);
3269 emit_jmp(stubs[n].retaddr);
3272 static void do_store_smc_check(int i, const struct regstat *i_regs, u_int reglist, int addr)
3274 if (HACK_ENABLED(NDHACK_NO_SMC_CHECK))
3276 // this can't be used any more since we started to check exact
3277 // block boundaries in invalidate_range()
3278 //if (i_regs->waswritten & (1<<dops[i].rs1))
3280 // (naively) assume nobody will run code from stack
3281 if (dops[i].rs1 == 29)
3284 int j, imm_maxdiff = 32, imm_min = cinfo[i].imm, imm_max = cinfo[i].imm, count = 1;
3285 if (i < slen - 1 && dops[i+1].is_store && dops[i+1].rs1 == dops[i].rs1
3286 && abs(cinfo[i+1].imm - cinfo[i].imm) <= imm_maxdiff)
3288 for (j = i - 1; j >= 0; j--) {
3289 if (!dops[j].is_store || dops[j].rs1 != dops[i].rs1
3290 || abs(cinfo[j].imm - cinfo[j+1].imm) > imm_maxdiff)
3293 if (imm_min > cinfo[j].imm)
3294 imm_min = cinfo[j].imm;
3295 if (imm_max < cinfo[j].imm)
3296 imm_max = cinfo[j].imm;
3298 #if defined(HOST_IMM8)
3299 int ir = get_reg(i_regs->regmap, INVCP);
3301 host_tempreg_acquire();
3302 emit_ldrb_indexedsr12_reg(ir, addr, HOST_TEMPREG);
3304 emit_cmpmem_indexedsr12_imm(invalid_code, addr, 1);
3307 #ifdef INVALIDATE_USE_COND_CALL
3309 emit_cmpimm(HOST_TEMPREG, 1);
3310 emit_callne(invalidate_addr_reg[addr]);
3311 host_tempreg_release();
3315 void *jaddr = emit_cbz(HOST_TEMPREG, 0);
3316 host_tempreg_release();
3317 imm_min -= cinfo[i].imm;
3318 imm_max -= cinfo[i].imm;
3319 add_stub(INVCODE_STUB, jaddr, out, reglist|(1<<HOST_CCREG),
3320 addr, imm_min, imm_max, i);
3323 // determines if code overwrite checking is needed only
3324 // (also true non-existent 0x20000000 mirror that shouldn't matter)
3325 #define is_ram_addr(a) !((a) & 0x5f800000)
3327 static void store_assemble(int i, const struct regstat *i_regs, int ccadj_)
3330 int addr = cinfo[i].addr;
3333 enum stub_type type=0;
3334 int memtarget=0,c=0;
3335 int offset_reg = -1;
3336 int fastio_reg_override = -1;
3337 u_int addr_const = ~0;
3338 u_int reglist=get_host_reglist(i_regs->regmap);
3339 tl=get_reg(i_regs->regmap,dops[i].rs2);
3340 s=get_reg(i_regs->regmap,dops[i].rs1);
3341 offset=cinfo[i].imm;
3343 c=(i_regs->wasconst>>s)&1;
3345 addr_const = constmap[i][s] + offset;
3346 memtarget = ((signed int)addr_const) < (signed int)(0x80000000 + RAM_SIZE);
3351 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3352 reglist |= 1u << addr;
3354 jaddr = emit_fastpath_cmp_jump(i, i_regs, addr,
3355 &offset_reg, &fastio_reg_override, ccadj_);
3357 else if (ram_offset && memtarget) {
3358 offset_reg = get_ro_reg(i_regs, 0);
3361 switch (dops[i].opcode) {
3365 if (fastio_reg_override >= 0)
3366 a = fastio_reg_override;
3367 do_store_byte(a, tl, offset_reg);
3374 if (fastio_reg_override >= 0)
3375 a = fastio_reg_override;
3376 do_store_hword(a, 0, tl, offset_reg, 1);
3383 if (fastio_reg_override >= 0)
3384 a = fastio_reg_override;
3385 do_store_word(a, 0, tl, offset_reg, 1);
3392 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
3393 host_tempreg_release();
3395 // PCSX store handlers don't check invcode again
3396 add_stub_r(type,jaddr,out,i,addr,i_regs,ccadj_,reglist);
3398 if (!c || is_ram_addr(addr_const))
3399 do_store_smc_check(i, i_regs, reglist, addr);
3400 if (c && !memtarget)
3401 inline_writestub(type, i, addr_const, i_regs->regmap, dops[i].rs2, ccadj_, reglist);
3402 // basic current block modification detection..
3403 // not looking back as that should be in mips cache already
3404 // (see Spyro2 title->attract mode)
3405 if (start + i*4 < addr_const && addr_const < start + slen*4) {
3406 SysPrintf("write to %08x hits block %08x, pc=%08x\n", addr_const, start, start+i*4);
3407 assert(i_regs->regmap==regs[i].regmap); // not delay slot
3408 if(i_regs->regmap==regs[i].regmap) {
3409 load_all_consts(regs[i].regmap_entry,regs[i].wasdirty,i);
3410 wb_dirtys(regs[i].regmap_entry,regs[i].wasdirty);
3411 emit_movimm(start+i*4+4,0);
3412 emit_writeword(0,&pcaddr);
3413 emit_addimm(HOST_CCREG,2,HOST_CCREG);
3414 emit_far_call(ndrc_get_addr_ht);
3420 static void storelr_assemble(int i, const struct regstat *i_regs, int ccadj_)
3422 int addr = cinfo[i].addr;
3426 void *case1, *case23, *case3;
3427 void *done0, *done1, *done2;
3428 int memtarget=0,c=0;
3429 int offset_reg = -1;
3430 u_int addr_const = ~0;
3431 u_int reglist = get_host_reglist(i_regs->regmap);
3432 tl=get_reg(i_regs->regmap,dops[i].rs2);
3433 s=get_reg(i_regs->regmap,dops[i].rs1);
3434 offset=cinfo[i].imm;
3436 c = (i_regs->isconst >> s) & 1;
3438 addr_const = constmap[i][s] + offset;
3439 memtarget = ((signed int)addr_const) < (signed int)(0x80000000 + RAM_SIZE);
3444 reglist |= 1u << addr;
3446 emit_cmpimm(addr, RAM_SIZE);
3452 if(!memtarget||!dops[i].rs1) {
3458 offset_reg = get_ro_reg(i_regs, 0);
3460 emit_testimm(addr,2);
3463 emit_testimm(addr,1);
3467 if (dops[i].opcode == 0x2A) { // SWL
3468 // Write msb into least significant byte
3469 if (dops[i].rs2) emit_rorimm(tl, 24, tl);
3470 do_store_byte(addr, tl, offset_reg);
3471 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3473 else if (dops[i].opcode == 0x2E) { // SWR
3474 // Write entire word
3475 do_store_word(addr, 0, tl, offset_reg, 1);
3480 set_jump_target(case1, out);
3481 if (dops[i].opcode == 0x2A) { // SWL
3482 // Write two msb into two least significant bytes
3483 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
3484 do_store_hword(addr, -1, tl, offset_reg, 1);
3485 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
3487 else if (dops[i].opcode == 0x2E) { // SWR
3488 // Write 3 lsb into three most significant bytes
3489 do_store_byte(addr, tl, offset_reg);
3490 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3491 do_store_hword(addr, 1, tl, offset_reg, 1);
3492 if (dops[i].rs2) emit_rorimm(tl, 24, tl);
3497 set_jump_target(case23, out);
3498 emit_testimm(addr,1);
3502 if (dops[i].opcode==0x2A) { // SWL
3503 // Write 3 msb into three least significant bytes
3504 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3505 do_store_hword(addr, -2, tl, offset_reg, 1);
3506 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
3507 do_store_byte(addr, tl, offset_reg);
3508 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3510 else if (dops[i].opcode == 0x2E) { // SWR
3511 // Write two lsb into two most significant bytes
3512 do_store_hword(addr, 0, tl, offset_reg, 1);
3517 set_jump_target(case3, out);
3518 if (dops[i].opcode == 0x2A) { // SWL
3519 do_store_word(addr, -3, tl, offset_reg, 1);
3521 else if (dops[i].opcode == 0x2E) { // SWR
3522 do_store_byte(addr, tl, offset_reg);
3524 set_jump_target(done0, out);
3525 set_jump_target(done1, out);
3526 set_jump_target(done2, out);
3527 if (offset_reg == HOST_TEMPREG)
3528 host_tempreg_release();
3529 if (!c || !memtarget)
3530 add_stub_r(STORELR_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
3531 if (!c || is_ram_addr(addr_const))
3532 do_store_smc_check(i, i_regs, reglist, addr);
3535 static void cop0_assemble(int i, const struct regstat *i_regs, int ccadj_)
3537 if(dops[i].opcode2==0) // MFC0
3539 signed char t=get_reg_w(i_regs->regmap, dops[i].rt1);
3540 u_int copr=(source[i]>>11)&0x1f;
3541 if(t>=0&&dops[i].rt1!=0) {
3542 emit_readword(®_cop0[copr],t);
3545 else if(dops[i].opcode2==4) // MTC0
3547 int s = get_reg(i_regs->regmap, dops[i].rs1);
3548 int cc = get_reg(i_regs->regmap, CCREG);
3549 char copr=(source[i]>>11)&0x1f;
3551 wb_register(dops[i].rs1,i_regs->regmap,i_regs->dirty);
3552 if (copr == 12 || copr == 13) {
3553 emit_readword(&last_count,HOST_TEMPREG);
3554 if (cc != HOST_CCREG)
3555 emit_loadreg(CCREG, HOST_CCREG);
3556 emit_add(HOST_CCREG, HOST_TEMPREG, HOST_CCREG);
3557 emit_addimm(HOST_CCREG, ccadj_ + 2, HOST_CCREG);
3558 emit_writeword(HOST_CCREG, &psxRegs.cycle);
3560 // burn cycles to cause cc_interrupt, which will
3561 // reschedule next_interupt. Relies on CCREG from above.
3562 assem_debug("MTC0 DS %d\n", copr);
3563 emit_writeword(HOST_CCREG,&last_count);
3564 emit_movimm(0,HOST_CCREG);
3565 emit_storereg(CCREG,HOST_CCREG);
3566 emit_loadreg(dops[i].rs1,1);
3567 emit_movimm(copr,0);
3568 emit_far_call(pcsx_mtc0_ds);
3569 emit_loadreg(dops[i].rs1,s);
3572 emit_movimm(start+i*4+4,HOST_TEMPREG);
3573 emit_writeword(HOST_TEMPREG,&pcaddr);
3574 emit_movimm(0,HOST_TEMPREG);
3575 emit_writeword(HOST_TEMPREG,&pending_exception);
3579 emit_movimm(copr, 0);
3580 emit_far_call(pcsx_mtc0);
3581 if (copr == 12 || copr == 13) {
3582 emit_readword(&psxRegs.cycle,HOST_CCREG);
3583 emit_readword(&last_count,HOST_TEMPREG);
3584 emit_sub(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
3585 //emit_writeword(HOST_TEMPREG,&last_count);
3586 assert(!is_delayslot);
3587 emit_readword(&pending_exception,HOST_TEMPREG);
3588 emit_test(HOST_TEMPREG,HOST_TEMPREG);
3591 emit_readword(&pcaddr, 0);
3592 emit_far_call(ndrc_get_addr_ht);
3594 set_jump_target(jaddr, out);
3595 emit_addimm(HOST_CCREG, -ccadj_ - 2, HOST_CCREG);
3596 if (cc != HOST_CCREG)
3597 emit_storereg(CCREG, HOST_CCREG);
3599 emit_loadreg(dops[i].rs1,s);
3603 static void rfe_assemble(int i, const struct regstat *i_regs)
3605 emit_readword(&psxRegs.CP0.n.SR, 0);
3606 emit_andimm(0, 0x3c, 1);
3607 emit_andimm(0, ~0xf, 0);
3608 emit_orrshr_imm(1, 2, 0);
3609 emit_writeword(0, &psxRegs.CP0.n.SR);
3612 static int cop2_is_stalling_op(int i, int *cycles)
3614 if (dops[i].opcode == 0x3a) { // SWC2
3618 if (dops[i].itype == COP2 && (dops[i].opcode2 == 0 || dops[i].opcode2 == 2)) { // MFC2/CFC2
3622 if (dops[i].itype == C2OP) {
3623 *cycles = gte_cycletab[source[i] & 0x3f];
3626 // ... what about MTC2/CTC2/LWC2?
3631 static void log_gte_stall(int stall, u_int cycle)
3633 if ((u_int)stall <= 44)
3634 printf("x stall %2d %u\n", stall, cycle + last_count);
3637 static void emit_log_gte_stall(int i, int stall, u_int reglist)
3641 emit_movimm(stall, 0);
3643 emit_mov(HOST_TEMPREG, 0);
3644 emit_addimm(HOST_CCREG, cinfo[i].ccadj, 1);
3645 emit_far_call(log_gte_stall);
3646 restore_regs(reglist);
3650 static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist)
3652 int j = i, other_gte_op_cycles = -1, stall = -MAXBLOCK, cycles_passed;
3653 int rtmp = reglist_find_free(reglist);
3655 if (HACK_ENABLED(NDHACK_NO_STALLS))
3657 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) {
3658 // happens occasionally... cc evicted? Don't bother then
3659 //printf("no cc %08x\n", start + i*4);
3663 for (j = i - 1; j >= 0; j--) {
3664 //if (dops[j].is_ds) break;
3665 if (cop2_is_stalling_op(j, &other_gte_op_cycles) || dops[j].bt)
3667 if (j > 0 && cinfo[j - 1].ccadj > cinfo[j].ccadj)
3672 cycles_passed = cinfo[i].ccadj - cinfo[j].ccadj;
3673 if (other_gte_op_cycles >= 0)
3674 stall = other_gte_op_cycles - cycles_passed;
3675 else if (cycles_passed >= 44)
3676 stall = 0; // can't stall
3677 if (stall == -MAXBLOCK && rtmp >= 0) {
3678 // unknown stall, do the expensive runtime check
3679 assem_debug("; cop2_do_stall_check\n");
3682 emit_movimm(gte_cycletab[op], 0);
3683 emit_addimm(HOST_CCREG, cinfo[i].ccadj, 1);
3684 emit_far_call(call_gteStall);
3685 restore_regs(reglist);
3687 host_tempreg_acquire();
3688 emit_readword(&psxRegs.gteBusyCycle, rtmp);
3689 emit_addimm(rtmp, -cinfo[i].ccadj, rtmp);
3690 emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG);
3691 emit_cmpimm(HOST_TEMPREG, 44);
3692 emit_cmovb_reg(rtmp, HOST_CCREG);
3693 //emit_log_gte_stall(i, 0, reglist);
3694 host_tempreg_release();
3697 else if (stall > 0) {
3698 //emit_log_gte_stall(i, stall, reglist);
3699 emit_addimm(HOST_CCREG, stall, HOST_CCREG);
3702 // save gteBusyCycle, if needed
3703 if (gte_cycletab[op] == 0)
3705 other_gte_op_cycles = -1;
3706 for (j = i + 1; j < slen; j++) {
3707 if (cop2_is_stalling_op(j, &other_gte_op_cycles))
3709 if (dops[j].is_jump) {
3711 if (j + 1 < slen && cop2_is_stalling_op(j + 1, &other_gte_op_cycles))
3716 if (other_gte_op_cycles >= 0)
3717 // will handle stall when assembling that op
3719 cycles_passed = cinfo[min(j, slen -1)].ccadj - cinfo[i].ccadj;
3720 if (cycles_passed >= 44)
3722 assem_debug("; save gteBusyCycle\n");
3723 host_tempreg_acquire();
3725 emit_readword(&last_count, HOST_TEMPREG);
3726 emit_add(HOST_TEMPREG, HOST_CCREG, HOST_TEMPREG);
3727 emit_addimm(HOST_TEMPREG, cinfo[i].ccadj, HOST_TEMPREG);
3728 emit_addimm(HOST_TEMPREG, gte_cycletab[op]), HOST_TEMPREG);
3729 emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle);
3731 emit_addimm(HOST_CCREG, cinfo[i].ccadj + gte_cycletab[op], HOST_TEMPREG);
3732 emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle);
3734 host_tempreg_release();
3737 static int is_mflohi(int i)
3739 return (dops[i].itype == MOV && (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG));
3742 static int check_multdiv(int i, int *cycles)
3744 if (dops[i].itype != MULTDIV)
3746 if (dops[i].opcode2 == 0x18 || dops[i].opcode2 == 0x19) // MULT(U)
3747 *cycles = 11; // approx from 7 11 14
3753 static void multdiv_prepare_stall(int i, const struct regstat *i_regs, int ccadj_)
3755 int j, found = 0, c = 0;
3756 if (HACK_ENABLED(NDHACK_NO_STALLS))
3758 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) {
3759 // happens occasionally... cc evicted? Don't bother then
3762 for (j = i + 1; j < slen; j++) {
3765 if ((found = is_mflohi(j)))
3767 if (dops[j].is_jump) {
3769 if (j + 1 < slen && (found = is_mflohi(j + 1)))
3775 // handle all in multdiv_do_stall()
3777 check_multdiv(i, &c);
3779 assem_debug("; muldiv prepare stall %d\n", c);
3780 host_tempreg_acquire();
3781 emit_addimm(HOST_CCREG, ccadj_ + c, HOST_TEMPREG);
3782 emit_writeword(HOST_TEMPREG, &psxRegs.muldivBusyCycle);
3783 host_tempreg_release();
3786 static void multdiv_do_stall(int i, const struct regstat *i_regs)
3788 int j, known_cycles = 0;
3789 u_int reglist = get_host_reglist(i_regs->regmap);
3790 int rtmp = get_reg_temp(i_regs->regmap);
3792 rtmp = reglist_find_free(reglist);
3793 if (HACK_ENABLED(NDHACK_NO_STALLS))
3795 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG || rtmp < 0) {
3796 // happens occasionally... cc evicted? Don't bother then
3797 //printf("no cc/rtmp %08x\n", start + i*4);
3801 for (j = i - 1; j >= 0; j--) {
3802 if (dops[j].is_ds) break;
3803 if (check_multdiv(j, &known_cycles))
3806 // already handled by this op
3808 if (dops[j].bt || (j > 0 && cinfo[j - 1].ccadj > cinfo[j].ccadj))
3813 if (known_cycles > 0) {
3814 known_cycles -= cinfo[i].ccadj - cinfo[j].ccadj;
3815 assem_debug("; muldiv stall resolved %d\n", known_cycles);
3816 if (known_cycles > 0)
3817 emit_addimm(HOST_CCREG, known_cycles, HOST_CCREG);
3820 assem_debug("; muldiv stall unresolved\n");
3821 host_tempreg_acquire();
3822 emit_readword(&psxRegs.muldivBusyCycle, rtmp);
3823 emit_addimm(rtmp, -cinfo[i].ccadj, rtmp);
3824 emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG);
3825 emit_cmpimm(HOST_TEMPREG, 37);
3826 emit_cmovb_reg(rtmp, HOST_CCREG);
3827 //emit_log_gte_stall(i, 0, reglist);
3828 host_tempreg_release();
3831 static void cop2_get_dreg(u_int copr,signed char tl,signed char temp)
3841 emit_readword(®_cop2d[copr],tl);
3842 emit_signextend16(tl,tl);
3843 emit_writeword(tl,®_cop2d[copr]); // hmh
3850 emit_readword(®_cop2d[copr],tl);
3851 emit_andimm(tl,0xffff,tl);
3852 emit_writeword(tl,®_cop2d[copr]);
3855 emit_readword(®_cop2d[14],tl); // SXY2
3856 emit_writeword(tl,®_cop2d[copr]);
3860 c2op_mfc2_29_assemble(tl,temp);
3863 emit_readword(®_cop2d[copr],tl);
3868 static void cop2_put_dreg(u_int copr,signed char sl,signed char temp)
3872 emit_readword(®_cop2d[13],temp); // SXY1
3873 emit_writeword(sl,®_cop2d[copr]);
3874 emit_writeword(temp,®_cop2d[12]); // SXY0
3875 emit_readword(®_cop2d[14],temp); // SXY2
3876 emit_writeword(sl,®_cop2d[14]);
3877 emit_writeword(temp,®_cop2d[13]); // SXY1
3880 emit_andimm(sl,0x001f,temp);
3881 emit_shlimm(temp,7,temp);
3882 emit_writeword(temp,®_cop2d[9]);
3883 emit_andimm(sl,0x03e0,temp);
3884 emit_shlimm(temp,2,temp);
3885 emit_writeword(temp,®_cop2d[10]);
3886 emit_andimm(sl,0x7c00,temp);
3887 emit_shrimm(temp,3,temp);
3888 emit_writeword(temp,®_cop2d[11]);
3889 emit_writeword(sl,®_cop2d[28]);
3892 emit_xorsar_imm(sl,sl,31,temp);
3893 #if defined(HAVE_ARMV5) || defined(__aarch64__)
3894 emit_clz(temp,temp);
3896 emit_movs(temp,HOST_TEMPREG);
3897 emit_movimm(0,temp);
3898 emit_jeq((int)out+4*4);
3899 emit_addpl_imm(temp,1,temp);
3900 emit_lslpls_imm(HOST_TEMPREG,1,HOST_TEMPREG);
3901 emit_jns((int)out-2*4);
3903 emit_writeword(sl,®_cop2d[30]);
3904 emit_writeword(temp,®_cop2d[31]);
3909 emit_writeword(sl,®_cop2d[copr]);
3914 static void c2ls_assemble(int i, const struct regstat *i_regs, int ccadj_)
3919 int memtarget=0,c=0;
3921 enum stub_type type;
3922 int offset_reg = -1;
3923 int fastio_reg_override = -1;
3924 u_int addr_const = ~0;
3925 u_int reglist=get_host_reglist(i_regs->regmap);
3926 u_int copr=(source[i]>>16)&0x1f;
3927 s=get_reg(i_regs->regmap,dops[i].rs1);
3928 tl=get_reg(i_regs->regmap,FTEMP);
3929 offset=cinfo[i].imm;
3932 if(i_regs->regmap[HOST_CCREG]==CCREG)
3933 reglist&=~(1<<HOST_CCREG);
3938 if (dops[i].opcode==0x3a) { // SWC2
3942 c = (i_regs->isconst >> s) & 1;
3944 addr_const = constmap[i][s] + offset;
3945 memtarget = ((signed int)addr_const) < (signed int)(0x80000000 + RAM_SIZE);
3949 cop2_do_stall_check(0, i, i_regs, reglist);
3951 if (dops[i].opcode==0x3a) { // SWC2
3952 cop2_get_dreg(copr,tl,-1);
3960 emit_jmp(0); // inline_readstub/inline_writestub?
3964 jaddr2 = emit_fastpath_cmp_jump(i, i_regs, ar,
3965 &offset_reg, &fastio_reg_override, ccadj_);
3967 else if (ram_offset && memtarget) {
3968 offset_reg = get_ro_reg(i_regs, 0);
3970 switch (dops[i].opcode) {
3971 case 0x32: { // LWC2
3973 if (fastio_reg_override >= 0)
3974 a = fastio_reg_override;
3975 do_load_word(a, tl, offset_reg);
3978 case 0x3a: { // SWC2
3979 #ifdef DESTRUCTIVE_SHIFT
3980 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3983 if (fastio_reg_override >= 0)
3984 a = fastio_reg_override;
3985 do_store_word(a, 0, tl, offset_reg, 1);
3992 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
3993 host_tempreg_release();
3995 add_stub_r(type,jaddr2,out,i,ar,i_regs,ccadj_,reglist);
3996 if (dops[i].opcode == 0x3a && (!c || is_ram_addr(addr_const))) // SWC2
3997 do_store_smc_check(i, i_regs, reglist, ar);
3998 if (dops[i].opcode == 0x32) { // LWC2
3999 host_tempreg_acquire();
4000 cop2_put_dreg(copr,tl,HOST_TEMPREG);
4001 host_tempreg_release();
4005 static void cop2_assemble(int i, const struct regstat *i_regs)
4007 u_int copr = (source[i]>>11) & 0x1f;
4008 signed char temp = get_reg_temp(i_regs->regmap);
4010 if (!HACK_ENABLED(NDHACK_NO_STALLS)) {
4011 u_int reglist = reglist_exclude(get_host_reglist(i_regs->regmap), temp, -1);
4012 if (dops[i].opcode2 == 0 || dops[i].opcode2 == 2) { // MFC2/CFC2
4013 signed char tl = get_reg(i_regs->regmap, dops[i].rt1);
4014 reglist = reglist_exclude(reglist, tl, -1);
4016 cop2_do_stall_check(0, i, i_regs, reglist);
4018 if (dops[i].opcode2==0) { // MFC2
4019 signed char tl=get_reg_w(i_regs->regmap, dops[i].rt1);
4020 if(tl>=0&&dops[i].rt1!=0)
4021 cop2_get_dreg(copr,tl,temp);
4023 else if (dops[i].opcode2==4) { // MTC2
4024 signed char sl=get_reg(i_regs->regmap,dops[i].rs1);
4025 cop2_put_dreg(copr,sl,temp);
4027 else if (dops[i].opcode2==2) // CFC2
4029 signed char tl=get_reg_w(i_regs->regmap, dops[i].rt1);
4030 if(tl>=0&&dops[i].rt1!=0)
4031 emit_readword(®_cop2c[copr],tl);
4033 else if (dops[i].opcode2==6) // CTC2
4035 signed char sl=get_reg(i_regs->regmap,dops[i].rs1);
4044 emit_signextend16(sl,temp);
4047 c2op_ctc2_31_assemble(sl,temp);
4053 emit_writeword(temp,®_cop2c[copr]);
4058 static void do_unalignedwritestub(int n)
4060 assem_debug("do_unalignedwritestub %x\n",start+stubs[n].a*4);
4062 set_jump_target(stubs[n].addr, out);
4065 struct regstat *i_regs=(struct regstat *)stubs[n].c;
4066 int addr=stubs[n].b;
4067 u_int reglist=stubs[n].e;
4068 signed char *i_regmap=i_regs->regmap;
4069 int temp2=get_reg(i_regmap,FTEMP);
4071 rt=get_reg(i_regmap,dops[i].rs2);
4074 assert(dops[i].opcode==0x2a||dops[i].opcode==0x2e); // SWL/SWR only implemented
4076 reglist&=~(1<<temp2);
4078 // don't bother with it and call write handler
4081 int cc=get_reg(i_regmap,CCREG);
4083 emit_loadreg(CCREG,2);
4084 emit_addimm(cc<0?2:cc,(int)stubs[n].d+1,2);
4085 emit_movimm(start + i*4,3);
4086 emit_writeword(3,&psxRegs.pc);
4087 emit_far_call((dops[i].opcode==0x2a?jump_handle_swl:jump_handle_swr));
4088 emit_addimm(0,-((int)stubs[n].d+1),cc<0?2:cc);
4090 emit_storereg(CCREG,2);
4091 restore_regs(reglist);
4092 emit_jmp(stubs[n].retaddr); // return address
4095 static void do_overflowstub(int n)
4097 assem_debug("do_overflowstub %x\n", start + (u_int)stubs[n].a * 4);
4100 struct regstat *i_regs = (struct regstat *)stubs[n].c;
4101 int ccadj = stubs[n].d;
4102 set_jump_target(stubs[n].addr, out);
4103 wb_dirtys(regs[i].regmap, regs[i].dirty);
4104 exception_assemble(i, i_regs, ccadj);
4107 static void do_alignmentstub(int n)
4109 assem_debug("do_alignmentstub %x\n", start + (u_int)stubs[n].a * 4);
4112 struct regstat *i_regs = (struct regstat *)stubs[n].c;
4113 int ccadj = stubs[n].d;
4114 int is_store = dops[i].itype == STORE || dops[i].opcode == 0x3A; // SWC2
4115 int cause = (dops[i].opcode & 3) << 28;
4116 cause |= is_store ? (R3000E_AdES << 2) : (R3000E_AdEL << 2);
4117 set_jump_target(stubs[n].addr, out);
4118 wb_dirtys(regs[i].regmap, regs[i].dirty);
4119 if (stubs[n].b != 1)
4120 emit_mov(stubs[n].b, 1); // faulting address
4121 emit_movimm(cause, 0);
4122 exception_assemble(i, i_regs, ccadj);
4125 #ifndef multdiv_assemble
4126 void multdiv_assemble(int i,struct regstat *i_regs)
4128 printf("Need multdiv_assemble for this architecture.\n");
4133 static void mov_assemble(int i, const struct regstat *i_regs)
4135 //if(dops[i].opcode2==0x10||dops[i].opcode2==0x12) { // MFHI/MFLO
4136 //if(dops[i].opcode2==0x11||dops[i].opcode2==0x13) { // MTHI/MTLO
4139 tl=get_reg_w(i_regs->regmap, dops[i].rt1);
4142 sl=get_reg(i_regs->regmap,dops[i].rs1);
4143 if(sl>=0) emit_mov(sl,tl);
4144 else emit_loadreg(dops[i].rs1,tl);
4147 if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) // MFHI/MFLO
4148 multdiv_do_stall(i, i_regs);
4151 // call interpreter, exception handler, things that change pc/regs/cycles ...
4152 static void call_c_cpu_handler(int i, const struct regstat *i_regs, int ccadj_, u_int pc, void *func)
4154 signed char ccreg=get_reg(i_regs->regmap,CCREG);
4155 assert(ccreg==HOST_CCREG);
4156 assert(!is_delayslot);
4159 emit_movimm(pc,3); // Get PC
4160 emit_readword(&last_count,2);
4161 emit_writeword(3,&psxRegs.pc);
4162 emit_addimm(HOST_CCREG,ccadj_,HOST_CCREG);
4163 emit_add(2,HOST_CCREG,2);
4164 emit_writeword(2,&psxRegs.cycle);
4165 emit_addimm_ptr(FP,(u_char *)&psxRegs - (u_char *)&dynarec_local,0);
4166 emit_far_call(func);
4167 emit_far_jump(jump_to_new_pc);
4170 static void exception_assemble(int i, const struct regstat *i_regs, int ccadj_)
4172 // 'break' tends to be littered around to catch things like
4173 // division by 0 and is almost never executed, so don't emit much code here
4175 if (dops[i].itype == ALU || dops[i].itype == IMM16)
4176 func = is_delayslot ? jump_overflow_ds : jump_overflow;
4177 else if (dops[i].itype == LOAD || dops[i].itype == STORE)
4178 func = is_delayslot ? jump_addrerror_ds : jump_addrerror;
4179 else if (dops[i].opcode2 == 0x0C)
4180 func = is_delayslot ? jump_syscall_ds : jump_syscall;
4182 func = is_delayslot ? jump_break_ds : jump_break;
4183 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) // evicted
4184 emit_loadreg(CCREG, HOST_CCREG);
4185 emit_movimm(start + i*4, 2); // pc
4186 emit_addimm(HOST_CCREG, ccadj_ + CLOCK_ADJUST(1), HOST_CCREG);
4187 emit_far_jump(func);
4190 static void hlecall_bad()
4195 static void hlecall_assemble(int i, const struct regstat *i_regs, int ccadj_)
4197 void *hlefunc = hlecall_bad;
4198 uint32_t hleCode = source[i] & 0x03ffffff;
4199 if (hleCode < ARRAY_SIZE(psxHLEt))
4200 hlefunc = psxHLEt[hleCode];
4202 call_c_cpu_handler(i, i_regs, ccadj_, start + i*4+4, hlefunc);
4205 static void intcall_assemble(int i, const struct regstat *i_regs, int ccadj_)
4207 call_c_cpu_handler(i, i_regs, ccadj_, start + i*4, execI);
4210 static void speculate_mov(int rs,int rt)
4213 smrv_strong_next|=1<<rt;
4218 static void speculate_mov_weak(int rs,int rt)
4221 smrv_weak_next|=1<<rt;
4226 static void speculate_register_values(int i)
4229 memcpy(smrv,psxRegs.GPR.r,sizeof(smrv));
4230 // gp,sp are likely to stay the same throughout the block
4231 smrv_strong_next=(1<<28)|(1<<29)|(1<<30);
4232 smrv_weak_next=~smrv_strong_next;
4233 //printf(" llr %08x\n", smrv[4]);
4235 smrv_strong=smrv_strong_next;
4236 smrv_weak=smrv_weak_next;
4237 switch(dops[i].itype) {
4239 if ((smrv_strong>>dops[i].rs1)&1) speculate_mov(dops[i].rs1,dops[i].rt1);
4240 else if((smrv_strong>>dops[i].rs2)&1) speculate_mov(dops[i].rs2,dops[i].rt1);
4241 else if((smrv_weak>>dops[i].rs1)&1) speculate_mov_weak(dops[i].rs1,dops[i].rt1);
4242 else if((smrv_weak>>dops[i].rs2)&1) speculate_mov_weak(dops[i].rs2,dops[i].rt1);
4244 smrv_strong_next&=~(1<<dops[i].rt1);
4245 smrv_weak_next&=~(1<<dops[i].rt1);
4249 smrv_strong_next&=~(1<<dops[i].rt1);
4250 smrv_weak_next&=~(1<<dops[i].rt1);
4253 if(dops[i].rt1&&is_const(®s[i],dops[i].rt1)) {
4254 int hr = get_reg_w(regs[i].regmap, dops[i].rt1);
4257 if(get_final_value(hr,i,&value))
4258 smrv[dops[i].rt1]=value;
4259 else smrv[dops[i].rt1]=constmap[i][hr];
4260 smrv_strong_next|=1<<dops[i].rt1;
4264 if ((smrv_strong>>dops[i].rs1)&1) speculate_mov(dops[i].rs1,dops[i].rt1);
4265 else if((smrv_weak>>dops[i].rs1)&1) speculate_mov_weak(dops[i].rs1,dops[i].rt1);
4269 if(start<0x2000&&(dops[i].rt1==26||(smrv[dops[i].rt1]>>24)==0xa0)) {
4270 // special case for BIOS
4271 smrv[dops[i].rt1]=0xa0000000;
4272 smrv_strong_next|=1<<dops[i].rt1;
4279 smrv_strong_next&=~(1<<dops[i].rt1);
4280 smrv_weak_next&=~(1<<dops[i].rt1);
4284 if(dops[i].opcode2==0||dops[i].opcode2==2) { // MFC/CFC
4285 smrv_strong_next&=~(1<<dops[i].rt1);
4286 smrv_weak_next&=~(1<<dops[i].rt1);
4290 if (dops[i].opcode==0x32) { // LWC2
4291 smrv_strong_next&=~(1<<dops[i].rt1);
4292 smrv_weak_next&=~(1<<dops[i].rt1);
4298 printf("x %08x %08x %d %d c %08x %08x\n",smrv[r],start+i*4,
4299 ((smrv_strong>>r)&1),(smrv_weak>>r)&1,regs[i].isconst,regs[i].wasconst);
4303 static void ujump_assemble(int i, const struct regstat *i_regs);
4304 static void rjump_assemble(int i, const struct regstat *i_regs);
4305 static void cjump_assemble(int i, const struct regstat *i_regs);
4306 static void sjump_assemble(int i, const struct regstat *i_regs);
4308 static int assemble(int i, const struct regstat *i_regs, int ccadj_)
4311 switch (dops[i].itype) {
4313 alu_assemble(i, i_regs, ccadj_);
4316 imm16_assemble(i, i_regs, ccadj_);
4319 shift_assemble(i, i_regs);
4322 shiftimm_assemble(i, i_regs);
4325 load_assemble(i, i_regs, ccadj_);
4328 loadlr_assemble(i, i_regs, ccadj_);
4331 store_assemble(i, i_regs, ccadj_);
4334 storelr_assemble(i, i_regs, ccadj_);
4337 cop0_assemble(i, i_regs, ccadj_);
4340 rfe_assemble(i, i_regs);
4343 cop2_assemble(i, i_regs);
4346 c2ls_assemble(i, i_regs, ccadj_);
4349 c2op_assemble(i, i_regs);
4352 multdiv_assemble(i, i_regs);
4353 multdiv_prepare_stall(i, i_regs, ccadj_);
4356 mov_assemble(i, i_regs);
4359 exception_assemble(i, i_regs, ccadj_);
4362 hlecall_assemble(i, i_regs, ccadj_);
4365 intcall_assemble(i, i_regs, ccadj_);
4368 ujump_assemble(i, i_regs);
4372 rjump_assemble(i, i_regs);
4376 cjump_assemble(i, i_regs);
4380 sjump_assemble(i, i_regs);
4385 // not handled, just skip
4393 static void ds_assemble(int i, const struct regstat *i_regs)
4395 speculate_register_values(i);
4397 switch (dops[i].itype) {
4405 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
4408 assemble(i, i_regs, cinfo[i].ccadj);
4413 // Is the branch target a valid internal jump?
4414 static int internal_branch(int addr)
4416 if(addr&1) return 0; // Indirect (register) jump
4417 if(addr>=start && addr<start+slen*4-4)
4424 static void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t u)
4427 for(hr=0;hr<HOST_REGS;hr++) {
4428 if(hr!=EXCLUDE_REG) {
4429 if(pre[hr]!=entry[hr]) {
4432 if(get_reg(entry,pre[hr])<0) {
4434 if(!((u>>pre[hr])&1))
4435 emit_storereg(pre[hr],hr);
4442 // Move from one register to another (no writeback)
4443 for(hr=0;hr<HOST_REGS;hr++) {
4444 if(hr!=EXCLUDE_REG) {
4445 if(pre[hr]!=entry[hr]) {
4446 if(pre[hr]>=0&&pre[hr]<TEMPREG) {
4448 if((nr=get_reg(entry,pre[hr]))>=0) {
4457 // Load the specified registers
4458 // This only loads the registers given as arguments because
4459 // we don't want to load things that will be overwritten
4460 static inline void load_reg(signed char entry[], signed char regmap[], int rs)
4462 int hr = get_reg(regmap, rs);
4463 if (hr >= 0 && entry[hr] != regmap[hr])
4464 emit_loadreg(regmap[hr], hr);
4467 static void load_regs(signed char entry[], signed char regmap[], int rs1, int rs2)
4469 load_reg(entry, regmap, rs1);
4471 load_reg(entry, regmap, rs2);
4474 // Load registers prior to the start of a loop
4475 // so that they are not loaded within the loop
4476 static void loop_preload(signed char pre[],signed char entry[])
4479 for (hr = 0; hr < HOST_REGS; hr++) {
4481 if (r >= 0 && pre[hr] != r && get_reg(pre, r) < 0) {
4482 assem_debug("loop preload:\n");
4484 emit_loadreg(r, hr);
4489 // Generate address for load/store instruction
4490 // goes to AGEN (or temp) for writes, FTEMP for LOADLR and cop1/2 loads
4491 // AGEN is assigned by pass5b_preallocate2
4492 static void address_generation(int i, const struct regstat *i_regs, signed char entry[])
4494 if (dops[i].is_load || dops[i].is_store) {
4496 int agr = AGEN1 + (i&1);
4497 if(dops[i].itype==LOAD) {
4498 if (!dops[i].may_except)
4499 ra = get_reg_w(i_regs->regmap, dops[i].rt1); // reuse dest for agen
4501 ra = get_reg_temp(i_regs->regmap);
4503 if(dops[i].itype==LOADLR) {
4504 ra=get_reg(i_regs->regmap,FTEMP);
4506 if(dops[i].itype==STORE||dops[i].itype==STORELR) {
4507 ra=get_reg(i_regs->regmap,agr);
4508 if(ra<0) ra=get_reg_temp(i_regs->regmap);
4510 if(dops[i].itype==C2LS) {
4511 if (dops[i].opcode == 0x32) // LWC2
4512 ra=get_reg(i_regs->regmap,FTEMP);
4514 ra=get_reg(i_regs->regmap,agr);
4515 if(ra<0) ra=get_reg_temp(i_regs->regmap);
4518 int rs = get_reg(i_regs->regmap, dops[i].rs1);
4521 int offset = cinfo[i].imm;
4522 int add_offset = offset != 0;
4523 int c = rs >= 0 && ((i_regs->wasconst >> rs) & 1);
4524 if(dops[i].rs1==0) {
4525 // Using r0 as a base address
4527 if(!entry||entry[ra]!=agr) {
4528 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
4529 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4531 emit_movimm(offset,ra);
4533 } // else did it in the previous cycle
4539 if (!entry || entry[ra] != dops[i].rs1)
4540 emit_loadreg(dops[i].rs1, ra);
4542 //if(!entry||entry[ra]!=dops[i].rs1)
4543 // printf("poor load scheduling!\n");
4546 if(dops[i].rs1!=dops[i].rt1||dops[i].itype!=LOAD) {
4548 if(!entry||entry[ra]!=agr) {
4549 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
4550 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4552 emit_movimm(constmap[i][rs]+offset,ra);
4553 regs[i].loadedconst|=1<<ra;
4555 } // else did it in the previous cycle
4558 else // else load_consts already did it
4567 emit_addimm(rs,offset,ra);
4569 emit_addimm(ra,offset,ra);
4574 assert(cinfo[i].addr >= 0);
4576 // Preload constants for next instruction
4577 if (dops[i+1].is_load || dops[i+1].is_store) {
4580 agr=AGEN1+((i+1)&1);
4581 ra=get_reg(i_regs->regmap,agr);
4583 int rs=get_reg(regs[i+1].regmap,dops[i+1].rs1);
4584 int offset=cinfo[i+1].imm;
4585 int c=(regs[i+1].wasconst>>rs)&1;
4586 if(c&&(dops[i+1].rs1!=dops[i+1].rt1||dops[i+1].itype!=LOAD)) {
4587 if (dops[i+1].opcode==0x22||dops[i+1].opcode==0x26) {
4588 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4589 }else if (dops[i+1].opcode==0x1a||dops[i+1].opcode==0x1b) {
4590 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4592 emit_movimm(constmap[i+1][rs]+offset,ra);
4593 regs[i+1].loadedconst|=1<<ra;
4596 else if(dops[i+1].rs1==0) {
4597 // Using r0 as a base address
4598 if (dops[i+1].opcode==0x22||dops[i+1].opcode==0x26) {
4599 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4600 }else if (dops[i+1].opcode==0x1a||dops[i+1].opcode==0x1b) {
4601 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4603 emit_movimm(offset,ra);
4610 static int get_final_value(int hr, int i, u_int *value)
4612 int reg=regs[i].regmap[hr];
4614 if(regs[i+1].regmap[hr]!=reg) break;
4615 if(!((regs[i+1].isconst>>hr)&1)) break;
4616 if(dops[i+1].bt) break;
4620 if (dops[i].is_jump) {
4621 *value=constmap[i][hr];
4625 if (dops[i+1].is_jump) {
4626 // Load in delay slot, out-of-order execution
4627 if(dops[i+2].itype==LOAD&&dops[i+2].rs1==reg&&dops[i+2].rt1==reg&&((regs[i+1].wasconst>>hr)&1))
4629 // Precompute load address
4630 *value=constmap[i][hr]+cinfo[i+2].imm;
4634 if(dops[i+1].itype==LOAD&&dops[i+1].rs1==reg&&dops[i+1].rt1==reg)
4636 // Precompute load address
4637 *value=constmap[i][hr]+cinfo[i+1].imm;
4638 //printf("c=%x imm=%lx\n",(long)constmap[i][hr],cinfo[i+1].imm);
4643 *value=constmap[i][hr];
4644 //printf("c=%lx\n",(long)constmap[i][hr]);
4645 if(i==slen-1) return 1;
4647 return !((unneeded_reg[i+1]>>reg)&1);
4650 // Load registers with known constants
4651 static void load_consts(signed char pre[],signed char regmap[],int i)
4654 // propagate loaded constant flags
4655 if(i==0||dops[i].bt)
4656 regs[i].loadedconst=0;
4658 for (hr = 0; hr < HOST_REGS; hr++) {
4659 if (hr == EXCLUDE_REG || regmap[hr] < 0 || pre[hr] != regmap[hr])
4661 if ((((regs[i-1].isconst & regs[i-1].loadedconst) >> hr) & 1)
4662 && regmap[hr] == regs[i-1].regmap[hr])
4664 regs[i].loadedconst |= 1u << hr;
4669 for(hr=0;hr<HOST_REGS;hr++) {
4670 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4671 //if(entry[hr]!=regmap[hr]) {
4672 if(!((regs[i].loadedconst>>hr)&1)) {
4673 assert(regmap[hr]<64);
4674 if(((regs[i].isconst>>hr)&1)&®map[hr]>0) {
4675 u_int value, similar=0;
4676 if(get_final_value(hr,i,&value)) {
4677 // see if some other register has similar value
4678 for(hr2=0;hr2<HOST_REGS;hr2++) {
4679 if(hr2!=EXCLUDE_REG&&((regs[i].loadedconst>>hr2)&1)) {
4680 if(is_similar_value(value,constmap[i][hr2])) {
4688 if(get_final_value(hr2,i,&value2)) // is this needed?
4689 emit_movimm_from(value2,hr2,value,hr);
4691 emit_movimm(value,hr);
4697 emit_movimm(value,hr);
4700 regs[i].loadedconst|=1<<hr;
4707 static void load_all_consts(const signed char regmap[], u_int dirty, int i)
4711 for(hr=0;hr<HOST_REGS;hr++) {
4712 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) {
4713 assert(regmap[hr] < 64);
4714 if(((regs[i].isconst>>hr)&1)&®map[hr]>0) {
4715 int value=constmap[i][hr];
4720 emit_movimm(value,hr);
4727 // Write out all dirty registers (except cycle count)
4729 static void wb_dirtys(const signed char i_regmap[], u_int i_dirty)
4732 for(hr=0;hr<HOST_REGS;hr++) {
4733 if(hr!=EXCLUDE_REG) {
4734 if(i_regmap[hr]>0) {
4735 if(i_regmap[hr]!=CCREG) {
4736 if((i_dirty>>hr)&1) {
4737 assert(i_regmap[hr]<64);
4738 emit_storereg(i_regmap[hr],hr);
4747 // Write out dirty registers that we need to reload (pair with load_needed_regs)
4748 // This writes the registers not written by store_regs_bt
4749 static void wb_needed_dirtys(const signed char i_regmap[], u_int i_dirty, int addr)
4752 int t=(addr-start)>>2;
4753 for(hr=0;hr<HOST_REGS;hr++) {
4754 if(hr!=EXCLUDE_REG) {
4755 if(i_regmap[hr]>0) {
4756 if(i_regmap[hr]!=CCREG) {
4757 if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1)) {
4758 if((i_dirty>>hr)&1) {
4759 assert(i_regmap[hr]<64);
4760 emit_storereg(i_regmap[hr],hr);
4769 // Load all registers (except cycle count)
4770 #ifndef load_all_regs
4771 static void load_all_regs(const signed char i_regmap[])
4774 for(hr=0;hr<HOST_REGS;hr++) {
4775 if(hr!=EXCLUDE_REG) {
4776 if(i_regmap[hr]==0) {
4780 if(i_regmap[hr]>0 && i_regmap[hr]<TEMPREG && i_regmap[hr]!=CCREG)
4782 emit_loadreg(i_regmap[hr],hr);
4789 // Load all current registers also needed by next instruction
4790 static void load_needed_regs(const signed char i_regmap[], const signed char next_regmap[])
4792 signed char regmap_sel[HOST_REGS];
4794 for (hr = 0; hr < HOST_REGS; hr++) {
4795 regmap_sel[hr] = -1;
4796 if (hr != EXCLUDE_REG)
4797 if (next_regmap[hr] == i_regmap[hr] || get_reg(next_regmap, i_regmap[hr]) >= 0)
4798 regmap_sel[hr] = i_regmap[hr];
4800 load_all_regs(regmap_sel);
4803 // Load all regs, storing cycle count if necessary
4804 static void load_regs_entry(int t)
4806 if(dops[t].is_ds) emit_addimm(HOST_CCREG,CLOCK_ADJUST(1),HOST_CCREG);
4807 else if(cinfo[t].ccadj) emit_addimm(HOST_CCREG,-cinfo[t].ccadj,HOST_CCREG);
4808 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4809 emit_storereg(CCREG,HOST_CCREG);
4811 load_all_regs(regs[t].regmap_entry);
4814 // Store dirty registers prior to branch
4815 static void store_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
4817 if(internal_branch(addr))
4819 int t=(addr-start)>>2;
4821 for(hr=0;hr<HOST_REGS;hr++) {
4822 if(hr!=EXCLUDE_REG) {
4823 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4824 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1)) {
4825 if((i_dirty>>hr)&1) {
4826 assert(i_regmap[hr]<64);
4827 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4828 emit_storereg(i_regmap[hr],hr);
4837 // Branch out of this block, write out all dirty regs
4838 wb_dirtys(i_regmap,i_dirty);
4842 // Load all needed registers for branch target
4843 static void load_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
4845 //if(addr>=start && addr<(start+slen*4))
4846 if(internal_branch(addr))
4848 int t=(addr-start)>>2;
4850 // Store the cycle count before loading something else
4851 if(i_regmap[HOST_CCREG]!=CCREG) {
4852 assert(i_regmap[HOST_CCREG]==-1);
4854 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4855 emit_storereg(CCREG,HOST_CCREG);
4858 for(hr=0;hr<HOST_REGS;hr++) {
4859 if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) {
4860 if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4861 if(regs[t].regmap_entry[hr]==0) {
4864 else if(regs[t].regmap_entry[hr]!=CCREG)
4866 emit_loadreg(regs[t].regmap_entry[hr],hr);
4874 static int match_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
4876 if(addr>=start && addr<start+slen*4-4)
4878 int t=(addr-start)>>2;
4880 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4881 for(hr=0;hr<HOST_REGS;hr++)
4885 if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4887 if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
4894 if(i_regmap[hr]<TEMPREG)
4896 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4899 else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
4905 else // Same register but is it 32-bit or dirty?
4908 if(!((regs[t].dirty>>hr)&1))
4912 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4914 //printf("%x: dirty no match\n",addr);
4922 // Delay slots are not valid branch targets
4923 //if(t>0&&(dops[t-1].is_jump) return 0;
4924 // Delay slots require additional processing, so do not match
4925 if(dops[t].is_ds) return 0;
4930 for(hr=0;hr<HOST_REGS;hr++)
4936 if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4951 static void drc_dbg_emit_do_cmp(int i, int ccadj_)
4953 extern void do_insn_cmp();
4955 u_int hr, reglist = get_host_reglist(regs[i].regmap);
4956 reglist |= get_host_reglist(regs[i].regmap_entry);
4957 reglist &= DRC_DBG_REGMASK;
4959 assem_debug("//do_insn_cmp %08x\n", start+i*4);
4961 // write out changed consts to match the interpreter
4962 if (i > 0 && !dops[i].bt) {
4963 for (hr = 0; hr < HOST_REGS; hr++) {
4964 int reg = regs[i].regmap_entry[hr]; // regs[i-1].regmap[hr];
4965 if (hr == EXCLUDE_REG || reg <= 0)
4967 if (!((regs[i-1].isconst >> hr) & 1))
4969 if (i > 1 && reg == regs[i-2].regmap[hr] && constmap[i-1][hr] == constmap[i-2][hr])
4971 emit_movimm(constmap[i-1][hr],0);
4972 emit_storereg(reg, 0);
4975 if (dops[i].opcode == 0x0f) { // LUI
4976 emit_movimm(cinfo[i].imm << 16, 0);
4977 emit_storereg(dops[i].rt1, 0);
4979 emit_movimm(start+i*4,0);
4980 emit_writeword(0,&pcaddr);
4981 int cc = get_reg(regs[i].regmap_entry, CCREG);
4983 emit_loadreg(CCREG, cc = 0);
4984 emit_addimm(cc, ccadj_, 0);
4985 emit_writeword(0, &psxRegs.cycle);
4986 emit_far_call(do_insn_cmp);
4987 //emit_readword(&cycle,0);
4988 //emit_addimm(0,2,0);
4989 //emit_writeword(0,&cycle);
4991 restore_regs(reglist);
4992 assem_debug("\\\\do_insn_cmp\n");
4994 static void drc_dbg_emit_wb_dirtys(int i, const struct regstat *i_regs)
4996 // write-out non-consts, consts are likely different because of get_final_value()
4997 if (i_regs->dirty & ~i_regs->loadedconst) {
4998 assem_debug("/ drc_dbg_wb\n");
4999 wb_dirtys(i_regs->regmap, i_regs->dirty & ~i_regs->loadedconst);
5000 assem_debug("\\ drc_dbg_wb\n");
5004 #define drc_dbg_emit_do_cmp(x,y)
5005 #define drc_dbg_emit_wb_dirtys(x,y)
5008 // Used when a branch jumps into the delay slot of another branch
5009 static void ds_assemble_entry(int i)
5011 int t = (cinfo[i].ba - start) >> 2;
5012 int ccadj_ = -CLOCK_ADJUST(1);
5014 instr_addr[t] = out;
5015 assem_debug("Assemble delay slot at %x\n",cinfo[i].ba);
5016 assem_debug("<->\n");
5017 drc_dbg_emit_do_cmp(t, ccadj_);
5018 if(regs[t].regmap_entry[HOST_CCREG]==CCREG&®s[t].regmap[HOST_CCREG]!=CCREG)
5019 wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty);
5020 load_regs(regs[t].regmap_entry,regs[t].regmap,dops[t].rs1,dops[t].rs2);
5021 address_generation(t,®s[t],regs[t].regmap_entry);
5022 if (ram_offset && (dops[t].is_load || dops[t].is_store))
5023 load_reg(regs[t].regmap_entry,regs[t].regmap,ROREG);
5024 if (dops[t].is_store)
5025 load_reg(regs[t].regmap_entry,regs[t].regmap,INVCP);
5027 switch (dops[t].itype) {
5035 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
5038 assemble(t, ®s[t], ccadj_);
5040 store_regs_bt(regs[t].regmap,regs[t].dirty,cinfo[i].ba+4);
5041 load_regs_bt(regs[t].regmap,regs[t].dirty,cinfo[i].ba+4);
5042 if(internal_branch(cinfo[i].ba+4))
5043 assem_debug("branch: internal\n");
5045 assem_debug("branch: external\n");
5046 assert(internal_branch(cinfo[i].ba+4));
5047 add_to_linker(out,cinfo[i].ba+4,internal_branch(cinfo[i].ba+4));
5051 // Load 2 immediates optimizing for small code size
5052 static void emit_mov2imm_compact(int imm1,u_int rt1,int imm2,u_int rt2)
5054 emit_movimm(imm1,rt1);
5055 emit_movimm_from(imm1,rt1,imm2,rt2);
5058 static void do_cc(int i, const signed char i_regmap[], int *adj,
5059 int addr, int taken, int invert)
5061 int count, count_plus2;
5065 if(dops[i].itype==RJUMP)
5069 //if(cinfo[i].ba>=start && cinfo[i].ba<(start+slen*4))
5070 if(internal_branch(cinfo[i].ba))
5072 t=(cinfo[i].ba-start)>>2;
5073 if(dops[t].is_ds) *adj=-CLOCK_ADJUST(1); // Branch into delay slot adds an extra cycle
5074 else *adj=cinfo[t].ccadj;
5080 count = cinfo[i].ccadj;
5081 count_plus2 = count + CLOCK_ADJUST(2);
5082 if(taken==TAKEN && i==(cinfo[i].ba-start)>>2 && source[i+1]==0) {
5084 if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
5086 //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
5087 emit_andimm(HOST_CCREG,3,HOST_CCREG);
5091 else if(*adj==0||invert) {
5092 int cycles = count_plus2;
5097 if(-NO_CYCLE_PENALTY_THR<rel&&rel<0)
5098 cycles=*adj+count+2-*adj;
5101 emit_addimm_and_set_flags(cycles, HOST_CCREG);
5107 emit_cmpimm(HOST_CCREG, -count_plus2);
5111 add_stub(CC_STUB,jaddr,idle?idle:out,(*adj==0||invert||idle)?0:count_plus2,i,addr,taken,0);
5114 static void do_ccstub(int n)
5117 assem_debug("do_ccstub %x\n",start+(u_int)stubs[n].b*4);
5118 set_jump_target(stubs[n].addr, out);
5120 if (stubs[n].d != TAKEN) {
5121 wb_dirtys(branch_regs[i].regmap,branch_regs[i].dirty);
5124 if(internal_branch(cinfo[i].ba))
5125 wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5129 // Save PC as return address
5130 emit_movimm(stubs[n].c,0);
5131 emit_writeword(0,&pcaddr);
5135 // Return address depends on which way the branch goes
5136 if(dops[i].itype==CJUMP||dops[i].itype==SJUMP)
5138 int s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
5139 int s2l=get_reg(branch_regs[i].regmap,dops[i].rs2);
5145 else if(dops[i].rs2==0)
5150 #ifdef DESTRUCTIVE_WRITEBACK
5152 if((branch_regs[i].dirty>>s1l)&&1)
5153 emit_loadreg(dops[i].rs1,s1l);
5156 if((branch_regs[i].dirty>>s1l)&1)
5157 emit_loadreg(dops[i].rs2,s1l);
5160 if((branch_regs[i].dirty>>s2l)&1)
5161 emit_loadreg(dops[i].rs2,s2l);
5164 int addr=-1,alt=-1,ntaddr=-1;
5167 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5168 branch_regs[i].regmap[hr]!=dops[i].rs1 &&
5169 branch_regs[i].regmap[hr]!=dops[i].rs2 )
5177 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5178 branch_regs[i].regmap[hr]!=dops[i].rs1 &&
5179 branch_regs[i].regmap[hr]!=dops[i].rs2 )
5185 if ((dops[i].opcode & 0x3e) == 6) // BLEZ/BGTZ needs another register
5189 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5190 branch_regs[i].regmap[hr]!=dops[i].rs1 &&
5191 branch_regs[i].regmap[hr]!=dops[i].rs2 )
5197 assert(hr<HOST_REGS);
5199 if (dops[i].opcode == 4) // BEQ
5201 #ifdef HAVE_CMOV_IMM
5202 if(s2l>=0) emit_cmp(s1l,s2l);
5203 else emit_test(s1l,s1l);
5204 emit_cmov2imm_e_ne_compact(cinfo[i].ba,start+i*4+8,addr);
5206 emit_mov2imm_compact(cinfo[i].ba,addr,start+i*4+8,alt);
5207 if(s2l>=0) emit_cmp(s1l,s2l);
5208 else emit_test(s1l,s1l);
5209 emit_cmovne_reg(alt,addr);
5212 else if (dops[i].opcode == 5) // BNE
5214 #ifdef HAVE_CMOV_IMM
5215 if(s2l>=0) emit_cmp(s1l,s2l);
5216 else emit_test(s1l,s1l);
5217 emit_cmov2imm_e_ne_compact(start+i*4+8,cinfo[i].ba,addr);
5219 emit_mov2imm_compact(start+i*4+8,addr,cinfo[i].ba,alt);
5220 if(s2l>=0) emit_cmp(s1l,s2l);
5221 else emit_test(s1l,s1l);
5222 emit_cmovne_reg(alt,addr);
5225 else if (dops[i].opcode == 6) // BLEZ
5227 //emit_movimm(cinfo[i].ba,alt);
5228 //emit_movimm(start+i*4+8,addr);
5229 emit_mov2imm_compact(cinfo[i].ba,alt,start+i*4+8,addr);
5231 emit_cmovl_reg(alt,addr);
5233 else if (dops[i].opcode == 7) // BGTZ
5235 //emit_movimm(cinfo[i].ba,addr);
5236 //emit_movimm(start+i*4+8,ntaddr);
5237 emit_mov2imm_compact(cinfo[i].ba,addr,start+i*4+8,ntaddr);
5239 emit_cmovl_reg(ntaddr,addr);
5241 else if (dops[i].itype == SJUMP) // BLTZ/BGEZ
5243 //emit_movimm(cinfo[i].ba,alt);
5244 //emit_movimm(start+i*4+8,addr);
5246 emit_mov2imm_compact(cinfo[i].ba,
5247 (dops[i].opcode2 & 1) ? addr : alt, start + i*4 + 8,
5248 (dops[i].opcode2 & 1) ? alt : addr);
5250 emit_cmovs_reg(alt,addr);
5253 emit_movimm((dops[i].opcode2 & 1) ? cinfo[i].ba : start + i*4 + 8, addr);
5255 emit_writeword(addr, &pcaddr);
5258 if(dops[i].itype==RJUMP)
5260 int r=get_reg(branch_regs[i].regmap,dops[i].rs1);
5261 if (ds_writes_rjump_rs(i)) {
5262 r=get_reg(branch_regs[i].regmap,RTEMP);
5264 emit_writeword(r,&pcaddr);
5266 else {SysPrintf("Unknown branch type in do_ccstub\n");abort();}
5268 // Update cycle count
5269 assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
5270 if(stubs[n].a) emit_addimm(HOST_CCREG,(int)stubs[n].a,HOST_CCREG);
5271 emit_far_call(cc_interrupt);
5272 if(stubs[n].a) emit_addimm(HOST_CCREG,-(int)stubs[n].a,HOST_CCREG);
5273 if(stubs[n].d==TAKEN) {
5274 if(internal_branch(cinfo[i].ba))
5275 load_needed_regs(branch_regs[i].regmap,regs[(cinfo[i].ba-start)>>2].regmap_entry);
5276 else if(dops[i].itype==RJUMP) {
5277 if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
5278 emit_readword(&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
5280 emit_loadreg(dops[i].rs1,get_reg(branch_regs[i].regmap,dops[i].rs1));
5282 }else if(stubs[n].d==NOTTAKEN) {
5283 if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5284 else load_all_regs(branch_regs[i].regmap);
5286 load_all_regs(branch_regs[i].regmap);
5288 if (stubs[n].retaddr)
5289 emit_jmp(stubs[n].retaddr);
5291 do_jump_vaddr(stubs[n].e);
5294 static void add_to_linker(void *addr, u_int target, int is_internal)
5296 assert(linkcount < ARRAY_SIZE(link_addr));
5297 link_addr[linkcount].addr = addr;
5298 link_addr[linkcount].target = target;
5299 link_addr[linkcount].internal = is_internal;
5303 static void ujump_assemble_write_ra(int i)
5306 unsigned int return_address;
5307 rt=get_reg(branch_regs[i].regmap,31);
5308 //assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5310 return_address=start+i*4+8;
5313 if(internal_branch(return_address)&&dops[i+1].rt1!=31) {
5314 int temp=-1; // note: must be ds-safe
5318 if(temp>=0) do_miniht_insert(return_address,rt,temp);
5319 else emit_movimm(return_address,rt);
5327 if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
5330 if (!((regs[i].loadedconst >> rt) & 1))
5331 emit_movimm(return_address, rt); // PC into link register
5333 emit_prefetch(hash_table_get(return_address));
5339 static void ujump_assemble(int i, const struct regstat *i_regs)
5341 if(i==(cinfo[i].ba-start)>>2) assem_debug("idle loop\n");
5342 address_generation(i+1,i_regs,regs[i].regmap_entry);
5344 int temp=get_reg(branch_regs[i].regmap,PTEMP);
5345 if(dops[i].rt1==31&&temp>=0)
5347 signed char *i_regmap=i_regs->regmap;
5348 int return_address=start+i*4+8;
5349 if(get_reg(branch_regs[i].regmap,31)>0)
5350 if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
5353 if (dops[i].rt1 == 31)
5354 ujump_assemble_write_ra(i); // writeback ra for DS
5355 ds_assemble(i+1,i_regs);
5356 uint64_t bc_unneeded=branch_regs[i].u;
5357 bc_unneeded|=1|(1LL<<dops[i].rt1);
5358 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
5359 load_reg(regs[i].regmap,branch_regs[i].regmap,CCREG);
5361 cc=get_reg(branch_regs[i].regmap,CCREG);
5362 assert(cc==HOST_CCREG);
5363 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5365 if(dops[i].rt1==31&&temp>=0) emit_prefetchreg(temp);
5367 do_cc(i,branch_regs[i].regmap,&adj,cinfo[i].ba,TAKEN,0);
5368 if(adj) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc);
5369 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5370 if(internal_branch(cinfo[i].ba))
5371 assem_debug("branch: internal\n");
5373 assem_debug("branch: external\n");
5374 if (internal_branch(cinfo[i].ba) && dops[(cinfo[i].ba-start)>>2].is_ds) {
5375 ds_assemble_entry(i);
5378 add_to_linker(out,cinfo[i].ba,internal_branch(cinfo[i].ba));
5383 static void rjump_assemble_write_ra(int i)
5385 int rt,return_address;
5386 rt=get_reg_w(branch_regs[i].regmap, dops[i].rt1);
5387 //assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5389 return_address=start+i*4+8;
5393 if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
5396 if (!((regs[i].loadedconst >> rt) & 1))
5397 emit_movimm(return_address, rt); // PC into link register
5399 emit_prefetch(hash_table_get(return_address));
5403 static void rjump_assemble(int i, const struct regstat *i_regs)
5407 rs=get_reg(branch_regs[i].regmap,dops[i].rs1);
5409 if (ds_writes_rjump_rs(i)) {
5410 // Delay slot abuse, make a copy of the branch address register
5411 temp=get_reg(branch_regs[i].regmap,RTEMP);
5413 assert(regs[i].regmap[temp]==RTEMP);
5417 address_generation(i+1,i_regs,regs[i].regmap_entry);
5421 if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5422 signed char *i_regmap=i_regs->regmap;
5423 int return_address=start+i*4+8;
5424 if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
5429 if(dops[i].rs1==31) {
5430 int rh=get_reg(regs[i].regmap,RHASH);
5431 if(rh>=0) do_preload_rhash(rh);
5434 if (dops[i].rt1 != 0)
5435 rjump_assemble_write_ra(i);
5436 ds_assemble(i+1,i_regs);
5437 uint64_t bc_unneeded=branch_regs[i].u;
5438 bc_unneeded|=1|(1LL<<dops[i].rt1);
5439 bc_unneeded&=~(1LL<<dops[i].rs1);
5440 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
5441 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,CCREG);
5442 cc=get_reg(branch_regs[i].regmap,CCREG);
5443 assert(cc==HOST_CCREG);
5446 int rh=get_reg(branch_regs[i].regmap,RHASH);
5447 int ht=get_reg(branch_regs[i].regmap,RHTBL);
5448 if(dops[i].rs1==31) {
5449 if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5450 do_preload_rhtbl(ht);
5454 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1);
5455 #ifdef DESTRUCTIVE_WRITEBACK
5456 if((branch_regs[i].dirty>>rs)&1) {
5457 if(dops[i].rs1!=dops[i+1].rt1&&dops[i].rs1!=dops[i+1].rt2) {
5458 emit_loadreg(dops[i].rs1,rs);
5463 if(dops[i].rt1==31&&temp>=0) emit_prefetchreg(temp);
5466 if(dops[i].rs1==31) {
5467 do_miniht_load(ht,rh);
5470 //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5471 //if(adj) emit_addimm(cc,2*(cinfo[i].ccadj+2-adj),cc); // ??? - Shouldn't happen
5473 emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), HOST_CCREG);
5474 add_stub(CC_STUB,out,NULL,0,i,-1,TAKEN,rs);
5475 if (dops[i+1].itype == RFE)
5476 // special case for RFE
5480 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1);
5482 if(dops[i].rs1==31) {
5483 do_miniht_jump(rs,rh,ht);
5490 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5491 if(dops[i].rt1!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5495 static void cjump_assemble(int i, const struct regstat *i_regs)
5497 const signed char *i_regmap = i_regs->regmap;
5500 match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5501 assem_debug("match=%d\n",match);
5503 int unconditional=0,nop=0;
5505 int internal=internal_branch(cinfo[i].ba);
5506 if(i==(cinfo[i].ba-start)>>2) assem_debug("idle loop\n");
5507 if(!match) invert=1;
5508 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5509 if(i>(cinfo[i].ba-start)>>2) invert=1;
5512 invert=1; // because of near cond. branches
5516 s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
5517 s2l=get_reg(branch_regs[i].regmap,dops[i].rs2);
5520 s1l=get_reg(i_regmap,dops[i].rs1);
5521 s2l=get_reg(i_regmap,dops[i].rs2);
5523 if(dops[i].rs1==0&&dops[i].rs2==0)
5525 if(dops[i].opcode&1) nop=1;
5526 else unconditional=1;
5527 //assert(dops[i].opcode!=5);
5528 //assert(dops[i].opcode!=7);
5529 //assert(dops[i].opcode!=0x15);
5530 //assert(dops[i].opcode!=0x17);
5532 else if(dops[i].rs1==0)
5537 else if(dops[i].rs2==0)
5543 // Out of order execution (delay slot first)
5545 address_generation(i+1,i_regs,regs[i].regmap_entry);
5546 ds_assemble(i+1,i_regs);
5548 uint64_t bc_unneeded=branch_regs[i].u;
5549 bc_unneeded&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
5551 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
5552 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,dops[i].rs2);
5553 load_reg(regs[i].regmap,branch_regs[i].regmap,CCREG);
5554 cc=get_reg(branch_regs[i].regmap,CCREG);
5555 assert(cc==HOST_CCREG);
5557 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5558 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?cinfo[i].ba:-1,unconditional);
5559 //assem_debug("cycle count (adj)\n");
5561 do_cc(i,branch_regs[i].regmap,&adj,cinfo[i].ba,TAKEN,0);
5562 if(i!=(cinfo[i].ba-start)>>2 || source[i+1]!=0) {
5563 if(adj) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc);
5564 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5566 assem_debug("branch: internal\n");
5568 assem_debug("branch: external\n");
5569 if (internal && dops[(cinfo[i].ba-start)>>2].is_ds) {
5570 ds_assemble_entry(i);
5573 add_to_linker(out,cinfo[i].ba,internal);
5576 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5577 if(((u_int)out)&7) emit_addnop(0);
5582 emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), cc);
5585 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5588 void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL;
5589 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5590 if(adj&&!invert) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc);
5592 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5594 if(dops[i].opcode==4) // BEQ
5596 if(s2l>=0) emit_cmp(s1l,s2l);
5597 else emit_test(s1l,s1l);
5602 add_to_linker(out,cinfo[i].ba,internal);
5606 if(dops[i].opcode==5) // BNE
5608 if(s2l>=0) emit_cmp(s1l,s2l);
5609 else emit_test(s1l,s1l);
5614 add_to_linker(out,cinfo[i].ba,internal);
5618 if(dops[i].opcode==6) // BLEZ
5625 add_to_linker(out,cinfo[i].ba,internal);
5629 if(dops[i].opcode==7) // BGTZ
5636 add_to_linker(out,cinfo[i].ba,internal);
5641 if(taken) set_jump_target(taken, out);
5642 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5643 if (match && (!internal || !dops[(cinfo[i].ba-start)>>2].is_ds)) {
5645 emit_addimm(cc,-adj,cc);
5646 add_to_linker(out,cinfo[i].ba,internal);
5649 add_to_linker(out,cinfo[i].ba,internal*2);
5655 if(adj) emit_addimm(cc,-adj,cc);
5656 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5657 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5659 assem_debug("branch: internal\n");
5661 assem_debug("branch: external\n");
5662 if (internal && dops[(cinfo[i].ba - start) >> 2].is_ds) {
5663 ds_assemble_entry(i);
5666 add_to_linker(out,cinfo[i].ba,internal);
5670 set_jump_target(nottaken, out);
5673 if(nottaken1) set_jump_target(nottaken1, out);
5675 if(!invert) emit_addimm(cc,adj,cc);
5677 } // (!unconditional)
5681 // In-order execution (branch first)
5682 void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL;
5683 if(!unconditional&&!nop) {
5684 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5686 if((dops[i].opcode&0x2f)==4) // BEQ
5688 if(s2l>=0) emit_cmp(s1l,s2l);
5689 else emit_test(s1l,s1l);
5693 if((dops[i].opcode&0x2f)==5) // BNE
5695 if(s2l>=0) emit_cmp(s1l,s2l);
5696 else emit_test(s1l,s1l);
5700 if((dops[i].opcode&0x2f)==6) // BLEZ
5706 if((dops[i].opcode&0x2f)==7) // BGTZ
5712 } // if(!unconditional)
5714 uint64_t ds_unneeded=branch_regs[i].u;
5715 ds_unneeded&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
5719 if(taken) set_jump_target(taken, out);
5720 assem_debug("1:\n");
5721 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5723 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5724 address_generation(i+1,&branch_regs[i],0);
5726 load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG);
5727 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
5728 ds_assemble(i+1,&branch_regs[i]);
5729 drc_dbg_emit_wb_dirtys(i+1, &branch_regs[i]);
5730 cc=get_reg(branch_regs[i].regmap,CCREG);
5732 emit_loadreg(CCREG,cc=HOST_CCREG);
5733 // CHECK: Is the following instruction (fall thru) allocated ok?
5735 assert(cc==HOST_CCREG);
5736 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5737 do_cc(i,i_regmap,&adj,cinfo[i].ba,TAKEN,0);
5738 assem_debug("cycle count (adj)\n");
5739 if(adj) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc);
5740 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5742 assem_debug("branch: internal\n");
5744 assem_debug("branch: external\n");
5745 if (internal && dops[(cinfo[i].ba - start) >> 2].is_ds) {
5746 ds_assemble_entry(i);
5749 add_to_linker(out,cinfo[i].ba,internal);
5754 if(!unconditional) {
5755 if(nottaken1) set_jump_target(nottaken1, out);
5756 set_jump_target(nottaken, out);
5757 assem_debug("2:\n");
5758 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5760 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5761 address_generation(i+1,&branch_regs[i],0);
5763 load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG);
5764 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
5765 ds_assemble(i+1,&branch_regs[i]);
5766 cc=get_reg(branch_regs[i].regmap,CCREG);
5768 // Cycle count isn't in a register, temporarily load it then write it out
5769 emit_loadreg(CCREG,HOST_CCREG);
5770 emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), HOST_CCREG);
5773 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5774 emit_storereg(CCREG,HOST_CCREG);
5777 cc=get_reg(i_regmap,CCREG);
5778 assert(cc==HOST_CCREG);
5779 emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), cc);
5782 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5788 static void sjump_assemble(int i, const struct regstat *i_regs)
5790 const signed char *i_regmap = i_regs->regmap;
5793 match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5794 assem_debug("smatch=%d ooo=%d\n", match, dops[i].ooo);
5796 int unconditional=0,nevertaken=0;
5798 int internal=internal_branch(cinfo[i].ba);
5799 if(i==(cinfo[i].ba-start)>>2) assem_debug("idle loop\n");
5800 if(!match) invert=1;
5801 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5802 if(i>(cinfo[i].ba-start)>>2) invert=1;
5805 invert=1; // because of near cond. branches
5808 //if(dops[i].opcode2>=0x10) return; // FIXME (BxxZAL)
5809 //assert(dops[i].opcode2<0x10||dops[i].rs1==0); // FIXME (BxxZAL)
5812 s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
5815 s1l=get_reg(i_regmap,dops[i].rs1);
5819 if(dops[i].opcode2&1) unconditional=1;
5821 // These are never taken (r0 is never less than zero)
5822 //assert(dops[i].opcode2!=0);
5823 //assert(dops[i].opcode2!=2);
5824 //assert(dops[i].opcode2!=0x10);
5825 //assert(dops[i].opcode2!=0x12);
5829 // Out of order execution (delay slot first)
5831 address_generation(i+1,i_regs,regs[i].regmap_entry);
5832 ds_assemble(i+1,i_regs);
5834 uint64_t bc_unneeded=branch_regs[i].u;
5835 bc_unneeded&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
5837 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
5838 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,dops[i].rs1);
5839 load_reg(regs[i].regmap,branch_regs[i].regmap,CCREG);
5840 if(dops[i].rt1==31) {
5841 int rt,return_address;
5842 rt=get_reg(branch_regs[i].regmap,31);
5843 //assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5845 // Save the PC even if the branch is not taken
5846 return_address=start+i*4+8;
5847 emit_movimm(return_address,rt); // PC into link register
5849 if(!nevertaken) emit_prefetch(hash_table_get(return_address));
5853 cc=get_reg(branch_regs[i].regmap,CCREG);
5854 assert(cc==HOST_CCREG);
5856 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5857 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?cinfo[i].ba:-1,unconditional);
5858 assem_debug("cycle count (adj)\n");
5860 do_cc(i,branch_regs[i].regmap,&adj,cinfo[i].ba,TAKEN,0);
5861 if(i!=(cinfo[i].ba-start)>>2 || source[i+1]!=0) {
5862 if(adj) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc);
5863 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5865 assem_debug("branch: internal\n");
5867 assem_debug("branch: external\n");
5868 if (internal && dops[(cinfo[i].ba - start) >> 2].is_ds) {
5869 ds_assemble_entry(i);
5872 add_to_linker(out,cinfo[i].ba,internal);
5875 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5876 if(((u_int)out)&7) emit_addnop(0);
5880 else if(nevertaken) {
5881 emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), cc);
5884 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5887 void *nottaken = NULL;
5888 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5889 if(adj&&!invert) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc);
5892 if ((dops[i].opcode2 & 1) == 0) // BLTZ/BLTZAL
5899 add_to_linker(out,cinfo[i].ba,internal);
5910 add_to_linker(out,cinfo[i].ba,internal);
5917 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5918 if (match && (!internal || !dops[(cinfo[i].ba - start) >> 2].is_ds)) {
5920 emit_addimm(cc,-adj,cc);
5921 add_to_linker(out,cinfo[i].ba,internal);
5924 add_to_linker(out,cinfo[i].ba,internal*2);
5930 if(adj) emit_addimm(cc,-adj,cc);
5931 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5932 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5934 assem_debug("branch: internal\n");
5936 assem_debug("branch: external\n");
5937 if (internal && dops[(cinfo[i].ba - start) >> 2].is_ds) {
5938 ds_assemble_entry(i);
5941 add_to_linker(out,cinfo[i].ba,internal);
5945 set_jump_target(nottaken, out);
5949 if(!invert) emit_addimm(cc,adj,cc);
5951 } // (!unconditional)
5955 // In-order execution (branch first)
5957 void *nottaken = NULL;
5958 if (!unconditional && !nevertaken) {
5960 emit_test(s1l, s1l);
5962 if (dops[i].rt1 == 31) {
5963 int rt, return_address;
5964 rt = get_reg(branch_regs[i].regmap,31);
5966 // Save the PC even if the branch is not taken
5967 return_address = start + i*4+8;
5968 emit_movimm(return_address, rt); // PC into link register
5970 emit_prefetch(hash_table_get(return_address));
5974 if (!unconditional && !nevertaken) {
5976 if (!(dops[i].opcode2 & 1)) // BLTZ/BLTZAL
5982 uint64_t ds_unneeded=branch_regs[i].u;
5983 ds_unneeded&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
5987 //assem_debug("1:\n");
5988 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5990 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5991 address_generation(i+1,&branch_regs[i],0);
5993 load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG);
5994 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
5995 ds_assemble(i+1,&branch_regs[i]);
5996 cc=get_reg(branch_regs[i].regmap,CCREG);
5998 emit_loadreg(CCREG,cc=HOST_CCREG);
5999 // CHECK: Is the following instruction (fall thru) allocated ok?
6001 assert(cc==HOST_CCREG);
6002 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
6003 do_cc(i,i_regmap,&adj,cinfo[i].ba,TAKEN,0);
6004 assem_debug("cycle count (adj)\n");
6005 if(adj) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc);
6006 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
6008 assem_debug("branch: internal\n");
6010 assem_debug("branch: external\n");
6011 if (internal && dops[(cinfo[i].ba - start) >> 2].is_ds) {
6012 ds_assemble_entry(i);
6015 add_to_linker(out,cinfo[i].ba,internal);
6020 if(!unconditional) {
6023 set_jump_target(nottaken, out);
6025 assem_debug("1:\n");
6026 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
6027 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
6028 address_generation(i+1,&branch_regs[i],0);
6030 load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG);
6031 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
6032 ds_assemble(i+1,&branch_regs[i]);
6033 cc=get_reg(branch_regs[i].regmap,CCREG);
6035 // Cycle count isn't in a register, temporarily load it then write it out
6036 emit_loadreg(CCREG,HOST_CCREG);
6037 emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), HOST_CCREG);
6040 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
6041 emit_storereg(CCREG,HOST_CCREG);
6044 cc=get_reg(i_regmap,CCREG);
6045 assert(cc==HOST_CCREG);
6046 emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), cc);
6049 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
6055 static void check_regmap(signed char *regmap)
6059 for (i = 0; i < HOST_REGS; i++) {
6062 for (j = i + 1; j < HOST_REGS; j++)
6063 assert(regmap[i] != regmap[j]);
6069 #include <inttypes.h>
6070 static char insn[MAXBLOCK][10];
6072 #define set_mnemonic(i_, n_) \
6073 strcpy(insn[i_], n_)
6075 void print_regmap(const char *name, const signed char *regmap)
6079 fputs(name, stdout);
6080 for (i = 0; i < HOST_REGS; i++) {
6083 l = snprintf(buf, sizeof(buf), "$%d", regmap[i]);
6087 printf(" r%d=%s", i, buf);
6089 fputs("\n", stdout);
6093 void disassemble_inst(int i)
6095 if (dops[i].bt) printf("*"); else printf(" ");
6096 switch(dops[i].itype) {
6098 printf (" %x: %s %8x\n",start+i*4,insn[i],cinfo[i].ba);break;
6100 printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2,i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):cinfo[i].ba);break;
6102 printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
6104 if (dops[i].opcode2 == 9 && dops[i].rt1 != 31)
6105 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1);
6107 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rs1);
6110 if(dops[i].opcode==0xf) //LUI
6111 printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],dops[i].rt1,cinfo[i].imm&0xffff);
6113 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,cinfo[i].imm);
6117 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,cinfo[i].imm);
6121 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],dops[i].rs2,dops[i].rs1,cinfo[i].imm);
6125 printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,dops[i].rs2);
6128 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2);
6131 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,cinfo[i].imm);
6134 if((dops[i].opcode2&0x1d)==0x10)
6135 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rt1);
6136 else if((dops[i].opcode2&0x1d)==0x11)
6137 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rs1);
6139 printf (" %x: %s\n",start+i*4,insn[i]);
6142 if(dops[i].opcode2==0)
6143 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC0
6144 else if(dops[i].opcode2==4)
6145 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC0
6146 else printf (" %x: %s\n",start+i*4,insn[i]);
6149 if(dops[i].opcode2<3)
6150 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC2
6151 else if(dops[i].opcode2>3)
6152 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC2
6153 else printf (" %x: %s\n",start+i*4,insn[i]);
6156 printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,dops[i].rs1,cinfo[i].imm);
6159 printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
6162 //printf (" %s %8x\n",insn[i],source[i]);
6163 printf (" %x: %s\n",start+i*4,insn[i]);
6165 #ifndef REGMAP_PRINT
6168 printf("D: %x WD: %x U: %"PRIx64" hC: %x hWC: %x hLC: %x\n",
6169 regs[i].dirty, regs[i].wasdirty, unneeded_reg[i],
6170 regs[i].isconst, regs[i].wasconst, regs[i].loadedconst);
6171 print_regmap("pre: ", regmap_pre[i]);
6172 print_regmap("entry: ", regs[i].regmap_entry);
6173 print_regmap("map: ", regs[i].regmap);
6174 if (dops[i].is_jump) {
6175 print_regmap("bentry:", branch_regs[i].regmap_entry);
6176 print_regmap("bmap: ", branch_regs[i].regmap);
6180 #define set_mnemonic(i_, n_)
6181 static void disassemble_inst(int i) {}
6184 #define DRC_TEST_VAL 0x74657374
6186 static noinline void new_dynarec_test(void)
6188 int (*testfunc)(void);
6193 // check structure linkage
6194 if ((u_char *)rcnts - (u_char *)&psxRegs != sizeof(psxRegs))
6196 SysPrintf("linkage_arm* miscompilation/breakage detected.\n");
6199 SysPrintf("(%p) testing if we can run recompiled code @%p...\n",
6200 new_dynarec_test, out);
6201 ((volatile u_int *)NDRC_WRITE_OFFSET(out))[0]++; // make the cache dirty
6203 for (i = 0; i < ARRAY_SIZE(ret); i++) {
6204 out = ndrc->translation_cache;
6205 beginning = start_block();
6206 emit_movimm(DRC_TEST_VAL + i, 0); // test
6209 end_block(beginning);
6210 testfunc = beginning;
6211 ret[i] = testfunc();
6214 if (ret[0] == DRC_TEST_VAL && ret[1] == DRC_TEST_VAL + 1)
6215 SysPrintf("test passed.\n");
6217 SysPrintf("test failed, will likely crash soon (r=%08x %08x)\n", ret[0], ret[1]);
6218 out = ndrc->translation_cache;
6221 static int get_cycle_multiplier(void)
6223 return Config.cycle_multiplier_override && Config.cycle_multiplier == CYCLE_MULT_DEFAULT
6224 ? Config.cycle_multiplier_override : Config.cycle_multiplier;
6227 // clear the state completely, instead of just marking
6228 // things invalid like invalidate_all_pages() does
6229 void new_dynarec_clear_full(void)
6232 out = ndrc->translation_cache;
6233 memset(invalid_code,1,sizeof(invalid_code));
6234 memset(shadow,0,sizeof(shadow));
6238 expirep = EXPIRITY_OFFSET;
6239 pending_exception=0;
6242 inv_code_start=inv_code_end=~0;
6245 for (n = 0; n < ARRAY_SIZE(blocks); n++)
6246 blocks_clear(&blocks[n]);
6247 for (n = 0; n < ARRAY_SIZE(jumps); n++) {
6251 stat_clear(stat_blocks);
6252 stat_clear(stat_links);
6254 if (cycle_multiplier_old != Config.cycle_multiplier
6255 || new_dynarec_hacks_old != new_dynarec_hacks)
6257 SysPrintf("ndrc config: mul=%d, ha=%x, pex=%d\n",
6258 get_cycle_multiplier(), new_dynarec_hacks, Config.PreciseExceptions);
6260 cycle_multiplier_old = Config.cycle_multiplier;
6261 new_dynarec_hacks_old = new_dynarec_hacks;
6264 static int pgsize(void)
6268 ret = sysconf(_SC_PAGESIZE);
6275 void new_dynarec_init(void)
6277 int align = pgsize() - 1;
6278 SysPrintf("Init new dynarec, ndrc size %x, pgsize %d\n",
6279 (int)sizeof(*ndrc), align + 1);
6284 #ifdef BASE_ADDR_DYNAMIC
6286 sceBlock = getVMBlock(); //sceKernelAllocMemBlockForVM("code", sizeof(*ndrc));
6288 SysPrintf("sceKernelAllocMemBlockForVM failed: %x\n", sceBlock);
6289 int ret = sceKernelGetMemBlockBase(sceBlock, (void **)&ndrc);
6291 SysPrintf("sceKernelGetMemBlockBase failed: %x\n", ret);
6292 sceKernelOpenVMDomain();
6293 sceClibPrintf("translation_cache = 0x%08lx\n ", (long)ndrc->translation_cache);
6294 #elif defined(_MSC_VER)
6295 ndrc = VirtualAlloc(NULL, sizeof(*ndrc), MEM_COMMIT | MEM_RESERVE,
6296 PAGE_EXECUTE_READWRITE);
6297 #elif defined(HAVE_LIBNX)
6298 Result rc = jitCreate(&g_jit, sizeof(*ndrc));
6300 SysPrintf("jitCreate failed: %08x\n", rc);
6301 SysPrintf("jitCreate: RX: %p RW: %p type: %d\n", g_jit.rx_addr, g_jit.rw_addr, g_jit.type);
6302 jitTransitionToWritable(&g_jit);
6303 ndrc = g_jit.rx_addr;
6304 ndrc_write_ofs = (char *)g_jit.rw_addr - (char *)ndrc;
6305 memset(NDRC_WRITE_OFFSET(&ndrc->tramp), 0, sizeof(ndrc->tramp));
6307 uintptr_t desired_addr = 0;
6308 int prot = PROT_READ | PROT_WRITE | PROT_EXEC;
6309 int flags = MAP_PRIVATE | MAP_ANONYMOUS;
6313 desired_addr = ((uintptr_t)&_end + 0xffffff) & ~0xffffffl;
6315 #ifdef TC_WRITE_OFFSET
6316 // mostly for testing
6317 fd = open("/dev/shm/pcsxr", O_CREAT | O_RDWR, 0600);
6318 ftruncate(fd, sizeof(*ndrc));
6319 void *mw = mmap(NULL, sizeof(*ndrc), PROT_READ | PROT_WRITE,
6320 (flags = MAP_SHARED), fd, 0);
6321 assert(mw != MAP_FAILED);
6322 prot = PROT_READ | PROT_EXEC;
6324 ndrc = mmap((void *)desired_addr, sizeof(*ndrc), prot, flags, fd, 0);
6325 if (ndrc == MAP_FAILED) {
6326 SysPrintf("mmap() failed: %s\n", strerror(errno));
6329 #ifdef TC_WRITE_OFFSET
6330 ndrc_write_ofs = (char *)mw - (char *)ndrc;
6334 #ifndef NO_WRITE_EXEC
6335 ndrc = (struct ndrc_mem *)((size_t)(ndrc_bss + align) & ~align);
6336 // not all systems allow execute in data segment by default
6337 // size must be 4K aligned for 3DS?
6338 if (mprotect(ndrc, sizeof(*ndrc),
6339 PROT_READ | PROT_WRITE | PROT_EXEC) != 0)
6340 SysPrintf("mprotect(%p) failed: %s\n", ndrc, strerror(errno));
6343 out = ndrc->translation_cache;
6344 new_dynarec_clear_full();
6346 // Copy this into local area so we don't have to put it in every literal pool
6347 invc_ptr=invalid_code;
6351 ram_offset = (uintptr_t)psxM - 0x80000000;
6353 SysPrintf("warning: RAM is not directly mapped, performance will suffer\n");
6354 SysPrintf("Mapped (RAM/scrp/ROM/LUTs/TC):\n");
6355 SysPrintf("%p/%p/%p/%p/%p\n", psxM, psxH, psxR, mem_rtab, out);
6358 void new_dynarec_cleanup(void)
6361 #ifdef BASE_ADDR_DYNAMIC
6363 // sceBlock is managed by retroarch's bootstrap code
6364 //sceKernelFreeMemBlock(sceBlock);
6366 #elif defined(HAVE_LIBNX)
6370 if (munmap(ndrc, sizeof(*ndrc)) < 0)
6371 SysPrintf("munmap() failed\n");
6375 for (n = 0; n < ARRAY_SIZE(blocks); n++)
6376 blocks_clear(&blocks[n]);
6377 for (n = 0; n < ARRAY_SIZE(jumps); n++) {
6381 stat_clear(stat_blocks);
6382 stat_clear(stat_links);
6383 new_dynarec_print_stats();
6386 static u_int *get_source_start(u_int addr, u_int *limit)
6388 if (addr < 0x00800000
6389 || (0x80000000 <= addr && addr < 0x80800000)
6390 || (0xa0000000 <= addr && addr < 0xa0800000))
6392 // used for BIOS calls mostly?
6393 *limit = (addr & 0xa0600000) + 0x00200000;
6394 return (u_int *)(psxM + (addr & 0x1fffff));
6397 /* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
6398 (0xbfc00000 <= addr && addr < 0xbfc80000))
6400 // BIOS. The multiplier should be much higher as it's uncached 8bit mem,
6401 // but timings in PCSX are too tied to the interpreter's 2-per-insn assumption
6402 if (!HACK_ENABLED(NDHACK_OVERRIDE_CYCLE_M))
6403 cycle_multiplier_active = 200;
6405 *limit = (addr & 0xfff00000) | 0x80000;
6406 return (u_int *)((u_char *)psxR + (addr&0x7ffff));
6411 static u_int scan_for_ret(u_int addr)
6416 mem = get_source_start(addr, &limit);
6420 if (limit > addr + 0x1000)
6421 limit = addr + 0x1000;
6422 for (; addr < limit; addr += 4, mem++) {
6423 if (*mem == 0x03e00008) // jr $ra
6429 struct savestate_block {
6434 static int addr_cmp(const void *p1_, const void *p2_)
6436 const struct savestate_block *p1 = p1_, *p2 = p2_;
6437 return p1->addr - p2->addr;
6440 int new_dynarec_save_blocks(void *save, int size)
6442 struct savestate_block *sblocks = save;
6443 int maxcount = size / sizeof(sblocks[0]);
6444 struct savestate_block tmp_blocks[1024];
6445 struct block_info *block;
6446 int p, s, d, o, bcnt;
6450 for (p = 0; p < ARRAY_SIZE(blocks); p++) {
6452 for (block = blocks[p]; block != NULL; block = block->next) {
6453 if (block->is_dirty)
6455 tmp_blocks[bcnt].addr = block->start;
6456 tmp_blocks[bcnt].regflags = block->reg_sv_flags;
6461 qsort(tmp_blocks, bcnt, sizeof(tmp_blocks[0]), addr_cmp);
6463 addr = tmp_blocks[0].addr;
6464 for (s = d = 0; s < bcnt; s++) {
6465 if (tmp_blocks[s].addr < addr)
6467 if (d == 0 || tmp_blocks[d-1].addr != tmp_blocks[s].addr)
6468 tmp_blocks[d++] = tmp_blocks[s];
6469 addr = scan_for_ret(tmp_blocks[s].addr);
6472 if (o + d > maxcount)
6474 memcpy(&sblocks[o], tmp_blocks, d * sizeof(sblocks[0]));
6478 return o * sizeof(sblocks[0]);
6481 void new_dynarec_load_blocks(const void *save, int size)
6483 const struct savestate_block *sblocks = save;
6484 int count = size / sizeof(sblocks[0]);
6485 struct block_info *block;
6486 u_int regs_save[32];
6491 // restore clean blocks, if any
6492 for (page = 0, b = i = 0; page < ARRAY_SIZE(blocks); page++) {
6493 for (block = blocks[page]; block != NULL; block = block->next, b++) {
6494 if (!block->is_dirty)
6496 assert(block->source && block->copy);
6497 if (memcmp(block->source, block->copy, block->len))
6500 // see try_restore_block
6501 block->is_dirty = 0;
6502 mark_invalid_code(block->start, block->len, 0);
6506 inv_debug("load_blocks: %d/%d clean blocks\n", i, b);
6508 // change GPRs for speculation to at least partially work..
6509 memcpy(regs_save, &psxRegs.GPR, sizeof(regs_save));
6510 for (i = 1; i < 32; i++)
6511 psxRegs.GPR.r[i] = 0x80000000;
6513 for (b = 0; b < count; b++) {
6514 for (f = sblocks[b].regflags, i = 0; f; f >>= 1, i++) {
6516 psxRegs.GPR.r[i] = 0x1f800000;
6519 ndrc_get_addr_ht(sblocks[b].addr);
6521 for (f = sblocks[b].regflags, i = 0; f; f >>= 1, i++) {
6523 psxRegs.GPR.r[i] = 0x80000000;
6527 memcpy(&psxRegs.GPR, regs_save, sizeof(regs_save));
6530 void new_dynarec_print_stats(void)
6533 printf("cc %3d,%3d,%3d lu%6d,%3d,%3d c%3d inv%3d,%3d tc_offs %zu b %u,%u\n",
6534 stat_bc_pre, stat_bc_direct, stat_bc_restore,
6535 stat_ht_lookups, stat_jump_in_lookups, stat_restore_tries,
6536 stat_restore_compares, stat_inv_addr_calls, stat_inv_hits,
6537 out - ndrc->translation_cache, stat_blocks, stat_links);
6538 stat_bc_direct = stat_bc_pre = stat_bc_restore =
6539 stat_ht_lookups = stat_jump_in_lookups = stat_restore_tries =
6540 stat_restore_compares = stat_inv_addr_calls = stat_inv_hits = 0;
6544 static void force_intcall(int i)
6546 memset(&dops[i], 0, sizeof(dops[i]));
6547 dops[i].itype = INTCALL;
6548 dops[i].rs1 = CCREG;
6549 dops[i].is_exception = 1;
6553 static int apply_hacks(void)
6556 if (HACK_ENABLED(NDHACK_NO_COMPAT_HACKS))
6558 /* special hack(s) */
6559 for (i = 0; i < slen - 4; i++)
6561 // lui a4, 0xf200; jal <rcnt_read>; addu a0, 2; slti v0, 28224
6562 if (source[i] == 0x3c04f200 && dops[i+1].itype == UJUMP
6563 && source[i+2] == 0x34840002 && dops[i+3].opcode == 0x0a
6564 && cinfo[i+3].imm == 0x6e40 && dops[i+3].rs1 == 2)
6566 SysPrintf("PE2 hack @%08x\n", start + (i+3)*4);
6567 dops[i + 3].itype = NOP;
6571 if (i > 10 && source[i-1] == 0 && source[i-2] == 0x03e00008
6572 && source[i-4] == 0x8fbf0018 && source[i-6] == 0x00c0f809
6573 && dops[i-7].itype == STORE)
6576 if (dops[i].itype == IMM16)
6578 // swl r2, 15(r6); swr r2, 12(r6); sw r6, *; jalr r6
6579 if (dops[i].itype == STORELR && dops[i].rs1 == 6
6580 && dops[i-1].itype == STORELR && dops[i-1].rs1 == 6)
6582 SysPrintf("F1 hack from %08x, old dst %08x\n", start, hack_addr);
6589 if (start <= psxRegs.biosBranchCheck && psxRegs.biosBranchCheck < start + i*4)
6591 i = (psxRegs.biosBranchCheck - start) / 4u + 23;
6592 if (dops[i].is_jump && !dops[i+1].bt)
6595 dops[i+1].is_ds = 0;
6602 static int is_ld_use_hazard(const struct decoded_insn *op_ld,
6603 const struct decoded_insn *op)
6605 if (op_ld->rt1 == 0 || (op_ld->rt1 != op->rs1 && op_ld->rt1 != op->rs2))
6607 if (op_ld->itype == LOADLR && op->itype == LOADLR)
6608 return op_ld->rt1 == op_ld->rs1;
6609 return op->itype != CJUMP && op->itype != SJUMP;
6612 static void disassemble_one(int i, u_int src)
6614 unsigned int type, op, op2, op3;
6615 enum ls_width_type ls_type = LS_32;
6616 memset(&dops[i], 0, sizeof(dops[i]));
6617 memset(&cinfo[i], 0, sizeof(cinfo[i]));
6620 dops[i].opcode = op = src >> 26;
6623 set_mnemonic(i, "???");
6626 case 0x00: set_mnemonic(i, "special");
6630 case 0x00: set_mnemonic(i, "SLL"); type=SHIFTIMM; break;
6631 case 0x02: set_mnemonic(i, "SRL"); type=SHIFTIMM; break;
6632 case 0x03: set_mnemonic(i, "SRA"); type=SHIFTIMM; break;
6633 case 0x04: set_mnemonic(i, "SLLV"); type=SHIFT; break;
6634 case 0x06: set_mnemonic(i, "SRLV"); type=SHIFT; break;
6635 case 0x07: set_mnemonic(i, "SRAV"); type=SHIFT; break;
6636 case 0x08: set_mnemonic(i, "JR"); type=RJUMP; break;
6637 case 0x09: set_mnemonic(i, "JALR"); type=RJUMP; break;
6638 case 0x0C: set_mnemonic(i, "SYSCALL"); type=SYSCALL; break;
6639 case 0x0D: set_mnemonic(i, "BREAK"); type=SYSCALL; break;
6640 case 0x10: set_mnemonic(i, "MFHI"); type=MOV; break;
6641 case 0x11: set_mnemonic(i, "MTHI"); type=MOV; break;
6642 case 0x12: set_mnemonic(i, "MFLO"); type=MOV; break;
6643 case 0x13: set_mnemonic(i, "MTLO"); type=MOV; break;
6644 case 0x18: set_mnemonic(i, "MULT"); type=MULTDIV; break;
6645 case 0x19: set_mnemonic(i, "MULTU"); type=MULTDIV; break;
6646 case 0x1A: set_mnemonic(i, "DIV"); type=MULTDIV; break;
6647 case 0x1B: set_mnemonic(i, "DIVU"); type=MULTDIV; break;
6648 case 0x20: set_mnemonic(i, "ADD"); type=ALU; break;
6649 case 0x21: set_mnemonic(i, "ADDU"); type=ALU; break;
6650 case 0x22: set_mnemonic(i, "SUB"); type=ALU; break;
6651 case 0x23: set_mnemonic(i, "SUBU"); type=ALU; break;
6652 case 0x24: set_mnemonic(i, "AND"); type=ALU; break;
6653 case 0x25: set_mnemonic(i, "OR"); type=ALU; break;
6654 case 0x26: set_mnemonic(i, "XOR"); type=ALU; break;
6655 case 0x27: set_mnemonic(i, "NOR"); type=ALU; break;
6656 case 0x2A: set_mnemonic(i, "SLT"); type=ALU; break;
6657 case 0x2B: set_mnemonic(i, "SLTU"); type=ALU; break;
6660 case 0x01: set_mnemonic(i, "regimm");
6662 op2 = (src >> 16) & 0x1f;
6665 case 0x10: set_mnemonic(i, "BLTZAL"); break;
6666 case 0x11: set_mnemonic(i, "BGEZAL"); break;
6669 set_mnemonic(i, "BGEZ");
6671 set_mnemonic(i, "BLTZ");
6674 case 0x02: set_mnemonic(i, "J"); type=UJUMP; break;
6675 case 0x03: set_mnemonic(i, "JAL"); type=UJUMP; break;
6676 case 0x04: set_mnemonic(i, "BEQ"); type=CJUMP; break;
6677 case 0x05: set_mnemonic(i, "BNE"); type=CJUMP; break;
6678 case 0x06: set_mnemonic(i, "BLEZ"); type=CJUMP; break;
6679 case 0x07: set_mnemonic(i, "BGTZ"); type=CJUMP; break;
6680 case 0x08: set_mnemonic(i, "ADDI"); type=IMM16; break;
6681 case 0x09: set_mnemonic(i, "ADDIU"); type=IMM16; break;
6682 case 0x0A: set_mnemonic(i, "SLTI"); type=IMM16; break;
6683 case 0x0B: set_mnemonic(i, "SLTIU"); type=IMM16; break;
6684 case 0x0C: set_mnemonic(i, "ANDI"); type=IMM16; break;
6685 case 0x0D: set_mnemonic(i, "ORI"); type=IMM16; break;
6686 case 0x0E: set_mnemonic(i, "XORI"); type=IMM16; break;
6687 case 0x0F: set_mnemonic(i, "LUI"); type=IMM16; break;
6688 case 0x10: set_mnemonic(i, "COP0");
6689 op2 = (src >> 21) & 0x1f;
6694 case 0x01: case 0x02: case 0x06: case 0x08: type = INTCALL; break;
6695 case 0x10: set_mnemonic(i, "RFE"); type=RFE; break;
6696 default: type = OTHER; break;
6704 set_mnemonic(i, "MFC0");
6705 rd = (src >> 11) & 0x1F;
6706 if (!(0x00000417u & (1u << rd)))
6709 case 0x04: set_mnemonic(i, "MTC0"); type=COP0; break;
6711 case 0x06: type = INTCALL; break;
6712 default: type = OTHER; break;
6715 case 0x11: set_mnemonic(i, "COP1");
6716 op2 = (src >> 21) & 0x1f;
6718 case 0x12: set_mnemonic(i, "COP2");
6719 op2 = (src >> 21) & 0x1f;
6722 if (gte_handlers[src & 0x3f] != NULL) {
6724 if (gte_regnames[src & 0x3f] != NULL)
6725 strcpy(insn[i], gte_regnames[src & 0x3f]);
6727 snprintf(insn[i], sizeof(insn[i]), "COP2 %x", src & 0x3f);
6734 case 0x00: set_mnemonic(i, "MFC2"); type=COP2; break;
6735 case 0x02: set_mnemonic(i, "CFC2"); type=COP2; break;
6736 case 0x04: set_mnemonic(i, "MTC2"); type=COP2; break;
6737 case 0x06: set_mnemonic(i, "CTC2"); type=COP2; break;
6740 case 0x13: set_mnemonic(i, "COP3");
6741 op2 = (src >> 21) & 0x1f;
6743 case 0x20: set_mnemonic(i, "LB"); type=LOAD; ls_type = LS_8; break;
6744 case 0x21: set_mnemonic(i, "LH"); type=LOAD; ls_type = LS_16; break;
6745 case 0x22: set_mnemonic(i, "LWL"); type=LOADLR; ls_type = LS_LR; break;
6746 case 0x23: set_mnemonic(i, "LW"); type=LOAD; ls_type = LS_32; break;
6747 case 0x24: set_mnemonic(i, "LBU"); type=LOAD; ls_type = LS_8; break;
6748 case 0x25: set_mnemonic(i, "LHU"); type=LOAD; ls_type = LS_16; break;
6749 case 0x26: set_mnemonic(i, "LWR"); type=LOADLR; ls_type = LS_LR; break;
6750 case 0x28: set_mnemonic(i, "SB"); type=STORE; ls_type = LS_8; break;
6751 case 0x29: set_mnemonic(i, "SH"); type=STORE; ls_type = LS_16; break;
6752 case 0x2A: set_mnemonic(i, "SWL"); type=STORELR; ls_type = LS_LR; break;
6753 case 0x2B: set_mnemonic(i, "SW"); type=STORE; ls_type = LS_32; break;
6754 case 0x2E: set_mnemonic(i, "SWR"); type=STORELR; ls_type = LS_LR; break;
6755 case 0x32: set_mnemonic(i, "LWC2"); type=C2LS; ls_type = LS_32; break;
6756 case 0x3A: set_mnemonic(i, "SWC2"); type=C2LS; ls_type = LS_32; break;
6758 if (Config.HLE && (src & 0x03ffffff) < ARRAY_SIZE(psxHLEt)) {
6759 set_mnemonic(i, "HLECALL");
6766 if (type == INTCALL)
6767 SysPrintf("NI %08x @%08x (%08x)\n", src, start + i*4, start);
6768 dops[i].itype = type;
6769 dops[i].opcode2 = op2;
6770 dops[i].ls_type = ls_type;
6771 /* Get registers/immediates */
6773 gte_rs[i]=gte_rt[i]=0;
6780 dops[i].rs1 = (src >> 21) & 0x1f;
6781 dops[i].rt1 = (src >> 16) & 0x1f;
6782 cinfo[i].imm = (short)src;
6786 dops[i].rs1 = (src >> 21) & 0x1f;
6787 dops[i].rs2 = (src >> 16) & 0x1f;
6788 cinfo[i].imm = (short)src;
6791 // LWL/LWR only load part of the register,
6792 // therefore the target register must be treated as a source too
6793 dops[i].rs1 = (src >> 21) & 0x1f;
6794 dops[i].rs2 = (src >> 16) & 0x1f;
6795 dops[i].rt1 = (src >> 16) & 0x1f;
6796 cinfo[i].imm = (short)src;
6799 if (op==0x0f) dops[i].rs1=0; // LUI instruction has no source register
6800 else dops[i].rs1 = (src >> 21) & 0x1f;
6802 dops[i].rt1 = (src >> 16) & 0x1f;
6803 if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
6804 cinfo[i].imm = (unsigned short)src;
6806 cinfo[i].imm = (short)src;
6810 // The JAL instruction writes to r31.
6817 dops[i].rs1 = (src >> 21) & 0x1f;
6818 // The JALR instruction writes to rd.
6820 dops[i].rt1 = (src >> 11) & 0x1f;
6825 dops[i].rs1 = (src >> 21) & 0x1f;
6826 dops[i].rs2 = (src >> 16) & 0x1f;
6827 if(op&2) { // BGTZ/BLEZ
6832 dops[i].rs1 = (src >> 21) & 0x1f;
6833 dops[i].rs2 = CCREG;
6834 if (op2 == 0x10 || op2 == 0x11) { // BxxAL
6836 // NOTE: If the branch is not taken, r31 is still overwritten
6840 dops[i].rs1=(src>>21)&0x1f; // source
6841 dops[i].rs2=(src>>16)&0x1f; // subtract amount
6842 dops[i].rt1=(src>>11)&0x1f; // destination
6845 dops[i].rs1=(src>>21)&0x1f; // source
6846 dops[i].rs2=(src>>16)&0x1f; // divisor
6851 if(op2==0x10) dops[i].rs1=HIREG; // MFHI
6852 if(op2==0x11) dops[i].rt1=HIREG; // MTHI
6853 if(op2==0x12) dops[i].rs1=LOREG; // MFLO
6854 if(op2==0x13) dops[i].rt1=LOREG; // MTLO
6855 if((op2&0x1d)==0x10) dops[i].rt1=(src>>11)&0x1f; // MFxx
6856 if((op2&0x1d)==0x11) dops[i].rs1=(src>>21)&0x1f; // MTxx
6859 dops[i].rs1=(src>>16)&0x1f; // target of shift
6860 dops[i].rs2=(src>>21)&0x1f; // shift amount
6861 dops[i].rt1=(src>>11)&0x1f; // destination
6864 dops[i].rs1=(src>>16)&0x1f;
6866 dops[i].rt1=(src>>11)&0x1f;
6867 cinfo[i].imm=(src>>6)&0x1f;
6870 if(op2==0) dops[i].rt1=(src>>16)&0x1F; // MFC0
6871 if(op2==4) dops[i].rs1=(src>>16)&0x1F; // MTC0
6872 if(op2==4&&((src>>11)&0x1e)==12) dops[i].rs2=CCREG;
6875 if(op2<3) dops[i].rt1=(src>>16)&0x1F; // MFC2/CFC2
6876 if(op2>3) dops[i].rs1=(src>>16)&0x1F; // MTC2/CTC2
6877 int gr=(src>>11)&0x1F;
6880 case 0x00: gte_rs[i]=1ll<<gr; break; // MFC2
6881 case 0x04: gte_rt[i]=1ll<<gr; break; // MTC2
6882 case 0x02: gte_rs[i]=1ll<<(gr+32); break; // CFC2
6883 case 0x06: gte_rt[i]=1ll<<(gr+32); break; // CTC2
6887 dops[i].rs1=(src>>21)&0x1F;
6888 cinfo[i].imm=(short)src;
6889 if(op==0x32) gte_rt[i]=1ll<<((src>>16)&0x1F); // LWC2
6890 else gte_rs[i]=1ll<<((src>>16)&0x1F); // SWC2
6893 gte_rs[i]=gte_reg_reads[src&0x3f];
6894 gte_rt[i]=gte_reg_writes[src&0x3f];
6895 gte_rt[i]|=1ll<<63; // every op changes flags
6896 if((src&0x3f)==GTE_MVMVA) {
6897 int v = (src >> 15) & 3;
6898 gte_rs[i]&=~0xe3fll;
6899 if(v==3) gte_rs[i]|=0xe00ll;
6900 else gte_rs[i]|=3ll<<(v*2);
6913 static noinline void pass1_disassemble(u_int pagelimit)
6915 int i, j, done = 0, ni_count = 0;
6918 for (i = 0; !done; i++)
6920 int force_j_to_interpreter = 0;
6921 unsigned int type, op, op2;
6923 disassemble_one(i, source[i]);
6924 dops[i].is_ds = ds_next; ds_next = 0;
6925 type = dops[i].itype;
6926 op = dops[i].opcode;
6927 op2 = dops[i].opcode2;
6929 /* Calculate branch target addresses */
6931 cinfo[i].ba=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
6932 else if(type==CJUMP&&dops[i].rs1==dops[i].rs2&&(op&1))
6933 cinfo[i].ba=start+i*4+8; // Ignore never taken branch
6934 else if(type==SJUMP&&dops[i].rs1==0&&!(op2&1))
6935 cinfo[i].ba=start+i*4+8; // Ignore never taken branch
6936 else if(type==CJUMP||type==SJUMP)
6937 cinfo[i].ba=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
6939 /* simplify always (not)taken branches */
6940 if (type == CJUMP && dops[i].rs1 == dops[i].rs2) {
6941 dops[i].rs1 = dops[i].rs2 = 0;
6943 dops[i].itype = type = UJUMP;
6944 dops[i].rs2 = CCREG;
6947 else if (type == SJUMP && dops[i].rs1 == 0 && (op2 & 1))
6948 dops[i].itype = type = UJUMP;
6950 dops[i].is_jump = type == RJUMP || type == UJUMP || type == CJUMP || type == SJUMP;
6951 dops[i].is_ujump = type == RJUMP || type == UJUMP;
6952 dops[i].is_load = type == LOAD || type == LOADLR || op == 0x32; // LWC2
6953 dops[i].is_delay_load = (dops[i].is_load || (source[i] & 0xf3d00000) == 0x40000000); // MFC/CFC
6954 dops[i].is_store = type == STORE || type == STORELR || op == 0x3a; // SWC2
6955 dops[i].is_exception = type == SYSCALL || type == HLECALL || type == INTCALL;
6956 dops[i].may_except = dops[i].is_exception || (type == ALU && (op2 == 0x20 || op2 == 0x22)) || op == 8;
6957 ds_next = dops[i].is_jump;
6959 if (((op & 0x37) == 0x21 || op == 0x25) // LH/SH/LHU
6960 && ((cinfo[i].imm & 1) || Config.PreciseExceptions))
6961 dops[i].may_except = 1;
6962 if (((op & 0x37) == 0x23 || (op & 0x37) == 0x32) // LW/SW/LWC2/SWC2
6963 && ((cinfo[i].imm & 3) || Config.PreciseExceptions))
6964 dops[i].may_except = 1;
6966 /* rare messy cases to just pass over to the interpreter */
6967 if (i > 0 && dops[i-1].is_jump) {
6969 // branch in delay slot?
6970 if (dops[i].is_jump) {
6971 // don't handle first branch and call interpreter if it's hit
6972 SysPrintf("branch in DS @%08x (%08x)\n", start + i*4, start);
6973 force_j_to_interpreter = 1;
6975 // load delay detection through a branch
6976 else if (dops[i].is_delay_load && dops[i].rt1 != 0) {
6977 const struct decoded_insn *dop = NULL;
6979 if (cinfo[i-1].ba != -1) {
6980 t = (cinfo[i-1].ba - start) / 4;
6981 if (t < 0 || t > i) {
6983 u_int *mem = get_source_start(cinfo[i-1].ba, &limit);
6985 disassemble_one(MAXBLOCK - 1, mem[0]);
6986 dop = &dops[MAXBLOCK - 1];
6992 if ((dop && is_ld_use_hazard(&dops[i], dop))
6993 || (!dop && Config.PreciseExceptions)) {
6994 // jump target wants DS result - potential load delay effect
6995 SysPrintf("load delay in DS @%08x (%08x)\n", start + i*4, start);
6996 force_j_to_interpreter = 1;
6997 if (0 <= t && t < i)
6998 dops[t + 1].bt = 1; // expected return from interpreter
7000 else if(i>=2&&dops[i-2].rt1==2&&dops[i].rt1==2&&dops[i].rs1!=2&&dops[i].rs2!=2&&dops[i-1].rs1!=2&&dops[i-1].rs2!=2&&
7001 !(i>=3&&dops[i-3].is_jump)) {
7002 // v0 overwrite like this is a sign of trouble, bail out
7003 SysPrintf("v0 overwrite @%08x (%08x)\n", start + i*4, start);
7004 force_j_to_interpreter = 1;
7008 else if (i > 0 && dops[i-1].is_delay_load
7009 && is_ld_use_hazard(&dops[i-1], &dops[i])
7010 && (i < 2 || !dops[i-2].is_ujump)) {
7011 SysPrintf("load delay @%08x (%08x)\n", start + i*4, start);
7012 for (j = i - 1; j > 0 && dops[j-1].is_delay_load; j--)
7013 if (dops[j-1].rt1 != dops[i-1].rt1)
7015 force_j_to_interpreter = 1;
7017 if (force_j_to_interpreter) {
7020 i = j; // don't compile the problematic branch/load/etc
7022 if (dops[i].is_exception && i > 0 && dops[i-1].is_jump) {
7023 SysPrintf("exception in DS @%08x (%08x)\n", start + i*4, start);
7028 if (i >= 2 && (source[i-2] & 0xffe0f800) == 0x40806000) // MTC0 $12
7030 if (i >= 1 && (source[i-1] & 0xffe0f800) == 0x40806800) // MTC0 $13
7033 /* Is this the end of the block? */
7034 if (i > 0 && dops[i-1].is_ujump) {
7035 if (dops[i-1].rt1 == 0) { // not jal
7036 int found_bbranch = 0, t = (cinfo[i-1].ba - start) / 4;
7037 if ((u_int)(t - i) < 64 && start + (t+64)*4 < pagelimit) {
7038 // scan for a branch back to i+1
7039 for (j = t; j < t + 64; j++) {
7040 int tmpop = source[j] >> 26;
7041 if (tmpop == 1 || ((tmpop & ~3) == 4)) {
7042 int t2 = j + 1 + (int)(signed short)source[j];
7044 //printf("blk expand %08x<-%08x\n", start + (i+1)*4, start + j*4);
7055 if(stop_after_jal) done=1;
7057 if((source[i+1]&0xfc00003f)==0x0d) done=1;
7059 // Don't recompile stuff that's already compiled
7060 if(check_addr(start+i*4+4)) done=1;
7061 // Don't get too close to the limit
7062 if (i > MAXBLOCK - 64)
7065 if (dops[i].itype == HLECALL)
7067 else if (dops[i].itype == INTCALL)
7069 else if (dops[i].is_exception)
7070 done = stop_after_jal ? 1 : 2;
7072 // Does the block continue due to a branch?
7075 if(cinfo[j].ba==start+i*4) done=j=0; // Branch into delay slot
7076 if(cinfo[j].ba==start+i*4+4) done=j=0;
7077 if(cinfo[j].ba==start+i*4+8) done=j=0;
7080 //assert(i<MAXBLOCK-1);
7081 if(start+i*4==pagelimit-4) done=1;
7082 assert(start+i*4<pagelimit);
7083 if (i == MAXBLOCK - 2)
7085 // Stop if we're compiling junk
7086 if (dops[i].itype == INTCALL && (++ni_count > 8 || dops[i].opcode == 0x11)) {
7087 done=stop_after_jal=1;
7088 SysPrintf("Disabled speculative precompilation\n");
7091 while (i > 0 && dops[i-1].is_jump)
7094 assert(!dops[i-1].is_jump);
7098 // Basic liveness analysis for MIPS registers
7099 static noinline void pass2_unneeded_regs(int istart,int iend,int r)
7102 uint64_t u,gte_u,b,gte_b;
7103 uint64_t temp_u,temp_gte_u=0;
7104 uint64_t gte_u_unknown=0;
7105 if (HACK_ENABLED(NDHACK_GTE_UNNEEDED))
7109 gte_u=gte_u_unknown;
7111 //u=unneeded_reg[iend+1];
7113 gte_u=gte_unneeded[iend+1];
7116 for (i=iend;i>=istart;i--)
7118 //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
7121 // If subroutine call, flag return address as a possible branch target
7122 if(dops[i].rt1==31 && i<slen-2) dops[i+2].bt=1;
7124 if(cinfo[i].ba<start || cinfo[i].ba>=(start+slen*4))
7126 // Branch out of this block, flush all regs
7128 gte_u=gte_u_unknown;
7129 branch_unneeded_reg[i]=u;
7130 // Merge in delay slot
7131 u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
7132 u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7135 gte_u&=~gte_rs[i+1];
7139 // Internal branch, flag target
7140 dops[(cinfo[i].ba-start)>>2].bt=1;
7141 if(cinfo[i].ba<=start+i*4) {
7143 if(dops[i].is_ujump)
7145 // Unconditional branch
7149 // Conditional branch (not taken case)
7150 temp_u=unneeded_reg[i+2];
7151 temp_gte_u&=gte_unneeded[i+2];
7153 // Merge in delay slot
7154 temp_u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
7155 temp_u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7157 temp_gte_u|=gte_rt[i+1];
7158 temp_gte_u&=~gte_rs[i+1];
7159 temp_u|=(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2);
7160 temp_u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7162 temp_gte_u|=gte_rt[i];
7163 temp_gte_u&=~gte_rs[i];
7164 unneeded_reg[i]=temp_u;
7165 gte_unneeded[i]=temp_gte_u;
7166 // Only go three levels deep. This recursion can take an
7167 // excessive amount of time if there are a lot of nested loops.
7169 pass2_unneeded_regs((cinfo[i].ba-start)>>2,i-1,r+1);
7171 unneeded_reg[(cinfo[i].ba-start)>>2]=1;
7172 gte_unneeded[(cinfo[i].ba-start)>>2]=gte_u_unknown;
7175 if (dops[i].is_ujump)
7177 // Unconditional branch
7178 u=unneeded_reg[(cinfo[i].ba-start)>>2];
7179 gte_u=gte_unneeded[(cinfo[i].ba-start)>>2];
7180 branch_unneeded_reg[i]=u;
7181 // Merge in delay slot
7182 u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
7183 u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7186 gte_u&=~gte_rs[i+1];
7188 // Conditional branch
7189 b=unneeded_reg[(cinfo[i].ba-start)>>2];
7190 gte_b=gte_unneeded[(cinfo[i].ba-start)>>2];
7191 branch_unneeded_reg[i]=b;
7192 // Branch delay slot
7193 b|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
7194 b&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7197 gte_b&=~gte_rs[i+1];
7201 branch_unneeded_reg[i]&=unneeded_reg[i+2];
7203 branch_unneeded_reg[i]=1;
7210 // Written registers are unneeded
7211 u|=1LL<<dops[i].rt1;
7212 u|=1LL<<dops[i].rt2;
7214 // Accessed registers are needed
7215 u&=~(1LL<<dops[i].rs1);
7216 u&=~(1LL<<dops[i].rs2);
7218 if(gte_rs[i]&&dops[i].rt1&&(unneeded_reg[i+1]&(1ll<<dops[i].rt1)))
7219 gte_u|=gte_rs[i]>e_unneeded[i+1]; // MFC2/CFC2 to dead register, unneeded
7220 if (dops[i].may_except || dops[i].itype == RFE)
7222 // SYSCALL instruction, etc or conditional exception
7225 // Source-target dependencies
7226 // R0 is always unneeded
7230 gte_unneeded[i]=gte_u;
7232 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
7235 for(r=1;r<=CCREG;r++) {
7236 if((unneeded_reg[i]>>r)&1) {
7237 if(r==HIREG) printf(" HI");
7238 else if(r==LOREG) printf(" LO");
7239 else printf(" r%d",r);
7247 static noinline void pass2a_unneeded_other(void)
7250 for (i = 0; i < slen; i++)
7252 // remove redundant alignment checks
7253 if (dops[i].may_except && (dops[i].is_load || dops[i].is_store)
7254 && dops[i].rt1 != dops[i].rs1 && !dops[i].is_ds)
7256 int base = dops[i].rs1, lsb = cinfo[i].imm, ls_type = dops[i].ls_type;
7257 int mask = ls_type == LS_32 ? 3 : 1;
7259 for (j = i + 1; j < slen; j++) {
7260 if (dops[j].bt || dops[j].is_jump)
7262 if ((dops[j].is_load || dops[j].is_store) && dops[j].rs1 == base
7263 && dops[j].ls_type == ls_type && (cinfo[j].imm & mask) == lsb)
7264 dops[j].may_except = 0;
7265 if (dops[j].rt1 == base)
7272 static noinline void pass3_register_alloc(u_int addr)
7274 struct regstat current; // Current register allocations/status
7275 clear_all_regs(current.regmap_entry);
7276 clear_all_regs(current.regmap);
7277 current.wasdirty = current.dirty = 0;
7278 current.u = unneeded_reg[0];
7279 alloc_reg(¤t, 0, CCREG);
7280 dirty_reg(¤t, CCREG);
7281 current.wasconst = 0;
7282 current.isconst = 0;
7283 current.loadedconst = 0;
7284 current.noevict = 0;
7285 //current.waswritten = 0;
7292 // First instruction is delay slot
7303 for(hr=0;hr<HOST_REGS;hr++)
7305 // Is this really necessary?
7306 if(current.regmap[hr]==0) current.regmap[hr]=-1;
7309 //current.waswritten=0;
7312 memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
7313 regs[i].wasconst=current.isconst;
7314 regs[i].wasdirty=current.dirty;
7318 regs[i].loadedconst=0;
7319 if (!dops[i].is_jump) {
7321 current.u=unneeded_reg[i+1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7328 current.u=branch_unneeded_reg[i]&~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7329 current.u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7332 SysPrintf("oops, branch at end of block with no delay slot @%08x\n", start + i*4);
7336 assert(dops[i].is_ds == ds);
7338 ds=0; // Skip delay slot, already allocated as part of branch
7339 // ...but we need to alloc it in case something jumps here
7341 current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
7343 current.u=branch_unneeded_reg[i-1];
7345 current.u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7347 struct regstat temp;
7348 memcpy(&temp,¤t,sizeof(current));
7349 temp.wasdirty=temp.dirty;
7350 // TODO: Take into account unconditional branches, as below
7351 delayslot_alloc(&temp,i);
7352 memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
7353 regs[i].wasdirty=temp.wasdirty;
7354 regs[i].dirty=temp.dirty;
7358 // Create entry (branch target) regmap
7359 for(hr=0;hr<HOST_REGS;hr++)
7361 int r=temp.regmap[hr];
7363 if(r!=regmap_pre[i][hr]) {
7364 regs[i].regmap_entry[hr]=-1;
7369 if((current.u>>r)&1) {
7370 regs[i].regmap_entry[hr]=-1;
7371 regs[i].regmap[hr]=-1;
7372 //Don't clear regs in the delay slot as the branch might need them
7373 //current.regmap[hr]=-1;
7375 regs[i].regmap_entry[hr]=r;
7378 // First instruction expects CCREG to be allocated
7379 if(i==0&&hr==HOST_CCREG)
7380 regs[i].regmap_entry[hr]=CCREG;
7382 regs[i].regmap_entry[hr]=-1;
7386 else { // Not delay slot
7387 current.noevict = 0;
7388 switch(dops[i].itype) {
7390 //current.isconst=0; // DEBUG
7391 //current.wasconst=0; // DEBUG
7392 //regs[i].wasconst=0; // DEBUG
7393 clear_const(¤t,dops[i].rt1);
7394 alloc_cc(¤t,i);
7395 dirty_reg(¤t,CCREG);
7396 if (dops[i].rt1==31) {
7397 alloc_reg(¤t,i,31);
7398 dirty_reg(¤t,31);
7399 //assert(dops[i+1].rs1!=31&&dops[i+1].rs2!=31);
7400 //assert(dops[i+1].rt1!=dops[i].rt1);
7402 alloc_reg(¤t,i,PTEMP);
7406 delayslot_alloc(¤t,i+1);
7407 //current.isconst=0; // DEBUG
7411 //current.isconst=0;
7412 //current.wasconst=0;
7413 //regs[i].wasconst=0;
7414 clear_const(¤t,dops[i].rs1);
7415 clear_const(¤t,dops[i].rt1);
7416 alloc_cc(¤t,i);
7417 dirty_reg(¤t,CCREG);
7418 if (!ds_writes_rjump_rs(i)) {
7419 alloc_reg(¤t,i,dops[i].rs1);
7420 if (dops[i].rt1!=0) {
7421 alloc_reg(¤t,i,dops[i].rt1);
7422 dirty_reg(¤t,dops[i].rt1);
7424 alloc_reg(¤t,i,PTEMP);
7428 if(dops[i].rs1==31) { // JALR
7429 alloc_reg(¤t,i,RHASH);
7430 alloc_reg(¤t,i,RHTBL);
7433 delayslot_alloc(¤t,i+1);
7435 // The delay slot overwrites our source register,
7436 // allocate a temporary register to hold the old value.
7440 delayslot_alloc(¤t,i+1);
7442 alloc_reg(¤t,i,RTEMP);
7444 //current.isconst=0; // DEBUG
7449 //current.isconst=0;
7450 //current.wasconst=0;
7451 //regs[i].wasconst=0;
7452 clear_const(¤t,dops[i].rs1);
7453 clear_const(¤t,dops[i].rs2);
7454 if((dops[i].opcode&0x3E)==4) // BEQ/BNE
7456 alloc_cc(¤t,i);
7457 dirty_reg(¤t,CCREG);
7458 if(dops[i].rs1) alloc_reg(¤t,i,dops[i].rs1);
7459 if(dops[i].rs2) alloc_reg(¤t,i,dops[i].rs2);
7460 if((dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2))||
7461 (dops[i].rs2&&(dops[i].rs2==dops[i+1].rt1||dops[i].rs2==dops[i+1].rt2))) {
7462 // The delay slot overwrites one of our conditions.
7463 // Allocate the branch condition registers instead.
7467 if(dops[i].rs1) alloc_reg(¤t,i,dops[i].rs1);
7468 if(dops[i].rs2) alloc_reg(¤t,i,dops[i].rs2);
7473 delayslot_alloc(¤t,i+1);
7477 if((dops[i].opcode&0x3E)==6) // BLEZ/BGTZ
7479 alloc_cc(¤t,i);
7480 dirty_reg(¤t,CCREG);
7481 alloc_reg(¤t,i,dops[i].rs1);
7482 if(dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2)) {
7483 // The delay slot overwrites one of our conditions.
7484 // Allocate the branch condition registers instead.
7488 if(dops[i].rs1) alloc_reg(¤t,i,dops[i].rs1);
7493 delayslot_alloc(¤t,i+1);
7497 // Don't alloc the delay slot yet because we might not execute it
7498 if((dops[i].opcode&0x3E)==0x14) // BEQL/BNEL
7503 alloc_cc(¤t,i);
7504 dirty_reg(¤t,CCREG);
7505 alloc_reg(¤t,i,dops[i].rs1);
7506 alloc_reg(¤t,i,dops[i].rs2);
7509 if((dops[i].opcode&0x3E)==0x16) // BLEZL/BGTZL
7514 alloc_cc(¤t,i);
7515 dirty_reg(¤t,CCREG);
7516 alloc_reg(¤t,i,dops[i].rs1);
7519 //current.isconst=0;
7522 clear_const(¤t,dops[i].rs1);
7523 clear_const(¤t,dops[i].rt1);
7525 alloc_cc(¤t,i);
7526 dirty_reg(¤t,CCREG);
7527 alloc_reg(¤t,i,dops[i].rs1);
7528 if (dops[i].rt1 == 31) { // BLTZAL/BGEZAL
7529 alloc_reg(¤t,i,31);
7530 dirty_reg(¤t,31);
7533 (dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2)) // The delay slot overwrites the branch condition.
7534 ||(dops[i].rt1 == 31 && dops[i].rs1 == 31) // overwrites it's own condition
7535 ||(dops[i].rt1==31&&(dops[i+1].rs1==31||dops[i+1].rs2==31||dops[i+1].rt1==31||dops[i+1].rt2==31))) { // DS touches $ra
7536 // Allocate the branch condition registers instead.
7540 if(dops[i].rs1) alloc_reg(¤t,i,dops[i].rs1);
7545 delayslot_alloc(¤t,i+1);
7549 //current.isconst=0;
7552 imm16_alloc(¤t,i);
7556 load_alloc(¤t,i);
7560 store_alloc(¤t,i);
7563 alu_alloc(¤t,i);
7566 shift_alloc(¤t,i);
7569 multdiv_alloc(¤t,i);
7572 shiftimm_alloc(¤t,i);
7575 mov_alloc(¤t,i);
7578 cop0_alloc(¤t,i);
7581 rfe_alloc(¤t,i);
7584 cop2_alloc(¤t,i);
7587 c2ls_alloc(¤t,i);
7590 c2op_alloc(¤t,i);
7595 syscall_alloc(¤t,i);
7599 // Create entry (branch target) regmap
7600 for(hr=0;hr<HOST_REGS;hr++)
7603 r=current.regmap[hr];
7605 if(r!=regmap_pre[i][hr]) {
7606 // TODO: delay slot (?)
7607 or=get_reg(regmap_pre[i],r); // Get old mapping for this register
7608 if(or<0||r>=TEMPREG){
7609 regs[i].regmap_entry[hr]=-1;
7613 // Just move it to a different register
7614 regs[i].regmap_entry[hr]=r;
7615 // If it was dirty before, it's still dirty
7616 if((regs[i].wasdirty>>or)&1) dirty_reg(¤t,r);
7623 regs[i].regmap_entry[hr]=0;
7628 if((current.u>>r)&1) {
7629 regs[i].regmap_entry[hr]=-1;
7630 //regs[i].regmap[hr]=-1;
7631 current.regmap[hr]=-1;
7633 regs[i].regmap_entry[hr]=r;
7637 // Branches expect CCREG to be allocated at the target
7638 if(regmap_pre[i][hr]==CCREG)
7639 regs[i].regmap_entry[hr]=CCREG;
7641 regs[i].regmap_entry[hr]=-1;
7644 memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
7647 #if 0 // see do_store_smc_check()
7648 if(i>0&&(dops[i-1].itype==STORE||dops[i-1].itype==STORELR||(dops[i-1].itype==C2LS&&dops[i-1].opcode==0x3a))&&(u_int)cinfo[i-1].imm<0x800)
7649 current.waswritten|=1<<dops[i-1].rs1;
7650 current.waswritten&=~(1<<dops[i].rt1);
7651 current.waswritten&=~(1<<dops[i].rt2);
7652 if((dops[i].itype==STORE||dops[i].itype==STORELR||(dops[i].itype==C2LS&&dops[i].opcode==0x3a))&&(u_int)cinfo[i].imm>=0x800)
7653 current.waswritten&=~(1<<dops[i].rs1);
7656 /* Branch post-alloc */
7659 current.wasdirty=current.dirty;
7660 switch(dops[i-1].itype) {
7662 memcpy(&branch_regs[i-1],¤t,sizeof(current));
7663 branch_regs[i-1].isconst=0;
7664 branch_regs[i-1].wasconst=0;
7665 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
7666 alloc_cc(&branch_regs[i-1],i-1);
7667 dirty_reg(&branch_regs[i-1],CCREG);
7668 if(dops[i-1].rt1==31) { // JAL
7669 alloc_reg(&branch_regs[i-1],i-1,31);
7670 dirty_reg(&branch_regs[i-1],31);
7672 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
7673 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
7676 memcpy(&branch_regs[i-1],¤t,sizeof(current));
7677 branch_regs[i-1].isconst=0;
7678 branch_regs[i-1].wasconst=0;
7679 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
7680 alloc_cc(&branch_regs[i-1],i-1);
7681 dirty_reg(&branch_regs[i-1],CCREG);
7682 alloc_reg(&branch_regs[i-1],i-1,dops[i-1].rs1);
7683 if(dops[i-1].rt1!=0) { // JALR
7684 alloc_reg(&branch_regs[i-1],i-1,dops[i-1].rt1);
7685 dirty_reg(&branch_regs[i-1],dops[i-1].rt1);
7688 if(dops[i-1].rs1==31) { // JALR
7689 alloc_reg(&branch_regs[i-1],i-1,RHASH);
7690 alloc_reg(&branch_regs[i-1],i-1,RHTBL);
7693 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
7694 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
7697 if((dops[i-1].opcode&0x3E)==4) // BEQ/BNE
7699 alloc_cc(¤t,i-1);
7700 dirty_reg(¤t,CCREG);
7701 if((dops[i-1].rs1&&(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2))||
7702 (dops[i-1].rs2&&(dops[i-1].rs2==dops[i].rt1||dops[i-1].rs2==dops[i].rt2))) {
7703 // The delay slot overwrote one of our conditions
7704 // Delay slot goes after the test (in order)
7705 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7707 delayslot_alloc(¤t,i);
7712 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
7713 // Alloc the branch condition registers
7714 if(dops[i-1].rs1) alloc_reg(¤t,i-1,dops[i-1].rs1);
7715 if(dops[i-1].rs2) alloc_reg(¤t,i-1,dops[i-1].rs2);
7717 memcpy(&branch_regs[i-1],¤t,sizeof(current));
7718 branch_regs[i-1].isconst=0;
7719 branch_regs[i-1].wasconst=0;
7720 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
7721 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
7724 if((dops[i-1].opcode&0x3E)==6) // BLEZ/BGTZ
7726 alloc_cc(¤t,i-1);
7727 dirty_reg(¤t,CCREG);
7728 if(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2) {
7729 // The delay slot overwrote the branch condition
7730 // Delay slot goes after the test (in order)
7731 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7733 delayslot_alloc(¤t,i);
7738 current.u=branch_unneeded_reg[i-1]&~(1LL<<dops[i-1].rs1);
7739 // Alloc the branch condition register
7740 alloc_reg(¤t,i-1,dops[i-1].rs1);
7742 memcpy(&branch_regs[i-1],¤t,sizeof(current));
7743 branch_regs[i-1].isconst=0;
7744 branch_regs[i-1].wasconst=0;
7745 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
7746 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
7751 alloc_cc(¤t,i-1);
7752 dirty_reg(¤t,CCREG);
7753 if(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2) {
7754 // The delay slot overwrote the branch condition
7755 // Delay slot goes after the test (in order)
7756 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7758 delayslot_alloc(¤t,i);
7763 current.u=branch_unneeded_reg[i-1]&~(1LL<<dops[i-1].rs1);
7764 // Alloc the branch condition register
7765 alloc_reg(¤t,i-1,dops[i-1].rs1);
7767 memcpy(&branch_regs[i-1],¤t,sizeof(current));
7768 branch_regs[i-1].isconst=0;
7769 branch_regs[i-1].wasconst=0;
7770 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
7771 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
7776 if (dops[i-1].is_ujump)
7778 if(dops[i-1].rt1==31) // JAL/JALR
7780 // Subroutine call will return here, don't alloc any registers
7782 clear_all_regs(current.regmap);
7783 alloc_reg(¤t,i,CCREG);
7784 dirty_reg(¤t,CCREG);
7788 // Internal branch will jump here, match registers to caller
7790 clear_all_regs(current.regmap);
7791 alloc_reg(¤t,i,CCREG);
7792 dirty_reg(¤t,CCREG);
7795 if(cinfo[j].ba==start+i*4+4) {
7796 memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
7797 current.dirty=branch_regs[j].dirty;
7802 if(cinfo[j].ba==start+i*4+4) {
7803 for(hr=0;hr<HOST_REGS;hr++) {
7804 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
7805 current.regmap[hr]=-1;
7807 current.dirty&=branch_regs[j].dirty;
7816 // Count cycles in between branches
7817 cinfo[i].ccadj = CLOCK_ADJUST(cc);
7818 if (i > 0 && (dops[i-1].is_jump || dops[i].is_exception))
7822 #if !defined(DRC_DBG)
7823 else if(dops[i].itype==C2OP&>e_cycletab[source[i]&0x3f]>2)
7825 // this should really be removed since the real stalls have been implemented,
7826 // but doing so causes sizeable perf regression against the older version
7827 u_int gtec = gte_cycletab[source[i] & 0x3f];
7828 cc += HACK_ENABLED(NDHACK_NO_STALLS) ? gtec/2 : 2;
7830 else if(i>1&&dops[i].itype==STORE&&dops[i-1].itype==STORE&&dops[i-2].itype==STORE&&!dops[i].bt)
7834 else if(dops[i].itype==C2LS)
7836 // same as with C2OP
7837 cc += HACK_ENABLED(NDHACK_NO_STALLS) ? 4 : 2;
7845 if(!dops[i].is_ds) {
7846 regs[i].dirty=current.dirty;
7847 regs[i].isconst=current.isconst;
7848 memcpy(constmap[i],current_constmap,sizeof(constmap[i]));
7850 for(hr=0;hr<HOST_REGS;hr++) {
7851 if(hr!=EXCLUDE_REG&®s[i].regmap[hr]>=0) {
7852 if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
7853 regs[i].wasconst&=~(1<<hr);
7857 //regs[i].waswritten=current.waswritten;
7861 static noinline void pass4_cull_unused_regs(void)
7863 u_int last_needed_regs[4] = {0,0,0,0};
7867 for (i=slen-1;i>=0;i--)
7870 __builtin_prefetch(regs[i-2].regmap);
7873 if(cinfo[i].ba<start || cinfo[i].ba>=(start+slen*4))
7875 // Branch out of this block, don't need anything
7881 // Need whatever matches the target
7883 int t=(cinfo[i].ba-start)>>2;
7884 for(hr=0;hr<HOST_REGS;hr++)
7886 if(regs[i].regmap_entry[hr]>=0) {
7887 if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
7891 // Conditional branch may need registers for following instructions
7892 if (!dops[i].is_ujump)
7895 nr |= last_needed_regs[(i+2) & 3];
7896 for(hr=0;hr<HOST_REGS;hr++)
7898 if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
7899 //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
7903 // Don't need stuff which is overwritten
7904 //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
7905 //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
7906 // Merge in delay slot
7907 if (dops[i+1].rt1) nr &= ~get_regm(regs[i].regmap, dops[i+1].rt1);
7908 if (dops[i+1].rt2) nr &= ~get_regm(regs[i].regmap, dops[i+1].rt2);
7909 nr |= get_regm(regmap_pre[i], dops[i+1].rs1);
7910 nr |= get_regm(regmap_pre[i], dops[i+1].rs2);
7911 nr |= get_regm(regs[i].regmap_entry, dops[i+1].rs1);
7912 nr |= get_regm(regs[i].regmap_entry, dops[i+1].rs2);
7913 if (ram_offset && (dops[i+1].is_load || dops[i+1].is_store)) {
7914 nr |= get_regm(regmap_pre[i], ROREG);
7915 nr |= get_regm(regs[i].regmap_entry, ROREG);
7917 if (dops[i+1].is_store) {
7918 nr |= get_regm(regmap_pre[i], INVCP);
7919 nr |= get_regm(regs[i].regmap_entry, INVCP);
7922 else if (dops[i].is_exception)
7924 // SYSCALL instruction, etc
7930 for(hr=0;hr<HOST_REGS;hr++) {
7931 if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
7932 if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
7933 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
7934 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
7938 // Overwritten registers are not needed
7939 if (dops[i].rt1) nr &= ~get_regm(regs[i].regmap, dops[i].rt1);
7940 if (dops[i].rt2) nr &= ~get_regm(regs[i].regmap, dops[i].rt2);
7941 nr &= ~get_regm(regs[i].regmap, FTEMP);
7942 // Source registers are needed
7943 nr |= get_regm(regmap_pre[i], dops[i].rs1);
7944 nr |= get_regm(regmap_pre[i], dops[i].rs2);
7945 nr |= get_regm(regs[i].regmap_entry, dops[i].rs1);
7946 nr |= get_regm(regs[i].regmap_entry, dops[i].rs2);
7947 if (ram_offset && (dops[i].is_load || dops[i].is_store)) {
7948 nr |= get_regm(regmap_pre[i], ROREG);
7949 nr |= get_regm(regs[i].regmap_entry, ROREG);
7951 if (dops[i].is_store) {
7952 nr |= get_regm(regmap_pre[i], INVCP);
7953 nr |= get_regm(regs[i].regmap_entry, INVCP);
7956 if (i > 0 && !dops[i].bt && regs[i].wasdirty)
7957 for(hr=0;hr<HOST_REGS;hr++)
7959 // Don't store a register immediately after writing it,
7960 // may prevent dual-issue.
7961 // But do so if this is a branch target, otherwise we
7962 // might have to load the register before the branch.
7963 if((regs[i].wasdirty>>hr)&1) {
7964 if((regmap_pre[i][hr]>0&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1))) {
7965 if(dops[i-1].rt1==regmap_pre[i][hr]) nr|=1<<hr;
7966 if(dops[i-1].rt2==regmap_pre[i][hr]) nr|=1<<hr;
7968 if((regs[i].regmap_entry[hr]>0&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1))) {
7969 if(dops[i-1].rt1==regs[i].regmap_entry[hr]) nr|=1<<hr;
7970 if(dops[i-1].rt2==regs[i].regmap_entry[hr]) nr|=1<<hr;
7974 // Cycle count is needed at branches. Assume it is needed at the target too.
7975 if (i == 0 || dops[i].bt || dops[i].may_except || dops[i].itype == CJUMP) {
7976 if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
7977 if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
7980 last_needed_regs[i & 3] = nr;
7982 // Deallocate unneeded registers
7983 for(hr=0;hr<HOST_REGS;hr++)
7986 if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
7989 int map1 = 0, map2 = 0, temp = 0; // or -1 ??
7990 if (dops[i+1].is_load || dops[i+1].is_store)
7992 if (dops[i+1].is_store)
7994 if(dops[i+1].itype==LOADLR || dops[i+1].itype==STORELR || dops[i+1].itype==C2LS)
7996 if(regs[i].regmap[hr]!=dops[i].rs1 && regs[i].regmap[hr]!=dops[i].rs2 &&
7997 regs[i].regmap[hr]!=dops[i].rt1 && regs[i].regmap[hr]!=dops[i].rt2 &&
7998 regs[i].regmap[hr]!=dops[i+1].rt1 && regs[i].regmap[hr]!=dops[i+1].rt2 &&
7999 regs[i].regmap[hr]!=dops[i+1].rs1 && regs[i].regmap[hr]!=dops[i+1].rs2 &&
8000 regs[i].regmap[hr]!=temp && regs[i].regmap[hr]!=PTEMP &&
8001 regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
8002 regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
8003 regs[i].regmap[hr]!=map1 && regs[i].regmap[hr]!=map2)
8005 regs[i].regmap[hr]=-1;
8006 regs[i].isconst&=~(1<<hr);
8007 regs[i].dirty&=~(1<<hr);
8008 regs[i+1].wasdirty&=~(1<<hr);
8009 if(branch_regs[i].regmap[hr]!=dops[i].rs1 && branch_regs[i].regmap[hr]!=dops[i].rs2 &&
8010 branch_regs[i].regmap[hr]!=dops[i].rt1 && branch_regs[i].regmap[hr]!=dops[i].rt2 &&
8011 branch_regs[i].regmap[hr]!=dops[i+1].rt1 && branch_regs[i].regmap[hr]!=dops[i+1].rt2 &&
8012 branch_regs[i].regmap[hr]!=dops[i+1].rs1 && branch_regs[i].regmap[hr]!=dops[i+1].rs2 &&
8013 branch_regs[i].regmap[hr]!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
8014 branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
8015 branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
8016 branch_regs[i].regmap[hr]!=map1 && branch_regs[i].regmap[hr]!=map2)
8018 branch_regs[i].regmap[hr]=-1;
8019 branch_regs[i].regmap_entry[hr]=-1;
8020 if (!dops[i].is_ujump)
8023 regmap_pre[i+2][hr]=-1;
8024 regs[i+2].wasconst&=~(1<<hr);
8035 int map1 = -1, map2 = -1, temp=-1;
8036 if (dops[i].is_load || dops[i].is_store)
8038 if (dops[i].is_store)
8040 if (dops[i].itype==LOADLR || dops[i].itype==STORELR || dops[i].itype==C2LS)
8042 if(regs[i].regmap[hr]!=dops[i].rt1 && regs[i].regmap[hr]!=dops[i].rt2 &&
8043 regs[i].regmap[hr]!=dops[i].rs1 && regs[i].regmap[hr]!=dops[i].rs2 &&
8044 regs[i].regmap[hr]!=temp && regs[i].regmap[hr]!=map1 && regs[i].regmap[hr]!=map2 &&
8045 //(dops[i].itype!=SPAN||regs[i].regmap[hr]!=CCREG)
8046 regs[i].regmap[hr] != CCREG)
8048 if(i<slen-1&&!dops[i].is_ds) {
8049 assert(regs[i].regmap[hr]<64);
8050 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]>0)
8051 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
8053 SysPrintf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
8054 assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
8056 regmap_pre[i+1][hr]=-1;
8057 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
8058 regs[i+1].wasconst&=~(1<<hr);
8060 regs[i].regmap[hr]=-1;
8061 regs[i].isconst&=~(1<<hr);
8062 regs[i].dirty&=~(1<<hr);
8063 regs[i+1].wasdirty&=~(1<<hr);
8072 // If a register is allocated during a loop, try to allocate it for the
8073 // entire loop, if possible. This avoids loading/storing registers
8074 // inside of the loop.
8075 static noinline void pass5a_preallocate1(void)
8078 signed char f_regmap[HOST_REGS];
8079 clear_all_regs(f_regmap);
8080 for(i=0;i<slen-1;i++)
8082 if(dops[i].itype==UJUMP||dops[i].itype==CJUMP||dops[i].itype==SJUMP)
8084 if(cinfo[i].ba>=start && cinfo[i].ba<(start+i*4))
8085 if(dops[i+1].itype==NOP||dops[i+1].itype==MOV||dops[i+1].itype==ALU
8086 ||dops[i+1].itype==SHIFTIMM||dops[i+1].itype==IMM16||dops[i+1].itype==LOAD
8087 ||dops[i+1].itype==STORE||dops[i+1].itype==STORELR
8088 ||dops[i+1].itype==SHIFT
8089 ||dops[i+1].itype==COP2||dops[i+1].itype==C2LS||dops[i+1].itype==C2OP)
8091 int t=(cinfo[i].ba-start)>>2;
8092 if(t > 0 && !dops[t-1].is_jump) // loop_preload can't handle jumps into delay slots
8093 if(t<2||(dops[t-2].itype!=UJUMP&&dops[t-2].itype!=RJUMP)||dops[t-2].rt1!=31) // call/ret assumes no registers allocated
8094 for(hr=0;hr<HOST_REGS;hr++)
8096 if(regs[i].regmap[hr]>=0) {
8097 if(f_regmap[hr]!=regs[i].regmap[hr]) {
8098 // dealloc old register
8100 for(n=0;n<HOST_REGS;n++)
8102 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
8104 // and alloc new one
8105 f_regmap[hr]=regs[i].regmap[hr];
8108 if(branch_regs[i].regmap[hr]>=0) {
8109 if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
8110 // dealloc old register
8112 for(n=0;n<HOST_REGS;n++)
8114 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
8116 // and alloc new one
8117 f_regmap[hr]=branch_regs[i].regmap[hr];
8121 if(count_free_regs(regs[i].regmap)<=cinfo[i+1].min_free_regs)
8122 f_regmap[hr]=branch_regs[i].regmap[hr];
8124 if(count_free_regs(branch_regs[i].regmap)<=cinfo[i+1].min_free_regs)
8125 f_regmap[hr]=branch_regs[i].regmap[hr];
8127 // Avoid dirty->clean transition
8128 #ifdef DESTRUCTIVE_WRITEBACK
8129 if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
8131 // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
8132 // case above, however it's always a good idea. We can't hoist the
8133 // load if the register was already allocated, so there's no point
8134 // wasting time analyzing most of these cases. It only "succeeds"
8135 // when the mapping was different and the load can be replaced with
8136 // a mov, which is of negligible benefit. So such cases are
8138 if(f_regmap[hr]>0) {
8139 if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
8143 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,cinfo[i].ba,start+j*4,hr,r);
8144 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
8146 if(regs[j].regmap[hr]==f_regmap[hr]&&f_regmap[hr]<TEMPREG) {
8147 //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,cinfo[i].ba,start+j*4,hr,r);
8149 if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
8150 if(get_reg(regs[i].regmap,f_regmap[hr])>=0) break;
8151 if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
8153 while(k>1&®s[k-1].regmap[hr]==-1) {
8154 if(count_free_regs(regs[k-1].regmap)<=cinfo[k-1].min_free_regs) {
8155 //printf("no free regs for store %x\n",start+(k-1)*4);
8158 if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
8159 //printf("no-match due to different register\n");
8162 if (dops[k-2].is_jump) {
8163 //printf("no-match due to branch\n");
8166 // call/ret fast path assumes no registers allocated
8167 if(k>2&&(dops[k-3].itype==UJUMP||dops[k-3].itype==RJUMP)&&dops[k-3].rt1==31) {
8172 if(regs[k-1].regmap[hr]==f_regmap[hr]&®map_pre[k][hr]==f_regmap[hr]) {
8173 //printf("Extend r%d, %x ->\n",hr,start+k*4);
8175 regs[k].regmap_entry[hr]=f_regmap[hr];
8176 regs[k].regmap[hr]=f_regmap[hr];
8177 regmap_pre[k+1][hr]=f_regmap[hr];
8178 regs[k].wasdirty&=~(1<<hr);
8179 regs[k].dirty&=~(1<<hr);
8180 regs[k].wasdirty|=(1<<hr)®s[k-1].dirty;
8181 regs[k].dirty|=(1<<hr)®s[k].wasdirty;
8182 regs[k].wasconst&=~(1<<hr);
8183 regs[k].isconst&=~(1<<hr);
8188 //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
8191 assert(regs[i-1].regmap[hr]==f_regmap[hr]);
8192 if(regs[i-1].regmap[hr]==f_regmap[hr]&®map_pre[i][hr]==f_regmap[hr]) {
8193 //printf("OK fill %x (r%d)\n",start+i*4,hr);
8194 regs[i].regmap_entry[hr]=f_regmap[hr];
8195 regs[i].regmap[hr]=f_regmap[hr];
8196 regs[i].wasdirty&=~(1<<hr);
8197 regs[i].dirty&=~(1<<hr);
8198 regs[i].wasdirty|=(1<<hr)®s[i-1].dirty;
8199 regs[i].dirty|=(1<<hr)®s[i-1].dirty;
8200 regs[i].wasconst&=~(1<<hr);
8201 regs[i].isconst&=~(1<<hr);
8202 branch_regs[i].regmap_entry[hr]=f_regmap[hr];
8203 branch_regs[i].wasdirty&=~(1<<hr);
8204 branch_regs[i].wasdirty|=(1<<hr)®s[i].dirty;
8205 branch_regs[i].regmap[hr]=f_regmap[hr];
8206 branch_regs[i].dirty&=~(1<<hr);
8207 branch_regs[i].dirty|=(1<<hr)®s[i].dirty;
8208 branch_regs[i].wasconst&=~(1<<hr);
8209 branch_regs[i].isconst&=~(1<<hr);
8210 if (!dops[i].is_ujump) {
8211 regmap_pre[i+2][hr]=f_regmap[hr];
8212 regs[i+2].wasdirty&=~(1<<hr);
8213 regs[i+2].wasdirty|=(1<<hr)®s[i].dirty;
8218 // Alloc register clean at beginning of loop,
8219 // but may dirty it in pass 6
8220 regs[k].regmap_entry[hr]=f_regmap[hr];
8221 regs[k].regmap[hr]=f_regmap[hr];
8222 regs[k].dirty&=~(1<<hr);
8223 regs[k].wasconst&=~(1<<hr);
8224 regs[k].isconst&=~(1<<hr);
8225 if (dops[k].is_jump) {
8226 branch_regs[k].regmap_entry[hr]=f_regmap[hr];
8227 branch_regs[k].regmap[hr]=f_regmap[hr];
8228 branch_regs[k].dirty&=~(1<<hr);
8229 branch_regs[k].wasconst&=~(1<<hr);
8230 branch_regs[k].isconst&=~(1<<hr);
8231 if (!dops[k].is_ujump) {
8232 regmap_pre[k+2][hr]=f_regmap[hr];
8233 regs[k+2].wasdirty&=~(1<<hr);
8238 regmap_pre[k+1][hr]=f_regmap[hr];
8239 regs[k+1].wasdirty&=~(1<<hr);
8242 if(regs[j].regmap[hr]==f_regmap[hr])
8243 regs[j].regmap_entry[hr]=f_regmap[hr];
8247 if(regs[j].regmap[hr]>=0)
8249 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
8250 //printf("no-match due to different register\n");
8253 if (dops[j].is_ujump)
8255 // Stop on unconditional branch
8258 if(dops[j].itype==CJUMP||dops[j].itype==SJUMP)
8261 if(count_free_regs(regs[j].regmap)<=cinfo[j+1].min_free_regs)
8264 if(count_free_regs(branch_regs[j].regmap)<=cinfo[j+1].min_free_regs)
8267 if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
8268 //printf("no-match due to different register (branch)\n");
8272 if(count_free_regs(regs[j].regmap)<=cinfo[j].min_free_regs) {
8273 //printf("No free regs for store %x\n",start+j*4);
8276 assert(f_regmap[hr]<64);
8283 // Non branch or undetermined branch target
8284 for(hr=0;hr<HOST_REGS;hr++)
8286 if(hr!=EXCLUDE_REG) {
8287 if(regs[i].regmap[hr]>=0) {
8288 if(f_regmap[hr]!=regs[i].regmap[hr]) {
8289 // dealloc old register
8291 for(n=0;n<HOST_REGS;n++)
8293 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
8295 // and alloc new one
8296 f_regmap[hr]=regs[i].regmap[hr];
8301 // Try to restore cycle count at branch targets
8303 for(j=i;j<slen-1;j++) {
8304 if(regs[j].regmap[HOST_CCREG]!=-1) break;
8305 if(count_free_regs(regs[j].regmap)<=cinfo[j].min_free_regs) {
8306 //printf("no free regs for store %x\n",start+j*4);
8310 if(regs[j].regmap[HOST_CCREG]==CCREG) {
8312 //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
8314 regs[k].regmap_entry[HOST_CCREG]=CCREG;
8315 regs[k].regmap[HOST_CCREG]=CCREG;
8316 regmap_pre[k+1][HOST_CCREG]=CCREG;
8317 regs[k+1].wasdirty|=1<<HOST_CCREG;
8318 regs[k].dirty|=1<<HOST_CCREG;
8319 regs[k].wasconst&=~(1<<HOST_CCREG);
8320 regs[k].isconst&=~(1<<HOST_CCREG);
8323 regs[j].regmap_entry[HOST_CCREG]=CCREG;
8325 // Work backwards from the branch target
8326 if(j>i&&f_regmap[HOST_CCREG]==CCREG)
8328 //printf("Extend backwards\n");
8331 while(regs[k-1].regmap[HOST_CCREG]==-1) {
8332 if(count_free_regs(regs[k-1].regmap)<=cinfo[k-1].min_free_regs) {
8333 //printf("no free regs for store %x\n",start+(k-1)*4);
8338 if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
8339 //printf("Extend CC, %x ->\n",start+k*4);
8341 regs[k].regmap_entry[HOST_CCREG]=CCREG;
8342 regs[k].regmap[HOST_CCREG]=CCREG;
8343 regmap_pre[k+1][HOST_CCREG]=CCREG;
8344 regs[k+1].wasdirty|=1<<HOST_CCREG;
8345 regs[k].dirty|=1<<HOST_CCREG;
8346 regs[k].wasconst&=~(1<<HOST_CCREG);
8347 regs[k].isconst&=~(1<<HOST_CCREG);
8352 //printf("Fail Extend CC, %x ->\n",start+k*4);
8356 if(dops[i].itype!=STORE&&dops[i].itype!=STORELR&&dops[i].itype!=SHIFT&&
8357 dops[i].itype!=NOP&&dops[i].itype!=MOV&&dops[i].itype!=ALU&&dops[i].itype!=SHIFTIMM&&
8358 dops[i].itype!=IMM16&&dops[i].itype!=LOAD)
8360 memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
8366 // This allocates registers (if possible) one instruction prior
8367 // to use, which can avoid a load-use penalty on certain CPUs.
8368 static noinline void pass5b_preallocate2(void)
8371 for(i=0;i<slen-1;i++)
8373 if (!i || !dops[i-1].is_jump)
8377 int j, can_steal = 1;
8378 for (j = i; j < i + 2; j++) {
8380 if (cinfo[j].min_free_regs == 0)
8382 for (hr = 0; hr < HOST_REGS; hr++)
8383 if (hr != EXCLUDE_REG && regs[j].regmap[hr] < 0)
8385 if (free_regs <= cinfo[j].min_free_regs) {
8392 if(dops[i].itype==ALU||dops[i].itype==MOV||dops[i].itype==LOAD||dops[i].itype==SHIFTIMM||dops[i].itype==IMM16
8393 ||(dops[i].itype==COP2&&dops[i].opcode2<3))
8396 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rs1))>=0)
8398 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
8400 regs[i].regmap[hr]=regs[i+1].regmap[hr];
8401 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
8402 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
8403 regs[i].isconst&=~(1<<hr);
8404 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8405 constmap[i][hr]=constmap[i+1][hr];
8406 regs[i+1].wasdirty&=~(1<<hr);
8407 regs[i].dirty&=~(1<<hr);
8412 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rs2))>=0)
8414 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
8416 regs[i].regmap[hr]=regs[i+1].regmap[hr];
8417 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
8418 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
8419 regs[i].isconst&=~(1<<hr);
8420 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8421 constmap[i][hr]=constmap[i+1][hr];
8422 regs[i+1].wasdirty&=~(1<<hr);
8423 regs[i].dirty&=~(1<<hr);
8427 // Preload target address for load instruction (non-constant)
8428 if(dops[i+1].itype==LOAD&&dops[i+1].rs1&&get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8429 if((hr=get_reg_w(regs[i+1].regmap, dops[i+1].rt1))>=0)
8431 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
8433 regs[i].regmap[hr]=dops[i+1].rs1;
8434 regmap_pre[i+1][hr]=dops[i+1].rs1;
8435 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8436 regs[i].isconst&=~(1<<hr);
8437 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8438 constmap[i][hr]=constmap[i+1][hr];
8439 regs[i+1].wasdirty&=~(1<<hr);
8440 regs[i].dirty&=~(1<<hr);
8444 // Load source into target register
8445 if(dops[i+1].use_lt1&&get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8446 if((hr=get_reg_w(regs[i+1].regmap, dops[i+1].rt1))>=0)
8448 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
8450 regs[i].regmap[hr]=dops[i+1].rs1;
8451 regmap_pre[i+1][hr]=dops[i+1].rs1;
8452 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8453 regs[i].isconst&=~(1<<hr);
8454 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8455 constmap[i][hr]=constmap[i+1][hr];
8456 regs[i+1].wasdirty&=~(1<<hr);
8457 regs[i].dirty&=~(1<<hr);
8461 // Address for store instruction (non-constant)
8462 if (dops[i+1].is_store) { // SB/SH/SW/SWC2
8463 if(get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8464 hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
8465 if(hr<0) hr=get_reg_temp(regs[i+1].regmap);
8467 regs[i+1].regmap[hr]=AGEN1+((i+1)&1);
8468 regs[i+1].isconst&=~(1<<hr);
8469 regs[i+1].dirty&=~(1<<hr);
8470 regs[i+2].wasdirty&=~(1<<hr);
8473 #if 0 // what is this for? double allocs $0 in ps1_rom.bin
8474 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
8476 regs[i].regmap[hr]=dops[i+1].rs1;
8477 regmap_pre[i+1][hr]=dops[i+1].rs1;
8478 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8479 regs[i].isconst&=~(1<<hr);
8480 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8481 constmap[i][hr]=constmap[i+1][hr];
8482 regs[i+1].wasdirty&=~(1<<hr);
8483 regs[i].dirty&=~(1<<hr);
8488 if (dops[i+1].itype == LOADLR || dops[i+1].opcode == 0x32) { // LWC2
8489 if(get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8491 hr=get_reg(regs[i+1].regmap,FTEMP);
8493 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
8495 regs[i].regmap[hr]=dops[i+1].rs1;
8496 regmap_pre[i+1][hr]=dops[i+1].rs1;
8497 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8498 regs[i].isconst&=~(1<<hr);
8499 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8500 constmap[i][hr]=constmap[i+1][hr];
8501 regs[i+1].wasdirty&=~(1<<hr);
8502 regs[i].dirty&=~(1<<hr);
8504 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
8506 // move it to another register
8507 regs[i+1].regmap[hr]=-1;
8508 regmap_pre[i+2][hr]=-1;
8509 regs[i+1].regmap[nr]=FTEMP;
8510 regmap_pre[i+2][nr]=FTEMP;
8511 regs[i].regmap[nr]=dops[i+1].rs1;
8512 regmap_pre[i+1][nr]=dops[i+1].rs1;
8513 regs[i+1].regmap_entry[nr]=dops[i+1].rs1;
8514 regs[i].isconst&=~(1<<nr);
8515 regs[i+1].isconst&=~(1<<nr);
8516 regs[i].dirty&=~(1<<nr);
8517 regs[i+1].wasdirty&=~(1<<nr);
8518 regs[i+1].dirty&=~(1<<nr);
8519 regs[i+2].wasdirty&=~(1<<nr);
8523 if(dops[i+1].itype==LOAD||dops[i+1].itype==LOADLR||dops[i+1].itype==STORE||dops[i+1].itype==STORELR/*||dops[i+1].itype==C2LS*/) {
8525 if(dops[i+1].itype==LOAD)
8526 hr=get_reg_w(regs[i+1].regmap, dops[i+1].rt1);
8527 if (dops[i+1].itype == LOADLR || dops[i+1].opcode == 0x32) // LWC2
8528 hr=get_reg(regs[i+1].regmap,FTEMP);
8529 if (dops[i+1].is_store) {
8530 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
8531 if(hr<0) hr=get_reg_temp(regs[i+1].regmap);
8533 if(hr>=0&®s[i].regmap[hr]<0) {
8534 int rs=get_reg(regs[i+1].regmap,dops[i+1].rs1);
8535 if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
8536 regs[i].regmap[hr]=AGEN1+((i+1)&1);
8537 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
8538 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
8539 regs[i].isconst&=~(1<<hr);
8540 regs[i+1].wasdirty&=~(1<<hr);
8541 regs[i].dirty&=~(1<<hr);
8551 // Write back dirty registers as soon as we will no longer modify them,
8552 // so that we don't end up with lots of writes at the branches.
8553 static noinline void pass6_clean_registers(int istart, int iend, int wr)
8555 static u_int wont_dirty[MAXBLOCK];
8556 static u_int will_dirty[MAXBLOCK];
8559 u_int will_dirty_i,will_dirty_next,temp_will_dirty;
8560 u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
8562 will_dirty_i=will_dirty_next=0;
8563 wont_dirty_i=wont_dirty_next=0;
8565 will_dirty_i=will_dirty_next=will_dirty[iend+1];
8566 wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
8568 for (i=iend;i>=istart;i--)
8570 signed char rregmap_i[RRMAP_SIZE];
8571 u_int hr_candirty = 0;
8572 assert(HOST_REGS < 32);
8573 make_rregs(regs[i].regmap, rregmap_i, &hr_candirty);
8574 __builtin_prefetch(regs[i-1].regmap);
8577 signed char branch_rregmap_i[RRMAP_SIZE];
8578 u_int branch_hr_candirty = 0;
8579 make_rregs(branch_regs[i].regmap, branch_rregmap_i, &branch_hr_candirty);
8580 if(cinfo[i].ba<start || cinfo[i].ba>=(start+slen*4))
8582 // Branch out of this block, flush all regs
8584 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8585 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8586 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8587 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8588 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8589 will_dirty_i &= branch_hr_candirty;
8590 if (dops[i].is_ujump)
8592 // Unconditional branch
8594 // Merge in delay slot (will dirty)
8595 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8596 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8597 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8598 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8599 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8600 will_dirty_i &= hr_candirty;
8604 // Conditional branch
8605 wont_dirty_i = wont_dirty_next;
8606 // Merge in delay slot (will dirty)
8607 // (the original code had no explanation why these 2 are commented out)
8608 //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8609 //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8610 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8611 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8612 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8613 will_dirty_i &= hr_candirty;
8615 // Merge in delay slot (wont dirty)
8616 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8617 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8618 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8619 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8620 wont_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8621 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8622 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8623 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8624 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8625 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8626 wont_dirty_i &= ~(1u << 31);
8628 #ifndef DESTRUCTIVE_WRITEBACK
8629 branch_regs[i].dirty&=wont_dirty_i;
8631 branch_regs[i].dirty|=will_dirty_i;
8637 if(cinfo[i].ba<=start+i*4) {
8639 if (dops[i].is_ujump)
8641 // Unconditional branch
8644 // Merge in delay slot (will dirty)
8645 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8646 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8647 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8648 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8649 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8650 temp_will_dirty &= branch_hr_candirty;
8651 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8652 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8653 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8654 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8655 temp_will_dirty |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8656 temp_will_dirty &= hr_candirty;
8658 // Conditional branch (not taken case)
8659 temp_will_dirty=will_dirty_next;
8660 temp_wont_dirty=wont_dirty_next;
8661 // Merge in delay slot (will dirty)
8662 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8663 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8664 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8665 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8666 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8667 temp_will_dirty &= branch_hr_candirty;
8668 //temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8669 //temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8670 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8671 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8672 temp_will_dirty |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8673 temp_will_dirty &= hr_candirty;
8675 // Merge in delay slot (wont dirty)
8676 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8677 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8678 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8679 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8680 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8681 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8682 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8683 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8684 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8685 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8686 temp_wont_dirty &= ~(1u << 31);
8687 // Deal with changed mappings
8689 for(r=0;r<HOST_REGS;r++) {
8690 if(r!=EXCLUDE_REG) {
8691 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
8692 temp_will_dirty&=~(1<<r);
8693 temp_wont_dirty&=~(1<<r);
8694 if(regmap_pre[i][r]>0 && regmap_pre[i][r]<34) {
8695 temp_will_dirty|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r;
8696 temp_wont_dirty|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r;
8698 temp_will_dirty|=1<<r;
8699 temp_wont_dirty|=1<<r;
8706 will_dirty[i]=temp_will_dirty;
8707 wont_dirty[i]=temp_wont_dirty;
8708 pass6_clean_registers((cinfo[i].ba-start)>>2,i-1,0);
8710 // Limit recursion. It can take an excessive amount
8711 // of time if there are a lot of nested loops.
8712 will_dirty[(cinfo[i].ba-start)>>2]=0;
8713 wont_dirty[(cinfo[i].ba-start)>>2]=-1;
8718 if (dops[i].is_ujump)
8720 // Unconditional branch
8723 //if(cinfo[i].ba>start+i*4) { // Disable recursion (for debugging)
8724 for(r=0;r<HOST_REGS;r++) {
8725 if(r!=EXCLUDE_REG) {
8726 if(branch_regs[i].regmap[r]==regs[(cinfo[i].ba-start)>>2].regmap_entry[r]) {
8727 will_dirty_i|=will_dirty[(cinfo[i].ba-start)>>2]&(1<<r);
8728 wont_dirty_i|=wont_dirty[(cinfo[i].ba-start)>>2]&(1<<r);
8730 if(branch_regs[i].regmap[r]>=0) {
8731 will_dirty_i|=((unneeded_reg[(cinfo[i].ba-start)>>2]>>branch_regs[i].regmap[r])&1)<<r;
8732 wont_dirty_i|=((unneeded_reg[(cinfo[i].ba-start)>>2]>>branch_regs[i].regmap[r])&1)<<r;
8737 // Merge in delay slot
8738 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8739 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8740 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8741 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8742 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8743 will_dirty_i &= branch_hr_candirty;
8744 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8745 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8746 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8747 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8748 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8749 will_dirty_i &= hr_candirty;
8751 // Conditional branch
8752 will_dirty_i=will_dirty_next;
8753 wont_dirty_i=wont_dirty_next;
8754 //if(cinfo[i].ba>start+i*4) // Disable recursion (for debugging)
8755 for(r=0;r<HOST_REGS;r++) {
8756 if(r!=EXCLUDE_REG) {
8757 signed char target_reg=branch_regs[i].regmap[r];
8758 if(target_reg==regs[(cinfo[i].ba-start)>>2].regmap_entry[r]) {
8759 will_dirty_i&=will_dirty[(cinfo[i].ba-start)>>2]&(1<<r);
8760 wont_dirty_i|=wont_dirty[(cinfo[i].ba-start)>>2]&(1<<r);
8762 else if(target_reg>=0) {
8763 will_dirty_i&=((unneeded_reg[(cinfo[i].ba-start)>>2]>>target_reg)&1)<<r;
8764 wont_dirty_i|=((unneeded_reg[(cinfo[i].ba-start)>>2]>>target_reg)&1)<<r;
8768 // Merge in delay slot
8769 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8770 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8771 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8772 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8773 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8774 will_dirty_i &= branch_hr_candirty;
8775 //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8776 //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8777 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8778 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8779 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8780 will_dirty_i &= hr_candirty;
8782 // Merge in delay slot (won't dirty)
8783 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8784 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8785 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8786 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8787 wont_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8788 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8789 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8790 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8791 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8792 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8793 wont_dirty_i &= ~(1u << 31);
8795 #ifndef DESTRUCTIVE_WRITEBACK
8796 branch_regs[i].dirty&=wont_dirty_i;
8798 branch_regs[i].dirty|=will_dirty_i;
8803 else if (dops[i].is_exception)
8805 // SYSCALL instruction, etc
8809 will_dirty_next=will_dirty_i;
8810 wont_dirty_next=wont_dirty_i;
8811 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8812 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8813 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8814 will_dirty_i &= hr_candirty;
8815 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8816 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8817 wont_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8818 wont_dirty_i &= ~(1u << 31);
8819 if (i > istart && !dops[i].is_jump) {
8820 // Don't store a register immediately after writing it,
8821 // may prevent dual-issue.
8822 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i-1].rt1) & 31);
8823 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i-1].rt2) & 31);
8826 will_dirty[i]=will_dirty_i;
8827 wont_dirty[i]=wont_dirty_i;
8828 // Mark registers that won't be dirtied as not dirty
8830 regs[i].dirty|=will_dirty_i;
8831 #ifndef DESTRUCTIVE_WRITEBACK
8832 regs[i].dirty&=wont_dirty_i;
8835 if (i < iend-1 && !dops[i].is_ujump) {
8836 for(r=0;r<HOST_REGS;r++) {
8837 if(r!=EXCLUDE_REG) {
8838 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
8839 regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
8840 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
8848 for(r=0;r<HOST_REGS;r++) {
8849 if(r!=EXCLUDE_REG) {
8850 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
8851 regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
8852 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
8859 // Deal with changed mappings
8860 temp_will_dirty=will_dirty_i;
8861 temp_wont_dirty=wont_dirty_i;
8862 for(r=0;r<HOST_REGS;r++) {
8863 if(r!=EXCLUDE_REG) {
8865 if(regs[i].regmap[r]==regmap_pre[i][r]) {
8867 #ifndef DESTRUCTIVE_WRITEBACK
8868 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
8870 regs[i].wasdirty|=will_dirty_i&(1<<r);
8873 else if(regmap_pre[i][r]>=0&&(nr=get_rreg(rregmap_i,regmap_pre[i][r]))>=0) {
8874 // Register moved to a different register
8875 will_dirty_i&=~(1<<r);
8876 wont_dirty_i&=~(1<<r);
8877 will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
8878 wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
8880 #ifndef DESTRUCTIVE_WRITEBACK
8881 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
8883 regs[i].wasdirty|=will_dirty_i&(1<<r);
8887 will_dirty_i&=~(1<<r);
8888 wont_dirty_i&=~(1<<r);
8889 if(regmap_pre[i][r]>0 && regmap_pre[i][r]<34) {
8890 will_dirty_i|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r;
8891 wont_dirty_i|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r;
8894 /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);assert(!((will_dirty>>r)&1));*/
8902 static noinline void pass10_expire_blocks(void)
8904 u_int step = MAX_OUTPUT_BLOCK_SIZE / PAGE_COUNT / 2;
8905 // not sizeof(ndrc->translation_cache) due to vita hack
8906 u_int step_mask = ((1u << TARGET_SIZE_2) - 1u) & ~(step - 1u);
8907 u_int end = (out - ndrc->translation_cache + EXPIRITY_OFFSET) & step_mask;
8908 u_int base_shift = __builtin_ctz(MAX_OUTPUT_BLOCK_SIZE);
8911 for (; expirep != end; expirep = ((expirep + step) & step_mask))
8913 u_int base_offs = expirep & ~(MAX_OUTPUT_BLOCK_SIZE - 1);
8914 u_int block_i = expirep / step & (PAGE_COUNT - 1);
8915 u_int phase = (expirep >> (base_shift - 1)) & 1u;
8916 if (!(expirep & (MAX_OUTPUT_BLOCK_SIZE / 2 - 1))) {
8917 inv_debug("EXP: base_offs %x/%lx phase %u\n", base_offs,
8918 (long)(out - ndrc->translation_cache), phase);
8922 hit = blocks_remove_matching_addrs(&blocks[block_i], base_offs, base_shift);
8929 unlink_jumps_tc_range(jumps[block_i], base_offs, base_shift);
8933 static struct block_info *new_block_info(u_int start, u_int len,
8934 const void *source, const void *copy, u_char *beginning, u_short jump_in_count)
8936 struct block_info **b_pptr;
8937 struct block_info *block;
8938 u_int page = get_page(start);
8940 block = malloc(sizeof(*block) + jump_in_count * sizeof(block->jump_in[0]));
8942 assert(jump_in_count > 0);
8943 block->source = source;
8945 block->start = start;
8947 block->reg_sv_flags = 0;
8948 block->tc_offs = beginning - ndrc->translation_cache;
8949 //block->tc_len = out - beginning;
8950 block->is_dirty = 0;
8951 block->inv_near_misses = 0;
8952 block->jump_in_cnt = jump_in_count;
8954 // insert sorted by start mirror-unmasked vaddr
8955 for (b_pptr = &blocks[page]; ; b_pptr = &((*b_pptr)->next)) {
8956 if (*b_pptr == NULL || (*b_pptr)->start >= start) {
8957 block->next = *b_pptr;
8962 stat_inc(stat_blocks);
8966 static int new_recompile_block(u_int addr)
8968 u_int pagelimit = 0;
8969 u_int state_rflags = 0;
8972 assem_debug("NOTCOMPILED: addr = %x -> %p\n", addr, out);
8975 if (addr != hack_addr) {
8976 SysPrintf("game crash @%08x, ra=%08x\n", addr, psxRegs.GPR.n.ra);
8982 // this is just for speculation
8983 for (i = 1; i < 32; i++) {
8984 if ((psxRegs.GPR.r[i] & 0xffff0000) == 0x1f800000)
8985 state_rflags |= 1 << i;
8989 new_dynarec_did_compile=1;
8990 if (Config.HLE && start == 0x80001000) // hlecall
8992 void *beginning = start_block();
8994 emit_movimm(start,0);
8995 emit_writeword(0,&pcaddr);
8996 emit_far_jump(new_dyna_leave);
8998 end_block(beginning);
8999 struct block_info *block = new_block_info(start, 4, NULL, NULL, beginning, 1);
9000 block->jump_in[0].vaddr = start;
9001 block->jump_in[0].addr = beginning;
9004 else if (f1_hack && hack_addr == 0) {
9005 void *beginning = start_block();
9006 emit_movimm(start, 0);
9007 emit_writeword(0, &hack_addr);
9008 emit_readword(&psxRegs.GPR.n.sp, 0);
9009 emit_readptr(&mem_rtab, 1);
9010 emit_shrimm(0, 12, 2);
9011 emit_readptr_dualindexedx_ptrlen(1, 2, 1);
9012 emit_addimm(0, 0x18, 0);
9013 emit_adds_ptr(1, 1, 1);
9014 emit_ldr_dualindexed(1, 0, 0);
9015 emit_writeword(0, &psxRegs.GPR.r[26]); // lw k0, 0x18(sp)
9016 emit_far_call(ndrc_get_addr_ht);
9017 emit_jmpreg(0); // jr k0
9019 end_block(beginning);
9021 struct block_info *block = new_block_info(start, 4, NULL, NULL, beginning, 1);
9022 block->jump_in[0].vaddr = start;
9023 block->jump_in[0].addr = beginning;
9024 SysPrintf("F1 hack to %08x\n", start);
9028 cycle_multiplier_active = get_cycle_multiplier();
9030 source = get_source_start(start, &pagelimit);
9031 if (source == NULL) {
9032 if (addr != hack_addr) {
9033 SysPrintf("Compile at bogus memory address: %08x, ra=%x\n",
9034 addr, psxRegs.GPR.n.ra);
9041 /* Pass 1: disassemble */
9042 /* Pass 2: register dependencies, branch targets */
9043 /* Pass 3: register allocation */
9044 /* Pass 4: branch dependencies */
9045 /* Pass 5: pre-alloc */
9046 /* Pass 6: optimize clean/dirty state */
9047 /* Pass 7: flag 32-bit registers */
9048 /* Pass 8: assembly */
9049 /* Pass 9: linker */
9050 /* Pass 10: garbage collection / free memory */
9052 /* Pass 1 disassembly */
9054 pass1_disassemble(pagelimit);
9056 int clear_hack_addr = apply_hacks();
9058 /* Pass 2 - Register dependencies and branch targets */
9060 pass2_unneeded_regs(0,slen-1,0);
9062 pass2a_unneeded_other();
9064 /* Pass 3 - Register allocation */
9066 pass3_register_alloc(addr);
9068 /* Pass 4 - Cull unused host registers */
9070 pass4_cull_unused_regs();
9072 /* Pass 5 - Pre-allocate registers */
9074 pass5a_preallocate1();
9075 pass5b_preallocate2();
9077 /* Pass 6 - Optimize clean/dirty state */
9078 pass6_clean_registers(0, slen-1, 1);
9081 for (i=slen-1;i>=0;i--)
9083 if(dops[i].itype==CJUMP||dops[i].itype==SJUMP)
9085 // Conditional branch
9086 if((source[i]>>16)!=0x1000&&i<slen-2) {
9087 // Mark this address as a branch target since it may be called
9088 // upon return from interrupt
9094 /* Pass 8 - Assembly */
9095 linkcount=0;stubcount=0;
9098 void *beginning=start_block();
9099 void *instr_addr0_override = NULL;
9102 if ((Config.HLE && start == 0x80000080) || start == 0x80030000) {
9103 instr_addr0_override = out;
9104 emit_movimm(start, 0);
9105 if (start == 0x80030000) {
9106 // for BiosBootBypass() to work
9107 // io address var abused as a "already been here" flag
9108 emit_readword(&address, 1);
9109 emit_writeword(0, &pcaddr);
9110 emit_writeword(0, &address);
9114 emit_readword(&psxRegs.cpuInRecursion, 1);
9115 emit_writeword(0, &pcaddr);
9119 emit_jeq(out + 4*2);
9120 emit_far_jump(new_dyna_leave);
9122 emit_jne(new_dyna_leave);
9127 __builtin_prefetch(regs[i+1].regmap);
9128 check_regmap(regmap_pre[i]);
9129 check_regmap(regs[i].regmap_entry);
9130 check_regmap(regs[i].regmap);
9131 //if(ds) printf("ds: ");
9132 disassemble_inst(i);
9134 ds=0; // Skip delay slot
9135 if(dops[i].bt) assem_debug("OOPS - branch into delay slot\n");
9136 instr_addr[i] = NULL;
9138 speculate_register_values(i);
9139 #ifndef DESTRUCTIVE_WRITEBACK
9140 if (i < 2 || !dops[i-2].is_ujump)
9142 wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,unneeded_reg[i]);
9144 if((dops[i].itype==CJUMP||dops[i].itype==SJUMP)) {
9145 dirty_pre=branch_regs[i].dirty;
9147 dirty_pre=regs[i].dirty;
9151 if (i < 2 || !dops[i-2].is_ujump)
9153 wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,unneeded_reg[i]);
9154 loop_preload(regmap_pre[i],regs[i].regmap_entry);
9156 // branch target entry point
9157 instr_addr[i] = out;
9158 assem_debug("<->\n");
9159 drc_dbg_emit_do_cmp(i, cinfo[i].ccadj);
9160 if (clear_hack_addr) {
9162 emit_writeword(0, &hack_addr);
9163 clear_hack_addr = 0;
9167 if(regs[i].regmap_entry[HOST_CCREG]==CCREG&®s[i].regmap[HOST_CCREG]!=CCREG)
9168 wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty);
9169 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i].rs1,dops[i].rs2);
9170 address_generation(i,®s[i],regs[i].regmap_entry);
9171 load_consts(regmap_pre[i],regs[i].regmap,i);
9174 // Load the delay slot registers if necessary
9175 if(dops[i+1].rs1!=dops[i].rs1&&dops[i+1].rs1!=dops[i].rs2&&(dops[i+1].rs1!=dops[i].rt1||dops[i].rt1==0))
9176 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs1,dops[i+1].rs1);
9177 if(dops[i+1].rs2!=dops[i+1].rs1&&dops[i+1].rs2!=dops[i].rs1&&dops[i+1].rs2!=dops[i].rs2&&(dops[i+1].rs2!=dops[i].rt1||dops[i].rt1==0))
9178 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2);
9179 if (ram_offset && (dops[i+1].is_load || dops[i+1].is_store))
9180 load_reg(regs[i].regmap_entry,regs[i].regmap,ROREG);
9181 if (dops[i+1].is_store)
9182 load_reg(regs[i].regmap_entry,regs[i].regmap,INVCP);
9186 // Preload registers for following instruction
9187 if(dops[i+1].rs1!=dops[i].rs1&&dops[i+1].rs1!=dops[i].rs2)
9188 if(dops[i+1].rs1!=dops[i].rt1&&dops[i+1].rs1!=dops[i].rt2)
9189 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs1,dops[i+1].rs1);
9190 if(dops[i+1].rs2!=dops[i+1].rs1&&dops[i+1].rs2!=dops[i].rs1&&dops[i+1].rs2!=dops[i].rs2)
9191 if(dops[i+1].rs2!=dops[i].rt1&&dops[i+1].rs2!=dops[i].rt2)
9192 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2);
9194 // TODO: if(is_ooo(i)) address_generation(i+1);
9195 if (!dops[i].is_jump || dops[i].itype == CJUMP)
9196 load_reg(regs[i].regmap_entry,regs[i].regmap,CCREG);
9197 if (ram_offset && (dops[i].is_load || dops[i].is_store))
9198 load_reg(regs[i].regmap_entry,regs[i].regmap,ROREG);
9199 if (dops[i].is_store)
9200 load_reg(regs[i].regmap_entry,regs[i].regmap,INVCP);
9202 ds = assemble(i, ®s[i], cinfo[i].ccadj);
9204 drc_dbg_emit_wb_dirtys(i, ®s[i]);
9205 if (dops[i].is_ujump)
9208 literal_pool_jumpover(256);
9213 if (slen > 0 && dops[slen-1].itype == INTCALL) {
9214 // no ending needed for this block since INTCALL never returns
9216 // If the block did not end with an unconditional branch,
9217 // add a jump to the next instruction.
9219 if (!dops[i-2].is_ujump) {
9220 assert(!dops[i-1].is_jump);
9222 if(dops[i-2].itype!=CJUMP&&dops[i-2].itype!=SJUMP) {
9223 store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4);
9224 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
9225 emit_loadreg(CCREG,HOST_CCREG);
9226 emit_addimm(HOST_CCREG, cinfo[i-1].ccadj + CLOCK_ADJUST(1), HOST_CCREG);
9230 store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].dirty,start+i*4);
9231 assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
9233 add_to_linker(out,start+i*4,0);
9240 assert(!dops[i-1].is_jump);
9241 store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4);
9242 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
9243 emit_loadreg(CCREG,HOST_CCREG);
9244 emit_addimm(HOST_CCREG, cinfo[i-1].ccadj + CLOCK_ADJUST(1), HOST_CCREG);
9245 add_to_linker(out,start+i*4,0);
9250 for(i = 0; i < stubcount; i++)
9252 switch(stubs[i].type)
9259 do_readstub(i);break;
9263 do_writestub(i);break;
9267 do_invstub(i);break;
9269 do_unalignedwritestub(i);break;
9271 do_overflowstub(i); break;
9272 case ALIGNMENT_STUB:
9273 do_alignmentstub(i); break;
9279 if (instr_addr0_override)
9280 instr_addr[0] = instr_addr0_override;
9283 /* check for improper expiration */
9284 for (i = 0; i < ARRAY_SIZE(jumps); i++) {
9288 for (j = 0; j < jumps[i]->count; j++)
9289 assert(jumps[i]->e[j].stub < beginning || (u_char *)jumps[i]->e[j].stub > out);
9293 /* Pass 9 - Linker */
9294 for(i=0;i<linkcount;i++)
9296 assem_debug("%p -> %8x\n",link_addr[i].addr,link_addr[i].target);
9298 if (!link_addr[i].internal)
9301 void *addr = check_addr(link_addr[i].target);
9302 emit_extjump(link_addr[i].addr, link_addr[i].target);
9304 set_jump_target(link_addr[i].addr, addr);
9305 ndrc_add_jump_out(link_addr[i].target,stub);
9308 set_jump_target(link_addr[i].addr, stub);
9313 int target=(link_addr[i].target-start)>>2;
9314 assert(target>=0&&target<slen);
9315 assert(instr_addr[target]);
9316 //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
9317 //set_jump_target_fillslot(link_addr[i].addr,instr_addr[target],link_addr[i].ext>>1);
9319 set_jump_target(link_addr[i].addr, instr_addr[target]);
9324 u_int source_len = slen*4;
9325 if (dops[slen-1].itype == INTCALL && source_len > 4)
9326 // no need to treat the last instruction as compiled
9327 // as interpreter fully handles it
9330 if ((u_char *)copy + source_len > (u_char *)shadow + sizeof(shadow))
9333 // External Branch Targets (jump_in)
9334 int jump_in_count = 1;
9335 assert(instr_addr[0]);
9336 for (i = 1; i < slen; i++)
9338 if (dops[i].bt && instr_addr[i])
9342 struct block_info *block =
9343 new_block_info(start, slen * 4, source, copy, beginning, jump_in_count);
9344 block->reg_sv_flags = state_rflags;
9347 for (i = 0; i < slen; i++)
9349 if ((i == 0 || dops[i].bt) && instr_addr[i])
9351 assem_debug("%p (%d) <- %8x\n", instr_addr[i], i, start + i*4);
9352 u_int vaddr = start + i*4;
9358 entry = instr_addr[i];
9360 emit_jmp(instr_addr[i]);
9362 block->jump_in[jump_in_i].vaddr = vaddr;
9363 block->jump_in[jump_in_i].addr = entry;
9367 assert(jump_in_i == jump_in_count);
9368 hash_table_add(block->jump_in[0].vaddr, block->jump_in[0].addr);
9369 // Write out the literal pool if necessary
9371 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
9373 if(((u_int)out)&7) emit_addnop(13);
9375 assert(out - (u_char *)beginning < MAX_OUTPUT_BLOCK_SIZE);
9376 //printf("shadow buffer: %p-%p\n",copy,(u_char *)copy+slen*4);
9377 memcpy(copy, source, source_len);
9380 end_block(beginning);
9382 // If we're within 256K of the end of the buffer,
9383 // start over from the beginning. (Is 256K enough?)
9384 if (out > ndrc->translation_cache + sizeof(ndrc->translation_cache) - MAX_OUTPUT_BLOCK_SIZE)
9385 out = ndrc->translation_cache;
9387 // Trap writes to any of the pages we compiled
9388 mark_invalid_code(start, slen*4, 0);
9390 /* Pass 10 - Free memory by expiring oldest blocks */
9392 pass10_expire_blocks();
9397 stat_inc(stat_bc_direct);
9401 // vim:shiftwidth=2:expandtab