1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
3 * Copyright (C) 2009-2011 Ari64 *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
22 #include <stdint.h> //include for uint64_t
27 #include <libkern/OSCacheControl.h>
30 #include <3ds_utils.h>
33 #include "new_dynarec_config.h"
34 #include "../psxhle.h"
35 #include "../psxinterpreter.h"
37 #include "emu_if.h" // emulator interface
39 #define noinline __attribute__((noinline,noclone))
41 #define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
44 #define min(a, b) ((b) < (a) ? (b) : (a))
47 #define max(a, b) ((b) > (a) ? (b) : (a))
54 #define assem_debug printf
56 #define assem_debug(...)
58 //#define inv_debug printf
59 #define inv_debug(...)
62 #include "assem_x86.h"
65 #include "assem_x64.h"
68 #include "assem_arm.h"
71 #include "assem_arm64.h"
74 #define RAM_SIZE 0x200000
76 #define MAX_OUTPUT_BLOCK_SIZE 262144
80 u_char translation_cache[1 << TARGET_SIZE_2];
83 struct tramp_insns ops[2048 / sizeof(struct tramp_insns)];
84 const void *f[2048 / sizeof(void *)];
88 #ifdef BASE_ADDR_DYNAMIC
89 static struct ndrc_mem *ndrc;
91 static struct ndrc_mem ndrc_ __attribute__((aligned(4096)));
92 static struct ndrc_mem *ndrc = &ndrc_;
115 signed char regmap_entry[HOST_REGS]; // pre-insn + loop preloaded regs?
116 signed char regmap[HOST_REGS];
120 u_int wasconst; // before; for example 'lw r2, (r2)' wasconst is true
121 u_int isconst; // ... but isconst is false when r2 is known
122 u_int loadedconst; // host regs that have constants loaded
123 u_int waswritten; // MIPS regs that were used as store base before
126 // note: asm depends on this layout
132 struct ll_entry *next;
160 static struct decoded_insn
181 struct ht_entry hash_table[65536] __attribute__((aligned(16)));
182 struct ll_entry *jump_in[4096] __attribute__((aligned(16)));
183 struct ll_entry *jump_dirty[4096];
185 static struct ll_entry *jump_out[4096];
187 static u_int *source;
188 static char insn[MAXBLOCK][10];
189 static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
190 static uint64_t gte_rt[MAXBLOCK];
191 static uint64_t gte_unneeded[MAXBLOCK];
192 static u_int smrv[32]; // speculated MIPS register values
193 static u_int smrv_strong; // mask or regs that are likely to have correct values
194 static u_int smrv_weak; // same, but somewhat less likely
195 static u_int smrv_strong_next; // same, but after current insn executes
196 static u_int smrv_weak_next;
197 static int imm[MAXBLOCK];
198 static u_int ba[MAXBLOCK];
199 static uint64_t unneeded_reg[MAXBLOCK];
200 static uint64_t branch_unneeded_reg[MAXBLOCK];
201 // pre-instruction [i], excluding loop-preload regs?
202 static signed char regmap_pre[MAXBLOCK][HOST_REGS];
203 // contains 'real' consts at [i] insn, but may differ from what's actually
204 // loaded in host reg as 'final' value is always loaded, see get_final_value()
205 static uint32_t current_constmap[HOST_REGS];
206 static uint32_t constmap[MAXBLOCK][HOST_REGS];
207 static struct regstat regs[MAXBLOCK];
208 static struct regstat branch_regs[MAXBLOCK];
209 static signed char minimum_free_regs[MAXBLOCK];
210 static u_int needed_reg[MAXBLOCK];
211 static u_int wont_dirty[MAXBLOCK];
212 static u_int will_dirty[MAXBLOCK];
213 static int ccadj[MAXBLOCK];
215 static void *instr_addr[MAXBLOCK];
216 static struct link_entry link_addr[MAXBLOCK];
217 static int linkcount;
218 static struct code_stub stubs[MAXBLOCK*3];
219 static int stubcount;
220 static u_int literals[1024][2];
221 static int literalcount;
222 static int is_delayslot;
223 static char shadow[1048576] __attribute__((aligned(16)));
226 static u_int stop_after_jal;
227 static u_int f1_hack; // 0 - off, ~0 - capture address, else addr
229 int new_dynarec_hacks;
230 int new_dynarec_hacks_pergame;
231 int new_dynarec_hacks_old;
232 int new_dynarec_did_compile;
234 #define HACK_ENABLED(x) ((new_dynarec_hacks | new_dynarec_hacks_pergame) & (x))
236 extern int cycle_count; // ... until end of the timeslice, counts -N -> 0
237 extern int last_count; // last absolute target, often = next_interupt
239 extern int pending_exception;
240 extern int branch_target;
241 extern uintptr_t ram_offset;
242 extern uintptr_t mini_ht[32][2];
243 extern u_char restore_candidate[512];
245 /* registers that may be allocated */
247 #define LOREG 32 // lo
248 #define HIREG 33 // hi
249 //#define FSREG 34 // FPU status (FCSR)
250 #define CSREG 35 // Coprocessor status
251 #define CCREG 36 // Cycle count
252 #define INVCP 37 // Pointer to invalid_code
253 //#define MMREG 38 // Pointer to memory_map
254 #define ROREG 39 // ram offset (if rdram!=0x80000000)
256 #define FTEMP 40 // FPU temporary register
257 #define PTEMP 41 // Prefetch temporary register
258 //#define TLREG 42 // TLB mapping offset
259 #define RHASH 43 // Return address hash
260 #define RHTBL 44 // Return address hash table address
261 #define RTEMP 45 // JR/JALR address register
263 #define AGEN1 46 // Address generation temporary register
264 //#define AGEN2 47 // Address generation temporary register
265 //#define MGEN1 48 // Maptable address generation temporary register
266 //#define MGEN2 49 // Maptable address generation temporary register
267 #define BTREG 50 // Branch target temporary register
269 /* instruction types */
270 #define NOP 0 // No operation
271 #define LOAD 1 // Load
272 #define STORE 2 // Store
273 #define LOADLR 3 // Unaligned load
274 #define STORELR 4 // Unaligned store
275 #define MOV 5 // Move
276 #define ALU 6 // Arithmetic/logic
277 #define MULTDIV 7 // Multiply/divide
278 #define SHIFT 8 // Shift by register
279 #define SHIFTIMM 9// Shift by immediate
280 #define IMM16 10 // 16-bit immediate
281 #define RJUMP 11 // Unconditional jump to register
282 #define UJUMP 12 // Unconditional jump
283 #define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
284 #define SJUMP 14 // Conditional branch (regimm format)
285 #define COP0 15 // Coprocessor 0
286 #define COP1 16 // Coprocessor 1
287 #define C1LS 17 // Coprocessor 1 load/store
288 //#define FJUMP 18 // Conditional branch (floating point)
289 //#define FLOAT 19 // Floating point unit
290 //#define FCONV 20 // Convert integer to float
291 //#define FCOMP 21 // Floating point compare (sets FSREG)
292 #define SYSCALL 22// SYSCALL
293 #define OTHER 23 // Other
294 #define SPAN 24 // Branch/delay slot spans 2 pages
295 #define NI 25 // Not implemented
296 #define HLECALL 26// PCSX fake opcodes for HLE
297 #define COP2 27 // Coprocessor 2 move
298 #define C2LS 28 // Coprocessor 2 load/store
299 #define C2OP 29 // Coprocessor 2 operation
300 #define INTCALL 30// Call interpreter to handle rare corner cases
307 #define DJT_1 (void *)1l // no function, just a label in assem_debug log
308 #define DJT_2 (void *)2l
311 int new_recompile_block(u_int addr);
312 void *get_addr_ht(u_int vaddr);
313 void invalidate_block(u_int block);
314 void invalidate_addr(u_int addr);
315 void remove_hash(int vaddr);
317 void dyna_linker_ds();
319 void verify_code_ds();
322 void fp_exception_ds();
323 void jump_to_new_pc();
324 void call_gteStall();
325 void new_dyna_leave();
327 // Needed by assembler
328 static void wb_register(signed char r, const signed char regmap[], uint64_t dirty);
329 static void wb_dirtys(const signed char i_regmap[], uint64_t i_dirty);
330 static void wb_needed_dirtys(const signed char i_regmap[], uint64_t i_dirty, int addr);
331 static void load_all_regs(const signed char i_regmap[]);
332 static void load_needed_regs(const signed char i_regmap[], const signed char next_regmap[]);
333 static void load_regs_entry(int t);
334 static void load_all_consts(const signed char regmap[], u_int dirty, int i);
335 static u_int get_host_reglist(const signed char *regmap);
337 static int verify_dirty(const u_int *ptr);
338 static int get_final_value(int hr, int i, int *value);
339 static void add_stub(enum stub_type type, void *addr, void *retaddr,
340 u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e);
341 static void add_stub_r(enum stub_type type, void *addr, void *retaddr,
342 int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist);
343 static void add_to_linker(void *addr, u_int target, int ext);
344 static void *emit_fastpath_cmp_jump(int i, const struct regstat *i_regs,
345 int addr, int *offset_reg, int *addr_reg_override);
346 static void *get_direct_memhandler(void *table, u_int addr,
347 enum stub_type type, uintptr_t *addr_host);
348 static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist);
349 static void pass_args(int a0, int a1);
350 static void emit_far_jump(const void *f);
351 static void emit_far_call(const void *f);
354 #include <psp2/kernel/sysmem.h>
356 // note: this interacts with RetroArch's Vita bootstrap code: bootstrap/vita/sbrk.c
357 extern int getVMBlock();
358 int _newlib_vm_size_user = sizeof(*ndrc);
361 static void mprotect_w_x(void *start, void *end, int is_x)
365 // *Open* enables write on all memory that was
366 // allocated by sceKernelAllocMemBlockForVM()?
368 sceKernelCloseVMDomain();
370 sceKernelOpenVMDomain();
372 u_long mstart = (u_long)start & ~4095ul;
373 u_long mend = (u_long)end;
374 if (mprotect((void *)mstart, mend - mstart,
375 PROT_READ | (is_x ? PROT_EXEC : PROT_WRITE)) != 0)
376 SysPrintf("mprotect(%c) failed: %s\n", is_x ? 'x' : 'w', strerror(errno));
381 static void start_tcache_write(void *start, void *end)
383 mprotect_w_x(start, end, 0);
386 static void end_tcache_write(void *start, void *end)
388 #if defined(__arm__) || defined(__aarch64__)
389 size_t len = (char *)end - (char *)start;
390 #if defined(__BLACKBERRY_QNX__)
391 msync(start, len, MS_SYNC | MS_CACHE_ONLY | MS_INVALIDATE_ICACHE);
392 #elif defined(__MACH__)
393 sys_cache_control(kCacheFunctionPrepareForExecution, start, len);
395 sceKernelSyncVMDomain(sceBlock, start, len);
397 ctr_flush_invalidate_cache();
398 #elif defined(__aarch64__)
399 // as of 2021, __clear_cache() is still broken on arm64
400 // so here is a custom one :(
401 clear_cache_arm64(start, end);
403 __clear_cache(start, end);
408 mprotect_w_x(start, end, 1);
411 static void *start_block(void)
413 u_char *end = out + MAX_OUTPUT_BLOCK_SIZE;
414 if (end > ndrc->translation_cache + sizeof(ndrc->translation_cache))
415 end = ndrc->translation_cache + sizeof(ndrc->translation_cache);
416 start_tcache_write(out, end);
420 static void end_block(void *start)
422 end_tcache_write(start, out);
425 // also takes care of w^x mappings when patching code
426 static u_int needs_clear_cache[1<<(TARGET_SIZE_2-17)];
428 static void mark_clear_cache(void *target)
430 uintptr_t offset = (u_char *)target - ndrc->translation_cache;
431 u_int mask = 1u << ((offset >> 12) & 31);
432 if (!(needs_clear_cache[offset >> 17] & mask)) {
433 char *start = (char *)((uintptr_t)target & ~4095l);
434 start_tcache_write(start, start + 4095);
435 needs_clear_cache[offset >> 17] |= mask;
439 // Clearing the cache is rather slow on ARM Linux, so mark the areas
440 // that need to be cleared, and then only clear these areas once.
441 static void do_clear_cache(void)
444 for (i = 0; i < (1<<(TARGET_SIZE_2-17)); i++)
446 u_int bitmap = needs_clear_cache[i];
449 for (j = 0; j < 32; j++)
452 if (!(bitmap & (1<<j)))
455 start = ndrc->translation_cache + i*131072 + j*4096;
457 for (j++; j < 32; j++) {
458 if (!(bitmap & (1<<j)))
462 end_tcache_write(start, end);
464 needs_clear_cache[i] = 0;
468 //#define DEBUG_CYCLE_COUNT 1
470 #define NO_CYCLE_PENALTY_THR 12
472 int cycle_multiplier = CYCLE_MULT_DEFAULT; // 100 for 1.0
473 int cycle_multiplier_override;
474 int cycle_multiplier_old;
475 static int cycle_multiplier_active;
477 static int CLOCK_ADJUST(int x)
479 int m = cycle_multiplier_active;
480 int s = (x >> 31) | 1;
481 return (x * m + s * 50) / 100;
484 static int ds_writes_rjump_rs(int i)
486 return dops[i].rs1 != 0 && (dops[i].rs1 == dops[i+1].rt1 || dops[i].rs1 == dops[i+1].rt2);
489 static u_int get_page(u_int vaddr)
491 u_int page=vaddr&~0xe0000000;
492 if (page < 0x1000000)
493 page &= ~0x0e00000; // RAM mirrors
495 if(page>2048) page=2048+(page&2047);
499 // no virtual mem in PCSX
500 static u_int get_vpage(u_int vaddr)
502 return get_page(vaddr);
505 static struct ht_entry *hash_table_get(u_int vaddr)
507 return &hash_table[((vaddr>>16)^vaddr)&0xFFFF];
510 static void hash_table_add(struct ht_entry *ht_bin, u_int vaddr, void *tcaddr)
512 ht_bin->vaddr[1] = ht_bin->vaddr[0];
513 ht_bin->tcaddr[1] = ht_bin->tcaddr[0];
514 ht_bin->vaddr[0] = vaddr;
515 ht_bin->tcaddr[0] = tcaddr;
518 // some messy ari64's code, seems to rely on unsigned 32bit overflow
519 static int doesnt_expire_soon(void *tcaddr)
521 u_int diff = (u_int)((u_char *)tcaddr - out) << (32-TARGET_SIZE_2);
522 return diff > (u_int)(0x60000000 + (MAX_OUTPUT_BLOCK_SIZE << (32-TARGET_SIZE_2)));
525 // Get address from virtual address
526 // This is called from the recompiled JR/JALR instructions
527 void noinline *get_addr(u_int vaddr)
529 u_int page=get_page(vaddr);
530 u_int vpage=get_vpage(vaddr);
531 struct ll_entry *head;
532 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
535 if(head->vaddr==vaddr) {
536 //printf("TRACE: count=%d next=%d (get_addr match %x: %p)\n",Count,next_interupt,vaddr,head->addr);
537 hash_table_add(hash_table_get(vaddr), vaddr, head->addr);
542 head=jump_dirty[vpage];
544 if(head->vaddr==vaddr) {
545 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %p)\n",Count,next_interupt,vaddr,head->addr);
546 // Don't restore blocks which are about to expire from the cache
547 if (doesnt_expire_soon(head->addr))
548 if (verify_dirty(head->addr)) {
549 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
550 invalid_code[vaddr>>12]=0;
551 inv_code_start=inv_code_end=~0;
553 restore_candidate[vpage>>3]|=1<<(vpage&7);
555 else restore_candidate[page>>3]|=1<<(page&7);
556 struct ht_entry *ht_bin = hash_table_get(vaddr);
557 if (ht_bin->vaddr[0] == vaddr)
558 ht_bin->tcaddr[0] = head->addr; // Replace existing entry
560 hash_table_add(ht_bin, vaddr, head->addr);
567 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
568 int r=new_recompile_block(vaddr);
569 if(r==0) return get_addr(vaddr);
570 // Execute in unmapped page, generate pagefault execption
572 Cause=(vaddr<<31)|0x8;
573 EPC=(vaddr&1)?vaddr-5:vaddr;
575 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
576 EntryHi=BadVAddr&0xFFFFE000;
577 return get_addr_ht(0x80000000);
579 // Look up address in hash table first
580 void *get_addr_ht(u_int vaddr)
582 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
583 const struct ht_entry *ht_bin = hash_table_get(vaddr);
584 if (ht_bin->vaddr[0] == vaddr) return ht_bin->tcaddr[0];
585 if (ht_bin->vaddr[1] == vaddr) return ht_bin->tcaddr[1];
586 return get_addr(vaddr);
589 void clear_all_regs(signed char regmap[])
592 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
595 static signed char get_reg(const signed char regmap[],int r)
598 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map[hr]==r) return hr;
602 // Find a register that is available for two consecutive cycles
603 static signed char get_reg2(signed char regmap1[], const signed char regmap2[], int r)
606 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map1[hr]==r&®map2[hr]==r) return hr;
610 int count_free_regs(signed char regmap[])
614 for(hr=0;hr<HOST_REGS;hr++)
616 if(hr!=EXCLUDE_REG) {
617 if(regmap[hr]<0) count++;
623 void dirty_reg(struct regstat *cur,signed char reg)
627 for (hr=0;hr<HOST_REGS;hr++) {
628 if((cur->regmap[hr]&63)==reg) {
634 static void set_const(struct regstat *cur, signed char reg, uint32_t value)
638 for (hr=0;hr<HOST_REGS;hr++) {
639 if(cur->regmap[hr]==reg) {
641 current_constmap[hr]=value;
646 static void clear_const(struct regstat *cur, signed char reg)
650 for (hr=0;hr<HOST_REGS;hr++) {
651 if((cur->regmap[hr]&63)==reg) {
652 cur->isconst&=~(1<<hr);
657 static int is_const(struct regstat *cur, signed char reg)
662 for (hr=0;hr<HOST_REGS;hr++) {
663 if((cur->regmap[hr]&63)==reg) {
664 return (cur->isconst>>hr)&1;
670 static uint32_t get_const(struct regstat *cur, signed char reg)
674 for (hr=0;hr<HOST_REGS;hr++) {
675 if(cur->regmap[hr]==reg) {
676 return current_constmap[hr];
679 SysPrintf("Unknown constant in r%d\n",reg);
683 // Least soon needed registers
684 // Look at the next ten instructions and see which registers
685 // will be used. Try not to reallocate these.
686 void lsn(u_char hsn[], int i, int *preferred_reg)
696 if (dops[i+j].is_ujump)
698 // Don't go past an unconditonal jump
705 if(dops[i+j].rs1) hsn[dops[i+j].rs1]=j;
706 if(dops[i+j].rs2) hsn[dops[i+j].rs2]=j;
707 if(dops[i+j].rt1) hsn[dops[i+j].rt1]=j;
708 if(dops[i+j].rt2) hsn[dops[i+j].rt2]=j;
709 if(dops[i+j].itype==STORE || dops[i+j].itype==STORELR) {
710 // Stores can allocate zero
711 hsn[dops[i+j].rs1]=j;
712 hsn[dops[i+j].rs2]=j;
714 if (ram_offset && (dops[i+j].is_load || dops[i+j].is_store))
716 // On some architectures stores need invc_ptr
717 #if defined(HOST_IMM8)
718 if (dops[i+j].is_store)
721 if(i+j>=0&&(dops[i+j].itype==UJUMP||dops[i+j].itype==CJUMP||dops[i+j].itype==SJUMP))
729 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
731 // Follow first branch
732 int t=(ba[i+b]-start)>>2;
733 j=7-b;if(t+j>=slen) j=slen-t-1;
736 if(dops[t+j].rs1) if(hsn[dops[t+j].rs1]>j+b+2) hsn[dops[t+j].rs1]=j+b+2;
737 if(dops[t+j].rs2) if(hsn[dops[t+j].rs2]>j+b+2) hsn[dops[t+j].rs2]=j+b+2;
738 //if(dops[t+j].rt1) if(hsn[dops[t+j].rt1]>j+b+2) hsn[dops[t+j].rt1]=j+b+2;
739 //if(dops[t+j].rt2) if(hsn[dops[t+j].rt2]>j+b+2) hsn[dops[t+j].rt2]=j+b+2;
742 // TODO: preferred register based on backward branch
744 // Delay slot should preferably not overwrite branch conditions or cycle count
745 if (i > 0 && dops[i-1].is_jump) {
746 if(dops[i-1].rs1) if(hsn[dops[i-1].rs1]>1) hsn[dops[i-1].rs1]=1;
747 if(dops[i-1].rs2) if(hsn[dops[i-1].rs2]>1) hsn[dops[i-1].rs2]=1;
753 // Coprocessor load/store needs FTEMP, even if not declared
754 if(dops[i].itype==C2LS) {
757 // Load L/R also uses FTEMP as a temporary register
758 if(dops[i].itype==LOADLR) {
761 // Also SWL/SWR/SDL/SDR
762 if(dops[i].opcode==0x2a||dops[i].opcode==0x2e||dops[i].opcode==0x2c||dops[i].opcode==0x2d) {
765 // Don't remove the miniht registers
766 if(dops[i].itype==UJUMP||dops[i].itype==RJUMP)
773 // We only want to allocate registers if we're going to use them again soon
774 int needed_again(int r, int i)
780 if (i > 0 && dops[i-1].is_ujump)
782 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
783 return 0; // Don't need any registers if exiting the block
791 if (dops[i+j].is_ujump)
793 // Don't go past an unconditonal jump
797 if(dops[i+j].itype==SYSCALL||dops[i+j].itype==HLECALL||dops[i+j].itype==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
804 if(dops[i+j].rs1==r) rn=j;
805 if(dops[i+j].rs2==r) rn=j;
806 if((unneeded_reg[i+j]>>r)&1) rn=10;
807 if(i+j>=0&&(dops[i+j].itype==UJUMP||dops[i+j].itype==CJUMP||dops[i+j].itype==SJUMP))
817 // Try to match register allocations at the end of a loop with those
819 int loop_reg(int i, int r, int hr)
828 if (dops[i+j].is_ujump)
830 // Don't go past an unconditonal jump
837 if(dops[i-1].itype==UJUMP||dops[i-1].itype==CJUMP||dops[i-1].itype==SJUMP)
843 if((unneeded_reg[i+k]>>r)&1) return hr;
844 if(i+k>=0&&(dops[i+k].itype==UJUMP||dops[i+k].itype==CJUMP||dops[i+k].itype==SJUMP))
846 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
848 int t=(ba[i+k]-start)>>2;
849 int reg=get_reg(regs[t].regmap_entry,r);
850 if(reg>=0) return reg;
851 //reg=get_reg(regs[t+1].regmap_entry,r);
852 //if(reg>=0) return reg;
860 // Allocate every register, preserving source/target regs
861 void alloc_all(struct regstat *cur,int i)
865 for(hr=0;hr<HOST_REGS;hr++) {
866 if(hr!=EXCLUDE_REG) {
867 if(((cur->regmap[hr]&63)!=dops[i].rs1)&&((cur->regmap[hr]&63)!=dops[i].rs2)&&
868 ((cur->regmap[hr]&63)!=dops[i].rt1)&&((cur->regmap[hr]&63)!=dops[i].rt2))
871 cur->dirty&=~(1<<hr);
874 if((cur->regmap[hr]&63)==0)
877 cur->dirty&=~(1<<hr);
884 static int host_tempreg_in_use;
886 static void host_tempreg_acquire(void)
888 assert(!host_tempreg_in_use);
889 host_tempreg_in_use = 1;
892 static void host_tempreg_release(void)
894 host_tempreg_in_use = 0;
897 static void host_tempreg_acquire(void) {}
898 static void host_tempreg_release(void) {}
902 extern void gen_interupt();
903 extern void do_insn_cmp();
904 #define FUNCNAME(f) { f, " " #f }
905 static const struct {
908 } function_names[] = {
909 FUNCNAME(cc_interrupt),
910 FUNCNAME(gen_interupt),
911 FUNCNAME(get_addr_ht),
913 FUNCNAME(jump_handler_read8),
914 FUNCNAME(jump_handler_read16),
915 FUNCNAME(jump_handler_read32),
916 FUNCNAME(jump_handler_write8),
917 FUNCNAME(jump_handler_write16),
918 FUNCNAME(jump_handler_write32),
919 FUNCNAME(invalidate_addr),
920 FUNCNAME(jump_to_new_pc),
921 FUNCNAME(call_gteStall),
922 FUNCNAME(new_dyna_leave),
924 FUNCNAME(pcsx_mtc0_ds),
926 FUNCNAME(do_insn_cmp),
929 FUNCNAME(verify_code),
933 static const char *func_name(const void *a)
936 for (i = 0; i < sizeof(function_names)/sizeof(function_names[0]); i++)
937 if (function_names[i].addr == a)
938 return function_names[i].name;
942 #define func_name(x) ""
946 #include "assem_x86.c"
949 #include "assem_x64.c"
952 #include "assem_arm.c"
955 #include "assem_arm64.c"
958 static void *get_trampoline(const void *f)
962 for (i = 0; i < ARRAY_SIZE(ndrc->tramp.f); i++) {
963 if (ndrc->tramp.f[i] == f || ndrc->tramp.f[i] == NULL)
966 if (i == ARRAY_SIZE(ndrc->tramp.f)) {
967 SysPrintf("trampoline table is full, last func %p\n", f);
970 if (ndrc->tramp.f[i] == NULL) {
971 start_tcache_write(&ndrc->tramp.f[i], &ndrc->tramp.f[i + 1]);
972 ndrc->tramp.f[i] = f;
973 end_tcache_write(&ndrc->tramp.f[i], &ndrc->tramp.f[i + 1]);
975 return &ndrc->tramp.ops[i];
978 static void emit_far_jump(const void *f)
980 if (can_jump_or_call(f)) {
985 f = get_trampoline(f);
989 static void emit_far_call(const void *f)
991 if (can_jump_or_call(f)) {
996 f = get_trampoline(f);
1000 // Add virtual address mapping to linked list
1001 void ll_add(struct ll_entry **head,int vaddr,void *addr)
1003 struct ll_entry *new_entry;
1004 new_entry=malloc(sizeof(struct ll_entry));
1005 assert(new_entry!=NULL);
1006 new_entry->vaddr=vaddr;
1007 new_entry->reg_sv_flags=0;
1008 new_entry->addr=addr;
1009 new_entry->next=*head;
1013 void ll_add_flags(struct ll_entry **head,int vaddr,u_int reg_sv_flags,void *addr)
1015 ll_add(head,vaddr,addr);
1016 (*head)->reg_sv_flags=reg_sv_flags;
1019 // Check if an address is already compiled
1020 // but don't return addresses which are about to expire from the cache
1021 void *check_addr(u_int vaddr)
1023 struct ht_entry *ht_bin = hash_table_get(vaddr);
1025 for (i = 0; i < ARRAY_SIZE(ht_bin->vaddr); i++) {
1026 if (ht_bin->vaddr[i] == vaddr)
1027 if (doesnt_expire_soon((u_char *)ht_bin->tcaddr[i] - MAX_OUTPUT_BLOCK_SIZE))
1028 if (isclean(ht_bin->tcaddr[i]))
1029 return ht_bin->tcaddr[i];
1031 u_int page=get_page(vaddr);
1032 struct ll_entry *head;
1034 while (head != NULL) {
1035 if (head->vaddr == vaddr) {
1036 if (doesnt_expire_soon(head->addr)) {
1037 // Update existing entry with current address
1038 if (ht_bin->vaddr[0] == vaddr) {
1039 ht_bin->tcaddr[0] = head->addr;
1042 if (ht_bin->vaddr[1] == vaddr) {
1043 ht_bin->tcaddr[1] = head->addr;
1046 // Insert into hash table with low priority.
1047 // Don't evict existing entries, as they are probably
1048 // addresses that are being accessed frequently.
1049 if (ht_bin->vaddr[0] == -1) {
1050 ht_bin->vaddr[0] = vaddr;
1051 ht_bin->tcaddr[0] = head->addr;
1053 else if (ht_bin->vaddr[1] == -1) {
1054 ht_bin->vaddr[1] = vaddr;
1055 ht_bin->tcaddr[1] = head->addr;
1065 void remove_hash(int vaddr)
1067 //printf("remove hash: %x\n",vaddr);
1068 struct ht_entry *ht_bin = hash_table_get(vaddr);
1069 if (ht_bin->vaddr[1] == vaddr) {
1070 ht_bin->vaddr[1] = -1;
1071 ht_bin->tcaddr[1] = NULL;
1073 if (ht_bin->vaddr[0] == vaddr) {
1074 ht_bin->vaddr[0] = ht_bin->vaddr[1];
1075 ht_bin->tcaddr[0] = ht_bin->tcaddr[1];
1076 ht_bin->vaddr[1] = -1;
1077 ht_bin->tcaddr[1] = NULL;
1081 static void ll_remove_matching_addrs(struct ll_entry **head,
1082 uintptr_t base_offs_s, int shift)
1084 struct ll_entry *next;
1086 uintptr_t o1 = (u_char *)(*head)->addr - ndrc->translation_cache;
1087 uintptr_t o2 = o1 - MAX_OUTPUT_BLOCK_SIZE;
1088 if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s)
1090 inv_debug("EXP: Remove pointer to %p (%x)\n",(*head)->addr,(*head)->vaddr);
1091 remove_hash((*head)->vaddr);
1098 head=&((*head)->next);
1103 // Remove all entries from linked list
1104 void ll_clear(struct ll_entry **head)
1106 struct ll_entry *cur;
1107 struct ll_entry *next;
1118 // Dereference the pointers and remove if it matches
1119 static void ll_kill_pointers(struct ll_entry *head,
1120 uintptr_t base_offs_s, int shift)
1123 u_char *ptr = get_pointer(head->addr);
1124 uintptr_t o1 = ptr - ndrc->translation_cache;
1125 uintptr_t o2 = o1 - MAX_OUTPUT_BLOCK_SIZE;
1126 inv_debug("EXP: Lookup pointer to %p at %p (%x)\n",ptr,head->addr,head->vaddr);
1127 if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s)
1129 inv_debug("EXP: Kill pointer at %p (%x)\n",head->addr,head->vaddr);
1130 void *host_addr=find_extjump_insn(head->addr);
1131 mark_clear_cache(host_addr);
1132 set_jump_target(host_addr, head->addr);
1138 // This is called when we write to a compiled block (see do_invstub)
1139 static void invalidate_page(u_int page)
1141 struct ll_entry *head;
1142 struct ll_entry *next;
1146 inv_debug("INVALIDATE: %x\n",head->vaddr);
1147 remove_hash(head->vaddr);
1152 head=jump_out[page];
1155 inv_debug("INVALIDATE: kill pointer to %x (%p)\n",head->vaddr,head->addr);
1156 void *host_addr=find_extjump_insn(head->addr);
1157 mark_clear_cache(host_addr);
1158 set_jump_target(host_addr, head->addr); // point back to dyna_linker
1165 static void invalidate_block_range(u_int block, u_int first, u_int last)
1167 u_int page=get_page(block<<12);
1168 //printf("first=%d last=%d\n",first,last);
1169 invalidate_page(page);
1170 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1171 assert(last<page+5);
1172 // Invalidate the adjacent pages if a block crosses a 4K boundary
1174 invalidate_page(first);
1177 for(first=page+1;first<last;first++) {
1178 invalidate_page(first);
1182 // Don't trap writes
1183 invalid_code[block]=1;
1186 memset(mini_ht,-1,sizeof(mini_ht));
1190 void invalidate_block(u_int block)
1192 u_int page=get_page(block<<12);
1193 u_int vpage=get_vpage(block<<12);
1194 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1195 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1198 struct ll_entry *head;
1199 head=jump_dirty[vpage];
1200 //printf("page=%d vpage=%d\n",page,vpage);
1202 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1203 u_char *start, *end;
1204 get_bounds(head->addr, &start, &end);
1205 //printf("start: %p end: %p\n", start, end);
1206 if (page < 2048 && start >= rdram && end < rdram+RAM_SIZE) {
1207 if (((start-rdram)>>12) <= page && ((end-1-rdram)>>12) >= page) {
1208 if ((((start-rdram)>>12)&2047) < first) first = ((start-rdram)>>12)&2047;
1209 if ((((end-1-rdram)>>12)&2047) > last) last = ((end-1-rdram)>>12)&2047;
1215 invalidate_block_range(block,first,last);
1218 void invalidate_addr(u_int addr)
1221 // this check is done by the caller
1222 //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
1223 u_int page=get_vpage(addr);
1224 if(page<2048) { // RAM
1225 struct ll_entry *head;
1226 u_int addr_min=~0, addr_max=0;
1227 u_int mask=RAM_SIZE-1;
1228 u_int addr_main=0x80000000|(addr&mask);
1230 inv_code_start=addr_main&~0xfff;
1231 inv_code_end=addr_main|0xfff;
1234 // must check previous page too because of spans..
1236 inv_code_start-=0x1000;
1238 for(;pg1<=page;pg1++) {
1239 for(head=jump_dirty[pg1];head!=NULL;head=head->next) {
1240 u_char *start_h, *end_h;
1242 get_bounds(head->addr, &start_h, &end_h);
1243 start = (uintptr_t)start_h - ram_offset;
1244 end = (uintptr_t)end_h - ram_offset;
1245 if(start<=addr_main&&addr_main<end) {
1246 if(start<addr_min) addr_min=start;
1247 if(end>addr_max) addr_max=end;
1249 else if(addr_main<start) {
1250 if(start<inv_code_end)
1251 inv_code_end=start-1;
1254 if(end>inv_code_start)
1260 inv_debug("INV ADDR: %08x hit %08x-%08x\n", addr, addr_min, addr_max);
1261 inv_code_start=inv_code_end=~0;
1262 invalidate_block_range(addr>>12,(addr_min&mask)>>12,(addr_max&mask)>>12);
1266 inv_code_start=(addr&~mask)|(inv_code_start&mask);
1267 inv_code_end=(addr&~mask)|(inv_code_end&mask);
1268 inv_debug("INV ADDR: %08x miss, inv %08x-%08x, sk %d\n", addr, inv_code_start, inv_code_end, 0);
1272 invalidate_block(addr>>12);
1275 // This is called when loading a save state.
1276 // Anything could have changed, so invalidate everything.
1277 void invalidate_all_pages(void)
1280 for(page=0;page<4096;page++)
1281 invalidate_page(page);
1282 for(page=0;page<1048576;page++)
1283 if(!invalid_code[page]) {
1284 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1285 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1288 memset(mini_ht,-1,sizeof(mini_ht));
1293 static void do_invstub(int n)
1296 u_int reglist=stubs[n].a;
1297 set_jump_target(stubs[n].addr, out);
1299 if(stubs[n].b!=0) emit_mov(stubs[n].b,0);
1300 emit_far_call(invalidate_addr);
1301 restore_regs(reglist);
1302 emit_jmp(stubs[n].retaddr); // return address
1305 // Add an entry to jump_out after making a link
1306 // src should point to code by emit_extjump2()
1307 void add_jump_out(u_int vaddr,void *src)
1309 u_int page=get_page(vaddr);
1310 inv_debug("add_jump_out: %p -> %x (%d)\n",src,vaddr,page);
1311 check_extjump2(src);
1312 ll_add(jump_out+page,vaddr,src);
1313 //inv_debug("add_jump_out: to %p\n",get_pointer(src));
1316 // If a code block was found to be unmodified (bit was set in
1317 // restore_candidate) and it remains unmodified (bit is clear
1318 // in invalid_code) then move the entries for that 4K page from
1319 // the dirty list to the clean list.
1320 void clean_blocks(u_int page)
1322 struct ll_entry *head;
1323 inv_debug("INV: clean_blocks page=%d\n",page);
1324 head=jump_dirty[page];
1326 if(!invalid_code[head->vaddr>>12]) {
1327 // Don't restore blocks which are about to expire from the cache
1328 if (doesnt_expire_soon(head->addr)) {
1329 if(verify_dirty(head->addr)) {
1330 u_char *start, *end;
1331 //printf("Possibly Restore %x (%p)\n",head->vaddr, head->addr);
1334 get_bounds(head->addr, &start, &end);
1335 if (start - rdram < RAM_SIZE) {
1336 for (i = (start-rdram+0x80000000)>>12; i <= (end-1-rdram+0x80000000)>>12; i++) {
1337 inv|=invalid_code[i];
1340 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
1344 void *clean_addr = get_clean_addr(head->addr);
1345 if (doesnt_expire_soon(clean_addr)) {
1347 inv_debug("INV: Restored %x (%p/%p)\n",head->vaddr, head->addr, clean_addr);
1348 //printf("page=%x, addr=%x\n",page,head->vaddr);
1349 //assert(head->vaddr>>12==(page|0x80000));
1350 ll_add_flags(jump_in+ppage,head->vaddr,head->reg_sv_flags,clean_addr);
1351 struct ht_entry *ht_bin = hash_table_get(head->vaddr);
1352 if (ht_bin->vaddr[0] == head->vaddr)
1353 ht_bin->tcaddr[0] = clean_addr; // Replace existing entry
1354 if (ht_bin->vaddr[1] == head->vaddr)
1355 ht_bin->tcaddr[1] = clean_addr; // Replace existing entry
1365 /* Register allocation */
1367 // Note: registers are allocated clean (unmodified state)
1368 // if you intend to modify the register, you must call dirty_reg().
1369 static void alloc_reg(struct regstat *cur,int i,signed char reg)
1372 int preferred_reg = PREFERRED_REG_FIRST
1373 + reg % (PREFERRED_REG_LAST - PREFERRED_REG_FIRST + 1);
1374 if (reg == CCREG) preferred_reg = HOST_CCREG;
1375 if (reg == PTEMP || reg == FTEMP) preferred_reg = 12;
1376 assert(PREFERRED_REG_FIRST != EXCLUDE_REG && EXCLUDE_REG != HOST_REGS);
1378 // Don't allocate unused registers
1379 if((cur->u>>reg)&1) return;
1381 // see if it's already allocated
1382 for(hr=0;hr<HOST_REGS;hr++)
1384 if(cur->regmap[hr]==reg) return;
1387 // Keep the same mapping if the register was already allocated in a loop
1388 preferred_reg = loop_reg(i,reg,preferred_reg);
1390 // Try to allocate the preferred register
1391 if(cur->regmap[preferred_reg]==-1) {
1392 cur->regmap[preferred_reg]=reg;
1393 cur->dirty&=~(1<<preferred_reg);
1394 cur->isconst&=~(1<<preferred_reg);
1397 r=cur->regmap[preferred_reg];
1400 cur->regmap[preferred_reg]=reg;
1401 cur->dirty&=~(1<<preferred_reg);
1402 cur->isconst&=~(1<<preferred_reg);
1406 // Clear any unneeded registers
1407 // We try to keep the mapping consistent, if possible, because it
1408 // makes branches easier (especially loops). So we try to allocate
1409 // first (see above) before removing old mappings. If this is not
1410 // possible then go ahead and clear out the registers that are no
1412 for(hr=0;hr<HOST_REGS;hr++)
1417 if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
1421 // Try to allocate any available register, but prefer
1422 // registers that have not been used recently.
1424 for (hr = PREFERRED_REG_FIRST; ; ) {
1425 if (cur->regmap[hr] < 0) {
1426 int oldreg = regs[i-1].regmap[hr];
1427 if (oldreg < 0 || (oldreg != dops[i-1].rs1 && oldreg != dops[i-1].rs2
1428 && oldreg != dops[i-1].rt1 && oldreg != dops[i-1].rt2))
1430 cur->regmap[hr]=reg;
1431 cur->dirty&=~(1<<hr);
1432 cur->isconst&=~(1<<hr);
1437 if (hr == EXCLUDE_REG)
1439 if (hr == HOST_REGS)
1441 if (hr == PREFERRED_REG_FIRST)
1446 // Try to allocate any available register
1447 for (hr = PREFERRED_REG_FIRST; ; ) {
1448 if (cur->regmap[hr] < 0) {
1449 cur->regmap[hr]=reg;
1450 cur->dirty&=~(1<<hr);
1451 cur->isconst&=~(1<<hr);
1455 if (hr == EXCLUDE_REG)
1457 if (hr == HOST_REGS)
1459 if (hr == PREFERRED_REG_FIRST)
1463 // Ok, now we have to evict someone
1464 // Pick a register we hopefully won't need soon
1465 u_char hsn[MAXREG+1];
1466 memset(hsn,10,sizeof(hsn));
1468 lsn(hsn,i,&preferred_reg);
1469 //printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",cur->regmap[0],cur->regmap[1],cur->regmap[2],cur->regmap[3],cur->regmap[5],cur->regmap[6],cur->regmap[7]);
1470 //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
1472 // Don't evict the cycle count at entry points, otherwise the entry
1473 // stub will have to write it.
1474 if(dops[i].bt&&hsn[CCREG]>2) hsn[CCREG]=2;
1475 if (i>1 && hsn[CCREG] > 2 && dops[i-2].is_jump) hsn[CCREG]=2;
1478 // Alloc preferred register if available
1479 if(hsn[r=cur->regmap[preferred_reg]&63]==j) {
1480 for(hr=0;hr<HOST_REGS;hr++) {
1481 // Evict both parts of a 64-bit register
1482 if((cur->regmap[hr]&63)==r) {
1484 cur->dirty&=~(1<<hr);
1485 cur->isconst&=~(1<<hr);
1488 cur->regmap[preferred_reg]=reg;
1491 for(r=1;r<=MAXREG;r++)
1493 if(hsn[r]==j&&r!=dops[i-1].rs1&&r!=dops[i-1].rs2&&r!=dops[i-1].rt1&&r!=dops[i-1].rt2) {
1494 for(hr=0;hr<HOST_REGS;hr++) {
1495 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
1496 if(cur->regmap[hr]==r) {
1497 cur->regmap[hr]=reg;
1498 cur->dirty&=~(1<<hr);
1499 cur->isconst&=~(1<<hr);
1510 for(r=1;r<=MAXREG;r++)
1513 for(hr=0;hr<HOST_REGS;hr++) {
1514 if(cur->regmap[hr]==r) {
1515 cur->regmap[hr]=reg;
1516 cur->dirty&=~(1<<hr);
1517 cur->isconst&=~(1<<hr);
1524 SysPrintf("This shouldn't happen (alloc_reg)");abort();
1527 // Allocate a temporary register. This is done without regard to
1528 // dirty status or whether the register we request is on the unneeded list
1529 // Note: This will only allocate one register, even if called multiple times
1530 static void alloc_reg_temp(struct regstat *cur,int i,signed char reg)
1533 int preferred_reg = -1;
1535 // see if it's already allocated
1536 for(hr=0;hr<HOST_REGS;hr++)
1538 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==reg) return;
1541 // Try to allocate any available register
1542 for(hr=HOST_REGS-1;hr>=0;hr--) {
1543 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
1544 cur->regmap[hr]=reg;
1545 cur->dirty&=~(1<<hr);
1546 cur->isconst&=~(1<<hr);
1551 // Find an unneeded register
1552 for(hr=HOST_REGS-1;hr>=0;hr--)
1558 if(i==0||((unneeded_reg[i-1]>>r)&1)) {
1559 cur->regmap[hr]=reg;
1560 cur->dirty&=~(1<<hr);
1561 cur->isconst&=~(1<<hr);
1568 // Ok, now we have to evict someone
1569 // Pick a register we hopefully won't need soon
1570 // TODO: we might want to follow unconditional jumps here
1571 // TODO: get rid of dupe code and make this into a function
1572 u_char hsn[MAXREG+1];
1573 memset(hsn,10,sizeof(hsn));
1575 lsn(hsn,i,&preferred_reg);
1576 //printf("hsn: %d %d %d %d %d %d %d\n",hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
1578 // Don't evict the cycle count at entry points, otherwise the entry
1579 // stub will have to write it.
1580 if(dops[i].bt&&hsn[CCREG]>2) hsn[CCREG]=2;
1581 if (i>1 && hsn[CCREG] > 2 && dops[i-2].is_jump) hsn[CCREG]=2;
1584 for(r=1;r<=MAXREG;r++)
1586 if(hsn[r]==j&&r!=dops[i-1].rs1&&r!=dops[i-1].rs2&&r!=dops[i-1].rt1&&r!=dops[i-1].rt2) {
1587 for(hr=0;hr<HOST_REGS;hr++) {
1588 if(hr!=HOST_CCREG||hsn[CCREG]>2) {
1589 if(cur->regmap[hr]==r) {
1590 cur->regmap[hr]=reg;
1591 cur->dirty&=~(1<<hr);
1592 cur->isconst&=~(1<<hr);
1603 for(r=1;r<=MAXREG;r++)
1606 for(hr=0;hr<HOST_REGS;hr++) {
1607 if(cur->regmap[hr]==r) {
1608 cur->regmap[hr]=reg;
1609 cur->dirty&=~(1<<hr);
1610 cur->isconst&=~(1<<hr);
1617 SysPrintf("This shouldn't happen");abort();
1620 static void mov_alloc(struct regstat *current,int i)
1622 if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) {
1623 alloc_cc(current,i); // for stalls
1624 dirty_reg(current,CCREG);
1627 // Note: Don't need to actually alloc the source registers
1628 //alloc_reg(current,i,dops[i].rs1);
1629 alloc_reg(current,i,dops[i].rt1);
1631 clear_const(current,dops[i].rs1);
1632 clear_const(current,dops[i].rt1);
1633 dirty_reg(current,dops[i].rt1);
1636 static void shiftimm_alloc(struct regstat *current,int i)
1638 if(dops[i].opcode2<=0x3) // SLL/SRL/SRA
1641 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1642 else dops[i].lt1=dops[i].rs1;
1643 alloc_reg(current,i,dops[i].rt1);
1644 dirty_reg(current,dops[i].rt1);
1645 if(is_const(current,dops[i].rs1)) {
1646 int v=get_const(current,dops[i].rs1);
1647 if(dops[i].opcode2==0x00) set_const(current,dops[i].rt1,v<<imm[i]);
1648 if(dops[i].opcode2==0x02) set_const(current,dops[i].rt1,(u_int)v>>imm[i]);
1649 if(dops[i].opcode2==0x03) set_const(current,dops[i].rt1,v>>imm[i]);
1651 else clear_const(current,dops[i].rt1);
1656 clear_const(current,dops[i].rs1);
1657 clear_const(current,dops[i].rt1);
1660 if(dops[i].opcode2>=0x38&&dops[i].opcode2<=0x3b) // DSLL/DSRL/DSRA
1664 if(dops[i].opcode2==0x3c) // DSLL32
1668 if(dops[i].opcode2==0x3e) // DSRL32
1672 if(dops[i].opcode2==0x3f) // DSRA32
1678 static void shift_alloc(struct regstat *current,int i)
1681 if(dops[i].opcode2<=0x07) // SLLV/SRLV/SRAV
1683 if(dops[i].rs1) alloc_reg(current,i,dops[i].rs1);
1684 if(dops[i].rs2) alloc_reg(current,i,dops[i].rs2);
1685 alloc_reg(current,i,dops[i].rt1);
1686 if(dops[i].rt1==dops[i].rs2) {
1687 alloc_reg_temp(current,i,-1);
1688 minimum_free_regs[i]=1;
1690 } else { // DSLLV/DSRLV/DSRAV
1693 clear_const(current,dops[i].rs1);
1694 clear_const(current,dops[i].rs2);
1695 clear_const(current,dops[i].rt1);
1696 dirty_reg(current,dops[i].rt1);
1700 static void alu_alloc(struct regstat *current,int i)
1702 if(dops[i].opcode2>=0x20&&dops[i].opcode2<=0x23) { // ADD/ADDU/SUB/SUBU
1704 if(dops[i].rs1&&dops[i].rs2) {
1705 alloc_reg(current,i,dops[i].rs1);
1706 alloc_reg(current,i,dops[i].rs2);
1709 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1710 if(dops[i].rs2&&needed_again(dops[i].rs2,i)) alloc_reg(current,i,dops[i].rs2);
1712 alloc_reg(current,i,dops[i].rt1);
1715 if(dops[i].opcode2==0x2a||dops[i].opcode2==0x2b) { // SLT/SLTU
1717 alloc_reg(current,i,dops[i].rs1);
1718 alloc_reg(current,i,dops[i].rs2);
1719 alloc_reg(current,i,dops[i].rt1);
1722 if(dops[i].opcode2>=0x24&&dops[i].opcode2<=0x27) { // AND/OR/XOR/NOR
1724 if(dops[i].rs1&&dops[i].rs2) {
1725 alloc_reg(current,i,dops[i].rs1);
1726 alloc_reg(current,i,dops[i].rs2);
1730 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1731 if(dops[i].rs2&&needed_again(dops[i].rs2,i)) alloc_reg(current,i,dops[i].rs2);
1733 alloc_reg(current,i,dops[i].rt1);
1736 if(dops[i].opcode2>=0x2c&&dops[i].opcode2<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1739 clear_const(current,dops[i].rs1);
1740 clear_const(current,dops[i].rs2);
1741 clear_const(current,dops[i].rt1);
1742 dirty_reg(current,dops[i].rt1);
1745 static void imm16_alloc(struct regstat *current,int i)
1747 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1748 else dops[i].lt1=dops[i].rs1;
1749 if(dops[i].rt1) alloc_reg(current,i,dops[i].rt1);
1750 if(dops[i].opcode==0x18||dops[i].opcode==0x19) { // DADDI/DADDIU
1753 else if(dops[i].opcode==0x0a||dops[i].opcode==0x0b) { // SLTI/SLTIU
1754 clear_const(current,dops[i].rs1);
1755 clear_const(current,dops[i].rt1);
1757 else if(dops[i].opcode>=0x0c&&dops[i].opcode<=0x0e) { // ANDI/ORI/XORI
1758 if(is_const(current,dops[i].rs1)) {
1759 int v=get_const(current,dops[i].rs1);
1760 if(dops[i].opcode==0x0c) set_const(current,dops[i].rt1,v&imm[i]);
1761 if(dops[i].opcode==0x0d) set_const(current,dops[i].rt1,v|imm[i]);
1762 if(dops[i].opcode==0x0e) set_const(current,dops[i].rt1,v^imm[i]);
1764 else clear_const(current,dops[i].rt1);
1766 else if(dops[i].opcode==0x08||dops[i].opcode==0x09) { // ADDI/ADDIU
1767 if(is_const(current,dops[i].rs1)) {
1768 int v=get_const(current,dops[i].rs1);
1769 set_const(current,dops[i].rt1,v+imm[i]);
1771 else clear_const(current,dops[i].rt1);
1774 set_const(current,dops[i].rt1,imm[i]<<16); // LUI
1776 dirty_reg(current,dops[i].rt1);
1779 static void load_alloc(struct regstat *current,int i)
1781 clear_const(current,dops[i].rt1);
1782 //if(dops[i].rs1!=dops[i].rt1&&needed_again(dops[i].rs1,i)) clear_const(current,dops[i].rs1); // Does this help or hurt?
1783 if(!dops[i].rs1) current->u&=~1LL; // Allow allocating r0 if it's the source register
1784 if (needed_again(dops[i].rs1, i))
1785 alloc_reg(current, i, dops[i].rs1);
1787 alloc_reg(current, i, ROREG);
1788 if(dops[i].rt1&&!((current->u>>dops[i].rt1)&1)) {
1789 alloc_reg(current,i,dops[i].rt1);
1790 assert(get_reg(current->regmap,dops[i].rt1)>=0);
1791 if(dops[i].opcode==0x27||dops[i].opcode==0x37) // LWU/LD
1795 else if(dops[i].opcode==0x1A||dops[i].opcode==0x1B) // LDL/LDR
1799 dirty_reg(current,dops[i].rt1);
1800 // LWL/LWR need a temporary register for the old value
1801 if(dops[i].opcode==0x22||dops[i].opcode==0x26)
1803 alloc_reg(current,i,FTEMP);
1804 alloc_reg_temp(current,i,-1);
1805 minimum_free_regs[i]=1;
1810 // Load to r0 or unneeded register (dummy load)
1811 // but we still need a register to calculate the address
1812 if(dops[i].opcode==0x22||dops[i].opcode==0x26)
1814 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1816 alloc_reg_temp(current,i,-1);
1817 minimum_free_regs[i]=1;
1818 if(dops[i].opcode==0x1A||dops[i].opcode==0x1B) // LDL/LDR
1825 void store_alloc(struct regstat *current,int i)
1827 clear_const(current,dops[i].rs2);
1828 if(!(dops[i].rs2)) current->u&=~1LL; // Allow allocating r0 if necessary
1829 if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1830 alloc_reg(current,i,dops[i].rs2);
1831 if(dops[i].opcode==0x2c||dops[i].opcode==0x2d||dops[i].opcode==0x3f) { // 64-bit SDL/SDR/SD
1835 alloc_reg(current, i, ROREG);
1836 #if defined(HOST_IMM8)
1837 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1838 alloc_reg(current, i, INVCP);
1840 if(dops[i].opcode==0x2a||dops[i].opcode==0x2e||dops[i].opcode==0x2c||dops[i].opcode==0x2d) { // SWL/SWL/SDL/SDR
1841 alloc_reg(current,i,FTEMP);
1843 // We need a temporary register for address generation
1844 alloc_reg_temp(current,i,-1);
1845 minimum_free_regs[i]=1;
1848 void c1ls_alloc(struct regstat *current,int i)
1850 clear_const(current,dops[i].rt1);
1851 alloc_reg(current,i,CSREG); // Status
1854 void c2ls_alloc(struct regstat *current,int i)
1856 clear_const(current,dops[i].rt1);
1857 if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1858 alloc_reg(current,i,FTEMP);
1860 alloc_reg(current, i, ROREG);
1861 #if defined(HOST_IMM8)
1862 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1863 if (dops[i].opcode == 0x3a) // SWC2
1864 alloc_reg(current,i,INVCP);
1866 // We need a temporary register for address generation
1867 alloc_reg_temp(current,i,-1);
1868 minimum_free_regs[i]=1;
1871 #ifndef multdiv_alloc
1872 void multdiv_alloc(struct regstat *current,int i)
1879 // case 0x1D: DMULTU
1882 clear_const(current,dops[i].rs1);
1883 clear_const(current,dops[i].rs2);
1884 alloc_cc(current,i); // for stalls
1885 if(dops[i].rs1&&dops[i].rs2)
1887 if((dops[i].opcode2&4)==0) // 32-bit
1889 current->u&=~(1LL<<HIREG);
1890 current->u&=~(1LL<<LOREG);
1891 alloc_reg(current,i,HIREG);
1892 alloc_reg(current,i,LOREG);
1893 alloc_reg(current,i,dops[i].rs1);
1894 alloc_reg(current,i,dops[i].rs2);
1895 dirty_reg(current,HIREG);
1896 dirty_reg(current,LOREG);
1905 // Multiply by zero is zero.
1906 // MIPS does not have a divide by zero exception.
1907 // The result is undefined, we return zero.
1908 alloc_reg(current,i,HIREG);
1909 alloc_reg(current,i,LOREG);
1910 dirty_reg(current,HIREG);
1911 dirty_reg(current,LOREG);
1916 void cop0_alloc(struct regstat *current,int i)
1918 if(dops[i].opcode2==0) // MFC0
1921 clear_const(current,dops[i].rt1);
1922 alloc_all(current,i);
1923 alloc_reg(current,i,dops[i].rt1);
1924 dirty_reg(current,dops[i].rt1);
1927 else if(dops[i].opcode2==4) // MTC0
1930 clear_const(current,dops[i].rs1);
1931 alloc_reg(current,i,dops[i].rs1);
1932 alloc_all(current,i);
1935 alloc_all(current,i); // FIXME: Keep r0
1937 alloc_reg(current,i,0);
1942 // TLBR/TLBWI/TLBWR/TLBP/ERET
1943 assert(dops[i].opcode2==0x10);
1944 alloc_all(current,i);
1946 minimum_free_regs[i]=HOST_REGS;
1949 static void cop2_alloc(struct regstat *current,int i)
1951 if (dops[i].opcode2 < 3) // MFC2/CFC2
1953 alloc_cc(current,i); // for stalls
1954 dirty_reg(current,CCREG);
1956 clear_const(current,dops[i].rt1);
1957 alloc_reg(current,i,dops[i].rt1);
1958 dirty_reg(current,dops[i].rt1);
1961 else if (dops[i].opcode2 > 3) // MTC2/CTC2
1964 clear_const(current,dops[i].rs1);
1965 alloc_reg(current,i,dops[i].rs1);
1969 alloc_reg(current,i,0);
1972 alloc_reg_temp(current,i,-1);
1973 minimum_free_regs[i]=1;
1976 void c2op_alloc(struct regstat *current,int i)
1978 alloc_cc(current,i); // for stalls
1979 dirty_reg(current,CCREG);
1980 alloc_reg_temp(current,i,-1);
1983 void syscall_alloc(struct regstat *current,int i)
1985 alloc_cc(current,i);
1986 dirty_reg(current,CCREG);
1987 alloc_all(current,i);
1988 minimum_free_regs[i]=HOST_REGS;
1992 void delayslot_alloc(struct regstat *current,int i)
1994 switch(dops[i].itype) {
2002 assem_debug("jump in the delay slot. this shouldn't happen.\n");//abort();
2003 SysPrintf("Disabled speculative precompilation\n");
2007 imm16_alloc(current,i);
2011 load_alloc(current,i);
2015 store_alloc(current,i);
2018 alu_alloc(current,i);
2021 shift_alloc(current,i);
2024 multdiv_alloc(current,i);
2027 shiftimm_alloc(current,i);
2030 mov_alloc(current,i);
2033 cop0_alloc(current,i);
2038 cop2_alloc(current,i);
2041 c1ls_alloc(current,i);
2044 c2ls_alloc(current,i);
2047 c2op_alloc(current,i);
2052 // Special case where a branch and delay slot span two pages in virtual memory
2053 static void pagespan_alloc(struct regstat *current,int i)
2056 current->wasconst=0;
2058 minimum_free_regs[i]=HOST_REGS;
2059 alloc_all(current,i);
2060 alloc_cc(current,i);
2061 dirty_reg(current,CCREG);
2062 if(dops[i].opcode==3) // JAL
2064 alloc_reg(current,i,31);
2065 dirty_reg(current,31);
2067 if(dops[i].opcode==0&&(dops[i].opcode2&0x3E)==8) // JR/JALR
2069 alloc_reg(current,i,dops[i].rs1);
2070 if (dops[i].rt1!=0) {
2071 alloc_reg(current,i,dops[i].rt1);
2072 dirty_reg(current,dops[i].rt1);
2075 if((dops[i].opcode&0x2E)==4) // BEQ/BNE/BEQL/BNEL
2077 if(dops[i].rs1) alloc_reg(current,i,dops[i].rs1);
2078 if(dops[i].rs2) alloc_reg(current,i,dops[i].rs2);
2081 if((dops[i].opcode&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
2083 if(dops[i].rs1) alloc_reg(current,i,dops[i].rs1);
2088 static void add_stub(enum stub_type type, void *addr, void *retaddr,
2089 u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e)
2091 assert(stubcount < ARRAY_SIZE(stubs));
2092 stubs[stubcount].type = type;
2093 stubs[stubcount].addr = addr;
2094 stubs[stubcount].retaddr = retaddr;
2095 stubs[stubcount].a = a;
2096 stubs[stubcount].b = b;
2097 stubs[stubcount].c = c;
2098 stubs[stubcount].d = d;
2099 stubs[stubcount].e = e;
2103 static void add_stub_r(enum stub_type type, void *addr, void *retaddr,
2104 int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist)
2106 add_stub(type, addr, retaddr, i, addr_reg, (uintptr_t)i_regs, ccadj, reglist);
2109 // Write out a single register
2110 static void wb_register(signed char r, const signed char regmap[], uint64_t dirty)
2113 for(hr=0;hr<HOST_REGS;hr++) {
2114 if(hr!=EXCLUDE_REG) {
2115 if((regmap[hr]&63)==r) {
2117 assert(regmap[hr]<64);
2118 emit_storereg(r,hr);
2125 static void wb_valid(signed char pre[],signed char entry[],u_int dirty_pre,u_int dirty,uint64_t u)
2127 //if(dirty_pre==dirty) return;
2129 for(hr=0;hr<HOST_REGS;hr++) {
2130 if(hr!=EXCLUDE_REG) {
2132 if(((~u)>>(reg&63))&1) {
2134 if(((dirty_pre&~dirty)>>hr)&1) {
2136 emit_storereg(reg,hr);
2149 static void pass_args(int a0, int a1)
2153 emit_mov(a0,2); emit_mov(a1,1); emit_mov(2,0);
2155 else if(a0!=0&&a1==0) {
2157 if (a0>=0) emit_mov(a0,0);
2160 if(a0>=0&&a0!=0) emit_mov(a0,0);
2161 if(a1>=0&&a1!=1) emit_mov(a1,1);
2165 static void alu_assemble(int i, const struct regstat *i_regs)
2167 if(dops[i].opcode2>=0x20&&dops[i].opcode2<=0x23) { // ADD/ADDU/SUB/SUBU
2169 signed char s1,s2,t;
2170 t=get_reg(i_regs->regmap,dops[i].rt1);
2172 s1=get_reg(i_regs->regmap,dops[i].rs1);
2173 s2=get_reg(i_regs->regmap,dops[i].rs2);
2174 if(dops[i].rs1&&dops[i].rs2) {
2177 if(dops[i].opcode2&2) emit_sub(s1,s2,t);
2178 else emit_add(s1,s2,t);
2180 else if(dops[i].rs1) {
2181 if(s1>=0) emit_mov(s1,t);
2182 else emit_loadreg(dops[i].rs1,t);
2184 else if(dops[i].rs2) {
2186 if(dops[i].opcode2&2) emit_neg(s2,t);
2187 else emit_mov(s2,t);
2190 emit_loadreg(dops[i].rs2,t);
2191 if(dops[i].opcode2&2) emit_neg(t,t);
2194 else emit_zeroreg(t);
2198 if(dops[i].opcode2>=0x2c&&dops[i].opcode2<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2201 if(dops[i].opcode2==0x2a||dops[i].opcode2==0x2b) { // SLT/SLTU
2203 signed char s1l,s2l,t;
2205 t=get_reg(i_regs->regmap,dops[i].rt1);
2208 s1l=get_reg(i_regs->regmap,dops[i].rs1);
2209 s2l=get_reg(i_regs->regmap,dops[i].rs2);
2210 if(dops[i].rs2==0) // rx<r0
2212 if(dops[i].opcode2==0x2a&&dops[i].rs1!=0) { // SLT
2214 emit_shrimm(s1l,31,t);
2216 else // SLTU (unsigned can not be less than zero, 0<0)
2219 else if(dops[i].rs1==0) // r0<rx
2222 if(dops[i].opcode2==0x2a) // SLT
2223 emit_set_gz32(s2l,t);
2224 else // SLTU (set if not zero)
2225 emit_set_nz32(s2l,t);
2228 assert(s1l>=0);assert(s2l>=0);
2229 if(dops[i].opcode2==0x2a) // SLT
2230 emit_set_if_less32(s1l,s2l,t);
2232 emit_set_if_carry32(s1l,s2l,t);
2238 if(dops[i].opcode2>=0x24&&dops[i].opcode2<=0x27) { // AND/OR/XOR/NOR
2240 signed char s1l,s2l,tl;
2241 tl=get_reg(i_regs->regmap,dops[i].rt1);
2244 s1l=get_reg(i_regs->regmap,dops[i].rs1);
2245 s2l=get_reg(i_regs->regmap,dops[i].rs2);
2246 if(dops[i].rs1&&dops[i].rs2) {
2249 if(dops[i].opcode2==0x24) { // AND
2250 emit_and(s1l,s2l,tl);
2252 if(dops[i].opcode2==0x25) { // OR
2253 emit_or(s1l,s2l,tl);
2255 if(dops[i].opcode2==0x26) { // XOR
2256 emit_xor(s1l,s2l,tl);
2258 if(dops[i].opcode2==0x27) { // NOR
2259 emit_or(s1l,s2l,tl);
2265 if(dops[i].opcode2==0x24) { // AND
2268 if(dops[i].opcode2==0x25||dops[i].opcode2==0x26) { // OR/XOR
2270 if(s1l>=0) emit_mov(s1l,tl);
2271 else emit_loadreg(dops[i].rs1,tl); // CHECK: regmap_entry?
2275 if(s2l>=0) emit_mov(s2l,tl);
2276 else emit_loadreg(dops[i].rs2,tl); // CHECK: regmap_entry?
2278 else emit_zeroreg(tl);
2280 if(dops[i].opcode2==0x27) { // NOR
2282 if(s1l>=0) emit_not(s1l,tl);
2284 emit_loadreg(dops[i].rs1,tl);
2290 if(s2l>=0) emit_not(s2l,tl);
2292 emit_loadreg(dops[i].rs2,tl);
2296 else emit_movimm(-1,tl);
2305 static void imm16_assemble(int i, const struct regstat *i_regs)
2307 if (dops[i].opcode==0x0f) { // LUI
2310 t=get_reg(i_regs->regmap,dops[i].rt1);
2313 if(!((i_regs->isconst>>t)&1))
2314 emit_movimm(imm[i]<<16,t);
2318 if(dops[i].opcode==0x08||dops[i].opcode==0x09) { // ADDI/ADDIU
2321 t=get_reg(i_regs->regmap,dops[i].rt1);
2322 s=get_reg(i_regs->regmap,dops[i].rs1);
2327 if(!((i_regs->isconst>>t)&1)) {
2329 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
2330 emit_addimm(t,imm[i],t);
2332 if(!((i_regs->wasconst>>s)&1))
2333 emit_addimm(s,imm[i],t);
2335 emit_movimm(constmap[i][s]+imm[i],t);
2341 if(!((i_regs->isconst>>t)&1))
2342 emit_movimm(imm[i],t);
2347 if(dops[i].opcode==0x18||dops[i].opcode==0x19) { // DADDI/DADDIU
2350 tl=get_reg(i_regs->regmap,dops[i].rt1);
2351 sl=get_reg(i_regs->regmap,dops[i].rs1);
2355 emit_addimm(sl,imm[i],tl);
2357 emit_movimm(imm[i],tl);
2362 else if(dops[i].opcode==0x0a||dops[i].opcode==0x0b) { // SLTI/SLTIU
2364 //assert(dops[i].rs1!=0); // r0 might be valid, but it's probably a bug
2366 t=get_reg(i_regs->regmap,dops[i].rt1);
2367 sl=get_reg(i_regs->regmap,dops[i].rs1);
2371 if(dops[i].opcode==0x0a) { // SLTI
2373 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
2374 emit_slti32(t,imm[i],t);
2376 emit_slti32(sl,imm[i],t);
2381 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
2382 emit_sltiu32(t,imm[i],t);
2384 emit_sltiu32(sl,imm[i],t);
2388 // SLTI(U) with r0 is just stupid,
2389 // nonetheless examples can be found
2390 if(dops[i].opcode==0x0a) // SLTI
2391 if(0<imm[i]) emit_movimm(1,t);
2392 else emit_zeroreg(t);
2395 if(imm[i]) emit_movimm(1,t);
2396 else emit_zeroreg(t);
2402 else if(dops[i].opcode>=0x0c&&dops[i].opcode<=0x0e) { // ANDI/ORI/XORI
2405 tl=get_reg(i_regs->regmap,dops[i].rt1);
2406 sl=get_reg(i_regs->regmap,dops[i].rs1);
2407 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2408 if(dops[i].opcode==0x0c) //ANDI
2412 if(i_regs->regmap_entry[tl]!=dops[i].rs1) emit_loadreg(dops[i].rs1,tl);
2413 emit_andimm(tl,imm[i],tl);
2415 if(!((i_regs->wasconst>>sl)&1))
2416 emit_andimm(sl,imm[i],tl);
2418 emit_movimm(constmap[i][sl]&imm[i],tl);
2428 if(i_regs->regmap_entry[tl]!=dops[i].rs1) emit_loadreg(dops[i].rs1,tl);
2430 if(dops[i].opcode==0x0d) { // ORI
2432 emit_orimm(tl,imm[i],tl);
2434 if(!((i_regs->wasconst>>sl)&1))
2435 emit_orimm(sl,imm[i],tl);
2437 emit_movimm(constmap[i][sl]|imm[i],tl);
2440 if(dops[i].opcode==0x0e) { // XORI
2442 emit_xorimm(tl,imm[i],tl);
2444 if(!((i_regs->wasconst>>sl)&1))
2445 emit_xorimm(sl,imm[i],tl);
2447 emit_movimm(constmap[i][sl]^imm[i],tl);
2452 emit_movimm(imm[i],tl);
2460 static void shiftimm_assemble(int i, const struct regstat *i_regs)
2462 if(dops[i].opcode2<=0x3) // SLL/SRL/SRA
2466 t=get_reg(i_regs->regmap,dops[i].rt1);
2467 s=get_reg(i_regs->regmap,dops[i].rs1);
2469 if(t>=0&&!((i_regs->isconst>>t)&1)){
2476 if(s<0&&i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
2478 if(dops[i].opcode2==0) // SLL
2480 emit_shlimm(s<0?t:s,imm[i],t);
2482 if(dops[i].opcode2==2) // SRL
2484 emit_shrimm(s<0?t:s,imm[i],t);
2486 if(dops[i].opcode2==3) // SRA
2488 emit_sarimm(s<0?t:s,imm[i],t);
2492 if(s>=0 && s!=t) emit_mov(s,t);
2496 //emit_storereg(dops[i].rt1,t); //DEBUG
2499 if(dops[i].opcode2>=0x38&&dops[i].opcode2<=0x3b) // DSLL/DSRL/DSRA
2503 if(dops[i].opcode2==0x3c) // DSLL32
2507 if(dops[i].opcode2==0x3e) // DSRL32
2511 if(dops[i].opcode2==0x3f) // DSRA32
2517 #ifndef shift_assemble
2518 static void shift_assemble(int i, const struct regstat *i_regs)
2520 signed char s,t,shift;
2521 if (dops[i].rt1 == 0)
2523 assert(dops[i].opcode2<=0x07); // SLLV/SRLV/SRAV
2524 t = get_reg(i_regs->regmap, dops[i].rt1);
2525 s = get_reg(i_regs->regmap, dops[i].rs1);
2526 shift = get_reg(i_regs->regmap, dops[i].rs2);
2532 else if(dops[i].rs2==0) {
2534 if(s!=t) emit_mov(s,t);
2537 host_tempreg_acquire();
2538 emit_andimm(shift,31,HOST_TEMPREG);
2539 switch(dops[i].opcode2) {
2541 emit_shl(s,HOST_TEMPREG,t);
2544 emit_shr(s,HOST_TEMPREG,t);
2547 emit_sar(s,HOST_TEMPREG,t);
2552 host_tempreg_release();
2566 static int get_ptr_mem_type(u_int a)
2568 if(a < 0x00200000) {
2569 if(a<0x1000&&((start>>20)==0xbfc||(start>>24)==0xa0))
2570 // return wrong, must use memhandler for BIOS self-test to pass
2571 // 007 does similar stuff from a00 mirror, weird stuff
2575 if(0x1f800000 <= a && a < 0x1f801000)
2577 if(0x80200000 <= a && a < 0x80800000)
2579 if(0xa0000000 <= a && a < 0xa0200000)
2584 static int get_ro_reg(const struct regstat *i_regs, int host_tempreg_free)
2586 int r = get_reg(i_regs->regmap, ROREG);
2587 if (r < 0 && host_tempreg_free) {
2588 host_tempreg_acquire();
2589 emit_loadreg(ROREG, r = HOST_TEMPREG);
2596 static void *emit_fastpath_cmp_jump(int i, const struct regstat *i_regs,
2597 int addr, int *offset_reg, int *addr_reg_override)
2601 int mr = dops[i].rs1;
2603 if(((smrv_strong|smrv_weak)>>mr)&1) {
2604 type=get_ptr_mem_type(smrv[mr]);
2605 //printf("set %08x @%08x r%d %d\n", smrv[mr], start+i*4, mr, type);
2608 // use the mirror we are running on
2609 type=get_ptr_mem_type(start);
2610 //printf("set nospec @%08x r%d %d\n", start+i*4, mr, type);
2613 if(type==MTYPE_8020) { // RAM 80200000+ mirror
2614 host_tempreg_acquire();
2615 emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
2616 addr=*addr_reg_override=HOST_TEMPREG;
2619 else if(type==MTYPE_0000) { // RAM 0 mirror
2620 host_tempreg_acquire();
2621 emit_orimm(addr,0x80000000,HOST_TEMPREG);
2622 addr=*addr_reg_override=HOST_TEMPREG;
2625 else if(type==MTYPE_A000) { // RAM A mirror
2626 host_tempreg_acquire();
2627 emit_andimm(addr,~0x20000000,HOST_TEMPREG);
2628 addr=*addr_reg_override=HOST_TEMPREG;
2631 else if(type==MTYPE_1F80) { // scratchpad
2632 if (psxH == (void *)0x1f800000) {
2633 host_tempreg_acquire();
2634 emit_xorimm(addr,0x1f800000,HOST_TEMPREG);
2635 emit_cmpimm(HOST_TEMPREG,0x1000);
2636 host_tempreg_release();
2641 // do the usual RAM check, jump will go to the right handler
2646 if (type == 0) // need ram check
2648 emit_cmpimm(addr,RAM_SIZE);
2650 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2651 // Hint to branch predictor that the branch is unlikely to be taken
2652 if (dops[i].rs1 >= 28)
2653 emit_jno_unlikely(0);
2657 if (ram_offset != 0)
2658 *offset_reg = get_ro_reg(i_regs, 0);
2664 // return memhandler, or get directly accessable address and return 0
2665 static void *get_direct_memhandler(void *table, u_int addr,
2666 enum stub_type type, uintptr_t *addr_host)
2668 uintptr_t msb = 1ull << (sizeof(uintptr_t)*8 - 1);
2669 uintptr_t l1, l2 = 0;
2670 l1 = ((uintptr_t *)table)[addr>>12];
2672 uintptr_t v = l1 << 1;
2673 *addr_host = v + addr;
2678 if (type == LOADB_STUB || type == LOADBU_STUB || type == STOREB_STUB)
2679 l2 = ((uintptr_t *)l1)[0x1000/4 + 0x1000/2 + (addr&0xfff)];
2680 else if (type == LOADH_STUB || type == LOADHU_STUB || type == STOREH_STUB)
2681 l2 = ((uintptr_t *)l1)[0x1000/4 + (addr&0xfff)/2];
2683 l2 = ((uintptr_t *)l1)[(addr&0xfff)/4];
2685 uintptr_t v = l2 << 1;
2686 *addr_host = v + (addr&0xfff);
2689 return (void *)(l2 << 1);
2693 static u_int get_host_reglist(const signed char *regmap)
2695 u_int reglist = 0, hr;
2696 for (hr = 0; hr < HOST_REGS; hr++) {
2697 if (hr != EXCLUDE_REG && regmap[hr] >= 0)
2703 static u_int reglist_exclude(u_int reglist, int r1, int r2)
2706 reglist &= ~(1u << r1);
2708 reglist &= ~(1u << r2);
2712 // find a temp caller-saved register not in reglist (so assumed to be free)
2713 static int reglist_find_free(u_int reglist)
2715 u_int free_regs = ~reglist & CALLER_SAVE_REGS;
2718 return __builtin_ctz(free_regs);
2721 static void do_load_word(int a, int rt, int offset_reg)
2723 if (offset_reg >= 0)
2724 emit_ldr_dualindexed(offset_reg, a, rt);
2726 emit_readword_indexed(0, a, rt);
2729 static void do_store_word(int a, int ofs, int rt, int offset_reg, int preseve_a)
2731 if (offset_reg < 0) {
2732 emit_writeword_indexed(rt, ofs, a);
2736 emit_addimm(a, ofs, a);
2737 emit_str_dualindexed(offset_reg, a, rt);
2738 if (ofs != 0 && preseve_a)
2739 emit_addimm(a, -ofs, a);
2742 static void do_store_hword(int a, int ofs, int rt, int offset_reg, int preseve_a)
2744 if (offset_reg < 0) {
2745 emit_writehword_indexed(rt, ofs, a);
2749 emit_addimm(a, ofs, a);
2750 emit_strh_dualindexed(offset_reg, a, rt);
2751 if (ofs != 0 && preseve_a)
2752 emit_addimm(a, -ofs, a);
2755 static void do_store_byte(int a, int rt, int offset_reg)
2757 if (offset_reg >= 0)
2758 emit_strb_dualindexed(offset_reg, a, rt);
2760 emit_writebyte_indexed(rt, 0, a);
2763 static void load_assemble(int i, const struct regstat *i_regs, int ccadj_)
2768 int memtarget=0,c=0;
2769 int offset_reg = -1;
2770 int fastio_reg_override = -1;
2771 u_int reglist=get_host_reglist(i_regs->regmap);
2772 tl=get_reg(i_regs->regmap,dops[i].rt1);
2773 s=get_reg(i_regs->regmap,dops[i].rs1);
2775 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2777 c=(i_regs->wasconst>>s)&1;
2779 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2782 //printf("load_assemble: c=%d\n",c);
2783 //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset);
2784 // FIXME: Even if the load is a NOP, we should check for pagefaults...
2785 if((tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80))
2787 // could be FIFO, must perform the read
2789 assem_debug("(forced read)\n");
2790 tl=get_reg(i_regs->regmap,-1);
2793 if(offset||s<0||c) addr=tl;
2795 //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2797 //printf("load_assemble: c=%d\n",c);
2798 //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset);
2799 assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2803 // Strmnnrmn's speed hack
2804 if(dops[i].rs1!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2807 jaddr = emit_fastpath_cmp_jump(i, i_regs, addr,
2808 &offset_reg, &fastio_reg_override);
2811 else if (ram_offset && memtarget) {
2812 offset_reg = get_ro_reg(i_regs, 0);
2814 int dummy=(dops[i].rt1==0)||(tl!=get_reg(i_regs->regmap,dops[i].rt1)); // ignore loads to r0 and unneeded reg
2815 switch (dops[i].opcode) {
2821 if (fastio_reg_override >= 0)
2822 a = fastio_reg_override;
2824 if (offset_reg >= 0)
2825 emit_ldrsb_dualindexed(offset_reg, a, tl);
2827 emit_movsbl_indexed(0, a, tl);
2830 add_stub_r(LOADB_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
2833 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
2840 if (fastio_reg_override >= 0)
2841 a = fastio_reg_override;
2842 if (offset_reg >= 0)
2843 emit_ldrsh_dualindexed(offset_reg, a, tl);
2845 emit_movswl_indexed(0, a, tl);
2848 add_stub_r(LOADH_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
2851 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
2857 if (fastio_reg_override >= 0)
2858 a = fastio_reg_override;
2859 do_load_word(a, tl, offset_reg);
2862 add_stub_r(LOADW_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
2865 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
2872 if (fastio_reg_override >= 0)
2873 a = fastio_reg_override;
2875 if (offset_reg >= 0)
2876 emit_ldrb_dualindexed(offset_reg, a, tl);
2878 emit_movzbl_indexed(0, a, tl);
2881 add_stub_r(LOADBU_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
2884 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
2891 if (fastio_reg_override >= 0)
2892 a = fastio_reg_override;
2893 if (offset_reg >= 0)
2894 emit_ldrh_dualindexed(offset_reg, a, tl);
2896 emit_movzwl_indexed(0, a, tl);
2899 add_stub_r(LOADHU_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
2902 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
2910 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
2911 host_tempreg_release();
2914 #ifndef loadlr_assemble
2915 static void loadlr_assemble(int i, const struct regstat *i_regs, int ccadj_)
2917 int s,tl,temp,temp2,addr;
2920 int memtarget=0,c=0;
2921 int offset_reg = -1;
2922 int fastio_reg_override = -1;
2923 u_int reglist=get_host_reglist(i_regs->regmap);
2924 tl=get_reg(i_regs->regmap,dops[i].rt1);
2925 s=get_reg(i_regs->regmap,dops[i].rs1);
2926 temp=get_reg(i_regs->regmap,-1);
2927 temp2=get_reg(i_regs->regmap,FTEMP);
2928 addr=get_reg(i_regs->regmap,AGEN1+(i&1));
2932 if(offset||s<0||c) addr=temp2;
2935 c=(i_regs->wasconst>>s)&1;
2937 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2941 emit_shlimm(addr,3,temp);
2942 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
2943 emit_andimm(addr,0xFFFFFFFC,temp2); // LWL/LWR
2945 emit_andimm(addr,0xFFFFFFF8,temp2); // LDL/LDR
2947 jaddr = emit_fastpath_cmp_jump(i, i_regs, temp2,
2948 &offset_reg, &fastio_reg_override);
2951 if (ram_offset && memtarget) {
2952 offset_reg = get_ro_reg(i_regs, 0);
2954 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
2955 emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR
2957 emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR
2960 if (dops[i].opcode==0x22||dops[i].opcode==0x26) { // LWL/LWR
2963 if (fastio_reg_override >= 0)
2964 a = fastio_reg_override;
2965 do_load_word(a, temp2, offset_reg);
2966 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
2967 host_tempreg_release();
2968 if(jaddr) add_stub_r(LOADW_STUB,jaddr,out,i,temp2,i_regs,ccadj_,reglist);
2971 inline_readstub(LOADW_STUB,i,(constmap[i][s]+offset)&0xFFFFFFFC,i_regs->regmap,FTEMP,ccadj_,reglist);
2974 emit_andimm(temp,24,temp);
2975 if (dops[i].opcode==0x22) // LWL
2976 emit_xorimm(temp,24,temp);
2977 host_tempreg_acquire();
2978 emit_movimm(-1,HOST_TEMPREG);
2979 if (dops[i].opcode==0x26) {
2980 emit_shr(temp2,temp,temp2);
2981 emit_bic_lsr(tl,HOST_TEMPREG,temp,tl);
2983 emit_shl(temp2,temp,temp2);
2984 emit_bic_lsl(tl,HOST_TEMPREG,temp,tl);
2986 host_tempreg_release();
2987 emit_or(temp2,tl,tl);
2989 //emit_storereg(dops[i].rt1,tl); // DEBUG
2991 if (dops[i].opcode==0x1A||dops[i].opcode==0x1B) { // LDL/LDR
2997 static void store_assemble(int i, const struct regstat *i_regs, int ccadj_)
3003 enum stub_type type=0;
3004 int memtarget=0,c=0;
3005 int agr=AGEN1+(i&1);
3006 int offset_reg = -1;
3007 int fastio_reg_override = -1;
3008 u_int reglist=get_host_reglist(i_regs->regmap);
3009 tl=get_reg(i_regs->regmap,dops[i].rs2);
3010 s=get_reg(i_regs->regmap,dops[i].rs1);
3011 temp=get_reg(i_regs->regmap,agr);
3012 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3015 c=(i_regs->wasconst>>s)&1;
3017 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3022 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3023 if(offset||s<0||c) addr=temp;
3026 jaddr = emit_fastpath_cmp_jump(i, i_regs, addr,
3027 &offset_reg, &fastio_reg_override);
3029 else if (ram_offset && memtarget) {
3030 offset_reg = get_ro_reg(i_regs, 0);
3033 switch (dops[i].opcode) {
3038 if (fastio_reg_override >= 0)
3039 a = fastio_reg_override;
3040 do_store_byte(a, tl, offset_reg);
3048 if (fastio_reg_override >= 0)
3049 a = fastio_reg_override;
3050 do_store_hword(a, 0, tl, offset_reg, 1);
3057 if (fastio_reg_override >= 0)
3058 a = fastio_reg_override;
3059 do_store_word(a, 0, tl, offset_reg, 1);
3067 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
3068 host_tempreg_release();
3070 // PCSX store handlers don't check invcode again
3072 add_stub_r(type,jaddr,out,i,addr,i_regs,ccadj_,reglist);
3075 if(!(i_regs->waswritten&(1<<dops[i].rs1)) && !HACK_ENABLED(NDHACK_NO_SMC_CHECK)) {
3077 #ifdef DESTRUCTIVE_SHIFT
3078 // The x86 shift operation is 'destructive'; it overwrites the
3079 // source register, so we need to make a copy first and use that.
3082 #if defined(HOST_IMM8)
3083 int ir=get_reg(i_regs->regmap,INVCP);
3085 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3087 emit_cmpmem_indexedsr12_imm(invalid_code,addr,1);
3089 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3090 emit_callne(invalidate_addr_reg[addr]);
3094 add_stub(INVCODE_STUB,jaddr2,out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3098 u_int addr_val=constmap[i][s]+offset;
3100 add_stub_r(type,jaddr,out,i,addr,i_regs,ccadj_,reglist);
3101 } else if(c&&!memtarget) {
3102 inline_writestub(type,i,addr_val,i_regs->regmap,dops[i].rs2,ccadj_,reglist);
3104 // basic current block modification detection..
3105 // not looking back as that should be in mips cache already
3106 // (see Spyro2 title->attract mode)
3107 if(c&&start+i*4<addr_val&&addr_val<start+slen*4) {
3108 SysPrintf("write to %08x hits block %08x, pc=%08x\n",addr_val,start,start+i*4);
3109 assert(i_regs->regmap==regs[i].regmap); // not delay slot
3110 if(i_regs->regmap==regs[i].regmap) {
3111 load_all_consts(regs[i].regmap_entry,regs[i].wasdirty,i);
3112 wb_dirtys(regs[i].regmap_entry,regs[i].wasdirty);
3113 emit_movimm(start+i*4+4,0);
3114 emit_writeword(0,&pcaddr);
3115 emit_addimm(HOST_CCREG,2,HOST_CCREG);
3116 emit_far_call(get_addr_ht);
3122 static void storelr_assemble(int i, const struct regstat *i_regs, int ccadj_)
3128 void *case1, *case23, *case3;
3129 void *done0, *done1, *done2;
3130 int memtarget=0,c=0;
3131 int agr=AGEN1+(i&1);
3132 int offset_reg = -1;
3133 u_int reglist=get_host_reglist(i_regs->regmap);
3134 tl=get_reg(i_regs->regmap,dops[i].rs2);
3135 s=get_reg(i_regs->regmap,dops[i].rs1);
3136 temp=get_reg(i_regs->regmap,agr);
3137 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3140 c=(i_regs->isconst>>s)&1;
3142 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3148 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3149 if(!offset&&s!=temp) emit_mov(s,temp);
3155 if(!memtarget||!dops[i].rs1) {
3161 offset_reg = get_ro_reg(i_regs, 0);
3163 if (dops[i].opcode==0x2C||dops[i].opcode==0x2D) { // SDL/SDR
3167 emit_testimm(temp,2);
3170 emit_testimm(temp,1);
3174 if (dops[i].opcode == 0x2A) { // SWL
3175 // Write msb into least significant byte
3176 if (dops[i].rs2) emit_rorimm(tl, 24, tl);
3177 do_store_byte(temp, tl, offset_reg);
3178 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3180 else if (dops[i].opcode == 0x2E) { // SWR
3181 // Write entire word
3182 do_store_word(temp, 0, tl, offset_reg, 1);
3187 set_jump_target(case1, out);
3188 if (dops[i].opcode == 0x2A) { // SWL
3189 // Write two msb into two least significant bytes
3190 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
3191 do_store_hword(temp, -1, tl, offset_reg, 0);
3192 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
3194 else if (dops[i].opcode == 0x2E) { // SWR
3195 // Write 3 lsb into three most significant bytes
3196 do_store_byte(temp, tl, offset_reg);
3197 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3198 do_store_hword(temp, 1, tl, offset_reg, 0);
3199 if (dops[i].rs2) emit_rorimm(tl, 24, tl);
3204 set_jump_target(case23, out);
3205 emit_testimm(temp,1);
3209 if (dops[i].opcode==0x2A) { // SWL
3210 // Write 3 msb into three least significant bytes
3211 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3212 do_store_hword(temp, -2, tl, offset_reg, 1);
3213 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
3214 do_store_byte(temp, tl, offset_reg);
3215 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3217 else if (dops[i].opcode == 0x2E) { // SWR
3218 // Write two lsb into two most significant bytes
3219 do_store_hword(temp, 0, tl, offset_reg, 1);
3224 set_jump_target(case3, out);
3225 if (dops[i].opcode == 0x2A) { // SWL
3226 do_store_word(temp, -3, tl, offset_reg, 0);
3228 else if (dops[i].opcode == 0x2E) { // SWR
3229 do_store_byte(temp, tl, offset_reg);
3231 set_jump_target(done0, out);
3232 set_jump_target(done1, out);
3233 set_jump_target(done2, out);
3234 if (offset_reg == HOST_TEMPREG)
3235 host_tempreg_release();
3237 add_stub_r(STORELR_STUB,jaddr,out,i,temp,i_regs,ccadj_,reglist);
3238 if(!(i_regs->waswritten&(1<<dops[i].rs1)) && !HACK_ENABLED(NDHACK_NO_SMC_CHECK)) {
3239 #if defined(HOST_IMM8)
3240 int ir=get_reg(i_regs->regmap,INVCP);
3242 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3244 emit_cmpmem_indexedsr12_imm(invalid_code,temp,1);
3246 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3247 emit_callne(invalidate_addr_reg[temp]);
3251 add_stub(INVCODE_STUB,jaddr2,out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3256 static void cop0_assemble(int i, const struct regstat *i_regs, int ccadj_)
3258 if(dops[i].opcode2==0) // MFC0
3260 signed char t=get_reg(i_regs->regmap,dops[i].rt1);
3261 u_int copr=(source[i]>>11)&0x1f;
3262 //assert(t>=0); // Why does this happen? OOT is weird
3263 if(t>=0&&dops[i].rt1!=0) {
3264 emit_readword(®_cop0[copr],t);
3267 else if(dops[i].opcode2==4) // MTC0
3269 signed char s=get_reg(i_regs->regmap,dops[i].rs1);
3270 char copr=(source[i]>>11)&0x1f;
3272 wb_register(dops[i].rs1,i_regs->regmap,i_regs->dirty);
3273 if(copr==9||copr==11||copr==12||copr==13) {
3274 emit_readword(&last_count,HOST_TEMPREG);
3275 emit_loadreg(CCREG,HOST_CCREG); // TODO: do proper reg alloc
3276 emit_add(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
3277 emit_addimm(HOST_CCREG,ccadj_,HOST_CCREG);
3278 emit_writeword(HOST_CCREG,&Count);
3280 // What a mess. The status register (12) can enable interrupts,
3281 // so needs a special case to handle a pending interrupt.
3282 // The interrupt must be taken immediately, because a subsequent
3283 // instruction might disable interrupts again.
3284 if(copr==12||copr==13) {
3286 // burn cycles to cause cc_interrupt, which will
3287 // reschedule next_interupt. Relies on CCREG from above.
3288 assem_debug("MTC0 DS %d\n", copr);
3289 emit_writeword(HOST_CCREG,&last_count);
3290 emit_movimm(0,HOST_CCREG);
3291 emit_storereg(CCREG,HOST_CCREG);
3292 emit_loadreg(dops[i].rs1,1);
3293 emit_movimm(copr,0);
3294 emit_far_call(pcsx_mtc0_ds);
3295 emit_loadreg(dops[i].rs1,s);
3298 emit_movimm(start+i*4+4,HOST_TEMPREG);
3299 emit_writeword(HOST_TEMPREG,&pcaddr);
3300 emit_movimm(0,HOST_TEMPREG);
3301 emit_writeword(HOST_TEMPREG,&pending_exception);
3304 emit_loadreg(dops[i].rs1,1);
3307 emit_movimm(copr,0);
3308 emit_far_call(pcsx_mtc0);
3309 if(copr==9||copr==11||copr==12||copr==13) {
3310 emit_readword(&Count,HOST_CCREG);
3311 emit_readword(&next_interupt,HOST_TEMPREG);
3312 emit_addimm(HOST_CCREG,-ccadj_,HOST_CCREG);
3313 emit_sub(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
3314 emit_writeword(HOST_TEMPREG,&last_count);
3315 emit_storereg(CCREG,HOST_CCREG);
3317 if(copr==12||copr==13) {
3318 assert(!is_delayslot);
3319 emit_readword(&pending_exception,14);
3323 emit_readword(&pcaddr, 0);
3324 emit_addimm(HOST_CCREG,2,HOST_CCREG);
3325 emit_far_call(get_addr_ht);
3327 set_jump_target(jaddr, out);
3329 emit_loadreg(dops[i].rs1,s);
3333 assert(dops[i].opcode2==0x10);
3334 //if((source[i]&0x3f)==0x10) // RFE
3336 emit_readword(&Status,0);
3337 emit_andimm(0,0x3c,1);
3338 emit_andimm(0,~0xf,0);
3339 emit_orrshr_imm(1,2,0);
3340 emit_writeword(0,&Status);
3345 static void cop1_unusable(int i, const struct regstat *i_regs)
3347 // XXX: should just just do the exception instead
3352 add_stub_r(FP_STUB,jaddr,out,i,0,i_regs,is_delayslot,0);
3356 static void cop1_assemble(int i, const struct regstat *i_regs)
3358 cop1_unusable(i, i_regs);
3361 static void c1ls_assemble(int i, const struct regstat *i_regs)
3363 cop1_unusable(i, i_regs);
3367 static void do_cop1stub(int n)
3370 assem_debug("do_cop1stub %x\n",start+stubs[n].a*4);
3371 set_jump_target(stubs[n].addr, out);
3373 // int rs=stubs[n].b;
3374 struct regstat *i_regs=(struct regstat *)stubs[n].c;
3377 load_all_consts(regs[i].regmap_entry,regs[i].wasdirty,i);
3378 //if(i_regs!=®s[i]) printf("oops: regs[i]=%x i_regs=%x",(int)®s[i],(int)i_regs);
3380 //else {printf("fp exception in delay slot\n");}
3381 wb_dirtys(i_regs->regmap_entry,i_regs->wasdirty);
3382 if(regs[i].regmap_entry[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
3383 emit_movimm(start+(i-ds)*4,EAX); // Get PC
3384 emit_addimm(HOST_CCREG,ccadj[i],HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
3385 emit_far_jump(ds?fp_exception_ds:fp_exception);
3388 static int cop2_is_stalling_op(int i, int *cycles)
3390 if (dops[i].opcode == 0x3a) { // SWC2
3394 if (dops[i].itype == COP2 && (dops[i].opcode2 == 0 || dops[i].opcode2 == 2)) { // MFC2/CFC2
3398 if (dops[i].itype == C2OP) {
3399 *cycles = gte_cycletab[source[i] & 0x3f];
3402 // ... what about MTC2/CTC2/LWC2?
3407 static void log_gte_stall(int stall, u_int cycle)
3409 if ((u_int)stall <= 44)
3410 printf("x stall %2d %u\n", stall, cycle + last_count);
3413 static void emit_log_gte_stall(int i, int stall, u_int reglist)
3417 emit_movimm(stall, 0);
3419 emit_mov(HOST_TEMPREG, 0);
3420 emit_addimm(HOST_CCREG, ccadj[i], 1);
3421 emit_far_call(log_gte_stall);
3422 restore_regs(reglist);
3426 static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist)
3428 int j = i, other_gte_op_cycles = -1, stall = -MAXBLOCK, cycles_passed;
3429 int rtmp = reglist_find_free(reglist);
3431 if (HACK_ENABLED(NDHACK_NO_STALLS))
3433 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) {
3434 // happens occasionally... cc evicted? Don't bother then
3435 //printf("no cc %08x\n", start + i*4);
3439 for (j = i - 1; j >= 0; j--) {
3440 //if (dops[j].is_ds) break;
3441 if (cop2_is_stalling_op(j, &other_gte_op_cycles) || dops[j].bt)
3443 if (j > 0 && ccadj[j - 1] > ccadj[j])
3448 cycles_passed = ccadj[i] - ccadj[j];
3449 if (other_gte_op_cycles >= 0)
3450 stall = other_gte_op_cycles - cycles_passed;
3451 else if (cycles_passed >= 44)
3452 stall = 0; // can't stall
3453 if (stall == -MAXBLOCK && rtmp >= 0) {
3454 // unknown stall, do the expensive runtime check
3455 assem_debug("; cop2_do_stall_check\n");
3458 emit_movimm(gte_cycletab[op], 0);
3459 emit_addimm(HOST_CCREG, ccadj[i], 1);
3460 emit_far_call(call_gteStall);
3461 restore_regs(reglist);
3463 host_tempreg_acquire();
3464 emit_readword(&psxRegs.gteBusyCycle, rtmp);
3465 emit_addimm(rtmp, -ccadj[i], rtmp);
3466 emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG);
3467 emit_cmpimm(HOST_TEMPREG, 44);
3468 emit_cmovb_reg(rtmp, HOST_CCREG);
3469 //emit_log_gte_stall(i, 0, reglist);
3470 host_tempreg_release();
3473 else if (stall > 0) {
3474 //emit_log_gte_stall(i, stall, reglist);
3475 emit_addimm(HOST_CCREG, stall, HOST_CCREG);
3478 // save gteBusyCycle, if needed
3479 if (gte_cycletab[op] == 0)
3481 other_gte_op_cycles = -1;
3482 for (j = i + 1; j < slen; j++) {
3483 if (cop2_is_stalling_op(j, &other_gte_op_cycles))
3485 if (dops[j].is_jump) {
3487 if (j + 1 < slen && cop2_is_stalling_op(j + 1, &other_gte_op_cycles))
3492 if (other_gte_op_cycles >= 0)
3493 // will handle stall when assembling that op
3495 cycles_passed = ccadj[min(j, slen -1)] - ccadj[i];
3496 if (cycles_passed >= 44)
3498 assem_debug("; save gteBusyCycle\n");
3499 host_tempreg_acquire();
3501 emit_readword(&last_count, HOST_TEMPREG);
3502 emit_add(HOST_TEMPREG, HOST_CCREG, HOST_TEMPREG);
3503 emit_addimm(HOST_TEMPREG, ccadj[i], HOST_TEMPREG);
3504 emit_addimm(HOST_TEMPREG, gte_cycletab[op]), HOST_TEMPREG);
3505 emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle);
3507 emit_addimm(HOST_CCREG, ccadj[i] + gte_cycletab[op], HOST_TEMPREG);
3508 emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle);
3510 host_tempreg_release();
3513 static int is_mflohi(int i)
3515 return (dops[i].itype == MOV && (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG));
3518 static int check_multdiv(int i, int *cycles)
3520 if (dops[i].itype != MULTDIV)
3522 if (dops[i].opcode2 == 0x18 || dops[i].opcode2 == 0x19) // MULT(U)
3523 *cycles = 11; // approx from 7 11 14
3529 static void multdiv_prepare_stall(int i, const struct regstat *i_regs, int ccadj_)
3531 int j, found = 0, c = 0;
3532 if (HACK_ENABLED(NDHACK_NO_STALLS))
3534 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) {
3535 // happens occasionally... cc evicted? Don't bother then
3538 for (j = i + 1; j < slen; j++) {
3541 if ((found = is_mflohi(j)))
3543 if (dops[j].is_jump) {
3545 if (j + 1 < slen && (found = is_mflohi(j + 1)))
3551 // handle all in multdiv_do_stall()
3553 check_multdiv(i, &c);
3555 assem_debug("; muldiv prepare stall %d\n", c);
3556 host_tempreg_acquire();
3557 emit_addimm(HOST_CCREG, ccadj_ + c, HOST_TEMPREG);
3558 emit_writeword(HOST_TEMPREG, &psxRegs.muldivBusyCycle);
3559 host_tempreg_release();
3562 static void multdiv_do_stall(int i, const struct regstat *i_regs)
3564 int j, known_cycles = 0;
3565 u_int reglist = get_host_reglist(i_regs->regmap);
3566 int rtmp = get_reg(i_regs->regmap, -1);
3568 rtmp = reglist_find_free(reglist);
3569 if (HACK_ENABLED(NDHACK_NO_STALLS))
3571 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG || rtmp < 0) {
3572 // happens occasionally... cc evicted? Don't bother then
3573 //printf("no cc/rtmp %08x\n", start + i*4);
3577 for (j = i - 1; j >= 0; j--) {
3578 if (dops[j].is_ds) break;
3579 if (check_multdiv(j, &known_cycles))
3582 // already handled by this op
3584 if (dops[j].bt || (j > 0 && ccadj[j - 1] > ccadj[j]))
3589 if (known_cycles > 0) {
3590 known_cycles -= ccadj[i] - ccadj[j];
3591 assem_debug("; muldiv stall resolved %d\n", known_cycles);
3592 if (known_cycles > 0)
3593 emit_addimm(HOST_CCREG, known_cycles, HOST_CCREG);
3596 assem_debug("; muldiv stall unresolved\n");
3597 host_tempreg_acquire();
3598 emit_readword(&psxRegs.muldivBusyCycle, rtmp);
3599 emit_addimm(rtmp, -ccadj[i], rtmp);
3600 emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG);
3601 emit_cmpimm(HOST_TEMPREG, 37);
3602 emit_cmovb_reg(rtmp, HOST_CCREG);
3603 //emit_log_gte_stall(i, 0, reglist);
3604 host_tempreg_release();
3607 static void cop2_get_dreg(u_int copr,signed char tl,signed char temp)
3617 emit_readword(®_cop2d[copr],tl);
3618 emit_signextend16(tl,tl);
3619 emit_writeword(tl,®_cop2d[copr]); // hmh
3626 emit_readword(®_cop2d[copr],tl);
3627 emit_andimm(tl,0xffff,tl);
3628 emit_writeword(tl,®_cop2d[copr]);
3631 emit_readword(®_cop2d[14],tl); // SXY2
3632 emit_writeword(tl,®_cop2d[copr]);
3636 c2op_mfc2_29_assemble(tl,temp);
3639 emit_readword(®_cop2d[copr],tl);
3644 static void cop2_put_dreg(u_int copr,signed char sl,signed char temp)
3648 emit_readword(®_cop2d[13],temp); // SXY1
3649 emit_writeword(sl,®_cop2d[copr]);
3650 emit_writeword(temp,®_cop2d[12]); // SXY0
3651 emit_readword(®_cop2d[14],temp); // SXY2
3652 emit_writeword(sl,®_cop2d[14]);
3653 emit_writeword(temp,®_cop2d[13]); // SXY1
3656 emit_andimm(sl,0x001f,temp);
3657 emit_shlimm(temp,7,temp);
3658 emit_writeword(temp,®_cop2d[9]);
3659 emit_andimm(sl,0x03e0,temp);
3660 emit_shlimm(temp,2,temp);
3661 emit_writeword(temp,®_cop2d[10]);
3662 emit_andimm(sl,0x7c00,temp);
3663 emit_shrimm(temp,3,temp);
3664 emit_writeword(temp,®_cop2d[11]);
3665 emit_writeword(sl,®_cop2d[28]);
3668 emit_xorsar_imm(sl,sl,31,temp);
3669 #if defined(HAVE_ARMV5) || defined(__aarch64__)
3670 emit_clz(temp,temp);
3672 emit_movs(temp,HOST_TEMPREG);
3673 emit_movimm(0,temp);
3674 emit_jeq((int)out+4*4);
3675 emit_addpl_imm(temp,1,temp);
3676 emit_lslpls_imm(HOST_TEMPREG,1,HOST_TEMPREG);
3677 emit_jns((int)out-2*4);
3679 emit_writeword(sl,®_cop2d[30]);
3680 emit_writeword(temp,®_cop2d[31]);
3685 emit_writeword(sl,®_cop2d[copr]);
3690 static void c2ls_assemble(int i, const struct regstat *i_regs, int ccadj_)
3695 int memtarget=0,c=0;
3697 enum stub_type type;
3698 int agr=AGEN1+(i&1);
3699 int offset_reg = -1;
3700 int fastio_reg_override = -1;
3701 u_int reglist=get_host_reglist(i_regs->regmap);
3702 u_int copr=(source[i]>>16)&0x1f;
3703 s=get_reg(i_regs->regmap,dops[i].rs1);
3704 tl=get_reg(i_regs->regmap,FTEMP);
3706 assert(dops[i].rs1>0);
3709 if(i_regs->regmap[HOST_CCREG]==CCREG)
3710 reglist&=~(1<<HOST_CCREG);
3713 if (dops[i].opcode==0x3a) { // SWC2
3714 ar=get_reg(i_regs->regmap,agr);
3715 if(ar<0) ar=get_reg(i_regs->regmap,-1);
3720 if(s>=0) c=(i_regs->wasconst>>s)&1;
3721 memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
3722 if (!offset&&!c&&s>=0) ar=s;
3725 cop2_do_stall_check(0, i, i_regs, reglist);
3727 if (dops[i].opcode==0x3a) { // SWC2
3728 cop2_get_dreg(copr,tl,-1);
3736 emit_jmp(0); // inline_readstub/inline_writestub?
3740 jaddr2 = emit_fastpath_cmp_jump(i, i_regs, ar,
3741 &offset_reg, &fastio_reg_override);
3743 else if (ram_offset && memtarget) {
3744 offset_reg = get_ro_reg(i_regs, 0);
3746 switch (dops[i].opcode) {
3747 case 0x32: { // LWC2
3749 if (fastio_reg_override >= 0)
3750 a = fastio_reg_override;
3751 do_load_word(a, tl, offset_reg);
3754 case 0x3a: { // SWC2
3755 #ifdef DESTRUCTIVE_SHIFT
3756 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3759 if (fastio_reg_override >= 0)
3760 a = fastio_reg_override;
3761 do_store_word(a, 0, tl, offset_reg, 1);
3768 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
3769 host_tempreg_release();
3771 add_stub_r(type,jaddr2,out,i,ar,i_regs,ccadj_,reglist);
3772 if(dops[i].opcode==0x3a) // SWC2
3773 if(!(i_regs->waswritten&(1<<dops[i].rs1)) && !HACK_ENABLED(NDHACK_NO_SMC_CHECK)) {
3774 #if defined(HOST_IMM8)
3775 int ir=get_reg(i_regs->regmap,INVCP);
3777 emit_cmpmem_indexedsr12_reg(ir,ar,1);
3779 emit_cmpmem_indexedsr12_imm(invalid_code,ar,1);
3781 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3782 emit_callne(invalidate_addr_reg[ar]);
3786 add_stub(INVCODE_STUB,jaddr3,out,reglist|(1<<HOST_CCREG),ar,0,0,0);
3789 if (dops[i].opcode==0x32) { // LWC2
3790 host_tempreg_acquire();
3791 cop2_put_dreg(copr,tl,HOST_TEMPREG);
3792 host_tempreg_release();
3796 static void cop2_assemble(int i, const struct regstat *i_regs)
3798 u_int copr = (source[i]>>11) & 0x1f;
3799 signed char temp = get_reg(i_regs->regmap, -1);
3801 if (!HACK_ENABLED(NDHACK_NO_STALLS)) {
3802 u_int reglist = reglist_exclude(get_host_reglist(i_regs->regmap), temp, -1);
3803 if (dops[i].opcode2 == 0 || dops[i].opcode2 == 2) { // MFC2/CFC2
3804 signed char tl = get_reg(i_regs->regmap, dops[i].rt1);
3805 reglist = reglist_exclude(reglist, tl, -1);
3807 cop2_do_stall_check(0, i, i_regs, reglist);
3809 if (dops[i].opcode2==0) { // MFC2
3810 signed char tl=get_reg(i_regs->regmap,dops[i].rt1);
3811 if(tl>=0&&dops[i].rt1!=0)
3812 cop2_get_dreg(copr,tl,temp);
3814 else if (dops[i].opcode2==4) { // MTC2
3815 signed char sl=get_reg(i_regs->regmap,dops[i].rs1);
3816 cop2_put_dreg(copr,sl,temp);
3818 else if (dops[i].opcode2==2) // CFC2
3820 signed char tl=get_reg(i_regs->regmap,dops[i].rt1);
3821 if(tl>=0&&dops[i].rt1!=0)
3822 emit_readword(®_cop2c[copr],tl);
3824 else if (dops[i].opcode2==6) // CTC2
3826 signed char sl=get_reg(i_regs->regmap,dops[i].rs1);
3835 emit_signextend16(sl,temp);
3838 c2op_ctc2_31_assemble(sl,temp);
3844 emit_writeword(temp,®_cop2c[copr]);
3849 static void do_unalignedwritestub(int n)
3851 assem_debug("do_unalignedwritestub %x\n",start+stubs[n].a*4);
3853 set_jump_target(stubs[n].addr, out);
3856 struct regstat *i_regs=(struct regstat *)stubs[n].c;
3857 int addr=stubs[n].b;
3858 u_int reglist=stubs[n].e;
3859 signed char *i_regmap=i_regs->regmap;
3860 int temp2=get_reg(i_regmap,FTEMP);
3862 rt=get_reg(i_regmap,dops[i].rs2);
3865 assert(dops[i].opcode==0x2a||dops[i].opcode==0x2e); // SWL/SWR only implemented
3867 reglist&=~(1<<temp2);
3869 // don't bother with it and call write handler
3872 int cc=get_reg(i_regmap,CCREG);
3874 emit_loadreg(CCREG,2);
3875 emit_addimm(cc<0?2:cc,(int)stubs[n].d+1,2);
3876 emit_far_call((dops[i].opcode==0x2a?jump_handle_swl:jump_handle_swr));
3877 emit_addimm(0,-((int)stubs[n].d+1),cc<0?2:cc);
3879 emit_storereg(CCREG,2);
3880 restore_regs(reglist);
3881 emit_jmp(stubs[n].retaddr); // return address
3884 #ifndef multdiv_assemble
3885 void multdiv_assemble(int i,struct regstat *i_regs)
3887 printf("Need multdiv_assemble for this architecture.\n");
3892 static void mov_assemble(int i, const struct regstat *i_regs)
3894 //if(dops[i].opcode2==0x10||dops[i].opcode2==0x12) { // MFHI/MFLO
3895 //if(dops[i].opcode2==0x11||dops[i].opcode2==0x13) { // MTHI/MTLO
3898 tl=get_reg(i_regs->regmap,dops[i].rt1);
3901 sl=get_reg(i_regs->regmap,dops[i].rs1);
3902 if(sl>=0) emit_mov(sl,tl);
3903 else emit_loadreg(dops[i].rs1,tl);
3906 if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) // MFHI/MFLO
3907 multdiv_do_stall(i, i_regs);
3910 // call interpreter, exception handler, things that change pc/regs/cycles ...
3911 static void call_c_cpu_handler(int i, const struct regstat *i_regs, int ccadj_, u_int pc, void *func)
3913 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3914 assert(ccreg==HOST_CCREG);
3915 assert(!is_delayslot);
3918 emit_movimm(pc,3); // Get PC
3919 emit_readword(&last_count,2);
3920 emit_writeword(3,&psxRegs.pc);
3921 emit_addimm(HOST_CCREG,ccadj_,HOST_CCREG);
3922 emit_add(2,HOST_CCREG,2);
3923 emit_writeword(2,&psxRegs.cycle);
3924 emit_far_call(func);
3925 emit_far_jump(jump_to_new_pc);
3928 static void syscall_assemble(int i, const struct regstat *i_regs, int ccadj_)
3930 emit_movimm(0x20,0); // cause code
3931 emit_movimm(0,1); // not in delay slot
3932 call_c_cpu_handler(i, i_regs, ccadj_, start+i*4, psxException);
3935 static void hlecall_assemble(int i, const struct regstat *i_regs, int ccadj_)
3937 void *hlefunc = psxNULL;
3938 uint32_t hleCode = source[i] & 0x03ffffff;
3939 if (hleCode < ARRAY_SIZE(psxHLEt))
3940 hlefunc = psxHLEt[hleCode];
3942 call_c_cpu_handler(i, i_regs, ccadj_, start + i*4+4, hlefunc);
3945 static void intcall_assemble(int i, const struct regstat *i_regs, int ccadj_)
3947 call_c_cpu_handler(i, i_regs, ccadj_, start + i*4, execI);
3950 static void speculate_mov(int rs,int rt)
3953 smrv_strong_next|=1<<rt;
3958 static void speculate_mov_weak(int rs,int rt)
3961 smrv_weak_next|=1<<rt;
3966 static void speculate_register_values(int i)
3969 memcpy(smrv,psxRegs.GPR.r,sizeof(smrv));
3970 // gp,sp are likely to stay the same throughout the block
3971 smrv_strong_next=(1<<28)|(1<<29)|(1<<30);
3972 smrv_weak_next=~smrv_strong_next;
3973 //printf(" llr %08x\n", smrv[4]);
3975 smrv_strong=smrv_strong_next;
3976 smrv_weak=smrv_weak_next;
3977 switch(dops[i].itype) {
3979 if ((smrv_strong>>dops[i].rs1)&1) speculate_mov(dops[i].rs1,dops[i].rt1);
3980 else if((smrv_strong>>dops[i].rs2)&1) speculate_mov(dops[i].rs2,dops[i].rt1);
3981 else if((smrv_weak>>dops[i].rs1)&1) speculate_mov_weak(dops[i].rs1,dops[i].rt1);
3982 else if((smrv_weak>>dops[i].rs2)&1) speculate_mov_weak(dops[i].rs2,dops[i].rt1);
3984 smrv_strong_next&=~(1<<dops[i].rt1);
3985 smrv_weak_next&=~(1<<dops[i].rt1);
3989 smrv_strong_next&=~(1<<dops[i].rt1);
3990 smrv_weak_next&=~(1<<dops[i].rt1);
3993 if(dops[i].rt1&&is_const(®s[i],dops[i].rt1)) {
3994 int value,hr=get_reg(regs[i].regmap,dops[i].rt1);
3996 if(get_final_value(hr,i,&value))
3997 smrv[dops[i].rt1]=value;
3998 else smrv[dops[i].rt1]=constmap[i][hr];
3999 smrv_strong_next|=1<<dops[i].rt1;
4003 if ((smrv_strong>>dops[i].rs1)&1) speculate_mov(dops[i].rs1,dops[i].rt1);
4004 else if((smrv_weak>>dops[i].rs1)&1) speculate_mov_weak(dops[i].rs1,dops[i].rt1);
4008 if(start<0x2000&&(dops[i].rt1==26||(smrv[dops[i].rt1]>>24)==0xa0)) {
4009 // special case for BIOS
4010 smrv[dops[i].rt1]=0xa0000000;
4011 smrv_strong_next|=1<<dops[i].rt1;
4018 smrv_strong_next&=~(1<<dops[i].rt1);
4019 smrv_weak_next&=~(1<<dops[i].rt1);
4023 if(dops[i].opcode2==0||dops[i].opcode2==2) { // MFC/CFC
4024 smrv_strong_next&=~(1<<dops[i].rt1);
4025 smrv_weak_next&=~(1<<dops[i].rt1);
4029 if (dops[i].opcode==0x32) { // LWC2
4030 smrv_strong_next&=~(1<<dops[i].rt1);
4031 smrv_weak_next&=~(1<<dops[i].rt1);
4037 printf("x %08x %08x %d %d c %08x %08x\n",smrv[r],start+i*4,
4038 ((smrv_strong>>r)&1),(smrv_weak>>r)&1,regs[i].isconst,regs[i].wasconst);
4042 static void ujump_assemble(int i, const struct regstat *i_regs);
4043 static void rjump_assemble(int i, const struct regstat *i_regs);
4044 static void cjump_assemble(int i, const struct regstat *i_regs);
4045 static void sjump_assemble(int i, const struct regstat *i_regs);
4046 static void pagespan_assemble(int i, const struct regstat *i_regs);
4048 static int assemble(int i, const struct regstat *i_regs, int ccadj_)
4051 switch (dops[i].itype) {
4053 alu_assemble(i, i_regs);
4056 imm16_assemble(i, i_regs);
4059 shift_assemble(i, i_regs);
4062 shiftimm_assemble(i, i_regs);
4065 load_assemble(i, i_regs, ccadj_);
4068 loadlr_assemble(i, i_regs, ccadj_);
4071 store_assemble(i, i_regs, ccadj_);
4074 storelr_assemble(i, i_regs, ccadj_);
4077 cop0_assemble(i, i_regs, ccadj_);
4080 cop1_assemble(i, i_regs);
4083 c1ls_assemble(i, i_regs);
4086 cop2_assemble(i, i_regs);
4089 c2ls_assemble(i, i_regs, ccadj_);
4092 c2op_assemble(i, i_regs);
4095 multdiv_assemble(i, i_regs);
4096 multdiv_prepare_stall(i, i_regs, ccadj_);
4099 mov_assemble(i, i_regs);
4102 syscall_assemble(i, i_regs, ccadj_);
4105 hlecall_assemble(i, i_regs, ccadj_);
4108 intcall_assemble(i, i_regs, ccadj_);
4111 ujump_assemble(i, i_regs);
4115 rjump_assemble(i, i_regs);
4119 cjump_assemble(i, i_regs);
4123 sjump_assemble(i, i_regs);
4127 pagespan_assemble(i, i_regs);
4132 // not handled, just skip
4140 static void ds_assemble(int i, const struct regstat *i_regs)
4142 speculate_register_values(i);
4144 switch (dops[i].itype) {
4153 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
4156 assemble(i, i_regs, ccadj[i]);
4161 // Is the branch target a valid internal jump?
4162 static int internal_branch(int addr)
4164 if(addr&1) return 0; // Indirect (register) jump
4165 if(addr>=start && addr<start+slen*4-4)
4172 static void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t u)
4175 for(hr=0;hr<HOST_REGS;hr++) {
4176 if(hr!=EXCLUDE_REG) {
4177 if(pre[hr]!=entry[hr]) {
4180 if(get_reg(entry,pre[hr])<0) {
4182 if(!((u>>pre[hr])&1))
4183 emit_storereg(pre[hr],hr);
4190 // Move from one register to another (no writeback)
4191 for(hr=0;hr<HOST_REGS;hr++) {
4192 if(hr!=EXCLUDE_REG) {
4193 if(pre[hr]!=entry[hr]) {
4194 if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
4196 if((nr=get_reg(entry,pre[hr]))>=0) {
4205 // Load the specified registers
4206 // This only loads the registers given as arguments because
4207 // we don't want to load things that will be overwritten
4208 static void load_regs(signed char entry[],signed char regmap[],int rs1,int rs2)
4212 for(hr=0;hr<HOST_REGS;hr++) {
4213 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4214 if(entry[hr]!=regmap[hr]) {
4215 if(regmap[hr]==rs1||regmap[hr]==rs2)
4222 emit_loadreg(regmap[hr],hr);
4230 // Load registers prior to the start of a loop
4231 // so that they are not loaded within the loop
4232 static void loop_preload(signed char pre[],signed char entry[])
4235 for(hr=0;hr<HOST_REGS;hr++) {
4236 if(hr!=EXCLUDE_REG) {
4237 if(pre[hr]!=entry[hr]) {
4239 if(get_reg(pre,entry[hr])<0) {
4240 assem_debug("loop preload:\n");
4241 //printf("loop preload: %d\n",hr);
4245 else if(entry[hr]<TEMPREG)
4247 emit_loadreg(entry[hr],hr);
4249 else if(entry[hr]-64<TEMPREG)
4251 emit_loadreg(entry[hr],hr);
4260 // Generate address for load/store instruction
4261 // goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
4262 void address_generation(int i, const struct regstat *i_regs, signed char entry[])
4264 if (dops[i].is_load || dops[i].is_store) {
4266 int agr=AGEN1+(i&1);
4267 if(dops[i].itype==LOAD) {
4268 ra=get_reg(i_regs->regmap,dops[i].rt1);
4269 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4272 if(dops[i].itype==LOADLR) {
4273 ra=get_reg(i_regs->regmap,FTEMP);
4275 if(dops[i].itype==STORE||dops[i].itype==STORELR) {
4276 ra=get_reg(i_regs->regmap,agr);
4277 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4279 if(dops[i].itype==C2LS) {
4280 if ((dops[i].opcode&0x3b)==0x31||(dops[i].opcode&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
4281 ra=get_reg(i_regs->regmap,FTEMP);
4282 else { // SWC1/SDC1/SWC2/SDC2
4283 ra=get_reg(i_regs->regmap,agr);
4284 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4287 int rs=get_reg(i_regs->regmap,dops[i].rs1);
4290 int c=(i_regs->wasconst>>rs)&1;
4291 if(dops[i].rs1==0) {
4292 // Using r0 as a base address
4293 if(!entry||entry[ra]!=agr) {
4294 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
4295 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4296 }else if (dops[i].opcode==0x1a||dops[i].opcode==0x1b) {
4297 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4299 emit_movimm(offset,ra);
4301 } // else did it in the previous cycle
4304 if(!entry||entry[ra]!=dops[i].rs1)
4305 emit_loadreg(dops[i].rs1,ra);
4306 //if(!entry||entry[ra]!=dops[i].rs1)
4307 // printf("poor load scheduling!\n");
4310 if(dops[i].rs1!=dops[i].rt1||dops[i].itype!=LOAD) {
4311 if(!entry||entry[ra]!=agr) {
4312 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
4313 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4314 }else if (dops[i].opcode==0x1a||dops[i].opcode==0x1b) {
4315 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4317 emit_movimm(constmap[i][rs]+offset,ra);
4318 regs[i].loadedconst|=1<<ra;
4320 } // else did it in the previous cycle
4321 } // else load_consts already did it
4323 if(offset&&!c&&dops[i].rs1) {
4325 emit_addimm(rs,offset,ra);
4327 emit_addimm(ra,offset,ra);
4332 // Preload constants for next instruction
4333 if (dops[i+1].is_load || dops[i+1].is_store) {
4336 agr=AGEN1+((i+1)&1);
4337 ra=get_reg(i_regs->regmap,agr);
4339 int rs=get_reg(regs[i+1].regmap,dops[i+1].rs1);
4340 int offset=imm[i+1];
4341 int c=(regs[i+1].wasconst>>rs)&1;
4342 if(c&&(dops[i+1].rs1!=dops[i+1].rt1||dops[i+1].itype!=LOAD)) {
4343 if (dops[i+1].opcode==0x22||dops[i+1].opcode==0x26) {
4344 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4345 }else if (dops[i+1].opcode==0x1a||dops[i+1].opcode==0x1b) {
4346 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4348 emit_movimm(constmap[i+1][rs]+offset,ra);
4349 regs[i+1].loadedconst|=1<<ra;
4352 else if(dops[i+1].rs1==0) {
4353 // Using r0 as a base address
4354 if (dops[i+1].opcode==0x22||dops[i+1].opcode==0x26) {
4355 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4356 }else if (dops[i+1].opcode==0x1a||dops[i+1].opcode==0x1b) {
4357 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4359 emit_movimm(offset,ra);
4366 static int get_final_value(int hr, int i, int *value)
4368 int reg=regs[i].regmap[hr];
4370 if(regs[i+1].regmap[hr]!=reg) break;
4371 if(!((regs[i+1].isconst>>hr)&1)) break;
4372 if(dops[i+1].bt) break;
4376 if (dops[i].is_jump) {
4377 *value=constmap[i][hr];
4381 if (dops[i+1].is_jump) {
4382 // Load in delay slot, out-of-order execution
4383 if(dops[i+2].itype==LOAD&&dops[i+2].rs1==reg&&dops[i+2].rt1==reg&&((regs[i+1].wasconst>>hr)&1))
4385 // Precompute load address
4386 *value=constmap[i][hr]+imm[i+2];
4390 if(dops[i+1].itype==LOAD&&dops[i+1].rs1==reg&&dops[i+1].rt1==reg)
4392 // Precompute load address
4393 *value=constmap[i][hr]+imm[i+1];
4394 //printf("c=%x imm=%lx\n",(long)constmap[i][hr],imm[i+1]);
4399 *value=constmap[i][hr];
4400 //printf("c=%lx\n",(long)constmap[i][hr]);
4401 if(i==slen-1) return 1;
4403 return !((unneeded_reg[i+1]>>reg)&1);
4406 // Load registers with known constants
4407 static void load_consts(signed char pre[],signed char regmap[],int i)
4410 // propagate loaded constant flags
4411 if(i==0||dops[i].bt)
4412 regs[i].loadedconst=0;
4414 for(hr=0;hr<HOST_REGS;hr++) {
4415 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((regs[i-1].isconst>>hr)&1)&&pre[hr]==regmap[hr]
4416 &®map[hr]==regs[i-1].regmap[hr]&&((regs[i-1].loadedconst>>hr)&1))
4418 regs[i].loadedconst|=1<<hr;
4423 for(hr=0;hr<HOST_REGS;hr++) {
4424 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4425 //if(entry[hr]!=regmap[hr]) {
4426 if(!((regs[i].loadedconst>>hr)&1)) {
4427 assert(regmap[hr]<64);
4428 if(((regs[i].isconst>>hr)&1)&®map[hr]>0) {
4429 int value,similar=0;
4430 if(get_final_value(hr,i,&value)) {
4431 // see if some other register has similar value
4432 for(hr2=0;hr2<HOST_REGS;hr2++) {
4433 if(hr2!=EXCLUDE_REG&&((regs[i].loadedconst>>hr2)&1)) {
4434 if(is_similar_value(value,constmap[i][hr2])) {
4442 if(get_final_value(hr2,i,&value2)) // is this needed?
4443 emit_movimm_from(value2,hr2,value,hr);
4445 emit_movimm(value,hr);
4451 emit_movimm(value,hr);
4454 regs[i].loadedconst|=1<<hr;
4461 static void load_all_consts(const signed char regmap[], u_int dirty, int i)
4465 for(hr=0;hr<HOST_REGS;hr++) {
4466 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) {
4467 assert(regmap[hr] < 64);
4468 if(((regs[i].isconst>>hr)&1)&®map[hr]>0) {
4469 int value=constmap[i][hr];
4474 emit_movimm(value,hr);
4481 // Write out all dirty registers (except cycle count)
4482 static void wb_dirtys(const signed char i_regmap[], uint64_t i_dirty)
4485 for(hr=0;hr<HOST_REGS;hr++) {
4486 if(hr!=EXCLUDE_REG) {
4487 if(i_regmap[hr]>0) {
4488 if(i_regmap[hr]!=CCREG) {
4489 if((i_dirty>>hr)&1) {
4490 assert(i_regmap[hr]<64);
4491 emit_storereg(i_regmap[hr],hr);
4499 // Write out dirty registers that we need to reload (pair with load_needed_regs)
4500 // This writes the registers not written by store_regs_bt
4501 static void wb_needed_dirtys(const signed char i_regmap[], uint64_t i_dirty, int addr)
4504 int t=(addr-start)>>2;
4505 for(hr=0;hr<HOST_REGS;hr++) {
4506 if(hr!=EXCLUDE_REG) {
4507 if(i_regmap[hr]>0) {
4508 if(i_regmap[hr]!=CCREG) {
4509 if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1)) {
4510 if((i_dirty>>hr)&1) {
4511 assert(i_regmap[hr]<64);
4512 emit_storereg(i_regmap[hr],hr);
4521 // Load all registers (except cycle count)
4522 static void load_all_regs(const signed char i_regmap[])
4525 for(hr=0;hr<HOST_REGS;hr++) {
4526 if(hr!=EXCLUDE_REG) {
4527 if(i_regmap[hr]==0) {
4531 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4533 emit_loadreg(i_regmap[hr],hr);
4539 // Load all current registers also needed by next instruction
4540 static void load_needed_regs(const signed char i_regmap[], const signed char next_regmap[])
4543 for(hr=0;hr<HOST_REGS;hr++) {
4544 if(hr!=EXCLUDE_REG) {
4545 if(get_reg(next_regmap,i_regmap[hr])>=0) {
4546 if(i_regmap[hr]==0) {
4550 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4552 emit_loadreg(i_regmap[hr],hr);
4559 // Load all regs, storing cycle count if necessary
4560 static void load_regs_entry(int t)
4563 if(dops[t].is_ds) emit_addimm(HOST_CCREG,CLOCK_ADJUST(1),HOST_CCREG);
4564 else if(ccadj[t]) emit_addimm(HOST_CCREG,-ccadj[t],HOST_CCREG);
4565 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4566 emit_storereg(CCREG,HOST_CCREG);
4569 for(hr=0;hr<HOST_REGS;hr++) {
4570 if(regs[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) {
4571 if(regs[t].regmap_entry[hr]==0) {
4574 else if(regs[t].regmap_entry[hr]!=CCREG)
4576 emit_loadreg(regs[t].regmap_entry[hr],hr);
4582 // Store dirty registers prior to branch
4583 void store_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
4585 if(internal_branch(addr))
4587 int t=(addr-start)>>2;
4589 for(hr=0;hr<HOST_REGS;hr++) {
4590 if(hr!=EXCLUDE_REG) {
4591 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4592 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1)) {
4593 if((i_dirty>>hr)&1) {
4594 assert(i_regmap[hr]<64);
4595 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4596 emit_storereg(i_regmap[hr],hr);
4605 // Branch out of this block, write out all dirty regs
4606 wb_dirtys(i_regmap,i_dirty);
4610 // Load all needed registers for branch target
4611 static void load_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
4613 //if(addr>=start && addr<(start+slen*4))
4614 if(internal_branch(addr))
4616 int t=(addr-start)>>2;
4618 // Store the cycle count before loading something else
4619 if(i_regmap[HOST_CCREG]!=CCREG) {
4620 assert(i_regmap[HOST_CCREG]==-1);
4622 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4623 emit_storereg(CCREG,HOST_CCREG);
4626 for(hr=0;hr<HOST_REGS;hr++) {
4627 if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) {
4628 if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4629 if(regs[t].regmap_entry[hr]==0) {
4632 else if(regs[t].regmap_entry[hr]!=CCREG)
4634 emit_loadreg(regs[t].regmap_entry[hr],hr);
4642 static int match_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
4644 if(addr>=start && addr<start+slen*4-4)
4646 int t=(addr-start)>>2;
4648 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4649 for(hr=0;hr<HOST_REGS;hr++)
4653 if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4655 if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
4662 if(i_regmap[hr]<TEMPREG)
4664 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4667 else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
4673 else // Same register but is it 32-bit or dirty?
4676 if(!((regs[t].dirty>>hr)&1))
4680 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4682 //printf("%x: dirty no match\n",addr);
4690 // Delay slots are not valid branch targets
4691 //if(t>0&&(dops[t-1].is_jump) return 0;
4692 // Delay slots require additional processing, so do not match
4693 if(dops[t].is_ds) return 0;
4698 for(hr=0;hr<HOST_REGS;hr++)
4704 if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4719 static void drc_dbg_emit_do_cmp(int i, int ccadj_)
4721 extern void do_insn_cmp();
4723 u_int hr, reglist = get_host_reglist(regs[i].regmap);
4725 assem_debug("//do_insn_cmp %08x\n", start+i*4);
4727 // write out changed consts to match the interpreter
4728 if (i > 0 && !dops[i].bt) {
4729 for (hr = 0; hr < HOST_REGS; hr++) {
4730 int reg = regs[i].regmap_entry[hr]; // regs[i-1].regmap[hr];
4731 if (hr == EXCLUDE_REG || reg < 0)
4733 if (!((regs[i-1].isconst >> hr) & 1))
4735 if (i > 1 && reg == regs[i-2].regmap[hr] && constmap[i-1][hr] == constmap[i-2][hr])
4737 emit_movimm(constmap[i-1][hr],0);
4738 emit_storereg(reg, 0);
4741 emit_movimm(start+i*4,0);
4742 emit_writeword(0,&pcaddr);
4743 int cc = get_reg(regs[i].regmap_entry, CCREG);
4745 emit_loadreg(CCREG, cc = 0);
4746 emit_addimm(cc, ccadj_, 0);
4747 emit_writeword(0, &psxRegs.cycle);
4748 emit_far_call(do_insn_cmp);
4749 //emit_readword(&cycle,0);
4750 //emit_addimm(0,2,0);
4751 //emit_writeword(0,&cycle);
4753 restore_regs(reglist);
4754 assem_debug("\\\\do_insn_cmp\n");
4757 #define drc_dbg_emit_do_cmp(x,y)
4760 // Used when a branch jumps into the delay slot of another branch
4761 static void ds_assemble_entry(int i)
4763 int t = (ba[i] - start) >> 2;
4764 int ccadj_ = -CLOCK_ADJUST(1);
4766 instr_addr[t] = out;
4767 assem_debug("Assemble delay slot at %x\n",ba[i]);
4768 assem_debug("<->\n");
4769 drc_dbg_emit_do_cmp(t, ccadj_);
4770 if(regs[t].regmap_entry[HOST_CCREG]==CCREG&®s[t].regmap[HOST_CCREG]!=CCREG)
4771 wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty);
4772 load_regs(regs[t].regmap_entry,regs[t].regmap,dops[t].rs1,dops[t].rs2);
4773 address_generation(t,®s[t],regs[t].regmap_entry);
4774 if (ram_offset && (dops[t].is_load || dops[t].is_store))
4775 load_regs(regs[t].regmap_entry,regs[t].regmap,ROREG,ROREG);
4776 if (dops[t].is_store)
4777 load_regs(regs[t].regmap_entry,regs[t].regmap,INVCP,INVCP);
4779 switch (dops[t].itype) {
4788 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
4791 assemble(t, ®s[t], ccadj_);
4793 store_regs_bt(regs[t].regmap,regs[t].dirty,ba[i]+4);
4794 load_regs_bt(regs[t].regmap,regs[t].dirty,ba[i]+4);
4795 if(internal_branch(ba[i]+4))
4796 assem_debug("branch: internal\n");
4798 assem_debug("branch: external\n");
4799 assert(internal_branch(ba[i]+4));
4800 add_to_linker(out,ba[i]+4,internal_branch(ba[i]+4));
4804 static void emit_extjump(void *addr, u_int target)
4806 emit_extjump2(addr, target, dyna_linker);
4809 static void emit_extjump_ds(void *addr, u_int target)
4811 emit_extjump2(addr, target, dyna_linker_ds);
4814 // Load 2 immediates optimizing for small code size
4815 static void emit_mov2imm_compact(int imm1,u_int rt1,int imm2,u_int rt2)
4817 emit_movimm(imm1,rt1);
4818 emit_movimm_from(imm1,rt1,imm2,rt2);
4821 static void do_cc(int i, const signed char i_regmap[], int *adj,
4822 int addr, int taken, int invert)
4824 int count, count_plus2;
4828 if(dops[i].itype==RJUMP)
4832 //if(ba[i]>=start && ba[i]<(start+slen*4))
4833 if(internal_branch(ba[i]))
4836 if(dops[t].is_ds) *adj=-CLOCK_ADJUST(1); // Branch into delay slot adds an extra cycle
4844 count_plus2 = count + CLOCK_ADJUST(2);
4845 if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4847 if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
4849 //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4850 emit_andimm(HOST_CCREG,3,HOST_CCREG);
4854 else if(*adj==0||invert) {
4855 int cycles = count_plus2;
4860 if(-NO_CYCLE_PENALTY_THR<rel&&rel<0)
4861 cycles=*adj+count+2-*adj;
4864 emit_addimm_and_set_flags(cycles, HOST_CCREG);
4870 emit_cmpimm(HOST_CCREG, -count_plus2);
4874 add_stub(CC_STUB,jaddr,idle?idle:out,(*adj==0||invert||idle)?0:count_plus2,i,addr,taken,0);
4877 static void do_ccstub(int n)
4880 assem_debug("do_ccstub %x\n",start+(u_int)stubs[n].b*4);
4881 set_jump_target(stubs[n].addr, out);
4883 if(stubs[n].d==NULLDS) {
4884 // Delay slot instruction is nullified ("likely" branch)
4885 wb_dirtys(regs[i].regmap,regs[i].dirty);
4887 else if(stubs[n].d!=TAKEN) {
4888 wb_dirtys(branch_regs[i].regmap,branch_regs[i].dirty);
4891 if(internal_branch(ba[i]))
4892 wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
4896 // Save PC as return address
4897 emit_movimm(stubs[n].c,EAX);
4898 emit_writeword(EAX,&pcaddr);
4902 // Return address depends on which way the branch goes
4903 if(dops[i].itype==CJUMP||dops[i].itype==SJUMP)
4905 int s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
4906 int s2l=get_reg(branch_regs[i].regmap,dops[i].rs2);
4912 else if(dops[i].rs2==0)
4917 #ifdef DESTRUCTIVE_WRITEBACK
4919 if((branch_regs[i].dirty>>s1l)&&1)
4920 emit_loadreg(dops[i].rs1,s1l);
4923 if((branch_regs[i].dirty>>s1l)&1)
4924 emit_loadreg(dops[i].rs2,s1l);
4927 if((branch_regs[i].dirty>>s2l)&1)
4928 emit_loadreg(dops[i].rs2,s2l);
4931 int addr=-1,alt=-1,ntaddr=-1;
4934 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4935 (branch_regs[i].regmap[hr]&63)!=dops[i].rs1 &&
4936 (branch_regs[i].regmap[hr]&63)!=dops[i].rs2 )
4944 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4945 (branch_regs[i].regmap[hr]&63)!=dops[i].rs1 &&
4946 (branch_regs[i].regmap[hr]&63)!=dops[i].rs2 )
4952 if((dops[i].opcode&0x2E)==6) // BLEZ/BGTZ needs another register
4956 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4957 (branch_regs[i].regmap[hr]&63)!=dops[i].rs1 &&
4958 (branch_regs[i].regmap[hr]&63)!=dops[i].rs2 )
4964 assert(hr<HOST_REGS);
4966 if((dops[i].opcode&0x2f)==4) // BEQ
4968 #ifdef HAVE_CMOV_IMM
4969 if(s2l>=0) emit_cmp(s1l,s2l);
4970 else emit_test(s1l,s1l);
4971 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
4973 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4974 if(s2l>=0) emit_cmp(s1l,s2l);
4975 else emit_test(s1l,s1l);
4976 emit_cmovne_reg(alt,addr);
4979 if((dops[i].opcode&0x2f)==5) // BNE
4981 #ifdef HAVE_CMOV_IMM
4982 if(s2l>=0) emit_cmp(s1l,s2l);
4983 else emit_test(s1l,s1l);
4984 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
4986 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
4987 if(s2l>=0) emit_cmp(s1l,s2l);
4988 else emit_test(s1l,s1l);
4989 emit_cmovne_reg(alt,addr);
4992 if((dops[i].opcode&0x2f)==6) // BLEZ
4994 //emit_movimm(ba[i],alt);
4995 //emit_movimm(start+i*4+8,addr);
4996 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4998 emit_cmovl_reg(alt,addr);
5000 if((dops[i].opcode&0x2f)==7) // BGTZ
5002 //emit_movimm(ba[i],addr);
5003 //emit_movimm(start+i*4+8,ntaddr);
5004 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
5006 emit_cmovl_reg(ntaddr,addr);
5008 if((dops[i].opcode==1)&&(dops[i].opcode2&0x2D)==0) // BLTZ
5010 //emit_movimm(ba[i],alt);
5011 //emit_movimm(start+i*4+8,addr);
5012 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5014 emit_cmovs_reg(alt,addr);
5016 if((dops[i].opcode==1)&&(dops[i].opcode2&0x2D)==1) // BGEZ
5018 //emit_movimm(ba[i],addr);
5019 //emit_movimm(start+i*4+8,alt);
5020 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5022 emit_cmovs_reg(alt,addr);
5024 if(dops[i].opcode==0x11 && dops[i].opcode2==0x08 ) {
5025 if(source[i]&0x10000) // BC1T
5027 //emit_movimm(ba[i],alt);
5028 //emit_movimm(start+i*4+8,addr);
5029 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5030 emit_testimm(s1l,0x800000);
5031 emit_cmovne_reg(alt,addr);
5035 //emit_movimm(ba[i],addr);
5036 //emit_movimm(start+i*4+8,alt);
5037 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5038 emit_testimm(s1l,0x800000);
5039 emit_cmovne_reg(alt,addr);
5042 emit_writeword(addr,&pcaddr);
5045 if(dops[i].itype==RJUMP)
5047 int r=get_reg(branch_regs[i].regmap,dops[i].rs1);
5048 if (ds_writes_rjump_rs(i)) {
5049 r=get_reg(branch_regs[i].regmap,RTEMP);
5051 emit_writeword(r,&pcaddr);
5053 else {SysPrintf("Unknown branch type in do_ccstub\n");abort();}
5055 // Update cycle count
5056 assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
5057 if(stubs[n].a) emit_addimm(HOST_CCREG,(int)stubs[n].a,HOST_CCREG);
5058 emit_far_call(cc_interrupt);
5059 if(stubs[n].a) emit_addimm(HOST_CCREG,-(int)stubs[n].a,HOST_CCREG);
5060 if(stubs[n].d==TAKEN) {
5061 if(internal_branch(ba[i]))
5062 load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
5063 else if(dops[i].itype==RJUMP) {
5064 if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
5065 emit_readword(&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
5067 emit_loadreg(dops[i].rs1,get_reg(branch_regs[i].regmap,dops[i].rs1));
5069 }else if(stubs[n].d==NOTTAKEN) {
5070 if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5071 else load_all_regs(branch_regs[i].regmap);
5072 }else if(stubs[n].d==NULLDS) {
5073 // Delay slot instruction is nullified ("likely" branch)
5074 if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
5075 else load_all_regs(regs[i].regmap);
5077 load_all_regs(branch_regs[i].regmap);
5079 if (stubs[n].retaddr)
5080 emit_jmp(stubs[n].retaddr);
5082 do_jump_vaddr(stubs[n].e);
5085 static void add_to_linker(void *addr, u_int target, int ext)
5087 assert(linkcount < ARRAY_SIZE(link_addr));
5088 link_addr[linkcount].addr = addr;
5089 link_addr[linkcount].target = target;
5090 link_addr[linkcount].ext = ext;
5094 static void ujump_assemble_write_ra(int i)
5097 unsigned int return_address;
5098 rt=get_reg(branch_regs[i].regmap,31);
5099 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5101 return_address=start+i*4+8;
5104 if(internal_branch(return_address)&&dops[i+1].rt1!=31) {
5105 int temp=-1; // note: must be ds-safe
5109 if(temp>=0) do_miniht_insert(return_address,rt,temp);
5110 else emit_movimm(return_address,rt);
5118 if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
5121 emit_movimm(return_address,rt); // PC into link register
5123 emit_prefetch(hash_table_get(return_address));
5129 static void ujump_assemble(int i, const struct regstat *i_regs)
5132 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5133 address_generation(i+1,i_regs,regs[i].regmap_entry);
5135 int temp=get_reg(branch_regs[i].regmap,PTEMP);
5136 if(dops[i].rt1==31&&temp>=0)
5138 signed char *i_regmap=i_regs->regmap;
5139 int return_address=start+i*4+8;
5140 if(get_reg(branch_regs[i].regmap,31)>0)
5141 if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
5144 if(dops[i].rt1==31&&(dops[i].rt1==dops[i+1].rs1||dops[i].rt1==dops[i+1].rs2)) {
5145 ujump_assemble_write_ra(i); // writeback ra for DS
5148 ds_assemble(i+1,i_regs);
5149 uint64_t bc_unneeded=branch_regs[i].u;
5150 bc_unneeded|=1|(1LL<<dops[i].rt1);
5151 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
5152 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG);
5153 if(!ra_done&&dops[i].rt1==31)
5154 ujump_assemble_write_ra(i);
5156 cc=get_reg(branch_regs[i].regmap,CCREG);
5157 assert(cc==HOST_CCREG);
5158 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5160 if(dops[i].rt1==31&&temp>=0) emit_prefetchreg(temp);
5162 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5163 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
5164 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5165 if(internal_branch(ba[i]))
5166 assem_debug("branch: internal\n");
5168 assem_debug("branch: external\n");
5169 if (internal_branch(ba[i]) && dops[(ba[i]-start)>>2].is_ds) {
5170 ds_assemble_entry(i);
5173 add_to_linker(out,ba[i],internal_branch(ba[i]));
5178 static void rjump_assemble_write_ra(int i)
5180 int rt,return_address;
5181 assert(dops[i+1].rt1!=dops[i].rt1);
5182 assert(dops[i+1].rt2!=dops[i].rt1);
5183 rt=get_reg(branch_regs[i].regmap,dops[i].rt1);
5184 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5186 return_address=start+i*4+8;
5190 if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
5193 emit_movimm(return_address,rt); // PC into link register
5195 emit_prefetch(hash_table_get(return_address));
5199 static void rjump_assemble(int i, const struct regstat *i_regs)
5204 rs=get_reg(branch_regs[i].regmap,dops[i].rs1);
5206 if (ds_writes_rjump_rs(i)) {
5207 // Delay slot abuse, make a copy of the branch address register
5208 temp=get_reg(branch_regs[i].regmap,RTEMP);
5210 assert(regs[i].regmap[temp]==RTEMP);
5214 address_generation(i+1,i_regs,regs[i].regmap_entry);
5218 if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5219 signed char *i_regmap=i_regs->regmap;
5220 int return_address=start+i*4+8;
5221 if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
5226 if(dops[i].rs1==31) {
5227 int rh=get_reg(regs[i].regmap,RHASH);
5228 if(rh>=0) do_preload_rhash(rh);
5231 if(dops[i].rt1!=0&&(dops[i].rt1==dops[i+1].rs1||dops[i].rt1==dops[i+1].rs2)) {
5232 rjump_assemble_write_ra(i);
5235 ds_assemble(i+1,i_regs);
5236 uint64_t bc_unneeded=branch_regs[i].u;
5237 bc_unneeded|=1|(1LL<<dops[i].rt1);
5238 bc_unneeded&=~(1LL<<dops[i].rs1);
5239 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
5240 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,CCREG);
5241 if(!ra_done&&dops[i].rt1!=0)
5242 rjump_assemble_write_ra(i);
5243 cc=get_reg(branch_regs[i].regmap,CCREG);
5244 assert(cc==HOST_CCREG);
5247 int rh=get_reg(branch_regs[i].regmap,RHASH);
5248 int ht=get_reg(branch_regs[i].regmap,RHTBL);
5249 if(dops[i].rs1==31) {
5250 if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5251 do_preload_rhtbl(ht);
5255 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1);
5256 #ifdef DESTRUCTIVE_WRITEBACK
5257 if((branch_regs[i].dirty>>rs)&1) {
5258 if(dops[i].rs1!=dops[i+1].rt1&&dops[i].rs1!=dops[i+1].rt2) {
5259 emit_loadreg(dops[i].rs1,rs);
5264 if(dops[i].rt1==31&&temp>=0) emit_prefetchreg(temp);
5267 if(dops[i].rs1==31) {
5268 do_miniht_load(ht,rh);
5271 //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5272 //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5274 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG);
5275 add_stub(CC_STUB,out,NULL,0,i,-1,TAKEN,rs);
5276 if(dops[i+1].itype==COP0&&(source[i+1]&0x3f)==0x10)
5277 // special case for RFE
5281 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1);
5283 if(dops[i].rs1==31) {
5284 do_miniht_jump(rs,rh,ht);
5291 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5292 if(dops[i].rt1!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5296 static void cjump_assemble(int i, const struct regstat *i_regs)
5298 const signed char *i_regmap = i_regs->regmap;
5301 match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5302 assem_debug("match=%d\n",match);
5304 int unconditional=0,nop=0;
5306 int internal=internal_branch(ba[i]);
5307 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5308 if(!match) invert=1;
5309 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5310 if(i>(ba[i]-start)>>2) invert=1;
5313 invert=1; // because of near cond. branches
5317 s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
5318 s2l=get_reg(branch_regs[i].regmap,dops[i].rs2);
5321 s1l=get_reg(i_regmap,dops[i].rs1);
5322 s2l=get_reg(i_regmap,dops[i].rs2);
5324 if(dops[i].rs1==0&&dops[i].rs2==0)
5326 if(dops[i].opcode&1) nop=1;
5327 else unconditional=1;
5328 //assert(dops[i].opcode!=5);
5329 //assert(dops[i].opcode!=7);
5330 //assert(dops[i].opcode!=0x15);
5331 //assert(dops[i].opcode!=0x17);
5333 else if(dops[i].rs1==0)
5338 else if(dops[i].rs2==0)
5344 // Out of order execution (delay slot first)
5346 address_generation(i+1,i_regs,regs[i].regmap_entry);
5347 ds_assemble(i+1,i_regs);
5349 uint64_t bc_unneeded=branch_regs[i].u;
5350 bc_unneeded&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
5352 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
5353 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,dops[i].rs2);
5354 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG);
5355 cc=get_reg(branch_regs[i].regmap,CCREG);
5356 assert(cc==HOST_CCREG);
5358 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5359 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5360 //assem_debug("cycle count (adj)\n");
5362 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5363 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5364 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
5365 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5367 assem_debug("branch: internal\n");
5369 assem_debug("branch: external\n");
5370 if (internal && dops[(ba[i]-start)>>2].is_ds) {
5371 ds_assemble_entry(i);
5374 add_to_linker(out,ba[i],internal);
5377 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5378 if(((u_int)out)&7) emit_addnop(0);
5383 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc);
5386 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5389 void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL;
5390 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5391 if(adj&&!invert) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
5393 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5395 if(dops[i].opcode==4) // BEQ
5397 if(s2l>=0) emit_cmp(s1l,s2l);
5398 else emit_test(s1l,s1l);
5403 add_to_linker(out,ba[i],internal);
5407 if(dops[i].opcode==5) // BNE
5409 if(s2l>=0) emit_cmp(s1l,s2l);
5410 else emit_test(s1l,s1l);
5415 add_to_linker(out,ba[i],internal);
5419 if(dops[i].opcode==6) // BLEZ
5426 add_to_linker(out,ba[i],internal);
5430 if(dops[i].opcode==7) // BGTZ
5437 add_to_linker(out,ba[i],internal);
5442 if(taken) set_jump_target(taken, out);
5443 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5444 if (match && (!internal || !dops[(ba[i]-start)>>2].is_ds)) {
5446 emit_addimm(cc,-adj,cc);
5447 add_to_linker(out,ba[i],internal);
5450 add_to_linker(out,ba[i],internal*2);
5456 if(adj) emit_addimm(cc,-adj,cc);
5457 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5458 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5460 assem_debug("branch: internal\n");
5462 assem_debug("branch: external\n");
5463 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
5464 ds_assemble_entry(i);
5467 add_to_linker(out,ba[i],internal);
5471 set_jump_target(nottaken, out);
5474 if(nottaken1) set_jump_target(nottaken1, out);
5476 if(!invert) emit_addimm(cc,adj,cc);
5478 } // (!unconditional)
5482 // In-order execution (branch first)
5483 void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL;
5484 if(!unconditional&&!nop) {
5485 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5487 if((dops[i].opcode&0x2f)==4) // BEQ
5489 if(s2l>=0) emit_cmp(s1l,s2l);
5490 else emit_test(s1l,s1l);
5494 if((dops[i].opcode&0x2f)==5) // BNE
5496 if(s2l>=0) emit_cmp(s1l,s2l);
5497 else emit_test(s1l,s1l);
5501 if((dops[i].opcode&0x2f)==6) // BLEZ
5507 if((dops[i].opcode&0x2f)==7) // BGTZ
5513 } // if(!unconditional)
5515 uint64_t ds_unneeded=branch_regs[i].u;
5516 ds_unneeded&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
5520 if(taken) set_jump_target(taken, out);
5521 assem_debug("1:\n");
5522 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5524 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5525 address_generation(i+1,&branch_regs[i],0);
5527 load_regs(regs[i].regmap,branch_regs[i].regmap,ROREG,ROREG);
5528 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
5529 ds_assemble(i+1,&branch_regs[i]);
5530 cc=get_reg(branch_regs[i].regmap,CCREG);
5532 emit_loadreg(CCREG,cc=HOST_CCREG);
5533 // CHECK: Is the following instruction (fall thru) allocated ok?
5535 assert(cc==HOST_CCREG);
5536 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5537 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5538 assem_debug("cycle count (adj)\n");
5539 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
5540 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5542 assem_debug("branch: internal\n");
5544 assem_debug("branch: external\n");
5545 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
5546 ds_assemble_entry(i);
5549 add_to_linker(out,ba[i],internal);
5554 if(!unconditional) {
5555 if(nottaken1) set_jump_target(nottaken1, out);
5556 set_jump_target(nottaken, out);
5557 assem_debug("2:\n");
5558 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5560 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5561 address_generation(i+1,&branch_regs[i],0);
5563 load_regs(regs[i].regmap,branch_regs[i].regmap,ROREG,ROREG);
5564 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
5565 ds_assemble(i+1,&branch_regs[i]);
5566 cc=get_reg(branch_regs[i].regmap,CCREG);
5568 // Cycle count isn't in a register, temporarily load it then write it out
5569 emit_loadreg(CCREG,HOST_CCREG);
5570 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG);
5573 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5574 emit_storereg(CCREG,HOST_CCREG);
5577 cc=get_reg(i_regmap,CCREG);
5578 assert(cc==HOST_CCREG);
5579 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc);
5582 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5588 static void sjump_assemble(int i, const struct regstat *i_regs)
5590 const signed char *i_regmap = i_regs->regmap;
5593 match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5594 assem_debug("smatch=%d\n",match);
5596 int unconditional=0,nevertaken=0;
5598 int internal=internal_branch(ba[i]);
5599 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5600 if(!match) invert=1;
5601 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5602 if(i>(ba[i]-start)>>2) invert=1;
5605 invert=1; // because of near cond. branches
5608 //if(dops[i].opcode2>=0x10) return; // FIXME (BxxZAL)
5609 //assert(dops[i].opcode2<0x10||dops[i].rs1==0); // FIXME (BxxZAL)
5612 s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
5615 s1l=get_reg(i_regmap,dops[i].rs1);
5619 if(dops[i].opcode2&1) unconditional=1;
5621 // These are never taken (r0 is never less than zero)
5622 //assert(dops[i].opcode2!=0);
5623 //assert(dops[i].opcode2!=2);
5624 //assert(dops[i].opcode2!=0x10);
5625 //assert(dops[i].opcode2!=0x12);
5629 // Out of order execution (delay slot first)
5631 address_generation(i+1,i_regs,regs[i].regmap_entry);
5632 ds_assemble(i+1,i_regs);
5634 uint64_t bc_unneeded=branch_regs[i].u;
5635 bc_unneeded&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
5637 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
5638 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,dops[i].rs1);
5639 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG);
5640 if(dops[i].rt1==31) {
5641 int rt,return_address;
5642 rt=get_reg(branch_regs[i].regmap,31);
5643 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5645 // Save the PC even if the branch is not taken
5646 return_address=start+i*4+8;
5647 emit_movimm(return_address,rt); // PC into link register
5649 if(!nevertaken) emit_prefetch(hash_table_get(return_address));
5653 cc=get_reg(branch_regs[i].regmap,CCREG);
5654 assert(cc==HOST_CCREG);
5656 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5657 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5658 assem_debug("cycle count (adj)\n");
5660 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5661 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5662 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
5663 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5665 assem_debug("branch: internal\n");
5667 assem_debug("branch: external\n");
5668 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
5669 ds_assemble_entry(i);
5672 add_to_linker(out,ba[i],internal);
5675 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5676 if(((u_int)out)&7) emit_addnop(0);
5680 else if(nevertaken) {
5681 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc);
5684 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5687 void *nottaken = NULL;
5688 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5689 if(adj&&!invert) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
5692 if((dops[i].opcode2&0xf)==0) // BLTZ/BLTZAL
5699 add_to_linker(out,ba[i],internal);
5703 if((dops[i].opcode2&0xf)==1) // BGEZ/BLTZAL
5710 add_to_linker(out,ba[i],internal);
5717 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5718 if (match && (!internal || !dops[(ba[i] - start) >> 2].is_ds)) {
5720 emit_addimm(cc,-adj,cc);
5721 add_to_linker(out,ba[i],internal);
5724 add_to_linker(out,ba[i],internal*2);
5730 if(adj) emit_addimm(cc,-adj,cc);
5731 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5732 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5734 assem_debug("branch: internal\n");
5736 assem_debug("branch: external\n");
5737 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
5738 ds_assemble_entry(i);
5741 add_to_linker(out,ba[i],internal);
5745 set_jump_target(nottaken, out);
5749 if(!invert) emit_addimm(cc,adj,cc);
5751 } // (!unconditional)
5755 // In-order execution (branch first)
5757 void *nottaken = NULL;
5758 if(dops[i].rt1==31) {
5759 int rt,return_address;
5760 rt=get_reg(branch_regs[i].regmap,31);
5762 // Save the PC even if the branch is not taken
5763 return_address=start+i*4+8;
5764 emit_movimm(return_address,rt); // PC into link register
5766 emit_prefetch(hash_table_get(return_address));
5770 if(!unconditional) {
5771 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5773 if((dops[i].opcode2&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
5779 if((dops[i].opcode2&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
5785 } // if(!unconditional)
5787 uint64_t ds_unneeded=branch_regs[i].u;
5788 ds_unneeded&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
5792 //assem_debug("1:\n");
5793 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5795 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5796 address_generation(i+1,&branch_regs[i],0);
5798 load_regs(regs[i].regmap,branch_regs[i].regmap,ROREG,ROREG);
5799 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
5800 ds_assemble(i+1,&branch_regs[i]);
5801 cc=get_reg(branch_regs[i].regmap,CCREG);
5803 emit_loadreg(CCREG,cc=HOST_CCREG);
5804 // CHECK: Is the following instruction (fall thru) allocated ok?
5806 assert(cc==HOST_CCREG);
5807 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5808 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5809 assem_debug("cycle count (adj)\n");
5810 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
5811 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5813 assem_debug("branch: internal\n");
5815 assem_debug("branch: external\n");
5816 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
5817 ds_assemble_entry(i);
5820 add_to_linker(out,ba[i],internal);
5825 if(!unconditional) {
5826 set_jump_target(nottaken, out);
5827 assem_debug("1:\n");
5828 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5829 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5830 address_generation(i+1,&branch_regs[i],0);
5831 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG);
5832 ds_assemble(i+1,&branch_regs[i]);
5833 cc=get_reg(branch_regs[i].regmap,CCREG);
5835 // Cycle count isn't in a register, temporarily load it then write it out
5836 emit_loadreg(CCREG,HOST_CCREG);
5837 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG);
5840 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5841 emit_storereg(CCREG,HOST_CCREG);
5844 cc=get_reg(i_regmap,CCREG);
5845 assert(cc==HOST_CCREG);
5846 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc);
5849 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5855 static void pagespan_assemble(int i, const struct regstat *i_regs)
5857 int s1l=get_reg(i_regs->regmap,dops[i].rs1);
5858 int s2l=get_reg(i_regs->regmap,dops[i].rs2);
5860 void *nottaken = NULL;
5861 int unconditional=0;
5867 else if(dops[i].rs2==0)
5872 int addr=-1,alt=-1,ntaddr=-1;
5873 if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
5877 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5878 (i_regs->regmap[hr]&63)!=dops[i].rs1 &&
5879 (i_regs->regmap[hr]&63)!=dops[i].rs2 )
5888 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
5889 (i_regs->regmap[hr]&63)!=dops[i].rs1 &&
5890 (i_regs->regmap[hr]&63)!=dops[i].rs2 )
5896 if((dops[i].opcode&0x2E)==6) // BLEZ/BGTZ needs another register
5900 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
5901 (i_regs->regmap[hr]&63)!=dops[i].rs1 &&
5902 (i_regs->regmap[hr]&63)!=dops[i].rs2 )
5909 assert(hr<HOST_REGS);
5910 if((dops[i].opcode&0x2e)==4||dops[i].opcode==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
5911 load_regs(regs[i].regmap_entry,regs[i].regmap,CCREG,CCREG);
5913 emit_addimm(HOST_CCREG, ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG);
5914 if(dops[i].opcode==2) // J
5918 if(dops[i].opcode==3) // JAL
5921 int rt=get_reg(i_regs->regmap,31);
5922 emit_movimm(start+i*4+8,rt);
5925 if(dops[i].opcode==0&&(dops[i].opcode2&0x3E)==8) // JR/JALR
5928 if(dops[i].opcode2==9) // JALR
5930 int rt=get_reg(i_regs->regmap,dops[i].rt1);
5931 emit_movimm(start+i*4+8,rt);
5934 if((dops[i].opcode&0x3f)==4) // BEQ
5936 if(dops[i].rs1==dops[i].rs2)
5941 #ifdef HAVE_CMOV_IMM
5943 if(s2l>=0) emit_cmp(s1l,s2l);
5944 else emit_test(s1l,s1l);
5945 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
5951 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5952 if(s2l>=0) emit_cmp(s1l,s2l);
5953 else emit_test(s1l,s1l);
5954 emit_cmovne_reg(alt,addr);
5957 if((dops[i].opcode&0x3f)==5) // BNE
5959 #ifdef HAVE_CMOV_IMM
5960 if(s2l>=0) emit_cmp(s1l,s2l);
5961 else emit_test(s1l,s1l);
5962 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
5965 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
5966 if(s2l>=0) emit_cmp(s1l,s2l);
5967 else emit_test(s1l,s1l);
5968 emit_cmovne_reg(alt,addr);
5971 if((dops[i].opcode&0x3f)==0x14) // BEQL
5973 if(s2l>=0) emit_cmp(s1l,s2l);
5974 else emit_test(s1l,s1l);
5975 if(nottaken) set_jump_target(nottaken, out);
5979 if((dops[i].opcode&0x3f)==0x15) // BNEL
5981 if(s2l>=0) emit_cmp(s1l,s2l);
5982 else emit_test(s1l,s1l);
5985 if(taken) set_jump_target(taken, out);
5987 if((dops[i].opcode&0x3f)==6) // BLEZ
5989 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5991 emit_cmovl_reg(alt,addr);
5993 if((dops[i].opcode&0x3f)==7) // BGTZ
5995 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
5997 emit_cmovl_reg(ntaddr,addr);
5999 if((dops[i].opcode&0x3f)==0x16) // BLEZL
6001 assert((dops[i].opcode&0x3f)!=0x16);
6003 if((dops[i].opcode&0x3f)==0x17) // BGTZL
6005 assert((dops[i].opcode&0x3f)!=0x17);
6007 assert(dops[i].opcode!=1); // BLTZ/BGEZ
6009 //FIXME: Check CSREG
6010 if(dops[i].opcode==0x11 && dops[i].opcode2==0x08 ) {
6011 if((source[i]&0x30000)==0) // BC1F
6013 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6014 emit_testimm(s1l,0x800000);
6015 emit_cmovne_reg(alt,addr);
6017 if((source[i]&0x30000)==0x10000) // BC1T
6019 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6020 emit_testimm(s1l,0x800000);
6021 emit_cmovne_reg(alt,addr);
6023 if((source[i]&0x30000)==0x20000) // BC1FL
6025 emit_testimm(s1l,0x800000);
6029 if((source[i]&0x30000)==0x30000) // BC1TL
6031 emit_testimm(s1l,0x800000);
6037 assert(i_regs->regmap[HOST_CCREG]==CCREG);
6038 wb_dirtys(regs[i].regmap,regs[i].dirty);
6041 emit_movimm(ba[i],HOST_BTREG);
6043 else if(addr!=HOST_BTREG)
6045 emit_mov(addr,HOST_BTREG);
6047 void *branch_addr=out;
6049 int target_addr=start+i*4+5;
6051 void *compiled_target_addr=check_addr(target_addr);
6052 emit_extjump_ds(branch_addr, target_addr);
6053 if(compiled_target_addr) {
6054 set_jump_target(branch_addr, compiled_target_addr);
6055 add_jump_out(target_addr,stub);
6057 else set_jump_target(branch_addr, stub);
6060 // Assemble the delay slot for the above
6061 static void pagespan_ds()
6063 assem_debug("initial delay slot:\n");
6064 u_int vaddr=start+1;
6065 u_int page=get_page(vaddr);
6066 u_int vpage=get_vpage(vaddr);
6067 ll_add(jump_dirty+vpage,vaddr,(void *)out);
6068 do_dirty_stub_ds(slen*4);
6069 ll_add(jump_in+page,vaddr,(void *)out);
6070 assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6071 if(regs[0].regmap[HOST_CCREG]!=CCREG)
6072 wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty);
6073 if(regs[0].regmap[HOST_BTREG]!=BTREG)
6074 emit_writeword(HOST_BTREG,&branch_target);
6075 load_regs(regs[0].regmap_entry,regs[0].regmap,dops[0].rs1,dops[0].rs2);
6076 address_generation(0,®s[0],regs[0].regmap_entry);
6077 if (ram_offset && (dops[0].is_load || dops[0].is_store))
6078 load_regs(regs[0].regmap_entry,regs[0].regmap,ROREG,ROREG);
6079 if (dops[0].is_store)
6080 load_regs(regs[0].regmap_entry,regs[0].regmap,INVCP,INVCP);
6082 switch (dops[0].itype) {
6091 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
6094 assemble(0, ®s[0], 0);
6096 int btaddr=get_reg(regs[0].regmap,BTREG);
6098 btaddr=get_reg(regs[0].regmap,-1);
6099 emit_readword(&branch_target,btaddr);
6101 assert(btaddr!=HOST_CCREG);
6102 if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6104 host_tempreg_acquire();
6105 emit_movimm(start+4,HOST_TEMPREG);
6106 emit_cmp(btaddr,HOST_TEMPREG);
6107 host_tempreg_release();
6109 emit_cmpimm(btaddr,start+4);
6113 store_regs_bt(regs[0].regmap,regs[0].dirty,-1);
6114 do_jump_vaddr(btaddr);
6115 set_jump_target(branch, out);
6116 store_regs_bt(regs[0].regmap,regs[0].dirty,start+4);
6117 load_regs_bt(regs[0].regmap,regs[0].dirty,start+4);
6120 // Basic liveness analysis for MIPS registers
6121 void unneeded_registers(int istart,int iend,int r)
6124 uint64_t u,gte_u,b,gte_b;
6125 uint64_t temp_u,temp_gte_u=0;
6126 uint64_t gte_u_unknown=0;
6127 if (HACK_ENABLED(NDHACK_GTE_UNNEEDED))
6131 gte_u=gte_u_unknown;
6133 //u=unneeded_reg[iend+1];
6135 gte_u=gte_unneeded[iend+1];
6138 for (i=iend;i>=istart;i--)
6140 //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
6143 // If subroutine call, flag return address as a possible branch target
6144 if(dops[i].rt1==31 && i<slen-2) dops[i+2].bt=1;
6146 if(ba[i]<start || ba[i]>=(start+slen*4))
6148 // Branch out of this block, flush all regs
6150 gte_u=gte_u_unknown;
6151 branch_unneeded_reg[i]=u;
6152 // Merge in delay slot
6153 u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
6154 u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
6157 gte_u&=~gte_rs[i+1];
6161 // Internal branch, flag target
6162 dops[(ba[i]-start)>>2].bt=1;
6163 if(ba[i]<=start+i*4) {
6165 if(dops[i].is_ujump)
6167 // Unconditional branch
6171 // Conditional branch (not taken case)
6172 temp_u=unneeded_reg[i+2];
6173 temp_gte_u&=gte_unneeded[i+2];
6175 // Merge in delay slot
6176 temp_u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
6177 temp_u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
6179 temp_gte_u|=gte_rt[i+1];
6180 temp_gte_u&=~gte_rs[i+1];
6181 temp_u|=(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2);
6182 temp_u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
6184 temp_gte_u|=gte_rt[i];
6185 temp_gte_u&=~gte_rs[i];
6186 unneeded_reg[i]=temp_u;
6187 gte_unneeded[i]=temp_gte_u;
6188 // Only go three levels deep. This recursion can take an
6189 // excessive amount of time if there are a lot of nested loops.
6191 unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6193 unneeded_reg[(ba[i]-start)>>2]=1;
6194 gte_unneeded[(ba[i]-start)>>2]=gte_u_unknown;
6197 if (dops[i].is_ujump)
6199 // Unconditional branch
6200 u=unneeded_reg[(ba[i]-start)>>2];
6201 gte_u=gte_unneeded[(ba[i]-start)>>2];
6202 branch_unneeded_reg[i]=u;
6203 // Merge in delay slot
6204 u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
6205 u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
6208 gte_u&=~gte_rs[i+1];
6210 // Conditional branch
6211 b=unneeded_reg[(ba[i]-start)>>2];
6212 gte_b=gte_unneeded[(ba[i]-start)>>2];
6213 branch_unneeded_reg[i]=b;
6214 // Branch delay slot
6215 b|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
6216 b&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
6219 gte_b&=~gte_rs[i+1];
6223 branch_unneeded_reg[i]&=unneeded_reg[i+2];
6225 branch_unneeded_reg[i]=1;
6231 else if(dops[i].itype==SYSCALL||dops[i].itype==HLECALL||dops[i].itype==INTCALL)
6233 // SYSCALL instruction (software interrupt)
6236 else if(dops[i].itype==COP0 && (source[i]&0x3f)==0x18)
6238 // ERET instruction (return from interrupt)
6242 // Written registers are unneeded
6243 u|=1LL<<dops[i].rt1;
6244 u|=1LL<<dops[i].rt2;
6246 // Accessed registers are needed
6247 u&=~(1LL<<dops[i].rs1);
6248 u&=~(1LL<<dops[i].rs2);
6250 if(gte_rs[i]&&dops[i].rt1&&(unneeded_reg[i+1]&(1ll<<dops[i].rt1)))
6251 gte_u|=gte_rs[i]>e_unneeded[i+1]; // MFC2/CFC2 to dead register, unneeded
6252 // Source-target dependencies
6253 // R0 is always unneeded
6257 gte_unneeded[i]=gte_u;
6259 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
6262 for(r=1;r<=CCREG;r++) {
6263 if((unneeded_reg[i]>>r)&1) {
6264 if(r==HIREG) printf(" HI");
6265 else if(r==LOREG) printf(" LO");
6266 else printf(" r%d",r);
6274 // Write back dirty registers as soon as we will no longer modify them,
6275 // so that we don't end up with lots of writes at the branches.
6276 void clean_registers(int istart,int iend,int wr)
6280 u_int will_dirty_i,will_dirty_next,temp_will_dirty;
6281 u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
6283 will_dirty_i=will_dirty_next=0;
6284 wont_dirty_i=wont_dirty_next=0;
6286 will_dirty_i=will_dirty_next=will_dirty[iend+1];
6287 wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
6289 for (i=iend;i>=istart;i--)
6293 if(ba[i]<start || ba[i]>=(start+slen*4))
6295 // Branch out of this block, flush all regs
6296 if (dops[i].is_ujump)
6298 // Unconditional branch
6301 // Merge in delay slot (will dirty)
6302 for(r=0;r<HOST_REGS;r++) {
6303 if(r!=EXCLUDE_REG) {
6304 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6305 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6306 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6307 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
6308 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6309 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6310 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6311 if((regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6312 if((regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6313 if((regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6314 if((regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
6315 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6316 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6317 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6323 // Conditional branch
6325 wont_dirty_i=wont_dirty_next;
6326 // Merge in delay slot (will dirty)
6327 for(r=0;r<HOST_REGS;r++) {
6328 if(r!=EXCLUDE_REG) {
6329 if (1) { // !dops[i].likely) {
6330 // Might not dirty if likely branch is not taken
6331 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6332 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6333 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6334 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
6335 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6336 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
6337 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6338 //if((regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6339 //if((regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6340 if((regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6341 if((regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
6342 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6343 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6344 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6349 // Merge in delay slot (wont dirty)
6350 for(r=0;r<HOST_REGS;r++) {
6351 if(r!=EXCLUDE_REG) {
6352 if((regs[i].regmap[r]&63)==dops[i].rt1) wont_dirty_i|=1<<r;
6353 if((regs[i].regmap[r]&63)==dops[i].rt2) wont_dirty_i|=1<<r;
6354 if((regs[i].regmap[r]&63)==dops[i+1].rt1) wont_dirty_i|=1<<r;
6355 if((regs[i].regmap[r]&63)==dops[i+1].rt2) wont_dirty_i|=1<<r;
6356 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6357 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) wont_dirty_i|=1<<r;
6358 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) wont_dirty_i|=1<<r;
6359 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) wont_dirty_i|=1<<r;
6360 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) wont_dirty_i|=1<<r;
6361 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6365 #ifndef DESTRUCTIVE_WRITEBACK
6366 branch_regs[i].dirty&=wont_dirty_i;
6368 branch_regs[i].dirty|=will_dirty_i;
6374 if(ba[i]<=start+i*4) {
6376 if (dops[i].is_ujump)
6378 // Unconditional branch
6381 // Merge in delay slot (will dirty)
6382 for(r=0;r<HOST_REGS;r++) {
6383 if(r!=EXCLUDE_REG) {
6384 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) temp_will_dirty|=1<<r;
6385 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) temp_will_dirty|=1<<r;
6386 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) temp_will_dirty|=1<<r;
6387 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) temp_will_dirty|=1<<r;
6388 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
6389 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
6390 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
6391 if((regs[i].regmap[r]&63)==dops[i].rt1) temp_will_dirty|=1<<r;
6392 if((regs[i].regmap[r]&63)==dops[i].rt2) temp_will_dirty|=1<<r;
6393 if((regs[i].regmap[r]&63)==dops[i+1].rt1) temp_will_dirty|=1<<r;
6394 if((regs[i].regmap[r]&63)==dops[i+1].rt2) temp_will_dirty|=1<<r;
6395 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
6396 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
6397 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
6401 // Conditional branch (not taken case)
6402 temp_will_dirty=will_dirty_next;
6403 temp_wont_dirty=wont_dirty_next;
6404 // Merge in delay slot (will dirty)
6405 for(r=0;r<HOST_REGS;r++) {
6406 if(r!=EXCLUDE_REG) {
6407 if (1) { // !dops[i].likely) {
6408 // Will not dirty if likely branch is not taken
6409 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) temp_will_dirty|=1<<r;
6410 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) temp_will_dirty|=1<<r;
6411 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) temp_will_dirty|=1<<r;
6412 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) temp_will_dirty|=1<<r;
6413 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
6414 if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
6415 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
6416 //if((regs[i].regmap[r]&63)==dops[i].rt1) temp_will_dirty|=1<<r;
6417 //if((regs[i].regmap[r]&63)==dops[i].rt2) temp_will_dirty|=1<<r;
6418 if((regs[i].regmap[r]&63)==dops[i+1].rt1) temp_will_dirty|=1<<r;
6419 if((regs[i].regmap[r]&63)==dops[i+1].rt2) temp_will_dirty|=1<<r;
6420 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
6421 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
6422 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
6427 // Merge in delay slot (wont dirty)
6428 for(r=0;r<HOST_REGS;r++) {
6429 if(r!=EXCLUDE_REG) {
6430 if((regs[i].regmap[r]&63)==dops[i].rt1) temp_wont_dirty|=1<<r;
6431 if((regs[i].regmap[r]&63)==dops[i].rt2) temp_wont_dirty|=1<<r;
6432 if((regs[i].regmap[r]&63)==dops[i+1].rt1) temp_wont_dirty|=1<<r;
6433 if((regs[i].regmap[r]&63)==dops[i+1].rt2) temp_wont_dirty|=1<<r;
6434 if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
6435 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) temp_wont_dirty|=1<<r;
6436 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) temp_wont_dirty|=1<<r;
6437 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) temp_wont_dirty|=1<<r;
6438 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) temp_wont_dirty|=1<<r;
6439 if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
6442 // Deal with changed mappings
6444 for(r=0;r<HOST_REGS;r++) {
6445 if(r!=EXCLUDE_REG) {
6446 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
6447 temp_will_dirty&=~(1<<r);
6448 temp_wont_dirty&=~(1<<r);
6449 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
6450 temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6451 temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6453 temp_will_dirty|=1<<r;
6454 temp_wont_dirty|=1<<r;
6461 will_dirty[i]=temp_will_dirty;
6462 wont_dirty[i]=temp_wont_dirty;
6463 clean_registers((ba[i]-start)>>2,i-1,0);
6465 // Limit recursion. It can take an excessive amount
6466 // of time if there are a lot of nested loops.
6467 will_dirty[(ba[i]-start)>>2]=0;
6468 wont_dirty[(ba[i]-start)>>2]=-1;
6473 if (dops[i].is_ujump)
6475 // Unconditional branch
6478 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
6479 for(r=0;r<HOST_REGS;r++) {
6480 if(r!=EXCLUDE_REG) {
6481 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
6482 will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
6483 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
6485 if(branch_regs[i].regmap[r]>=0) {
6486 will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
6487 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
6492 // Merge in delay slot
6493 for(r=0;r<HOST_REGS;r++) {
6494 if(r!=EXCLUDE_REG) {
6495 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6496 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6497 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6498 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
6499 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6500 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6501 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6502 if((regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6503 if((regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6504 if((regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6505 if((regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
6506 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6507 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6508 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6512 // Conditional branch
6513 will_dirty_i=will_dirty_next;
6514 wont_dirty_i=wont_dirty_next;
6515 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
6516 for(r=0;r<HOST_REGS;r++) {
6517 if(r!=EXCLUDE_REG) {
6518 signed char target_reg=branch_regs[i].regmap[r];
6519 if(target_reg==regs[(ba[i]-start)>>2].regmap_entry[r]) {
6520 will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
6521 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
6523 else if(target_reg>=0) {
6524 will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
6525 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
6530 // Merge in delay slot
6531 for(r=0;r<HOST_REGS;r++) {
6532 if(r!=EXCLUDE_REG) {
6533 if (1) { // !dops[i].likely) {
6534 // Might not dirty if likely branch is not taken
6535 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6536 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6537 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6538 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
6539 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6540 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6541 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6542 //if((regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6543 //if((regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6544 if((regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6545 if((regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
6546 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6547 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6548 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6553 // Merge in delay slot (won't dirty)
6554 for(r=0;r<HOST_REGS;r++) {
6555 if(r!=EXCLUDE_REG) {
6556 if((regs[i].regmap[r]&63)==dops[i].rt1) wont_dirty_i|=1<<r;
6557 if((regs[i].regmap[r]&63)==dops[i].rt2) wont_dirty_i|=1<<r;
6558 if((regs[i].regmap[r]&63)==dops[i+1].rt1) wont_dirty_i|=1<<r;
6559 if((regs[i].regmap[r]&63)==dops[i+1].rt2) wont_dirty_i|=1<<r;
6560 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6561 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) wont_dirty_i|=1<<r;
6562 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) wont_dirty_i|=1<<r;
6563 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) wont_dirty_i|=1<<r;
6564 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) wont_dirty_i|=1<<r;
6565 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6569 #ifndef DESTRUCTIVE_WRITEBACK
6570 branch_regs[i].dirty&=wont_dirty_i;
6572 branch_regs[i].dirty|=will_dirty_i;
6577 else if(dops[i].itype==SYSCALL||dops[i].itype==HLECALL||dops[i].itype==INTCALL)
6579 // SYSCALL instruction (software interrupt)
6583 else if(dops[i].itype==COP0 && (source[i]&0x3f)==0x18)
6585 // ERET instruction (return from interrupt)
6589 will_dirty_next=will_dirty_i;
6590 wont_dirty_next=wont_dirty_i;
6591 for(r=0;r<HOST_REGS;r++) {
6592 if(r!=EXCLUDE_REG) {
6593 if((regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6594 if((regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6595 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6596 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6597 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6598 if((regs[i].regmap[r]&63)==dops[i].rt1) wont_dirty_i|=1<<r;
6599 if((regs[i].regmap[r]&63)==dops[i].rt2) wont_dirty_i|=1<<r;
6600 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6602 if (!dops[i].is_jump)
6604 // Don't store a register immediately after writing it,
6605 // may prevent dual-issue.
6606 if((regs[i].regmap[r]&63)==dops[i-1].rt1) wont_dirty_i|=1<<r;
6607 if((regs[i].regmap[r]&63)==dops[i-1].rt2) wont_dirty_i|=1<<r;
6613 will_dirty[i]=will_dirty_i;
6614 wont_dirty[i]=wont_dirty_i;
6615 // Mark registers that won't be dirtied as not dirty
6617 regs[i].dirty|=will_dirty_i;
6618 #ifndef DESTRUCTIVE_WRITEBACK
6619 regs[i].dirty&=wont_dirty_i;
6622 if (i < iend-1 && !dops[i].is_ujump) {
6623 for(r=0;r<HOST_REGS;r++) {
6624 if(r!=EXCLUDE_REG) {
6625 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
6626 regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
6627 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
6635 for(r=0;r<HOST_REGS;r++) {
6636 if(r!=EXCLUDE_REG) {
6637 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
6638 regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
6639 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
6647 // Deal with changed mappings
6648 temp_will_dirty=will_dirty_i;
6649 temp_wont_dirty=wont_dirty_i;
6650 for(r=0;r<HOST_REGS;r++) {
6651 if(r!=EXCLUDE_REG) {
6653 if(regs[i].regmap[r]==regmap_pre[i][r]) {
6655 #ifndef DESTRUCTIVE_WRITEBACK
6656 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
6658 regs[i].wasdirty|=will_dirty_i&(1<<r);
6661 else if(regmap_pre[i][r]>=0&&(nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
6662 // Register moved to a different register
6663 will_dirty_i&=~(1<<r);
6664 wont_dirty_i&=~(1<<r);
6665 will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
6666 wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
6668 #ifndef DESTRUCTIVE_WRITEBACK
6669 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
6671 regs[i].wasdirty|=will_dirty_i&(1<<r);
6675 will_dirty_i&=~(1<<r);
6676 wont_dirty_i&=~(1<<r);
6677 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
6678 will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6679 wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6682 /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);assert(!((will_dirty>>r)&1));*/
6692 void disassemble_inst(int i)
6694 if (dops[i].bt) printf("*"); else printf(" ");
6695 switch(dops[i].itype) {
6697 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
6699 printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2,i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
6701 printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
6703 if (dops[i].opcode==0x9&&dops[i].rt1!=31)
6704 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1);
6706 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rs1);
6709 printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2,ba[i]);break;
6711 if(dops[i].opcode==0xf) //LUI
6712 printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],dops[i].rt1,imm[i]&0xffff);
6714 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,imm[i]);
6718 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,imm[i]);
6722 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],dops[i].rs2,dops[i].rs1,imm[i]);
6726 printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,dops[i].rs2);
6729 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2);
6732 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,imm[i]);
6735 if((dops[i].opcode2&0x1d)==0x10)
6736 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rt1);
6737 else if((dops[i].opcode2&0x1d)==0x11)
6738 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rs1);
6740 printf (" %x: %s\n",start+i*4,insn[i]);
6743 if(dops[i].opcode2==0)
6744 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC0
6745 else if(dops[i].opcode2==4)
6746 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC0
6747 else printf (" %x: %s\n",start+i*4,insn[i]);
6750 if(dops[i].opcode2<3)
6751 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC1
6752 else if(dops[i].opcode2>3)
6753 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC1
6754 else printf (" %x: %s\n",start+i*4,insn[i]);
6757 if(dops[i].opcode2<3)
6758 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC2
6759 else if(dops[i].opcode2>3)
6760 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC2
6761 else printf (" %x: %s\n",start+i*4,insn[i]);
6764 printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,dops[i].rs1,imm[i]);
6767 printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,dops[i].rs1,imm[i]);
6770 printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
6773 //printf (" %s %8x\n",insn[i],source[i]);
6774 printf (" %x: %s\n",start+i*4,insn[i]);
6778 static void disassemble_inst(int i) {}
6781 #define DRC_TEST_VAL 0x74657374
6783 static void new_dynarec_test(void)
6785 int (*testfunc)(void);
6790 // check structure linkage
6791 if ((u_char *)rcnts - (u_char *)&psxRegs != sizeof(psxRegs))
6793 SysPrintf("linkage_arm* miscompilation/breakage detected.\n");
6796 SysPrintf("testing if we can run recompiled code @%p...\n", out);
6797 ((volatile u_int *)out)[0]++; // make cache dirty
6799 for (i = 0; i < ARRAY_SIZE(ret); i++) {
6800 out = ndrc->translation_cache;
6801 beginning = start_block();
6802 emit_movimm(DRC_TEST_VAL + i, 0); // test
6805 end_block(beginning);
6806 testfunc = beginning;
6807 ret[i] = testfunc();
6810 if (ret[0] == DRC_TEST_VAL && ret[1] == DRC_TEST_VAL + 1)
6811 SysPrintf("test passed.\n");
6813 SysPrintf("test failed, will likely crash soon (r=%08x %08x)\n", ret[0], ret[1]);
6814 out = ndrc->translation_cache;
6817 // clear the state completely, instead of just marking
6818 // things invalid like invalidate_all_pages() does
6819 void new_dynarec_clear_full(void)
6822 out = ndrc->translation_cache;
6823 memset(invalid_code,1,sizeof(invalid_code));
6824 memset(hash_table,0xff,sizeof(hash_table));
6825 memset(mini_ht,-1,sizeof(mini_ht));
6826 memset(restore_candidate,0,sizeof(restore_candidate));
6827 memset(shadow,0,sizeof(shadow));
6829 expirep=16384; // Expiry pointer, +2 blocks
6830 pending_exception=0;
6833 inv_code_start=inv_code_end=~0;
6836 for(n=0;n<4096;n++) ll_clear(jump_in+n);
6837 for(n=0;n<4096;n++) ll_clear(jump_out+n);
6838 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
6840 cycle_multiplier_old = cycle_multiplier;
6841 new_dynarec_hacks_old = new_dynarec_hacks;
6844 void new_dynarec_init(void)
6846 SysPrintf("Init new dynarec\n");
6851 #ifdef BASE_ADDR_DYNAMIC
6853 sceBlock = getVMBlock(); //sceKernelAllocMemBlockForVM("code", sizeof(*ndrc));
6855 SysPrintf("sceKernelAllocMemBlockForVM failed\n");
6856 int ret = sceKernelGetMemBlockBase(sceBlock, (void **)&ndrc);
6858 SysPrintf("sceKernelGetMemBlockBase failed\n");
6859 sceKernelOpenVMDomain();
6860 sceClibPrintf("translation_cache = 0x%08lx\n ", (long)ndrc->translation_cache);
6861 #elif defined(_MSC_VER)
6862 ndrc = VirtualAlloc(NULL, sizeof(*ndrc), MEM_COMMIT | MEM_RESERVE,
6863 PAGE_EXECUTE_READWRITE);
6865 uintptr_t desired_addr = 0;
6868 desired_addr = ((uintptr_t)&_end + 0xffffff) & ~0xffffffl;
6870 ndrc = mmap((void *)desired_addr, sizeof(*ndrc),
6871 PROT_READ | PROT_WRITE | PROT_EXEC,
6872 MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
6873 if (ndrc == MAP_FAILED) {
6874 SysPrintf("mmap() failed: %s\n", strerror(errno));
6879 #ifndef NO_WRITE_EXEC
6880 // not all systems allow execute in data segment by default
6881 // size must be 4K aligned for 3DS?
6882 if (mprotect(ndrc, sizeof(*ndrc),
6883 PROT_READ | PROT_WRITE | PROT_EXEC) != 0)
6884 SysPrintf("mprotect() failed: %s\n", strerror(errno));
6887 out = ndrc->translation_cache;
6888 cycle_multiplier=200;
6889 new_dynarec_clear_full();
6891 // Copy this into local area so we don't have to put it in every literal pool
6892 invc_ptr=invalid_code;
6896 ram_offset=(uintptr_t)rdram-0x80000000;
6898 SysPrintf("warning: RAM is not directly mapped, performance will suffer\n");
6901 void new_dynarec_cleanup(void)
6904 #ifdef BASE_ADDR_DYNAMIC
6906 //sceKernelFreeMemBlock(sceBlock);
6909 if (munmap(ndrc, sizeof(*ndrc)) < 0)
6910 SysPrintf("munmap() failed\n");
6913 for(n=0;n<4096;n++) ll_clear(jump_in+n);
6914 for(n=0;n<4096;n++) ll_clear(jump_out+n);
6915 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
6917 if (munmap (ROM_COPY, 67108864) < 0) {SysPrintf("munmap() failed\n");}
6921 static u_int *get_source_start(u_int addr, u_int *limit)
6923 if (addr < 0x00200000 ||
6924 (0xa0000000 <= addr && addr < 0xa0200000))
6926 // used for BIOS calls mostly?
6927 *limit = (addr&0xa0000000)|0x00200000;
6928 return (u_int *)(rdram + (addr&0x1fffff));
6930 else if (!Config.HLE && (
6931 /* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
6932 (0xbfc00000 <= addr && addr < 0xbfc80000)))
6934 // BIOS. The multiplier should be much higher as it's uncached 8bit mem,
6935 // but timings in PCSX are too tied to the interpreter's BIAS
6936 if (!HACK_ENABLED(NDHACK_OVERRIDE_CYCLE_M))
6937 cycle_multiplier_active = 200;
6939 *limit = (addr & 0xfff00000) | 0x80000;
6940 return (u_int *)((u_char *)psxR + (addr&0x7ffff));
6942 else if (addr >= 0x80000000 && addr < 0x80000000+RAM_SIZE) {
6943 *limit = (addr & 0x80600000) + 0x00200000;
6944 return (u_int *)(rdram + (addr&0x1fffff));
6949 static u_int scan_for_ret(u_int addr)
6954 mem = get_source_start(addr, &limit);
6958 if (limit > addr + 0x1000)
6959 limit = addr + 0x1000;
6960 for (; addr < limit; addr += 4, mem++) {
6961 if (*mem == 0x03e00008) // jr $ra
6967 struct savestate_block {
6972 static int addr_cmp(const void *p1_, const void *p2_)
6974 const struct savestate_block *p1 = p1_, *p2 = p2_;
6975 return p1->addr - p2->addr;
6978 int new_dynarec_save_blocks(void *save, int size)
6980 struct savestate_block *blocks = save;
6981 int maxcount = size / sizeof(blocks[0]);
6982 struct savestate_block tmp_blocks[1024];
6983 struct ll_entry *head;
6984 int p, s, d, o, bcnt;
6988 for (p = 0; p < ARRAY_SIZE(jump_in); p++) {
6990 for (head = jump_in[p]; head != NULL; head = head->next) {
6991 tmp_blocks[bcnt].addr = head->vaddr;
6992 tmp_blocks[bcnt].regflags = head->reg_sv_flags;
6997 qsort(tmp_blocks, bcnt, sizeof(tmp_blocks[0]), addr_cmp);
6999 addr = tmp_blocks[0].addr;
7000 for (s = d = 0; s < bcnt; s++) {
7001 if (tmp_blocks[s].addr < addr)
7003 if (d == 0 || tmp_blocks[d-1].addr != tmp_blocks[s].addr)
7004 tmp_blocks[d++] = tmp_blocks[s];
7005 addr = scan_for_ret(tmp_blocks[s].addr);
7008 if (o + d > maxcount)
7010 memcpy(&blocks[o], tmp_blocks, d * sizeof(blocks[0]));
7014 return o * sizeof(blocks[0]);
7017 void new_dynarec_load_blocks(const void *save, int size)
7019 const struct savestate_block *blocks = save;
7020 int count = size / sizeof(blocks[0]);
7021 u_int regs_save[32];
7025 get_addr(psxRegs.pc);
7027 // change GPRs for speculation to at least partially work..
7028 memcpy(regs_save, &psxRegs.GPR, sizeof(regs_save));
7029 for (i = 1; i < 32; i++)
7030 psxRegs.GPR.r[i] = 0x80000000;
7032 for (b = 0; b < count; b++) {
7033 for (f = blocks[b].regflags, i = 0; f; f >>= 1, i++) {
7035 psxRegs.GPR.r[i] = 0x1f800000;
7038 get_addr(blocks[b].addr);
7040 for (f = blocks[b].regflags, i = 0; f; f >>= 1, i++) {
7042 psxRegs.GPR.r[i] = 0x80000000;
7046 memcpy(&psxRegs.GPR, regs_save, sizeof(regs_save));
7049 static void apply_hacks(void)
7052 if (HACK_ENABLED(NDHACK_NO_COMPAT_HACKS))
7054 /* special hack(s) */
7055 for (i = 0; i < slen - 4; i++)
7057 // lui a4, 0xf200; jal <rcnt_read>; addu a0, 2; slti v0, 28224
7058 if (source[i] == 0x3c04f200 && dops[i+1].itype == UJUMP
7059 && source[i+2] == 0x34840002 && dops[i+3].opcode == 0x0a
7060 && imm[i+3] == 0x6e40 && dops[i+3].rs1 == 2)
7062 SysPrintf("PE2 hack @%08x\n", start + (i+3)*4);
7063 dops[i + 3].itype = NOP;
7067 if (i > 10 && source[i-1] == 0 && source[i-2] == 0x03e00008
7068 && source[i-4] == 0x8fbf0018 && source[i-6] == 0x00c0f809
7069 && dops[i-7].itype == STORE)
7072 if (dops[i].itype == IMM16)
7074 // swl r2, 15(r6); swr r2, 12(r6); sw r6, *; jalr r6
7075 if (dops[i].itype == STORELR && dops[i].rs1 == 6
7076 && dops[i-1].itype == STORELR && dops[i-1].rs1 == 6)
7078 SysPrintf("F1 hack from %08x\n", start);
7085 int new_recompile_block(u_int addr)
7087 u_int pagelimit = 0;
7088 u_int state_rflags = 0;
7091 assem_debug("NOTCOMPILED: addr = %x -> %p\n", addr, out);
7092 //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
7094 //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
7096 // this is just for speculation
7097 for (i = 1; i < 32; i++) {
7098 if ((psxRegs.GPR.r[i] & 0xffff0000) == 0x1f800000)
7099 state_rflags |= 1 << i;
7102 start = (u_int)addr&~3;
7103 //assert(((u_int)addr&1)==0); // start-in-delay-slot flag
7104 new_dynarec_did_compile=1;
7105 if (Config.HLE && start == 0x80001000) // hlecall
7107 // XXX: is this enough? Maybe check hleSoftCall?
7108 void *beginning=start_block();
7109 u_int page=get_page(start);
7111 invalid_code[start>>12]=0;
7112 emit_movimm(start,0);
7113 emit_writeword(0,&pcaddr);
7114 emit_far_jump(new_dyna_leave);
7116 end_block(beginning);
7117 ll_add_flags(jump_in+page,start,state_rflags,(void *)beginning);
7120 else if (f1_hack == ~0u || (f1_hack != 0 && start == f1_hack)) {
7121 void *beginning = start_block();
7122 u_int page = get_page(start);
7123 emit_readword(&psxRegs.GPR.n.sp, 0);
7124 emit_readptr(&mem_rtab, 1);
7125 emit_shrimm(0, 12, 2);
7126 emit_readptr_dualindexedx_ptrlen(1, 2, 1);
7127 emit_addimm(0, 0x18, 0);
7128 emit_adds_ptr(1, 1, 1);
7129 emit_ldr_dualindexed(1, 0, 0);
7130 emit_writeword(0, &psxRegs.GPR.r[26]); // lw k0, 0x18(sp)
7131 emit_far_call(get_addr_ht);
7132 emit_jmpreg(0); // jr k0
7134 end_block(beginning);
7136 ll_add_flags(jump_in + page, start, state_rflags, beginning);
7137 SysPrintf("F1 hack to %08x\n", start);
7142 cycle_multiplier_active = cycle_multiplier_override && cycle_multiplier == CYCLE_MULT_DEFAULT
7143 ? cycle_multiplier_override : cycle_multiplier;
7145 source = get_source_start(start, &pagelimit);
7146 if (source == NULL) {
7147 SysPrintf("Compile at bogus memory address: %08x\n", addr);
7151 /* Pass 1: disassemble */
7152 /* Pass 2: register dependencies, branch targets */
7153 /* Pass 3: register allocation */
7154 /* Pass 4: branch dependencies */
7155 /* Pass 5: pre-alloc */
7156 /* Pass 6: optimize clean/dirty state */
7157 /* Pass 7: flag 32-bit registers */
7158 /* Pass 8: assembly */
7159 /* Pass 9: linker */
7160 /* Pass 10: garbage collection / free memory */
7164 unsigned int type,op,op2;
7166 //printf("addr = %x source = %x %x\n", addr,source,source[0]);
7168 /* Pass 1 disassembly */
7170 for (i = 0; !done; i++)
7172 memset(&dops[i], 0, sizeof(dops[i]));
7174 minimum_free_regs[i]=0;
7175 dops[i].opcode=op=source[i]>>26;
7178 case 0x00: strcpy(insn[i],"special"); type=NI;
7182 case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
7183 case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
7184 case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
7185 case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
7186 case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
7187 case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
7188 case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
7189 case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
7190 case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
7191 case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
7192 case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
7193 case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
7194 case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
7195 case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
7196 case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
7197 case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
7198 case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
7199 case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
7200 case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
7201 case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
7202 case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
7203 case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
7204 case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
7205 case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
7206 case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
7207 case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
7208 case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
7209 case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
7210 case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
7211 case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
7212 case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
7213 case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
7214 case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
7215 case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
7216 case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
7218 case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
7219 case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
7220 case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
7221 case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
7222 case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
7223 case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
7224 case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
7225 case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
7226 case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
7227 case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
7228 case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
7229 case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
7230 case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
7231 case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
7232 case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
7233 case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
7234 case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
7238 case 0x01: strcpy(insn[i],"regimm"); type=NI;
7239 op2=(source[i]>>16)&0x1f;
7242 case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
7243 case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
7244 //case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
7245 //case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
7246 //case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
7247 //case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
7248 //case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
7249 //case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
7250 //case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
7251 //case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
7252 case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
7253 case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
7254 //case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
7255 //case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
7258 case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
7259 case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
7260 case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
7261 case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
7262 case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
7263 case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
7264 case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
7265 case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
7266 case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
7267 case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
7268 case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
7269 case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
7270 case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
7271 case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
7272 case 0x10: strcpy(insn[i],"cop0"); type=NI;
7273 op2=(source[i]>>21)&0x1f;
7276 case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
7277 case 0x02: strcpy(insn[i],"CFC0"); type=COP0; break;
7278 case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
7279 case 0x06: strcpy(insn[i],"CTC0"); type=COP0; break;
7280 case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
7283 case 0x11: strcpy(insn[i],"cop1"); type=COP1;
7284 op2=(source[i]>>21)&0x1f;
7287 case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
7288 case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
7289 case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
7290 case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
7291 case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
7292 case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
7293 case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
7294 case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
7296 case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
7297 case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
7298 case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
7299 case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
7300 case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
7301 case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
7302 case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
7304 case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
7306 case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
7307 case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
7308 case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
7309 case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
7311 case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
7312 case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
7314 case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
7315 case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
7316 case 0x30: strcpy(insn[i],"LL"); type=NI; break;
7317 case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
7319 case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
7320 case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
7321 case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
7323 case 0x38: strcpy(insn[i],"SC"); type=NI; break;
7324 case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
7326 case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
7327 case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
7328 case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
7330 case 0x12: strcpy(insn[i],"COP2"); type=NI;
7331 op2=(source[i]>>21)&0x1f;
7333 if (source[i]&0x3f) { // use this hack to support old savestates with patched gte insns
7334 if (gte_handlers[source[i]&0x3f]!=NULL) {
7335 if (gte_regnames[source[i]&0x3f]!=NULL)
7336 strcpy(insn[i],gte_regnames[source[i]&0x3f]);
7338 snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
7344 case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
7345 case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
7346 case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
7347 case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
7350 case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
7351 case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
7352 case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
7353 default: strcpy(insn[i],"???"); type=NI;
7354 SysPrintf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
7358 dops[i].opcode2=op2;
7359 /* Get registers/immediates */
7361 gte_rs[i]=gte_rt[i]=0;
7364 dops[i].rs1=(source[i]>>21)&0x1f;
7366 dops[i].rt1=(source[i]>>16)&0x1f;
7368 imm[i]=(short)source[i];
7372 dops[i].rs1=(source[i]>>21)&0x1f;
7373 dops[i].rs2=(source[i]>>16)&0x1f;
7376 imm[i]=(short)source[i];
7379 // LWL/LWR only load part of the register,
7380 // therefore the target register must be treated as a source too
7381 dops[i].rs1=(source[i]>>21)&0x1f;
7382 dops[i].rs2=(source[i]>>16)&0x1f;
7383 dops[i].rt1=(source[i]>>16)&0x1f;
7385 imm[i]=(short)source[i];
7388 if (op==0x0f) dops[i].rs1=0; // LUI instruction has no source register
7389 else dops[i].rs1=(source[i]>>21)&0x1f;
7391 dops[i].rt1=(source[i]>>16)&0x1f;
7393 if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
7394 imm[i]=(unsigned short)source[i];
7396 imm[i]=(short)source[i];
7404 // The JAL instruction writes to r31.
7411 dops[i].rs1=(source[i]>>21)&0x1f;
7415 // The JALR instruction writes to rd.
7417 dops[i].rt1=(source[i]>>11)&0x1f;
7422 dops[i].rs1=(source[i]>>21)&0x1f;
7423 dops[i].rs2=(source[i]>>16)&0x1f;
7426 if(op&2) { // BGTZ/BLEZ
7431 dops[i].rs1=(source[i]>>21)&0x1f;
7435 if(op2&0x10) { // BxxAL
7437 // NOTE: If the branch is not taken, r31 is still overwritten
7441 dops[i].rs1=(source[i]>>21)&0x1f; // source
7442 dops[i].rs2=(source[i]>>16)&0x1f; // subtract amount
7443 dops[i].rt1=(source[i]>>11)&0x1f; // destination
7447 dops[i].rs1=(source[i]>>21)&0x1f; // source
7448 dops[i].rs2=(source[i]>>16)&0x1f; // divisor
7457 if(op2==0x10) dops[i].rs1=HIREG; // MFHI
7458 if(op2==0x11) dops[i].rt1=HIREG; // MTHI
7459 if(op2==0x12) dops[i].rs1=LOREG; // MFLO
7460 if(op2==0x13) dops[i].rt1=LOREG; // MTLO
7461 if((op2&0x1d)==0x10) dops[i].rt1=(source[i]>>11)&0x1f; // MFxx
7462 if((op2&0x1d)==0x11) dops[i].rs1=(source[i]>>21)&0x1f; // MTxx
7465 dops[i].rs1=(source[i]>>16)&0x1f; // target of shift
7466 dops[i].rs2=(source[i]>>21)&0x1f; // shift amount
7467 dops[i].rt1=(source[i]>>11)&0x1f; // destination
7471 dops[i].rs1=(source[i]>>16)&0x1f;
7473 dops[i].rt1=(source[i]>>11)&0x1f;
7475 imm[i]=(source[i]>>6)&0x1f;
7476 // DSxx32 instructions
7477 if(op2>=0x3c) imm[i]|=0x20;
7484 if(op2==0||op2==2) dops[i].rt1=(source[i]>>16)&0x1F; // MFC0/CFC0
7485 if(op2==4||op2==6) dops[i].rs1=(source[i]>>16)&0x1F; // MTC0/CTC0
7486 if(op2==4&&((source[i]>>11)&0x1f)==12) dops[i].rt2=CSREG; // Status
7487 if(op2==16) if((source[i]&0x3f)==0x18) dops[i].rs2=CCREG; // ERET
7494 if(op2<3) dops[i].rt1=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
7495 if(op2>3) dops[i].rs1=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
7503 if(op2<3) dops[i].rt1=(source[i]>>16)&0x1F; // MFC2/CFC2
7504 if(op2>3) dops[i].rs1=(source[i]>>16)&0x1F; // MTC2/CTC2
7506 int gr=(source[i]>>11)&0x1F;
7509 case 0x00: gte_rs[i]=1ll<<gr; break; // MFC2
7510 case 0x04: gte_rt[i]=1ll<<gr; break; // MTC2
7511 case 0x02: gte_rs[i]=1ll<<(gr+32); break; // CFC2
7512 case 0x06: gte_rt[i]=1ll<<(gr+32); break; // CTC2
7516 dops[i].rs1=(source[i]>>21)&0x1F;
7520 imm[i]=(short)source[i];
7523 dops[i].rs1=(source[i]>>21)&0x1F;
7527 imm[i]=(short)source[i];
7528 if(op==0x32) gte_rt[i]=1ll<<((source[i]>>16)&0x1F); // LWC2
7529 else gte_rs[i]=1ll<<((source[i]>>16)&0x1F); // SWC2
7536 gte_rs[i]=gte_reg_reads[source[i]&0x3f];
7537 gte_rt[i]=gte_reg_writes[source[i]&0x3f];
7538 gte_rt[i]|=1ll<<63; // every op changes flags
7539 if((source[i]&0x3f)==GTE_MVMVA) {
7540 int v = (source[i] >> 15) & 3;
7541 gte_rs[i]&=~0xe3fll;
7542 if(v==3) gte_rs[i]|=0xe00ll;
7543 else gte_rs[i]|=3ll<<(v*2);
7560 /* Calculate branch target addresses */
7562 ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
7563 else if(type==CJUMP&&dops[i].rs1==dops[i].rs2&&(op&1))
7564 ba[i]=start+i*4+8; // Ignore never taken branch
7565 else if(type==SJUMP&&dops[i].rs1==0&&!(op2&1))
7566 ba[i]=start+i*4+8; // Ignore never taken branch
7567 else if(type==CJUMP||type==SJUMP)
7568 ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
7571 /* simplify always (not)taken branches */
7572 if (type == CJUMP && dops[i].rs1 == dops[i].rs2) {
7573 dops[i].rs1 = dops[i].rs2 = 0;
7575 dops[i].itype = type = UJUMP;
7576 dops[i].rs2 = CCREG;
7579 else if (type == SJUMP && dops[i].rs1 == 0 && (op2 & 1))
7580 dops[i].itype = type = UJUMP;
7582 dops[i].is_jump = (dops[i].itype == RJUMP || dops[i].itype == UJUMP || dops[i].itype == CJUMP || dops[i].itype == SJUMP);
7583 dops[i].is_ujump = (dops[i].itype == RJUMP || dops[i].itype == UJUMP); // || (source[i] >> 16) == 0x1000 // beq r0,r0
7584 dops[i].is_load = (dops[i].itype == LOAD || dops[i].itype == LOADLR || op == 0x32); // LWC2
7585 dops[i].is_store = (dops[i].itype == STORE || dops[i].itype == STORELR || op == 0x3a); // SWC2
7587 /* messy cases to just pass over to the interpreter */
7588 if (i > 0 && dops[i-1].is_jump) {
7590 // branch in delay slot?
7591 if (dops[i].is_jump) {
7592 // don't handle first branch and call interpreter if it's hit
7593 SysPrintf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr);
7596 // basic load delay detection
7597 else if((type==LOAD||type==LOADLR||type==COP0||type==COP2||type==C2LS)&&dops[i].rt1!=0) {
7598 int t=(ba[i-1]-start)/4;
7599 if(0 <= t && t < i &&(dops[i].rt1==dops[t].rs1||dops[i].rt1==dops[t].rs2)&&dops[t].itype!=CJUMP&&dops[t].itype!=SJUMP) {
7600 // jump target wants DS result - potential load delay effect
7601 SysPrintf("load delay @%08x (%08x)\n", addr + i*4, addr);
7603 dops[t+1].bt=1; // expected return from interpreter
7605 else if(i>=2&&dops[i-2].rt1==2&&dops[i].rt1==2&&dops[i].rs1!=2&&dops[i].rs2!=2&&dops[i-1].rs1!=2&&dops[i-1].rs2!=2&&
7606 !(i>=3&&dops[i-3].is_jump)) {
7607 // v0 overwrite like this is a sign of trouble, bail out
7608 SysPrintf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr);
7613 memset(&dops[i-1], 0, sizeof(dops[i-1]));
7614 dops[i-1].itype = INTCALL;
7615 dops[i-1].rs1 = CCREG;
7618 i--; // don't compile the DS
7622 /* Is this the end of the block? */
7623 if (i > 0 && dops[i-1].is_ujump) {
7624 if(dops[i-1].rt1==0) { // Continue past subroutine call (JAL)
7628 if(stop_after_jal) done=1;
7630 if((source[i+1]&0xfc00003f)==0x0d) done=1;
7632 // Don't recompile stuff that's already compiled
7633 if(check_addr(start+i*4+4)) done=1;
7634 // Don't get too close to the limit
7635 if(i>MAXBLOCK/2) done=1;
7637 if(dops[i].itype==SYSCALL&&stop_after_jal) done=1;
7638 if(dops[i].itype==HLECALL||dops[i].itype==INTCALL) done=2;
7640 // Does the block continue due to a branch?
7643 if(ba[j]==start+i*4) done=j=0; // Branch into delay slot
7644 if(ba[j]==start+i*4+4) done=j=0;
7645 if(ba[j]==start+i*4+8) done=j=0;
7648 //assert(i<MAXBLOCK-1);
7649 if(start+i*4==pagelimit-4) done=1;
7650 assert(start+i*4<pagelimit);
7651 if (i==MAXBLOCK-1) done=1;
7652 // Stop if we're compiling junk
7653 if(dops[i].itype==NI&&dops[i].opcode==0x11) {
7654 done=stop_after_jal=1;
7655 SysPrintf("Disabled speculative precompilation\n");
7659 if (dops[i-1].is_jump) {
7660 if(start+i*4==pagelimit) {
7661 dops[i-1].itype=SPAN;
7668 /* Pass 2 - Register dependencies and branch targets */
7670 unneeded_registers(0,slen-1,0);
7672 /* Pass 3 - Register allocation */
7674 struct regstat current; // Current register allocations/status
7676 current.u=unneeded_reg[0];
7677 clear_all_regs(current.regmap);
7678 alloc_reg(¤t,0,CCREG);
7679 dirty_reg(¤t,CCREG);
7682 current.waswritten=0;
7688 // First instruction is delay slot
7693 current.regmap[HOST_BTREG]=BTREG;
7701 for(hr=0;hr<HOST_REGS;hr++)
7703 // Is this really necessary?
7704 if(current.regmap[hr]==0) current.regmap[hr]=-1;
7707 current.waswritten=0;
7710 memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
7711 regs[i].wasconst=current.isconst;
7712 regs[i].wasdirty=current.dirty;
7713 regs[i].loadedconst=0;
7714 if (!dops[i].is_jump) {
7716 current.u=unneeded_reg[i+1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7723 current.u=branch_unneeded_reg[i]&~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7724 current.u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7727 SysPrintf("oops, branch at end of block with no delay slot @%08x\n", start + i*4);
7733 ds=0; // Skip delay slot, already allocated as part of branch
7734 // ...but we need to alloc it in case something jumps here
7736 current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
7738 current.u=branch_unneeded_reg[i-1];
7740 current.u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7742 struct regstat temp;
7743 memcpy(&temp,¤t,sizeof(current));
7744 temp.wasdirty=temp.dirty;
7745 // TODO: Take into account unconditional branches, as below
7746 delayslot_alloc(&temp,i);
7747 memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
7748 regs[i].wasdirty=temp.wasdirty;
7749 regs[i].dirty=temp.dirty;
7753 // Create entry (branch target) regmap
7754 for(hr=0;hr<HOST_REGS;hr++)
7756 int r=temp.regmap[hr];
7758 if(r!=regmap_pre[i][hr]) {
7759 regs[i].regmap_entry[hr]=-1;
7764 if((current.u>>r)&1) {
7765 regs[i].regmap_entry[hr]=-1;
7766 regs[i].regmap[hr]=-1;
7767 //Don't clear regs in the delay slot as the branch might need them
7768 //current.regmap[hr]=-1;
7770 regs[i].regmap_entry[hr]=r;
7773 // First instruction expects CCREG to be allocated
7774 if(i==0&&hr==HOST_CCREG)
7775 regs[i].regmap_entry[hr]=CCREG;
7777 regs[i].regmap_entry[hr]=-1;
7781 else { // Not delay slot
7782 switch(dops[i].itype) {
7784 //current.isconst=0; // DEBUG
7785 //current.wasconst=0; // DEBUG
7786 //regs[i].wasconst=0; // DEBUG
7787 clear_const(¤t,dops[i].rt1);
7788 alloc_cc(¤t,i);
7789 dirty_reg(¤t,CCREG);
7790 if (dops[i].rt1==31) {
7791 alloc_reg(¤t,i,31);
7792 dirty_reg(¤t,31);
7793 //assert(dops[i+1].rs1!=31&&dops[i+1].rs2!=31);
7794 //assert(dops[i+1].rt1!=dops[i].rt1);
7796 alloc_reg(¤t,i,PTEMP);
7800 delayslot_alloc(¤t,i+1);
7801 //current.isconst=0; // DEBUG
7803 //printf("i=%d, isconst=%x\n",i,current.isconst);
7806 //current.isconst=0;
7807 //current.wasconst=0;
7808 //regs[i].wasconst=0;
7809 clear_const(¤t,dops[i].rs1);
7810 clear_const(¤t,dops[i].rt1);
7811 alloc_cc(¤t,i);
7812 dirty_reg(¤t,CCREG);
7813 if (!ds_writes_rjump_rs(i)) {
7814 alloc_reg(¤t,i,dops[i].rs1);
7815 if (dops[i].rt1!=0) {
7816 alloc_reg(¤t,i,dops[i].rt1);
7817 dirty_reg(¤t,dops[i].rt1);
7818 assert(dops[i+1].rs1!=dops[i].rt1&&dops[i+1].rs2!=dops[i].rt1);
7819 assert(dops[i+1].rt1!=dops[i].rt1);
7821 alloc_reg(¤t,i,PTEMP);
7825 if(dops[i].rs1==31) { // JALR
7826 alloc_reg(¤t,i,RHASH);
7827 alloc_reg(¤t,i,RHTBL);
7830 delayslot_alloc(¤t,i+1);
7832 // The delay slot overwrites our source register,
7833 // allocate a temporary register to hold the old value.
7837 delayslot_alloc(¤t,i+1);
7839 alloc_reg(¤t,i,RTEMP);
7841 //current.isconst=0; // DEBUG
7846 //current.isconst=0;
7847 //current.wasconst=0;
7848 //regs[i].wasconst=0;
7849 clear_const(¤t,dops[i].rs1);
7850 clear_const(¤t,dops[i].rs2);
7851 if((dops[i].opcode&0x3E)==4) // BEQ/BNE
7853 alloc_cc(¤t,i);
7854 dirty_reg(¤t,CCREG);
7855 if(dops[i].rs1) alloc_reg(¤t,i,dops[i].rs1);
7856 if(dops[i].rs2) alloc_reg(¤t,i,dops[i].rs2);
7857 if((dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2))||
7858 (dops[i].rs2&&(dops[i].rs2==dops[i+1].rt1||dops[i].rs2==dops[i+1].rt2))) {
7859 // The delay slot overwrites one of our conditions.
7860 // Allocate the branch condition registers instead.
7864 if(dops[i].rs1) alloc_reg(¤t,i,dops[i].rs1);
7865 if(dops[i].rs2) alloc_reg(¤t,i,dops[i].rs2);
7870 delayslot_alloc(¤t,i+1);
7874 if((dops[i].opcode&0x3E)==6) // BLEZ/BGTZ
7876 alloc_cc(¤t,i);
7877 dirty_reg(¤t,CCREG);
7878 alloc_reg(¤t,i,dops[i].rs1);
7879 if(dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2)) {
7880 // The delay slot overwrites one of our conditions.
7881 // Allocate the branch condition registers instead.
7885 if(dops[i].rs1) alloc_reg(¤t,i,dops[i].rs1);
7890 delayslot_alloc(¤t,i+1);
7894 // Don't alloc the delay slot yet because we might not execute it
7895 if((dops[i].opcode&0x3E)==0x14) // BEQL/BNEL
7900 alloc_cc(¤t,i);
7901 dirty_reg(¤t,CCREG);
7902 alloc_reg(¤t,i,dops[i].rs1);
7903 alloc_reg(¤t,i,dops[i].rs2);
7906 if((dops[i].opcode&0x3E)==0x16) // BLEZL/BGTZL
7911 alloc_cc(¤t,i);
7912 dirty_reg(¤t,CCREG);
7913 alloc_reg(¤t,i,dops[i].rs1);
7916 //current.isconst=0;
7919 //current.isconst=0;
7920 //current.wasconst=0;
7921 //regs[i].wasconst=0;
7922 clear_const(¤t,dops[i].rs1);
7923 clear_const(¤t,dops[i].rt1);
7924 //if((dops[i].opcode2&0x1E)==0x0) // BLTZ/BGEZ
7925 if((dops[i].opcode2&0x0E)==0x0) // BLTZ/BGEZ
7927 alloc_cc(¤t,i);
7928 dirty_reg(¤t,CCREG);
7929 alloc_reg(¤t,i,dops[i].rs1);
7930 if (dops[i].rt1==31) { // BLTZAL/BGEZAL
7931 alloc_reg(¤t,i,31);
7932 dirty_reg(¤t,31);
7933 //#ifdef REG_PREFETCH
7934 //alloc_reg(¤t,i,PTEMP);
7937 if((dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2)) // The delay slot overwrites the branch condition.
7938 ||(dops[i].rt1==31&&(dops[i+1].rs1==31||dops[i+1].rs2==31||dops[i+1].rt1==31||dops[i+1].rt2==31))) { // DS touches $ra
7939 // Allocate the branch condition registers instead.
7943 if(dops[i].rs1) alloc_reg(¤t,i,dops[i].rs1);
7948 delayslot_alloc(¤t,i+1);
7952 // Don't alloc the delay slot yet because we might not execute it
7953 if((dops[i].opcode2&0x1E)==0x2) // BLTZL/BGEZL
7958 alloc_cc(¤t,i);
7959 dirty_reg(¤t,CCREG);
7960 alloc_reg(¤t,i,dops[i].rs1);
7963 //current.isconst=0;
7966 imm16_alloc(¤t,i);
7970 load_alloc(¤t,i);
7974 store_alloc(¤t,i);
7977 alu_alloc(¤t,i);
7980 shift_alloc(¤t,i);
7983 multdiv_alloc(¤t,i);
7986 shiftimm_alloc(¤t,i);
7989 mov_alloc(¤t,i);
7992 cop0_alloc(¤t,i);
7997 cop2_alloc(¤t,i);
8000 c1ls_alloc(¤t,i);
8003 c2ls_alloc(¤t,i);
8006 c2op_alloc(¤t,i);
8011 syscall_alloc(¤t,i);
8014 pagespan_alloc(¤t,i);
8018 // Create entry (branch target) regmap
8019 for(hr=0;hr<HOST_REGS;hr++)
8022 r=current.regmap[hr];
8024 if(r!=regmap_pre[i][hr]) {
8025 // TODO: delay slot (?)
8026 or=get_reg(regmap_pre[i],r); // Get old mapping for this register
8027 if(or<0||(r&63)>=TEMPREG){
8028 regs[i].regmap_entry[hr]=-1;
8032 // Just move it to a different register
8033 regs[i].regmap_entry[hr]=r;
8034 // If it was dirty before, it's still dirty
8035 if((regs[i].wasdirty>>or)&1) dirty_reg(¤t,r&63);
8042 regs[i].regmap_entry[hr]=0;
8047 if((current.u>>r)&1) {
8048 regs[i].regmap_entry[hr]=-1;
8049 //regs[i].regmap[hr]=-1;
8050 current.regmap[hr]=-1;
8052 regs[i].regmap_entry[hr]=r;
8056 // Branches expect CCREG to be allocated at the target
8057 if(regmap_pre[i][hr]==CCREG)
8058 regs[i].regmap_entry[hr]=CCREG;
8060 regs[i].regmap_entry[hr]=-1;
8063 memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
8066 if(i>0&&(dops[i-1].itype==STORE||dops[i-1].itype==STORELR||(dops[i-1].itype==C2LS&&dops[i-1].opcode==0x3a))&&(u_int)imm[i-1]<0x800)
8067 current.waswritten|=1<<dops[i-1].rs1;
8068 current.waswritten&=~(1<<dops[i].rt1);
8069 current.waswritten&=~(1<<dops[i].rt2);
8070 if((dops[i].itype==STORE||dops[i].itype==STORELR||(dops[i].itype==C2LS&&dops[i].opcode==0x3a))&&(u_int)imm[i]>=0x800)
8071 current.waswritten&=~(1<<dops[i].rs1);
8073 /* Branch post-alloc */
8076 current.wasdirty=current.dirty;
8077 switch(dops[i-1].itype) {
8079 memcpy(&branch_regs[i-1],¤t,sizeof(current));
8080 branch_regs[i-1].isconst=0;
8081 branch_regs[i-1].wasconst=0;
8082 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
8083 alloc_cc(&branch_regs[i-1],i-1);
8084 dirty_reg(&branch_regs[i-1],CCREG);
8085 if(dops[i-1].rt1==31) { // JAL
8086 alloc_reg(&branch_regs[i-1],i-1,31);
8087 dirty_reg(&branch_regs[i-1],31);
8089 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8090 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
8093 memcpy(&branch_regs[i-1],¤t,sizeof(current));
8094 branch_regs[i-1].isconst=0;
8095 branch_regs[i-1].wasconst=0;
8096 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
8097 alloc_cc(&branch_regs[i-1],i-1);
8098 dirty_reg(&branch_regs[i-1],CCREG);
8099 alloc_reg(&branch_regs[i-1],i-1,dops[i-1].rs1);
8100 if(dops[i-1].rt1!=0) { // JALR
8101 alloc_reg(&branch_regs[i-1],i-1,dops[i-1].rt1);
8102 dirty_reg(&branch_regs[i-1],dops[i-1].rt1);
8105 if(dops[i-1].rs1==31) { // JALR
8106 alloc_reg(&branch_regs[i-1],i-1,RHASH);
8107 alloc_reg(&branch_regs[i-1],i-1,RHTBL);
8110 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8111 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
8114 if((dops[i-1].opcode&0x3E)==4) // BEQ/BNE
8116 alloc_cc(¤t,i-1);
8117 dirty_reg(¤t,CCREG);
8118 if((dops[i-1].rs1&&(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2))||
8119 (dops[i-1].rs2&&(dops[i-1].rs2==dops[i].rt1||dops[i-1].rs2==dops[i].rt2))) {
8120 // The delay slot overwrote one of our conditions
8121 // Delay slot goes after the test (in order)
8122 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
8124 delayslot_alloc(¤t,i);
8129 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
8130 // Alloc the branch condition registers
8131 if(dops[i-1].rs1) alloc_reg(¤t,i-1,dops[i-1].rs1);
8132 if(dops[i-1].rs2) alloc_reg(¤t,i-1,dops[i-1].rs2);
8134 memcpy(&branch_regs[i-1],¤t,sizeof(current));
8135 branch_regs[i-1].isconst=0;
8136 branch_regs[i-1].wasconst=0;
8137 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
8138 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
8141 if((dops[i-1].opcode&0x3E)==6) // BLEZ/BGTZ
8143 alloc_cc(¤t,i-1);
8144 dirty_reg(¤t,CCREG);
8145 if(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2) {
8146 // The delay slot overwrote the branch condition
8147 // Delay slot goes after the test (in order)
8148 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
8150 delayslot_alloc(¤t,i);
8155 current.u=branch_unneeded_reg[i-1]&~(1LL<<dops[i-1].rs1);
8156 // Alloc the branch condition register
8157 alloc_reg(¤t,i-1,dops[i-1].rs1);
8159 memcpy(&branch_regs[i-1],¤t,sizeof(current));
8160 branch_regs[i-1].isconst=0;
8161 branch_regs[i-1].wasconst=0;
8162 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
8163 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
8166 // Alloc the delay slot in case the branch is taken
8167 if((dops[i-1].opcode&0x3E)==0x14) // BEQL/BNEL
8169 memcpy(&branch_regs[i-1],¤t,sizeof(current));
8170 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)|(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2)))|1;
8171 alloc_cc(&branch_regs[i-1],i);
8172 dirty_reg(&branch_regs[i-1],CCREG);
8173 delayslot_alloc(&branch_regs[i-1],i);
8174 branch_regs[i-1].isconst=0;
8175 alloc_reg(¤t,i,CCREG); // Not taken path
8176 dirty_reg(¤t,CCREG);
8177 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8180 if((dops[i-1].opcode&0x3E)==0x16) // BLEZL/BGTZL
8182 memcpy(&branch_regs[i-1],¤t,sizeof(current));
8183 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)|(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2)))|1;
8184 alloc_cc(&branch_regs[i-1],i);
8185 dirty_reg(&branch_regs[i-1],CCREG);
8186 delayslot_alloc(&branch_regs[i-1],i);
8187 branch_regs[i-1].isconst=0;
8188 alloc_reg(¤t,i,CCREG); // Not taken path
8189 dirty_reg(¤t,CCREG);
8190 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8194 //if((dops[i-1].opcode2&0x1E)==0) // BLTZ/BGEZ
8195 if((dops[i-1].opcode2&0x0E)==0) // BLTZ/BGEZ
8197 alloc_cc(¤t,i-1);
8198 dirty_reg(¤t,CCREG);
8199 if(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2) {
8200 // The delay slot overwrote the branch condition
8201 // Delay slot goes after the test (in order)
8202 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
8204 delayslot_alloc(¤t,i);
8209 current.u=branch_unneeded_reg[i-1]&~(1LL<<dops[i-1].rs1);
8210 // Alloc the branch condition register
8211 alloc_reg(¤t,i-1,dops[i-1].rs1);
8213 memcpy(&branch_regs[i-1],¤t,sizeof(current));
8214 branch_regs[i-1].isconst=0;
8215 branch_regs[i-1].wasconst=0;
8216 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
8217 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
8220 // Alloc the delay slot in case the branch is taken
8221 if((dops[i-1].opcode2&0x1E)==2) // BLTZL/BGEZL
8223 memcpy(&branch_regs[i-1],¤t,sizeof(current));
8224 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)|(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2)))|1;
8225 alloc_cc(&branch_regs[i-1],i);
8226 dirty_reg(&branch_regs[i-1],CCREG);
8227 delayslot_alloc(&branch_regs[i-1],i);
8228 branch_regs[i-1].isconst=0;
8229 alloc_reg(¤t,i,CCREG); // Not taken path
8230 dirty_reg(¤t,CCREG);
8231 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8233 // FIXME: BLTZAL/BGEZAL
8234 if(dops[i-1].opcode2&0x10) { // BxxZAL
8235 alloc_reg(&branch_regs[i-1],i-1,31);
8236 dirty_reg(&branch_regs[i-1],31);
8241 if (dops[i-1].is_ujump)
8243 if(dops[i-1].rt1==31) // JAL/JALR
8245 // Subroutine call will return here, don't alloc any registers
8247 clear_all_regs(current.regmap);
8248 alloc_reg(¤t,i,CCREG);
8249 dirty_reg(¤t,CCREG);
8253 // Internal branch will jump here, match registers to caller
8255 clear_all_regs(current.regmap);
8256 alloc_reg(¤t,i,CCREG);
8257 dirty_reg(¤t,CCREG);
8260 if(ba[j]==start+i*4+4) {
8261 memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
8262 current.dirty=branch_regs[j].dirty;
8267 if(ba[j]==start+i*4+4) {
8268 for(hr=0;hr<HOST_REGS;hr++) {
8269 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
8270 current.regmap[hr]=-1;
8272 current.dirty&=branch_regs[j].dirty;
8281 // Count cycles in between branches
8282 ccadj[i] = CLOCK_ADJUST(cc);
8283 if (i > 0 && (dops[i-1].is_jump || dops[i].itype == SYSCALL || dops[i].itype == HLECALL))
8287 #if !defined(DRC_DBG)
8288 else if(dops[i].itype==C2OP&>e_cycletab[source[i]&0x3f]>2)
8290 // this should really be removed since the real stalls have been implemented,
8291 // but doing so causes sizeable perf regression against the older version
8292 u_int gtec = gte_cycletab[source[i] & 0x3f];
8293 cc += HACK_ENABLED(NDHACK_NO_STALLS) ? gtec/2 : 2;
8295 else if(i>1&&dops[i].itype==STORE&&dops[i-1].itype==STORE&&dops[i-2].itype==STORE&&!dops[i].bt)
8299 else if(dops[i].itype==C2LS)
8301 // same as with C2OP
8302 cc += HACK_ENABLED(NDHACK_NO_STALLS) ? 4 : 2;
8310 if(!dops[i].is_ds) {
8311 regs[i].dirty=current.dirty;
8312 regs[i].isconst=current.isconst;
8313 memcpy(constmap[i],current_constmap,sizeof(constmap[i]));
8315 for(hr=0;hr<HOST_REGS;hr++) {
8316 if(hr!=EXCLUDE_REG&®s[i].regmap[hr]>=0) {
8317 if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
8318 regs[i].wasconst&=~(1<<hr);
8322 if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
8323 regs[i].waswritten=current.waswritten;
8326 /* Pass 4 - Cull unused host registers */
8330 for (i=slen-1;i>=0;i--)
8335 if(ba[i]<start || ba[i]>=(start+slen*4))
8337 // Branch out of this block, don't need anything
8343 // Need whatever matches the target
8345 int t=(ba[i]-start)>>2;
8346 for(hr=0;hr<HOST_REGS;hr++)
8348 if(regs[i].regmap_entry[hr]>=0) {
8349 if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
8353 // Conditional branch may need registers for following instructions
8354 if (!dops[i].is_ujump)
8357 nr|=needed_reg[i+2];
8358 for(hr=0;hr<HOST_REGS;hr++)
8360 if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
8361 //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
8365 // Don't need stuff which is overwritten
8366 //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
8367 //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
8368 // Merge in delay slot
8369 for(hr=0;hr<HOST_REGS;hr++)
8371 if(dops[i+1].rt1&&dops[i+1].rt1==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
8372 if(dops[i+1].rt2&&dops[i+1].rt2==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
8373 if(dops[i+1].rs1==regmap_pre[i][hr]) nr|=1<<hr;
8374 if(dops[i+1].rs2==regmap_pre[i][hr]) nr|=1<<hr;
8375 if(dops[i+1].rs1==regs[i].regmap_entry[hr]) nr|=1<<hr;
8376 if(dops[i+1].rs2==regs[i].regmap_entry[hr]) nr|=1<<hr;
8377 if(ram_offset && (dops[i+1].is_load || dops[i+1].is_store)) {
8378 if(regmap_pre[i][hr]==ROREG) nr|=1<<hr;
8379 if(regs[i].regmap_entry[hr]==ROREG) nr|=1<<hr;
8381 if(dops[i+1].is_store) {
8382 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
8383 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
8387 else if(dops[i].itype==SYSCALL||dops[i].itype==HLECALL||dops[i].itype==INTCALL)
8389 // SYSCALL instruction (software interrupt)
8392 else if(dops[i].itype==COP0 && (source[i]&0x3f)==0x18)
8394 // ERET instruction (return from interrupt)
8400 for(hr=0;hr<HOST_REGS;hr++) {
8401 if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
8402 if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
8403 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
8404 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
8408 for(hr=0;hr<HOST_REGS;hr++)
8410 // Overwritten registers are not needed
8411 if(dops[i].rt1&&dops[i].rt1==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
8412 if(dops[i].rt2&&dops[i].rt2==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
8413 if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
8414 // Source registers are needed
8415 if(dops[i].rs1==regmap_pre[i][hr]) nr|=1<<hr;
8416 if(dops[i].rs2==regmap_pre[i][hr]) nr|=1<<hr;
8417 if(dops[i].rs1==regs[i].regmap_entry[hr]) nr|=1<<hr;
8418 if(dops[i].rs2==regs[i].regmap_entry[hr]) nr|=1<<hr;
8419 if(ram_offset && (dops[i].is_load || dops[i].is_store)) {
8420 if(regmap_pre[i][hr]==ROREG) nr|=1<<hr;
8421 if(regs[i].regmap_entry[hr]==ROREG) nr|=1<<hr;
8423 if(dops[i].is_store) {
8424 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
8425 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
8427 // Don't store a register immediately after writing it,
8428 // may prevent dual-issue.
8429 // But do so if this is a branch target, otherwise we
8430 // might have to load the register before the branch.
8431 if(i>0&&!dops[i].bt&&((regs[i].wasdirty>>hr)&1)) {
8432 if((regmap_pre[i][hr]>0&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1))) {
8433 if(dops[i-1].rt1==(regmap_pre[i][hr]&63)) nr|=1<<hr;
8434 if(dops[i-1].rt2==(regmap_pre[i][hr]&63)) nr|=1<<hr;
8436 if((regs[i].regmap_entry[hr]>0&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1))) {
8437 if(dops[i-1].rt1==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
8438 if(dops[i-1].rt2==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
8442 // Cycle count is needed at branches. Assume it is needed at the target too.
8443 if(i==0||dops[i].bt||dops[i].itype==CJUMP||dops[i].itype==SPAN) {
8444 if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
8445 if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
8450 // Deallocate unneeded registers
8451 for(hr=0;hr<HOST_REGS;hr++)
8454 if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
8457 int map1 = 0, map2 = 0, temp = 0; // or -1 ??
8458 if (dops[i+1].is_load || dops[i+1].is_store)
8460 if (dops[i+1].is_store)
8462 if(dops[i+1].itype==LOADLR || dops[i+1].itype==STORELR || dops[i+1].itype==C2LS)
8464 if((regs[i].regmap[hr]&63)!=dops[i].rs1 && (regs[i].regmap[hr]&63)!=dops[i].rs2 &&
8465 (regs[i].regmap[hr]&63)!=dops[i].rt1 && (regs[i].regmap[hr]&63)!=dops[i].rt2 &&
8466 (regs[i].regmap[hr]&63)!=dops[i+1].rt1 && (regs[i].regmap[hr]&63)!=dops[i+1].rt2 &&
8467 regs[i].regmap[hr]!=dops[i+1].rs1 && regs[i].regmap[hr]!=dops[i+1].rs2 &&
8468 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
8469 regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
8470 regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
8471 regs[i].regmap[hr]!=map1 && regs[i].regmap[hr]!=map2)
8473 regs[i].regmap[hr]=-1;
8474 regs[i].isconst&=~(1<<hr);
8475 if((branch_regs[i].regmap[hr]&63)!=dops[i].rs1 && (branch_regs[i].regmap[hr]&63)!=dops[i].rs2 &&
8476 (branch_regs[i].regmap[hr]&63)!=dops[i].rt1 && (branch_regs[i].regmap[hr]&63)!=dops[i].rt2 &&
8477 (branch_regs[i].regmap[hr]&63)!=dops[i+1].rt1 && (branch_regs[i].regmap[hr]&63)!=dops[i+1].rt2 &&
8478 branch_regs[i].regmap[hr]!=dops[i+1].rs1 && branch_regs[i].regmap[hr]!=dops[i+1].rs2 &&
8479 (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
8480 branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
8481 branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
8482 branch_regs[i].regmap[hr]!=map1 && branch_regs[i].regmap[hr]!=map2)
8484 branch_regs[i].regmap[hr]=-1;
8485 branch_regs[i].regmap_entry[hr]=-1;
8486 if (!dops[i].is_ujump)
8489 regmap_pre[i+2][hr]=-1;
8490 regs[i+2].wasconst&=~(1<<hr);
8501 int map1 = -1, map2 = -1, temp=-1;
8502 if (dops[i].is_load || dops[i].is_store)
8504 if (dops[i].is_store)
8506 if (dops[i].itype==LOADLR || dops[i].itype==STORELR || dops[i].itype==C2LS)
8508 if((regs[i].regmap[hr]&63)!=dops[i].rt1 && (regs[i].regmap[hr]&63)!=dops[i].rt2 &&
8509 regs[i].regmap[hr]!=dops[i].rs1 && regs[i].regmap[hr]!=dops[i].rs2 &&
8510 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map1 && regs[i].regmap[hr]!=map2 &&
8511 //(dops[i].itype!=SPAN||regs[i].regmap[hr]!=CCREG)
8512 regs[i].regmap[hr] != CCREG)
8514 if(i<slen-1&&!dops[i].is_ds) {
8515 assert(regs[i].regmap[hr]<64);
8516 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]>0)
8517 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
8519 SysPrintf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
8520 assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
8522 regmap_pre[i+1][hr]=-1;
8523 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
8524 regs[i+1].wasconst&=~(1<<hr);
8526 regs[i].regmap[hr]=-1;
8527 regs[i].isconst&=~(1<<hr);
8535 /* Pass 5 - Pre-allocate registers */
8537 // If a register is allocated during a loop, try to allocate it for the
8538 // entire loop, if possible. This avoids loading/storing registers
8539 // inside of the loop.
8541 signed char f_regmap[HOST_REGS];
8542 clear_all_regs(f_regmap);
8543 for(i=0;i<slen-1;i++)
8545 if(dops[i].itype==UJUMP||dops[i].itype==CJUMP||dops[i].itype==SJUMP)
8547 if(ba[i]>=start && ba[i]<(start+i*4))
8548 if(dops[i+1].itype==NOP||dops[i+1].itype==MOV||dops[i+1].itype==ALU
8549 ||dops[i+1].itype==SHIFTIMM||dops[i+1].itype==IMM16||dops[i+1].itype==LOAD
8550 ||dops[i+1].itype==STORE||dops[i+1].itype==STORELR||dops[i+1].itype==C1LS
8551 ||dops[i+1].itype==SHIFT||dops[i+1].itype==COP1
8552 ||dops[i+1].itype==COP2||dops[i+1].itype==C2LS||dops[i+1].itype==C2OP)
8554 int t=(ba[i]-start)>>2;
8555 if(t > 0 && !dops[t-1].is_jump) // loop_preload can't handle jumps into delay slots
8556 if(t<2||(dops[t-2].itype!=UJUMP&&dops[t-2].itype!=RJUMP)||dops[t-2].rt1!=31) // call/ret assumes no registers allocated
8557 for(hr=0;hr<HOST_REGS;hr++)
8559 if(regs[i].regmap[hr]>=0) {
8560 if(f_regmap[hr]!=regs[i].regmap[hr]) {
8561 // dealloc old register
8563 for(n=0;n<HOST_REGS;n++)
8565 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
8567 // and alloc new one
8568 f_regmap[hr]=regs[i].regmap[hr];
8571 if(branch_regs[i].regmap[hr]>=0) {
8572 if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
8573 // dealloc old register
8575 for(n=0;n<HOST_REGS;n++)
8577 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
8579 // and alloc new one
8580 f_regmap[hr]=branch_regs[i].regmap[hr];
8584 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
8585 f_regmap[hr]=branch_regs[i].regmap[hr];
8587 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
8588 f_regmap[hr]=branch_regs[i].regmap[hr];
8590 // Avoid dirty->clean transition
8591 #ifdef DESTRUCTIVE_WRITEBACK
8592 if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
8594 // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
8595 // case above, however it's always a good idea. We can't hoist the
8596 // load if the register was already allocated, so there's no point
8597 // wasting time analyzing most of these cases. It only "succeeds"
8598 // when the mapping was different and the load can be replaced with
8599 // a mov, which is of negligible benefit. So such cases are
8601 if(f_regmap[hr]>0) {
8602 if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
8606 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
8607 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
8609 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
8610 //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
8612 if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
8613 if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
8615 if(get_reg(regs[i].regmap,r&63)<0) break;
8616 if(get_reg(branch_regs[i].regmap,r&63)<0) break;
8619 while(k>1&®s[k-1].regmap[hr]==-1) {
8620 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
8621 //printf("no free regs for store %x\n",start+(k-1)*4);
8624 if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
8625 //printf("no-match due to different register\n");
8628 if (dops[k-2].is_jump) {
8629 //printf("no-match due to branch\n");
8632 // call/ret fast path assumes no registers allocated
8633 if(k>2&&(dops[k-3].itype==UJUMP||dops[k-3].itype==RJUMP)&&dops[k-3].rt1==31) {
8639 if(regs[k-1].regmap[hr]==f_regmap[hr]&®map_pre[k][hr]==f_regmap[hr]) {
8640 //printf("Extend r%d, %x ->\n",hr,start+k*4);
8642 regs[k].regmap_entry[hr]=f_regmap[hr];
8643 regs[k].regmap[hr]=f_regmap[hr];
8644 regmap_pre[k+1][hr]=f_regmap[hr];
8645 regs[k].wasdirty&=~(1<<hr);
8646 regs[k].dirty&=~(1<<hr);
8647 regs[k].wasdirty|=(1<<hr)®s[k-1].dirty;
8648 regs[k].dirty|=(1<<hr)®s[k].wasdirty;
8649 regs[k].wasconst&=~(1<<hr);
8650 regs[k].isconst&=~(1<<hr);
8655 //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
8658 assert(regs[i-1].regmap[hr]==f_regmap[hr]);
8659 if(regs[i-1].regmap[hr]==f_regmap[hr]&®map_pre[i][hr]==f_regmap[hr]) {
8660 //printf("OK fill %x (r%d)\n",start+i*4,hr);
8661 regs[i].regmap_entry[hr]=f_regmap[hr];
8662 regs[i].regmap[hr]=f_regmap[hr];
8663 regs[i].wasdirty&=~(1<<hr);
8664 regs[i].dirty&=~(1<<hr);
8665 regs[i].wasdirty|=(1<<hr)®s[i-1].dirty;
8666 regs[i].dirty|=(1<<hr)®s[i-1].dirty;
8667 regs[i].wasconst&=~(1<<hr);
8668 regs[i].isconst&=~(1<<hr);
8669 branch_regs[i].regmap_entry[hr]=f_regmap[hr];
8670 branch_regs[i].wasdirty&=~(1<<hr);
8671 branch_regs[i].wasdirty|=(1<<hr)®s[i].dirty;
8672 branch_regs[i].regmap[hr]=f_regmap[hr];
8673 branch_regs[i].dirty&=~(1<<hr);
8674 branch_regs[i].dirty|=(1<<hr)®s[i].dirty;
8675 branch_regs[i].wasconst&=~(1<<hr);
8676 branch_regs[i].isconst&=~(1<<hr);
8677 if (!dops[i].is_ujump) {
8678 regmap_pre[i+2][hr]=f_regmap[hr];
8679 regs[i+2].wasdirty&=~(1<<hr);
8680 regs[i+2].wasdirty|=(1<<hr)®s[i].dirty;
8685 // Alloc register clean at beginning of loop,
8686 // but may dirty it in pass 6
8687 regs[k].regmap_entry[hr]=f_regmap[hr];
8688 regs[k].regmap[hr]=f_regmap[hr];
8689 regs[k].dirty&=~(1<<hr);
8690 regs[k].wasconst&=~(1<<hr);
8691 regs[k].isconst&=~(1<<hr);
8692 if (dops[k].is_jump) {
8693 branch_regs[k].regmap_entry[hr]=f_regmap[hr];
8694 branch_regs[k].regmap[hr]=f_regmap[hr];
8695 branch_regs[k].dirty&=~(1<<hr);
8696 branch_regs[k].wasconst&=~(1<<hr);
8697 branch_regs[k].isconst&=~(1<<hr);
8698 if (!dops[k].is_ujump) {
8699 regmap_pre[k+2][hr]=f_regmap[hr];
8700 regs[k+2].wasdirty&=~(1<<hr);
8705 regmap_pre[k+1][hr]=f_regmap[hr];
8706 regs[k+1].wasdirty&=~(1<<hr);
8709 if(regs[j].regmap[hr]==f_regmap[hr])
8710 regs[j].regmap_entry[hr]=f_regmap[hr];
8714 if(regs[j].regmap[hr]>=0)
8716 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
8717 //printf("no-match due to different register\n");
8720 if (dops[j].is_ujump)
8722 // Stop on unconditional branch
8725 if(dops[j].itype==CJUMP||dops[j].itype==SJUMP)
8728 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
8731 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
8734 if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
8735 //printf("no-match due to different register (branch)\n");
8739 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
8740 //printf("No free regs for store %x\n",start+j*4);
8743 assert(f_regmap[hr]<64);
8750 // Non branch or undetermined branch target
8751 for(hr=0;hr<HOST_REGS;hr++)
8753 if(hr!=EXCLUDE_REG) {
8754 if(regs[i].regmap[hr]>=0) {
8755 if(f_regmap[hr]!=regs[i].regmap[hr]) {
8756 // dealloc old register
8758 for(n=0;n<HOST_REGS;n++)
8760 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
8762 // and alloc new one
8763 f_regmap[hr]=regs[i].regmap[hr];
8768 // Try to restore cycle count at branch targets
8770 for(j=i;j<slen-1;j++) {
8771 if(regs[j].regmap[HOST_CCREG]!=-1) break;
8772 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
8773 //printf("no free regs for store %x\n",start+j*4);
8777 if(regs[j].regmap[HOST_CCREG]==CCREG) {
8779 //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
8781 regs[k].regmap_entry[HOST_CCREG]=CCREG;
8782 regs[k].regmap[HOST_CCREG]=CCREG;
8783 regmap_pre[k+1][HOST_CCREG]=CCREG;
8784 regs[k+1].wasdirty|=1<<HOST_CCREG;
8785 regs[k].dirty|=1<<HOST_CCREG;
8786 regs[k].wasconst&=~(1<<HOST_CCREG);
8787 regs[k].isconst&=~(1<<HOST_CCREG);
8790 regs[j].regmap_entry[HOST_CCREG]=CCREG;
8792 // Work backwards from the branch target
8793 if(j>i&&f_regmap[HOST_CCREG]==CCREG)
8795 //printf("Extend backwards\n");
8798 while(regs[k-1].regmap[HOST_CCREG]==-1) {
8799 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
8800 //printf("no free regs for store %x\n",start+(k-1)*4);
8805 if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
8806 //printf("Extend CC, %x ->\n",start+k*4);
8808 regs[k].regmap_entry[HOST_CCREG]=CCREG;
8809 regs[k].regmap[HOST_CCREG]=CCREG;
8810 regmap_pre[k+1][HOST_CCREG]=CCREG;
8811 regs[k+1].wasdirty|=1<<HOST_CCREG;
8812 regs[k].dirty|=1<<HOST_CCREG;
8813 regs[k].wasconst&=~(1<<HOST_CCREG);
8814 regs[k].isconst&=~(1<<HOST_CCREG);
8819 //printf("Fail Extend CC, %x ->\n",start+k*4);
8823 if(dops[i].itype!=STORE&&dops[i].itype!=STORELR&&dops[i].itype!=C1LS&&dops[i].itype!=SHIFT&&
8824 dops[i].itype!=NOP&&dops[i].itype!=MOV&&dops[i].itype!=ALU&&dops[i].itype!=SHIFTIMM&&
8825 dops[i].itype!=IMM16&&dops[i].itype!=LOAD&&dops[i].itype!=COP1)
8827 memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
8832 // This allocates registers (if possible) one instruction prior
8833 // to use, which can avoid a load-use penalty on certain CPUs.
8834 for(i=0;i<slen-1;i++)
8836 if (!i || !dops[i-1].is_jump)
8840 if(dops[i].itype==ALU||dops[i].itype==MOV||dops[i].itype==LOAD||dops[i].itype==SHIFTIMM||dops[i].itype==IMM16
8841 ||((dops[i].itype==COP1||dops[i].itype==COP2)&&dops[i].opcode2<3))
8844 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rs1))>=0)
8846 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
8848 regs[i].regmap[hr]=regs[i+1].regmap[hr];
8849 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
8850 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
8851 regs[i].isconst&=~(1<<hr);
8852 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8853 constmap[i][hr]=constmap[i+1][hr];
8854 regs[i+1].wasdirty&=~(1<<hr);
8855 regs[i].dirty&=~(1<<hr);
8860 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rs2))>=0)
8862 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
8864 regs[i].regmap[hr]=regs[i+1].regmap[hr];
8865 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
8866 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
8867 regs[i].isconst&=~(1<<hr);
8868 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8869 constmap[i][hr]=constmap[i+1][hr];
8870 regs[i+1].wasdirty&=~(1<<hr);
8871 regs[i].dirty&=~(1<<hr);
8875 // Preload target address for load instruction (non-constant)
8876 if(dops[i+1].itype==LOAD&&dops[i+1].rs1&&get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8877 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rt1))>=0)
8879 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
8881 regs[i].regmap[hr]=dops[i+1].rs1;
8882 regmap_pre[i+1][hr]=dops[i+1].rs1;
8883 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8884 regs[i].isconst&=~(1<<hr);
8885 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8886 constmap[i][hr]=constmap[i+1][hr];
8887 regs[i+1].wasdirty&=~(1<<hr);
8888 regs[i].dirty&=~(1<<hr);
8892 // Load source into target register
8893 if(dops[i+1].lt1&&get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8894 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rt1))>=0)
8896 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
8898 regs[i].regmap[hr]=dops[i+1].rs1;
8899 regmap_pre[i+1][hr]=dops[i+1].rs1;
8900 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8901 regs[i].isconst&=~(1<<hr);
8902 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8903 constmap[i][hr]=constmap[i+1][hr];
8904 regs[i+1].wasdirty&=~(1<<hr);
8905 regs[i].dirty&=~(1<<hr);
8909 // Address for store instruction (non-constant)
8910 if(dops[i+1].itype==STORE||dops[i+1].itype==STORELR
8911 ||(dops[i+1].opcode&0x3b)==0x39||(dops[i+1].opcode&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
8912 if(get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8913 hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
8914 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
8915 else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
8917 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
8919 regs[i].regmap[hr]=dops[i+1].rs1;
8920 regmap_pre[i+1][hr]=dops[i+1].rs1;
8921 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8922 regs[i].isconst&=~(1<<hr);
8923 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8924 constmap[i][hr]=constmap[i+1][hr];
8925 regs[i+1].wasdirty&=~(1<<hr);
8926 regs[i].dirty&=~(1<<hr);
8930 if(dops[i+1].itype==LOADLR||(dops[i+1].opcode&0x3b)==0x31||(dops[i+1].opcode&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
8931 if(get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8933 hr=get_reg(regs[i+1].regmap,FTEMP);
8935 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
8937 regs[i].regmap[hr]=dops[i+1].rs1;
8938 regmap_pre[i+1][hr]=dops[i+1].rs1;
8939 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8940 regs[i].isconst&=~(1<<hr);
8941 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8942 constmap[i][hr]=constmap[i+1][hr];
8943 regs[i+1].wasdirty&=~(1<<hr);
8944 regs[i].dirty&=~(1<<hr);
8946 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
8948 // move it to another register
8949 regs[i+1].regmap[hr]=-1;
8950 regmap_pre[i+2][hr]=-1;
8951 regs[i+1].regmap[nr]=FTEMP;
8952 regmap_pre[i+2][nr]=FTEMP;
8953 regs[i].regmap[nr]=dops[i+1].rs1;
8954 regmap_pre[i+1][nr]=dops[i+1].rs1;
8955 regs[i+1].regmap_entry[nr]=dops[i+1].rs1;
8956 regs[i].isconst&=~(1<<nr);
8957 regs[i+1].isconst&=~(1<<nr);
8958 regs[i].dirty&=~(1<<nr);
8959 regs[i+1].wasdirty&=~(1<<nr);
8960 regs[i+1].dirty&=~(1<<nr);
8961 regs[i+2].wasdirty&=~(1<<nr);
8965 if(dops[i+1].itype==LOAD||dops[i+1].itype==LOADLR||dops[i+1].itype==STORE||dops[i+1].itype==STORELR/*||dops[i+1].itype==C1LS||||dops[i+1].itype==C2LS*/) {
8966 if(dops[i+1].itype==LOAD)
8967 hr=get_reg(regs[i+1].regmap,dops[i+1].rt1);
8968 if(dops[i+1].itype==LOADLR||(dops[i+1].opcode&0x3b)==0x31||(dops[i+1].opcode&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
8969 hr=get_reg(regs[i+1].regmap,FTEMP);
8970 if(dops[i+1].itype==STORE||dops[i+1].itype==STORELR||(dops[i+1].opcode&0x3b)==0x39||(dops[i+1].opcode&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
8971 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
8972 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
8974 if(hr>=0&®s[i].regmap[hr]<0) {
8975 int rs=get_reg(regs[i+1].regmap,dops[i+1].rs1);
8976 if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
8977 regs[i].regmap[hr]=AGEN1+((i+1)&1);
8978 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
8979 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
8980 regs[i].isconst&=~(1<<hr);
8981 regs[i+1].wasdirty&=~(1<<hr);
8982 regs[i].dirty&=~(1<<hr);
8991 /* Pass 6 - Optimize clean/dirty state */
8992 clean_registers(0,slen-1,1);
8994 /* Pass 7 - Identify 32-bit registers */
8995 for (i=slen-1;i>=0;i--)
8997 if(dops[i].itype==CJUMP||dops[i].itype==SJUMP)
8999 // Conditional branch
9000 if((source[i]>>16)!=0x1000&&i<slen-2) {
9001 // Mark this address as a branch target since it may be called
9002 // upon return from interrupt
9008 if(dops[slen-1].itype==SPAN) {
9009 dops[slen-1].bt=1; // Mark as a branch target so instruction can restart after exception
9013 /* Debug/disassembly */
9018 for(r=1;r<=CCREG;r++) {
9019 if((unneeded_reg[i]>>r)&1) {
9020 if(r==HIREG) printf(" HI");
9021 else if(r==LOREG) printf(" LO");
9022 else printf(" r%d",r);
9026 #if defined(__i386__) || defined(__x86_64__)
9027 printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
9030 printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
9032 #if defined(__i386__) || defined(__x86_64__)
9034 if(needed_reg[i]&1) printf("eax ");
9035 if((needed_reg[i]>>1)&1) printf("ecx ");
9036 if((needed_reg[i]>>2)&1) printf("edx ");
9037 if((needed_reg[i]>>3)&1) printf("ebx ");
9038 if((needed_reg[i]>>5)&1) printf("ebp ");
9039 if((needed_reg[i]>>6)&1) printf("esi ");
9040 if((needed_reg[i]>>7)&1) printf("edi ");
9042 printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
9044 if(regs[i].wasdirty&1) printf("eax ");
9045 if((regs[i].wasdirty>>1)&1) printf("ecx ");
9046 if((regs[i].wasdirty>>2)&1) printf("edx ");
9047 if((regs[i].wasdirty>>3)&1) printf("ebx ");
9048 if((regs[i].wasdirty>>5)&1) printf("ebp ");
9049 if((regs[i].wasdirty>>6)&1) printf("esi ");
9050 if((regs[i].wasdirty>>7)&1) printf("edi ");
9053 printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
9055 if(regs[i].wasdirty&1) printf("r0 ");
9056 if((regs[i].wasdirty>>1)&1) printf("r1 ");
9057 if((regs[i].wasdirty>>2)&1) printf("r2 ");
9058 if((regs[i].wasdirty>>3)&1) printf("r3 ");
9059 if((regs[i].wasdirty>>4)&1) printf("r4 ");
9060 if((regs[i].wasdirty>>5)&1) printf("r5 ");
9061 if((regs[i].wasdirty>>6)&1) printf("r6 ");
9062 if((regs[i].wasdirty>>7)&1) printf("r7 ");
9063 if((regs[i].wasdirty>>8)&1) printf("r8 ");
9064 if((regs[i].wasdirty>>9)&1) printf("r9 ");
9065 if((regs[i].wasdirty>>10)&1) printf("r10 ");
9066 if((regs[i].wasdirty>>12)&1) printf("r12 ");
9069 disassemble_inst(i);
9070 //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
9071 #if defined(__i386__) || defined(__x86_64__)
9072 printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
9073 if(regs[i].dirty&1) printf("eax ");
9074 if((regs[i].dirty>>1)&1) printf("ecx ");
9075 if((regs[i].dirty>>2)&1) printf("edx ");
9076 if((regs[i].dirty>>3)&1) printf("ebx ");
9077 if((regs[i].dirty>>5)&1) printf("ebp ");
9078 if((regs[i].dirty>>6)&1) printf("esi ");
9079 if((regs[i].dirty>>7)&1) printf("edi ");
9082 printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
9083 if(regs[i].dirty&1) printf("r0 ");
9084 if((regs[i].dirty>>1)&1) printf("r1 ");
9085 if((regs[i].dirty>>2)&1) printf("r2 ");
9086 if((regs[i].dirty>>3)&1) printf("r3 ");
9087 if((regs[i].dirty>>4)&1) printf("r4 ");
9088 if((regs[i].dirty>>5)&1) printf("r5 ");
9089 if((regs[i].dirty>>6)&1) printf("r6 ");
9090 if((regs[i].dirty>>7)&1) printf("r7 ");
9091 if((regs[i].dirty>>8)&1) printf("r8 ");
9092 if((regs[i].dirty>>9)&1) printf("r9 ");
9093 if((regs[i].dirty>>10)&1) printf("r10 ");
9094 if((regs[i].dirty>>12)&1) printf("r12 ");
9097 if(regs[i].isconst) {
9098 printf("constants: ");
9099 #if defined(__i386__) || defined(__x86_64__)
9100 if(regs[i].isconst&1) printf("eax=%x ",(u_int)constmap[i][0]);
9101 if((regs[i].isconst>>1)&1) printf("ecx=%x ",(u_int)constmap[i][1]);
9102 if((regs[i].isconst>>2)&1) printf("edx=%x ",(u_int)constmap[i][2]);
9103 if((regs[i].isconst>>3)&1) printf("ebx=%x ",(u_int)constmap[i][3]);
9104 if((regs[i].isconst>>5)&1) printf("ebp=%x ",(u_int)constmap[i][5]);
9105 if((regs[i].isconst>>6)&1) printf("esi=%x ",(u_int)constmap[i][6]);
9106 if((regs[i].isconst>>7)&1) printf("edi=%x ",(u_int)constmap[i][7]);
9108 #if defined(__arm__) || defined(__aarch64__)
9110 for (r = 0; r < ARRAY_SIZE(constmap[i]); r++)
9111 if ((regs[i].isconst >> r) & 1)
9112 printf(" r%d=%x", r, (u_int)constmap[i][r]);
9116 if(dops[i].is_jump) {
9117 #if defined(__i386__) || defined(__x86_64__)
9118 printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
9119 if(branch_regs[i].dirty&1) printf("eax ");
9120 if((branch_regs[i].dirty>>1)&1) printf("ecx ");
9121 if((branch_regs[i].dirty>>2)&1) printf("edx ");
9122 if((branch_regs[i].dirty>>3)&1) printf("ebx ");
9123 if((branch_regs[i].dirty>>5)&1) printf("ebp ");
9124 if((branch_regs[i].dirty>>6)&1) printf("esi ");
9125 if((branch_regs[i].dirty>>7)&1) printf("edi ");
9128 printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
9129 if(branch_regs[i].dirty&1) printf("r0 ");
9130 if((branch_regs[i].dirty>>1)&1) printf("r1 ");
9131 if((branch_regs[i].dirty>>2)&1) printf("r2 ");
9132 if((branch_regs[i].dirty>>3)&1) printf("r3 ");
9133 if((branch_regs[i].dirty>>4)&1) printf("r4 ");
9134 if((branch_regs[i].dirty>>5)&1) printf("r5 ");
9135 if((branch_regs[i].dirty>>6)&1) printf("r6 ");
9136 if((branch_regs[i].dirty>>7)&1) printf("r7 ");
9137 if((branch_regs[i].dirty>>8)&1) printf("r8 ");
9138 if((branch_regs[i].dirty>>9)&1) printf("r9 ");
9139 if((branch_regs[i].dirty>>10)&1) printf("r10 ");
9140 if((branch_regs[i].dirty>>12)&1) printf("r12 ");
9146 /* Pass 8 - Assembly */
9147 linkcount=0;stubcount=0;
9148 ds=0;is_delayslot=0;
9150 void *beginning=start_block();
9155 void *instr_addr0_override = NULL;
9157 if (start == 0x80030000) {
9158 // nasty hack for the fastbios thing
9159 // override block entry to this code
9160 instr_addr0_override = out;
9161 emit_movimm(start,0);
9162 // abuse io address var as a flag that we
9163 // have already returned here once
9164 emit_readword(&address,1);
9165 emit_writeword(0,&pcaddr);
9166 emit_writeword(0,&address);
9169 emit_jeq(out + 4*2);
9170 emit_far_jump(new_dyna_leave);
9172 emit_jne(new_dyna_leave);
9177 //if(ds) printf("ds: ");
9178 disassemble_inst(i);
9180 ds=0; // Skip delay slot
9181 if(dops[i].bt) assem_debug("OOPS - branch into delay slot\n");
9182 instr_addr[i] = NULL;
9184 speculate_register_values(i);
9185 #ifndef DESTRUCTIVE_WRITEBACK
9186 if (i < 2 || !dops[i-2].is_ujump)
9188 wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,unneeded_reg[i]);
9190 if((dops[i].itype==CJUMP||dops[i].itype==SJUMP)) {
9191 dirty_pre=branch_regs[i].dirty;
9193 dirty_pre=regs[i].dirty;
9197 if (i < 2 || !dops[i-2].is_ujump)
9199 wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,unneeded_reg[i]);
9200 loop_preload(regmap_pre[i],regs[i].regmap_entry);
9202 // branch target entry point
9203 instr_addr[i] = out;
9204 assem_debug("<->\n");
9205 drc_dbg_emit_do_cmp(i, ccadj[i]);
9208 if(regs[i].regmap_entry[HOST_CCREG]==CCREG&®s[i].regmap[HOST_CCREG]!=CCREG)
9209 wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty);
9210 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i].rs1,dops[i].rs2);
9211 address_generation(i,®s[i],regs[i].regmap_entry);
9212 load_consts(regmap_pre[i],regs[i].regmap,i);
9215 // Load the delay slot registers if necessary
9216 if(dops[i+1].rs1!=dops[i].rs1&&dops[i+1].rs1!=dops[i].rs2&&(dops[i+1].rs1!=dops[i].rt1||dops[i].rt1==0))
9217 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs1,dops[i+1].rs1);
9218 if(dops[i+1].rs2!=dops[i+1].rs1&&dops[i+1].rs2!=dops[i].rs1&&dops[i+1].rs2!=dops[i].rs2&&(dops[i+1].rs2!=dops[i].rt1||dops[i].rt1==0))
9219 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2);
9220 if (ram_offset && (dops[i+1].is_load || dops[i+1].is_store))
9221 load_regs(regs[i].regmap_entry,regs[i].regmap,ROREG,ROREG);
9222 if (dops[i+1].is_store)
9223 load_regs(regs[i].regmap_entry,regs[i].regmap,INVCP,INVCP);
9227 // Preload registers for following instruction
9228 if(dops[i+1].rs1!=dops[i].rs1&&dops[i+1].rs1!=dops[i].rs2)
9229 if(dops[i+1].rs1!=dops[i].rt1&&dops[i+1].rs1!=dops[i].rt2)
9230 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs1,dops[i+1].rs1);
9231 if(dops[i+1].rs2!=dops[i+1].rs1&&dops[i+1].rs2!=dops[i].rs1&&dops[i+1].rs2!=dops[i].rs2)
9232 if(dops[i+1].rs2!=dops[i].rt1&&dops[i+1].rs2!=dops[i].rt2)
9233 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2);
9235 // TODO: if(is_ooo(i)) address_generation(i+1);
9236 if (!dops[i].is_jump || dops[i].itype == CJUMP)
9237 load_regs(regs[i].regmap_entry,regs[i].regmap,CCREG,CCREG);
9238 if (ram_offset && (dops[i].is_load || dops[i].is_store))
9239 load_regs(regs[i].regmap_entry,regs[i].regmap,ROREG,ROREG);
9240 if (dops[i].is_store)
9241 load_regs(regs[i].regmap_entry,regs[i].regmap,INVCP,INVCP);
9243 ds = assemble(i, ®s[i], ccadj[i]);
9245 if (dops[i].is_ujump)
9248 literal_pool_jumpover(256);
9253 if (slen > 0 && dops[slen-1].itype == INTCALL) {
9254 // no ending needed for this block since INTCALL never returns
9256 // If the block did not end with an unconditional branch,
9257 // add a jump to the next instruction.
9259 if (!dops[i-2].is_ujump && dops[i-1].itype != SPAN) {
9260 assert(!dops[i-1].is_jump);
9262 if(dops[i-2].itype!=CJUMP&&dops[i-2].itype!=SJUMP) {
9263 store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4);
9264 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
9265 emit_loadreg(CCREG,HOST_CCREG);
9266 emit_addimm(HOST_CCREG, ccadj[i-1] + CLOCK_ADJUST(1), HOST_CCREG);
9270 store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].dirty,start+i*4);
9271 assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
9273 add_to_linker(out,start+i*4,0);
9280 assert(!dops[i-1].is_jump);
9281 store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4);
9282 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
9283 emit_loadreg(CCREG,HOST_CCREG);
9284 emit_addimm(HOST_CCREG, ccadj[i-1] + CLOCK_ADJUST(1), HOST_CCREG);
9285 add_to_linker(out,start+i*4,0);
9289 // TODO: delay slot stubs?
9291 for(i=0;i<stubcount;i++)
9293 switch(stubs[i].type)
9301 do_readstub(i);break;
9306 do_writestub(i);break;
9310 do_invstub(i);break;
9312 do_cop1stub(i);break;
9314 do_unalignedwritestub(i);break;
9318 if (instr_addr0_override)
9319 instr_addr[0] = instr_addr0_override;
9321 /* Pass 9 - Linker */
9322 for(i=0;i<linkcount;i++)
9324 assem_debug("%p -> %8x\n",link_addr[i].addr,link_addr[i].target);
9326 if (!link_addr[i].ext)
9329 void *addr = check_addr(link_addr[i].target);
9330 emit_extjump(link_addr[i].addr, link_addr[i].target);
9332 set_jump_target(link_addr[i].addr, addr);
9333 add_jump_out(link_addr[i].target,stub);
9336 set_jump_target(link_addr[i].addr, stub);
9341 int target=(link_addr[i].target-start)>>2;
9342 assert(target>=0&&target<slen);
9343 assert(instr_addr[target]);
9344 //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
9345 //set_jump_target_fillslot(link_addr[i].addr,instr_addr[target],link_addr[i].ext>>1);
9347 set_jump_target(link_addr[i].addr, instr_addr[target]);
9352 u_int source_len = slen*4;
9353 if (dops[slen-1].itype == INTCALL && source_len > 4)
9354 // no need to treat the last instruction as compiled
9355 // as interpreter fully handles it
9358 if ((u_char *)copy + source_len > (u_char *)shadow + sizeof(shadow))
9361 // External Branch Targets (jump_in)
9364 if(dops[i].bt||i==0)
9366 if(instr_addr[i]) // TODO - delay slots (=null)
9368 u_int vaddr=start+i*4;
9369 u_int page=get_page(vaddr);
9370 u_int vpage=get_vpage(vaddr);
9373 assem_debug("%p (%d) <- %8x\n",instr_addr[i],i,start+i*4);
9374 assem_debug("jump_in: %x\n",start+i*4);
9375 ll_add(jump_dirty+vpage,vaddr,out);
9376 void *entry_point = do_dirty_stub(i, source_len);
9377 ll_add_flags(jump_in+page,vaddr,state_rflags,entry_point);
9378 // If there was an existing entry in the hash table,
9379 // replace it with the new address.
9380 // Don't add new entries. We'll insert the
9381 // ones that actually get used in check_addr().
9382 struct ht_entry *ht_bin = hash_table_get(vaddr);
9383 if (ht_bin->vaddr[0] == vaddr)
9384 ht_bin->tcaddr[0] = entry_point;
9385 if (ht_bin->vaddr[1] == vaddr)
9386 ht_bin->tcaddr[1] = entry_point;
9391 // Write out the literal pool if necessary
9393 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
9395 if(((u_int)out)&7) emit_addnop(13);
9397 assert(out - (u_char *)beginning < MAX_OUTPUT_BLOCK_SIZE);
9398 //printf("shadow buffer: %p-%p\n",copy,(u_char *)copy+slen*4);
9399 memcpy(copy, source, source_len);
9402 end_block(beginning);
9404 // If we're within 256K of the end of the buffer,
9405 // start over from the beginning. (Is 256K enough?)
9406 if (out > ndrc->translation_cache + sizeof(ndrc->translation_cache) - MAX_OUTPUT_BLOCK_SIZE)
9407 out = ndrc->translation_cache;
9409 // Trap writes to any of the pages we compiled
9410 for(i=start>>12;i<=(start+slen*4)>>12;i++) {
9413 inv_code_start=inv_code_end=~0;
9415 // for PCSX we need to mark all mirrors too
9416 if(get_page(start)<(RAM_SIZE>>12))
9417 for(i=start>>12;i<=(start+slen*4)>>12;i++)
9418 invalid_code[((u_int)0x00000000>>12)|(i&0x1ff)]=
9419 invalid_code[((u_int)0x80000000>>12)|(i&0x1ff)]=
9420 invalid_code[((u_int)0xa0000000>>12)|(i&0x1ff)]=0;
9422 /* Pass 10 - Free memory by expiring oldest blocks */
9424 int end=(((out-ndrc->translation_cache)>>(TARGET_SIZE_2-16))+16384)&65535;
9427 int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
9428 uintptr_t base_offs = ((uintptr_t)(expirep >> 13) << shift); // Base offset of this block
9429 uintptr_t base_offs_s = base_offs >> shift;
9430 inv_debug("EXP: Phase %d\n",expirep);
9431 switch((expirep>>11)&3)
9434 // Clear jump_in and jump_dirty
9435 ll_remove_matching_addrs(jump_in+(expirep&2047),base_offs_s,shift);
9436 ll_remove_matching_addrs(jump_dirty+(expirep&2047),base_offs_s,shift);
9437 ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base_offs_s,shift);
9438 ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base_offs_s,shift);
9442 ll_kill_pointers(jump_out[expirep&2047],base_offs_s,shift);
9443 ll_kill_pointers(jump_out[(expirep&2047)+2048],base_offs_s,shift);
9448 struct ht_entry *ht_bin = &hash_table[((expirep&2047)<<5)+i];
9449 uintptr_t o1 = (u_char *)ht_bin->tcaddr[1] - ndrc->translation_cache;
9450 uintptr_t o2 = o1 - MAX_OUTPUT_BLOCK_SIZE;
9451 if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s) {
9452 inv_debug("EXP: Remove hash %x -> %p\n",ht_bin->vaddr[1],ht_bin->tcaddr[1]);
9453 ht_bin->vaddr[1] = -1;
9454 ht_bin->tcaddr[1] = NULL;
9456 o1 = (u_char *)ht_bin->tcaddr[0] - ndrc->translation_cache;
9457 o2 = o1 - MAX_OUTPUT_BLOCK_SIZE;
9458 if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s) {
9459 inv_debug("EXP: Remove hash %x -> %p\n",ht_bin->vaddr[0],ht_bin->tcaddr[0]);
9460 ht_bin->vaddr[0] = ht_bin->vaddr[1];
9461 ht_bin->tcaddr[0] = ht_bin->tcaddr[1];
9462 ht_bin->vaddr[1] = -1;
9463 ht_bin->tcaddr[1] = NULL;
9469 if((expirep&2047)==0)
9471 ll_remove_matching_addrs(jump_out+(expirep&2047),base_offs_s,shift);
9472 ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base_offs_s,shift);
9475 expirep=(expirep+1)&65535;
9483 // vim:shiftwidth=2:expandtab