1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
3 * Copyright (C) 2009-2010 Ari64 *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
22 #include <stdint.h> //include for uint64_t
25 #include "emu_if.h" //emulator interface
30 #include "assem_x86.h"
33 #include "assem_x64.h"
36 #include "assem_arm.h"
40 #define MAX_OUTPUT_BLOCK_SIZE 262144
41 #define CLOCK_DIVIDER 2
45 signed char regmap_entry[HOST_REGS];
46 signed char regmap[HOST_REGS];
55 uint64_t constmap[HOST_REGS];
63 struct ll_entry *next;
69 char insn[MAXBLOCK][10];
70 u_char itype[MAXBLOCK];
71 u_char opcode[MAXBLOCK];
72 u_char opcode2[MAXBLOCK];
80 u_char dep1[MAXBLOCK];
81 u_char dep2[MAXBLOCK];
85 char likely[MAXBLOCK];
87 uint64_t unneeded_reg[MAXBLOCK];
88 uint64_t unneeded_reg_upper[MAXBLOCK];
89 uint64_t branch_unneeded_reg[MAXBLOCK];
90 uint64_t branch_unneeded_reg_upper[MAXBLOCK];
91 uint64_t p32[MAXBLOCK];
92 uint64_t pr32[MAXBLOCK];
93 signed char regmap_pre[MAXBLOCK][HOST_REGS];
94 signed char regmap[MAXBLOCK][HOST_REGS];
95 signed char regmap_entry[MAXBLOCK][HOST_REGS];
96 uint64_t constmap[MAXBLOCK][HOST_REGS];
97 uint64_t known_value[HOST_REGS];
99 struct regstat regs[MAXBLOCK];
100 struct regstat branch_regs[MAXBLOCK];
101 u_int needed_reg[MAXBLOCK];
102 uint64_t requires_32bit[MAXBLOCK];
103 u_int wont_dirty[MAXBLOCK];
104 u_int will_dirty[MAXBLOCK];
107 u_int instr_addr[MAXBLOCK];
108 u_int link_addr[MAXBLOCK][3];
110 u_int stubs[MAXBLOCK*3][8];
112 u_int literals[1024][2];
117 struct ll_entry *jump_in[4096];
118 struct ll_entry *jump_out[4096];
119 struct ll_entry *jump_dirty[4096];
120 u_int hash_table[65536][4] __attribute__((aligned(16)));
121 char shadow[1048576] __attribute__((aligned(16)));
125 u_int stop_after_jal;
126 extern u_char restore_candidate[512];
127 extern int cycle_count;
129 /* registers that may be allocated */
131 #define HIREG 32 // hi
132 #define LOREG 33 // lo
133 #define FSREG 34 // FPU status (FCSR)
134 #define CSREG 35 // Coprocessor status
135 #define CCREG 36 // Cycle count
136 #define INVCP 37 // Pointer to invalid_code
138 #define FTEMP 38 // FPU/LDL/LDR temporary register
139 #define PTEMP 39 // Prefetch temporary register
140 #define TLREG 40 // TLB mapping offset
141 #define RHASH 41 // Return address hash
142 #define RHTBL 42 // Return address hash table address
143 #define RTEMP 43 // JR/JALR address register
145 #define AGEN1 44 // Address generation temporary register
146 #define AGEN2 45 // Address generation temporary register
147 #define MGEN1 46 // Maptable address generation temporary register
148 #define MGEN2 47 // Maptable address generation temporary register
149 #define BTREG 48 // Branch target temporary register
151 /* instruction types */
152 #define NOP 0 // No operation
153 #define LOAD 1 // Load
154 #define STORE 2 // Store
155 #define LOADLR 3 // Unaligned load
156 #define STORELR 4 // Unaligned store
157 #define MOV 5 // Move
158 #define ALU 6 // Arithmetic/logic
159 #define MULTDIV 7 // Multiply/divide
160 #define SHIFT 8 // Shift by register
161 #define SHIFTIMM 9// Shift by immediate
162 #define IMM16 10 // 16-bit immediate
163 #define RJUMP 11 // Unconditional jump to register
164 #define UJUMP 12 // Unconditional jump
165 #define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
166 #define SJUMP 14 // Conditional branch (regimm format)
167 #define COP0 15 // Coprocessor 0
168 #define COP1 16 // Coprocessor 1
169 #define C1LS 17 // Coprocessor 1 load/store
170 #define FJUMP 18 // Conditional branch (floating point)
171 #define FLOAT 19 // Floating point unit
172 #define FCONV 20 // Convert integer to float
173 #define FCOMP 21 // Floating point compare (sets FSREG)
174 #define SYSCALL 22// SYSCALL
175 #define OTHER 23 // Other
176 #define SPAN 24 // Branch/delay slot spans 2 pages
177 #define NI 25 // Not implemented
178 #define HLECALL 26// PCSX fake opcodes for HLE
179 #define COP2 27 // Coprocessor 2 move
180 #define C2LS 28 // Coprocessor 2 load/store
181 #define C2OP 29 // Coprocessor 2 operation
190 #define LOADBU_STUB 7
191 #define LOADHU_STUB 8
192 #define STOREB_STUB 9
193 #define STOREH_STUB 10
194 #define STOREW_STUB 11
195 #define STORED_STUB 12
196 #define STORELR_STUB 13
197 #define INVCODE_STUB 14
205 int new_recompile_block(int addr);
206 void *get_addr_ht(u_int vaddr);
207 void invalidate_block(u_int block);
208 void invalidate_addr(u_int addr);
209 void remove_hash(int vaddr);
212 void dyna_linker_ds();
214 void verify_code_vm();
215 void verify_code_ds();
218 void fp_exception_ds();
220 void jump_syscall_hle();
223 void new_dyna_leave();
228 void read_nomem_new();
229 void read_nomemb_new();
230 void read_nomemh_new();
231 void read_nomemd_new();
232 void write_nomem_new();
233 void write_nomemb_new();
234 void write_nomemh_new();
235 void write_nomemd_new();
236 void write_rdram_new();
237 void write_rdramb_new();
238 void write_rdramh_new();
239 void write_rdramd_new();
240 extern u_int memory_map[1048576];
242 // Needed by assembler
243 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
244 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
245 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
246 void load_all_regs(signed char i_regmap[]);
247 void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
248 void load_regs_entry(int t);
249 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
253 //#define DEBUG_CYCLE_COUNT 1
256 //#define assem_debug printf
257 //#define inv_debug printf
258 #define assem_debug nullf
259 #define inv_debug nullf
261 static void tlb_hacks()
265 if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
269 switch (ROM_HEADER->Country_code&0xFF)
281 // Unknown country code
285 u_int rom_addr=(u_int)rom;
287 // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
288 // in the lower 4G of memory to use this hack. Copy it if necessary.
289 if((void *)rom>(void *)0xffffffff) {
290 munmap(ROM_COPY, 67108864);
291 if(mmap(ROM_COPY, 12582912,
292 PROT_READ | PROT_WRITE,
293 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
294 -1, 0) <= 0) {printf("mmap() failed\n");}
295 memcpy(ROM_COPY,rom,12582912);
296 rom_addr=(u_int)ROM_COPY;
300 for(n=0x7F000;n<0x80000;n++) {
301 memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
308 static u_int get_page(u_int vaddr)
310 u_int page=(vaddr^0x80000000)>>12;
312 if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
314 if(page>2048) page=2048+(page&2047);
318 static u_int get_vpage(u_int vaddr)
320 u_int vpage=(vaddr^0x80000000)>>12;
322 if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
324 if(vpage>2048) vpage=2048+(vpage&2047);
328 // Get address from virtual address
329 // This is called from the recompiled JR/JALR instructions
330 void *get_addr(u_int vaddr)
332 u_int page=get_page(vaddr);
333 u_int vpage=get_vpage(vaddr);
334 struct ll_entry *head;
335 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
338 if(head->vaddr==vaddr&&head->reg32==0) {
339 //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
340 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
343 ht_bin[1]=(int)head->addr;
349 head=jump_dirty[vpage];
351 if(head->vaddr==vaddr&&head->reg32==0) {
352 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
353 // Don't restore blocks which are about to expire from the cache
354 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
355 if(verify_dirty(head->addr)) {
356 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
357 invalid_code[vaddr>>12]=0;
358 memory_map[vaddr>>12]|=0x40000000;
361 if(tlb_LUT_r[vaddr>>12]) {
362 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
363 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
366 restore_candidate[vpage>>3]|=1<<(vpage&7);
368 else restore_candidate[page>>3]|=1<<(page&7);
369 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
370 if(ht_bin[0]==vaddr) {
371 ht_bin[1]=(int)head->addr; // Replace existing entry
377 ht_bin[1]=(int)head->addr;
385 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
386 int r=new_recompile_block(vaddr);
387 if(r==0) return get_addr(vaddr);
388 // Execute in unmapped page, generate pagefault execption
390 Cause=(vaddr<<31)|0x8;
391 EPC=(vaddr&1)?vaddr-5:vaddr;
393 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
394 EntryHi=BadVAddr&0xFFFFE000;
395 return get_addr_ht(0x80000000);
397 // Look up address in hash table first
398 void *get_addr_ht(u_int vaddr)
400 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
401 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
402 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
403 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
404 return get_addr(vaddr);
407 void *get_addr_32(u_int vaddr,u_int flags)
410 return get_addr(vaddr);
412 //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
413 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
414 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
415 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
416 u_int page=get_page(vaddr);
417 u_int vpage=get_vpage(vaddr);
418 struct ll_entry *head;
421 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
422 //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
424 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
426 ht_bin[1]=(int)head->addr;
428 }else if(ht_bin[2]==-1) {
429 ht_bin[3]=(int)head->addr;
432 //ht_bin[3]=ht_bin[1];
433 //ht_bin[2]=ht_bin[0];
434 //ht_bin[1]=(int)head->addr;
441 head=jump_dirty[vpage];
443 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
444 //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
445 // Don't restore blocks which are about to expire from the cache
446 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
447 if(verify_dirty(head->addr)) {
448 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
449 invalid_code[vaddr>>12]=0;
450 memory_map[vaddr>>12]|=0x40000000;
453 if(tlb_LUT_r[vaddr>>12]) {
454 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
455 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
458 restore_candidate[vpage>>3]|=1<<(vpage&7);
460 else restore_candidate[page>>3]|=1<<(page&7);
462 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
464 ht_bin[1]=(int)head->addr;
466 }else if(ht_bin[2]==-1) {
467 ht_bin[3]=(int)head->addr;
470 //ht_bin[3]=ht_bin[1];
471 //ht_bin[2]=ht_bin[0];
472 //ht_bin[1]=(int)head->addr;
480 //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
481 int r=new_recompile_block(vaddr);
482 if(r==0) return get_addr(vaddr);
483 // Execute in unmapped page, generate pagefault execption
485 Cause=(vaddr<<31)|0x8;
486 EPC=(vaddr&1)?vaddr-5:vaddr;
488 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
489 EntryHi=BadVAddr&0xFFFFE000;
490 return get_addr_ht(0x80000000);
494 void clear_all_regs(signed char regmap[])
497 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
500 signed char get_reg(signed char regmap[],int r)
503 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map[hr]==r) return hr;
507 // Find a register that is available for two consecutive cycles
508 signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
511 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map1[hr]==r&®map2[hr]==r) return hr;
515 int count_free_regs(signed char regmap[])
519 for(hr=0;hr<HOST_REGS;hr++)
521 if(hr!=EXCLUDE_REG) {
522 if(regmap[hr]<0) count++;
528 void dirty_reg(struct regstat *cur,signed char reg)
532 for (hr=0;hr<HOST_REGS;hr++) {
533 if((cur->regmap[hr]&63)==reg) {
539 // If we dirty the lower half of a 64 bit register which is now being
540 // sign-extended, we need to dump the upper half.
541 // Note: Do this only after completion of the instruction, because
542 // some instructions may need to read the full 64-bit value even if
543 // overwriting it (eg SLTI, DSRA32).
544 static void flush_dirty_uppers(struct regstat *cur)
547 for (hr=0;hr<HOST_REGS;hr++) {
548 if((cur->dirty>>hr)&1) {
551 if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
556 void set_const(struct regstat *cur,signed char reg,uint64_t value)
560 for (hr=0;hr<HOST_REGS;hr++) {
561 if(cur->regmap[hr]==reg) {
563 cur->constmap[hr]=value;
565 else if((cur->regmap[hr]^64)==reg) {
567 cur->constmap[hr]=value>>32;
572 void clear_const(struct regstat *cur,signed char reg)
576 for (hr=0;hr<HOST_REGS;hr++) {
577 if((cur->regmap[hr]&63)==reg) {
578 cur->isconst&=~(1<<hr);
583 int is_const(struct regstat *cur,signed char reg)
587 for (hr=0;hr<HOST_REGS;hr++) {
588 if((cur->regmap[hr]&63)==reg) {
589 return (cur->isconst>>hr)&1;
594 uint64_t get_const(struct regstat *cur,signed char reg)
598 for (hr=0;hr<HOST_REGS;hr++) {
599 if(cur->regmap[hr]==reg) {
600 return cur->constmap[hr];
603 printf("Unknown constant in r%d\n",reg);
607 // Least soon needed registers
608 // Look at the next ten instructions and see which registers
609 // will be used. Try not to reallocate these.
610 void lsn(u_char hsn[], int i, int *preferred_reg)
620 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
622 // Don't go past an unconditonal jump
629 if(rs1[i+j]) hsn[rs1[i+j]]=j;
630 if(rs2[i+j]) hsn[rs2[i+j]]=j;
631 if(rt1[i+j]) hsn[rt1[i+j]]=j;
632 if(rt2[i+j]) hsn[rt2[i+j]]=j;
633 if(itype[i+j]==STORE || itype[i+j]==STORELR) {
634 // Stores can allocate zero
638 // On some architectures stores need invc_ptr
639 #if defined(HOST_IMM8)
640 if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
644 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
652 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
654 // Follow first branch
655 int t=(ba[i+b]-start)>>2;
656 j=7-b;if(t+j>=slen) j=slen-t-1;
659 if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
660 if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
661 //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
662 //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
665 // TODO: preferred register based on backward branch
667 // Delay slot should preferably not overwrite branch conditions or cycle count
668 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
669 if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
670 if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
676 // Coprocessor load/store needs FTEMP, even if not declared
677 if(itype[i]==C1LS||itype[i]==C2LS) {
680 // Load L/R also uses FTEMP as a temporary register
681 if(itype[i]==LOADLR) {
684 // Also SWL/SWR/SDL/SDR
685 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
688 // Don't remove the TLB registers either
689 if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
692 // Don't remove the miniht registers
693 if(itype[i]==UJUMP||itype[i]==RJUMP)
700 // We only want to allocate registers if we're going to use them again soon
701 int needed_again(int r, int i)
707 u_char hsn[MAXREG+1];
710 memset(hsn,10,sizeof(hsn));
711 lsn(hsn,i,&preferred_reg);
713 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
715 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
716 return 0; // Don't need any registers if exiting the block
724 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
726 // Don't go past an unconditonal jump
730 if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||((source[i+j]&0xfc00003f)==0x0d))
737 if(rs1[i+j]==r) rn=j;
738 if(rs2[i+j]==r) rn=j;
739 if((unneeded_reg[i+j]>>r)&1) rn=10;
740 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
748 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
750 // Follow first branch
752 int t=(ba[i+b]-start)>>2;
753 j=7-b;if(t+j>=slen) j=slen-t-1;
756 if(!((unneeded_reg[t+j]>>r)&1)) {
757 if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
758 if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
764 for(hr=0;hr<HOST_REGS;hr++) {
765 if(hr!=EXCLUDE_REG) {
766 if(rn<hsn[hr]) return 1;
772 // Try to match register allocations at the end of a loop with those
774 int loop_reg(int i, int r, int hr)
783 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
785 // Don't go past an unconditonal jump
792 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
797 if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
798 if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
799 if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
801 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
803 int t=(ba[i+k]-start)>>2;
804 int reg=get_reg(regs[t].regmap_entry,r);
805 if(reg>=0) return reg;
806 //reg=get_reg(regs[t+1].regmap_entry,r);
807 //if(reg>=0) return reg;
815 // Allocate every register, preserving source/target regs
816 void alloc_all(struct regstat *cur,int i)
820 for(hr=0;hr<HOST_REGS;hr++) {
821 if(hr!=EXCLUDE_REG) {
822 if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
823 ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
826 cur->dirty&=~(1<<hr);
829 if((cur->regmap[hr]&63)==0)
832 cur->dirty&=~(1<<hr);
839 void div64(int64_t dividend,int64_t divisor)
843 //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
844 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
846 void divu64(uint64_t dividend,uint64_t divisor)
850 //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
851 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
854 void mult64(uint64_t m1,uint64_t m2)
856 unsigned long long int op1, op2, op3, op4;
857 unsigned long long int result1, result2, result3, result4;
858 unsigned long long int temp1, temp2, temp3, temp4;
874 op1 = op2 & 0xFFFFFFFF;
875 op2 = (op2 >> 32) & 0xFFFFFFFF;
876 op3 = op4 & 0xFFFFFFFF;
877 op4 = (op4 >> 32) & 0xFFFFFFFF;
880 temp2 = (temp1 >> 32) + op1 * op4;
882 temp4 = (temp3 >> 32) + op2 * op4;
884 result1 = temp1 & 0xFFFFFFFF;
885 result2 = temp2 + (temp3 & 0xFFFFFFFF);
886 result3 = (result2 >> 32) + temp4;
887 result4 = (result3 >> 32);
889 lo = result1 | (result2 << 32);
890 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
899 void multu64(uint64_t m1,uint64_t m2)
901 unsigned long long int op1, op2, op3, op4;
902 unsigned long long int result1, result2, result3, result4;
903 unsigned long long int temp1, temp2, temp3, temp4;
905 op1 = m1 & 0xFFFFFFFF;
906 op2 = (m1 >> 32) & 0xFFFFFFFF;
907 op3 = m2 & 0xFFFFFFFF;
908 op4 = (m2 >> 32) & 0xFFFFFFFF;
911 temp2 = (temp1 >> 32) + op1 * op4;
913 temp4 = (temp3 >> 32) + op2 * op4;
915 result1 = temp1 & 0xFFFFFFFF;
916 result2 = temp2 + (temp3 & 0xFFFFFFFF);
917 result3 = (result2 >> 32) + temp4;
918 result4 = (result3 >> 32);
920 lo = result1 | (result2 << 32);
921 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
923 //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
924 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
927 uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
935 else original=loaded;
938 uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
941 original>>=64-(bits^56);
942 original<<=64-(bits^56);
946 else original=loaded;
951 #include "assem_x86.c"
954 #include "assem_x64.c"
957 #include "assem_arm.c"
960 // Add virtual address mapping to linked list
961 void ll_add(struct ll_entry **head,int vaddr,void *addr)
963 struct ll_entry *new_entry;
964 new_entry=malloc(sizeof(struct ll_entry));
965 assert(new_entry!=NULL);
966 new_entry->vaddr=vaddr;
968 new_entry->addr=addr;
969 new_entry->next=*head;
973 // Add virtual address mapping for 32-bit compiled block
974 void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
976 ll_add(head,vaddr,addr);
978 (*head)->reg32=reg32;
982 // Check if an address is already compiled
983 // but don't return addresses which are about to expire from the cache
984 void *check_addr(u_int vaddr)
986 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
987 if(ht_bin[0]==vaddr) {
988 if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
989 if(isclean(ht_bin[1])) return (void *)ht_bin[1];
991 if(ht_bin[2]==vaddr) {
992 if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
993 if(isclean(ht_bin[3])) return (void *)ht_bin[3];
995 u_int page=get_page(vaddr);
996 struct ll_entry *head;
999 if(head->vaddr==vaddr&&head->reg32==0) {
1000 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1001 // Update existing entry with current address
1002 if(ht_bin[0]==vaddr) {
1003 ht_bin[1]=(int)head->addr;
1006 if(ht_bin[2]==vaddr) {
1007 ht_bin[3]=(int)head->addr;
1010 // Insert into hash table with low priority.
1011 // Don't evict existing entries, as they are probably
1012 // addresses that are being accessed frequently.
1014 ht_bin[1]=(int)head->addr;
1016 }else if(ht_bin[2]==-1) {
1017 ht_bin[3]=(int)head->addr;
1028 void remove_hash(int vaddr)
1030 //printf("remove hash: %x\n",vaddr);
1031 int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1032 if(ht_bin[2]==vaddr) {
1033 ht_bin[2]=ht_bin[3]=-1;
1035 if(ht_bin[0]==vaddr) {
1036 ht_bin[0]=ht_bin[2];
1037 ht_bin[1]=ht_bin[3];
1038 ht_bin[2]=ht_bin[3]=-1;
1042 void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1044 struct ll_entry *next;
1046 if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1047 ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1049 inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1050 remove_hash((*head)->vaddr);
1057 head=&((*head)->next);
1062 // Remove all entries from linked list
1063 void ll_clear(struct ll_entry **head)
1065 struct ll_entry *cur;
1066 struct ll_entry *next;
1077 // Dereference the pointers and remove if it matches
1078 void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1080 u_int old_host_addr=0;
1082 int ptr=get_pointer(head->addr);
1083 inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1084 if(((ptr>>shift)==(addr>>shift)) ||
1085 (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1087 printf("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1088 u_int host_addr=(u_int)kill_pointer(head->addr);
1090 if((host_addr>>12)!=(old_host_addr>>12)) {
1092 __clear_cache((void *)(old_host_addr&~0xfff),(void *)(old_host_addr|0xfff));
1094 old_host_addr=host_addr;
1101 __clear_cache((void *)(old_host_addr&~0xfff),(void *)(old_host_addr|0xfff));
1105 // This is called when we write to a compiled block (see do_invstub)
1106 void invalidate_page(u_int page)
1108 struct ll_entry *head;
1109 struct ll_entry *next;
1110 u_int old_host_addr=0;
1114 inv_debug("INVALIDATE: %x\n",head->vaddr);
1115 remove_hash(head->vaddr);
1120 head=jump_out[page];
1123 inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
1124 u_int host_addr=(u_int)kill_pointer(head->addr);
1126 if((host_addr>>12)!=(old_host_addr>>12)) {
1128 __clear_cache((void *)(old_host_addr&~0xfff),(void *)(old_host_addr|0xfff));
1130 old_host_addr=host_addr;
1138 __clear_cache((void *)(old_host_addr&~0xfff),(void *)(old_host_addr|0xfff));
1141 void invalidate_block(u_int block)
1143 u_int page=get_page(block<<12);
1144 u_int vpage=get_vpage(block<<12);
1145 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1146 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1149 struct ll_entry *head;
1150 head=jump_dirty[vpage];
1151 //printf("page=%d vpage=%d\n",page,vpage);
1154 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1155 get_bounds((int)head->addr,&start,&end);
1156 //printf("start: %x end: %x\n",start,end);
1157 if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) {
1158 if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1159 if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1160 if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1164 if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1165 if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1166 if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1167 if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1174 //printf("first=%d last=%d\n",first,last);
1175 invalidate_page(page);
1176 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1177 assert(last<page+5);
1178 // Invalidate the adjacent pages if a block crosses a 4K boundary
1180 invalidate_page(first);
1183 for(first=page+1;first<last;first++) {
1184 invalidate_page(first);
1187 // Don't trap writes
1188 invalid_code[block]=1;
1190 // If there is a valid TLB entry for this page, remove write protect
1191 if(tlb_LUT_w[block]) {
1192 assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1193 // CHECK: Is this right?
1194 memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1195 u_int real_block=tlb_LUT_w[block]>>12;
1196 invalid_code[real_block]=1;
1197 if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1199 else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
1203 memset(mini_ht,-1,sizeof(mini_ht));
1206 void invalidate_addr(u_int addr)
1208 invalidate_block(addr>>12);
1210 void invalidate_all_pages()
1213 for(page=0;page<4096;page++)
1214 invalidate_page(page);
1215 for(page=0;page<1048576;page++)
1216 if(!invalid_code[page]) {
1217 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1218 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1221 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1224 memset(mini_ht,-1,sizeof(mini_ht));
1228 for(page=0;page<0x100000;page++) {
1229 if(tlb_LUT_r[page]) {
1230 memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1231 if(!tlb_LUT_w[page]||!invalid_code[page])
1232 memory_map[page]|=0x40000000; // Write protect
1234 else memory_map[page]=-1;
1235 if(page==0x80000) page=0xC0000;
1241 // Add an entry to jump_out after making a link
1242 void add_link(u_int vaddr,void *src)
1244 u_int page=get_page(vaddr);
1245 inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1246 ll_add(jump_out+page,vaddr,src);
1247 //int ptr=get_pointer(src);
1248 //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1251 // If a code block was found to be unmodified (bit was set in
1252 // restore_candidate) and it remains unmodified (bit is clear
1253 // in invalid_code) then move the entries for that 4K page from
1254 // the dirty list to the clean list.
1255 void clean_blocks(u_int page)
1257 struct ll_entry *head;
1258 inv_debug("INV: clean_blocks page=%d\n",page);
1259 head=jump_dirty[page];
1261 if(!invalid_code[head->vaddr>>12]) {
1262 // Don't restore blocks which are about to expire from the cache
1263 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1265 if(verify_dirty((int)head->addr)) {
1266 //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1269 get_bounds((int)head->addr,&start,&end);
1270 if(start-(u_int)rdram<RAM_SIZE) {
1271 for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1272 inv|=invalid_code[i];
1275 if((signed int)head->vaddr>=(signed int)0xC0000000) {
1276 u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1277 //printf("addr=%x start=%x end=%x\n",addr,start,end);
1278 if(addr<start||addr>=end) inv=1;
1280 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
1284 void * clean_addr=(void *)get_clean_addr((int)head->addr);
1285 if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1288 if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
1290 inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1291 //printf("page=%x, addr=%x\n",page,head->vaddr);
1292 //assert(head->vaddr>>12==(page|0x80000));
1293 ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1294 int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1296 if(ht_bin[0]==head->vaddr) {
1297 ht_bin[1]=(int)clean_addr; // Replace existing entry
1299 if(ht_bin[2]==head->vaddr) {
1300 ht_bin[3]=(int)clean_addr; // Replace existing entry
1313 void mov_alloc(struct regstat *current,int i)
1315 // Note: Don't need to actually alloc the source registers
1316 if((~current->is32>>rs1[i])&1) {
1317 //alloc_reg64(current,i,rs1[i]);
1318 alloc_reg64(current,i,rt1[i]);
1319 current->is32&=~(1LL<<rt1[i]);
1321 //alloc_reg(current,i,rs1[i]);
1322 alloc_reg(current,i,rt1[i]);
1323 current->is32|=(1LL<<rt1[i]);
1325 clear_const(current,rs1[i]);
1326 clear_const(current,rt1[i]);
1327 dirty_reg(current,rt1[i]);
1330 void shiftimm_alloc(struct regstat *current,int i)
1332 clear_const(current,rs1[i]);
1333 clear_const(current,rt1[i]);
1334 if(opcode2[i]<=0x3) // SLL/SRL/SRA
1337 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1339 alloc_reg(current,i,rt1[i]);
1340 current->is32|=1LL<<rt1[i];
1341 dirty_reg(current,rt1[i]);
1344 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1347 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1348 alloc_reg64(current,i,rt1[i]);
1349 current->is32&=~(1LL<<rt1[i]);
1350 dirty_reg(current,rt1[i]);
1353 if(opcode2[i]==0x3c) // DSLL32
1356 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1357 alloc_reg64(current,i,rt1[i]);
1358 current->is32&=~(1LL<<rt1[i]);
1359 dirty_reg(current,rt1[i]);
1362 if(opcode2[i]==0x3e) // DSRL32
1365 alloc_reg64(current,i,rs1[i]);
1367 alloc_reg64(current,i,rt1[i]);
1368 current->is32&=~(1LL<<rt1[i]);
1370 alloc_reg(current,i,rt1[i]);
1371 current->is32|=1LL<<rt1[i];
1373 dirty_reg(current,rt1[i]);
1376 if(opcode2[i]==0x3f) // DSRA32
1379 alloc_reg64(current,i,rs1[i]);
1380 alloc_reg(current,i,rt1[i]);
1381 current->is32|=1LL<<rt1[i];
1382 dirty_reg(current,rt1[i]);
1387 void shift_alloc(struct regstat *current,int i)
1390 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1392 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1393 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1394 alloc_reg(current,i,rt1[i]);
1395 if(rt1[i]==rs2[i]) alloc_reg_temp(current,i,-1);
1396 current->is32|=1LL<<rt1[i];
1397 } else { // DSLLV/DSRLV/DSRAV
1398 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1399 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1400 alloc_reg64(current,i,rt1[i]);
1401 current->is32&=~(1LL<<rt1[i]);
1402 if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1403 alloc_reg_temp(current,i,-1);
1405 clear_const(current,rs1[i]);
1406 clear_const(current,rs2[i]);
1407 clear_const(current,rt1[i]);
1408 dirty_reg(current,rt1[i]);
1412 void alu_alloc(struct regstat *current,int i)
1414 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1416 if(rs1[i]&&rs2[i]) {
1417 alloc_reg(current,i,rs1[i]);
1418 alloc_reg(current,i,rs2[i]);
1421 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1422 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1424 alloc_reg(current,i,rt1[i]);
1426 current->is32|=1LL<<rt1[i];
1428 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1430 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1432 alloc_reg64(current,i,rs1[i]);
1433 alloc_reg64(current,i,rs2[i]);
1434 alloc_reg(current,i,rt1[i]);
1436 alloc_reg(current,i,rs1[i]);
1437 alloc_reg(current,i,rs2[i]);
1438 alloc_reg(current,i,rt1[i]);
1441 current->is32|=1LL<<rt1[i];
1443 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1445 if(rs1[i]&&rs2[i]) {
1446 alloc_reg(current,i,rs1[i]);
1447 alloc_reg(current,i,rs2[i]);
1451 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1452 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1454 alloc_reg(current,i,rt1[i]);
1455 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1457 if(!((current->uu>>rt1[i])&1)) {
1458 alloc_reg64(current,i,rt1[i]);
1460 if(get_reg(current->regmap,rt1[i]|64)>=0) {
1461 if(rs1[i]&&rs2[i]) {
1462 alloc_reg64(current,i,rs1[i]);
1463 alloc_reg64(current,i,rs2[i]);
1467 // Is is really worth it to keep 64-bit values in registers?
1469 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1470 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1474 current->is32&=~(1LL<<rt1[i]);
1476 current->is32|=1LL<<rt1[i];
1480 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1482 if(rs1[i]&&rs2[i]) {
1483 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1484 alloc_reg64(current,i,rs1[i]);
1485 alloc_reg64(current,i,rs2[i]);
1486 alloc_reg64(current,i,rt1[i]);
1488 alloc_reg(current,i,rs1[i]);
1489 alloc_reg(current,i,rs2[i]);
1490 alloc_reg(current,i,rt1[i]);
1494 alloc_reg(current,i,rt1[i]);
1495 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1496 // DADD used as move, or zeroing
1497 // If we have a 64-bit source, then make the target 64 bits too
1498 if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1499 if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1500 alloc_reg64(current,i,rt1[i]);
1501 } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1502 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1503 alloc_reg64(current,i,rt1[i]);
1505 if(opcode2[i]>=0x2e&&rs2[i]) {
1506 // DSUB used as negation - 64-bit result
1507 // If we have a 32-bit register, extend it to 64 bits
1508 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1509 alloc_reg64(current,i,rt1[i]);
1513 if(rs1[i]&&rs2[i]) {
1514 current->is32&=~(1LL<<rt1[i]);
1516 current->is32&=~(1LL<<rt1[i]);
1517 if((current->is32>>rs1[i])&1)
1518 current->is32|=1LL<<rt1[i];
1520 current->is32&=~(1LL<<rt1[i]);
1521 if((current->is32>>rs2[i])&1)
1522 current->is32|=1LL<<rt1[i];
1524 current->is32|=1LL<<rt1[i];
1528 clear_const(current,rs1[i]);
1529 clear_const(current,rs2[i]);
1530 clear_const(current,rt1[i]);
1531 dirty_reg(current,rt1[i]);
1534 void imm16_alloc(struct regstat *current,int i)
1536 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1538 if(rt1[i]) alloc_reg(current,i,rt1[i]);
1539 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1540 current->is32&=~(1LL<<rt1[i]);
1541 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1542 // TODO: Could preserve the 32-bit flag if the immediate is zero
1543 alloc_reg64(current,i,rt1[i]);
1544 alloc_reg64(current,i,rs1[i]);
1546 clear_const(current,rs1[i]);
1547 clear_const(current,rt1[i]);
1549 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1550 if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1551 current->is32|=1LL<<rt1[i];
1552 clear_const(current,rs1[i]);
1553 clear_const(current,rt1[i]);
1555 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1556 if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1557 if(rs1[i]!=rt1[i]) {
1558 if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1559 alloc_reg64(current,i,rt1[i]);
1560 current->is32&=~(1LL<<rt1[i]);
1563 else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1564 if(is_const(current,rs1[i])) {
1565 int v=get_const(current,rs1[i]);
1566 if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1567 if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1568 if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1570 else clear_const(current,rt1[i]);
1572 else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1573 if(is_const(current,rs1[i])) {
1574 int v=get_const(current,rs1[i]);
1575 set_const(current,rt1[i],v+imm[i]);
1577 else clear_const(current,rt1[i]);
1578 current->is32|=1LL<<rt1[i];
1581 set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1582 current->is32|=1LL<<rt1[i];
1584 dirty_reg(current,rt1[i]);
1587 void load_alloc(struct regstat *current,int i)
1589 clear_const(current,rt1[i]);
1590 //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1591 if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1592 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1594 alloc_reg(current,i,rt1[i]);
1595 if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1597 current->is32&=~(1LL<<rt1[i]);
1598 alloc_reg64(current,i,rt1[i]);
1600 else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1602 current->is32&=~(1LL<<rt1[i]);
1603 alloc_reg64(current,i,rt1[i]);
1604 alloc_all(current,i);
1605 alloc_reg64(current,i,FTEMP);
1607 else current->is32|=1LL<<rt1[i];
1608 dirty_reg(current,rt1[i]);
1609 // If using TLB, need a register for pointer to the mapping table
1610 if(using_tlb) alloc_reg(current,i,TLREG);
1611 // LWL/LWR need a temporary register for the old value
1612 if(opcode[i]==0x22||opcode[i]==0x26)
1614 alloc_reg(current,i,FTEMP);
1615 alloc_reg_temp(current,i,-1);
1620 // Load to r0 (dummy load)
1621 // but we still need a register to calculate the address
1622 alloc_reg_temp(current,i,-1);
1626 void store_alloc(struct regstat *current,int i)
1628 clear_const(current,rs2[i]);
1629 if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1630 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1631 alloc_reg(current,i,rs2[i]);
1632 if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1633 alloc_reg64(current,i,rs2[i]);
1634 if(rs2[i]) alloc_reg(current,i,FTEMP);
1636 // If using TLB, need a register for pointer to the mapping table
1637 if(using_tlb) alloc_reg(current,i,TLREG);
1638 #if defined(HOST_IMM8)
1639 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1640 else alloc_reg(current,i,INVCP);
1642 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
1643 alloc_reg(current,i,FTEMP);
1645 // We need a temporary register for address generation
1646 alloc_reg_temp(current,i,-1);
1649 void c1ls_alloc(struct regstat *current,int i)
1651 //clear_const(current,rs1[i]); // FIXME
1652 clear_const(current,rt1[i]);
1653 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1654 alloc_reg(current,i,CSREG); // Status
1655 alloc_reg(current,i,FTEMP);
1656 if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1657 alloc_reg64(current,i,FTEMP);
1659 // If using TLB, need a register for pointer to the mapping table
1660 if(using_tlb) alloc_reg(current,i,TLREG);
1661 #if defined(HOST_IMM8)
1662 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1663 else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1664 alloc_reg(current,i,INVCP);
1666 // We need a temporary register for address generation
1667 alloc_reg_temp(current,i,-1);
1670 void c2ls_alloc(struct regstat *current,int i)
1672 clear_const(current,rt1[i]);
1673 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1674 alloc_reg(current,i,FTEMP);
1675 // If using TLB, need a register for pointer to the mapping table
1676 if(using_tlb) alloc_reg(current,i,TLREG);
1677 #if defined(HOST_IMM8)
1678 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1679 else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1680 alloc_reg(current,i,INVCP);
1682 // We need a temporary register for address generation
1683 alloc_reg_temp(current,i,-1);
1686 #ifndef multdiv_alloc
1687 void multdiv_alloc(struct regstat *current,int i)
1694 // case 0x1D: DMULTU
1697 clear_const(current,rs1[i]);
1698 clear_const(current,rs2[i]);
1701 if((opcode2[i]&4)==0) // 32-bit
1703 current->u&=~(1LL<<HIREG);
1704 current->u&=~(1LL<<LOREG);
1705 alloc_reg(current,i,HIREG);
1706 alloc_reg(current,i,LOREG);
1707 alloc_reg(current,i,rs1[i]);
1708 alloc_reg(current,i,rs2[i]);
1709 current->is32|=1LL<<HIREG;
1710 current->is32|=1LL<<LOREG;
1711 dirty_reg(current,HIREG);
1712 dirty_reg(current,LOREG);
1716 current->u&=~(1LL<<HIREG);
1717 current->u&=~(1LL<<LOREG);
1718 current->uu&=~(1LL<<HIREG);
1719 current->uu&=~(1LL<<LOREG);
1720 alloc_reg64(current,i,HIREG);
1721 //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1722 alloc_reg64(current,i,rs1[i]);
1723 alloc_reg64(current,i,rs2[i]);
1724 alloc_all(current,i);
1725 current->is32&=~(1LL<<HIREG);
1726 current->is32&=~(1LL<<LOREG);
1727 dirty_reg(current,HIREG);
1728 dirty_reg(current,LOREG);
1733 // Multiply by zero is zero.
1734 // MIPS does not have a divide by zero exception.
1735 // The result is undefined, we return zero.
1736 alloc_reg(current,i,HIREG);
1737 alloc_reg(current,i,LOREG);
1738 current->is32|=1LL<<HIREG;
1739 current->is32|=1LL<<LOREG;
1740 dirty_reg(current,HIREG);
1741 dirty_reg(current,LOREG);
1746 void cop0_alloc(struct regstat *current,int i)
1748 if(opcode2[i]==0) // MFC0
1751 clear_const(current,rt1[i]);
1752 alloc_all(current,i);
1753 alloc_reg(current,i,rt1[i]);
1754 current->is32|=1LL<<rt1[i];
1755 dirty_reg(current,rt1[i]);
1758 else if(opcode2[i]==4) // MTC0
1761 clear_const(current,rs1[i]);
1762 alloc_reg(current,i,rs1[i]);
1763 alloc_all(current,i);
1766 alloc_all(current,i); // FIXME: Keep r0
1768 alloc_reg(current,i,0);
1773 // TLBR/TLBWI/TLBWR/TLBP/ERET
1774 assert(opcode2[i]==0x10);
1775 alloc_all(current,i);
1779 void cop1_alloc(struct regstat *current,int i)
1781 alloc_reg(current,i,CSREG); // Load status
1782 if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1785 clear_const(current,rt1[i]);
1787 alloc_reg64(current,i,rt1[i]); // DMFC1
1788 current->is32&=~(1LL<<rt1[i]);
1790 alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1791 current->is32|=1LL<<rt1[i];
1793 dirty_reg(current,rt1[i]);
1794 alloc_reg_temp(current,i,-1);
1796 else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1799 clear_const(current,rs1[i]);
1801 alloc_reg64(current,i,rs1[i]); // DMTC1
1803 alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1804 alloc_reg_temp(current,i,-1);
1808 alloc_reg(current,i,0);
1809 alloc_reg_temp(current,i,-1);
1813 void fconv_alloc(struct regstat *current,int i)
1815 alloc_reg(current,i,CSREG); // Load status
1816 alloc_reg_temp(current,i,-1);
1818 void float_alloc(struct regstat *current,int i)
1820 alloc_reg(current,i,CSREG); // Load status
1821 alloc_reg_temp(current,i,-1);
1823 void c2op_alloc(struct regstat *current,int i)
1825 alloc_reg_temp(current,i,-1);
1827 void fcomp_alloc(struct regstat *current,int i)
1829 alloc_reg(current,i,CSREG); // Load status
1830 alloc_reg(current,i,FSREG); // Load flags
1831 dirty_reg(current,FSREG); // Flag will be modified
1832 alloc_reg_temp(current,i,-1);
1835 void syscall_alloc(struct regstat *current,int i)
1837 alloc_cc(current,i);
1838 dirty_reg(current,CCREG);
1839 alloc_all(current,i);
1843 void delayslot_alloc(struct regstat *current,int i)
1854 assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1);
1855 printf("Disabled speculative precompilation\n");
1859 imm16_alloc(current,i);
1863 load_alloc(current,i);
1867 store_alloc(current,i);
1870 alu_alloc(current,i);
1873 shift_alloc(current,i);
1876 multdiv_alloc(current,i);
1879 shiftimm_alloc(current,i);
1882 mov_alloc(current,i);
1885 cop0_alloc(current,i);
1889 cop1_alloc(current,i);
1892 c1ls_alloc(current,i);
1895 c2ls_alloc(current,i);
1898 fconv_alloc(current,i);
1901 float_alloc(current,i);
1904 fcomp_alloc(current,i);
1907 c2op_alloc(current,i);
1912 // Special case where a branch and delay slot span two pages in virtual memory
1913 static void pagespan_alloc(struct regstat *current,int i)
1916 current->wasconst=0;
1918 alloc_all(current,i);
1919 alloc_cc(current,i);
1920 dirty_reg(current,CCREG);
1921 if(opcode[i]==3) // JAL
1923 alloc_reg(current,i,31);
1924 dirty_reg(current,31);
1926 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
1928 alloc_reg(current,i,rs1[i]);
1930 alloc_reg(current,i,rt1[i]);
1931 dirty_reg(current,rt1[i]);
1934 if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
1936 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1937 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1938 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1940 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1941 if(rs2[i]) alloc_reg64(current,i,rs2[i]);
1945 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
1947 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1948 if(!((current->is32>>rs1[i])&1))
1950 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1954 if(opcode[i]==0x11) // BC1
1956 alloc_reg(current,i,FSREG);
1957 alloc_reg(current,i,CSREG);
1962 add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
1964 stubs[stubcount][0]=type;
1965 stubs[stubcount][1]=addr;
1966 stubs[stubcount][2]=retaddr;
1967 stubs[stubcount][3]=a;
1968 stubs[stubcount][4]=b;
1969 stubs[stubcount][5]=c;
1970 stubs[stubcount][6]=d;
1971 stubs[stubcount][7]=e;
1975 // Write out a single register
1976 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
1979 for(hr=0;hr<HOST_REGS;hr++) {
1980 if(hr!=EXCLUDE_REG) {
1981 if((regmap[hr]&63)==r) {
1984 emit_storereg(r,hr);
1986 if((is32>>regmap[hr])&1) {
1987 emit_sarimm(hr,31,hr);
1988 emit_storereg(r|64,hr);
1992 emit_storereg(r|64,hr);
2002 //if(!tracedebug) return 0;
2005 for(i=0;i<2097152;i++) {
2006 unsigned int temp=sum;
2009 sum^=((u_int *)rdram)[i];
2018 sum^=((u_int *)reg)[i];
2026 printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2028 #ifndef DISABLE_COP1
2031 printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2041 void memdebug(int i)
2043 //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2044 //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2047 //if(Count>=-2084597794) {
2048 if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2050 printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2051 //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2052 //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2055 printf("TRACE: %x\n",(&i)[-1]);
2059 printf("TRACE: %x \n",(&j)[10]);
2060 printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2064 //printf("TRACE: %x\n",(&i)[-1]);
2067 void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2069 printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2072 void alu_assemble(int i,struct regstat *i_regs)
2074 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2076 signed char s1,s2,t;
2077 t=get_reg(i_regs->regmap,rt1[i]);
2079 s1=get_reg(i_regs->regmap,rs1[i]);
2080 s2=get_reg(i_regs->regmap,rs2[i]);
2081 if(rs1[i]&&rs2[i]) {
2084 if(opcode2[i]&2) emit_sub(s1,s2,t);
2085 else emit_add(s1,s2,t);
2088 if(s1>=0) emit_mov(s1,t);
2089 else emit_loadreg(rs1[i],t);
2093 if(opcode2[i]&2) emit_neg(s2,t);
2094 else emit_mov(s2,t);
2097 emit_loadreg(rs2[i],t);
2098 if(opcode2[i]&2) emit_neg(t,t);
2101 else emit_zeroreg(t);
2105 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2107 signed char s1l,s2l,s1h,s2h,tl,th;
2108 tl=get_reg(i_regs->regmap,rt1[i]);
2109 th=get_reg(i_regs->regmap,rt1[i]|64);
2111 s1l=get_reg(i_regs->regmap,rs1[i]);
2112 s2l=get_reg(i_regs->regmap,rs2[i]);
2113 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2114 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2115 if(rs1[i]&&rs2[i]) {
2118 if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2119 else emit_adds(s1l,s2l,tl);
2121 #ifdef INVERTED_CARRY
2122 if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2124 if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2126 else emit_add(s1h,s2h,th);
2130 if(s1l>=0) emit_mov(s1l,tl);
2131 else emit_loadreg(rs1[i],tl);
2133 if(s1h>=0) emit_mov(s1h,th);
2134 else emit_loadreg(rs1[i]|64,th);
2139 if(opcode2[i]&2) emit_negs(s2l,tl);
2140 else emit_mov(s2l,tl);
2143 emit_loadreg(rs2[i],tl);
2144 if(opcode2[i]&2) emit_negs(tl,tl);
2147 #ifdef INVERTED_CARRY
2148 if(s2h>=0) emit_mov(s2h,th);
2149 else emit_loadreg(rs2[i]|64,th);
2151 emit_adcimm(-1,th); // x86 has inverted carry flag
2156 if(s2h>=0) emit_rscimm(s2h,0,th);
2158 emit_loadreg(rs2[i]|64,th);
2159 emit_rscimm(th,0,th);
2162 if(s2h>=0) emit_mov(s2h,th);
2163 else emit_loadreg(rs2[i]|64,th);
2170 if(th>=0) emit_zeroreg(th);
2175 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2177 signed char s1l,s1h,s2l,s2h,t;
2178 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2180 t=get_reg(i_regs->regmap,rt1[i]);
2183 s1l=get_reg(i_regs->regmap,rs1[i]);
2184 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2185 s2l=get_reg(i_regs->regmap,rs2[i]);
2186 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2187 if(rs2[i]==0) // rx<r0
2190 if(opcode2[i]==0x2a) // SLT
2191 emit_shrimm(s1h,31,t);
2192 else // SLTU (unsigned can not be less than zero)
2195 else if(rs1[i]==0) // r0<rx
2198 if(opcode2[i]==0x2a) // SLT
2199 emit_set_gz64_32(s2h,s2l,t);
2200 else // SLTU (set if not zero)
2201 emit_set_nz64_32(s2h,s2l,t);
2204 assert(s1l>=0);assert(s1h>=0);
2205 assert(s2l>=0);assert(s2h>=0);
2206 if(opcode2[i]==0x2a) // SLT
2207 emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2209 emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2213 t=get_reg(i_regs->regmap,rt1[i]);
2216 s1l=get_reg(i_regs->regmap,rs1[i]);
2217 s2l=get_reg(i_regs->regmap,rs2[i]);
2218 if(rs2[i]==0) // rx<r0
2221 if(opcode2[i]==0x2a) // SLT
2222 emit_shrimm(s1l,31,t);
2223 else // SLTU (unsigned can not be less than zero)
2226 else if(rs1[i]==0) // r0<rx
2229 if(opcode2[i]==0x2a) // SLT
2230 emit_set_gz32(s2l,t);
2231 else // SLTU (set if not zero)
2232 emit_set_nz32(s2l,t);
2235 assert(s1l>=0);assert(s2l>=0);
2236 if(opcode2[i]==0x2a) // SLT
2237 emit_set_if_less32(s1l,s2l,t);
2239 emit_set_if_carry32(s1l,s2l,t);
2245 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2247 signed char s1l,s1h,s2l,s2h,th,tl;
2248 tl=get_reg(i_regs->regmap,rt1[i]);
2249 th=get_reg(i_regs->regmap,rt1[i]|64);
2250 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2254 s1l=get_reg(i_regs->regmap,rs1[i]);
2255 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2256 s2l=get_reg(i_regs->regmap,rs2[i]);
2257 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2258 if(rs1[i]&&rs2[i]) {
2259 assert(s1l>=0);assert(s1h>=0);
2260 assert(s2l>=0);assert(s2h>=0);
2261 if(opcode2[i]==0x24) { // AND
2262 emit_and(s1l,s2l,tl);
2263 emit_and(s1h,s2h,th);
2265 if(opcode2[i]==0x25) { // OR
2266 emit_or(s1l,s2l,tl);
2267 emit_or(s1h,s2h,th);
2269 if(opcode2[i]==0x26) { // XOR
2270 emit_xor(s1l,s2l,tl);
2271 emit_xor(s1h,s2h,th);
2273 if(opcode2[i]==0x27) { // NOR
2274 emit_or(s1l,s2l,tl);
2275 emit_or(s1h,s2h,th);
2282 if(opcode2[i]==0x24) { // AND
2286 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2288 if(s1l>=0) emit_mov(s1l,tl);
2289 else emit_loadreg(rs1[i],tl);
2290 if(s1h>=0) emit_mov(s1h,th);
2291 else emit_loadreg(rs1[i]|64,th);
2295 if(s2l>=0) emit_mov(s2l,tl);
2296 else emit_loadreg(rs2[i],tl);
2297 if(s2h>=0) emit_mov(s2h,th);
2298 else emit_loadreg(rs2[i]|64,th);
2305 if(opcode2[i]==0x27) { // NOR
2307 if(s1l>=0) emit_not(s1l,tl);
2309 emit_loadreg(rs1[i],tl);
2312 if(s1h>=0) emit_not(s1h,th);
2314 emit_loadreg(rs1[i]|64,th);
2320 if(s2l>=0) emit_not(s2l,tl);
2322 emit_loadreg(rs2[i],tl);
2325 if(s2h>=0) emit_not(s2h,th);
2327 emit_loadreg(rs2[i]|64,th);
2343 s1l=get_reg(i_regs->regmap,rs1[i]);
2344 s2l=get_reg(i_regs->regmap,rs2[i]);
2345 if(rs1[i]&&rs2[i]) {
2348 if(opcode2[i]==0x24) { // AND
2349 emit_and(s1l,s2l,tl);
2351 if(opcode2[i]==0x25) { // OR
2352 emit_or(s1l,s2l,tl);
2354 if(opcode2[i]==0x26) { // XOR
2355 emit_xor(s1l,s2l,tl);
2357 if(opcode2[i]==0x27) { // NOR
2358 emit_or(s1l,s2l,tl);
2364 if(opcode2[i]==0x24) { // AND
2367 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2369 if(s1l>=0) emit_mov(s1l,tl);
2370 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2374 if(s2l>=0) emit_mov(s2l,tl);
2375 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2377 else emit_zeroreg(tl);
2379 if(opcode2[i]==0x27) { // NOR
2381 if(s1l>=0) emit_not(s1l,tl);
2383 emit_loadreg(rs1[i],tl);
2389 if(s2l>=0) emit_not(s2l,tl);
2391 emit_loadreg(rs2[i],tl);
2395 else emit_movimm(-1,tl);
2404 void imm16_assemble(int i,struct regstat *i_regs)
2406 if (opcode[i]==0x0f) { // LUI
2409 t=get_reg(i_regs->regmap,rt1[i]);
2412 if(!((i_regs->isconst>>t)&1))
2413 emit_movimm(imm[i]<<16,t);
2417 if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2420 t=get_reg(i_regs->regmap,rt1[i]);
2421 s=get_reg(i_regs->regmap,rs1[i]);
2426 if(!((i_regs->isconst>>t)&1)) {
2428 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2429 emit_addimm(t,imm[i],t);
2431 if(!((i_regs->wasconst>>s)&1))
2432 emit_addimm(s,imm[i],t);
2434 emit_movimm(constmap[i][s]+imm[i],t);
2440 if(!((i_regs->isconst>>t)&1))
2441 emit_movimm(imm[i],t);
2446 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2448 signed char sh,sl,th,tl;
2449 th=get_reg(i_regs->regmap,rt1[i]|64);
2450 tl=get_reg(i_regs->regmap,rt1[i]);
2451 sh=get_reg(i_regs->regmap,rs1[i]|64);
2452 sl=get_reg(i_regs->regmap,rs1[i]);
2458 emit_addimm64_32(sh,sl,imm[i],th,tl);
2461 emit_addimm(sl,imm[i],tl);
2464 emit_movimm(imm[i],tl);
2465 if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2470 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2472 //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2473 signed char sh,sl,t;
2474 t=get_reg(i_regs->regmap,rt1[i]);
2475 sh=get_reg(i_regs->regmap,rs1[i]|64);
2476 sl=get_reg(i_regs->regmap,rs1[i]);
2480 if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2481 if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2482 if(opcode[i]==0x0a) { // SLTI
2484 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2485 emit_slti32(t,imm[i],t);
2487 emit_slti32(sl,imm[i],t);
2492 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2493 emit_sltiu32(t,imm[i],t);
2495 emit_sltiu32(sl,imm[i],t);
2500 if(opcode[i]==0x0a) // SLTI
2501 emit_slti64_32(sh,sl,imm[i],t);
2503 emit_sltiu64_32(sh,sl,imm[i],t);
2506 // SLTI(U) with r0 is just stupid,
2507 // nonetheless examples can be found
2508 if(opcode[i]==0x0a) // SLTI
2509 if(0<imm[i]) emit_movimm(1,t);
2510 else emit_zeroreg(t);
2513 if(imm[i]) emit_movimm(1,t);
2514 else emit_zeroreg(t);
2520 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2522 signed char sh,sl,th,tl;
2523 th=get_reg(i_regs->regmap,rt1[i]|64);
2524 tl=get_reg(i_regs->regmap,rt1[i]);
2525 sh=get_reg(i_regs->regmap,rs1[i]|64);
2526 sl=get_reg(i_regs->regmap,rs1[i]);
2527 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2528 if(opcode[i]==0x0c) //ANDI
2532 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2533 emit_andimm(tl,imm[i],tl);
2535 if(!((i_regs->wasconst>>sl)&1))
2536 emit_andimm(sl,imm[i],tl);
2538 emit_movimm(constmap[i][sl]&imm[i],tl);
2543 if(th>=0) emit_zeroreg(th);
2549 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2553 emit_loadreg(rs1[i]|64,th);
2558 if(opcode[i]==0x0d) //ORI
2560 emit_orimm(tl,imm[i],tl);
2562 if(!((i_regs->wasconst>>sl)&1))
2563 emit_orimm(sl,imm[i],tl);
2565 emit_movimm(constmap[i][sl]|imm[i],tl);
2567 if(opcode[i]==0x0e) //XORI
2569 emit_xorimm(tl,imm[i],tl);
2571 if(!((i_regs->wasconst>>sl)&1))
2572 emit_xorimm(sl,imm[i],tl);
2574 emit_movimm(constmap[i][sl]^imm[i],tl);
2578 emit_movimm(imm[i],tl);
2579 if(th>=0) emit_zeroreg(th);
2587 void shiftimm_assemble(int i,struct regstat *i_regs)
2589 if(opcode2[i]<=0x3) // SLL/SRL/SRA
2593 t=get_reg(i_regs->regmap,rt1[i]);
2594 s=get_reg(i_regs->regmap,rs1[i]);
2603 if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2605 if(opcode2[i]==0) // SLL
2607 emit_shlimm(s<0?t:s,imm[i],t);
2609 if(opcode2[i]==2) // SRL
2611 emit_shrimm(s<0?t:s,imm[i],t);
2613 if(opcode2[i]==3) // SRA
2615 emit_sarimm(s<0?t:s,imm[i],t);
2619 if(s>=0 && s!=t) emit_mov(s,t);
2623 //emit_storereg(rt1[i],t); //DEBUG
2626 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2629 signed char sh,sl,th,tl;
2630 th=get_reg(i_regs->regmap,rt1[i]|64);
2631 tl=get_reg(i_regs->regmap,rt1[i]);
2632 sh=get_reg(i_regs->regmap,rs1[i]|64);
2633 sl=get_reg(i_regs->regmap,rs1[i]);
2638 if(th>=0) emit_zeroreg(th);
2645 if(opcode2[i]==0x38) // DSLL
2647 if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2648 emit_shlimm(sl,imm[i],tl);
2650 if(opcode2[i]==0x3a) // DSRL
2652 emit_shrdimm(sl,sh,imm[i],tl);
2653 if(th>=0) emit_shrimm(sh,imm[i],th);
2655 if(opcode2[i]==0x3b) // DSRA
2657 emit_shrdimm(sl,sh,imm[i],tl);
2658 if(th>=0) emit_sarimm(sh,imm[i],th);
2662 if(sl!=tl) emit_mov(sl,tl);
2663 if(th>=0&&sh!=th) emit_mov(sh,th);
2669 if(opcode2[i]==0x3c) // DSLL32
2672 signed char sl,tl,th;
2673 tl=get_reg(i_regs->regmap,rt1[i]);
2674 th=get_reg(i_regs->regmap,rt1[i]|64);
2675 sl=get_reg(i_regs->regmap,rs1[i]);
2684 emit_shlimm(th,imm[i]&31,th);
2689 if(opcode2[i]==0x3e) // DSRL32
2692 signed char sh,tl,th;
2693 tl=get_reg(i_regs->regmap,rt1[i]);
2694 th=get_reg(i_regs->regmap,rt1[i]|64);
2695 sh=get_reg(i_regs->regmap,rs1[i]|64);
2699 if(th>=0) emit_zeroreg(th);
2702 emit_shrimm(tl,imm[i]&31,tl);
2707 if(opcode2[i]==0x3f) // DSRA32
2711 tl=get_reg(i_regs->regmap,rt1[i]);
2712 sh=get_reg(i_regs->regmap,rs1[i]|64);
2718 emit_sarimm(tl,imm[i]&31,tl);
2725 #ifndef shift_assemble
2726 void shift_assemble(int i,struct regstat *i_regs)
2728 printf("Need shift_assemble for this architecture.\n");
2733 void load_assemble(int i,struct regstat *i_regs)
2735 int s,th,tl,addr,map=-1;
2738 int memtarget=0,c=0;
2740 th=get_reg(i_regs->regmap,rt1[i]|64);
2741 tl=get_reg(i_regs->regmap,rt1[i]);
2742 s=get_reg(i_regs->regmap,rs1[i]);
2744 for(hr=0;hr<HOST_REGS;hr++) {
2745 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2747 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2749 c=(i_regs->wasconst>>s)&1;
2750 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2751 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2753 //printf("load_assemble: c=%d\n",c);
2754 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2755 // FIXME: Even if the load is a NOP, we should check for pagefaults...
2757 if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2759 // could be FIFO, must perform the read
2761 assem_debug("(forced read)\n");
2762 tl=get_reg(i_regs->regmap,-1);
2766 if(offset||s<0||c) addr=tl;
2772 if(th>=0) reglist&=~(1<<th);
2775 //#define R29_HACK 1
2777 // Strmnnrmn's speed hack
2778 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2781 emit_cmpimm(addr,RAM_SIZE);
2783 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2784 // Hint to branch predictor that the branch is unlikely to be taken
2786 emit_jno_unlikely(0);
2794 if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2795 if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2796 map=get_reg(i_regs->regmap,TLREG);
2798 map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2799 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2801 if (opcode[i]==0x20) { // LB
2803 #ifdef HOST_IMM_ADDR32
2805 emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2809 //emit_xorimm(addr,3,tl);
2810 //gen_tlb_addr_r(tl,map);
2811 //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2813 #ifdef BIG_ENDIAN_MIPS
2814 if(!c) emit_xorimm(addr,3,tl);
2815 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2817 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2818 else if (tl!=addr) emit_mov(addr,tl);
2820 emit_movsbl_indexed_tlb(x,tl,map,tl);
2823 add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2826 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2828 if (opcode[i]==0x21) { // LH
2830 #ifdef HOST_IMM_ADDR32
2832 emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2837 #ifdef BIG_ENDIAN_MIPS
2838 if(!c) emit_xorimm(addr,2,tl);
2839 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2841 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2842 else if (tl!=addr) emit_mov(addr,tl);
2845 //emit_movswl_indexed_tlb(x,tl,map,tl);
2848 gen_tlb_addr_r(tl,map);
2849 emit_movswl_indexed(x,tl,tl);
2851 emit_movswl_indexed((int)rdram-0x80000000+x,tl,tl);
2854 add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2857 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2859 if (opcode[i]==0x23) { // LW
2861 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2862 #ifdef HOST_IMM_ADDR32
2864 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2867 emit_readword_indexed_tlb(0,addr,map,tl);
2869 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2872 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2874 if (opcode[i]==0x24) { // LBU
2876 #ifdef HOST_IMM_ADDR32
2878 emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
2882 //emit_xorimm(addr,3,tl);
2883 //gen_tlb_addr_r(tl,map);
2884 //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
2886 #ifdef BIG_ENDIAN_MIPS
2887 if(!c) emit_xorimm(addr,3,tl);
2888 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2890 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2891 else if (tl!=addr) emit_mov(addr,tl);
2893 emit_movzbl_indexed_tlb(x,tl,map,tl);
2896 add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2899 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2901 if (opcode[i]==0x25) { // LHU
2903 #ifdef HOST_IMM_ADDR32
2905 emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
2910 #ifdef BIG_ENDIAN_MIPS
2911 if(!c) emit_xorimm(addr,2,tl);
2912 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2914 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2915 else if (tl!=addr) emit_mov(addr,tl);
2918 //emit_movzwl_indexed_tlb(x,tl,map,tl);
2921 gen_tlb_addr_r(tl,map);
2922 emit_movzwl_indexed(x,tl,tl);
2924 emit_movzwl_indexed((int)rdram-0x80000000+x,tl,tl);
2926 add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2930 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2932 if (opcode[i]==0x27) { // LWU
2935 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2936 #ifdef HOST_IMM_ADDR32
2938 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2941 emit_readword_indexed_tlb(0,addr,map,tl);
2943 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2946 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2950 if (opcode[i]==0x37) { // LD
2952 //gen_tlb_addr_r(tl,map);
2953 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
2954 //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
2955 #ifdef HOST_IMM_ADDR32
2957 emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
2960 emit_readdword_indexed_tlb(0,addr,map,th,tl);
2962 add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2965 inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2967 //emit_storereg(rt1[i],tl); // DEBUG
2969 //if(opcode[i]==0x23)
2970 //if(opcode[i]==0x24)
2971 //if(opcode[i]==0x23||opcode[i]==0x24)
2972 /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
2976 emit_readword((int)&last_count,ECX);
2978 if(get_reg(i_regs->regmap,CCREG)<0)
2979 emit_loadreg(CCREG,HOST_CCREG);
2980 emit_add(HOST_CCREG,ECX,HOST_CCREG);
2981 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
2982 emit_writeword(HOST_CCREG,(int)&Count);
2985 if(get_reg(i_regs->regmap,CCREG)<0)
2986 emit_loadreg(CCREG,0);
2988 emit_mov(HOST_CCREG,0);
2990 emit_addimm(0,2*ccadj[i],0);
2991 emit_writeword(0,(int)&Count);
2993 emit_call((int)memdebug);
2995 restore_regs(0x100f);
2999 #ifndef loadlr_assemble
3000 void loadlr_assemble(int i,struct regstat *i_regs)
3002 printf("Need loadlr_assemble for this architecture.\n");
3007 void store_assemble(int i,struct regstat *i_regs)
3012 int jaddr=0,jaddr2,type;
3013 int memtarget=0,c=0;
3014 int agr=AGEN1+(i&1);
3016 th=get_reg(i_regs->regmap,rs2[i]|64);
3017 tl=get_reg(i_regs->regmap,rs2[i]);
3018 s=get_reg(i_regs->regmap,rs1[i]);
3019 temp=get_reg(i_regs->regmap,agr);
3020 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3023 c=(i_regs->wasconst>>s)&1;
3024 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3025 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3029 for(hr=0;hr<HOST_REGS;hr++) {
3030 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3032 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3033 if(offset||s<0||c) addr=temp;
3038 // Strmnnrmn's speed hack
3040 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3042 emit_cmpimm(addr,RAM_SIZE);
3043 #ifdef DESTRUCTIVE_SHIFT
3044 if(s==addr) emit_mov(s,temp);
3047 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3051 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3052 // Hint to branch predictor that the branch is unlikely to be taken
3054 emit_jno_unlikely(0);
3062 if (opcode[i]==0x28) x=3; // SB
3063 if (opcode[i]==0x29) x=2; // SH
3064 map=get_reg(i_regs->regmap,TLREG);
3066 map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3067 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3070 if (opcode[i]==0x28) { // SB
3073 #ifdef BIG_ENDIAN_MIPS
3074 if(!c) emit_xorimm(addr,3,temp);
3075 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3077 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
3078 else if (addr!=temp) emit_mov(addr,temp);
3080 //gen_tlb_addr_w(temp,map);
3081 //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3082 emit_writebyte_indexed_tlb(tl,x,temp,map,temp);
3086 if (opcode[i]==0x29) { // SH
3089 #ifdef BIG_ENDIAN_MIPS
3090 if(!c) emit_xorimm(addr,2,temp);
3091 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3093 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
3094 else if (addr!=temp) emit_mov(addr,temp);
3097 //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3100 gen_tlb_addr_w(temp,map);
3101 emit_writehword_indexed(tl,x,temp);
3103 emit_writehword_indexed(tl,(int)rdram-0x80000000+x,temp);
3107 if (opcode[i]==0x2B) { // SW
3109 //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3110 emit_writeword_indexed_tlb(tl,0,addr,map,temp);
3113 if (opcode[i]==0x3F) { // SD
3117 //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3118 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3119 emit_writedword_indexed_tlb(th,tl,0,addr,map,temp);
3122 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3123 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3124 emit_writedword_indexed_tlb(tl,tl,0,addr,map,temp);
3129 if(!using_tlb&&(!c||memtarget))
3130 // addr could be a temp, make sure it survives STORE*_STUB
3133 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3134 } else if(!memtarget) {
3135 inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3139 #ifdef DESTRUCTIVE_SHIFT
3140 // The x86 shift operation is 'destructive'; it overwrites the
3141 // source register, so we need to make a copy first and use that.
3144 #if defined(HOST_IMM8)
3145 int ir=get_reg(i_regs->regmap,INVCP);
3147 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3149 emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3153 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3156 //if(opcode[i]==0x2B || opcode[i]==0x3F)
3157 //if(opcode[i]==0x2B || opcode[i]==0x28)
3158 //if(opcode[i]==0x2B || opcode[i]==0x29)
3159 //if(opcode[i]==0x2B)
3160 /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3164 emit_readword((int)&last_count,ECX);
3166 if(get_reg(i_regs->regmap,CCREG)<0)
3167 emit_loadreg(CCREG,HOST_CCREG);
3168 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3169 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3170 emit_writeword(HOST_CCREG,(int)&Count);
3173 if(get_reg(i_regs->regmap,CCREG)<0)
3174 emit_loadreg(CCREG,0);
3176 emit_mov(HOST_CCREG,0);
3178 emit_addimm(0,2*ccadj[i],0);
3179 emit_writeword(0,(int)&Count);
3181 emit_call((int)memdebug);
3183 restore_regs(0x100f);
3187 void storelr_assemble(int i,struct regstat *i_regs)
3194 int case1,case2,case3;
3195 int done0,done1,done2;
3197 int agr=AGEN1+(i&1);
3199 th=get_reg(i_regs->regmap,rs2[i]|64);
3200 tl=get_reg(i_regs->regmap,rs2[i]);
3201 s=get_reg(i_regs->regmap,rs1[i]);
3202 temp=get_reg(i_regs->regmap,agr);
3203 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3206 c=(i_regs->isconst>>s)&1;
3207 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3208 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3211 for(hr=0;hr<HOST_REGS;hr++) {
3212 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3218 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3219 if(!offset&&s!=temp) emit_mov(s,temp);
3225 if(!memtarget||!rs1[i]) {
3230 if((u_int)rdram!=0x80000000)
3231 emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3233 int map=get_reg(i_regs->regmap,TLREG);
3235 map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3236 if(!c&&!offset&&s>=0) emit_mov(s,temp);
3237 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3238 if(!jaddr&&!memtarget) {
3242 gen_tlb_addr_w(temp,map);
3245 if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3246 temp2=get_reg(i_regs->regmap,FTEMP);
3247 if(!rs2[i]) temp2=th=tl;
3250 #ifndef BIG_ENDIAN_MIPS
3251 emit_xorimm(temp,3,temp);
3253 emit_testimm(temp,2);
3256 emit_testimm(temp,1);
3260 if (opcode[i]==0x2A) { // SWL
3261 emit_writeword_indexed(tl,0,temp);
3263 if (opcode[i]==0x2E) { // SWR
3264 emit_writebyte_indexed(tl,3,temp);
3266 if (opcode[i]==0x2C) { // SDL
3267 emit_writeword_indexed(th,0,temp);
3268 if(rs2[i]) emit_mov(tl,temp2);
3270 if (opcode[i]==0x2D) { // SDR
3271 emit_writebyte_indexed(tl,3,temp);
3272 if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3277 set_jump_target(case1,(int)out);
3278 if (opcode[i]==0x2A) { // SWL
3279 // Write 3 msb into three least significant bytes
3280 if(rs2[i]) emit_rorimm(tl,8,tl);
3281 emit_writehword_indexed(tl,-1,temp);
3282 if(rs2[i]) emit_rorimm(tl,16,tl);
3283 emit_writebyte_indexed(tl,1,temp);
3284 if(rs2[i]) emit_rorimm(tl,8,tl);
3286 if (opcode[i]==0x2E) { // SWR
3287 // Write two lsb into two most significant bytes
3288 emit_writehword_indexed(tl,1,temp);
3290 if (opcode[i]==0x2C) { // SDL
3291 if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3292 // Write 3 msb into three least significant bytes
3293 if(rs2[i]) emit_rorimm(th,8,th);
3294 emit_writehword_indexed(th,-1,temp);
3295 if(rs2[i]) emit_rorimm(th,16,th);
3296 emit_writebyte_indexed(th,1,temp);
3297 if(rs2[i]) emit_rorimm(th,8,th);
3299 if (opcode[i]==0x2D) { // SDR
3300 if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3301 // Write two lsb into two most significant bytes
3302 emit_writehword_indexed(tl,1,temp);
3307 set_jump_target(case2,(int)out);
3308 emit_testimm(temp,1);
3311 if (opcode[i]==0x2A) { // SWL
3312 // Write two msb into two least significant bytes
3313 if(rs2[i]) emit_rorimm(tl,16,tl);
3314 emit_writehword_indexed(tl,-2,temp);
3315 if(rs2[i]) emit_rorimm(tl,16,tl);
3317 if (opcode[i]==0x2E) { // SWR
3318 // Write 3 lsb into three most significant bytes
3319 emit_writebyte_indexed(tl,-1,temp);
3320 if(rs2[i]) emit_rorimm(tl,8,tl);
3321 emit_writehword_indexed(tl,0,temp);
3322 if(rs2[i]) emit_rorimm(tl,24,tl);
3324 if (opcode[i]==0x2C) { // SDL
3325 if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3326 // Write two msb into two least significant bytes
3327 if(rs2[i]) emit_rorimm(th,16,th);
3328 emit_writehword_indexed(th,-2,temp);
3329 if(rs2[i]) emit_rorimm(th,16,th);
3331 if (opcode[i]==0x2D) { // SDR
3332 if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3333 // Write 3 lsb into three most significant bytes
3334 emit_writebyte_indexed(tl,-1,temp);
3335 if(rs2[i]) emit_rorimm(tl,8,tl);
3336 emit_writehword_indexed(tl,0,temp);
3337 if(rs2[i]) emit_rorimm(tl,24,tl);
3342 set_jump_target(case3,(int)out);
3343 if (opcode[i]==0x2A) { // SWL
3344 // Write msb into least significant byte
3345 if(rs2[i]) emit_rorimm(tl,24,tl);
3346 emit_writebyte_indexed(tl,-3,temp);
3347 if(rs2[i]) emit_rorimm(tl,8,tl);
3349 if (opcode[i]==0x2E) { // SWR
3350 // Write entire word
3351 emit_writeword_indexed(tl,-3,temp);
3353 if (opcode[i]==0x2C) { // SDL
3354 if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3355 // Write msb into least significant byte
3356 if(rs2[i]) emit_rorimm(th,24,th);
3357 emit_writebyte_indexed(th,-3,temp);
3358 if(rs2[i]) emit_rorimm(th,8,th);
3360 if (opcode[i]==0x2D) { // SDR
3361 if(rs2[i]) emit_mov(th,temp2);
3362 // Write entire word
3363 emit_writeword_indexed(tl,-3,temp);
3365 set_jump_target(done0,(int)out);
3366 set_jump_target(done1,(int)out);
3367 set_jump_target(done2,(int)out);
3368 if (opcode[i]==0x2C) { // SDL
3369 emit_testimm(temp,4);
3372 emit_andimm(temp,~3,temp);
3373 emit_writeword_indexed(temp2,4,temp);
3374 set_jump_target(done0,(int)out);
3376 if (opcode[i]==0x2D) { // SDR
3377 emit_testimm(temp,4);
3380 emit_andimm(temp,~3,temp);
3381 emit_writeword_indexed(temp2,-4,temp);
3382 set_jump_target(done0,(int)out);
3385 add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
3388 emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
3389 #if defined(HOST_IMM8)
3390 int ir=get_reg(i_regs->regmap,INVCP);
3392 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3394 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3398 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3402 //save_regs(0x100f);
3403 emit_readword((int)&last_count,ECX);
3404 if(get_reg(i_regs->regmap,CCREG)<0)
3405 emit_loadreg(CCREG,HOST_CCREG);
3406 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3407 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3408 emit_writeword(HOST_CCREG,(int)&Count);
3409 emit_call((int)memdebug);
3411 //restore_regs(0x100f);
3415 void c1ls_assemble(int i,struct regstat *i_regs)
3417 #ifndef DISABLE_COP1
3423 int jaddr,jaddr2=0,jaddr3,type;
3424 int agr=AGEN1+(i&1);
3426 th=get_reg(i_regs->regmap,FTEMP|64);
3427 tl=get_reg(i_regs->regmap,FTEMP);
3428 s=get_reg(i_regs->regmap,rs1[i]);
3429 temp=get_reg(i_regs->regmap,agr);
3430 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3435 for(hr=0;hr<HOST_REGS;hr++) {
3436 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3438 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3439 if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3441 // Loads use a temporary register which we need to save
3444 if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3448 //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3449 //else c=(i_regs->wasconst>>s)&1;
3450 if(s>=0) c=(i_regs->wasconst>>s)&1;
3451 // Check cop1 unusable
3453 signed char rs=get_reg(i_regs->regmap,CSREG);
3455 emit_testimm(rs,0x20000000);
3458 add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3461 if (opcode[i]==0x39) { // SWC1 (get float address)
3462 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],tl);
3464 if (opcode[i]==0x3D) { // SDC1 (get double address)
3465 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],tl);
3467 // Generate address + offset
3470 emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3474 map=get_reg(i_regs->regmap,TLREG);
3476 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3477 map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
3479 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3480 map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
3483 if (opcode[i]==0x39) { // SWC1 (read float)
3484 emit_readword_indexed(0,tl,tl);
3486 if (opcode[i]==0x3D) { // SDC1 (read double)
3487 emit_readword_indexed(4,tl,th);
3488 emit_readword_indexed(0,tl,tl);
3490 if (opcode[i]==0x31) { // LWC1 (get target address)
3491 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],temp);
3493 if (opcode[i]==0x35) { // LDC1 (get target address)
3494 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],temp);
3501 else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80000000+RAM_SIZE) {
3503 emit_jmp(0); // inline_readstub/inline_writestub? Very rare case
3505 #ifdef DESTRUCTIVE_SHIFT
3506 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3507 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3511 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3512 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3514 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3515 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3518 if (opcode[i]==0x31) { // LWC1
3519 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3520 //gen_tlb_addr_r(ar,map);
3521 //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3522 #ifdef HOST_IMM_ADDR32
3523 if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3526 emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3529 if (opcode[i]==0x35) { // LDC1
3531 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3532 //gen_tlb_addr_r(ar,map);
3533 //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3534 //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3535 #ifdef HOST_IMM_ADDR32
3536 if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3539 emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3542 if (opcode[i]==0x39) { // SWC1
3543 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3544 emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3547 if (opcode[i]==0x3D) { // SDC1
3549 //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3550 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3551 emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3555 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3556 #ifndef DESTRUCTIVE_SHIFT
3557 temp=offset||c||s<0?ar:s;
3559 #if defined(HOST_IMM8)
3560 int ir=get_reg(i_regs->regmap,INVCP);
3562 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3564 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3568 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3571 if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3572 if (opcode[i]==0x31) { // LWC1 (write float)
3573 emit_writeword_indexed(tl,0,temp);
3575 if (opcode[i]==0x35) { // LDC1 (write double)
3576 emit_writeword_indexed(th,4,temp);
3577 emit_writeword_indexed(tl,0,temp);
3579 //if(opcode[i]==0x39)
3580 /*if(opcode[i]==0x39||opcode[i]==0x31)
3583 emit_readword((int)&last_count,ECX);
3584 if(get_reg(i_regs->regmap,CCREG)<0)
3585 emit_loadreg(CCREG,HOST_CCREG);
3586 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3587 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3588 emit_writeword(HOST_CCREG,(int)&Count);
3589 emit_call((int)memdebug);
3593 cop1_unusable(i, i_regs);
3597 void c2ls_assemble(int i,struct regstat *i_regs)
3602 int memtarget=0,c=0;
3603 int jaddr,jaddr2=0,jaddr3,type;
3604 int agr=AGEN1+(i&1);
3606 u_int copr=(source[i]>>16)&0x1f;
3607 s=get_reg(i_regs->regmap,rs1[i]);
3608 tl=get_reg(i_regs->regmap,FTEMP);
3614 for(hr=0;hr<HOST_REGS;hr++) {
3615 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3617 if(i_regs->regmap[HOST_CCREG]==CCREG)
3618 reglist&=~(1<<HOST_CCREG);
3621 if (opcode[i]==0x3a) { // SWC2
3622 ar=get_reg(i_regs->regmap,agr);
3623 if(ar<0) ar=get_reg(i_regs->regmap,-1);
3628 if(s>=0) c=(i_regs->wasconst>>s)&1;
3629 memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
3630 if (!offset&&!c&&s>=0) ar=s;
3633 if (opcode[i]==0x3a) { // SWC2
3634 cop2_get_dreg(copr,tl,HOST_TEMPREG);
3642 emit_jmp(0); // inline_readstub/inline_writestub?
3646 emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3650 if (opcode[i]==0x32) { // LWC2
3651 #ifdef HOST_IMM_ADDR32
3652 if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
3655 emit_readword_indexed(0,ar,tl);
3657 if (opcode[i]==0x3a) { // SWC2
3658 #ifdef DESTRUCTIVE_SHIFT
3659 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3661 emit_writeword_indexed(tl,0,ar);
3665 add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist);
3666 if (opcode[i]==0x3a) { // SWC2
3667 #if defined(HOST_IMM8)
3668 int ir=get_reg(i_regs->regmap,INVCP);
3670 emit_cmpmem_indexedsr12_reg(ir,ar,1);
3672 emit_cmpmem_indexedsr12_imm((int)invalid_code,ar,1);
3676 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),ar,0,0,0);
3678 if (opcode[i]==0x32) { // LWC2
3679 cop2_put_dreg(copr,tl,HOST_TEMPREG);
3683 #ifndef multdiv_assemble
3684 void multdiv_assemble(int i,struct regstat *i_regs)
3686 printf("Need multdiv_assemble for this architecture.\n");
3691 void mov_assemble(int i,struct regstat *i_regs)
3693 //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3694 //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
3697 signed char sh,sl,th,tl;
3698 th=get_reg(i_regs->regmap,rt1[i]|64);
3699 tl=get_reg(i_regs->regmap,rt1[i]);
3702 sh=get_reg(i_regs->regmap,rs1[i]|64);
3703 sl=get_reg(i_regs->regmap,rs1[i]);
3704 if(sl>=0) emit_mov(sl,tl);
3705 else emit_loadreg(rs1[i],tl);
3707 if(sh>=0) emit_mov(sh,th);
3708 else emit_loadreg(rs1[i]|64,th);
3714 #ifndef fconv_assemble
3715 void fconv_assemble(int i,struct regstat *i_regs)
3717 printf("Need fconv_assemble for this architecture.\n");
3723 void float_assemble(int i,struct regstat *i_regs)
3725 printf("Need float_assemble for this architecture.\n");
3730 void syscall_assemble(int i,struct regstat *i_regs)
3732 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3733 assert(ccreg==HOST_CCREG);
3734 assert(!is_delayslot);
3735 emit_movimm(start+i*4,EAX); // Get PC
3736 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
3737 emit_jmp((int)jump_syscall_hle); // XXX
3740 void hlecall_assemble(int i,struct regstat *i_regs)
3742 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3743 assert(ccreg==HOST_CCREG);
3744 assert(!is_delayslot);
3745 emit_movimm(start+i*4+4,0); // Get PC
3746 emit_movimm((int)psxHLEt[source[i]&7],1);
3747 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // XXX
3748 emit_jmp((int)jump_hlecall);
3751 void ds_assemble(int i,struct regstat *i_regs)
3756 alu_assemble(i,i_regs);break;
3758 imm16_assemble(i,i_regs);break;
3760 shift_assemble(i,i_regs);break;
3762 shiftimm_assemble(i,i_regs);break;
3764 load_assemble(i,i_regs);break;
3766 loadlr_assemble(i,i_regs);break;
3768 store_assemble(i,i_regs);break;
3770 storelr_assemble(i,i_regs);break;
3772 cop0_assemble(i,i_regs);break;
3774 cop1_assemble(i,i_regs);break;
3776 c1ls_assemble(i,i_regs);break;
3778 cop2_assemble(i,i_regs);break;
3780 c2ls_assemble(i,i_regs);break;
3782 c2op_assemble(i,i_regs);break;
3784 fconv_assemble(i,i_regs);break;
3786 float_assemble(i,i_regs);break;
3788 fcomp_assemble(i,i_regs);break;
3790 multdiv_assemble(i,i_regs);break;
3792 mov_assemble(i,i_regs);break;
3801 printf("Jump in the delay slot. This is probably a bug.\n");
3806 // Is the branch target a valid internal jump?
3807 int internal_branch(uint64_t i_is32,int addr)
3809 if(addr&1) return 0; // Indirect (register) jump
3810 if(addr>=start && addr<start+slen*4-4)
3812 int t=(addr-start)>>2;
3813 // Delay slots are not valid branch targets
3814 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
3815 // 64 -> 32 bit transition requires a recompile
3816 /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
3818 if(requires_32bit[t]&~i_is32) printf("optimizable: no\n");
3819 else printf("optimizable: yes\n");
3821 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
3822 if(requires_32bit[t]&~i_is32) return 0;
3828 #ifndef wb_invalidate
3829 void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
3830 uint64_t u,uint64_t uu)
3833 for(hr=0;hr<HOST_REGS;hr++) {
3834 if(hr!=EXCLUDE_REG) {
3835 if(pre[hr]!=entry[hr]) {
3838 if(get_reg(entry,pre[hr])<0) {
3840 if(!((u>>pre[hr])&1)) {
3841 emit_storereg(pre[hr],hr);
3842 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
3843 emit_sarimm(hr,31,hr);
3844 emit_storereg(pre[hr]|64,hr);
3848 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
3849 emit_storereg(pre[hr],hr);
3858 // Move from one register to another (no writeback)
3859 for(hr=0;hr<HOST_REGS;hr++) {
3860 if(hr!=EXCLUDE_REG) {
3861 if(pre[hr]!=entry[hr]) {
3862 if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
3864 if((nr=get_reg(entry,pre[hr]))>=0) {
3874 // Load the specified registers
3875 // This only loads the registers given as arguments because
3876 // we don't want to load things that will be overwritten
3877 void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
3881 for(hr=0;hr<HOST_REGS;hr++) {
3882 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
3883 if(entry[hr]!=regmap[hr]) {
3884 if(regmap[hr]==rs1||regmap[hr]==rs2)
3891 emit_loadreg(regmap[hr],hr);
3898 for(hr=0;hr<HOST_REGS;hr++) {
3899 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
3900 if(entry[hr]!=regmap[hr]) {
3901 if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
3903 assert(regmap[hr]!=64);
3904 if((is32>>(regmap[hr]&63))&1) {
3905 int lr=get_reg(regmap,regmap[hr]-64);
3907 emit_sarimm(lr,31,hr);
3909 emit_loadreg(regmap[hr],hr);
3913 emit_loadreg(regmap[hr],hr);
3921 // Load registers prior to the start of a loop
3922 // so that they are not loaded within the loop
3923 static void loop_preload(signed char pre[],signed char entry[])
3926 for(hr=0;hr<HOST_REGS;hr++) {
3927 if(hr!=EXCLUDE_REG) {
3928 if(pre[hr]!=entry[hr]) {
3930 if(get_reg(pre,entry[hr])<0) {
3931 assem_debug("loop preload:\n");
3932 //printf("loop preload: %d\n",hr);
3936 else if(entry[hr]<TEMPREG)
3938 emit_loadreg(entry[hr],hr);
3940 else if(entry[hr]-64<TEMPREG)
3942 emit_loadreg(entry[hr],hr);
3951 // Generate address for load/store instruction
3952 // goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
3953 void address_generation(int i,struct regstat *i_regs,signed char entry[])
3955 if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS||itype[i]==C2LS) {
3957 int agr=AGEN1+(i&1);
3958 int mgr=MGEN1+(i&1);
3959 if(itype[i]==LOAD) {
3960 ra=get_reg(i_regs->regmap,rt1[i]);
3961 //if(rt1[i]) assert(ra>=0);
3963 if(itype[i]==LOADLR) {
3964 ra=get_reg(i_regs->regmap,FTEMP);
3966 if(itype[i]==STORE||itype[i]==STORELR) {
3967 ra=get_reg(i_regs->regmap,agr);
3968 if(ra<0) ra=get_reg(i_regs->regmap,-1);
3970 if(itype[i]==C1LS||itype[i]==C2LS) {
3971 if ((opcode[i]&0x3b)==0x31||(opcode[i]&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
3972 ra=get_reg(i_regs->regmap,FTEMP);
3973 else { // SWC1/SDC1/SWC2/SDC2
3974 ra=get_reg(i_regs->regmap,agr);
3975 if(ra<0) ra=get_reg(i_regs->regmap,-1);
3978 int rs=get_reg(i_regs->regmap,rs1[i]);
3979 int rm=get_reg(i_regs->regmap,TLREG);
3982 int c=(i_regs->wasconst>>rs)&1;
3984 // Using r0 as a base address
3986 if(!entry||entry[rm]!=mgr) {
3987 generate_map_const(offset,rm);
3988 } // else did it in the previous cycle
3990 if(!entry||entry[ra]!=agr) {
3991 if (opcode[i]==0x22||opcode[i]==0x26) {
3992 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
3993 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
3994 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
3996 emit_movimm(offset,ra);
3998 } // else did it in the previous cycle
4001 if(!entry||entry[ra]!=rs1[i])
4002 emit_loadreg(rs1[i],ra);
4003 //if(!entry||entry[ra]!=rs1[i])
4004 // printf("poor load scheduling!\n");
4008 if(!entry||entry[rm]!=mgr) {
4009 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a) {
4010 // Stores to memory go thru the mapper to detect self-modifying
4011 // code, loads don't.
4012 if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
4013 (unsigned int)(constmap[i][rs]+offset)<0x80000000+RAM_SIZE )
4014 generate_map_const(constmap[i][rs]+offset,rm);
4016 if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
4017 generate_map_const(constmap[i][rs]+offset,rm);
4021 if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
4022 if(!entry||entry[ra]!=agr) {
4023 if (opcode[i]==0x22||opcode[i]==0x26) {
4024 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4025 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4026 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4028 #ifdef HOST_IMM_ADDR32
4029 if((itype[i]!=LOAD&&(opcode[i]&0x3b)!=0x31&&(opcode[i]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4030 (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
4032 emit_movimm(constmap[i][rs]+offset,ra);
4034 } // else did it in the previous cycle
4035 } // else load_consts already did it
4037 if(offset&&!c&&rs1[i]) {
4039 emit_addimm(rs,offset,ra);
4041 emit_addimm(ra,offset,ra);
4046 // Preload constants for next instruction
4047 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
4049 #ifndef HOST_IMM_ADDR32
4051 agr=MGEN1+((i+1)&1);
4052 ra=get_reg(i_regs->regmap,agr);
4054 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4055 int offset=imm[i+1];
4056 int c=(regs[i+1].wasconst>>rs)&1;
4058 if(itype[i+1]==STORE||itype[i+1]==STORELR
4059 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1, SWC2/SDC2
4060 // Stores to memory go thru the mapper to detect self-modifying
4061 // code, loads don't.
4062 if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
4063 (unsigned int)(constmap[i+1][rs]+offset)<0x80000000+RAM_SIZE )
4064 generate_map_const(constmap[i+1][rs]+offset,ra);
4066 if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
4067 generate_map_const(constmap[i+1][rs]+offset,ra);
4070 /*else if(rs1[i]==0) {
4071 generate_map_const(offset,ra);
4076 agr=AGEN1+((i+1)&1);
4077 ra=get_reg(i_regs->regmap,agr);
4079 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4080 int offset=imm[i+1];
4081 int c=(regs[i+1].wasconst>>rs)&1;
4082 if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
4083 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4084 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4085 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4086 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4088 #ifdef HOST_IMM_ADDR32
4089 if((itype[i+1]!=LOAD&&(opcode[i+1]&0x3b)!=0x31&&(opcode[i+1]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4090 (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000))
4092 emit_movimm(constmap[i+1][rs]+offset,ra);
4095 else if(rs1[i+1]==0) {
4096 // Using r0 as a base address
4097 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4098 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4099 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4100 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4102 emit_movimm(offset,ra);
4109 int get_final_value(int hr, int i, int *value)
4111 int reg=regs[i].regmap[hr];
4113 if(regs[i+1].regmap[hr]!=reg) break;
4114 if(!((regs[i+1].isconst>>hr)&1)) break;
4119 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
4120 *value=constmap[i][hr];
4124 if(itype[i+1]==UJUMP||itype[i+1]==RJUMP||itype[i+1]==CJUMP||itype[i+1]==SJUMP) {
4125 // Load in delay slot, out-of-order execution
4126 if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
4128 #ifdef HOST_IMM_ADDR32
4129 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+2])<(signed int)0xC0000000) return 0;
4131 // Precompute load address
4132 *value=constmap[i][hr]+imm[i+2];
4136 if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)
4138 #ifdef HOST_IMM_ADDR32
4139 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+1])<(signed int)0xC0000000) return 0;
4141 // Precompute load address
4142 *value=constmap[i][hr]+imm[i+1];
4143 //printf("c=%x imm=%x\n",(int)constmap[i][hr],imm[i+1]);
4148 *value=constmap[i][hr];
4149 //printf("c=%x\n",(int)constmap[i][hr]);
4150 if(i==slen-1) return 1;
4152 return !((unneeded_reg[i+1]>>reg)&1);
4154 return !((unneeded_reg_upper[i+1]>>reg)&1);
4158 // Load registers with known constants
4159 void load_consts(signed char pre[],signed char regmap[],int is32,int i)
4163 for(hr=0;hr<HOST_REGS;hr++) {
4164 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4165 //if(entry[hr]!=regmap[hr]) {
4166 if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4167 if(((regs[i].isconst>>hr)&1)&®map[hr]<64&®map[hr]>0) {
4169 if(get_final_value(hr,i,&value)) {
4174 emit_movimm(value,hr);
4182 for(hr=0;hr<HOST_REGS;hr++) {
4183 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4184 //if(entry[hr]!=regmap[hr]) {
4185 if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4186 if(((regs[i].isconst>>hr)&1)&®map[hr]>64) {
4187 if((is32>>(regmap[hr]&63))&1) {
4188 int lr=get_reg(regmap,regmap[hr]-64);
4190 emit_sarimm(lr,31,hr);
4195 if(get_final_value(hr,i,&value)) {
4200 emit_movimm(value,hr);
4209 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i)
4213 for(hr=0;hr<HOST_REGS;hr++) {
4214 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) {
4215 if(((regs[i].isconst>>hr)&1)&®map[hr]<64&®map[hr]>0) {
4216 int value=constmap[i][hr];
4221 emit_movimm(value,hr);
4227 for(hr=0;hr<HOST_REGS;hr++) {
4228 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) {
4229 if(((regs[i].isconst>>hr)&1)&®map[hr]>64) {
4230 if((is32>>(regmap[hr]&63))&1) {
4231 int lr=get_reg(regmap,regmap[hr]-64);
4233 emit_sarimm(lr,31,hr);
4237 int value=constmap[i][hr];
4242 emit_movimm(value,hr);
4250 // Write out all dirty registers (except cycle count)
4251 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty)
4254 for(hr=0;hr<HOST_REGS;hr++) {
4255 if(hr!=EXCLUDE_REG) {
4256 if(i_regmap[hr]>0) {
4257 if(i_regmap[hr]!=CCREG) {
4258 if((i_dirty>>hr)&1) {
4259 if(i_regmap[hr]<64) {
4260 emit_storereg(i_regmap[hr],hr);
4262 if( ((i_is32>>i_regmap[hr])&1) ) {
4263 #ifdef DESTRUCTIVE_WRITEBACK
4264 emit_sarimm(hr,31,hr);
4265 emit_storereg(i_regmap[hr]|64,hr);
4267 emit_sarimm(hr,31,HOST_TEMPREG);
4268 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4273 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4274 emit_storereg(i_regmap[hr],hr);
4283 // Write out dirty registers that we need to reload (pair with load_needed_regs)
4284 // This writes the registers not written by store_regs_bt
4285 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4288 int t=(addr-start)>>2;
4289 for(hr=0;hr<HOST_REGS;hr++) {
4290 if(hr!=EXCLUDE_REG) {
4291 if(i_regmap[hr]>0) {
4292 if(i_regmap[hr]!=CCREG) {
4293 if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1) && !(((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4294 if((i_dirty>>hr)&1) {
4295 if(i_regmap[hr]<64) {
4296 emit_storereg(i_regmap[hr],hr);
4298 if( ((i_is32>>i_regmap[hr])&1) ) {
4299 #ifdef DESTRUCTIVE_WRITEBACK
4300 emit_sarimm(hr,31,hr);
4301 emit_storereg(i_regmap[hr]|64,hr);
4303 emit_sarimm(hr,31,HOST_TEMPREG);
4304 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4309 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4310 emit_storereg(i_regmap[hr],hr);
4321 // Load all registers (except cycle count)
4322 void load_all_regs(signed char i_regmap[])
4325 for(hr=0;hr<HOST_REGS;hr++) {
4326 if(hr!=EXCLUDE_REG) {
4327 if(i_regmap[hr]==0) {
4331 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG)
4333 emit_loadreg(i_regmap[hr],hr);
4339 // Load all current registers also needed by next instruction
4340 void load_needed_regs(signed char i_regmap[],signed char next_regmap[])
4343 for(hr=0;hr<HOST_REGS;hr++) {
4344 if(hr!=EXCLUDE_REG) {
4345 if(get_reg(next_regmap,i_regmap[hr])>=0) {
4346 if(i_regmap[hr]==0) {
4350 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG)
4352 emit_loadreg(i_regmap[hr],hr);
4359 // Load all regs, storing cycle count if necessary
4360 void load_regs_entry(int t)
4363 if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER,HOST_CCREG);
4364 else if(ccadj[t]) emit_addimm(HOST_CCREG,-ccadj[t]*CLOCK_DIVIDER,HOST_CCREG);
4365 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4366 emit_storereg(CCREG,HOST_CCREG);
4369 for(hr=0;hr<HOST_REGS;hr++) {
4370 if(regs[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<64) {
4371 if(regs[t].regmap_entry[hr]==0) {
4374 else if(regs[t].regmap_entry[hr]!=CCREG)
4376 emit_loadreg(regs[t].regmap_entry[hr],hr);
4381 for(hr=0;hr<HOST_REGS;hr++) {
4382 if(regs[t].regmap_entry[hr]>=64) {
4383 assert(regs[t].regmap_entry[hr]!=64);
4384 if((regs[t].was32>>(regs[t].regmap_entry[hr]&63))&1) {
4385 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4387 emit_loadreg(regs[t].regmap_entry[hr],hr);
4391 emit_sarimm(lr,31,hr);
4396 emit_loadreg(regs[t].regmap_entry[hr],hr);
4402 // Store dirty registers prior to branch
4403 void store_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4405 if(internal_branch(i_is32,addr))
4407 int t=(addr-start)>>2;
4409 for(hr=0;hr<HOST_REGS;hr++) {
4410 if(hr!=EXCLUDE_REG) {
4411 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4412 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4413 if((i_dirty>>hr)&1) {
4414 if(i_regmap[hr]<64) {
4415 if(!((unneeded_reg[t]>>i_regmap[hr])&1)) {
4416 emit_storereg(i_regmap[hr],hr);
4417 if( ((i_is32>>i_regmap[hr])&1) && !((unneeded_reg_upper[t]>>i_regmap[hr])&1) ) {
4418 #ifdef DESTRUCTIVE_WRITEBACK
4419 emit_sarimm(hr,31,hr);
4420 emit_storereg(i_regmap[hr]|64,hr);
4422 emit_sarimm(hr,31,HOST_TEMPREG);
4423 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4428 if( !((i_is32>>(i_regmap[hr]&63))&1) && !((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1) ) {
4429 emit_storereg(i_regmap[hr],hr);
4440 // Branch out of this block, write out all dirty regs
4441 wb_dirtys(i_regmap,i_is32,i_dirty);
4445 // Load all needed registers for branch target
4446 void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4448 //if(addr>=start && addr<(start+slen*4))
4449 if(internal_branch(i_is32,addr))
4451 int t=(addr-start)>>2;
4453 // Store the cycle count before loading something else
4454 if(i_regmap[HOST_CCREG]!=CCREG) {
4455 assert(i_regmap[HOST_CCREG]==-1);
4457 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4458 emit_storereg(CCREG,HOST_CCREG);
4461 for(hr=0;hr<HOST_REGS;hr++) {
4462 if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<64) {
4463 #ifdef DESTRUCTIVE_WRITEBACK
4464 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || ( !((regs[t].dirty>>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4466 if(i_regmap[hr]!=regs[t].regmap_entry[hr] ) {
4468 if(regs[t].regmap_entry[hr]==0) {
4471 else if(regs[t].regmap_entry[hr]!=CCREG)
4473 emit_loadreg(regs[t].regmap_entry[hr],hr);
4479 for(hr=0;hr<HOST_REGS;hr++) {
4480 if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=64) {
4481 if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4482 assert(regs[t].regmap_entry[hr]!=64);
4483 if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4484 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4486 emit_loadreg(regs[t].regmap_entry[hr],hr);
4490 emit_sarimm(lr,31,hr);
4495 emit_loadreg(regs[t].regmap_entry[hr],hr);
4498 else if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4499 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4501 emit_sarimm(lr,31,hr);
4508 int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4510 if(addr>=start && addr<start+slen*4-4)
4512 int t=(addr-start)>>2;
4514 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4515 for(hr=0;hr<HOST_REGS;hr++)
4519 if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4521 if(regs[t].regmap_entry[hr]!=-1)
4530 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4535 if(!((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1))
4540 else // Same register but is it 32-bit or dirty?
4543 if(!((regs[t].dirty>>hr)&1))
4547 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4549 //printf("%x: dirty no match\n",addr);
4554 if((((regs[t].was32^i_is32)&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)
4556 //printf("%x: is32 no match\n",addr);
4562 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4563 if(requires_32bit[t]&~i_is32) return 0;
4564 // Delay slots are not valid branch targets
4565 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4566 // Delay slots require additional processing, so do not match
4567 if(is_ds[t]) return 0;
4572 for(hr=0;hr<HOST_REGS;hr++)
4578 if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4592 // Used when a branch jumps into the delay slot of another branch
4593 void ds_assemble_entry(int i)
4595 int t=(ba[i]-start)>>2;
4596 if(!instr_addr[t]) instr_addr[t]=(u_int)out;
4597 assem_debug("Assemble delay slot at %x\n",ba[i]);
4598 assem_debug("<->\n");
4599 if(regs[t].regmap_entry[HOST_CCREG]==CCREG&®s[t].regmap[HOST_CCREG]!=CCREG)
4600 wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty,regs[t].was32);
4601 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,rs1[t],rs2[t]);
4602 address_generation(t,®s[t],regs[t].regmap_entry);
4603 if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39||(opcode[t]&0x3b)==0x3a)
4604 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,INVCP,INVCP);
4609 alu_assemble(t,®s[t]);break;
4611 imm16_assemble(t,®s[t]);break;
4613 shift_assemble(t,®s[t]);break;
4615 shiftimm_assemble(t,®s[t]);break;
4617 load_assemble(t,®s[t]);break;
4619 loadlr_assemble(t,®s[t]);break;
4621 store_assemble(t,®s[t]);break;
4623 storelr_assemble(t,®s[t]);break;
4625 cop0_assemble(t,®s[t]);break;
4627 cop1_assemble(t,®s[t]);break;
4629 c1ls_assemble(t,®s[t]);break;
4631 cop2_assemble(t,®s[t]);break;
4633 c2ls_assemble(t,®s[t]);break;
4635 c2op_assemble(t,®s[t]);break;
4637 fconv_assemble(t,®s[t]);break;
4639 float_assemble(t,®s[t]);break;
4641 fcomp_assemble(t,®s[t]);break;
4643 multdiv_assemble(t,®s[t]);break;
4645 mov_assemble(t,®s[t]);break;
4654 printf("Jump in the delay slot. This is probably a bug.\n");
4656 store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4657 load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4658 if(internal_branch(regs[t].is32,ba[i]+4))
4659 assem_debug("branch: internal\n");
4661 assem_debug("branch: external\n");
4662 assert(internal_branch(regs[t].is32,ba[i]+4));
4663 add_to_linker((int)out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4));
4667 void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
4676 //if(ba[i]>=start && ba[i]<(start+slen*4))
4677 if(internal_branch(branch_regs[i].is32,ba[i]))
4679 int t=(ba[i]-start)>>2;
4680 if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
4688 if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4690 if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
4692 //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4693 emit_andimm(HOST_CCREG,3,HOST_CCREG);
4697 else if(*adj==0||invert) {
4698 emit_addimm_and_set_flags(CLOCK_DIVIDER*(count+2),HOST_CCREG);
4704 emit_cmpimm(HOST_CCREG,-2*(count+2));
4708 add_stub(CC_STUB,jaddr,idle?idle:(int)out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
4711 void do_ccstub(int n)
4714 assem_debug("do_ccstub %x\n",start+stubs[n][4]*4);
4715 set_jump_target(stubs[n][1],(int)out);
4717 if(stubs[n][6]==NULLDS) {
4718 // Delay slot instruction is nullified ("likely" branch)
4719 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
4721 else if(stubs[n][6]!=TAKEN) {
4722 wb_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty);
4725 if(internal_branch(branch_regs[i].is32,ba[i]))
4726 wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4730 // Save PC as return address
4731 emit_movimm(stubs[n][5],EAX);
4732 emit_writeword(EAX,(int)&pcaddr);
4736 // Return address depends on which way the branch goes
4737 if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
4739 int s1l=get_reg(branch_regs[i].regmap,rs1[i]);
4740 int s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
4741 int s2l=get_reg(branch_regs[i].regmap,rs2[i]);
4742 int s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
4752 if((branch_regs[i].is32>>rs1[i])&(branch_regs[i].is32>>rs2[i])&1) {
4756 #ifdef DESTRUCTIVE_WRITEBACK
4758 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1)
4759 emit_loadreg(rs1[i],s1l);
4762 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1)
4763 emit_loadreg(rs2[i],s1l);
4766 if((branch_regs[i].dirty>>s2l)&(branch_regs[i].is32>>rs2[i])&1)
4767 emit_loadreg(rs2[i],s2l);
4770 int addr,alt,ntaddr;
4773 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4774 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4775 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4783 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4784 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4785 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4791 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
4795 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4796 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4797 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4803 assert(hr<HOST_REGS);
4805 if((opcode[i]&0x2f)==4) // BEQ
4807 #ifdef HAVE_CMOV_IMM
4809 if(s2l>=0) emit_cmp(s1l,s2l);
4810 else emit_test(s1l,s1l);
4811 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
4816 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4818 if(s2h>=0) emit_cmp(s1h,s2h);
4819 else emit_test(s1h,s1h);
4820 emit_cmovne_reg(alt,addr);
4822 if(s2l>=0) emit_cmp(s1l,s2l);
4823 else emit_test(s1l,s1l);
4824 emit_cmovne_reg(alt,addr);
4827 if((opcode[i]&0x2f)==5) // BNE
4829 #ifdef HAVE_CMOV_IMM
4831 if(s2l>=0) emit_cmp(s1l,s2l);
4832 else emit_test(s1l,s1l);
4833 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
4838 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
4840 if(s2h>=0) emit_cmp(s1h,s2h);
4841 else emit_test(s1h,s1h);
4842 emit_cmovne_reg(alt,addr);
4844 if(s2l>=0) emit_cmp(s1l,s2l);
4845 else emit_test(s1l,s1l);
4846 emit_cmovne_reg(alt,addr);
4849 if((opcode[i]&0x2f)==6) // BLEZ
4851 //emit_movimm(ba[i],alt);
4852 //emit_movimm(start+i*4+8,addr);
4853 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4855 if(s1h>=0) emit_mov(addr,ntaddr);
4856 emit_cmovl_reg(alt,addr);
4859 emit_cmovne_reg(ntaddr,addr);
4860 emit_cmovs_reg(alt,addr);
4863 if((opcode[i]&0x2f)==7) // BGTZ
4865 //emit_movimm(ba[i],addr);
4866 //emit_movimm(start+i*4+8,ntaddr);
4867 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
4869 if(s1h>=0) emit_mov(addr,alt);
4870 emit_cmovl_reg(ntaddr,addr);
4873 emit_cmovne_reg(alt,addr);
4874 emit_cmovs_reg(ntaddr,addr);
4877 if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ
4879 //emit_movimm(ba[i],alt);
4880 //emit_movimm(start+i*4+8,addr);
4881 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4882 if(s1h>=0) emit_test(s1h,s1h);
4883 else emit_test(s1l,s1l);
4884 emit_cmovs_reg(alt,addr);
4886 if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ
4888 //emit_movimm(ba[i],addr);
4889 //emit_movimm(start+i*4+8,alt);
4890 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4891 if(s1h>=0) emit_test(s1h,s1h);
4892 else emit_test(s1l,s1l);
4893 emit_cmovs_reg(alt,addr);
4895 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
4896 if(source[i]&0x10000) // BC1T
4898 //emit_movimm(ba[i],alt);
4899 //emit_movimm(start+i*4+8,addr);
4900 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4901 emit_testimm(s1l,0x800000);
4902 emit_cmovne_reg(alt,addr);
4906 //emit_movimm(ba[i],addr);
4907 //emit_movimm(start+i*4+8,alt);
4908 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4909 emit_testimm(s1l,0x800000);
4910 emit_cmovne_reg(alt,addr);
4913 emit_writeword(addr,(int)&pcaddr);
4918 int r=get_reg(branch_regs[i].regmap,rs1[i]);
4919 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
4920 r=get_reg(branch_regs[i].regmap,RTEMP);
4922 emit_writeword(r,(int)&pcaddr);
4924 else {printf("Unknown branch type in do_ccstub\n");exit(1);}
4926 // Update cycle count
4927 assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
4928 if(stubs[n][3]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
4929 emit_call((int)cc_interrupt);
4930 if(stubs[n][3]) emit_addimm(HOST_CCREG,-CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
4931 if(stubs[n][6]==TAKEN) {
4932 if(internal_branch(branch_regs[i].is32,ba[i]))
4933 load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
4934 else if(itype[i]==RJUMP) {
4935 if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
4936 emit_readword((int)&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
4938 emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i]));
4940 }else if(stubs[n][6]==NOTTAKEN) {
4941 if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
4942 else load_all_regs(branch_regs[i].regmap);
4943 }else if(stubs[n][6]==NULLDS) {
4944 // Delay slot instruction is nullified ("likely" branch)
4945 if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
4946 else load_all_regs(regs[i].regmap);
4948 load_all_regs(branch_regs[i].regmap);
4950 emit_jmp(stubs[n][2]); // return address
4952 /* This works but uses a lot of memory...
4953 emit_readword((int)&last_count,ECX);
4954 emit_add(HOST_CCREG,ECX,EAX);
4955 emit_writeword(EAX,(int)&Count);
4956 emit_call((int)gen_interupt);
4957 emit_readword((int)&Count,HOST_CCREG);
4958 emit_readword((int)&next_interupt,EAX);
4959 emit_readword((int)&pending_exception,EBX);
4960 emit_writeword(EAX,(int)&last_count);
4961 emit_sub(HOST_CCREG,EAX,HOST_CCREG);
4963 int jne_instr=(int)out;
4965 if(stubs[n][3]) emit_addimm(HOST_CCREG,-2*stubs[n][3],HOST_CCREG);
4966 load_all_regs(branch_regs[i].regmap);
4967 emit_jmp(stubs[n][2]); // return address
4968 set_jump_target(jne_instr,(int)out);
4969 emit_readword((int)&pcaddr,EAX);
4970 // Call get_addr_ht instead of doing the hash table here.
4971 // This code is executed infrequently and takes up a lot of space
4972 // so smaller is better.
4973 emit_storereg(CCREG,HOST_CCREG);
4975 emit_call((int)get_addr_ht);
4976 emit_loadreg(CCREG,HOST_CCREG);
4977 emit_addimm(ESP,4,ESP);
4981 add_to_linker(int addr,int target,int ext)
4983 link_addr[linkcount][0]=addr;
4984 link_addr[linkcount][1]=target;
4985 link_addr[linkcount][2]=ext;
4989 void ujump_assemble(int i,struct regstat *i_regs)
4991 signed char *i_regmap=i_regs->regmap;
4992 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
4993 address_generation(i+1,i_regs,regs[i].regmap_entry);
4995 int temp=get_reg(branch_regs[i].regmap,PTEMP);
4996 if(rt1[i]==31&&temp>=0)
4998 int return_address=start+i*4+8;
4999 if(get_reg(branch_regs[i].regmap,31)>0)
5000 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5003 ds_assemble(i+1,i_regs);
5004 uint64_t bc_unneeded=branch_regs[i].u;
5005 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5006 bc_unneeded|=1|(1LL<<rt1[i]);
5007 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5008 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5009 bc_unneeded,bc_unneeded_upper);
5010 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5013 unsigned int return_address;
5014 assert(rt1[i+1]!=31);
5015 assert(rt2[i+1]!=31);
5016 rt=get_reg(branch_regs[i].regmap,31);
5017 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5019 return_address=start+i*4+8;
5022 if(internal_branch(branch_regs[i].is32,return_address)) {
5024 if(temp==EXCLUDE_REG||temp>=HOST_REGS||
5025 branch_regs[i].regmap[temp]>=0)
5027 temp=get_reg(branch_regs[i].regmap,-1);
5030 if(temp<0) temp=HOST_TEMPREG;
5032 if(temp>=0) do_miniht_insert(return_address,rt,temp);
5033 else emit_movimm(return_address,rt);
5041 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5044 emit_movimm(return_address,rt); // PC into link register
5046 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5052 cc=get_reg(branch_regs[i].regmap,CCREG);
5053 assert(cc==HOST_CCREG);
5054 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5056 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5058 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5059 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5060 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5061 if(internal_branch(branch_regs[i].is32,ba[i]))
5062 assem_debug("branch: internal\n");
5064 assem_debug("branch: external\n");
5065 if(internal_branch(branch_regs[i].is32,ba[i])&&is_ds[(ba[i]-start)>>2]) {
5066 ds_assemble_entry(i);
5069 add_to_linker((int)out,ba[i],internal_branch(branch_regs[i].is32,ba[i]));
5074 void rjump_assemble(int i,struct regstat *i_regs)
5076 signed char *i_regmap=i_regs->regmap;
5079 rs=get_reg(branch_regs[i].regmap,rs1[i]);
5081 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5082 // Delay slot abuse, make a copy of the branch address register
5083 temp=get_reg(branch_regs[i].regmap,RTEMP);
5085 assert(regs[i].regmap[temp]==RTEMP);
5089 address_generation(i+1,i_regs,regs[i].regmap_entry);
5093 if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5094 int return_address=start+i*4+8;
5095 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5101 int rh=get_reg(regs[i].regmap,RHASH);
5102 if(rh>=0) do_preload_rhash(rh);
5105 ds_assemble(i+1,i_regs);
5106 uint64_t bc_unneeded=branch_regs[i].u;
5107 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5108 bc_unneeded|=1|(1LL<<rt1[i]);
5109 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5110 bc_unneeded&=~(1LL<<rs1[i]);
5111 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5112 bc_unneeded,bc_unneeded_upper);
5113 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
5115 int rt,return_address;
5116 assert(rt1[i+1]!=rt1[i]);
5117 assert(rt2[i+1]!=rt1[i]);
5118 rt=get_reg(branch_regs[i].regmap,rt1[i]);
5119 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5121 return_address=start+i*4+8;
5125 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5128 emit_movimm(return_address,rt); // PC into link register
5130 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5133 cc=get_reg(branch_regs[i].regmap,CCREG);
5134 assert(cc==HOST_CCREG);
5136 int rh=get_reg(branch_regs[i].regmap,RHASH);
5137 int ht=get_reg(branch_regs[i].regmap,RHTBL);
5139 if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5140 do_preload_rhtbl(ht);
5144 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5145 #ifdef DESTRUCTIVE_WRITEBACK
5146 if((branch_regs[i].dirty>>rs)&(branch_regs[i].is32>>rs1[i])&1) {
5147 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
5148 emit_loadreg(rs1[i],rs);
5153 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5157 do_miniht_load(ht,rh);
5160 //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5161 //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5163 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5164 add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
5166 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5169 do_miniht_jump(rs,rh,ht);
5174 //if(rs!=EAX) emit_mov(rs,EAX);
5175 //emit_jmp((int)jump_vaddr_eax);
5176 emit_jmp(jump_vaddr_reg[rs]);
5181 emit_shrimm(rs,16,rs);
5182 emit_xor(temp,rs,rs);
5183 emit_movzwl_reg(rs,rs);
5184 emit_shlimm(rs,4,rs);
5185 emit_cmpmem_indexed((int)hash_table,rs,temp);
5186 emit_jne((int)out+14);
5187 emit_readword_indexed((int)hash_table+4,rs,rs);
5189 emit_cmpmem_indexed((int)hash_table+8,rs,temp);
5190 emit_addimm_no_flags(8,rs);
5191 emit_jeq((int)out-17);
5192 // No hit on hash table, call compiler
5195 #ifdef DEBUG_CYCLE_COUNT
5196 emit_readword((int)&last_count,ECX);
5197 emit_add(HOST_CCREG,ECX,HOST_CCREG);
5198 emit_readword((int)&next_interupt,ECX);
5199 emit_writeword(HOST_CCREG,(int)&Count);
5200 emit_sub(HOST_CCREG,ECX,HOST_CCREG);
5201 emit_writeword(ECX,(int)&last_count);
5204 emit_storereg(CCREG,HOST_CCREG);
5205 emit_call((int)get_addr);
5206 emit_loadreg(CCREG,HOST_CCREG);
5207 emit_addimm(ESP,4,ESP);
5209 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5210 if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5214 void cjump_assemble(int i,struct regstat *i_regs)
5216 signed char *i_regmap=i_regs->regmap;
5219 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5220 assem_debug("match=%d\n",match);
5221 int s1h,s1l,s2h,s2l;
5222 int prev_cop1_usable=cop1_usable;
5223 int unconditional=0,nop=0;
5227 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5228 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5229 if(likely[i]) ooo=0;
5230 if(!match) invert=1;
5231 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5232 if(i>(ba[i]-start)>>2) invert=1;
5236 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
5237 (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1])))
5239 // Write-after-read dependency prevents out of order execution
5240 // First test branch condition, then execute delay slot, then branch
5245 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5246 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5247 s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5248 s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5251 s1l=get_reg(i_regmap,rs1[i]);
5252 s1h=get_reg(i_regmap,rs1[i]|64);
5253 s2l=get_reg(i_regmap,rs2[i]);
5254 s2h=get_reg(i_regmap,rs2[i]|64);
5256 if(rs1[i]==0&&rs2[i]==0)
5258 if(opcode[i]&1) nop=1;
5259 else unconditional=1;
5260 //assert(opcode[i]!=5);
5261 //assert(opcode[i]!=7);
5262 //assert(opcode[i]!=0x15);
5263 //assert(opcode[i]!=0x17);
5269 only32=(regs[i].was32>>rs2[i])&1;
5274 only32=(regs[i].was32>>rs1[i])&1;
5277 only32=(regs[i].was32>>rs1[i])&(regs[i].was32>>rs2[i])&1;
5281 // Out of order execution (delay slot first)
5283 address_generation(i+1,i_regs,regs[i].regmap_entry);
5284 ds_assemble(i+1,i_regs);
5286 uint64_t bc_unneeded=branch_regs[i].u;
5287 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5288 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5289 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5291 bc_unneeded_upper|=1;
5292 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5293 bc_unneeded,bc_unneeded_upper);
5294 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
5295 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5296 cc=get_reg(branch_regs[i].regmap,CCREG);
5297 assert(cc==HOST_CCREG);
5299 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5300 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5301 //assem_debug("cycle count (adj)\n");
5303 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5304 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5305 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5306 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5308 assem_debug("branch: internal\n");
5310 assem_debug("branch: external\n");
5311 if(internal&&is_ds[(ba[i]-start)>>2]) {
5312 ds_assemble_entry(i);
5315 add_to_linker((int)out,ba[i],internal);
5318 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5319 if(((u_int)out)&7) emit_addnop(0);
5324 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5327 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5330 int taken=0,nottaken=0,nottaken1=0;
5331 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5332 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5336 if(opcode[i]==4) // BEQ
5338 if(s2h>=0) emit_cmp(s1h,s2h);
5339 else emit_test(s1h,s1h);
5343 if(opcode[i]==5) // BNE
5345 if(s2h>=0) emit_cmp(s1h,s2h);
5346 else emit_test(s1h,s1h);
5347 if(invert) taken=(int)out;
5348 else add_to_linker((int)out,ba[i],internal);
5351 if(opcode[i]==6) // BLEZ
5354 if(invert) taken=(int)out;
5355 else add_to_linker((int)out,ba[i],internal);
5360 if(opcode[i]==7) // BGTZ
5365 if(invert) taken=(int)out;
5366 else add_to_linker((int)out,ba[i],internal);
5371 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5373 if(opcode[i]==4) // BEQ
5375 if(s2l>=0) emit_cmp(s1l,s2l);
5376 else emit_test(s1l,s1l);
5381 add_to_linker((int)out,ba[i],internal);
5385 if(opcode[i]==5) // BNE
5387 if(s2l>=0) emit_cmp(s1l,s2l);
5388 else emit_test(s1l,s1l);
5393 add_to_linker((int)out,ba[i],internal);
5397 if(opcode[i]==6) // BLEZ
5404 add_to_linker((int)out,ba[i],internal);
5408 if(opcode[i]==7) // BGTZ
5415 add_to_linker((int)out,ba[i],internal);
5420 if(taken) set_jump_target(taken,(int)out);
5421 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5422 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5424 emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5425 add_to_linker((int)out,ba[i],internal);
5428 add_to_linker((int)out,ba[i],internal*2);
5434 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5435 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5436 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5438 assem_debug("branch: internal\n");
5440 assem_debug("branch: external\n");
5441 if(internal&&is_ds[(ba[i]-start)>>2]) {
5442 ds_assemble_entry(i);
5445 add_to_linker((int)out,ba[i],internal);
5449 set_jump_target(nottaken,(int)out);
5452 if(nottaken1) set_jump_target(nottaken1,(int)out);
5454 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5456 } // (!unconditional)
5460 // In-order execution (branch first)
5461 //if(likely[i]) printf("IOL\n");
5464 int taken=0,nottaken=0,nottaken1=0;
5465 if(!unconditional&&!nop) {
5469 if((opcode[i]&0x2f)==4) // BEQ
5471 if(s2h>=0) emit_cmp(s1h,s2h);
5472 else emit_test(s1h,s1h);
5476 if((opcode[i]&0x2f)==5) // BNE
5478 if(s2h>=0) emit_cmp(s1h,s2h);
5479 else emit_test(s1h,s1h);
5483 if((opcode[i]&0x2f)==6) // BLEZ
5491 if((opcode[i]&0x2f)==7) // BGTZ
5501 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5503 if((opcode[i]&0x2f)==4) // BEQ
5505 if(s2l>=0) emit_cmp(s1l,s2l);
5506 else emit_test(s1l,s1l);
5510 if((opcode[i]&0x2f)==5) // BNE
5512 if(s2l>=0) emit_cmp(s1l,s2l);
5513 else emit_test(s1l,s1l);
5517 if((opcode[i]&0x2f)==6) // BLEZ
5523 if((opcode[i]&0x2f)==7) // BGTZ
5529 } // if(!unconditional)
5531 uint64_t ds_unneeded=branch_regs[i].u;
5532 uint64_t ds_unneeded_upper=branch_regs[i].uu;
5533 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5534 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5535 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5537 ds_unneeded_upper|=1;
5540 if(taken) set_jump_target(taken,(int)out);
5541 assem_debug("1:\n");
5542 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5543 ds_unneeded,ds_unneeded_upper);
5545 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5546 address_generation(i+1,&branch_regs[i],0);
5547 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5548 ds_assemble(i+1,&branch_regs[i]);
5549 cc=get_reg(branch_regs[i].regmap,CCREG);
5551 emit_loadreg(CCREG,cc=HOST_CCREG);
5552 // CHECK: Is the following instruction (fall thru) allocated ok?
5554 assert(cc==HOST_CCREG);
5555 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5556 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5557 assem_debug("cycle count (adj)\n");
5558 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5559 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5561 assem_debug("branch: internal\n");
5563 assem_debug("branch: external\n");
5564 if(internal&&is_ds[(ba[i]-start)>>2]) {
5565 ds_assemble_entry(i);
5568 add_to_linker((int)out,ba[i],internal);
5573 cop1_usable=prev_cop1_usable;
5574 if(!unconditional) {
5575 if(nottaken1) set_jump_target(nottaken1,(int)out);
5576 set_jump_target(nottaken,(int)out);
5577 assem_debug("2:\n");
5579 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5580 ds_unneeded,ds_unneeded_upper);
5581 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5582 address_generation(i+1,&branch_regs[i],0);
5583 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5584 ds_assemble(i+1,&branch_regs[i]);
5586 cc=get_reg(branch_regs[i].regmap,CCREG);
5587 if(cc==-1&&!likely[i]) {
5588 // Cycle count isn't in a register, temporarily load it then write it out
5589 emit_loadreg(CCREG,HOST_CCREG);
5590 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5593 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5594 emit_storereg(CCREG,HOST_CCREG);
5597 cc=get_reg(i_regmap,CCREG);
5598 assert(cc==HOST_CCREG);
5599 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5602 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5608 void sjump_assemble(int i,struct regstat *i_regs)
5610 signed char *i_regmap=i_regs->regmap;
5613 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5614 assem_debug("smatch=%d\n",match);
5616 int prev_cop1_usable=cop1_usable;
5617 int unconditional=0,nevertaken=0;
5621 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5622 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5623 if(likely[i]) ooo=0;
5624 if(!match) invert=1;
5625 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5626 if(i>(ba[i]-start)>>2) invert=1;
5629 //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
5630 //assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
5633 if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))
5635 // Write-after-read dependency prevents out of order execution
5636 // First test branch condition, then execute delay slot, then branch
5639 assert(opcode2[i]<0x10||ooo); // FIXME (BxxZALL)
5642 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5643 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5646 s1l=get_reg(i_regmap,rs1[i]);
5647 s1h=get_reg(i_regmap,rs1[i]|64);
5651 if(opcode2[i]&1) unconditional=1;
5653 // These are never taken (r0 is never less than zero)
5654 //assert(opcode2[i]!=0);
5655 //assert(opcode2[i]!=2);
5656 //assert(opcode2[i]!=0x10);
5657 //assert(opcode2[i]!=0x12);
5660 only32=(regs[i].was32>>rs1[i])&1;
5664 // Out of order execution (delay slot first)
5666 address_generation(i+1,i_regs,regs[i].regmap_entry);
5667 ds_assemble(i+1,i_regs);
5669 uint64_t bc_unneeded=branch_regs[i].u;
5670 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5671 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5672 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5674 bc_unneeded_upper|=1;
5675 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5676 bc_unneeded,bc_unneeded_upper);
5677 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5678 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5680 int rt,return_address;
5681 assert(rt1[i+1]!=31);
5682 assert(rt2[i+1]!=31);
5683 rt=get_reg(branch_regs[i].regmap,31);
5684 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5686 // Save the PC even if the branch is not taken
5687 return_address=start+i*4+8;
5688 emit_movimm(return_address,rt); // PC into link register
5690 if(!nevertaken) emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5694 cc=get_reg(branch_regs[i].regmap,CCREG);
5695 assert(cc==HOST_CCREG);
5697 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5698 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5699 assem_debug("cycle count (adj)\n");
5701 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5702 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5703 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5704 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5706 assem_debug("branch: internal\n");
5708 assem_debug("branch: external\n");
5709 if(internal&&is_ds[(ba[i]-start)>>2]) {
5710 ds_assemble_entry(i);
5713 add_to_linker((int)out,ba[i],internal);
5716 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5717 if(((u_int)out)&7) emit_addnop(0);
5721 else if(nevertaken) {
5722 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5725 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5729 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5730 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5734 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
5741 add_to_linker((int)out,ba[i],internal);
5745 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
5752 add_to_linker((int)out,ba[i],internal);
5760 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
5767 add_to_linker((int)out,ba[i],internal);
5771 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
5778 add_to_linker((int)out,ba[i],internal);
5785 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5786 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5788 emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5789 add_to_linker((int)out,ba[i],internal);
5792 add_to_linker((int)out,ba[i],internal*2);
5798 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5799 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5800 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5802 assem_debug("branch: internal\n");
5804 assem_debug("branch: external\n");
5805 if(internal&&is_ds[(ba[i]-start)>>2]) {
5806 ds_assemble_entry(i);
5809 add_to_linker((int)out,ba[i],internal);
5813 set_jump_target(nottaken,(int)out);
5817 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5819 } // (!unconditional)
5823 // In-order execution (branch first)
5826 if(!unconditional) {
5827 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5831 if((opcode2[i]&0x1d)==0) // BLTZ/BLTZL
5837 if((opcode2[i]&0x1d)==1) // BGEZ/BGEZL
5847 if((opcode2[i]&0x1d)==0) // BLTZ/BLTZL
5853 if((opcode2[i]&0x1d)==1) // BGEZ/BGEZL
5860 } // if(!unconditional)
5862 uint64_t ds_unneeded=branch_regs[i].u;
5863 uint64_t ds_unneeded_upper=branch_regs[i].uu;
5864 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5865 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5866 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5868 ds_unneeded_upper|=1;
5871 //assem_debug("1:\n");
5872 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5873 ds_unneeded,ds_unneeded_upper);
5875 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5876 address_generation(i+1,&branch_regs[i],0);
5877 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5878 ds_assemble(i+1,&branch_regs[i]);
5879 cc=get_reg(branch_regs[i].regmap,CCREG);
5881 emit_loadreg(CCREG,cc=HOST_CCREG);
5882 // CHECK: Is the following instruction (fall thru) allocated ok?
5884 assert(cc==HOST_CCREG);
5885 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5886 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5887 assem_debug("cycle count (adj)\n");
5888 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5889 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5891 assem_debug("branch: internal\n");
5893 assem_debug("branch: external\n");
5894 if(internal&&is_ds[(ba[i]-start)>>2]) {
5895 ds_assemble_entry(i);
5898 add_to_linker((int)out,ba[i],internal);
5903 cop1_usable=prev_cop1_usable;
5904 if(!unconditional) {
5905 set_jump_target(nottaken,(int)out);
5906 assem_debug("1:\n");
5908 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5909 ds_unneeded,ds_unneeded_upper);
5910 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5911 address_generation(i+1,&branch_regs[i],0);
5912 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5913 ds_assemble(i+1,&branch_regs[i]);
5915 cc=get_reg(branch_regs[i].regmap,CCREG);
5916 if(cc==-1&&!likely[i]) {
5917 // Cycle count isn't in a register, temporarily load it then write it out
5918 emit_loadreg(CCREG,HOST_CCREG);
5919 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5922 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5923 emit_storereg(CCREG,HOST_CCREG);
5926 cc=get_reg(i_regmap,CCREG);
5927 assert(cc==HOST_CCREG);
5928 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5931 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5937 void fjump_assemble(int i,struct regstat *i_regs)
5939 signed char *i_regmap=i_regs->regmap;
5942 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5943 assem_debug("fmatch=%d\n",match);
5948 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5949 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5950 if(likely[i]) ooo=0;
5951 if(!match) invert=1;
5952 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5953 if(i>(ba[i]-start)>>2) invert=1;
5957 if(itype[i+1]==FCOMP)
5959 // Write-after-read dependency prevents out of order execution
5960 // First test branch condition, then execute delay slot, then branch
5965 fs=get_reg(branch_regs[i].regmap,FSREG);
5966 address_generation(i+1,i_regs,regs[i].regmap_entry); // Is this okay?
5969 fs=get_reg(i_regmap,FSREG);
5972 // Check cop1 unusable
5974 cs=get_reg(i_regmap,CSREG);
5976 emit_testimm(cs,0x20000000);
5979 add_stub(FP_STUB,eaddr,(int)out,i,cs,(int)i_regs,0,0);
5984 // Out of order execution (delay slot first)
5986 ds_assemble(i+1,i_regs);
5988 uint64_t bc_unneeded=branch_regs[i].u;
5989 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5990 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5991 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5993 bc_unneeded_upper|=1;
5994 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5995 bc_unneeded,bc_unneeded_upper);
5996 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5997 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5998 cc=get_reg(branch_regs[i].regmap,CCREG);
5999 assert(cc==HOST_CCREG);
6000 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
6001 assem_debug("cycle count (adj)\n");
6004 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6007 emit_testimm(fs,0x800000);
6008 if(source[i]&0x10000) // BC1T
6014 add_to_linker((int)out,ba[i],internal);
6023 add_to_linker((int)out,ba[i],internal);
6031 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
6032 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6033 else if(match) emit_addnop(13);
6035 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6036 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6038 assem_debug("branch: internal\n");
6040 assem_debug("branch: external\n");
6041 if(internal&&is_ds[(ba[i]-start)>>2]) {
6042 ds_assemble_entry(i);
6045 add_to_linker((int)out,ba[i],internal);
6048 set_jump_target(nottaken,(int)out);
6052 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
6054 } // (!unconditional)
6058 // In-order execution (branch first)
6062 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6065 emit_testimm(fs,0x800000);
6066 if(source[i]&0x10000) // BC1T
6077 } // if(!unconditional)
6079 uint64_t ds_unneeded=branch_regs[i].u;
6080 uint64_t ds_unneeded_upper=branch_regs[i].uu;
6081 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6082 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6083 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6085 ds_unneeded_upper|=1;
6087 //assem_debug("1:\n");
6088 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6089 ds_unneeded,ds_unneeded_upper);
6091 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6092 address_generation(i+1,&branch_regs[i],0);
6093 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6094 ds_assemble(i+1,&branch_regs[i]);
6095 cc=get_reg(branch_regs[i].regmap,CCREG);
6097 emit_loadreg(CCREG,cc=HOST_CCREG);
6098 // CHECK: Is the following instruction (fall thru) allocated ok?
6100 assert(cc==HOST_CCREG);
6101 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6102 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6103 assem_debug("cycle count (adj)\n");
6104 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6105 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6107 assem_debug("branch: internal\n");
6109 assem_debug("branch: external\n");
6110 if(internal&&is_ds[(ba[i]-start)>>2]) {
6111 ds_assemble_entry(i);
6114 add_to_linker((int)out,ba[i],internal);
6119 if(1) { // <- FIXME (don't need this)
6120 set_jump_target(nottaken,(int)out);
6121 assem_debug("1:\n");
6123 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6124 ds_unneeded,ds_unneeded_upper);
6125 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6126 address_generation(i+1,&branch_regs[i],0);
6127 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6128 ds_assemble(i+1,&branch_regs[i]);
6130 cc=get_reg(branch_regs[i].regmap,CCREG);
6131 if(cc==-1&&!likely[i]) {
6132 // Cycle count isn't in a register, temporarily load it then write it out
6133 emit_loadreg(CCREG,HOST_CCREG);
6134 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6137 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6138 emit_storereg(CCREG,HOST_CCREG);
6141 cc=get_reg(i_regmap,CCREG);
6142 assert(cc==HOST_CCREG);
6143 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
6146 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6152 static void pagespan_assemble(int i,struct regstat *i_regs)
6154 int s1l=get_reg(i_regs->regmap,rs1[i]);
6155 int s1h=get_reg(i_regs->regmap,rs1[i]|64);
6156 int s2l=get_reg(i_regs->regmap,rs2[i]);
6157 int s2h=get_reg(i_regs->regmap,rs2[i]|64);
6158 void *nt_branch=NULL;
6161 int unconditional=0;
6171 if((i_regs->is32>>rs1[i])&(i_regs->is32>>rs2[i])&1) {
6175 int addr,alt,ntaddr;
6176 if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
6180 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
6181 (i_regs->regmap[hr]&63)!=rs1[i] &&
6182 (i_regs->regmap[hr]&63)!=rs2[i] )
6191 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6192 (i_regs->regmap[hr]&63)!=rs1[i] &&
6193 (i_regs->regmap[hr]&63)!=rs2[i] )
6199 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
6203 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6204 (i_regs->regmap[hr]&63)!=rs1[i] &&
6205 (i_regs->regmap[hr]&63)!=rs2[i] )
6212 assert(hr<HOST_REGS);
6213 if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
6214 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
6216 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6217 if(opcode[i]==2) // J
6221 if(opcode[i]==3) // JAL
6224 int rt=get_reg(i_regs->regmap,31);
6225 emit_movimm(start+i*4+8,rt);
6228 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
6231 if(opcode2[i]==9) // JALR
6233 int rt=get_reg(i_regs->regmap,rt1[i]);
6234 emit_movimm(start+i*4+8,rt);
6237 if((opcode[i]&0x3f)==4) // BEQ
6244 #ifdef HAVE_CMOV_IMM
6246 if(s2l>=0) emit_cmp(s1l,s2l);
6247 else emit_test(s1l,s1l);
6248 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
6254 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6256 if(s2h>=0) emit_cmp(s1h,s2h);
6257 else emit_test(s1h,s1h);
6258 emit_cmovne_reg(alt,addr);
6260 if(s2l>=0) emit_cmp(s1l,s2l);
6261 else emit_test(s1l,s1l);
6262 emit_cmovne_reg(alt,addr);
6265 if((opcode[i]&0x3f)==5) // BNE
6267 #ifdef HAVE_CMOV_IMM
6269 if(s2l>=0) emit_cmp(s1l,s2l);
6270 else emit_test(s1l,s1l);
6271 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
6277 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
6279 if(s2h>=0) emit_cmp(s1h,s2h);
6280 else emit_test(s1h,s1h);
6281 emit_cmovne_reg(alt,addr);
6283 if(s2l>=0) emit_cmp(s1l,s2l);
6284 else emit_test(s1l,s1l);
6285 emit_cmovne_reg(alt,addr);
6288 if((opcode[i]&0x3f)==0x14) // BEQL
6291 if(s2h>=0) emit_cmp(s1h,s2h);
6292 else emit_test(s1h,s1h);
6296 if(s2l>=0) emit_cmp(s1l,s2l);
6297 else emit_test(s1l,s1l);
6298 if(nottaken) set_jump_target(nottaken,(int)out);
6302 if((opcode[i]&0x3f)==0x15) // BNEL
6305 if(s2h>=0) emit_cmp(s1h,s2h);
6306 else emit_test(s1h,s1h);
6310 if(s2l>=0) emit_cmp(s1l,s2l);
6311 else emit_test(s1l,s1l);
6314 if(taken) set_jump_target(taken,(int)out);
6316 if((opcode[i]&0x3f)==6) // BLEZ
6318 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6320 if(s1h>=0) emit_mov(addr,ntaddr);
6321 emit_cmovl_reg(alt,addr);
6324 emit_cmovne_reg(ntaddr,addr);
6325 emit_cmovs_reg(alt,addr);
6328 if((opcode[i]&0x3f)==7) // BGTZ
6330 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
6332 if(s1h>=0) emit_mov(addr,alt);
6333 emit_cmovl_reg(ntaddr,addr);
6336 emit_cmovne_reg(alt,addr);
6337 emit_cmovs_reg(ntaddr,addr);
6340 if((opcode[i]&0x3f)==0x16) // BLEZL
6342 assert((opcode[i]&0x3f)!=0x16);
6344 if((opcode[i]&0x3f)==0x17) // BGTZL
6346 assert((opcode[i]&0x3f)!=0x17);
6348 assert(opcode[i]!=1); // BLTZ/BGEZ
6350 //FIXME: Check CSREG
6351 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
6352 if((source[i]&0x30000)==0) // BC1F
6354 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6355 emit_testimm(s1l,0x800000);
6356 emit_cmovne_reg(alt,addr);
6358 if((source[i]&0x30000)==0x10000) // BC1T
6360 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6361 emit_testimm(s1l,0x800000);
6362 emit_cmovne_reg(alt,addr);
6364 if((source[i]&0x30000)==0x20000) // BC1FL
6366 emit_testimm(s1l,0x800000);
6370 if((source[i]&0x30000)==0x30000) // BC1TL
6372 emit_testimm(s1l,0x800000);
6378 assert(i_regs->regmap[HOST_CCREG]==CCREG);
6379 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6380 if(likely[i]||unconditional)
6382 emit_movimm(ba[i],HOST_BTREG);
6384 else if(addr!=HOST_BTREG)
6386 emit_mov(addr,HOST_BTREG);
6388 void *branch_addr=out;
6390 int target_addr=start+i*4+5;
6392 void *compiled_target_addr=check_addr(target_addr);
6393 emit_extjump_ds((int)branch_addr,target_addr);
6394 if(compiled_target_addr) {
6395 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6396 add_link(target_addr,stub);
6398 else set_jump_target((int)branch_addr,(int)stub);
6401 set_jump_target((int)nottaken,(int)out);
6402 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6403 void *branch_addr=out;
6405 int target_addr=start+i*4+8;
6407 void *compiled_target_addr=check_addr(target_addr);
6408 emit_extjump_ds((int)branch_addr,target_addr);
6409 if(compiled_target_addr) {
6410 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6411 add_link(target_addr,stub);
6413 else set_jump_target((int)branch_addr,(int)stub);
6417 // Assemble the delay slot for the above
6418 static void pagespan_ds()
6420 assem_debug("initial delay slot:\n");
6421 u_int vaddr=start+1;
6422 u_int page=get_page(vaddr);
6423 u_int vpage=get_vpage(vaddr);
6424 ll_add(jump_dirty+vpage,vaddr,(void *)out);
6426 ll_add(jump_in+page,vaddr,(void *)out);
6427 assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6428 if(regs[0].regmap[HOST_CCREG]!=CCREG)
6429 wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty,regs[0].was32);
6430 if(regs[0].regmap[HOST_BTREG]!=BTREG)
6431 emit_writeword(HOST_BTREG,(int)&branch_target);
6432 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,rs1[0],rs2[0]);
6433 address_generation(0,®s[0],regs[0].regmap_entry);
6434 if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39||(opcode[0]&0x3b)==0x3a)
6435 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,INVCP,INVCP);
6440 alu_assemble(0,®s[0]);break;
6442 imm16_assemble(0,®s[0]);break;
6444 shift_assemble(0,®s[0]);break;
6446 shiftimm_assemble(0,®s[0]);break;
6448 load_assemble(0,®s[0]);break;
6450 loadlr_assemble(0,®s[0]);break;
6452 store_assemble(0,®s[0]);break;
6454 storelr_assemble(0,®s[0]);break;
6456 cop0_assemble(0,®s[0]);break;
6458 cop1_assemble(0,®s[0]);break;
6460 c1ls_assemble(0,®s[0]);break;
6462 cop2_assemble(0,®s[0]);break;
6464 c2ls_assemble(0,®s[0]);break;
6466 c2op_assemble(0,®s[0]);break;
6468 fconv_assemble(0,®s[0]);break;
6470 float_assemble(0,®s[0]);break;
6472 fcomp_assemble(0,®s[0]);break;
6474 multdiv_assemble(0,®s[0]);break;
6476 mov_assemble(0,®s[0]);break;
6485 printf("Jump in the delay slot. This is probably a bug.\n");
6487 int btaddr=get_reg(regs[0].regmap,BTREG);
6489 btaddr=get_reg(regs[0].regmap,-1);
6490 emit_readword((int)&branch_target,btaddr);
6492 assert(btaddr!=HOST_CCREG);
6493 if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6495 emit_movimm(start+4,HOST_TEMPREG);
6496 emit_cmp(btaddr,HOST_TEMPREG);
6498 emit_cmpimm(btaddr,start+4);
6500 int branch=(int)out;
6502 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,-1);
6503 emit_jmp(jump_vaddr_reg[btaddr]);
6504 set_jump_target(branch,(int)out);
6505 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6506 load_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6509 // Basic liveness analysis for MIPS registers
6510 void unneeded_registers(int istart,int iend,int r)
6514 uint64_t temp_u,temp_uu;
6519 u=unneeded_reg[iend+1];
6520 uu=unneeded_reg_upper[iend+1];
6523 for (i=iend;i>=istart;i--)
6525 //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
6526 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6528 // If subroutine call, flag return address as a possible branch target
6529 if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
6531 if(ba[i]<start || ba[i]>=(start+slen*4))
6533 // Branch out of this block, flush all regs
6537 if(itype[i]==UJUMP&&rt1[i]==31)
6539 uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
6541 if(itype[i]==RJUMP&&rs1[i]==31)
6543 uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9
6545 if(start>0x80000400&&start<0x80000000+RAM_SIZE) {
6546 if(itype[i]==UJUMP&&rt1[i]==31)
6548 //uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi
6549 uu=u=0x300FF0F; // Discard at, v0-v1, t0-t9
6551 if(itype[i]==RJUMP&&rs1[i]==31)
6553 //uu=u=0x30300FFF3LL; // Discard at, a0-a3, t0-t9, lo, hi
6554 uu=u=0x300FFF3; // Discard at, a0-a3, t0-t9
6557 branch_unneeded_reg[i]=u;
6558 branch_unneeded_reg_upper[i]=uu;
6559 // Merge in delay slot
6560 tdep=(~uu>>rt1[i+1])&1;
6561 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6562 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6563 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6564 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6565 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6567 // If branch is "likely" (and conditional)
6568 // then we skip the delay slot on the fall-thru path
6571 u&=unneeded_reg[i+2];
6572 uu&=unneeded_reg_upper[i+2];
6583 // Internal branch, flag target
6584 bt[(ba[i]-start)>>2]=1;
6585 if(ba[i]<=start+i*4) {
6587 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6589 // Unconditional branch
6592 // Conditional branch (not taken case)
6593 temp_u=unneeded_reg[i+2];
6594 temp_uu=unneeded_reg_upper[i+2];
6596 // Merge in delay slot
6597 tdep=(~temp_uu>>rt1[i+1])&1;
6598 temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6599 temp_uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6600 temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6601 temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6602 temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6603 temp_u|=1;temp_uu|=1;
6604 // If branch is "likely" (and conditional)
6605 // then we skip the delay slot on the fall-thru path
6608 temp_u&=unneeded_reg[i+2];
6609 temp_uu&=unneeded_reg_upper[i+2];
6617 tdep=(~temp_uu>>rt1[i])&1;
6618 temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6619 temp_uu|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6620 temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6621 temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
6622 temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i]));
6623 temp_u|=1;temp_uu|=1;
6624 unneeded_reg[i]=temp_u;
6625 unneeded_reg_upper[i]=temp_uu;
6626 // Only go three levels deep. This recursion can take an
6627 // excessive amount of time if there are a lot of nested loops.
6629 unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6631 unneeded_reg[(ba[i]-start)>>2]=1;
6632 unneeded_reg_upper[(ba[i]-start)>>2]=1;
6635 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6637 // Unconditional branch
6638 u=unneeded_reg[(ba[i]-start)>>2];
6639 uu=unneeded_reg_upper[(ba[i]-start)>>2];
6640 branch_unneeded_reg[i]=u;
6641 branch_unneeded_reg_upper[i]=uu;
6644 //branch_unneeded_reg[i]=u;
6645 //branch_unneeded_reg_upper[i]=uu;
6646 // Merge in delay slot
6647 tdep=(~uu>>rt1[i+1])&1;
6648 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6649 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6650 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6651 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6652 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6655 // Conditional branch
6656 b=unneeded_reg[(ba[i]-start)>>2];
6657 bu=unneeded_reg_upper[(ba[i]-start)>>2];
6658 branch_unneeded_reg[i]=b;
6659 branch_unneeded_reg_upper[i]=bu;
6662 //branch_unneeded_reg[i]=b;
6663 //branch_unneeded_reg_upper[i]=bu;
6664 // Branch delay slot
6665 tdep=(~uu>>rt1[i+1])&1;
6666 b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6667 bu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6668 b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6669 bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6670 bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6672 // If branch is "likely" then we skip the
6673 // delay slot on the fall-thru path
6678 u&=unneeded_reg[i+2];
6679 uu&=unneeded_reg_upper[i+2];
6690 branch_unneeded_reg[i]&=unneeded_reg[i+2];
6691 branch_unneeded_reg_upper[i]&=unneeded_reg_upper[i+2];
6692 //branch_unneeded_reg[i]=1;
6693 //branch_unneeded_reg_upper[i]=1;
6695 branch_unneeded_reg[i]=1;
6696 branch_unneeded_reg_upper[i]=1;
6702 else if(itype[i]==SYSCALL||itype[i]==HLECALL)
6704 // SYSCALL instruction (software interrupt)
6708 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
6710 // ERET instruction (return from interrupt)
6715 tdep=(~uu>>rt1[i])&1;
6716 // Written registers are unneeded
6721 // Accessed registers are needed
6726 // Source-target dependencies
6727 uu&=~(tdep<<dep1[i]);
6728 uu&=~(tdep<<dep2[i]);
6729 // R0 is always unneeded
6733 unneeded_reg_upper[i]=uu;
6735 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
6738 for(r=1;r<=CCREG;r++) {
6739 if((unneeded_reg[i]>>r)&1) {
6740 if(r==HIREG) printf(" HI");
6741 else if(r==LOREG) printf(" LO");
6742 else printf(" r%d",r);
6746 for(r=1;r<=CCREG;r++) {
6747 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
6748 if(r==HIREG) printf(" HI");
6749 else if(r==LOREG) printf(" LO");
6750 else printf(" r%d",r);
6756 for (i=iend;i>=istart;i--)
6758 unneeded_reg_upper[i]=branch_unneeded_reg_upper[i]=-1LL;
6763 // Identify registers which are likely to contain 32-bit values
6764 // This is used to predict whether any branches will jump to a
6765 // location with 64-bit values in registers.
6766 static void provisional_32bit()
6770 uint64_t lastbranch=1;
6775 if(itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) {
6776 if(i>1) is32=lastbranch;
6782 if(itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP) {
6784 if(i>2) is32=lastbranch;
6788 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
6790 if(rs1[i-2]==0||rs2[i-2]==0)
6793 is32|=1LL<<rs1[i-2];
6796 is32|=1LL<<rs2[i-2];
6801 // If something jumps here with 64-bit values
6802 // then promote those registers to 64 bits
6805 uint64_t temp_is32=is32;
6808 if(ba[j]==start+i*4)
6809 //temp_is32&=branch_regs[j].is32;
6814 if(ba[j]==start+i*4)
6825 if(type==UJUMP||type==RJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
6826 // Branches don't write registers, consider the delay slot instead.
6837 if(opcode[i]==0x27||opcode[i]==0x37|| // LWU/LD
6838 opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
6847 if(op==0x1a||op==0x1b) is32&=~(1LL<<rt); // LDR/LDL
6848 if(op==0x22) is32|=1LL<<rt; // LWL
6851 if (op==0x08||op==0x09|| // ADDI/ADDIU
6852 op==0x0a||op==0x0b|| // SLTI/SLTIU
6858 if(op==0x18||op==0x19) { // DADDI/DADDIU
6861 // is32|=((is32>>s1)&1LL)<<rt;
6863 if(op==0x0d||op==0x0e) { // ORI/XORI
6864 uint64_t sr=((is32>>s1)&1LL);
6880 if(op2>=0x20&&op2<=0x23) { // ADD/ADDU/SUB/SUBU
6883 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
6886 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
6887 uint64_t sr=((is32>>s1)&(is32>>s2)&1LL);
6891 else if(op2>=0x2c&&op2<=0x2d) { // DADD/DADDU
6896 uint64_t sr=((is32>>s1)&1LL);
6901 uint64_t sr=((is32>>s2)&1LL);
6909 else if(op2>=0x2e&&op2<=0x2f) { // DSUB/DSUBU
6914 uint64_t sr=((is32>>s1)&1LL);
6924 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
6925 is32&=~((1LL<<HIREG)|(1LL<<LOREG));
6928 is32|=(1LL<<HIREG)|(1LL<<LOREG);
6933 uint64_t sr=((is32>>s1)&1LL);
6939 if(op2>=0x14&&op2<=0x17) is32&=~(1LL<<rt); // DSLLV/DSRLV/DSRAV
6940 else is32|=1LL<<rt; // SLLV/SRLV/SRAV
6944 // DSLL/DSRL/DSRA/DSLL32/DSRL32 but not DSRA32 have 64-bit result
6945 if(op2>=0x38&&op2<0x3f) is32&=~(1LL<<rt);
6948 if(op2==0) is32|=1LL<<rt; // MFC0
6952 if(op2==0) is32|=1LL<<rt; // MFC1
6953 if(op2==1) is32&=~(1LL<<rt); // DMFC1
6954 if(op2==2) is32|=1LL<<rt; // CFC1
6976 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
6978 if(rt1[i-1]==31) // JAL/JALR
6980 // Subroutine call will return here, don't alloc any registers
6985 // Internal branch will jump here, match registers to caller
6993 // Identify registers which may be assumed to contain 32-bit values
6994 // and where optimizations will rely on this.
6995 // This is used to determine whether backward branches can safely
6996 // jump to a location with 64-bit values in registers.
6997 static void provisional_r32()
7002 for (i=slen-1;i>=0;i--)
7005 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7007 if(ba[i]<start || ba[i]>=(start+slen*4))
7009 // Branch out of this block, don't need anything
7015 // Need whatever matches the target
7016 // (and doesn't get overwritten by the delay slot instruction)
7018 int t=(ba[i]-start)>>2;
7019 if(ba[i]>start+i*4) {
7021 //if(!(requires_32bit[t]&~regs[i].was32))
7022 // r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7023 if(!(pr32[t]&~regs[i].was32))
7024 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7027 if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
7028 r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7031 // Conditional branch may need registers for following instructions
7032 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
7035 //r32|=requires_32bit[i+2];
7038 // Mark this address as a branch target since it may be called
7039 // upon return from interrupt
7043 // Merge in delay slot
7045 // These are overwritten unless the branch is "likely"
7046 // and the delay slot is nullified if not taken
7047 r32&=~(1LL<<rt1[i+1]);
7048 r32&=~(1LL<<rt2[i+1]);
7050 // Assume these are needed (delay slot)
7053 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
7057 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
7059 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
7061 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
7063 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
7065 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
7068 else if(itype[i]==SYSCALL||itype[i]==HLECALL)
7070 // SYSCALL instruction (software interrupt)
7073 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7075 // ERET instruction (return from interrupt)
7079 r32&=~(1LL<<rt1[i]);
7080 r32&=~(1LL<<rt2[i]);
7083 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
7087 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
7089 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
7091 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
7093 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
7095 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
7097 //requires_32bit[i]=r32;
7100 // Dirty registers which are 32-bit, require 32-bit input
7101 // as they will be written as 32-bit values
7102 for(hr=0;hr<HOST_REGS;hr++)
7104 if(regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64) {
7105 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
7106 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
7107 pr32[i]|=1LL<<regs[i].regmap_entry[hr];
7108 //requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
7115 // Write back dirty registers as soon as we will no longer modify them,
7116 // so that we don't end up with lots of writes at the branches.
7117 void clean_registers(int istart,int iend,int wr)
7121 u_int will_dirty_i,will_dirty_next,temp_will_dirty;
7122 u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
7124 will_dirty_i=will_dirty_next=0;
7125 wont_dirty_i=wont_dirty_next=0;
7127 will_dirty_i=will_dirty_next=will_dirty[iend+1];
7128 wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
7130 for (i=iend;i>=istart;i--)
7132 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7134 if(ba[i]<start || ba[i]>=(start+slen*4))
7136 // Branch out of this block, flush all regs
7137 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7139 // Unconditional branch
7142 // Merge in delay slot (will dirty)
7143 for(r=0;r<HOST_REGS;r++) {
7144 if(r!=EXCLUDE_REG) {
7145 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7146 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7147 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7148 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7149 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7150 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7151 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7152 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7153 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7154 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7155 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7156 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7157 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7158 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7164 // Conditional branch
7166 wont_dirty_i=wont_dirty_next;
7167 // Merge in delay slot (will dirty)
7168 for(r=0;r<HOST_REGS;r++) {
7169 if(r!=EXCLUDE_REG) {
7171 // Might not dirty if likely branch is not taken
7172 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7173 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7174 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7175 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7176 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7177 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
7178 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7179 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7180 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7181 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7182 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7183 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7184 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7185 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7190 // Merge in delay slot (wont dirty)
7191 for(r=0;r<HOST_REGS;r++) {
7192 if(r!=EXCLUDE_REG) {
7193 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7194 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7195 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7196 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7197 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7198 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7199 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7200 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7201 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7202 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7206 #ifndef DESTRUCTIVE_WRITEBACK
7207 branch_regs[i].dirty&=wont_dirty_i;
7209 branch_regs[i].dirty|=will_dirty_i;
7215 if(ba[i]<=start+i*4) {
7217 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7219 // Unconditional branch
7222 // Merge in delay slot (will dirty)
7223 for(r=0;r<HOST_REGS;r++) {
7224 if(r!=EXCLUDE_REG) {
7225 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7226 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7227 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7228 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7229 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7230 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7231 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7232 if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7233 if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7234 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7235 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7236 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7237 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7238 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7242 // Conditional branch (not taken case)
7243 temp_will_dirty=will_dirty_next;
7244 temp_wont_dirty=wont_dirty_next;
7245 // Merge in delay slot (will dirty)
7246 for(r=0;r<HOST_REGS;r++) {
7247 if(r!=EXCLUDE_REG) {
7249 // Will not dirty if likely branch is not taken
7250 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7251 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7252 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7253 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7254 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7255 if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
7256 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7257 //if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7258 //if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7259 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7260 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7261 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7262 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7263 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7268 // Merge in delay slot (wont dirty)
7269 for(r=0;r<HOST_REGS;r++) {
7270 if(r!=EXCLUDE_REG) {
7271 if((regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7272 if((regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7273 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7274 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7275 if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7276 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7277 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7278 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7279 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7280 if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7283 // Deal with changed mappings
7285 for(r=0;r<HOST_REGS;r++) {
7286 if(r!=EXCLUDE_REG) {
7287 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
7288 temp_will_dirty&=~(1<<r);
7289 temp_wont_dirty&=~(1<<r);
7290 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7291 temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7292 temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7294 temp_will_dirty|=1<<r;
7295 temp_wont_dirty|=1<<r;
7302 will_dirty[i]=temp_will_dirty;
7303 wont_dirty[i]=temp_wont_dirty;
7304 clean_registers((ba[i]-start)>>2,i-1,0);
7306 // Limit recursion. It can take an excessive amount
7307 // of time if there are a lot of nested loops.
7308 will_dirty[(ba[i]-start)>>2]=0;
7309 wont_dirty[(ba[i]-start)>>2]=-1;
7314 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7316 // Unconditional branch
7319 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7320 for(r=0;r<HOST_REGS;r++) {
7321 if(r!=EXCLUDE_REG) {
7322 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7323 will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
7324 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7329 // Merge in delay slot
7330 for(r=0;r<HOST_REGS;r++) {
7331 if(r!=EXCLUDE_REG) {
7332 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7333 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7334 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7335 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7336 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7337 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7338 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7339 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7340 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7341 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7342 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7343 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7344 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7345 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7349 // Conditional branch
7350 will_dirty_i=will_dirty_next;
7351 wont_dirty_i=wont_dirty_next;
7352 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7353 for(r=0;r<HOST_REGS;r++) {
7354 if(r!=EXCLUDE_REG) {
7355 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7356 will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7357 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7361 will_dirty_i&=~(1<<r);
7363 // Treat delay slot as part of branch too
7364 /*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7365 will_dirty[i+1]&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7366 wont_dirty[i+1]|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7370 will_dirty[i+1]&=~(1<<r);
7375 // Merge in delay slot
7376 for(r=0;r<HOST_REGS;r++) {
7377 if(r!=EXCLUDE_REG) {
7379 // Might not dirty if likely branch is not taken
7380 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7381 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7382 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7383 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7384 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7385 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7386 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7387 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7388 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7389 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7390 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7391 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7392 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7393 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7398 // Merge in delay slot
7399 for(r=0;r<HOST_REGS;r++) {
7400 if(r!=EXCLUDE_REG) {
7401 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7402 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7403 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7404 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7405 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7406 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7407 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7408 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7409 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7410 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7414 #ifndef DESTRUCTIVE_WRITEBACK
7415 branch_regs[i].dirty&=wont_dirty_i;
7417 branch_regs[i].dirty|=will_dirty_i;
7422 else if(itype[i]==SYSCALL||itype[i]==HLECALL)
7424 // SYSCALL instruction (software interrupt)
7428 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7430 // ERET instruction (return from interrupt)
7434 will_dirty_next=will_dirty_i;
7435 wont_dirty_next=wont_dirty_i;
7436 for(r=0;r<HOST_REGS;r++) {
7437 if(r!=EXCLUDE_REG) {
7438 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7439 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7440 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7441 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7442 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7443 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7444 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7445 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7447 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
7449 // Don't store a register immediately after writing it,
7450 // may prevent dual-issue.
7451 if((regs[i].regmap[r]&63)==rt1[i-1]) wont_dirty_i|=1<<r;
7452 if((regs[i].regmap[r]&63)==rt2[i-1]) wont_dirty_i|=1<<r;
7458 will_dirty[i]=will_dirty_i;
7459 wont_dirty[i]=wont_dirty_i;
7460 // Mark registers that won't be dirtied as not dirty
7462 /*printf("wr (%d,%d) %x will:",istart,iend,start+i*4);
7463 for(r=0;r<HOST_REGS;r++) {
7464 if((will_dirty_i>>r)&1) {
7470 //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=FJUMP)) {
7471 regs[i].dirty|=will_dirty_i;
7472 #ifndef DESTRUCTIVE_WRITEBACK
7473 regs[i].dirty&=wont_dirty_i;
7474 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7476 if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
7477 for(r=0;r<HOST_REGS;r++) {
7478 if(r!=EXCLUDE_REG) {
7479 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
7480 regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
7481 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7489 for(r=0;r<HOST_REGS;r++) {
7490 if(r!=EXCLUDE_REG) {
7491 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
7492 regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
7493 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7501 // Deal with changed mappings
7502 temp_will_dirty=will_dirty_i;
7503 temp_wont_dirty=wont_dirty_i;
7504 for(r=0;r<HOST_REGS;r++) {
7505 if(r!=EXCLUDE_REG) {
7507 if(regs[i].regmap[r]==regmap_pre[i][r]) {
7509 #ifndef DESTRUCTIVE_WRITEBACK
7510 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7512 regs[i].wasdirty|=will_dirty_i&(1<<r);
7515 else if((nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
7516 // Register moved to a different register
7517 will_dirty_i&=~(1<<r);
7518 wont_dirty_i&=~(1<<r);
7519 will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
7520 wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
7522 #ifndef DESTRUCTIVE_WRITEBACK
7523 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7525 regs[i].wasdirty|=will_dirty_i&(1<<r);
7529 will_dirty_i&=~(1<<r);
7530 wont_dirty_i&=~(1<<r);
7531 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7532 will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7533 wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7536 /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);/*assert(!((will_dirty>>r)&1));*/
7545 void disassemble_inst(int i)
7547 if (bt[i]) printf("*"); else printf(" ");
7550 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7552 printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
7554 printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
7556 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7558 if (opcode[i]==0x9&&rt1[i]!=31)
7559 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i]);
7561 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7564 printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break;
7566 if(opcode[i]==0xf) //LUI
7567 printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],rt1[i],imm[i]&0xffff);
7569 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7573 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7577 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rs2[i],rs1[i],imm[i]);
7581 printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i],rs2[i]);
7584 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rs1[i],rs2[i]);
7587 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7590 if((opcode2[i]&0x1d)==0x10)
7591 printf (" %x: %s r%d\n",start+i*4,insn[i],rt1[i]);
7592 else if((opcode2[i]&0x1d)==0x11)
7593 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7595 printf (" %x: %s\n",start+i*4,insn[i]);
7599 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC0
7600 else if(opcode2[i]==4)
7601 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC0
7602 else printf (" %x: %s\n",start+i*4,insn[i]);
7606 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC1
7607 else if(opcode2[i]>3)
7608 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC1
7609 else printf (" %x: %s\n",start+i*4,insn[i]);
7613 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC2
7614 else if(opcode2[i]>3)
7615 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC2
7616 else printf (" %x: %s\n",start+i*4,insn[i]);
7619 printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7622 printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7625 //printf (" %s %8x\n",insn[i],source[i]);
7626 printf (" %x: %s\n",start+i*4,insn[i]);
7630 void new_dynarec_init()
7632 printf("Init new dynarec\n");
7633 out=(u_char *)BASE_ADDR;
7634 if (mmap (out, 1<<TARGET_SIZE_2,
7635 PROT_READ | PROT_WRITE | PROT_EXEC,
7636 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
7637 -1, 0) <= 0) {printf("mmap() failed\n");}
7639 rdword=&readmem_dword;
7640 fake_pc.f.r.rs=&readmem_dword;
7641 fake_pc.f.r.rt=&readmem_dword;
7642 fake_pc.f.r.rd=&readmem_dword;
7645 for(n=0x80000;n<0x80800;n++)
7647 for(n=0;n<65536;n++)
7648 hash_table[n][0]=hash_table[n][2]=-1;
7649 memset(mini_ht,-1,sizeof(mini_ht));
7650 memset(restore_candidate,0,sizeof(restore_candidate));
7652 expirep=16384; // Expiry pointer, +2 blocks
7653 pending_exception=0;
7656 // Copy this into local area so we don't have to put it in every literal pool
7657 invc_ptr=invalid_code;
7662 for(n=0;n<524288;n++) // 0 .. 0x7FFFFFFF
7664 for(n=524288;n<526336;n++) // 0x80000000 .. 0x807FFFFF
7665 memory_map[n]=((u_int)rdram-0x80000000)>>2;
7666 for(n=526336;n<1048576;n++) // 0x80800000 .. 0xFFFFFFFF
7669 for(n=0;n<0x8000;n++) { // 0 .. 0x7FFFFFFF
7670 writemem[n] = write_nomem_new;
7671 writememb[n] = write_nomemb_new;
7672 writememh[n] = write_nomemh_new;
7674 writememd[n] = write_nomemd_new;
7676 readmem[n] = read_nomem_new;
7677 readmemb[n] = read_nomemb_new;
7678 readmemh[n] = read_nomemh_new;
7680 readmemd[n] = read_nomemd_new;
7683 for(n=0x8000;n<0x8080;n++) { // 0x80000000 .. 0x807FFFFF
7684 writemem[n] = write_rdram_new;
7685 writememb[n] = write_rdramb_new;
7686 writememh[n] = write_rdramh_new;
7688 writememd[n] = write_rdramd_new;
7691 for(n=0xC000;n<0x10000;n++) { // 0xC0000000 .. 0xFFFFFFFF
7692 writemem[n] = write_nomem_new;
7693 writememb[n] = write_nomemb_new;
7694 writememh[n] = write_nomemh_new;
7696 writememd[n] = write_nomemd_new;
7698 readmem[n] = read_nomem_new;
7699 readmemb[n] = read_nomemb_new;
7700 readmemh[n] = read_nomemh_new;
7702 readmemd[n] = read_nomemd_new;
7710 void new_dynarec_cleanup()
7713 if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0) {printf("munmap() failed\n");}
7714 for(n=0;n<4096;n++) ll_clear(jump_in+n);
7715 for(n=0;n<4096;n++) ll_clear(jump_out+n);
7716 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7718 if (munmap (ROM_COPY, 67108864) < 0) {printf("munmap() failed\n");}
7722 int new_recompile_block(int addr)
7725 if(addr==0x800cd050) {
7727 for(block=0x80000;block<0x80800;block++) invalidate_block(block);
7729 for(n=0;n<=2048;n++) ll_clear(jump_dirty+n);
7732 //if(Count==365117028) tracedebug=1;
7733 assem_debug("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7734 //printf("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7735 //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
7737 //printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
7738 //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
7739 /*if(Count>=312978186) {
7743 start = (u_int)addr&~3;
7744 //assert(((u_int)addr&1)==0);
7746 if (Config.HLE && start == 0x80001000) // hlecall
7748 // XXX: is this enough? Maybe check hleSoftCall?
7749 u_int beginning=(u_int)out;
7750 u_int page=get_page(start);
7751 invalid_code[start>>12]=0;
7752 emit_movimm(start,0);
7753 emit_writeword(0,(int)&pcaddr);
7754 emit_jmp((int)new_dyna_leave);
7756 __clear_cache((void *)beginning,out);
7758 ll_add(jump_in+page,start,(void *)beginning);
7761 else if ((u_int)addr < 0x00200000 ||
7762 (0xa0000000 <= addr && addr < 0xa0200000)) {
7763 // used for BIOS calls mostly?
7764 source = (u_int *)((u_int)rdram+(start&0x1fffff));
7765 pagelimit = (addr&0xa0000000)|0x00200000;
7767 else if (!Config.HLE && (
7768 /* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
7769 (0xbfc00000 <= addr && addr < 0xbfc80000))) {
7771 source = (u_int *)((u_int)psxR+(start&0x7ffff));
7772 pagelimit = (addr&0xfff00000)|0x80000;
7777 if ((int)addr >= 0xa4000000 && (int)addr < 0xa4001000) {
7778 source = (u_int *)((u_int)SP_DMEM+start-0xa4000000);
7779 pagelimit = 0xa4001000;
7783 if ((int)addr >= 0x80000000 && (int)addr < 0x80000000+RAM_SIZE) {
7784 source = (u_int *)((u_int)rdram+start-0x80000000);
7785 pagelimit = 0x80000000+RAM_SIZE;
7788 else if ((signed int)addr >= (signed int)0xC0000000) {
7789 //printf("addr=%x mm=%x\n",(u_int)addr,(memory_map[start>>12]<<2));
7790 //if(tlb_LUT_r[start>>12])
7791 //source = (u_int *)(((int)rdram)+(tlb_LUT_r[start>>12]&0xFFFFF000)+(((int)addr)&0xFFF)-0x80000000);
7792 if((signed int)memory_map[start>>12]>=0) {
7793 source = (u_int *)((u_int)(start+(memory_map[start>>12]<<2)));
7794 pagelimit=(start+4096)&0xFFFFF000;
7795 int map=memory_map[start>>12];
7798 //printf("start: %x next: %x\n",map,memory_map[pagelimit>>12]);
7799 if((map&0xBFFFFFFF)==(memory_map[pagelimit>>12]&0xBFFFFFFF)) pagelimit+=4096;
7801 assem_debug("pagelimit=%x\n",pagelimit);
7802 assem_debug("mapping=%x (%x)\n",memory_map[start>>12],(memory_map[start>>12]<<2)+start);
7805 assem_debug("Compile at unmapped memory address: %x \n", (int)addr);
7806 //assem_debug("start: %x next: %x\n",memory_map[start>>12],memory_map[(start+4096)>>12]);
7807 return -1; // Caller will invoke exception handler
7809 //printf("source= %x\n",(int)source);
7813 printf("Compile at bogus memory address: %x \n", (int)addr);
7817 /* Pass 1: disassemble */
7818 /* Pass 2: register dependencies, branch targets */
7819 /* Pass 3: register allocation */
7820 /* Pass 4: branch dependencies */
7821 /* Pass 5: pre-alloc */
7822 /* Pass 6: optimize clean/dirty state */
7823 /* Pass 7: flag 32-bit registers */
7824 /* Pass 8: assembly */
7825 /* Pass 9: linker */
7826 /* Pass 10: garbage collection / free memory */
7830 unsigned int type,op,op2;
7832 //printf("addr = %x source = %x %x\n", addr,source,source[0]);
7834 /* Pass 1 disassembly */
7836 for(i=0;!done;i++) {
7837 bt[i]=0;likely[i]=0;op2=0;
7838 opcode[i]=op=source[i]>>26;
7841 case 0x00: strcpy(insn[i],"special"); type=NI;
7845 case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
7846 case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
7847 case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
7848 case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
7849 case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
7850 case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
7851 case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
7852 case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
7853 case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
7854 case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
7855 case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
7856 case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
7857 case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
7858 case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
7859 case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
7860 case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
7861 case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
7862 case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
7863 case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
7864 case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
7865 case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
7866 case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
7867 case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
7868 case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
7869 case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
7870 case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
7871 case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
7872 case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
7873 case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
7874 case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
7875 case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
7876 case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
7877 case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
7878 case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
7879 case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
7880 case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
7881 case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
7882 case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
7883 case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
7884 case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
7885 case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
7886 case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
7887 case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
7888 case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
7889 case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
7890 case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
7891 case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
7892 case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
7893 case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
7894 case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
7895 case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
7896 case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
7899 case 0x01: strcpy(insn[i],"regimm"); type=NI;
7900 op2=(source[i]>>16)&0x1f;
7903 case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
7904 case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
7905 case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
7906 case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
7907 case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
7908 case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
7909 case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
7910 case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
7911 case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
7912 case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
7913 case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
7914 case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
7915 case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
7916 case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
7919 case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
7920 case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
7921 case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
7922 case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
7923 case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
7924 case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
7925 case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
7926 case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
7927 case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
7928 case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
7929 case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
7930 case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
7931 case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
7932 case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
7933 case 0x10: strcpy(insn[i],"cop0"); type=NI;
7934 op2=(source[i]>>21)&0x1f;
7937 case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
7938 case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
7939 case 0x10: strcpy(insn[i],"tlb"); type=NI;
7940 switch(source[i]&0x3f)
7942 case 0x01: strcpy(insn[i],"TLBR"); type=COP0; break;
7943 case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break;
7944 case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break;
7945 case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break;
7947 case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
7949 case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
7954 case 0x11: strcpy(insn[i],"cop1"); type=NI;
7955 op2=(source[i]>>21)&0x1f;
7958 case 0x00: strcpy(insn[i],"MFC1"); type=COP1; break;
7959 case 0x01: strcpy(insn[i],"DMFC1"); type=COP1; break;
7960 case 0x02: strcpy(insn[i],"CFC1"); type=COP1; break;
7961 case 0x04: strcpy(insn[i],"MTC1"); type=COP1; break;
7962 case 0x05: strcpy(insn[i],"DMTC1"); type=COP1; break;
7963 case 0x06: strcpy(insn[i],"CTC1"); type=COP1; break;
7964 case 0x08: strcpy(insn[i],"BC1"); type=FJUMP;
7965 switch((source[i]>>16)&0x3)
7967 case 0x00: strcpy(insn[i],"BC1F"); break;
7968 case 0x01: strcpy(insn[i],"BC1T"); break;
7969 case 0x02: strcpy(insn[i],"BC1FL"); break;
7970 case 0x03: strcpy(insn[i],"BC1TL"); break;
7973 case 0x10: strcpy(insn[i],"C1.S"); type=NI;
7974 switch(source[i]&0x3f)
7976 case 0x00: strcpy(insn[i],"ADD.S"); type=FLOAT; break;
7977 case 0x01: strcpy(insn[i],"SUB.S"); type=FLOAT; break;
7978 case 0x02: strcpy(insn[i],"MUL.S"); type=FLOAT; break;
7979 case 0x03: strcpy(insn[i],"DIV.S"); type=FLOAT; break;
7980 case 0x04: strcpy(insn[i],"SQRT.S"); type=FLOAT; break;
7981 case 0x05: strcpy(insn[i],"ABS.S"); type=FLOAT; break;
7982 case 0x06: strcpy(insn[i],"MOV.S"); type=FLOAT; break;
7983 case 0x07: strcpy(insn[i],"NEG.S"); type=FLOAT; break;
7984 case 0x08: strcpy(insn[i],"ROUND.L.S"); type=FCONV; break;
7985 case 0x09: strcpy(insn[i],"TRUNC.L.S"); type=FCONV; break;
7986 case 0x0A: strcpy(insn[i],"CEIL.L.S"); type=FCONV; break;
7987 case 0x0B: strcpy(insn[i],"FLOOR.L.S"); type=FCONV; break;
7988 case 0x0C: strcpy(insn[i],"ROUND.W.S"); type=FCONV; break;
7989 case 0x0D: strcpy(insn[i],"TRUNC.W.S"); type=FCONV; break;
7990 case 0x0E: strcpy(insn[i],"CEIL.W.S"); type=FCONV; break;
7991 case 0x0F: strcpy(insn[i],"FLOOR.W.S"); type=FCONV; break;
7992 case 0x21: strcpy(insn[i],"CVT.D.S"); type=FCONV; break;
7993 case 0x24: strcpy(insn[i],"CVT.W.S"); type=FCONV; break;
7994 case 0x25: strcpy(insn[i],"CVT.L.S"); type=FCONV; break;
7995 case 0x30: strcpy(insn[i],"C.F.S"); type=FCOMP; break;
7996 case 0x31: strcpy(insn[i],"C.UN.S"); type=FCOMP; break;
7997 case 0x32: strcpy(insn[i],"C.EQ.S"); type=FCOMP; break;
7998 case 0x33: strcpy(insn[i],"C.UEQ.S"); type=FCOMP; break;
7999 case 0x34: strcpy(insn[i],"C.OLT.S"); type=FCOMP; break;
8000 case 0x35: strcpy(insn[i],"C.ULT.S"); type=FCOMP; break;
8001 case 0x36: strcpy(insn[i],"C.OLE.S"); type=FCOMP; break;
8002 case 0x37: strcpy(insn[i],"C.ULE.S"); type=FCOMP; break;
8003 case 0x38: strcpy(insn[i],"C.SF.S"); type=FCOMP; break;
8004 case 0x39: strcpy(insn[i],"C.NGLE.S"); type=FCOMP; break;
8005 case 0x3A: strcpy(insn[i],"C.SEQ.S"); type=FCOMP; break;
8006 case 0x3B: strcpy(insn[i],"C.NGL.S"); type=FCOMP; break;
8007 case 0x3C: strcpy(insn[i],"C.LT.S"); type=FCOMP; break;
8008 case 0x3D: strcpy(insn[i],"C.NGE.S"); type=FCOMP; break;
8009 case 0x3E: strcpy(insn[i],"C.LE.S"); type=FCOMP; break;
8010 case 0x3F: strcpy(insn[i],"C.NGT.S"); type=FCOMP; break;
8013 case 0x11: strcpy(insn[i],"C1.D"); type=NI;
8014 switch(source[i]&0x3f)
8016 case 0x00: strcpy(insn[i],"ADD.D"); type=FLOAT; break;
8017 case 0x01: strcpy(insn[i],"SUB.D"); type=FLOAT; break;
8018 case 0x02: strcpy(insn[i],"MUL.D"); type=FLOAT; break;
8019 case 0x03: strcpy(insn[i],"DIV.D"); type=FLOAT; break;
8020 case 0x04: strcpy(insn[i],"SQRT.D"); type=FLOAT; break;
8021 case 0x05: strcpy(insn[i],"ABS.D"); type=FLOAT; break;
8022 case 0x06: strcpy(insn[i],"MOV.D"); type=FLOAT; break;
8023 case 0x07: strcpy(insn[i],"NEG.D"); type=FLOAT; break;
8024 case 0x08: strcpy(insn[i],"ROUND.L.D"); type=FCONV; break;
8025 case 0x09: strcpy(insn[i],"TRUNC.L.D"); type=FCONV; break;
8026 case 0x0A: strcpy(insn[i],"CEIL.L.D"); type=FCONV; break;
8027 case 0x0B: strcpy(insn[i],"FLOOR.L.D"); type=FCONV; break;
8028 case 0x0C: strcpy(insn[i],"ROUND.W.D"); type=FCONV; break;
8029 case 0x0D: strcpy(insn[i],"TRUNC.W.D"); type=FCONV; break;
8030 case 0x0E: strcpy(insn[i],"CEIL.W.D"); type=FCONV; break;
8031 case 0x0F: strcpy(insn[i],"FLOOR.W.D"); type=FCONV; break;
8032 case 0x20: strcpy(insn[i],"CVT.S.D"); type=FCONV; break;
8033 case 0x24: strcpy(insn[i],"CVT.W.D"); type=FCONV; break;
8034 case 0x25: strcpy(insn[i],"CVT.L.D"); type=FCONV; break;
8035 case 0x30: strcpy(insn[i],"C.F.D"); type=FCOMP; break;
8036 case 0x31: strcpy(insn[i],"C.UN.D"); type=FCOMP; break;
8037 case 0x32: strcpy(insn[i],"C.EQ.D"); type=FCOMP; break;
8038 case 0x33: strcpy(insn[i],"C.UEQ.D"); type=FCOMP; break;
8039 case 0x34: strcpy(insn[i],"C.OLT.D"); type=FCOMP; break;
8040 case 0x35: strcpy(insn[i],"C.ULT.D"); type=FCOMP; break;
8041 case 0x36: strcpy(insn[i],"C.OLE.D"); type=FCOMP; break;
8042 case 0x37: strcpy(insn[i],"C.ULE.D"); type=FCOMP; break;
8043 case 0x38: strcpy(insn[i],"C.SF.D"); type=FCOMP; break;
8044 case 0x39: strcpy(insn[i],"C.NGLE.D"); type=FCOMP; break;
8045 case 0x3A: strcpy(insn[i],"C.SEQ.D"); type=FCOMP; break;
8046 case 0x3B: strcpy(insn[i],"C.NGL.D"); type=FCOMP; break;
8047 case 0x3C: strcpy(insn[i],"C.LT.D"); type=FCOMP; break;
8048 case 0x3D: strcpy(insn[i],"C.NGE.D"); type=FCOMP; break;
8049 case 0x3E: strcpy(insn[i],"C.LE.D"); type=FCOMP; break;
8050 case 0x3F: strcpy(insn[i],"C.NGT.D"); type=FCOMP; break;
8053 case 0x14: strcpy(insn[i],"C1.W"); type=NI;
8054 switch(source[i]&0x3f)
8056 case 0x20: strcpy(insn[i],"CVT.S.W"); type=FCONV; break;
8057 case 0x21: strcpy(insn[i],"CVT.D.W"); type=FCONV; break;
8060 case 0x15: strcpy(insn[i],"C1.L"); type=NI;
8061 switch(source[i]&0x3f)
8063 case 0x20: strcpy(insn[i],"CVT.S.L"); type=FCONV; break;
8064 case 0x21: strcpy(insn[i],"CVT.D.L"); type=FCONV; break;
8069 case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
8070 case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
8071 case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
8072 case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
8074 case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
8075 case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
8076 case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
8077 case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
8079 case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
8080 case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
8081 case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
8082 case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
8083 case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
8084 case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
8085 case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
8086 case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
8087 case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
8088 case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
8089 case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
8090 case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
8092 case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
8093 case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
8095 case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
8096 case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
8097 case 0x30: strcpy(insn[i],"LL"); type=NI; break;
8098 case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
8100 case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
8101 case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
8102 case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
8104 case 0x38: strcpy(insn[i],"SC"); type=NI; break;
8105 case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
8107 case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
8108 case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
8109 case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
8112 case 0x12: strcpy(insn[i],"COP2"); type=NI;
8113 op2=(source[i]>>21)&0x1f;
8116 case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
8117 case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
8118 case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
8119 case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
8121 if (gte_handlers[source[i]&0x3f]!=NULL) {
8122 snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
8128 case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
8129 case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
8130 case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
8132 default: strcpy(insn[i],"???"); type=NI;
8133 printf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
8138 /* Get registers/immediates */
8146 rs1[i]=(source[i]>>21)&0x1f;
8148 rt1[i]=(source[i]>>16)&0x1f;
8150 imm[i]=(short)source[i];
8154 rs1[i]=(source[i]>>21)&0x1f;
8155 rs2[i]=(source[i]>>16)&0x1f;
8158 imm[i]=(short)source[i];
8159 if(op==0x2c||op==0x2d||op==0x3f) us1[i]=rs2[i]; // 64-bit SDL/SDR/SD
8162 // LWL/LWR only load part of the register,
8163 // therefore the target register must be treated as a source too
8164 rs1[i]=(source[i]>>21)&0x1f;
8165 rs2[i]=(source[i]>>16)&0x1f;
8166 rt1[i]=(source[i]>>16)&0x1f;
8168 imm[i]=(short)source[i];
8169 if(op==0x1a||op==0x1b) us1[i]=rs2[i]; // LDR/LDL
8170 if(op==0x26) dep1[i]=rt1[i]; // LWR
8173 if (op==0x0f) rs1[i]=0; // LUI instruction has no source register
8174 else rs1[i]=(source[i]>>21)&0x1f;
8176 rt1[i]=(source[i]>>16)&0x1f;
8178 if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
8179 imm[i]=(unsigned short)source[i];
8181 imm[i]=(short)source[i];
8183 if(op==0x18||op==0x19) us1[i]=rs1[i]; // DADDI/DADDIU
8184 if(op==0x0a||op==0x0b) us1[i]=rs1[i]; // SLTI/SLTIU
8185 if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI
8192 // The JAL instruction writes to r31.
8199 rs1[i]=(source[i]>>21)&0x1f;
8203 // The JALR instruction writes to rd.
8205 rt1[i]=(source[i]>>11)&0x1f;
8210 rs1[i]=(source[i]>>21)&0x1f;
8211 rs2[i]=(source[i]>>16)&0x1f;
8214 if(op&2) { // BGTZ/BLEZ
8222 rs1[i]=(source[i]>>21)&0x1f;
8227 if(op2&0x10) { // BxxAL
8229 // NOTE: If the branch is not taken, r31 is still overwritten
8231 likely[i]=(op2&2)>>1;
8238 likely[i]=((source[i])>>17)&1;
8241 rs1[i]=(source[i]>>21)&0x1f; // source
8242 rs2[i]=(source[i]>>16)&0x1f; // subtract amount
8243 rt1[i]=(source[i]>>11)&0x1f; // destination
8245 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
8246 us1[i]=rs1[i];us2[i]=rs2[i];
8248 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
8249 dep1[i]=rs1[i];dep2[i]=rs2[i];
8251 else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB
8252 dep1[i]=rs1[i];dep2[i]=rs2[i];
8256 rs1[i]=(source[i]>>21)&0x1f; // source
8257 rs2[i]=(source[i]>>16)&0x1f; // divisor
8260 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
8261 us1[i]=rs1[i];us2[i]=rs2[i];
8269 if(op2==0x10) rs1[i]=HIREG; // MFHI
8270 if(op2==0x11) rt1[i]=HIREG; // MTHI
8271 if(op2==0x12) rs1[i]=LOREG; // MFLO
8272 if(op2==0x13) rt1[i]=LOREG; // MTLO
8273 if((op2&0x1d)==0x10) rt1[i]=(source[i]>>11)&0x1f; // MFxx
8274 if((op2&0x1d)==0x11) rs1[i]=(source[i]>>21)&0x1f; // MTxx
8278 rs1[i]=(source[i]>>16)&0x1f; // target of shift
8279 rs2[i]=(source[i]>>21)&0x1f; // shift amount
8280 rt1[i]=(source[i]>>11)&0x1f; // destination
8282 // DSLLV/DSRLV/DSRAV are 64-bit
8283 if(op2>=0x14&&op2<=0x17) us1[i]=rs1[i];
8286 rs1[i]=(source[i]>>16)&0x1f;
8288 rt1[i]=(source[i]>>11)&0x1f;
8290 imm[i]=(source[i]>>6)&0x1f;
8291 // DSxx32 instructions
8292 if(op2>=0x3c) imm[i]|=0x20;
8293 // DSLL/DSRL/DSRA/DSRA32/DSRL32 but not DSLL32 require 64-bit source
8294 if(op2>=0x38&&op2!=0x3c) us1[i]=rs1[i];
8301 if(op2==0) rt1[i]=(source[i]>>16)&0x1F; // MFC0
8302 if(op2==4) rs1[i]=(source[i]>>16)&0x1F; // MTC0
8303 if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status
8304 if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET
8312 if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
8313 if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
8314 if(op2==5) us1[i]=rs1[i]; // DMTC1
8318 rs1[i]=(source[i]>>21)&0x1F;
8322 imm[i]=(short)source[i];
8325 rs1[i]=(source[i]>>21)&0x1F;
8329 imm[i]=(short)source[i];
8357 /* Calculate branch target addresses */
8359 ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
8360 else if(type==CJUMP&&rs1[i]==rs2[i]&&(op&1))
8361 ba[i]=start+i*4+8; // Ignore never taken branch
8362 else if(type==SJUMP&&rs1[i]==0&&!(op2&1))
8363 ba[i]=start+i*4+8; // Ignore never taken branch
8364 else if(type==CJUMP||type==SJUMP||type==FJUMP)
8365 ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
8367 /* Is this the end of the block? */
8368 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
8369 if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
8371 // Does the block continue due to a branch?
8374 if(ba[j]==start+i*4+4) done=j=0;
8375 if(ba[j]==start+i*4+8) done=j=0;
8379 if(stop_after_jal) done=1;
8381 if((source[i+1]&0xfc00003f)==0x0d) done=1;
8383 // Don't recompile stuff that's already compiled
8384 if(check_addr(start+i*4+4)) done=1;
8385 // Don't get too close to the limit
8386 if(i>MAXBLOCK/2) done=1;
8388 if(itype[i]==SYSCALL&&stop_after_jal) done=1;
8389 if(itype[i]==HLECALL) done=1;
8390 //assert(i<MAXBLOCK-1);
8391 if(start+i*4==pagelimit-4) done=1;
8392 assert(start+i*4<pagelimit);
8393 if (i==MAXBLOCK-1) done=1;
8394 // Stop if we're compiling junk
8395 if(itype[i]==NI&&opcode[i]==0x11) {
8396 done=stop_after_jal=1;
8397 printf("Disabled speculative precompilation\n");
8401 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP||itype[i-1]==FJUMP) {
8402 if(start+i*4==pagelimit) {
8408 /* Pass 2 - Register dependencies and branch targets */
8410 unneeded_registers(0,slen-1,0);
8412 /* Pass 3 - Register allocation */
8414 struct regstat current; // Current register allocations/status
8417 current.u=unneeded_reg[0];
8418 current.uu=unneeded_reg_upper[0];
8419 clear_all_regs(current.regmap);
8420 alloc_reg(¤t,0,CCREG);
8421 dirty_reg(¤t,CCREG);
8428 provisional_32bit();
8431 // First instruction is delay slot
8436 unneeded_reg_upper[0]=1;
8437 current.regmap[HOST_BTREG]=BTREG;
8445 for(hr=0;hr<HOST_REGS;hr++)
8447 // Is this really necessary?
8448 if(current.regmap[hr]==0) current.regmap[hr]=-1;
8454 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
8456 if(rs1[i-2]==0||rs2[i-2]==0)
8459 current.is32|=1LL<<rs1[i-2];
8460 int hr=get_reg(current.regmap,rs1[i-2]|64);
8461 if(hr>=0) current.regmap[hr]=-1;
8464 current.is32|=1LL<<rs2[i-2];
8465 int hr=get_reg(current.regmap,rs2[i-2]|64);
8466 if(hr>=0) current.regmap[hr]=-1;
8471 // If something jumps here with 64-bit values
8472 // then promote those registers to 64 bits
8475 uint64_t temp_is32=current.is32;
8478 if(ba[j]==start+i*4)
8479 temp_is32&=branch_regs[j].is32;
8483 if(ba[j]==start+i*4)
8487 if(temp_is32!=current.is32) {
8488 //printf("dumping 32-bit regs (%x)\n",start+i*4);
8489 #ifdef DESTRUCTIVE_WRITEBACK
8490 for(hr=0;hr<HOST_REGS;hr++)
8492 int r=current.regmap[hr];
8495 if((current.dirty>>hr)&((current.is32&~temp_is32)>>r)&1) {
8497 //printf("restore %d\n",r);
8502 current.is32=temp_is32;
8506 memset(p32, 0xff, sizeof(p32));
8510 memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
8511 regs[i].wasconst=current.isconst;
8512 regs[i].was32=current.is32;
8513 regs[i].wasdirty=current.dirty;
8514 #ifdef DESTRUCTIVE_WRITEBACK
8515 // To change a dirty register from 32 to 64 bits, we must write
8516 // it out during the previous cycle (for branches, 2 cycles)
8517 if(i<slen-1&&bt[i+1]&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP)
8519 uint64_t temp_is32=current.is32;
8522 if(ba[j]==start+i*4+4)
8523 temp_is32&=branch_regs[j].is32;
8527 if(ba[j]==start+i*4+4)
8531 if(temp_is32!=current.is32) {
8532 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8533 for(hr=0;hr<HOST_REGS;hr++)
8535 int r=current.regmap[hr];
8538 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8539 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP)
8541 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63))
8543 //printf("dump %d/r%d\n",hr,r);
8544 current.regmap[hr]=-1;
8545 if(get_reg(current.regmap,r|64)>=0)
8546 current.regmap[get_reg(current.regmap,r|64)]=-1;
8554 else if(i<slen-2&&bt[i+2]&&(source[i-1]>>16)!=0x1000&&(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP))
8556 uint64_t temp_is32=current.is32;
8559 if(ba[j]==start+i*4+8)
8560 temp_is32&=branch_regs[j].is32;
8564 if(ba[j]==start+i*4+8)
8568 if(temp_is32!=current.is32) {
8569 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8570 for(hr=0;hr<HOST_REGS;hr++)
8572 int r=current.regmap[hr];
8575 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8576 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63)&&rs1[i+1]!=(r&63)&&rs2[i+1]!=(r&63))
8578 //printf("dump %d/r%d\n",hr,r);
8579 current.regmap[hr]=-1;
8580 if(get_reg(current.regmap,r|64)>=0)
8581 current.regmap[get_reg(current.regmap,r|64)]=-1;
8589 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
8591 current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
8592 current.uu=unneeded_reg_upper[i+1]&~((1LL<<us1[i])|(1LL<<us2[i]));
8593 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8602 current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
8603 current.uu=branch_unneeded_reg_upper[i]&~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
8604 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
8605 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8606 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8609 } else { printf("oops, branch at end of block with no delay slot\n");exit(1); }
8613 ds=0; // Skip delay slot, already allocated as part of branch
8614 // ...but we need to alloc it in case something jumps here
8616 current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
8617 current.uu=branch_unneeded_reg_upper[i-1]&unneeded_reg_upper[i+1];
8619 current.u=branch_unneeded_reg[i-1];
8620 current.uu=branch_unneeded_reg_upper[i-1];
8622 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8623 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8624 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8627 struct regstat temp;
8628 memcpy(&temp,¤t,sizeof(current));
8629 temp.wasdirty=temp.dirty;
8630 temp.was32=temp.is32;
8631 // TODO: Take into account unconditional branches, as below
8632 delayslot_alloc(&temp,i);
8633 memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
8634 regs[i].wasdirty=temp.wasdirty;
8635 regs[i].was32=temp.was32;
8636 regs[i].dirty=temp.dirty;
8637 regs[i].is32=temp.is32;
8641 // Create entry (branch target) regmap
8642 for(hr=0;hr<HOST_REGS;hr++)
8644 int r=temp.regmap[hr];
8646 if(r!=regmap_pre[i][hr]) {
8647 regs[i].regmap_entry[hr]=-1;
8652 if((current.u>>r)&1) {
8653 regs[i].regmap_entry[hr]=-1;
8654 regs[i].regmap[hr]=-1;
8655 //Don't clear regs in the delay slot as the branch might need them
8656 //current.regmap[hr]=-1;
8658 regs[i].regmap_entry[hr]=r;
8661 if((current.uu>>(r&63))&1) {
8662 regs[i].regmap_entry[hr]=-1;
8663 regs[i].regmap[hr]=-1;
8664 //Don't clear regs in the delay slot as the branch might need them
8665 //current.regmap[hr]=-1;
8667 regs[i].regmap_entry[hr]=r;
8671 // First instruction expects CCREG to be allocated
8672 if(i==0&&hr==HOST_CCREG)
8673 regs[i].regmap_entry[hr]=CCREG;
8675 regs[i].regmap_entry[hr]=-1;
8679 else { // Not delay slot
8682 //current.isconst=0; // DEBUG
8683 //current.wasconst=0; // DEBUG
8684 //regs[i].wasconst=0; // DEBUG
8685 clear_const(¤t,rt1[i]);
8686 alloc_cc(¤t,i);
8687 dirty_reg(¤t,CCREG);
8689 alloc_reg(¤t,i,31);
8690 dirty_reg(¤t,31);
8691 assert(rs1[i+1]!=31&&rs2[i+1]!=31);
8693 alloc_reg(¤t,i,PTEMP);
8695 //current.is32|=1LL<<rt1[i];
8697 delayslot_alloc(¤t,i+1);
8698 //current.isconst=0; // DEBUG
8700 //printf("i=%d, isconst=%x\n",i,current.isconst);
8703 //current.isconst=0;
8704 //current.wasconst=0;
8705 //regs[i].wasconst=0;
8706 clear_const(¤t,rs1[i]);
8707 clear_const(¤t,rt1[i]);
8708 alloc_cc(¤t,i);
8709 dirty_reg(¤t,CCREG);
8710 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
8711 alloc_reg(¤t,i,rs1[i]);
8713 alloc_reg(¤t,i,rt1[i]);
8714 dirty_reg(¤t,rt1[i]);
8715 assert(rs1[i+1]!=31&&rs2[i+1]!=31);
8717 alloc_reg(¤t,i,PTEMP);
8721 if(rs1[i]==31) { // JALR
8722 alloc_reg(¤t,i,RHASH);
8723 #ifndef HOST_IMM_ADDR32
8724 alloc_reg(¤t,i,RHTBL);
8728 delayslot_alloc(¤t,i+1);
8730 // The delay slot overwrites our source register,
8731 // allocate a temporary register to hold the old value.
8735 delayslot_alloc(¤t,i+1);
8737 alloc_reg(¤t,i,RTEMP);
8739 //current.isconst=0; // DEBUG
8743 //current.isconst=0;
8744 //current.wasconst=0;
8745 //regs[i].wasconst=0;
8746 clear_const(¤t,rs1[i]);
8747 clear_const(¤t,rs2[i]);
8748 if((opcode[i]&0x3E)==4) // BEQ/BNE
8750 alloc_cc(¤t,i);
8751 dirty_reg(¤t,CCREG);
8752 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
8753 if(rs2[i]) alloc_reg(¤t,i,rs2[i]);
8754 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8756 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
8757 if(rs2[i]) alloc_reg64(¤t,i,rs2[i]);
8759 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
8760 (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) {
8761 // The delay slot overwrites one of our conditions.
8762 // Allocate the branch condition registers instead.
8763 // Note that such a sequence of instructions could
8764 // be considered a bug since the branch can not be
8765 // re-executed if an exception occurs.
8769 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
8770 if(rs2[i]) alloc_reg(¤t,i,rs2[i]);
8771 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8773 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
8774 if(rs2[i]) alloc_reg64(¤t,i,rs2[i]);
8777 else delayslot_alloc(¤t,i+1);
8780 if((opcode[i]&0x3E)==6) // BLEZ/BGTZ
8782 alloc_cc(¤t,i);
8783 dirty_reg(¤t,CCREG);
8784 alloc_reg(¤t,i,rs1[i]);
8785 if(!(current.is32>>rs1[i]&1))
8787 alloc_reg64(¤t,i,rs1[i]);
8789 if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
8790 // The delay slot overwrites one of our conditions.
8791 // Allocate the branch condition registers instead.
8792 // Note that such a sequence of instructions could
8793 // be considered a bug since the branch can not be
8794 // re-executed if an exception occurs.
8798 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
8799 if(!((current.is32>>rs1[i])&1))
8801 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
8804 else delayslot_alloc(¤t,i+1);
8807 // Don't alloc the delay slot yet because we might not execute it
8808 if((opcode[i]&0x3E)==0x14) // BEQL/BNEL
8813 alloc_cc(¤t,i);
8814 dirty_reg(¤t,CCREG);
8815 alloc_reg(¤t,i,rs1[i]);
8816 alloc_reg(¤t,i,rs2[i]);
8817 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8819 alloc_reg64(¤t,i,rs1[i]);
8820 alloc_reg64(¤t,i,rs2[i]);
8824 if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL
8829 alloc_cc(¤t,i);
8830 dirty_reg(¤t,CCREG);
8831 alloc_reg(¤t,i,rs1[i]);
8832 if(!(current.is32>>rs1[i]&1))
8834 alloc_reg64(¤t,i,rs1[i]);
8838 //current.isconst=0;
8841 //current.isconst=0;
8842 //current.wasconst=0;
8843 //regs[i].wasconst=0;
8844 clear_const(¤t,rs1[i]);
8845 clear_const(¤t,rt1[i]);
8846 //if((opcode2[i]&0x1E)==0x0) // BLTZ/BGEZ
8847 if((opcode2[i]&0x0E)==0x0) // BLTZ/BGEZ
8849 alloc_cc(¤t,i);
8850 dirty_reg(¤t,CCREG);
8851 alloc_reg(¤t,i,rs1[i]);
8852 if(!(current.is32>>rs1[i]&1))
8854 alloc_reg64(¤t,i,rs1[i]);
8856 if (rt1[i]==31) { // BLTZAL/BGEZAL
8857 alloc_reg(¤t,i,31);
8858 dirty_reg(¤t,31);
8859 assert(rs1[i+1]!=31&&rs2[i+1]!=31);
8860 //#ifdef REG_PREFETCH
8861 //alloc_reg(¤t,i,PTEMP);
8863 //current.is32|=1LL<<rt1[i];
8865 if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
8866 // The delay slot overwrites the branch condition.
8867 // Allocate the branch condition registers instead.
8868 // Note that such a sequence of instructions could
8869 // be considered a bug since the branch can not be
8870 // re-executed if an exception occurs.
8874 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
8875 if(!((current.is32>>rs1[i])&1))
8877 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
8880 else delayslot_alloc(¤t,i+1);
8883 // Don't alloc the delay slot yet because we might not execute it
8884 if((opcode2[i]&0x1E)==0x2) // BLTZL/BGEZL
8889 alloc_cc(¤t,i);
8890 dirty_reg(¤t,CCREG);
8891 alloc_reg(¤t,i,rs1[i]);
8892 if(!(current.is32>>rs1[i]&1))
8894 alloc_reg64(¤t,i,rs1[i]);
8898 //current.isconst=0;
8904 if(likely[i]==0) // BC1F/BC1T
8906 // TODO: Theoretically we can run out of registers here on x86.
8907 // The delay slot can allocate up to six, and we need to check
8908 // CSREG before executing the delay slot. Possibly we can drop
8909 // the cycle count and then reload it after checking that the
8910 // FPU is in a usable state, or don't do out-of-order execution.
8911 alloc_cc(¤t,i);
8912 dirty_reg(¤t,CCREG);
8913 alloc_reg(¤t,i,FSREG);
8914 alloc_reg(¤t,i,CSREG);
8915 if(itype[i+1]==FCOMP) {
8916 // The delay slot overwrites the branch condition.
8917 // Allocate the branch condition registers instead.
8918 // Note that such a sequence of instructions could
8919 // be considered a bug since the branch can not be
8920 // re-executed if an exception occurs.
8921 alloc_cc(¤t,i);
8922 dirty_reg(¤t,CCREG);
8923 alloc_reg(¤t,i,CSREG);
8924 alloc_reg(¤t,i,FSREG);
8927 delayslot_alloc(¤t,i+1);
8928 alloc_reg(¤t,i+1,CSREG);
8932 // Don't alloc the delay slot yet because we might not execute it
8933 if(likely[i]) // BC1FL/BC1TL
8935 alloc_cc(¤t,i);
8936 dirty_reg(¤t,CCREG);
8937 alloc_reg(¤t,i,CSREG);
8938 alloc_reg(¤t,i,FSREG);
8944 imm16_alloc(¤t,i);
8948 load_alloc(¤t,i);
8952 store_alloc(¤t,i);
8955 alu_alloc(¤t,i);
8958 shift_alloc(¤t,i);
8961 multdiv_alloc(¤t,i);
8964 shiftimm_alloc(¤t,i);
8967 mov_alloc(¤t,i);
8970 cop0_alloc(¤t,i);
8974 cop1_alloc(¤t,i);
8977 c1ls_alloc(¤t,i);
8980 c2ls_alloc(¤t,i);
8983 c2op_alloc(¤t,i);
8986 fconv_alloc(¤t,i);
8989 float_alloc(¤t,i);
8992 fcomp_alloc(¤t,i);
8996 syscall_alloc(¤t,i);
8999 pagespan_alloc(¤t,i);
9003 // Drop the upper half of registers that have become 32-bit
9004 current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i]));
9005 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
9006 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9007 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9010 current.uu|=current.is32&((1LL<<rt1[i+1])|(1LL<<rt2[i+1]));
9011 current.uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
9012 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
9013 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9017 // Create entry (branch target) regmap
9018 for(hr=0;hr<HOST_REGS;hr++)
9021 r=current.regmap[hr];
9023 if(r!=regmap_pre[i][hr]) {
9024 // TODO: delay slot (?)
9025 or=get_reg(regmap_pre[i],r); // Get old mapping for this register
9026 if(or<0||(r&63)>=TEMPREG){
9027 regs[i].regmap_entry[hr]=-1;
9031 // Just move it to a different register
9032 regs[i].regmap_entry[hr]=r;
9033 // If it was dirty before, it's still dirty
9034 if((regs[i].wasdirty>>or)&1) dirty_reg(¤t,r&63);
9041 regs[i].regmap_entry[hr]=0;
9045 if((current.u>>r)&1) {
9046 regs[i].regmap_entry[hr]=-1;
9047 //regs[i].regmap[hr]=-1;
9048 current.regmap[hr]=-1;
9050 regs[i].regmap_entry[hr]=r;
9053 if((current.uu>>(r&63))&1) {
9054 regs[i].regmap_entry[hr]=-1;
9055 //regs[i].regmap[hr]=-1;
9056 current.regmap[hr]=-1;
9058 regs[i].regmap_entry[hr]=r;
9062 // Branches expect CCREG to be allocated at the target
9063 if(regmap_pre[i][hr]==CCREG)
9064 regs[i].regmap_entry[hr]=CCREG;
9066 regs[i].regmap_entry[hr]=-1;
9069 memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
9071 /* Branch post-alloc */
9074 current.was32=current.is32;
9075 current.wasdirty=current.dirty;
9076 switch(itype[i-1]) {
9078 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9079 branch_regs[i-1].isconst=0;
9080 branch_regs[i-1].wasconst=0;
9081 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9082 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9083 alloc_cc(&branch_regs[i-1],i-1);
9084 dirty_reg(&branch_regs[i-1],CCREG);
9085 if(rt1[i-1]==31) { // JAL
9086 alloc_reg(&branch_regs[i-1],i-1,31);
9087 dirty_reg(&branch_regs[i-1],31);
9088 branch_regs[i-1].is32|=1LL<<31;
9090 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9091 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9094 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9095 branch_regs[i-1].isconst=0;
9096 branch_regs[i-1].wasconst=0;
9097 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9098 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9099 alloc_cc(&branch_regs[i-1],i-1);
9100 dirty_reg(&branch_regs[i-1],CCREG);
9101 alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]);
9102 if(rt1[i-1]!=0) { // JALR
9103 alloc_reg(&branch_regs[i-1],i-1,rt1[i-1]);
9104 dirty_reg(&branch_regs[i-1],rt1[i-1]);
9105 branch_regs[i-1].is32|=1LL<<rt1[i-1];
9108 if(rs1[i-1]==31) { // JALR
9109 alloc_reg(&branch_regs[i-1],i-1,RHASH);
9110 #ifndef HOST_IMM_ADDR32
9111 alloc_reg(&branch_regs[i-1],i-1,RHTBL);
9115 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9116 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9119 if((opcode[i-1]&0x3E)==4) // BEQ/BNE
9121 alloc_cc(¤t,i-1);
9122 dirty_reg(¤t,CCREG);
9123 if((rs1[i-1]&&(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]))||
9124 (rs2[i-1]&&(rs2[i-1]==rt1[i]||rs2[i-1]==rt2[i]))) {
9125 // The delay slot overwrote one of our conditions
9126 // Delay slot goes after the test (in order)
9127 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9128 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9129 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9132 delayslot_alloc(¤t,i);
9137 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9138 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9139 // Alloc the branch condition registers
9140 if(rs1[i-1]) alloc_reg(¤t,i-1,rs1[i-1]);
9141 if(rs2[i-1]) alloc_reg(¤t,i-1,rs2[i-1]);
9142 if(!((current.is32>>rs1[i-1])&(current.is32>>rs2[i-1])&1))
9144 if(rs1[i-1]) alloc_reg64(¤t,i-1,rs1[i-1]);
9145 if(rs2[i-1]) alloc_reg64(¤t,i-1,rs2[i-1]);
9148 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9149 branch_regs[i-1].isconst=0;
9150 branch_regs[i-1].wasconst=0;
9151 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9152 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9155 if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ
9157 alloc_cc(¤t,i-1);
9158 dirty_reg(¤t,CCREG);
9159 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9160 // The delay slot overwrote the branch condition
9161 // Delay slot goes after the test (in order)
9162 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9163 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9164 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9167 delayslot_alloc(¤t,i);
9172 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9173 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9174 // Alloc the branch condition register
9175 alloc_reg(¤t,i-1,rs1[i-1]);
9176 if(!(current.is32>>rs1[i-1]&1))
9178 alloc_reg64(¤t,i-1,rs1[i-1]);
9181 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9182 branch_regs[i-1].isconst=0;
9183 branch_regs[i-1].wasconst=0;
9184 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9185 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9188 // Alloc the delay slot in case the branch is taken
9189 if((opcode[i-1]&0x3E)==0x14) // BEQL/BNEL
9191 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9192 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9193 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9194 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9195 alloc_cc(&branch_regs[i-1],i);
9196 dirty_reg(&branch_regs[i-1],CCREG);
9197 delayslot_alloc(&branch_regs[i-1],i);
9198 branch_regs[i-1].isconst=0;
9199 alloc_reg(¤t,i,CCREG); // Not taken path
9200 dirty_reg(¤t,CCREG);
9201 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9204 if((opcode[i-1]&0x3E)==0x16) // BLEZL/BGTZL
9206 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9207 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9208 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9209 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9210 alloc_cc(&branch_regs[i-1],i);
9211 dirty_reg(&branch_regs[i-1],CCREG);
9212 delayslot_alloc(&branch_regs[i-1],i);
9213 branch_regs[i-1].isconst=0;
9214 alloc_reg(¤t,i,CCREG); // Not taken path
9215 dirty_reg(¤t,CCREG);
9216 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9220 //if((opcode2[i-1]&0x1E)==0) // BLTZ/BGEZ
9221 if((opcode2[i-1]&0x0E)==0) // BLTZ/BGEZ
9223 alloc_cc(¤t,i-1);
9224 dirty_reg(¤t,CCREG);
9225 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9226 // The delay slot overwrote the branch condition
9227 // Delay slot goes after the test (in order)
9228 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9229 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9230 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9233 delayslot_alloc(¤t,i);
9238 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9239 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9240 // Alloc the branch condition register
9241 alloc_reg(¤t,i-1,rs1[i-1]);
9242 if(!(current.is32>>rs1[i-1]&1))
9244 alloc_reg64(¤t,i-1,rs1[i-1]);
9247 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9248 branch_regs[i-1].isconst=0;
9249 branch_regs[i-1].wasconst=0;
9250 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9251 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9254 // Alloc the delay slot in case the branch is taken
9255 if((opcode2[i-1]&0x1E)==2) // BLTZL/BGEZL
9257 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9258 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9259 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9260 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9261 alloc_cc(&branch_regs[i-1],i);
9262 dirty_reg(&branch_regs[i-1],CCREG);
9263 delayslot_alloc(&branch_regs[i-1],i);
9264 branch_regs[i-1].isconst=0;
9265 alloc_reg(¤t,i,CCREG); // Not taken path
9266 dirty_reg(¤t,CCREG);
9267 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9269 // FIXME: BLTZAL/BGEZAL
9270 if(opcode2[i-1]&0x10) { // BxxZAL
9271 alloc_reg(&branch_regs[i-1],i-1,31);
9272 dirty_reg(&branch_regs[i-1],31);
9273 branch_regs[i-1].is32|=1LL<<31;
9277 if(likely[i-1]==0) // BC1F/BC1T
9279 alloc_cc(¤t,i-1);
9280 dirty_reg(¤t,CCREG);
9281 if(itype[i]==FCOMP) {
9282 // The delay slot overwrote the branch condition
9283 // Delay slot goes after the test (in order)
9284 delayslot_alloc(¤t,i);
9289 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9290 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9291 // Alloc the branch condition register
9292 alloc_reg(¤t,i-1,FSREG);
9294 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9295 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9299 // Alloc the delay slot in case the branch is taken
9300 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9301 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9302 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9303 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9304 alloc_cc(&branch_regs[i-1],i);
9305 dirty_reg(&branch_regs[i-1],CCREG);
9306 delayslot_alloc(&branch_regs[i-1],i);
9307 branch_regs[i-1].isconst=0;
9308 alloc_reg(¤t,i,CCREG); // Not taken path
9309 dirty_reg(¤t,CCREG);
9310 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9315 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
9317 if(rt1[i-1]==31) // JAL/JALR
9319 // Subroutine call will return here, don't alloc any registers
9322 clear_all_regs(current.regmap);
9323 alloc_reg(¤t,i,CCREG);
9324 dirty_reg(¤t,CCREG);
9328 // Internal branch will jump here, match registers to caller
9329 current.is32=0x3FFFFFFFFLL;
9331 clear_all_regs(current.regmap);
9332 alloc_reg(¤t,i,CCREG);
9333 dirty_reg(¤t,CCREG);
9336 if(ba[j]==start+i*4+4) {
9337 memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
9338 current.is32=branch_regs[j].is32;
9339 current.dirty=branch_regs[j].dirty;
9344 if(ba[j]==start+i*4+4) {
9345 for(hr=0;hr<HOST_REGS;hr++) {
9346 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
9347 current.regmap[hr]=-1;
9349 current.is32&=branch_regs[j].is32;
9350 current.dirty&=branch_regs[j].dirty;
9359 // Count cycles in between branches
9361 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP||itype[i]==SYSCALL||itype[i]==HLECALL))
9370 flush_dirty_uppers(¤t);
9372 regs[i].is32=current.is32;
9373 regs[i].dirty=current.dirty;
9374 regs[i].isconst=current.isconst;
9375 memcpy(constmap[i],current.constmap,sizeof(current.constmap));
9377 for(hr=0;hr<HOST_REGS;hr++) {
9378 if(hr!=EXCLUDE_REG&®s[i].regmap[hr]>=0) {
9379 if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
9380 regs[i].wasconst&=~(1<<hr);
9384 if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
9387 /* Pass 4 - Cull unused host registers */
9391 for (i=slen-1;i>=0;i--)
9394 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9396 if(ba[i]<start || ba[i]>=(start+slen*4))
9398 // Branch out of this block, don't need anything
9404 // Need whatever matches the target
9406 int t=(ba[i]-start)>>2;
9407 for(hr=0;hr<HOST_REGS;hr++)
9409 if(regs[i].regmap_entry[hr]>=0) {
9410 if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
9414 // Conditional branch may need registers for following instructions
9415 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9418 nr|=needed_reg[i+2];
9419 for(hr=0;hr<HOST_REGS;hr++)
9421 if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
9422 //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
9426 // Don't need stuff which is overwritten
9427 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9428 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9429 // Merge in delay slot
9430 for(hr=0;hr<HOST_REGS;hr++)
9433 // These are overwritten unless the branch is "likely"
9434 // and the delay slot is nullified if not taken
9435 if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9436 if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9438 if(us1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9439 if(us2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9440 if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9441 if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9442 if(us1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9443 if(us2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9444 if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9445 if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9446 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1)) {
9447 if(dep1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9448 if(dep2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9450 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1)) {
9451 if(dep1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9452 if(dep2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9454 if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) {
9455 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9456 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9460 else if(itype[i]==SYSCALL||itype[i]==HLECALL)
9462 // SYSCALL instruction (software interrupt)
9465 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
9467 // ERET instruction (return from interrupt)
9473 for(hr=0;hr<HOST_REGS;hr++) {
9474 if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
9475 if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
9476 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9477 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9481 for(hr=0;hr<HOST_REGS;hr++)
9483 // Overwritten registers are not needed
9484 if(rt1[i]&&rt1[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9485 if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9486 if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9487 // Source registers are needed
9488 if(us1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9489 if(us2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9490 if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr;
9491 if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr;
9492 if(us1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9493 if(us2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9494 if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9495 if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9496 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1)) {
9497 if(dep1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9498 if(dep1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9500 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1)) {
9501 if(dep2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9502 if(dep2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9504 if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) {
9505 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9506 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9508 // Don't store a register immediately after writing it,
9509 // may prevent dual-issue.
9510 // But do so if this is a branch target, otherwise we
9511 // might have to load the register before the branch.
9512 if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) {
9513 if((regmap_pre[i][hr]>0&®map_pre[i][hr]<64&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1)) ||
9514 (regmap_pre[i][hr]>64&&!((unneeded_reg_upper[i]>>(regmap_pre[i][hr]&63))&1)) ) {
9515 if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9516 if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9518 if((regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1)) ||
9519 (regs[i].regmap_entry[hr]>64&&!((unneeded_reg_upper[i]>>(regs[i].regmap_entry[hr]&63))&1)) ) {
9520 if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9521 if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9525 // Cycle count is needed at branches. Assume it is needed at the target too.
9526 if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==FJUMP||itype[i]==SPAN) {
9527 if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9528 if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9533 // Deallocate unneeded registers
9534 for(hr=0;hr<HOST_REGS;hr++)
9537 if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
9538 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9539 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9540 (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG)
9542 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9545 regs[i].regmap[hr]=-1;
9546 regs[i].isconst&=~(1<<hr);
9547 if(i<slen-2) regmap_pre[i+2][hr]=-1;
9551 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9553 int d1=0,d2=0,map=0,temp=0;
9554 if(get_reg(regs[i].regmap,rt1[i+1]|64)>=0||get_reg(branch_regs[i].regmap,rt1[i+1]|64)>=0)
9560 if(itype[i+1]==LOAD || itype[i+1]==LOADLR ||
9561 itype[i+1]==STORE || itype[i+1]==STORELR ||
9562 itype[i+1]==C1LS || itype[i+1]==C2LS)
9565 if(itype[i+1]==STORE || itype[i+1]==STORELR ||
9566 (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
9569 if(itype[i+1]==LOADLR || itype[i+1]==STORELR ||
9570 itype[i+1]==C1LS || itype[i+1]==C2LS)
9572 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9573 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9574 (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] &&
9575 (regs[i].regmap[hr]^64)!=us1[i+1] && (regs[i].regmap[hr]^64)!=us2[i+1] &&
9576 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9577 regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] &&
9578 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
9579 regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
9580 regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
9581 regs[i].regmap[hr]!=map )
9583 regs[i].regmap[hr]=-1;
9584 regs[i].isconst&=~(1<<hr);
9585 if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] &&
9586 (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] &&
9587 (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] &&
9588 (branch_regs[i].regmap[hr]^64)!=us1[i+1] && (branch_regs[i].regmap[hr]^64)!=us2[i+1] &&
9589 (branch_regs[i].regmap[hr]^64)!=d1 && (branch_regs[i].regmap[hr]^64)!=d2 &&
9590 branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] &&
9591 (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
9592 branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
9593 branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
9594 branch_regs[i].regmap[hr]!=map)
9596 branch_regs[i].regmap[hr]=-1;
9597 branch_regs[i].regmap_entry[hr]=-1;
9598 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9600 if(!likely[i]&&i<slen-2) {
9601 regmap_pre[i+2][hr]=-1;
9612 int d1=0,d2=0,map=-1,temp=-1;
9613 if(get_reg(regs[i].regmap,rt1[i]|64)>=0)
9619 if(itype[i]==LOAD || itype[i]==LOADLR ||
9620 itype[i]==STORE || itype[i]==STORELR ||
9621 itype[i]==C1LS || itype[i]==C2LS)
9623 } else if(itype[i]==STORE || itype[i]==STORELR ||
9624 (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
9627 if(itype[i]==LOADLR || itype[i]==STORELR ||
9628 itype[i]==C1LS || itype[i]==C2LS)
9630 if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9631 (regs[i].regmap[hr]^64)!=us1[i] && (regs[i].regmap[hr]^64)!=us2[i] &&
9632 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9633 regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] &&
9634 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map &&
9635 (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG))
9637 if(i<slen-1&&!is_ds[i]) {
9638 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]!=-1)
9639 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
9640 if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
9642 printf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
9643 assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
9645 regmap_pre[i+1][hr]=-1;
9646 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
9648 regs[i].regmap[hr]=-1;
9649 regs[i].isconst&=~(1<<hr);
9657 /* Pass 5 - Pre-allocate registers */
9659 // If a register is allocated during a loop, try to allocate it for the
9660 // entire loop, if possible. This avoids loading/storing registers
9661 // inside of the loop.
9663 signed char f_regmap[HOST_REGS];
9664 clear_all_regs(f_regmap);
9665 for(i=0;i<slen-1;i++)
9667 if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9669 if(ba[i]>=start && ba[i]<(start+i*4))
9670 if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
9671 ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
9672 ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
9673 ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
9674 ||itype[i+1]==FCOMP||itype[i+1]==FCONV
9675 ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
9677 int t=(ba[i]-start)>>2;
9678 if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots
9679 if(t<2||(itype[t-2]!=UJUMP)) // call/ret assumes no registers allocated
9680 for(hr=0;hr<HOST_REGS;hr++)
9682 if(regs[i].regmap[hr]>64) {
9683 if(!((regs[i].dirty>>hr)&1))
9684 f_regmap[hr]=regs[i].regmap[hr];
9685 else f_regmap[hr]=-1;
9687 else if(regs[i].regmap[hr]>=0) f_regmap[hr]=regs[i].regmap[hr];
9688 if(branch_regs[i].regmap[hr]>64) {
9689 if(!((branch_regs[i].dirty>>hr)&1))
9690 f_regmap[hr]=branch_regs[i].regmap[hr];
9691 else f_regmap[hr]=-1;
9693 else if(branch_regs[i].regmap[hr]>=0) f_regmap[hr]=branch_regs[i].regmap[hr];
9694 if(itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
9695 ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
9696 ||itype[i+1]==FCOMP||itype[i+1]==FCONV
9697 ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
9699 // Test both in case the delay slot is ooo,
9700 // could be done better...
9701 if(count_free_regs(branch_regs[i].regmap)<2
9702 ||count_free_regs(regs[i].regmap)<2)
9703 f_regmap[hr]=branch_regs[i].regmap[hr];
9705 // Avoid dirty->clean transition
9706 // #ifdef DESTRUCTIVE_WRITEBACK here?
9707 if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
9708 if(f_regmap[hr]>0) {
9709 if(regs[t].regmap_entry[hr]<0) {
9713 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
9714 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
9715 if(r>63&&((unneeded_reg_upper[j]>>(r&63))&1)) break;
9717 // NB This can exclude the case where the upper-half
9718 // register is lower numbered than the lower-half
9719 // register. Not sure if it's worth fixing...
9720 if(get_reg(regs[j].regmap,r&63)<0) break;
9721 if(regs[j].is32&(1LL<<(r&63))) break;
9723 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
9724 //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
9726 if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
9727 if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
9729 if(get_reg(regs[i].regmap,r&63)<0) break;
9730 if(get_reg(branch_regs[i].regmap,r&63)<0) break;
9733 while(k>1&®s[k-1].regmap[hr]==-1) {
9734 if(itype[k-1]==STORE||itype[k-1]==STORELR
9735 ||itype[k-1]==C1LS||itype[k-1]==SHIFT||itype[k-1]==COP1
9736 ||itype[k-1]==FLOAT||itype[k-1]==FCONV||itype[k-1]==FCOMP
9737 ||itype[k-1]==COP2||itype[k-1]==C2LS||itype[k-1]==C2OP) {
9738 if(count_free_regs(regs[k-1].regmap)<2) {
9739 //printf("no free regs for store %x\n",start+(k-1)*4);
9744 if(itype[k-1]!=NOP&&itype[k-1]!=MOV&&itype[k-1]!=ALU&&itype[k-1]!=SHIFTIMM&&itype[k-1]!=IMM16&&itype[k-1]!=LOAD) break;
9745 if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
9746 //printf("no-match due to different register\n");
9749 if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP||itype[k-2]==FJUMP) {
9750 //printf("no-match due to branch\n");
9753 // call/ret fast path assumes no registers allocated
9754 if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)) {
9758 // NB This can exclude the case where the upper-half
9759 // register is lower numbered than the lower-half
9760 // register. Not sure if it's worth fixing...
9761 if(get_reg(regs[k-1].regmap,r&63)<0) break;
9762 if(regs[k-1].is32&(1LL<<(r&63))) break;
9767 if((regs[k].is32&(1LL<<f_regmap[hr]))!=
9768 (regs[i+2].was32&(1LL<<f_regmap[hr]))) {
9769 //printf("bad match after branch\n");
9773 if(regs[k-1].regmap[hr]==f_regmap[hr]&®map_pre[k][hr]==f_regmap[hr]) {
9774 //printf("Extend r%d, %x ->\n",hr,start+k*4);
9776 regs[k].regmap_entry[hr]=f_regmap[hr];
9777 regs[k].regmap[hr]=f_regmap[hr];
9778 regmap_pre[k+1][hr]=f_regmap[hr];
9779 regs[k].wasdirty&=~(1<<hr);
9780 regs[k].dirty&=~(1<<hr);
9781 regs[k].wasdirty|=(1<<hr)®s[k-1].dirty;
9782 regs[k].dirty|=(1<<hr)®s[k].wasdirty;
9783 regs[k].wasconst&=~(1<<hr);
9784 regs[k].isconst&=~(1<<hr);
9789 //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
9792 assert(regs[i-1].regmap[hr]==f_regmap[hr]);
9793 if(regs[i-1].regmap[hr]==f_regmap[hr]&®map_pre[i][hr]==f_regmap[hr]) {
9794 //printf("OK fill %x (r%d)\n",start+i*4,hr);
9795 regs[i].regmap_entry[hr]=f_regmap[hr];
9796 regs[i].regmap[hr]=f_regmap[hr];
9797 regs[i].wasdirty&=~(1<<hr);
9798 regs[i].dirty&=~(1<<hr);
9799 regs[i].wasdirty|=(1<<hr)®s[i-1].dirty;
9800 regs[i].dirty|=(1<<hr)®s[i-1].dirty;
9801 regs[i].wasconst&=~(1<<hr);
9802 regs[i].isconst&=~(1<<hr);
9803 branch_regs[i].regmap_entry[hr]=f_regmap[hr];
9804 branch_regs[i].wasdirty&=~(1<<hr);
9805 branch_regs[i].wasdirty|=(1<<hr)®s[i].dirty;
9806 branch_regs[i].regmap[hr]=f_regmap[hr];
9807 branch_regs[i].dirty&=~(1<<hr);
9808 branch_regs[i].dirty|=(1<<hr)®s[i].dirty;
9809 branch_regs[i].wasconst&=~(1<<hr);
9810 branch_regs[i].isconst&=~(1<<hr);
9811 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
9812 regmap_pre[i+2][hr]=f_regmap[hr];
9813 regs[i+2].wasdirty&=~(1<<hr);
9814 regs[i+2].wasdirty|=(1<<hr)®s[i].dirty;
9815 assert((branch_regs[i].is32&(1LL<<f_regmap[hr]))==
9816 (regs[i+2].was32&(1LL<<f_regmap[hr])));
9821 regs[k].regmap_entry[hr]=f_regmap[hr];
9822 regs[k].regmap[hr]=f_regmap[hr];
9823 regmap_pre[k+1][hr]=f_regmap[hr];
9824 regs[k+1].wasdirty&=~(1<<hr);
9825 regs[k].dirty&=~(1<<hr);
9826 regs[k].wasconst&=~(1<<hr);
9827 regs[k].isconst&=~(1<<hr);
9829 if(regs[j].regmap[hr]==f_regmap[hr])
9830 regs[j].regmap_entry[hr]=f_regmap[hr];
9834 if(regs[j].regmap[hr]>=0)
9836 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
9837 //printf("no-match due to different register\n");
9840 if((regs[j+1].is32&(1LL<<f_regmap[hr]))!=(regs[j].is32&(1LL<<f_regmap[hr]))) {
9841 //printf("32/64 mismatch %x %d\n",start+j*4,hr);
9844 if(itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS
9845 ||itype[j]==SHIFT||itype[j]==COP1||itype[j]==FLOAT
9846 ||itype[j]==FCOMP||itype[j]==FCONV
9847 ||itype[j]==COP2||itype[j]==C2LS||itype[j]==C2OP) {
9848 if(count_free_regs(regs[j].regmap)<2) {
9849 //printf("No free regs for store %x\n",start+j*4);
9853 else if(itype[j]!=NOP&&itype[j]!=MOV&&itype[j]!=ALU&&itype[j]!=SHIFTIMM&&itype[j]!=IMM16&&itype[j]!=LOAD) break;
9854 if(f_regmap[hr]>=64) {
9855 if(regs[j].is32&(1LL<<(f_regmap[hr]&63))) {
9860 if(get_reg(regs[j].regmap,f_regmap[hr]&63)<0) {
9872 for(hr=0;hr<HOST_REGS;hr++)
9874 if(hr!=EXCLUDE_REG) {
9875 if(regs[i].regmap[hr]>64) {
9876 if(!((regs[i].dirty>>hr)&1))
9877 f_regmap[hr]=regs[i].regmap[hr];
9879 else if(regs[i].regmap[hr]>=0) f_regmap[hr]=regs[i].regmap[hr];
9880 else if(regs[i].regmap[hr]<0) count++;
9883 // Try to restore cycle count at branch targets
9885 for(j=i;j<slen-1;j++) {
9886 if(regs[j].regmap[HOST_CCREG]!=-1) break;
9887 if(itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS
9888 ||itype[j]==SHIFT||itype[j]==COP1||itype[j]==FLOAT
9889 ||itype[j]==FCOMP||itype[j]==FCONV
9890 ||itype[j]==COP2||itype[j]==C2LS||itype[j]==C2OP) {
9891 if(count_free_regs(regs[j].regmap)<2) {
9892 //printf("no free regs for store %x\n",start+j*4);
9897 if(itype[j]!=NOP&&itype[j]!=MOV&&itype[j]!=ALU&&itype[j]!=SHIFTIMM&&itype[j]!=IMM16&&itype[j]!=LOAD) break;
9899 if(regs[j].regmap[HOST_CCREG]==CCREG) {
9901 //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
9903 regs[k].regmap_entry[HOST_CCREG]=CCREG;
9904 regs[k].regmap[HOST_CCREG]=CCREG;
9905 regmap_pre[k+1][HOST_CCREG]=CCREG;
9906 regs[k+1].wasdirty|=1<<HOST_CCREG;
9907 regs[k].dirty|=1<<HOST_CCREG;
9908 regs[k].wasconst&=~(1<<HOST_CCREG);
9909 regs[k].isconst&=~(1<<HOST_CCREG);
9912 regs[j].regmap_entry[HOST_CCREG]=CCREG;
9914 // Work backwards from the branch target
9915 if(j>i&&f_regmap[HOST_CCREG]==CCREG)
9917 //printf("Extend backwards\n");
9920 while(regs[k-1].regmap[HOST_CCREG]==-1) {
9921 if(itype[k-1]==STORE||itype[k-1]==STORELR||itype[k-1]==C1LS
9922 ||itype[k-1]==SHIFT||itype[k-1]==COP1||itype[k-1]==FLOAT
9923 ||itype[k-1]==FCONV||itype[k-1]==FCOMP
9924 ||itype[k-1]==COP2||itype[k-1]==C2LS||itype[k-1]==C2OP) {
9925 if(count_free_regs(regs[k-1].regmap)<2) {
9926 //printf("no free regs for store %x\n",start+(k-1)*4);
9931 if(itype[k-1]!=NOP&&itype[k-1]!=MOV&&itype[k-1]!=ALU&&itype[k-1]!=SHIFTIMM&&itype[k-1]!=IMM16&&itype[k-1]!=LOAD) break;
9934 if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
9935 //printf("Extend CC, %x ->\n",start+k*4);
9937 regs[k].regmap_entry[HOST_CCREG]=CCREG;
9938 regs[k].regmap[HOST_CCREG]=CCREG;
9939 regmap_pre[k+1][HOST_CCREG]=CCREG;
9940 regs[k+1].wasdirty|=1<<HOST_CCREG;
9941 regs[k].dirty|=1<<HOST_CCREG;
9942 regs[k].wasconst&=~(1<<HOST_CCREG);
9943 regs[k].isconst&=~(1<<HOST_CCREG);
9948 //printf("Fail Extend CC, %x ->\n",start+k*4);
9952 if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&&
9953 itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&&
9954 itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1&&itype[i]!=FLOAT&&
9955 itype[i]!=FCONV&&itype[i]!=FCOMP&&
9956 itype[i]!=COP2&&itype[i]!=C2LS&&itype[i]!=C2OP)
9958 memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
9963 // This allocates registers (if possible) one instruction prior
9964 // to use, which can avoid a load-use penalty on certain CPUs.
9965 for(i=0;i<slen-1;i++)
9967 if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP))
9971 if(itype[i]==ALU||itype[i]==MOV||itype[i]==LOAD||itype[i]==SHIFTIMM||itype[i]==IMM16
9972 ||((itype[i]==COP1||itype[i]==COP2)&&opcode2[i]<3))
9975 if((hr=get_reg(regs[i+1].regmap,rs1[i+1]))>=0)
9977 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
9979 regs[i].regmap[hr]=regs[i+1].regmap[hr];
9980 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
9981 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
9982 regs[i].isconst&=~(1<<hr);
9983 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
9984 constmap[i][hr]=constmap[i+1][hr];
9985 regs[i+1].wasdirty&=~(1<<hr);
9986 regs[i].dirty&=~(1<<hr);
9991 if((hr=get_reg(regs[i+1].regmap,rs2[i+1]))>=0)
9993 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
9995 regs[i].regmap[hr]=regs[i+1].regmap[hr];
9996 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
9997 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
9998 regs[i].isconst&=~(1<<hr);
9999 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10000 constmap[i][hr]=constmap[i+1][hr];
10001 regs[i+1].wasdirty&=~(1<<hr);
10002 regs[i].dirty&=~(1<<hr);
10006 if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10007 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10009 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10011 regs[i].regmap[hr]=rs1[i+1];
10012 regmap_pre[i+1][hr]=rs1[i+1];
10013 regs[i+1].regmap_entry[hr]=rs1[i+1];
10014 regs[i].isconst&=~(1<<hr);
10015 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10016 constmap[i][hr]=constmap[i+1][hr];
10017 regs[i+1].wasdirty&=~(1<<hr);
10018 regs[i].dirty&=~(1<<hr);
10022 if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10023 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10025 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10027 regs[i].regmap[hr]=rs1[i+1];
10028 regmap_pre[i+1][hr]=rs1[i+1];
10029 regs[i+1].regmap_entry[hr]=rs1[i+1];
10030 regs[i].isconst&=~(1<<hr);
10031 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10032 constmap[i][hr]=constmap[i+1][hr];
10033 regs[i+1].wasdirty&=~(1<<hr);
10034 regs[i].dirty&=~(1<<hr);
10038 #ifndef HOST_IMM_ADDR32
10039 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
10040 hr=get_reg(regs[i+1].regmap,TLREG);
10042 int sr=get_reg(regs[i+1].regmap,rs1[i+1]);
10043 if(sr>=0&&((regs[i+1].wasconst>>sr)&1)) {
10045 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10047 regs[i].regmap[hr]=MGEN1+((i+1)&1);
10048 regmap_pre[i+1][hr]=MGEN1+((i+1)&1);
10049 regs[i+1].regmap_entry[hr]=MGEN1+((i+1)&1);
10050 regs[i].isconst&=~(1<<hr);
10051 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10052 constmap[i][hr]=constmap[i+1][hr];
10053 regs[i+1].wasdirty&=~(1<<hr);
10054 regs[i].dirty&=~(1<<hr);
10056 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10058 // move it to another register
10059 regs[i+1].regmap[hr]=-1;
10060 regmap_pre[i+2][hr]=-1;
10061 regs[i+1].regmap[nr]=TLREG;
10062 regmap_pre[i+2][nr]=TLREG;
10063 regs[i].regmap[nr]=MGEN1+((i+1)&1);
10064 regmap_pre[i+1][nr]=MGEN1+((i+1)&1);
10065 regs[i+1].regmap_entry[nr]=MGEN1+((i+1)&1);
10066 regs[i].isconst&=~(1<<nr);
10067 regs[i+1].isconst&=~(1<<nr);
10068 regs[i].dirty&=~(1<<nr);
10069 regs[i+1].wasdirty&=~(1<<nr);
10070 regs[i+1].dirty&=~(1<<nr);
10071 regs[i+2].wasdirty&=~(1<<nr);
10077 if(itype[i+1]==STORE||itype[i+1]==STORELR
10078 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
10079 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10080 hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
10081 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10082 else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
10084 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10086 regs[i].regmap[hr]=rs1[i+1];
10087 regmap_pre[i+1][hr]=rs1[i+1];
10088 regs[i+1].regmap_entry[hr]=rs1[i+1];
10089 regs[i].isconst&=~(1<<hr);
10090 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10091 constmap[i][hr]=constmap[i+1][hr];
10092 regs[i+1].wasdirty&=~(1<<hr);
10093 regs[i].dirty&=~(1<<hr);
10097 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
10098 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10100 hr=get_reg(regs[i+1].regmap,FTEMP);
10102 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10104 regs[i].regmap[hr]=rs1[i+1];
10105 regmap_pre[i+1][hr]=rs1[i+1];
10106 regs[i+1].regmap_entry[hr]=rs1[i+1];
10107 regs[i].isconst&=~(1<<hr);
10108 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10109 constmap[i][hr]=constmap[i+1][hr];
10110 regs[i+1].wasdirty&=~(1<<hr);
10111 regs[i].dirty&=~(1<<hr);
10113 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10115 // move it to another register
10116 regs[i+1].regmap[hr]=-1;
10117 regmap_pre[i+2][hr]=-1;
10118 regs[i+1].regmap[nr]=FTEMP;
10119 regmap_pre[i+2][nr]=FTEMP;
10120 regs[i].regmap[nr]=rs1[i+1];
10121 regmap_pre[i+1][nr]=rs1[i+1];
10122 regs[i+1].regmap_entry[nr]=rs1[i+1];
10123 regs[i].isconst&=~(1<<nr);
10124 regs[i+1].isconst&=~(1<<nr);
10125 regs[i].dirty&=~(1<<nr);
10126 regs[i+1].wasdirty&=~(1<<nr);
10127 regs[i+1].dirty&=~(1<<nr);
10128 regs[i+2].wasdirty&=~(1<<nr);
10132 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS||||itype[i+1]==C2LS*/) {
10133 if(itype[i+1]==LOAD)
10134 hr=get_reg(regs[i+1].regmap,rt1[i+1]);
10135 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
10136 hr=get_reg(regs[i+1].regmap,FTEMP);
10137 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
10138 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
10139 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10141 if(hr>=0&®s[i].regmap[hr]<0) {
10142 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
10143 if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
10144 regs[i].regmap[hr]=AGEN1+((i+1)&1);
10145 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
10146 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
10147 regs[i].isconst&=~(1<<hr);
10148 regs[i+1].wasdirty&=~(1<<hr);
10149 regs[i].dirty&=~(1<<hr);
10158 /* Pass 6 - Optimize clean/dirty state */
10159 clean_registers(0,slen-1,1);
10161 /* Pass 7 - Identify 32-bit registers */
10167 for (i=slen-1;i>=0;i--)
10170 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10172 if(ba[i]<start || ba[i]>=(start+slen*4))
10174 // Branch out of this block, don't need anything
10180 // Need whatever matches the target
10181 // (and doesn't get overwritten by the delay slot instruction)
10183 int t=(ba[i]-start)>>2;
10184 if(ba[i]>start+i*4) {
10186 if(!(requires_32bit[t]&~regs[i].was32))
10187 r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10190 //if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
10191 // r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10192 if(!(pr32[t]&~regs[i].was32))
10193 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10196 // Conditional branch may need registers for following instructions
10197 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10200 r32|=requires_32bit[i+2];
10201 r32&=regs[i].was32;
10202 // Mark this address as a branch target since it may be called
10203 // upon return from interrupt
10207 // Merge in delay slot
10209 // These are overwritten unless the branch is "likely"
10210 // and the delay slot is nullified if not taken
10211 r32&=~(1LL<<rt1[i+1]);
10212 r32&=~(1LL<<rt2[i+1]);
10214 // Assume these are needed (delay slot)
10217 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
10221 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
10223 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
10225 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
10227 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
10229 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
10232 else if(itype[i]==SYSCALL||itype[i]==HLECALL)
10234 // SYSCALL instruction (software interrupt)
10237 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
10239 // ERET instruction (return from interrupt)
10243 r32&=~(1LL<<rt1[i]);
10244 r32&=~(1LL<<rt2[i]);
10247 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
10251 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
10253 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
10255 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
10257 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
10259 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
10261 requires_32bit[i]=r32;
10263 // Dirty registers which are 32-bit, require 32-bit input
10264 // as they will be written as 32-bit values
10265 for(hr=0;hr<HOST_REGS;hr++)
10267 if(regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64) {
10268 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
10269 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
10270 requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
10274 //requires_32bit[i]=is32[i]&~unneeded_reg_upper[i]; // DEBUG
10277 if(itype[slen-1]==SPAN) {
10278 bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
10281 /* Debug/disassembly */
10282 if((void*)assem_debug==(void*)printf)
10283 for(i=0;i<slen;i++)
10287 for(r=1;r<=CCREG;r++) {
10288 if((unneeded_reg[i]>>r)&1) {
10289 if(r==HIREG) printf(" HI");
10290 else if(r==LOREG) printf(" LO");
10291 else printf(" r%d",r);
10296 for(r=1;r<=CCREG;r++) {
10297 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
10298 if(r==HIREG) printf(" HI");
10299 else if(r==LOREG) printf(" LO");
10300 else printf(" r%d",r);
10304 for(r=0;r<=CCREG;r++) {
10305 //if(((is32[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10306 if((regs[i].was32>>r)&1) {
10307 if(r==CCREG) printf(" CC");
10308 else if(r==HIREG) printf(" HI");
10309 else if(r==LOREG) printf(" LO");
10310 else printf(" r%d",r);
10315 #if defined(__i386__) || defined(__x86_64__)
10316 printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
10319 printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
10322 if(needed_reg[i]&1) printf("eax ");
10323 if((needed_reg[i]>>1)&1) printf("ecx ");
10324 if((needed_reg[i]>>2)&1) printf("edx ");
10325 if((needed_reg[i]>>3)&1) printf("ebx ");
10326 if((needed_reg[i]>>5)&1) printf("ebp ");
10327 if((needed_reg[i]>>6)&1) printf("esi ");
10328 if((needed_reg[i]>>7)&1) printf("edi ");
10330 for(r=0;r<=CCREG;r++) {
10331 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10332 if((requires_32bit[i]>>r)&1) {
10333 if(r==CCREG) printf(" CC");
10334 else if(r==HIREG) printf(" HI");
10335 else if(r==LOREG) printf(" LO");
10336 else printf(" r%d",r);
10341 for(r=0;r<=CCREG;r++) {
10342 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10343 if((pr32[i]>>r)&1) {
10344 if(r==CCREG) printf(" CC");
10345 else if(r==HIREG) printf(" HI");
10346 else if(r==LOREG) printf(" LO");
10347 else printf(" r%d",r);
10350 if(pr32[i]!=requires_32bit[i]) printf(" OOPS");
10352 #if defined(__i386__) || defined(__x86_64__)
10353 printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
10355 if(regs[i].wasdirty&1) printf("eax ");
10356 if((regs[i].wasdirty>>1)&1) printf("ecx ");
10357 if((regs[i].wasdirty>>2)&1) printf("edx ");
10358 if((regs[i].wasdirty>>3)&1) printf("ebx ");
10359 if((regs[i].wasdirty>>5)&1) printf("ebp ");
10360 if((regs[i].wasdirty>>6)&1) printf("esi ");
10361 if((regs[i].wasdirty>>7)&1) printf("edi ");
10364 printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
10366 if(regs[i].wasdirty&1) printf("r0 ");
10367 if((regs[i].wasdirty>>1)&1) printf("r1 ");
10368 if((regs[i].wasdirty>>2)&1) printf("r2 ");
10369 if((regs[i].wasdirty>>3)&1) printf("r3 ");
10370 if((regs[i].wasdirty>>4)&1) printf("r4 ");
10371 if((regs[i].wasdirty>>5)&1) printf("r5 ");
10372 if((regs[i].wasdirty>>6)&1) printf("r6 ");
10373 if((regs[i].wasdirty>>7)&1) printf("r7 ");
10374 if((regs[i].wasdirty>>8)&1) printf("r8 ");
10375 if((regs[i].wasdirty>>9)&1) printf("r9 ");
10376 if((regs[i].wasdirty>>10)&1) printf("r10 ");
10377 if((regs[i].wasdirty>>12)&1) printf("r12 ");
10380 disassemble_inst(i);
10381 //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
10382 #if defined(__i386__) || defined(__x86_64__)
10383 printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
10384 if(regs[i].dirty&1) printf("eax ");
10385 if((regs[i].dirty>>1)&1) printf("ecx ");
10386 if((regs[i].dirty>>2)&1) printf("edx ");
10387 if((regs[i].dirty>>3)&1) printf("ebx ");
10388 if((regs[i].dirty>>5)&1) printf("ebp ");
10389 if((regs[i].dirty>>6)&1) printf("esi ");
10390 if((regs[i].dirty>>7)&1) printf("edi ");
10393 printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
10394 if(regs[i].dirty&1) printf("r0 ");
10395 if((regs[i].dirty>>1)&1) printf("r1 ");
10396 if((regs[i].dirty>>2)&1) printf("r2 ");
10397 if((regs[i].dirty>>3)&1) printf("r3 ");
10398 if((regs[i].dirty>>4)&1) printf("r4 ");
10399 if((regs[i].dirty>>5)&1) printf("r5 ");
10400 if((regs[i].dirty>>6)&1) printf("r6 ");
10401 if((regs[i].dirty>>7)&1) printf("r7 ");
10402 if((regs[i].dirty>>8)&1) printf("r8 ");
10403 if((regs[i].dirty>>9)&1) printf("r9 ");
10404 if((regs[i].dirty>>10)&1) printf("r10 ");
10405 if((regs[i].dirty>>12)&1) printf("r12 ");
10408 if(regs[i].isconst) {
10409 printf("constants: ");
10410 #if defined(__i386__) || defined(__x86_64__)
10411 if(regs[i].isconst&1) printf("eax=%x ",(int)constmap[i][0]);
10412 if((regs[i].isconst>>1)&1) printf("ecx=%x ",(int)constmap[i][1]);
10413 if((regs[i].isconst>>2)&1) printf("edx=%x ",(int)constmap[i][2]);
10414 if((regs[i].isconst>>3)&1) printf("ebx=%x ",(int)constmap[i][3]);
10415 if((regs[i].isconst>>5)&1) printf("ebp=%x ",(int)constmap[i][5]);
10416 if((regs[i].isconst>>6)&1) printf("esi=%x ",(int)constmap[i][6]);
10417 if((regs[i].isconst>>7)&1) printf("edi=%x ",(int)constmap[i][7]);
10420 if(regs[i].isconst&1) printf("r0=%x ",(int)constmap[i][0]);
10421 if((regs[i].isconst>>1)&1) printf("r1=%x ",(int)constmap[i][1]);
10422 if((regs[i].isconst>>2)&1) printf("r2=%x ",(int)constmap[i][2]);
10423 if((regs[i].isconst>>3)&1) printf("r3=%x ",(int)constmap[i][3]);
10424 if((regs[i].isconst>>4)&1) printf("r4=%x ",(int)constmap[i][4]);
10425 if((regs[i].isconst>>5)&1) printf("r5=%x ",(int)constmap[i][5]);
10426 if((regs[i].isconst>>6)&1) printf("r6=%x ",(int)constmap[i][6]);
10427 if((regs[i].isconst>>7)&1) printf("r7=%x ",(int)constmap[i][7]);
10428 if((regs[i].isconst>>8)&1) printf("r8=%x ",(int)constmap[i][8]);
10429 if((regs[i].isconst>>9)&1) printf("r9=%x ",(int)constmap[i][9]);
10430 if((regs[i].isconst>>10)&1) printf("r10=%x ",(int)constmap[i][10]);
10431 if((regs[i].isconst>>12)&1) printf("r12=%x ",(int)constmap[i][12]);
10437 for(r=0;r<=CCREG;r++) {
10438 if((regs[i].is32>>r)&1) {
10439 if(r==CCREG) printf(" CC");
10440 else if(r==HIREG) printf(" HI");
10441 else if(r==LOREG) printf(" LO");
10442 else printf(" r%d",r);
10448 for(r=0;r<=CCREG;r++) {
10449 if((p32[i]>>r)&1) {
10450 if(r==CCREG) printf(" CC");
10451 else if(r==HIREG) printf(" HI");
10452 else if(r==LOREG) printf(" LO");
10453 else printf(" r%d",r);
10456 if(p32[i]!=regs[i].is32) printf(" NO MATCH\n");
10457 else printf("\n");*/
10458 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10459 #if defined(__i386__) || defined(__x86_64__)
10460 printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
10461 if(branch_regs[i].dirty&1) printf("eax ");
10462 if((branch_regs[i].dirty>>1)&1) printf("ecx ");
10463 if((branch_regs[i].dirty>>2)&1) printf("edx ");
10464 if((branch_regs[i].dirty>>3)&1) printf("ebx ");
10465 if((branch_regs[i].dirty>>5)&1) printf("ebp ");
10466 if((branch_regs[i].dirty>>6)&1) printf("esi ");
10467 if((branch_regs[i].dirty>>7)&1) printf("edi ");
10470 printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
10471 if(branch_regs[i].dirty&1) printf("r0 ");
10472 if((branch_regs[i].dirty>>1)&1) printf("r1 ");
10473 if((branch_regs[i].dirty>>2)&1) printf("r2 ");
10474 if((branch_regs[i].dirty>>3)&1) printf("r3 ");
10475 if((branch_regs[i].dirty>>4)&1) printf("r4 ");
10476 if((branch_regs[i].dirty>>5)&1) printf("r5 ");
10477 if((branch_regs[i].dirty>>6)&1) printf("r6 ");
10478 if((branch_regs[i].dirty>>7)&1) printf("r7 ");
10479 if((branch_regs[i].dirty>>8)&1) printf("r8 ");
10480 if((branch_regs[i].dirty>>9)&1) printf("r9 ");
10481 if((branch_regs[i].dirty>>10)&1) printf("r10 ");
10482 if((branch_regs[i].dirty>>12)&1) printf("r12 ");
10486 for(r=0;r<=CCREG;r++) {
10487 if((branch_regs[i].is32>>r)&1) {
10488 if(r==CCREG) printf(" CC");
10489 else if(r==HIREG) printf(" HI");
10490 else if(r==LOREG) printf(" LO");
10491 else printf(" r%d",r);
10499 /* Pass 8 - Assembly */
10500 linkcount=0;stubcount=0;
10501 ds=0;is_delayslot=0;
10503 uint64_t is32_pre=0;
10505 u_int beginning=(u_int)out;
10506 if((u_int)addr&1) {
10510 u_int instr_addr0_override=0;
10513 if (start == 0x80030000) {
10514 // nasty hack for fastbios thing
10515 instr_addr0_override=(u_int)out;
10516 emit_movimm(start,0);
10517 emit_readword((int)&pcaddr,1);
10518 emit_writeword(0,(int)&pcaddr);
10520 emit_jne((int)new_dyna_leave);
10523 for(i=0;i<slen;i++)
10525 //if(ds) printf("ds: ");
10526 if((void*)assem_debug==(void*)printf) disassemble_inst(i);
10528 ds=0; // Skip delay slot
10529 if(bt[i]) assem_debug("OOPS - branch into delay slot\n");
10532 #ifndef DESTRUCTIVE_WRITEBACK
10533 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
10535 wb_sx(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,is32_pre,regs[i].was32,
10536 unneeded_reg[i],unneeded_reg_upper[i]);
10537 wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre,
10538 unneeded_reg[i],unneeded_reg_upper[i]);
10540 is32_pre=regs[i].is32;
10541 dirty_pre=regs[i].dirty;
10544 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
10546 wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32,
10547 unneeded_reg[i],unneeded_reg_upper[i]);
10548 loop_preload(regmap_pre[i],regs[i].regmap_entry);
10550 // branch target entry point
10551 instr_addr[i]=(u_int)out;
10552 assem_debug("<->\n");
10554 if(regs[i].regmap_entry[HOST_CCREG]==CCREG&®s[i].regmap[HOST_CCREG]!=CCREG)
10555 wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32);
10556 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
10557 address_generation(i,®s[i],regs[i].regmap_entry);
10558 load_consts(regmap_pre[i],regs[i].regmap,regs[i].was32,i);
10559 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10561 // Load the delay slot registers if necessary
10562 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
10563 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
10564 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
10565 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
10566 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a)
10567 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
10571 // Preload registers for following instruction
10572 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
10573 if(rs1[i+1]!=rt1[i]&&rs1[i+1]!=rt2[i])
10574 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
10575 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
10576 if(rs2[i+1]!=rt1[i]&&rs2[i+1]!=rt2[i])
10577 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
10579 // TODO: if(is_ooo(i)) address_generation(i+1);
10580 if(itype[i]==CJUMP||itype[i]==FJUMP)
10581 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
10582 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a)
10583 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
10584 if(bt[i]) cop1_usable=0;
10588 alu_assemble(i,®s[i]);break;
10590 imm16_assemble(i,®s[i]);break;
10592 shift_assemble(i,®s[i]);break;
10594 shiftimm_assemble(i,®s[i]);break;
10596 load_assemble(i,®s[i]);break;
10598 loadlr_assemble(i,®s[i]);break;
10600 store_assemble(i,®s[i]);break;
10602 storelr_assemble(i,®s[i]);break;
10604 cop0_assemble(i,®s[i]);break;
10606 cop1_assemble(i,®s[i]);break;
10608 c1ls_assemble(i,®s[i]);break;
10610 cop2_assemble(i,®s[i]);break;
10612 c2ls_assemble(i,®s[i]);break;
10614 c2op_assemble(i,®s[i]);break;
10616 fconv_assemble(i,®s[i]);break;
10618 float_assemble(i,®s[i]);break;
10620 fcomp_assemble(i,®s[i]);break;
10622 multdiv_assemble(i,®s[i]);break;
10624 mov_assemble(i,®s[i]);break;
10626 syscall_assemble(i,®s[i]);break;
10628 hlecall_assemble(i,®s[i]);break;
10630 ujump_assemble(i,®s[i]);ds=1;break;
10632 rjump_assemble(i,®s[i]);ds=1;break;
10634 cjump_assemble(i,®s[i]);ds=1;break;
10636 sjump_assemble(i,®s[i]);ds=1;break;
10638 fjump_assemble(i,®s[i]);ds=1;break;
10640 pagespan_assemble(i,®s[i]);break;
10642 if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
10643 literal_pool(1024);
10645 literal_pool_jumpover(256);
10648 //assert(itype[i-2]==UJUMP||itype[i-2]==RJUMP||(source[i-2]>>16)==0x1000);
10649 // If the block did not end with an unconditional branch,
10650 // add a jump to the next instruction.
10652 if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) {
10653 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
10655 if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP&&itype[i-2]!=FJUMP) {
10656 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
10657 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
10658 emit_loadreg(CCREG,HOST_CCREG);
10659 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
10661 else if(!likely[i-2])
10663 store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].is32,branch_regs[i-2].dirty,start+i*4);
10664 assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
10668 store_regs_bt(regs[i-2].regmap,regs[i-2].is32,regs[i-2].dirty,start+i*4);
10669 assert(regs[i-2].regmap[HOST_CCREG]==CCREG);
10671 add_to_linker((int)out,start+i*4,0);
10678 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
10679 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
10680 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
10681 emit_loadreg(CCREG,HOST_CCREG);
10682 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
10683 add_to_linker((int)out,start+i*4,0);
10687 // TODO: delay slot stubs?
10689 for(i=0;i<stubcount;i++)
10691 switch(stubs[i][0])
10699 do_readstub(i);break;
10704 do_writestub(i);break;
10706 do_ccstub(i);break;
10708 do_invstub(i);break;
10710 do_cop1stub(i);break;
10712 do_unalignedwritestub(i);break;
10716 if (instr_addr0_override)
10717 instr_addr[0] = instr_addr0_override;
10719 /* Pass 9 - Linker */
10720 for(i=0;i<linkcount;i++)
10722 assem_debug("%8x -> %8x\n",link_addr[i][0],link_addr[i][1]);
10724 if(!link_addr[i][2])
10727 void *addr=check_addr(link_addr[i][1]);
10728 emit_extjump(link_addr[i][0],link_addr[i][1]);
10730 set_jump_target(link_addr[i][0],(int)addr);
10731 add_link(link_addr[i][1],stub);
10733 else set_jump_target(link_addr[i][0],(int)stub);
10738 int target=(link_addr[i][1]-start)>>2;
10739 assert(target>=0&&target<slen);
10740 assert(instr_addr[target]);
10741 //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
10742 //set_jump_target_fillslot(link_addr[i][0],instr_addr[target],link_addr[i][2]>>1);
10744 set_jump_target(link_addr[i][0],instr_addr[target]);
10748 // External Branch Targets (jump_in)
10749 if(copy+slen*4>(void *)shadow+sizeof(shadow)) copy=shadow;
10750 for(i=0;i<slen;i++)
10754 if(instr_addr[i]) // TODO - delay slots (=null)
10756 u_int vaddr=start+i*4;
10757 u_int page=get_page(vaddr);
10758 u_int vpage=get_vpage(vaddr);
10760 //if(!(is32[i]&(~unneeded_reg_upper[i])&~(1LL<<CCREG)))
10761 if(!requires_32bit[i])
10763 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
10764 assem_debug("jump_in: %x\n",start+i*4);
10765 ll_add(jump_dirty+vpage,vaddr,(void *)out);
10766 int entry_point=do_dirty_stub(i);
10767 ll_add(jump_in+page,vaddr,(void *)entry_point);
10768 // If there was an existing entry in the hash table,
10769 // replace it with the new address.
10770 // Don't add new entries. We'll insert the
10771 // ones that actually get used in check_addr().
10772 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
10773 if(ht_bin[0]==vaddr) {
10774 ht_bin[1]=entry_point;
10776 if(ht_bin[2]==vaddr) {
10777 ht_bin[3]=entry_point;
10782 u_int r=requires_32bit[i]|!!(requires_32bit[i]>>32);
10783 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
10784 assem_debug("jump_in: %x (restricted - %x)\n",start+i*4,r);
10785 //int entry_point=(int)out;
10786 ////assem_debug("entry_point: %x\n",entry_point);
10787 //load_regs_entry(i);
10788 //if(entry_point==(int)out)
10789 // entry_point=instr_addr[i];
10791 // emit_jmp(instr_addr[i]);
10792 //ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
10793 ll_add_32(jump_dirty+vpage,vaddr,r,(void *)out);
10794 int entry_point=do_dirty_stub(i);
10795 ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
10800 // Write out the literal pool if necessary
10802 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
10804 if(((u_int)out)&7) emit_addnop(13);
10806 assert((u_int)out-beginning<MAX_OUTPUT_BLOCK_SIZE);
10807 //printf("shadow buffer: %x-%x\n",(int)copy,(int)copy+slen*4);
10808 memcpy(copy,source,slen*4);
10812 __clear_cache((void *)beginning,out);
10815 // If we're within 256K of the end of the buffer,
10816 // start over from the beginning. (Is 256K enough?)
10817 if((int)out>BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR;
10819 // Trap writes to any of the pages we compiled
10820 for(i=start>>12;i<=(start+slen*4)>>12;i++) {
10822 #ifndef DISABLE_TLB
10823 memory_map[i]|=0x40000000;
10824 if((signed int)start>=(signed int)0xC0000000) {
10826 j=(((u_int)i<<12)+(memory_map[i]<<2)-(u_int)rdram+(u_int)0x80000000)>>12;
10828 memory_map[j]|=0x40000000;
10829 //printf("write protect physical page: %x (virtual %x)\n",j<<12,start);
10834 /* Pass 10 - Free memory by expiring oldest blocks */
10836 int end=((((int)out-BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535;
10837 while(expirep!=end)
10839 int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
10840 int base=BASE_ADDR+((expirep>>13)<<shift); // Base address of this block
10841 inv_debug("EXP: Phase %d\n",expirep);
10842 switch((expirep>>11)&3)
10845 // Clear jump_in and jump_dirty
10846 ll_remove_matching_addrs(jump_in+(expirep&2047),base,shift);
10847 ll_remove_matching_addrs(jump_dirty+(expirep&2047),base,shift);
10848 ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base,shift);
10849 ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base,shift);
10853 ll_kill_pointers(jump_out[expirep&2047],base,shift);
10854 ll_kill_pointers(jump_out[(expirep&2047)+2048],base,shift);
10857 // Clear hash table
10858 for(i=0;i<32;i++) {
10859 int *ht_bin=hash_table[((expirep&2047)<<5)+i];
10860 if((ht_bin[3]>>shift)==(base>>shift) ||
10861 ((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
10862 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[2],ht_bin[3]);
10863 ht_bin[2]=ht_bin[3]=-1;
10865 if((ht_bin[1]>>shift)==(base>>shift) ||
10866 ((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
10867 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[0],ht_bin[1]);
10868 ht_bin[0]=ht_bin[2];
10869 ht_bin[1]=ht_bin[3];
10870 ht_bin[2]=ht_bin[3]=-1;
10876 ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);
10877 ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base,shift);
10880 expirep=(expirep+1)&65535;
10885 // vim:shiftwidth=2:expandtab