2 * (C) GraÅžvydas "notaz" Ignotas, 2010-2011
4 * This work is licensed under the terms of GNU GPL version 2 or later.
5 * See the COPYING file in the top-level directory.
18 #error the dynarec does not have Thumb support, please remove -mthumb
21 //#define memprintf printf
22 #define memprintf(...)
24 static u32 *mem_readtab;
25 static u32 *mem_writetab;
26 static u32 mem_iortab[(1+2+4) * 0x1000 / 4];
27 static u32 mem_iowtab[(1+2+4) * 0x1000 / 4];
28 static u32 mem_ffwtab[(1+2+4) * 0x1000 / 4];
29 //static u32 mem_unmrtab[(1+2+4) * 0x1000 / 4];
30 static u32 mem_unmwtab[(1+2+4) * 0x1000 / 4];
32 static void map_item(u32 *out, const void *h, u32 flag)
36 fprintf(stderr, "FATAL: %p has LSB set\n", h);
39 *out = (hv >> 1) | (flag << 31);
42 // size must be power of 2, at least 4k
43 #define map_l1_mem(tab, i, addr, size, base) \
44 map_item(&tab[((addr)>>12) + i], (u8 *)(base) - (u32)(addr) - ((i << 12) & ~(size - 1)), 0)
46 #define IOMEM32(a) (((a) & 0xfff) / 4)
47 #define IOMEM16(a) (0x1000/4 + (((a) & 0xfff) / 2))
48 #define IOMEM8(a) (0x1000/4 + 0x1000/2 + ((a) & 0xfff))
57 static void write_mem_dummy(u32 data)
59 memprintf("unmapped w %08x, %08x @%08x %u\n", address, data, psxRegs.pc, psxRegs.cycle);
63 static u32 io_read_sio16()
65 return sioRead8() | (sioRead8() << 8);
68 static u32 io_read_sio32()
70 return sioRead8() | (sioRead8() << 8) | (sioRead8() << 16) | (sioRead8() << 24);
73 static void io_write_sio16(u32 value)
75 sioWrite8((unsigned char)value);
76 sioWrite8((unsigned char)(value>>8));
79 static void io_write_sio32(u32 value)
81 sioWrite8((unsigned char)value);
82 sioWrite8((unsigned char)(value >> 8));
83 sioWrite8((unsigned char)(value >> 16));
84 sioWrite8((unsigned char)(value >> 24));
89 static void map_rcnt_rcount0(u32 mode)
91 if (mode & 0x100) { // pixel clock
92 map_item(&mem_iortab[IOMEM32(0x1100)], rcnt0_read_count_m1, 1);
93 map_item(&mem_iortab[IOMEM16(0x1100)], rcnt0_read_count_m1, 1);
96 map_item(&mem_iortab[IOMEM32(0x1100)], rcnt0_read_count_m0, 1);
97 map_item(&mem_iortab[IOMEM16(0x1100)], rcnt0_read_count_m0, 1);
101 static void map_rcnt_rcount1(u32 mode)
103 if (mode & 0x100) { // hcnt
104 map_item(&mem_iortab[IOMEM32(0x1110)], rcnt1_read_count_m1, 1);
105 map_item(&mem_iortab[IOMEM16(0x1110)], rcnt1_read_count_m1, 1);
108 map_item(&mem_iortab[IOMEM32(0x1110)], rcnt1_read_count_m0, 1);
109 map_item(&mem_iortab[IOMEM16(0x1110)], rcnt1_read_count_m0, 1);
113 static void map_rcnt_rcount2(u32 mode)
115 if (mode & 0x01) { // gate
116 map_item(&mem_iortab[IOMEM32(0x1120)], &psxH[0x1000], 0);
117 map_item(&mem_iortab[IOMEM16(0x1120)], &psxH[0x1000], 0);
119 else if (mode & 0x200) { // clk/8
120 map_item(&mem_iortab[IOMEM32(0x1120)], rcnt2_read_count_m1, 1);
121 map_item(&mem_iortab[IOMEM16(0x1120)], rcnt2_read_count_m1, 1);
124 map_item(&mem_iortab[IOMEM32(0x1120)], rcnt2_read_count_m0, 1);
125 map_item(&mem_iortab[IOMEM16(0x1120)], rcnt2_read_count_m0, 1);
130 #define map_rcnt_rcount0(mode)
131 #define map_rcnt_rcount1(mode)
132 #define map_rcnt_rcount2(mode)
135 #define make_rcnt_funcs(i) \
136 static u32 io_rcnt_read_count##i() { return psxRcntRcount(i); } \
137 static u32 io_rcnt_read_mode##i() { return psxRcntRmode(i); } \
138 static u32 io_rcnt_read_target##i() { return psxRcntRtarget(i); } \
139 static void io_rcnt_write_count##i(u32 val) { psxRcntWcount(i, val & 0xffff); } \
140 static void io_rcnt_write_mode##i(u32 val) { psxRcntWmode(i, val); map_rcnt_rcount##i(val); } \
141 static void io_rcnt_write_target##i(u32 val) { psxRcntWtarget(i, val & 0xffff); }
147 static void io_write_ireg16(u32 value)
149 if (Config.Sio) psxHu16ref(0x1070) |= 0x80;
150 if (Config.SpuIrq) psxHu16ref(0x1070) |= 0x200;
151 psxHu16ref(0x1070) &= psxHu16(0x1074) & value;
154 static void io_write_imask16(u32 value)
156 psxHu16ref(0x1074) = value;
157 if (psxHu16ref(0x1070) & value)
158 new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
161 static void io_write_ireg32(u32 value)
163 if (Config.Sio) psxHu32ref(0x1070) |= 0x80;
164 if (Config.SpuIrq) psxHu32ref(0x1070) |= 0x200;
165 psxHu32ref(0x1070) &= psxHu32(0x1074) & value;
168 static void io_write_imask32(u32 value)
170 psxHu32ref(0x1074) = value;
171 if (psxHu32ref(0x1070) & value)
172 new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
175 static void io_write_dma_icr32(u32 value)
177 u32 tmp = value & 0x00ff803f;
178 tmp |= (SWAPu32(HW_DMA_ICR) & ~value) & 0x7f000000;
179 if ((tmp & HW_DMA_ICR_GLOBAL_ENABLE && tmp & 0x7f000000)
180 || tmp & HW_DMA_ICR_BUS_ERROR) {
181 if (!(SWAPu32(HW_DMA_ICR) & HW_DMA_ICR_IRQ_SENT))
182 psxHu32ref(0x1070) |= SWAP32(8);
183 tmp |= HW_DMA_ICR_IRQ_SENT;
185 HW_DMA_ICR = SWAPu32(tmp);
188 #define make_dma_func(n) \
189 static void io_write_chcr##n(u32 value) \
191 HW_DMA##n##_CHCR = value; \
192 if (value & 0x01000000 && HW_DMA_PCR & (8 << (n * 4))) { \
193 psxDma##n(HW_DMA##n##_MADR, HW_DMA##n##_BCR, value); \
204 static void io_spu_write16(u32 value)
207 SPU_writeRegister(address, value);
210 static void io_spu_write32(u32 value)
212 SPUwriteRegister wfunc = SPU_writeRegister;
215 wfunc(a, value & 0xffff);
216 wfunc(a + 2, value >> 16);
219 static u32 io_gpu_read_status(void)
223 // meh2, syncing for img bit, might want to avoid it..
227 // XXX: because of large timeslices can't use hSyncCount, using rough
228 // approximization instead. Perhaps better use hcounter code here or something.
229 if (hSyncCount < 240 && (HW_GPU_STATUS & PSXGPU_ILACE_BITS) != PSXGPU_ILACE_BITS)
230 v |= PSXGPU_LCF & (psxRegs.cycle << 20);
234 static void io_gpu_write_status(u32 value)
236 GPU_writeStatus(value);
240 static void map_ram_write(void)
244 for (i = 0; i < (0x800000 >> 12); i++) {
245 map_l1_mem(mem_writetab, i, 0x80000000, 0x200000, psxM);
246 map_l1_mem(mem_writetab, i, 0x00000000, 0x200000, psxM);
247 map_l1_mem(mem_writetab, i, 0xa0000000, 0x200000, psxM);
251 static void unmap_ram_write(void)
255 for (i = 0; i < (0x800000 >> 12); i++) {
256 map_item(&mem_writetab[0x80000|i], mem_unmwtab, 1);
257 map_item(&mem_writetab[0x00000|i], mem_unmwtab, 1);
258 map_item(&mem_writetab[0xa0000|i], mem_unmwtab, 1);
262 static void write_biu(u32 value)
264 memprintf("write_biu %08x, %08x @%08x %u\n", address, value, psxRegs.pc, psxRegs.cycle);
266 if (address != 0xfffe0130)
270 case 0x800: case 0x804:
273 case 0: case 0x1e988:
277 printf("write_biu: unexpected val: %08x\n", value);
282 void new_dyna_pcsx_mem_load_state(void)
284 map_rcnt_rcount0(rcnts[0].mode);
285 map_rcnt_rcount1(rcnts[1].mode);
286 map_rcnt_rcount2(rcnts[2].mode);
289 int pcsxmem_is_handler_dynamic(u_int addr)
291 if ((addr & 0xfffff000) != 0x1f801000)
295 return addr == 0x1100 || addr == 0x1110 || addr == 0x1120;
298 void new_dyna_pcsx_mem_init(void)
302 #ifdef CUSTOM_MEMMAPS
303 // WIZ lack-of-RAM hack
304 extern void *memtab_mmap(void *addr, size_t size);
305 mem_readtab = memtab_mmap((void *)0x08000000, 0x200000 * 4);
307 // have to map these further to keep tcache close to .text
308 mem_readtab = mmap((void *)0x08000000, 0x200000 * 4, PROT_READ | PROT_WRITE,
309 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
311 if (mem_readtab == MAP_FAILED) {
312 fprintf(stderr, "failed to map mem tables\n");
315 mem_writetab = mem_readtab + 0x100000;
321 // 0: direct mem variable
324 // default/unmapped memhandlers
325 for (i = 0; i < 0x100000; i++) {
326 //map_item(&mem_readtab[i], mem_unmrtab, 1);
327 map_l1_mem(mem_readtab, i, 0, 0x1000, zero_mem);
328 map_item(&mem_writetab[i], mem_unmwtab, 1);
331 // RAM and it's mirrors
332 for (i = 0; i < (0x800000 >> 12); i++) {
333 map_l1_mem(mem_readtab, i, 0x80000000, 0x200000, psxM);
334 map_l1_mem(mem_readtab, i, 0x00000000, 0x200000, psxM);
335 map_l1_mem(mem_readtab, i, 0xa0000000, 0x200000, psxM);
339 // BIOS and it's mirrors
340 for (i = 0; i < (0x80000 >> 12); i++) {
341 map_l1_mem(mem_readtab, i, 0x1fc00000, 0x80000, psxR);
342 map_l1_mem(mem_readtab, i, 0xbfc00000, 0x80000, psxR);
346 map_l1_mem(mem_readtab, 0, 0x1f800000, 0x1000, psxH);
347 map_l1_mem(mem_writetab, 0, 0x1f800000, 0x1000, psxH);
350 map_item(&mem_readtab[0x1f801000 >> 12], mem_iortab, 1);
351 map_item(&mem_writetab[0x1f801000 >> 12], mem_iowtab, 1);
355 for (i = 0; i < (1+2+4) * 0x1000 / 4; i++)
356 map_item(&mem_unmwtab[i], write_mem_dummy, 1);
359 for (i = 0; i < 0x1000/4; i++) {
360 map_item(&mem_iortab[i], &psxH[0x1000], 0);
361 map_item(&mem_iowtab[i], &psxH[0x1000], 0);
363 for (; i < 0x1000/4 + 0x1000/2; i++) {
364 map_item(&mem_iortab[i], &psxH[0x1000], 0);
365 map_item(&mem_iowtab[i], &psxH[0x1000], 0);
367 for (; i < 0x1000/4 + 0x1000/2 + 0x1000; i++) {
368 map_item(&mem_iortab[i], &psxH[0x1000], 0);
369 map_item(&mem_iowtab[i], &psxH[0x1000], 0);
372 map_item(&mem_iortab[IOMEM32(0x1040)], io_read_sio32, 1);
373 map_item(&mem_iortab[IOMEM32(0x1100)], io_rcnt_read_count0, 1);
374 map_item(&mem_iortab[IOMEM32(0x1104)], io_rcnt_read_mode0, 1);
375 map_item(&mem_iortab[IOMEM32(0x1108)], io_rcnt_read_target0, 1);
376 map_item(&mem_iortab[IOMEM32(0x1110)], io_rcnt_read_count1, 1);
377 map_item(&mem_iortab[IOMEM32(0x1114)], io_rcnt_read_mode1, 1);
378 map_item(&mem_iortab[IOMEM32(0x1118)], io_rcnt_read_target1, 1);
379 map_item(&mem_iortab[IOMEM32(0x1120)], io_rcnt_read_count2, 1);
380 map_item(&mem_iortab[IOMEM32(0x1124)], io_rcnt_read_mode2, 1);
381 map_item(&mem_iortab[IOMEM32(0x1128)], io_rcnt_read_target2, 1);
382 // map_item(&mem_iortab[IOMEM32(0x1810)], GPU_readData, 1);
383 map_item(&mem_iortab[IOMEM32(0x1814)], io_gpu_read_status, 1);
384 map_item(&mem_iortab[IOMEM32(0x1820)], mdecRead0, 1);
385 map_item(&mem_iortab[IOMEM32(0x1824)], mdecRead1, 1);
387 map_item(&mem_iortab[IOMEM16(0x1040)], io_read_sio16, 1);
388 map_item(&mem_iortab[IOMEM16(0x1044)], sioReadStat16, 1);
389 map_item(&mem_iortab[IOMEM16(0x1048)], sioReadMode16, 1);
390 map_item(&mem_iortab[IOMEM16(0x104a)], sioReadCtrl16, 1);
391 map_item(&mem_iortab[IOMEM16(0x104e)], sioReadBaud16, 1);
392 map_item(&mem_iortab[IOMEM16(0x1100)], io_rcnt_read_count0, 1);
393 map_item(&mem_iortab[IOMEM16(0x1104)], io_rcnt_read_mode0, 1);
394 map_item(&mem_iortab[IOMEM16(0x1108)], io_rcnt_read_target0, 1);
395 map_item(&mem_iortab[IOMEM16(0x1110)], io_rcnt_read_count1, 1);
396 map_item(&mem_iortab[IOMEM16(0x1114)], io_rcnt_read_mode1, 1);
397 map_item(&mem_iortab[IOMEM16(0x1118)], io_rcnt_read_target1, 1);
398 map_item(&mem_iortab[IOMEM16(0x1120)], io_rcnt_read_count2, 1);
399 map_item(&mem_iortab[IOMEM16(0x1124)], io_rcnt_read_mode2, 1);
400 map_item(&mem_iortab[IOMEM16(0x1128)], io_rcnt_read_target2, 1);
402 map_item(&mem_iortab[IOMEM8(0x1040)], sioRead8, 1);
403 map_item(&mem_iortab[IOMEM8(0x1800)], cdrRead0, 1);
404 map_item(&mem_iortab[IOMEM8(0x1801)], cdrRead1, 1);
405 map_item(&mem_iortab[IOMEM8(0x1802)], cdrRead2, 1);
406 map_item(&mem_iortab[IOMEM8(0x1803)], cdrRead3, 1);
409 map_item(&mem_iowtab[IOMEM32(0x1040)], io_write_sio32, 1);
410 map_item(&mem_iowtab[IOMEM32(0x1070)], io_write_ireg32, 1);
411 map_item(&mem_iowtab[IOMEM32(0x1074)], io_write_imask32, 1);
412 map_item(&mem_iowtab[IOMEM32(0x1088)], io_write_chcr0, 1);
413 map_item(&mem_iowtab[IOMEM32(0x1098)], io_write_chcr1, 1);
414 map_item(&mem_iowtab[IOMEM32(0x10a8)], io_write_chcr2, 1);
415 map_item(&mem_iowtab[IOMEM32(0x10b8)], io_write_chcr3, 1);
416 map_item(&mem_iowtab[IOMEM32(0x10c8)], io_write_chcr4, 1);
417 map_item(&mem_iowtab[IOMEM32(0x10e8)], io_write_chcr6, 1);
418 map_item(&mem_iowtab[IOMEM32(0x10f4)], io_write_dma_icr32, 1);
419 map_item(&mem_iowtab[IOMEM32(0x1100)], io_rcnt_write_count0, 1);
420 map_item(&mem_iowtab[IOMEM32(0x1104)], io_rcnt_write_mode0, 1);
421 map_item(&mem_iowtab[IOMEM32(0x1108)], io_rcnt_write_target0, 1);
422 map_item(&mem_iowtab[IOMEM32(0x1110)], io_rcnt_write_count1, 1);
423 map_item(&mem_iowtab[IOMEM32(0x1114)], io_rcnt_write_mode1, 1);
424 map_item(&mem_iowtab[IOMEM32(0x1118)], io_rcnt_write_target1, 1);
425 map_item(&mem_iowtab[IOMEM32(0x1120)], io_rcnt_write_count2, 1);
426 map_item(&mem_iowtab[IOMEM32(0x1124)], io_rcnt_write_mode2, 1);
427 map_item(&mem_iowtab[IOMEM32(0x1128)], io_rcnt_write_target2, 1);
428 // map_item(&mem_iowtab[IOMEM32(0x1810)], GPU_writeData, 1);
429 map_item(&mem_iowtab[IOMEM32(0x1814)], io_gpu_write_status, 1);
430 map_item(&mem_iowtab[IOMEM32(0x1820)], mdecWrite0, 1);
431 map_item(&mem_iowtab[IOMEM32(0x1824)], mdecWrite1, 1);
433 map_item(&mem_iowtab[IOMEM16(0x1040)], io_write_sio16, 1);
434 map_item(&mem_iowtab[IOMEM16(0x1044)], sioWriteStat16, 1);
435 map_item(&mem_iowtab[IOMEM16(0x1048)], sioWriteMode16, 1);
436 map_item(&mem_iowtab[IOMEM16(0x104a)], sioWriteCtrl16, 1);
437 map_item(&mem_iowtab[IOMEM16(0x104e)], sioWriteBaud16, 1);
438 map_item(&mem_iowtab[IOMEM16(0x1070)], io_write_ireg16, 1);
439 map_item(&mem_iowtab[IOMEM16(0x1074)], io_write_imask16, 1);
440 map_item(&mem_iowtab[IOMEM16(0x1100)], io_rcnt_write_count0, 1);
441 map_item(&mem_iowtab[IOMEM16(0x1104)], io_rcnt_write_mode0, 1);
442 map_item(&mem_iowtab[IOMEM16(0x1108)], io_rcnt_write_target0, 1);
443 map_item(&mem_iowtab[IOMEM16(0x1110)], io_rcnt_write_count1, 1);
444 map_item(&mem_iowtab[IOMEM16(0x1114)], io_rcnt_write_mode1, 1);
445 map_item(&mem_iowtab[IOMEM16(0x1118)], io_rcnt_write_target1, 1);
446 map_item(&mem_iowtab[IOMEM16(0x1120)], io_rcnt_write_count2, 1);
447 map_item(&mem_iowtab[IOMEM16(0x1124)], io_rcnt_write_mode2, 1);
448 map_item(&mem_iowtab[IOMEM16(0x1128)], io_rcnt_write_target2, 1);
450 map_item(&mem_iowtab[IOMEM8(0x1040)], sioWrite8, 1);
451 map_item(&mem_iowtab[IOMEM8(0x1800)], cdrWrite0, 1);
452 map_item(&mem_iowtab[IOMEM8(0x1801)], cdrWrite1, 1);
453 map_item(&mem_iowtab[IOMEM8(0x1802)], cdrWrite2, 1);
454 map_item(&mem_iowtab[IOMEM8(0x1803)], cdrWrite3, 1);
456 for (i = 0x1c00; i < 0x1e00; i += 2) {
457 map_item(&mem_iowtab[IOMEM16(i)], io_spu_write16, 1);
458 map_item(&mem_iowtab[IOMEM32(i)], io_spu_write32, 1);
462 map_item(&mem_writetab[0xfffe0130 >> 12], mem_ffwtab, 1);
463 for (i = 0; i < 0x1000/4 + 0x1000/2 + 0x1000; i++)
464 map_item(&mem_ffwtab[i], write_biu, 1);
466 mem_rtab = mem_readtab;
467 mem_wtab = mem_writetab;
469 new_dyna_pcsx_mem_load_state();
472 void new_dyna_pcsx_mem_reset(void)
476 // plugins might change so update the pointers
477 map_item(&mem_iortab[IOMEM32(0x1810)], GPU_readData, 1);
479 for (i = 0x1c00; i < 0x1e00; i += 2)
480 map_item(&mem_iortab[IOMEM16(i)], SPU_readRegister, 1);
482 map_item(&mem_iowtab[IOMEM32(0x1810)], GPU_writeData, 1);