2 * (C) GraÅžvydas "notaz" Ignotas, 2010-2011
4 * This work is licensed under the terms of GNU GPL version 2 or later.
5 * See the COPYING file in the top-level directory.
16 //#define memprintf printf
17 #define memprintf(...)
19 static u32 *mem_readtab;
20 static u32 *mem_writetab;
21 static u32 mem_iortab[(1+2+4) * 0x1000 / 4];
22 static u32 mem_iowtab[(1+2+4) * 0x1000 / 4];
23 static u32 mem_ffwtab[(1+2+4) * 0x1000 / 4];
24 //static u32 mem_unmrtab[(1+2+4) * 0x1000 / 4];
25 static u32 mem_unmwtab[(1+2+4) * 0x1000 / 4];
27 static void map_item(u32 *out, const void *h, u32 flag)
31 fprintf(stderr, "%p has LSB set\n", h);
32 *out = (hv >> 1) | (flag << 31);
35 // size must be power of 2, at least 4k
36 #define map_l1_mem(tab, i, addr, size, base) \
37 map_item(&tab[((addr)>>12) + i], (u8 *)(base) - (u32)(addr) - ((i << 12) & ~(size - 1)), 0)
39 #define IOMEM32(a) (((a) & 0xfff) / 4)
40 #define IOMEM16(a) (0x1000/4 + (((a) & 0xfff) / 2))
41 #define IOMEM8(a) (0x1000/4 + 0x1000/2 + ((a) & 0xfff))
50 static void write_mem_dummy(u32 data)
52 memprintf("unmapped w %08x, %08x @%08x %u\n", address, data, psxRegs.pc, psxRegs.cycle);
56 static u32 io_read_sio16()
58 return sioRead8() | (sioRead8() << 8);
61 static u32 io_read_sio32()
63 return sioRead8() | (sioRead8() << 8) | (sioRead8() << 16) | (sioRead8() << 24);
66 static void io_write_sio16(u32 value)
68 sioWrite8((unsigned char)value);
69 sioWrite8((unsigned char)(value>>8));
72 static void io_write_sio32(u32 value)
74 sioWrite8((unsigned char)value);
75 sioWrite8((unsigned char)(value >> 8));
76 sioWrite8((unsigned char)(value >> 16));
77 sioWrite8((unsigned char)(value >> 24));
80 static void map_rcnt_rcount0(u32 mode)
82 if (mode & 0x01) { // gate
83 map_item(&mem_iortab[IOMEM32(0x1100)], &psxH[0x1000], 0);
84 map_item(&mem_iortab[IOMEM16(0x1100)], &psxH[0x1000], 0);
86 else if (mode & 0x100) { // pixel clock
87 map_item(&mem_iortab[IOMEM32(0x1100)], rcnt0_read_count_m1, 1);
88 map_item(&mem_iortab[IOMEM16(0x1100)], rcnt0_read_count_m1, 1);
91 map_item(&mem_iortab[IOMEM32(0x1100)], rcnt0_read_count_m0, 1);
92 map_item(&mem_iortab[IOMEM16(0x1100)], rcnt0_read_count_m0, 1);
96 static void map_rcnt_rcount1(u32 mode)
98 if (mode & 0x01) { // gate
99 map_item(&mem_iortab[IOMEM32(0x1110)], &psxH[0x1000], 0);
100 map_item(&mem_iortab[IOMEM16(0x1110)], &psxH[0x1000], 0);
102 else if (mode & 0x100) { // hcnt
103 map_item(&mem_iortab[IOMEM32(0x1110)], rcnt1_read_count_m1, 1);
104 map_item(&mem_iortab[IOMEM16(0x1110)], rcnt1_read_count_m1, 1);
107 map_item(&mem_iortab[IOMEM32(0x1110)], rcnt1_read_count_m0, 1);
108 map_item(&mem_iortab[IOMEM16(0x1110)], rcnt1_read_count_m0, 1);
112 static void map_rcnt_rcount2(u32 mode)
114 if (mode & 0x01) { // gate
115 map_item(&mem_iortab[IOMEM32(0x1120)], &psxH[0x1000], 0);
116 map_item(&mem_iortab[IOMEM16(0x1120)], &psxH[0x1000], 0);
118 else if (mode & 0x200) { // clk/8
119 map_item(&mem_iortab[IOMEM32(0x1120)], rcnt2_read_count_m1, 1);
120 map_item(&mem_iortab[IOMEM16(0x1120)], rcnt2_read_count_m1, 1);
123 map_item(&mem_iortab[IOMEM32(0x1120)], rcnt2_read_count_m0, 1);
124 map_item(&mem_iortab[IOMEM16(0x1120)], rcnt2_read_count_m0, 1);
128 #define make_rcnt_funcs(i) \
129 static u32 io_rcnt_read_count##i() { return psxRcntRcount(i); } \
130 static u32 io_rcnt_read_mode##i() { return psxRcntRmode(i); } \
131 static u32 io_rcnt_read_target##i() { return psxRcntRtarget(i); } \
132 static void io_rcnt_write_count##i(u32 val) { psxRcntWcount(i, val & 0xffff); } \
133 static void io_rcnt_write_mode##i(u32 val) { psxRcntWmode(i, val); map_rcnt_rcount##i(val); } \
134 static void io_rcnt_write_target##i(u32 val) { psxRcntWtarget(i, val & 0xffff); }
140 static void io_write_ireg16(u32 value)
142 if (Config.Sio) psxHu16ref(0x1070) |= 0x80;
143 if (Config.SpuIrq) psxHu16ref(0x1070) |= 0x200;
144 psxHu16ref(0x1070) &= psxHu16(0x1074) & value;
147 static void io_write_imask16(u32 value)
149 psxHu16ref(0x1074) = value;
150 if (psxHu16ref(0x1070) & value)
151 new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
154 static void io_write_ireg32(u32 value)
156 if (Config.Sio) psxHu32ref(0x1070) |= 0x80;
157 if (Config.SpuIrq) psxHu32ref(0x1070) |= 0x200;
158 psxHu32ref(0x1070) &= psxHu32(0x1074) & value;
161 static void io_write_imask32(u32 value)
163 psxHu32ref(0x1074) = value;
164 if (psxHu32ref(0x1070) & value)
165 new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
168 static void io_write_dma_icr32(u32 value)
170 u32 tmp = value & 0x00ff803f;
171 tmp |= (SWAPu32(HW_DMA_ICR) & ~value) & 0x7f000000;
172 if ((tmp & HW_DMA_ICR_GLOBAL_ENABLE && tmp & 0x7f000000)
173 || tmp & HW_DMA_ICR_BUS_ERROR) {
174 if (!(SWAPu32(HW_DMA_ICR) & HW_DMA_ICR_IRQ_SENT))
175 psxHu32ref(0x1070) |= SWAP32(8);
176 tmp |= HW_DMA_ICR_IRQ_SENT;
178 HW_DMA_ICR = SWAPu32(tmp);
181 #define make_dma_func(n) \
182 static void io_write_chcr##n(u32 value) \
184 HW_DMA##n##_CHCR = value; \
185 if (value & 0x01000000 && HW_DMA_PCR & (8 << (n * 4))) { \
186 psxDma##n(HW_DMA##n##_MADR, HW_DMA##n##_BCR, value); \
197 static void io_spu_write16(u32 value)
200 SPU_writeRegister(address, value);
203 static void io_spu_write32(u32 value)
205 SPUwriteRegister wfunc = SPU_writeRegister;
208 wfunc(a, value & 0xffff);
209 wfunc(a + 2, value >> 16);
212 static void map_ram_write(void)
216 for (i = 0; i < (0x800000 >> 12); i++) {
217 map_l1_mem(mem_writetab, i, 0x80000000, 0x200000, psxM);
218 map_l1_mem(mem_writetab, i, 0x00000000, 0x200000, psxM);
219 map_l1_mem(mem_writetab, i, 0xa0000000, 0x200000, psxM);
223 static void unmap_ram_write(void)
227 for (i = 0; i < (0x800000 >> 12); i++) {
228 map_item(&mem_writetab[0x80000|i], mem_unmwtab, 1);
229 map_item(&mem_writetab[0x00000|i], mem_unmwtab, 1);
230 map_item(&mem_writetab[0xa0000|i], mem_unmwtab, 1);
234 static void write_biu(u32 value)
236 memprintf("write_biu %08x, %08x @%08x %u\n", address, value, psxRegs.pc, psxRegs.cycle);
238 if (address != 0xfffe0130)
242 case 0x800: case 0x804:
245 case 0: case 0x1e988:
249 printf("write_biu: unexpected val: %08x\n", value);
254 void new_dyna_pcsx_mem_load_state(void)
256 map_rcnt_rcount0(rcnts[0].mode);
257 map_rcnt_rcount1(rcnts[1].mode);
258 map_rcnt_rcount2(rcnts[2].mode);
261 int pcsxmem_is_handler_dynamic(u_int addr)
263 if ((addr & 0xfffff000) != 0x1f801000)
267 return addr == 0x1100 || addr == 0x1110 || addr == 0x1120;
270 void new_dyna_pcsx_mem_init(void)
274 // have to map these further to keep tcache close to .text
275 mem_readtab = mmap((void *)0x08000000, 0x200000 * 4, PROT_READ | PROT_WRITE,
276 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
277 if (mem_readtab == MAP_FAILED) {
278 fprintf(stderr, "failed to map mem tables\n");
281 mem_writetab = mem_readtab + 0x100000;
287 // 0: direct mem variable
290 // default/unmapped memhandlers
291 for (i = 0; i < 0x100000; i++) {
292 //map_item(&mem_readtab[i], mem_unmrtab, 1);
293 map_l1_mem(mem_readtab, i, 0, 0x1000, zero_mem);
294 map_item(&mem_writetab[i], mem_unmwtab, 1);
297 // RAM and it's mirrors
298 for (i = 0; i < (0x800000 >> 12); i++) {
299 map_l1_mem(mem_readtab, i, 0x80000000, 0x200000, psxM);
300 map_l1_mem(mem_readtab, i, 0x00000000, 0x200000, psxM);
301 map_l1_mem(mem_readtab, i, 0xa0000000, 0x200000, psxM);
305 // BIOS and it's mirrors
306 for (i = 0; i < (0x80000 >> 12); i++) {
307 map_l1_mem(mem_readtab, i, 0x1fc00000, 0x80000, psxR);
308 map_l1_mem(mem_readtab, i, 0xbfc00000, 0x80000, psxR);
312 map_l1_mem(mem_readtab, 0, 0x1f800000, 0x1000, psxH);
313 map_l1_mem(mem_writetab, 0, 0x1f800000, 0x1000, psxH);
316 map_item(&mem_readtab[0x1f801000 >> 12], mem_iortab, 1);
317 map_item(&mem_writetab[0x1f801000 >> 12], mem_iowtab, 1);
321 for (i = 0; i < (1+2+4) * 0x1000 / 4; i++)
322 map_item(&mem_unmwtab[i], write_mem_dummy, 1);
325 for (i = 0; i < 0x1000/4; i++) {
326 map_item(&mem_iortab[i], &psxH[0x1000], 0);
327 map_item(&mem_iowtab[i], &psxH[0x1000], 0);
329 for (; i < 0x1000/4 + 0x1000/2; i++) {
330 map_item(&mem_iortab[i], &psxH[0x1000], 0);
331 map_item(&mem_iowtab[i], &psxH[0x1000], 0);
333 for (; i < 0x1000/4 + 0x1000/2 + 0x1000; i++) {
334 map_item(&mem_iortab[i], &psxH[0x1000], 0);
335 map_item(&mem_iowtab[i], &psxH[0x1000], 0);
338 map_item(&mem_iortab[IOMEM32(0x1040)], io_read_sio32, 1);
339 map_item(&mem_iortab[IOMEM32(0x1100)], io_rcnt_read_count0, 1);
340 map_item(&mem_iortab[IOMEM32(0x1104)], io_rcnt_read_mode0, 1);
341 map_item(&mem_iortab[IOMEM32(0x1108)], io_rcnt_read_target0, 1);
342 map_item(&mem_iortab[IOMEM32(0x1110)], io_rcnt_read_count1, 1);
343 map_item(&mem_iortab[IOMEM32(0x1114)], io_rcnt_read_mode1, 1);
344 map_item(&mem_iortab[IOMEM32(0x1118)], io_rcnt_read_target1, 1);
345 map_item(&mem_iortab[IOMEM32(0x1120)], io_rcnt_read_count2, 1);
346 map_item(&mem_iortab[IOMEM32(0x1124)], io_rcnt_read_mode2, 1);
347 map_item(&mem_iortab[IOMEM32(0x1128)], io_rcnt_read_target2, 1);
348 // map_item(&mem_iortab[IOMEM32(0x1810)], GPU_readData, 1);
349 // map_item(&mem_iortab[IOMEM32(0x1814)], GPU_readStatus, 1);
350 map_item(&mem_iortab[IOMEM32(0x1820)], mdecRead0, 1);
351 map_item(&mem_iortab[IOMEM32(0x1824)], mdecRead1, 1);
353 map_item(&mem_iortab[IOMEM16(0x1040)], io_read_sio16, 1);
354 map_item(&mem_iortab[IOMEM16(0x1044)], sioReadStat16, 1);
355 map_item(&mem_iortab[IOMEM16(0x1048)], sioReadMode16, 1);
356 map_item(&mem_iortab[IOMEM16(0x104a)], sioReadCtrl16, 1);
357 map_item(&mem_iortab[IOMEM16(0x104e)], sioReadBaud16, 1);
358 map_item(&mem_iortab[IOMEM16(0x1100)], io_rcnt_read_count0, 1);
359 map_item(&mem_iortab[IOMEM16(0x1104)], io_rcnt_read_mode0, 1);
360 map_item(&mem_iortab[IOMEM16(0x1108)], io_rcnt_read_target0, 1);
361 map_item(&mem_iortab[IOMEM16(0x1110)], io_rcnt_read_count1, 1);
362 map_item(&mem_iortab[IOMEM16(0x1114)], io_rcnt_read_mode1, 1);
363 map_item(&mem_iortab[IOMEM16(0x1118)], io_rcnt_read_target1, 1);
364 map_item(&mem_iortab[IOMEM16(0x1120)], io_rcnt_read_count2, 1);
365 map_item(&mem_iortab[IOMEM16(0x1124)], io_rcnt_read_mode2, 1);
366 map_item(&mem_iortab[IOMEM16(0x1128)], io_rcnt_read_target2, 1);
368 map_item(&mem_iortab[IOMEM8(0x1040)], sioRead8, 1);
369 map_item(&mem_iortab[IOMEM8(0x1800)], cdrRead0, 1);
370 map_item(&mem_iortab[IOMEM8(0x1801)], cdrRead1, 1);
371 map_item(&mem_iortab[IOMEM8(0x1802)], cdrRead2, 1);
372 map_item(&mem_iortab[IOMEM8(0x1803)], cdrRead3, 1);
375 map_item(&mem_iowtab[IOMEM32(0x1040)], io_write_sio32, 1);
376 map_item(&mem_iowtab[IOMEM32(0x1070)], io_write_ireg32, 1);
377 map_item(&mem_iowtab[IOMEM32(0x1074)], io_write_imask32, 1);
378 map_item(&mem_iowtab[IOMEM32(0x1088)], io_write_chcr0, 1);
379 map_item(&mem_iowtab[IOMEM32(0x1098)], io_write_chcr1, 1);
380 map_item(&mem_iowtab[IOMEM32(0x10a8)], io_write_chcr2, 1);
381 map_item(&mem_iowtab[IOMEM32(0x10b8)], io_write_chcr3, 1);
382 map_item(&mem_iowtab[IOMEM32(0x10c8)], io_write_chcr4, 1);
383 map_item(&mem_iowtab[IOMEM32(0x10e8)], io_write_chcr6, 1);
384 map_item(&mem_iowtab[IOMEM32(0x10f4)], io_write_dma_icr32, 1);
385 map_item(&mem_iowtab[IOMEM32(0x1100)], io_rcnt_write_count0, 1);
386 map_item(&mem_iowtab[IOMEM32(0x1104)], io_rcnt_write_mode0, 1);
387 map_item(&mem_iowtab[IOMEM32(0x1108)], io_rcnt_write_target0, 1);
388 map_item(&mem_iowtab[IOMEM32(0x1110)], io_rcnt_write_count1, 1);
389 map_item(&mem_iowtab[IOMEM32(0x1114)], io_rcnt_write_mode1, 1);
390 map_item(&mem_iowtab[IOMEM32(0x1118)], io_rcnt_write_target1, 1);
391 map_item(&mem_iowtab[IOMEM32(0x1120)], io_rcnt_write_count2, 1);
392 map_item(&mem_iowtab[IOMEM32(0x1124)], io_rcnt_write_mode2, 1);
393 map_item(&mem_iowtab[IOMEM32(0x1128)], io_rcnt_write_target2, 1);
394 // map_item(&mem_iowtab[IOMEM32(0x1810)], GPU_writeData, 1);
395 // map_item(&mem_iowtab[IOMEM32(0x1814)], GPU_writeStatus, 1);
396 map_item(&mem_iowtab[IOMEM32(0x1820)], mdecWrite0, 1);
397 map_item(&mem_iowtab[IOMEM32(0x1824)], mdecWrite1, 1);
399 map_item(&mem_iowtab[IOMEM16(0x1040)], io_write_sio16, 1);
400 map_item(&mem_iowtab[IOMEM16(0x1044)], sioWriteStat16, 1);
401 map_item(&mem_iowtab[IOMEM16(0x1048)], sioWriteMode16, 1);
402 map_item(&mem_iowtab[IOMEM16(0x104a)], sioWriteCtrl16, 1);
403 map_item(&mem_iowtab[IOMEM16(0x104e)], sioWriteBaud16, 1);
404 map_item(&mem_iowtab[IOMEM16(0x1070)], io_write_ireg16, 1);
405 map_item(&mem_iowtab[IOMEM16(0x1074)], io_write_imask16, 1);
406 map_item(&mem_iowtab[IOMEM16(0x1100)], io_rcnt_write_count0, 1);
407 map_item(&mem_iowtab[IOMEM16(0x1104)], io_rcnt_write_mode0, 1);
408 map_item(&mem_iowtab[IOMEM16(0x1108)], io_rcnt_write_target0, 1);
409 map_item(&mem_iowtab[IOMEM16(0x1110)], io_rcnt_write_count1, 1);
410 map_item(&mem_iowtab[IOMEM16(0x1114)], io_rcnt_write_mode1, 1);
411 map_item(&mem_iowtab[IOMEM16(0x1118)], io_rcnt_write_target1, 1);
412 map_item(&mem_iowtab[IOMEM16(0x1120)], io_rcnt_write_count2, 1);
413 map_item(&mem_iowtab[IOMEM16(0x1124)], io_rcnt_write_mode2, 1);
414 map_item(&mem_iowtab[IOMEM16(0x1128)], io_rcnt_write_target2, 1);
416 map_item(&mem_iowtab[IOMEM8(0x1040)], sioWrite8, 1);
417 map_item(&mem_iowtab[IOMEM8(0x1800)], cdrWrite0, 1);
418 map_item(&mem_iowtab[IOMEM8(0x1801)], cdrWrite1, 1);
419 map_item(&mem_iowtab[IOMEM8(0x1802)], cdrWrite2, 1);
420 map_item(&mem_iowtab[IOMEM8(0x1803)], cdrWrite3, 1);
422 for (i = 0x1c00; i < 0x1e00; i += 2) {
423 map_item(&mem_iowtab[IOMEM16(i)], io_spu_write16, 1);
424 map_item(&mem_iowtab[IOMEM32(i)], io_spu_write32, 1);
428 map_item(&mem_writetab[0xfffe0130 >> 12], mem_ffwtab, 1);
429 for (i = 0; i < 0x1000/4 + 0x1000/2 + 0x1000; i++)
430 map_item(&mem_ffwtab[i], write_biu, 1);
432 mem_rtab = mem_readtab;
433 mem_wtab = mem_writetab;
435 new_dyna_pcsx_mem_load_state();
438 void new_dyna_pcsx_mem_reset(void)
442 // plugins might change so update the pointers
443 map_item(&mem_iortab[IOMEM32(0x1810)], GPU_readData, 1);
444 map_item(&mem_iortab[IOMEM32(0x1814)], GPU_readStatus, 1);
446 for (i = 0x1c00; i < 0x1e00; i += 2)
447 map_item(&mem_iortab[IOMEM16(i)], SPU_readRegister, 1);
449 map_item(&mem_iowtab[IOMEM32(0x1810)], GPU_writeData, 1);
450 map_item(&mem_iowtab[IOMEM32(0x1814)], GPU_writeStatus, 1);