1 /***************************************************************************
2 * Copyright (C) 2010 by Blade_Arma *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. *
18 ***************************************************************************/
21 * Internal PSX counters.
24 #include "psxcounters.h"
28 /******************************************************************************/
32 Rc0Gate = 0x0001, // 0 not implemented
33 Rc1Gate = 0x0001, // 0 not implemented
34 Rc2Disable = 0x0001, // 0 partially implemented
35 RcUnknown1 = 0x0002, // 1 ?
36 RcUnknown2 = 0x0004, // 2 ?
37 RcCountToTarget = 0x0008, // 3
38 RcIrqOnTarget = 0x0010, // 4
39 RcIrqOnOverflow = 0x0020, // 5
40 RcIrqRegenerate = 0x0040, // 6
41 RcUnknown7 = 0x0080, // 7 ?
42 Rc0PixelClock = 0x0100, // 8 fake implementation
43 Rc1HSyncClock = 0x0100, // 8
44 Rc2Unknown8 = 0x0100, // 8 ?
45 Rc0Unknown9 = 0x0200, // 9 ?
46 Rc1Unknown9 = 0x0200, // 9 ?
47 Rc2OneEighthClock = 0x0200, // 9
48 RcUnknown10 = 0x0400, // 10 ?
49 RcCountEqTarget = 0x0800, // 11
50 RcOverflow = 0x1000, // 12
51 RcUnknown13 = 0x2000, // 13 ? (always zero)
52 RcUnknown14 = 0x4000, // 14 ? (always zero)
53 RcUnknown15 = 0x8000, // 15 ? (always zero)
56 #define CounterQuantity ( 4 )
57 //static const u32 CounterQuantity = 4;
59 static const u32 CountToOverflow = 0;
60 static const u32 CountToTarget = 1;
62 static const u32 FrameRate[] = { 60, 50 };
63 static const u32 HSyncTotal[] = { 263, 314 }; // actually one more on odd lines for PAL
64 #define VBlankStart 240
66 #define VERBOSE_LEVEL 0
68 /******************************************************************************/
70 Rcnt rcnts[ CounterQuantity ];
73 u32 frame_counter = 0;
74 static u32 hsync_steps = 0;
75 static u32 base_cycle = 0;
77 u32 psxNextCounter = 0, psxNextsCounter = 0;
79 /******************************************************************************/
82 void setIrq( u32 irq )
84 psxHu32ref(0x1070) |= SWAPu32(irq);
88 void verboseLog( u32 level, const char *str, ... )
91 if( level <= VERBOSE_LEVEL )
97 vsprintf( buf, str, va );
106 /******************************************************************************/
109 void _psxRcntWcount( u32 index, u32 value )
113 verboseLog( 1, "[RCNT %i] wcount > 0xffff: %x\n", index, value );
117 rcnts[index].cycleStart = psxRegs.cycle;
118 rcnts[index].cycleStart -= value * rcnts[index].rate;
121 if( value < rcnts[index].target )
123 rcnts[index].cycle = rcnts[index].target * rcnts[index].rate;
124 rcnts[index].counterState = CountToTarget;
128 rcnts[index].cycle = 0x10000 * rcnts[index].rate;
129 rcnts[index].counterState = CountToOverflow;
134 u32 _psxRcntRcount( u32 index )
138 count = psxRegs.cycle;
139 count -= rcnts[index].cycleStart;
140 if (rcnts[index].rate > 1)
141 count /= rcnts[index].rate;
143 if( count > 0x10000 )
145 verboseLog( 1, "[RCNT %i] rcount > 0x10000: %x\n", index, count );
153 void _psxRcntWmode( u32 index, u32 value )
155 rcnts[index].mode = value;
160 if( value & Rc0PixelClock )
162 rcnts[index].rate = 5;
166 rcnts[index].rate = 1;
170 if( value & Rc1HSyncClock )
172 rcnts[index].rate = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType]));
176 rcnts[index].rate = 1;
180 if( value & Rc2OneEighthClock )
182 rcnts[index].rate = 8;
186 rcnts[index].rate = 1;
189 // TODO: wcount must work.
190 if( value & Rc2Disable )
192 rcnts[index].rate = 0xffffffff;
198 /******************************************************************************/
206 psxNextsCounter = psxRegs.cycle;
207 psxNextCounter = 0x7fffffff;
209 for( i = 0; i < CounterQuantity; ++i )
211 countToUpdate = rcnts[i].cycle - (psxNextsCounter - rcnts[i].cycleStart);
213 if( countToUpdate < 0 )
219 if( countToUpdate < (s32)psxNextCounter )
221 psxNextCounter = countToUpdate;
225 psxRegs.interrupt |= (1 << PSXINT_RCNT);
226 new_dyna_set_event(PSXINT_RCNT, psxNextCounter);
229 /******************************************************************************/
232 void psxRcntReset( u32 index )
236 rcnts[index].mode |= RcUnknown10;
238 if( rcnts[index].counterState == CountToTarget )
240 rcycles = psxRegs.cycle - rcnts[index].cycleStart;
241 if( rcnts[index].mode & RcCountToTarget )
243 rcycles -= rcnts[index].target * rcnts[index].rate;
244 rcnts[index].cycleStart = psxRegs.cycle - rcycles;
248 rcnts[index].cycle = 0x10000 * rcnts[index].rate;
249 rcnts[index].counterState = CountToOverflow;
252 if( rcnts[index].mode & RcIrqOnTarget )
254 if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) )
256 verboseLog( 3, "[RCNT %i] irq\n", index );
257 setIrq( rcnts[index].irq );
258 rcnts[index].irqState = 1;
262 rcnts[index].mode |= RcCountEqTarget;
264 if( rcycles < 0x10000 * rcnts[index].rate )
268 if( rcnts[index].counterState == CountToOverflow )
270 rcycles = psxRegs.cycle - rcnts[index].cycleStart;
271 rcycles -= 0x10000 * rcnts[index].rate;
273 rcnts[index].cycleStart = psxRegs.cycle - rcycles;
275 if( rcycles < rcnts[index].target * rcnts[index].rate )
277 rcnts[index].cycle = rcnts[index].target * rcnts[index].rate;
278 rcnts[index].counterState = CountToTarget;
281 if( rcnts[index].mode & RcIrqOnOverflow )
283 if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) )
285 verboseLog( 3, "[RCNT %i] irq\n", index );
286 setIrq( rcnts[index].irq );
287 rcnts[index].irqState = 1;
291 rcnts[index].mode |= RcOverflow;
299 cycle = psxRegs.cycle;
302 while( cycle - rcnts[0].cycleStart >= rcnts[0].cycle )
308 while( cycle - rcnts[1].cycleStart >= rcnts[1].cycle )
314 while( cycle - rcnts[2].cycleStart >= rcnts[2].cycle )
320 if( cycle - rcnts[3].cycleStart >= rcnts[3].cycle )
322 u32 leftover_cycles = cycle - rcnts[3].cycleStart - rcnts[3].cycle;
325 hSyncCount += hsync_steps;
328 if( hSyncCount == VBlankStart )
330 HW_GPU_STATUS &= SWAP32(~PSXGPU_LCF);
339 SPU_async( cycle, 1 );
343 // Update lace. (with InuYasha fix)
344 if( hSyncCount >= (Config.VSyncWA ? HSyncTotal[Config.PsxType] / BIAS : HSyncTotal[Config.PsxType]) )
350 if ((HW_GPU_STATUS & SWAP32(PSXGPU_ILACE_BITS)) == SWAP32(PSXGPU_ILACE_BITS))
351 HW_GPU_STATUS |= SWAP32(frame_counter << 31);
352 GPU_vBlank(0, SWAP32(HW_GPU_STATUS) >> 31);
355 // Schedule next call, in hsyncs
356 hsync_steps = HSyncTotal[Config.PsxType] - hSyncCount;
357 next_vsync = VBlankStart - hSyncCount; // ok to overflow
358 if( next_vsync && next_vsync < hsync_steps )
359 hsync_steps = next_vsync;
361 rcnts[3].cycleStart = cycle - leftover_cycles;
363 // 20.12 precision, clk / 50 / 313 ~= 2164.14
364 base_cycle += hsync_steps * 8864320;
366 // clk / 60 / 263 ~= 2146.31
367 base_cycle += hsync_steps * 8791293;
368 rcnts[3].cycle = base_cycle >> 12;
379 /******************************************************************************/
381 void psxRcntWcount( u32 index, u32 value )
383 verboseLog( 2, "[RCNT %i] wcount: %x\n", index, value );
385 _psxRcntWcount( index, value );
389 void psxRcntWmode( u32 index, u32 value )
391 verboseLog( 1, "[RCNT %i] wmode: %x\n", index, value );
393 _psxRcntWmode( index, value );
394 _psxRcntWcount( index, 0 );
396 rcnts[index].irqState = 0;
400 void psxRcntWtarget( u32 index, u32 value )
402 verboseLog( 1, "[RCNT %i] wtarget: %x\n", index, value );
404 rcnts[index].target = value;
406 _psxRcntWcount( index, _psxRcntRcount( index ) );
410 /******************************************************************************/
412 u32 psxRcntRcount( u32 index )
416 count = _psxRcntRcount( index );
418 // Parasite Eve 2 fix.
423 if( rcnts[index].counterState == CountToTarget )
430 verboseLog( 2, "[RCNT %i] rcount: %x\n", index, count );
435 u32 psxRcntRmode( u32 index )
439 mode = rcnts[index].mode;
440 rcnts[index].mode &= 0xe7ff;
442 verboseLog( 2, "[RCNT %i] rmode: %x\n", index, mode );
447 u32 psxRcntRtarget( u32 index )
449 verboseLog( 2, "[RCNT %i] rtarget: %x\n", index, rcnts[index].target );
451 return rcnts[index].target;
454 /******************************************************************************/
474 rcnts[3].mode = RcCountToTarget;
475 rcnts[3].target = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType]));
477 for( i = 0; i < CounterQuantity; ++i )
479 _psxRcntWcount( i, 0 );
488 /******************************************************************************/
490 s32 psxRcntFreeze( void *f, s32 Mode )
492 u32 spuSyncCount = 0;
496 gzfreeze( &rcnts, sizeof(Rcnt) * CounterQuantity );
497 gzfreeze( &hSyncCount, sizeof(hSyncCount) );
498 gzfreeze( &spuSyncCount, sizeof(spuSyncCount) );
499 gzfreeze( &psxNextCounter, sizeof(psxNextCounter) );
500 gzfreeze( &psxNextsCounter, sizeof(psxNextsCounter) );
504 // don't trust things from a savestate
506 for( i = 0; i < CounterQuantity; ++i )
508 _psxRcntWmode( i, rcnts[i].mode );
509 count = (psxRegs.cycle - rcnts[i].cycleStart) / rcnts[i].rate;
510 _psxRcntWcount( i, count );
514 hsync_steps = (psxRegs.cycle - rcnts[3].cycleStart) / rcnts[3].target;
523 /******************************************************************************/