1 /***************************************************************************
2 * Copyright (C) 2010 by Blade_Arma *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. *
18 ***************************************************************************/
21 * Internal PSX counters.
24 #include "psxcounters.h"
25 #include "psxevents.h"
30 /******************************************************************************/
34 RcSyncModeEnable = 0x0001, // 0
35 Rc01BlankPause = 0 << 1, // 1,2
36 Rc01UnblankReset = 1 << 1, // 1,2
37 Rc01UnblankReset2 = 2 << 1, // 1,2
38 Rc2Stop = 0 << 1, // 1,2
39 Rc2Stop2 = 3 << 1, // 1,2
40 RcCountToTarget = 0x0008, // 3
41 RcIrqOnTarget = 0x0010, // 4
42 RcIrqOnOverflow = 0x0020, // 5
43 RcIrqRegenerate = 0x0040, // 6
44 RcUnknown7 = 0x0080, // 7 ?
45 Rc0PixelClock = 0x0100, // 8 fake implementation
46 Rc1HSyncClock = 0x0100, // 8
47 Rc2Unknown8 = 0x0100, // 8 ?
48 Rc0Unknown9 = 0x0200, // 9 ?
49 Rc1Unknown9 = 0x0200, // 9 ?
50 Rc2OneEighthClock = 0x0200, // 9
51 RcUnknown10 = 0x0400, // 10 ?
52 RcCountEqTarget = 0x0800, // 11
53 RcOverflow = 0x1000, // 12
54 RcUnknown13 = 0x2000, // 13 ? (always zero)
55 RcUnknown14 = 0x4000, // 14 ? (always zero)
56 RcUnknown15 = 0x8000, // 15 ? (always zero)
59 #define CounterQuantity ( 4 )
60 //static const u32 CounterQuantity = 4;
62 static const u32 CountToOverflow = 0;
63 static const u32 CountToTarget = 1;
65 static const u32 HSyncTotal[] = { 263, 314 };
66 #define VBlankStart 240 // todo: depend on the actual GPU setting
68 #define VERBOSE_LEVEL 0
70 /******************************************************************************/
72 Rcnt rcnts[ CounterQuantity ];
75 u32 frame_counter = 0;
76 static u32 hsync_steps = 0;
78 u32 psxNextCounter = 0, psxNextsCounter = 0;
80 /******************************************************************************/
82 #define FPS_FRACTIONAL_PAL (53203425/314./3406) // ~49.75
83 #define FPS_FRACTIONAL_NTSC (53693175/263./3413) // ~59.81
88 int ff = Config.FractionalFramerate >= 0
89 ? Config.FractionalFramerate : Config.hacks.fractional_Framerate;
93 return (u32)(PSXCLK / FPS_FRACTIONAL_PAL);
95 return (u32)(PSXCLK / FPS_FRACTIONAL_NTSC);
97 return Config.PsxType ? (PSXCLK / 50) : (PSXCLK / 60);
100 // used to inform the frontend about the exact framerate
103 int ff = Config.FractionalFramerate >= 0
104 ? Config.FractionalFramerate : Config.hacks.fractional_Framerate;
106 return Config.PsxType ? FPS_FRACTIONAL_PAL : FPS_FRACTIONAL_NTSC;
108 return Config.PsxType ? 50.0 : 60.0;
111 // to inform the frontend about the exact famerate
115 // should be more like above, but our timing is already poor anyway
117 return PSXCLK / 50 / HSyncTotal[1];
119 return PSXCLK / 60 / HSyncTotal[0];
123 void setIrq( u32 irq )
125 psxHu32ref(0x1070) |= SWAPu32(irq);
129 void verboseLog( u32 level, const char *str, ... )
131 #if VERBOSE_LEVEL > 0
132 if( level <= VERBOSE_LEVEL )
138 vsprintf( buf, str, va );
147 /******************************************************************************/
150 void _psxRcntWcount( u32 index, u32 value )
154 rcnts[index].cycleStart = psxRegs.cycle;
155 rcnts[index].cycleStart -= value * rcnts[index].rate;
158 if( value < rcnts[index].target )
160 rcnts[index].cycle = rcnts[index].target * rcnts[index].rate;
161 rcnts[index].counterState = CountToTarget;
165 rcnts[index].cycle = 0x10000 * rcnts[index].rate;
166 rcnts[index].counterState = CountToOverflow;
171 u32 _psxRcntRcount( u32 index )
175 count = psxRegs.cycle;
176 count -= rcnts[index].cycleStart;
177 if (rcnts[index].rate > 1)
178 count /= rcnts[index].rate;
180 if( count > 0x10000 )
182 verboseLog( 1, "[RCNT %i] rcount > 0x10000: %x\n", index, count );
190 void _psxRcntWmode( u32 index, u32 value )
192 rcnts[index].mode = value;
197 if( value & Rc0PixelClock )
199 rcnts[index].rate = 5;
203 rcnts[index].rate = 1;
207 if( value & Rc1HSyncClock )
209 rcnts[index].rate = lineCycles();
213 rcnts[index].rate = 1;
217 if( value & Rc2OneEighthClock )
219 rcnts[index].rate = 8;
223 rcnts[index].rate = 1;
226 // TODO: wcount must work.
227 if( (value & 7) == (RcSyncModeEnable | Rc2Stop) ||
228 (value & 7) == (RcSyncModeEnable | Rc2Stop2) )
230 rcnts[index].rate = 0xffffffff;
236 /******************************************************************************/
244 psxNextsCounter = psxRegs.cycle;
245 psxNextCounter = 0x7fffffff;
247 for( i = 0; i < CounterQuantity; ++i )
249 countToUpdate = rcnts[i].cycle - (psxNextsCounter - rcnts[i].cycleStart);
251 if( countToUpdate < 0 )
257 if( countToUpdate < (s32)psxNextCounter )
259 psxNextCounter = countToUpdate;
263 set_event(PSXINT_RCNT, psxNextCounter);
266 /******************************************************************************/
269 void psxRcntReset( u32 index )
273 rcnts[index].mode |= RcUnknown10;
275 if( rcnts[index].counterState == CountToTarget )
277 rcycles = psxRegs.cycle - rcnts[index].cycleStart;
278 if( rcnts[index].mode & RcCountToTarget )
280 rcycles -= rcnts[index].target * rcnts[index].rate;
281 rcnts[index].cycleStart = psxRegs.cycle - rcycles;
285 rcnts[index].cycle = 0x10000 * rcnts[index].rate;
286 rcnts[index].counterState = CountToOverflow;
289 if( rcnts[index].mode & RcIrqOnTarget )
291 if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) )
293 verboseLog( 3, "[RCNT %i] irq\n", index );
294 setIrq( rcnts[index].irq );
295 rcnts[index].irqState = 1;
299 rcnts[index].mode |= RcCountEqTarget;
301 if( rcycles < 0x10000 * rcnts[index].rate )
305 if( rcnts[index].counterState == CountToOverflow )
307 rcycles = psxRegs.cycle - rcnts[index].cycleStart;
308 rcycles -= 0x10000 * rcnts[index].rate;
310 rcnts[index].cycleStart = psxRegs.cycle - rcycles;
312 if( rcycles < rcnts[index].target * rcnts[index].rate )
314 rcnts[index].cycle = rcnts[index].target * rcnts[index].rate;
315 rcnts[index].counterState = CountToTarget;
318 if( rcnts[index].mode & RcIrqOnOverflow )
320 if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) )
322 verboseLog( 3, "[RCNT %i] irq\n", index );
323 setIrq( rcnts[index].irq );
324 rcnts[index].irqState = 1;
328 rcnts[index].mode |= RcOverflow;
332 static void scheduleRcntBase(void)
334 // Schedule next call, in hsyncs
335 if (hSyncCount < VBlankStart)
336 hsync_steps = VBlankStart - hSyncCount;
338 hsync_steps = HSyncTotal[Config.PsxType] - hSyncCount;
340 if (hSyncCount + hsync_steps == HSyncTotal[Config.PsxType])
342 rcnts[3].cycle = frameCycles();
346 // clk / 50 / 314 ~= 2157.25
347 // clk / 60 / 263 ~= 2146.31
348 u32 mult = Config.PsxType ? 8836089 : 8791293;
349 rcnts[3].cycle = hsync_steps * mult >> 12;
355 u32 cycle, cycles_passed;
357 cycle = psxRegs.cycle;
360 cycles_passed = cycle - rcnts[0].cycleStart;
361 while( cycles_passed >= rcnts[0].cycle )
363 if (((rcnts[0].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset) ||
364 (rcnts[0].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset2))
365 && cycles_passed > lineCycles())
367 u32 q = cycles_passed / (lineCycles() + 1u);
368 rcnts[0].cycleStart += q * lineCycles();
374 cycles_passed = cycle - rcnts[0].cycleStart;
378 while( cycle - rcnts[1].cycleStart >= rcnts[1].cycle )
384 while( cycle - rcnts[2].cycleStart >= rcnts[2].cycle )
390 if( cycle - rcnts[3].cycleStart >= rcnts[3].cycle )
392 hSyncCount += hsync_steps;
395 if( hSyncCount == VBlankStart )
397 HW_GPU_STATUS &= SWAP32(~PSXGPU_LCF);
406 SPU_async( cycle, 1 );
411 if( hSyncCount >= HSyncTotal[Config.PsxType] )
413 u32 status, field = 0;
414 rcnts[3].cycleStart += frameCycles();
419 status = SWAP32(HW_GPU_STATUS) | PSXGPU_FIELD;
420 if ((status & PSXGPU_ILACE_BITS) == PSXGPU_ILACE_BITS) {
421 field = frame_counter & 1;
422 status |= field << 31;
423 status ^= field << 13;
425 HW_GPU_STATUS = SWAP32(status);
426 GPU_vBlank(0, field);
427 if ((s32)(psxRegs.gpuIdleAfter - psxRegs.cycle) < 0)
428 psxRegs.gpuIdleAfter = psxRegs.cycle - 1; // prevent overflow
430 if ((rcnts[0].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset) ||
431 (rcnts[0].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset2))
433 rcnts[0].cycleStart = rcnts[3].cycleStart;
436 if ((rcnts[1].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset) ||
437 (rcnts[1].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset2))
439 rcnts[1].cycleStart = rcnts[3].cycleStart;
441 else if (rcnts[1].mode & Rc1HSyncClock)
443 // adjust to remove the rounding error
444 _psxRcntWcount(1, (psxRegs.cycle - rcnts[1].cycleStart) / rcnts[1].rate);
458 /******************************************************************************/
460 void psxRcntWcount( u32 index, u32 value )
462 verboseLog( 2, "[RCNT %i] wcount: %x\n", index, value );
464 _psxRcntWcount( index, value );
468 void psxRcntWmode( u32 index, u32 value )
470 verboseLog( 1, "[RCNT %i] wmode: %x\n", index, value );
472 _psxRcntWmode( index, value );
473 _psxRcntWcount( index, 0 );
475 rcnts[index].irqState = 0;
479 void psxRcntWtarget( u32 index, u32 value )
481 verboseLog( 1, "[RCNT %i] wtarget: %x\n", index, value );
483 rcnts[index].target = value;
485 _psxRcntWcount( index, _psxRcntRcount( index ) );
489 /******************************************************************************/
496 if ((rcnts[0].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset) ||
497 (rcnts[0].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset2))
499 count = psxRegs.cycle - rcnts[index].cycleStart;
500 //count = ((16u * count) % (16u * PSXCLK / 60 / 263)) / 16u;
501 count = count % lineCycles();
502 rcnts[index].cycleStart = psxRegs.cycle - count;
505 count = _psxRcntRcount( index );
507 verboseLog( 2, "[RCNT 0] rcount: %04x m: %04x\n", count, rcnts[index].mode);
517 count = _psxRcntRcount( index );
519 verboseLog( 2, "[RCNT 1] rcount: %04x m: %04x\n", count, rcnts[index].mode);
529 count = _psxRcntRcount( index );
531 verboseLog( 2, "[RCNT 2] rcount: %04x m: %04x\n", count, rcnts[index].mode);
536 u32 psxRcntRmode( u32 index )
540 mode = rcnts[index].mode;
541 rcnts[index].mode &= 0xe7ff;
543 verboseLog( 2, "[RCNT %i] rmode: %x\n", index, mode );
548 u32 psxRcntRtarget( u32 index )
550 verboseLog( 2, "[RCNT %i] rtarget: %x\n", index, rcnts[index].target );
552 return rcnts[index].target;
555 /******************************************************************************/
576 for( i = 0; i < CounterQuantity; ++i )
578 _psxRcntWcount( i, 0 );
588 /******************************************************************************/
590 s32 psxRcntFreeze( void *f, s32 Mode )
592 u32 spuSyncCount = 0;
596 gzfreeze( &rcnts, sizeof(Rcnt) * CounterQuantity );
597 gzfreeze( &hSyncCount, sizeof(hSyncCount) );
598 gzfreeze( &spuSyncCount, sizeof(spuSyncCount) );
599 gzfreeze( &psxNextCounter, sizeof(psxNextCounter) );
600 gzfreeze( &psxNextsCounter, sizeof(psxNextsCounter) );
605 for( i = 0; i < CounterQuantity - 1; ++i )
607 _psxRcntWmode( i, rcnts[i].mode );
608 count = (psxRegs.cycle - rcnts[i].cycleStart) / rcnts[i].rate;
610 _psxRcntWcount( i, count & 0xffff );
619 /******************************************************************************/
620 // vim:ts=4:shiftwidth=4:expandtab