1 /***************************************************************************
2 * Copyright (C) 2010 by Blade_Arma *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. *
18 ***************************************************************************/
21 * Internal PSX counters.
24 #include "psxcounters.h"
28 /******************************************************************************/
32 Rc0Gate = 0x0001, // 0 not implemented
33 Rc1Gate = 0x0001, // 0 not implemented
34 Rc2Disable = 0x0001, // 0 partially implemented
35 RcUnknown1 = 0x0002, // 1 ?
36 RcUnknown2 = 0x0004, // 2 ?
37 RcCountToTarget = 0x0008, // 3
38 RcIrqOnTarget = 0x0010, // 4
39 RcIrqOnOverflow = 0x0020, // 5
40 RcIrqRegenerate = 0x0040, // 6
41 RcUnknown7 = 0x0080, // 7 ?
42 Rc0PixelClock = 0x0100, // 8 fake implementation
43 Rc1HSyncClock = 0x0100, // 8
44 Rc2Unknown8 = 0x0100, // 8 ?
45 Rc0Unknown9 = 0x0200, // 9 ?
46 Rc1Unknown9 = 0x0200, // 9 ?
47 Rc2OneEighthClock = 0x0200, // 9
48 RcUnknown10 = 0x0400, // 10 ?
49 RcCountEqTarget = 0x0800, // 11
50 RcOverflow = 0x1000, // 12
51 RcUnknown13 = 0x2000, // 13 ? (always zero)
52 RcUnknown14 = 0x4000, // 14 ? (always zero)
53 RcUnknown15 = 0x8000, // 15 ? (always zero)
56 #define CounterQuantity ( 4 )
57 //static const u32 CounterQuantity = 4;
59 static const u32 CountToOverflow = 0;
60 static const u32 CountToTarget = 1;
62 static const u32 FrameRate[] = { 60, 50 };
63 static const u32 VBlankStart[] = { 240, 256 };
64 static const u32 HSyncTotal[] = { 263, 313 };
65 static const u32 SpuUpdInterval[] = { 32, 32 };
67 #define VERBOSE_LEVEL 0
68 static const s32 VerboseLevel = VERBOSE_LEVEL;
70 /******************************************************************************/
72 Rcnt rcnts[ CounterQuantity ];
74 static u32 hSyncCount = 0;
75 static u32 spuSyncCount = 0;
76 static u32 hsync_steps = 0;
77 static u32 gpu_wants_hcnt = 0;
78 static u32 base_cycle = 0;
79 static u32 frame_counter = 0;
81 u32 psxNextCounter = 0, psxNextsCounter = 0;
83 /******************************************************************************/
86 void setIrq( u32 irq )
88 psxHu32ref(0x1070) |= SWAPu32(irq);
92 void verboseLog( u32 level, const char *str, ... )
95 if( level <= VerboseLevel )
101 vsprintf( buf, str, va );
110 /******************************************************************************/
113 void _psxRcntWcount( u32 index, u32 value )
117 verboseLog( 1, "[RCNT %i] wcount > 0xffff: %x\n", index, value );
121 rcnts[index].cycleStart = psxRegs.cycle;
122 rcnts[index].cycleStart -= value * rcnts[index].rate;
125 if( value < rcnts[index].target )
127 rcnts[index].cycle = rcnts[index].target * rcnts[index].rate;
128 rcnts[index].counterState = CountToTarget;
132 rcnts[index].cycle = 0xffff * rcnts[index].rate;
133 rcnts[index].counterState = CountToOverflow;
138 u32 _psxRcntRcount( u32 index )
142 count = psxRegs.cycle;
143 count -= rcnts[index].cycleStart;
144 if (rcnts[index].rate > 1)
145 count /= rcnts[index].rate;
149 verboseLog( 1, "[RCNT %i] rcount > 0xffff: %x\n", index, count );
156 /******************************************************************************/
164 psxNextsCounter = psxRegs.cycle;
165 psxNextCounter = 0x7fffffff;
167 for( i = 0; i < CounterQuantity; ++i )
169 countToUpdate = rcnts[i].cycle - (psxNextsCounter - rcnts[i].cycleStart);
171 if( countToUpdate < 0 )
177 if( countToUpdate < (s32)psxNextCounter )
179 psxNextCounter = countToUpdate;
183 psxRegs.interrupt |= (1 << PSXINT_RCNT);
184 new_dyna_set_event(PSXINT_RCNT, psxNextCounter);
187 /******************************************************************************/
190 void psxRcntReset( u32 index )
194 if( rcnts[index].counterState == CountToTarget )
196 if( rcnts[index].mode & RcCountToTarget )
198 count = psxRegs.cycle;
199 count -= rcnts[index].cycleStart;
200 if (rcnts[index].rate > 1)
201 count /= rcnts[index].rate;
202 count -= rcnts[index].target;
206 count = _psxRcntRcount( index );
209 _psxRcntWcount( index, count );
211 if( rcnts[index].mode & RcIrqOnTarget )
213 if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) )
215 verboseLog( 3, "[RCNT %i] irq: %x\n", index, count );
216 setIrq( rcnts[index].irq );
217 rcnts[index].irqState = 1;
221 rcnts[index].mode |= RcCountEqTarget;
223 else if( rcnts[index].counterState == CountToOverflow )
225 count = psxRegs.cycle;
226 count -= rcnts[index].cycleStart;
227 if (rcnts[index].rate > 1)
228 count /= rcnts[index].rate;
231 _psxRcntWcount( index, count );
233 if( rcnts[index].mode & RcIrqOnOverflow )
235 if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) )
237 verboseLog( 3, "[RCNT %i] irq: %x\n", index, count );
238 setIrq( rcnts[index].irq );
239 rcnts[index].irqState = 1;
243 rcnts[index].mode |= RcOverflow;
246 rcnts[index].mode |= RcUnknown10;
255 cycle = psxRegs.cycle;
258 if( cycle - rcnts[0].cycleStart >= rcnts[0].cycle )
264 if( cycle - rcnts[1].cycleStart >= rcnts[1].cycle )
270 if( cycle - rcnts[2].cycleStart >= rcnts[2].cycle )
276 if( cycle - rcnts[3].cycleStart >= rcnts[3].cycle )
278 u32 leftover_cycles = cycle - rcnts[3].cycleStart - rcnts[3].cycle;
279 u32 next_vsync, next_lace;
281 spuSyncCount += hsync_steps;
282 hSyncCount += hsync_steps;
285 if( spuSyncCount >= SpuUpdInterval[Config.PsxType] )
291 SPU_async( SpuUpdInterval[Config.PsxType] * rcnts[3].target );
296 if( hSyncCount == VBlankStart[Config.PsxType] )
298 GPU_vBlank( 1, &hSyncCount, &gpu_wants_hcnt );
299 //if( !(HW_GPU_STATUS & PSXGPU_ILACE) ) // hmh
300 HW_GPU_STATUS |= PSXGPU_LCF;
302 // For the best times. :D
306 // Update lace. (with InuYasha fix)
307 if( hSyncCount >= (Config.VSyncWA ? HSyncTotal[Config.PsxType] / BIAS : HSyncTotal[Config.PsxType]) )
312 GPU_vBlank( 0, &hSyncCount, &gpu_wants_hcnt );
318 HW_GPU_STATUS &= ~PSXGPU_LCF;
319 if( HW_GPU_STATUS & PSXGPU_ILACE )
320 HW_GPU_STATUS |= frame_counter << 31;
323 // Schedule next call, in hsyncs
324 hsync_steps = SpuUpdInterval[Config.PsxType] - spuSyncCount;
325 next_vsync = VBlankStart[Config.PsxType] - hSyncCount; // ok to overflow
326 next_lace = HSyncTotal[Config.PsxType] - hSyncCount;
327 if( next_vsync && next_vsync < hsync_steps )
328 hsync_steps = next_vsync;
329 if( next_lace && next_lace < hsync_steps )
330 hsync_steps = next_lace;
334 rcnts[3].cycleStart = cycle - leftover_cycles;
336 // 20.12 precision, clk / 50 / 313 ~= 2164.14
337 base_cycle += hsync_steps * 8864320;
339 // clk / 60 / 263 ~= 2146.31
340 base_cycle += hsync_steps * 8791293;
341 rcnts[3].cycle = base_cycle >> 12;
351 /******************************************************************************/
353 void psxRcntWcount( u32 index, u32 value )
355 verboseLog( 2, "[RCNT %i] wcount: %x\n", index, value );
357 _psxRcntWcount( index, value );
361 void psxRcntWmode( u32 index, u32 value )
363 verboseLog( 1, "[RCNT %i] wmode: %x\n", index, value );
365 rcnts[index].mode = value;
366 rcnts[index].irqState = 0;
371 if( value & Rc0PixelClock )
373 rcnts[index].rate = 5;
377 rcnts[index].rate = 1;
381 if( value & Rc1HSyncClock )
383 rcnts[index].rate = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType]));
387 rcnts[index].rate = 1;
391 if( value & Rc2OneEighthClock )
393 rcnts[index].rate = 8;
397 rcnts[index].rate = 1;
400 // TODO: wcount must work.
401 if( value & Rc2Disable )
403 rcnts[index].rate = 0xffffffff;
408 _psxRcntWcount( index, 0 );
412 void psxRcntWtarget( u32 index, u32 value )
414 verboseLog( 1, "[RCNT %i] wtarget: %x\n", index, value );
416 rcnts[index].target = value;
418 _psxRcntWcount( index, _psxRcntRcount( index ) );
422 /******************************************************************************/
424 u32 psxRcntRcount( u32 index )
428 count = _psxRcntRcount( index );
430 // Parasite Eve 2 fix.
435 if( rcnts[index].counterState == CountToTarget )
442 verboseLog( 2, "[RCNT %i] rcount: %x\n", index, count );
447 u32 psxRcntRmode( u32 index )
451 mode = rcnts[index].mode;
452 rcnts[index].mode &= 0xe7ff;
454 verboseLog( 2, "[RCNT %i] rmode: %x\n", index, mode );
459 u32 psxRcntRtarget( u32 index )
461 verboseLog( 2, "[RCNT %i] rtarget: %x\n", index, rcnts[index].target );
463 return rcnts[index].target;
466 /******************************************************************************/
486 rcnts[3].mode = RcCountToTarget;
487 rcnts[3].target = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType]));
489 for( i = 0; i < CounterQuantity; ++i )
491 _psxRcntWcount( i, 0 );
501 /******************************************************************************/
503 s32 psxRcntFreeze( gzFile f, s32 Mode )
505 gzfreeze( &rcnts, sizeof(rcnts) );
506 gzfreeze( &hSyncCount, sizeof(hSyncCount) );
507 gzfreeze( &spuSyncCount, sizeof(spuSyncCount) );
508 gzfreeze( &psxNextCounter, sizeof(psxNextCounter) );
509 gzfreeze( &psxNextsCounter, sizeof(psxNextsCounter) );
512 hsync_steps = (psxRegs.cycle - rcnts[3].cycleStart) / rcnts[3].target;
519 /******************************************************************************/