1 /***************************************************************************
2 * Copyright (C) 2007 Ryan Schultz, PCSX-df Team, PCSX team *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. *
18 ***************************************************************************/
21 * Functions for PSX hardware control.
30 //#define PSXHW_LOG printf
36 memset(psxH, 0, 0x10000);
38 mdecInit(); // initialize mdec decoder
41 HW_GPU_STATUS = SWAP32(0x14802000);
44 u8 psxHwRead8(u32 add) {
47 switch (add & 0x1fffffff) {
48 case 0x1f801040: hard = sioRead8(); break;
49 case 0x1f801800: hard = cdrRead0(); break;
50 case 0x1f801801: hard = cdrRead1(); break;
51 case 0x1f801802: hard = cdrRead2(); break;
52 case 0x1f801803: hard = cdrRead3(); break;
54 case 0x1f801041: case 0x1f801042: case 0x1f801043:
55 case 0x1f801044: case 0x1f801045:
56 case 0x1f801046: case 0x1f801047:
57 case 0x1f801048: case 0x1f801049:
58 case 0x1f80104a: case 0x1f80104b:
59 case 0x1f80104c: case 0x1f80104d:
60 case 0x1f80104e: case 0x1f80104f:
61 case 0x1f801050: case 0x1f801051:
62 case 0x1f801054: case 0x1f801055:
63 case 0x1f801058: case 0x1f801059:
64 case 0x1f80105a: case 0x1f80105b:
65 case 0x1f80105c: case 0x1f80105d:
66 case 0x1f801100: case 0x1f801101:
67 case 0x1f801104: case 0x1f801105:
68 case 0x1f801108: case 0x1f801109:
69 case 0x1f801110: case 0x1f801111:
70 case 0x1f801114: case 0x1f801115:
71 case 0x1f801118: case 0x1f801119:
72 case 0x1f801120: case 0x1f801121:
73 case 0x1f801124: case 0x1f801125:
74 case 0x1f801128: case 0x1f801129:
75 case 0x1f801810: case 0x1f801811:
76 case 0x1f801812: case 0x1f801813:
77 case 0x1f801814: case 0x1f801815:
78 case 0x1f801816: case 0x1f801817:
79 case 0x1f801820: case 0x1f801821:
80 case 0x1f801822: case 0x1f801823:
81 case 0x1f801824: case 0x1f801825:
82 case 0x1f801826: case 0x1f801827:
83 log_unhandled("unhandled r8 %08x @%08x\n", add, psxRegs.pc);
86 if (0x1f801c00 <= add && add < 0x1f802000)
87 log_unhandled("spu r8 %02x @%08x\n", add, psxRegs.pc);
90 PSXHW_LOG("*Unkwnown 8bit read at address %x\n", add);
96 PSXHW_LOG("*Known 8bit read at address %x value %x\n", add, hard);
101 u16 psxHwRead16(u32 add) {
104 switch (add & 0x1fffffff) {
106 case 0x1f801070: PSXHW_LOG("IREG 16bit read %x\n", psxHu16(0x1070));
107 return psxHu16(0x1070);
108 case 0x1f801074: PSXHW_LOG("IMASK 16bit read %x\n", psxHu16(0x1074));
109 return psxHu16(0x1074);
113 hard|= sioRead8() << 8;
114 PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
117 hard = sioReadStat16();
118 PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
121 hard = sioReadMode16();
122 PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
125 hard = sioReadCtrl16();
126 PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
129 hard = sioReadBaud16();
130 PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
133 /* Fixes Armored Core misdetecting the Link cable being detected.
134 * We want to turn that thing off and force it to do local multiplayer instead.
135 * Thanks Sony for the fix, they fixed it in their PS Classic fork.
141 hard = psxRcntRcount(0);
143 PSXHW_LOG("T0 count read16: %x\n", hard);
147 hard = psxRcntRmode(0);
149 PSXHW_LOG("T0 mode read16: %x\n", hard);
153 hard = psxRcntRtarget(0);
155 PSXHW_LOG("T0 target read16: %x\n", hard);
159 hard = psxRcntRcount(1);
161 PSXHW_LOG("T1 count read16: %x\n", hard);
165 hard = psxRcntRmode(1);
167 PSXHW_LOG("T1 mode read16: %x\n", hard);
171 hard = psxRcntRtarget(1);
173 PSXHW_LOG("T1 target read16: %x\n", hard);
177 hard = psxRcntRcount(2);
179 PSXHW_LOG("T2 count read16: %x\n", hard);
183 hard = psxRcntRmode(2);
185 PSXHW_LOG("T2 mode read16: %x\n", hard);
189 hard = psxRcntRtarget(2);
191 PSXHW_LOG("T2 target read16: %x\n", hard);
195 //case 0x1f802030: hard = //int_2000????
196 //case 0x1f802040: hard =//dip switches...??
215 log_unhandled("unhandled r16 %08x @%08x\n", add, psxRegs.pc);
218 if (0x1f801c00 <= add && add < 0x1f802000)
219 return SPU_readRegister(add);
222 PSXHW_LOG("*Unkwnown 16bit read at address %x\n", add);
228 PSXHW_LOG("*Known 16bit read at address %x value %x\n", add, hard);
233 u32 psxHwRead32(u32 add) {
236 switch (add & 0x1fffffff) {
239 hard |= sioRead8() << 8;
240 hard |= sioRead8() << 16;
241 hard |= sioRead8() << 24;
242 PAD_LOG("sio read32 ;ret = %x\n", hard);
245 hard = sioReadStat16();
246 PAD_LOG("sio read32 %x; ret = %x\n", add&0xf, hard);
250 PSXHW_LOG("RAM size read %x\n", psxHu32(0x1060));
251 return psxHu32(0x1060);
252 case 0x1f801070: PSXHW_LOG("IREG 32bit read %x\n", psxHu32(0x1070));
253 return psxHu32(0x1070);
254 case 0x1f801074: PSXHW_LOG("IMASK 32bit read %x\n", psxHu32(0x1074));
255 return psxHu32(0x1074);
259 hard = GPU_readData();
261 PSXHW_LOG("GPU DATA 32bit read %x\n", hard);
266 hard = SWAP32(HW_GPU_STATUS);
267 if (hSyncCount < 240 && (hard & PSXGPU_ILACE_BITS) != PSXGPU_ILACE_BITS)
268 hard |= PSXGPU_LCF & (psxRegs.cycle << 20);
270 PSXHW_LOG("GPU STATUS 32bit read %x\n", hard);
274 case 0x1f801820: hard = mdecRead0(); break;
275 case 0x1f801824: hard = mdecRead1(); break;
279 PSXHW_LOG("DMA2 MADR 32bit read %x\n", psxHu32(0x10a0));
280 return SWAPu32(HW_DMA2_MADR);
282 PSXHW_LOG("DMA2 BCR 32bit read %x\n", psxHu32(0x10a4));
283 return SWAPu32(HW_DMA2_BCR);
285 PSXHW_LOG("DMA2 CHCR 32bit read %x\n", psxHu32(0x10a8));
286 return SWAPu32(HW_DMA2_CHCR);
291 PSXHW_LOG("DMA3 MADR 32bit read %x\n", psxHu32(0x10b0));
292 return SWAPu32(HW_DMA3_MADR);
294 PSXHW_LOG("DMA3 BCR 32bit read %x\n", psxHu32(0x10b4));
295 return SWAPu32(HW_DMA3_BCR);
297 PSXHW_LOG("DMA3 CHCR 32bit read %x\n", psxHu32(0x10b8));
298 return SWAPu32(HW_DMA3_CHCR);
303 PSXHW_LOG("DMA PCR 32bit read %x\n", psxHu32(0x10f0));
304 return SWAPu32(HW_DMA_PCR); // dma rest channel
306 PSXHW_LOG("DMA ICR 32bit read %x\n", psxHu32(0x10f4));
307 return SWAPu32(HW_DMA_ICR); // interrupt enabler?*/
310 // time for rootcounters :)
312 hard = psxRcntRcount(0);
314 PSXHW_LOG("T0 count read32: %x\n", hard);
318 hard = psxRcntRmode(0);
320 PSXHW_LOG("T0 mode read32: %x\n", hard);
324 hard = psxRcntRtarget(0);
326 PSXHW_LOG("T0 target read32: %x\n", hard);
330 hard = psxRcntRcount(1);
332 PSXHW_LOG("T1 count read32: %x\n", hard);
336 hard = psxRcntRmode(1);
338 PSXHW_LOG("T1 mode read32: %x\n", hard);
342 hard = psxRcntRtarget(1);
344 PSXHW_LOG("T1 target read32: %x\n", hard);
348 hard = psxRcntRcount(2);
350 PSXHW_LOG("T2 count read32: %x\n", hard);
354 hard = psxRcntRmode(2);
356 PSXHW_LOG("T2 mode read32: %x\n", hard);
360 hard = psxRcntRtarget(2);
362 PSXHW_LOG("T2 target read32: %x\n", hard);
373 log_unhandled("unhandled r32 %08x @%08x\n", add, psxRegs.pc);
376 if (0x1f801c00 <= add && add < 0x1f802000) {
377 hard = SPU_readRegister(add);
378 hard |= SPU_readRegister(add + 2) << 16;
383 PSXHW_LOG("*Unkwnown 32bit read at address %x\n", add);
388 PSXHW_LOG("*Known 32bit read at address %x\n", add);
393 void psxHwWrite8(u32 add, u8 value) {
394 switch (add & 0x1fffffff) {
395 case 0x1f801040: sioWrite8(value); break;
\r
396 case 0x1f801800: cdrWrite0(value); break;
397 case 0x1f801801: cdrWrite1(value); break;
398 case 0x1f801802: cdrWrite2(value); break;
399 case 0x1f801803: cdrWrite3(value); break;
401 case 0x1f801041: case 0x1f801042: case 0x1f801043:
402 case 0x1f801044: case 0x1f801045:
403 case 0x1f801046: case 0x1f801047:
404 case 0x1f801048: case 0x1f801049:
405 case 0x1f80104a: case 0x1f80104b:
406 case 0x1f80104c: case 0x1f80104d:
407 case 0x1f80104e: case 0x1f80104f:
408 case 0x1f801050: case 0x1f801051:
409 case 0x1f801054: case 0x1f801055:
410 case 0x1f801058: case 0x1f801059:
411 case 0x1f80105a: case 0x1f80105b:
412 case 0x1f80105c: case 0x1f80105d:
413 case 0x1f801100: case 0x1f801101:
414 case 0x1f801104: case 0x1f801105:
415 case 0x1f801108: case 0x1f801109:
416 case 0x1f801110: case 0x1f801111:
417 case 0x1f801114: case 0x1f801115:
418 case 0x1f801118: case 0x1f801119:
419 case 0x1f801120: case 0x1f801121:
420 case 0x1f801124: case 0x1f801125:
421 case 0x1f801128: case 0x1f801129:
422 case 0x1f801810: case 0x1f801811:
423 case 0x1f801812: case 0x1f801813:
424 case 0x1f801814: case 0x1f801815:
425 case 0x1f801816: case 0x1f801817:
426 case 0x1f801820: case 0x1f801821:
427 case 0x1f801822: case 0x1f801823:
428 case 0x1f801824: case 0x1f801825:
429 case 0x1f801826: case 0x1f801827:
430 log_unhandled("unhandled w8 %08x @%08x\n", add, psxRegs.pc);
433 if (0x1f801c00 <= add && add < 0x1f802000) {
434 log_unhandled("spu w8 %02x @%08x\n", value, psxRegs.pc);
436 SPU_writeRegister(add, value, psxRegs.cycle);
442 PSXHW_LOG("*Unknown 8bit write at address %x value %x\n", add, value);
448 PSXHW_LOG("*Known 8bit write at address %x value %x\n", add, value);
452 void psxHwWrite16(u32 add, u16 value) {
453 switch (add & 0x1fffffff) {
455 sioWrite8((unsigned char)value);
456 sioWrite8((unsigned char)(value>>8));
457 PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
460 sioWriteStat16(value);
461 PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
464 sioWriteMode16(value);
465 PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
467 case 0x1f80104a: // control register
468 sioWriteCtrl16(value);
469 PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
471 case 0x1f80104e: // baudrate register
472 sioWriteBaud16(value);
473 PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
477 PSXHW_LOG("IREG 16bit write %x\n", value);
479 psxHu16ref(0x1070) &= SWAPu16(value);
484 PSXHW_LOG("IMASK 16bit write %x\n", value);
486 psxHu16ref(0x1074) = SWAPu16(value);
487 if (psxHu16ref(0x1070) & SWAPu16(value)) {
488 //if ((psxRegs.CP0.n.SR & 0x401) == 0x401)
489 // log_unhandled("irq on unmask @%08x\n", psxRegs.pc);
490 new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
496 PSXHW_LOG("COUNTER 0 COUNT 16bit write %x\n", value);
498 psxRcntWcount(0, value); return;
501 PSXHW_LOG("COUNTER 0 MODE 16bit write %x\n", value);
503 psxRcntWmode(0, value); return;
506 PSXHW_LOG("COUNTER 0 TARGET 16bit write %x\n", value);
508 psxRcntWtarget(0, value); return;
512 PSXHW_LOG("COUNTER 1 COUNT 16bit write %x\n", value);
514 psxRcntWcount(1, value); return;
517 PSXHW_LOG("COUNTER 1 MODE 16bit write %x\n", value);
519 psxRcntWmode(1, value); return;
522 PSXHW_LOG("COUNTER 1 TARGET 16bit write %x\n", value);
524 psxRcntWtarget(1, value); return;
528 PSXHW_LOG("COUNTER 2 COUNT 16bit write %x\n", value);
530 psxRcntWcount(2, value); return;
533 PSXHW_LOG("COUNTER 2 MODE 16bit write %x\n", value);
535 psxRcntWmode(2, value); return;
538 PSXHW_LOG("COUNTER 2 TARGET 16bit write %x\n", value);
540 psxRcntWtarget(2, value); return;
560 log_unhandled("unhandled w16 %08x @%08x\n", add, psxRegs.pc);
563 if (0x1f801c00 <= add && add < 0x1f802000) {
564 SPU_writeRegister(add, value, psxRegs.cycle);
568 psxHu16ref(add) = SWAPu16(value);
570 PSXHW_LOG("*Unknown 16bit write at address %x value %x\n", add, value);
574 psxHu16ref(add) = SWAPu16(value);
576 PSXHW_LOG("*Known 16bit write at address %x value %x\n", add, value);
580 #define DmaExec(n) { \
581 if (value & SWAPu32(HW_DMA##n##_CHCR) & 0x01000000) \
582 log_unhandled("dma" #n " %08x -> %08x\n", HW_DMA##n##_CHCR, value); \
583 HW_DMA##n##_CHCR = SWAPu32(value); \
585 if (SWAPu32(HW_DMA##n##_CHCR) & 0x01000000 && SWAPu32(HW_DMA_PCR) & (8 << (n * 4))) { \
586 psxDma##n(SWAPu32(HW_DMA##n##_MADR), SWAPu32(HW_DMA##n##_BCR), SWAPu32(HW_DMA##n##_CHCR)); \
590 void psxHwWrite32(u32 add, u32 value) {
591 switch (add & 0x1fffffff) {
593 sioWrite8((unsigned char)value);
594 sioWrite8((unsigned char)((value&0xff) >> 8));
595 sioWrite8((unsigned char)((value&0xff) >> 16));
596 sioWrite8((unsigned char)((value&0xff) >> 24));
597 PAD_LOG("sio write32 %x\n", value);
601 PSXHW_LOG("RAM size write %x\n", value);
602 psxHu32ref(add) = SWAPu32(value);
608 PSXHW_LOG("IREG 32bit write %x\n", value);
610 psxHu32ref(0x1070) &= SWAPu32(value);
614 PSXHW_LOG("IMASK 32bit write %x\n", value);
616 psxHu32ref(0x1074) = SWAPu32(value);
617 if (psxHu32ref(0x1070) & SWAPu32(value)) {
618 if ((psxRegs.CP0.n.SR & 0x401) == 0x401)
619 log_unhandled("irq on unmask @%08x\n", psxRegs.pc);
620 new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
626 PSXHW_LOG("DMA0 MADR 32bit write %x\n", value);
627 HW_DMA0_MADR = SWAPu32(value); return; // DMA0 madr
629 PSXHW_LOG("DMA0 BCR 32bit write %x\n", value);
630 HW_DMA0_BCR = SWAPu32(value); return; // DMA0 bcr
634 PSXHW_LOG("DMA0 CHCR 32bit write %x\n", value);
636 DmaExec(0); // DMA0 chcr (MDEC in DMA)
641 PSXHW_LOG("DMA1 MADR 32bit write %x\n", value);
642 HW_DMA1_MADR = SWAPu32(value); return; // DMA1 madr
644 PSXHW_LOG("DMA1 BCR 32bit write %x\n", value);
645 HW_DMA1_BCR = SWAPu32(value); return; // DMA1 bcr
649 PSXHW_LOG("DMA1 CHCR 32bit write %x\n", value);
651 DmaExec(1); // DMA1 chcr (MDEC out DMA)
656 PSXHW_LOG("DMA2 MADR 32bit write %x\n", value);
657 HW_DMA2_MADR = SWAPu32(value); return; // DMA2 madr
659 PSXHW_LOG("DMA2 BCR 32bit write %x\n", value);
660 HW_DMA2_BCR = SWAPu32(value); return; // DMA2 bcr
664 PSXHW_LOG("DMA2 CHCR 32bit write %x\n", value);
666 DmaExec(2); // DMA2 chcr (GPU DMA)
671 PSXHW_LOG("DMA3 MADR 32bit write %x\n", value);
672 HW_DMA3_MADR = SWAPu32(value); return; // DMA3 madr
674 PSXHW_LOG("DMA3 BCR 32bit write %x\n", value);
675 HW_DMA3_BCR = SWAPu32(value); return; // DMA3 bcr
679 PSXHW_LOG("DMA3 CHCR 32bit write %x\n", value);
681 DmaExec(3); // DMA3 chcr (CDROM DMA)
687 PSXHW_LOG("DMA4 MADR 32bit write %x\n", value);
688 HW_DMA4_MADR = SWAPu32(value); return; // DMA4 madr
690 PSXHW_LOG("DMA4 BCR 32bit write %x\n", value);
691 HW_DMA4_BCR = SWAPu32(value); return; // DMA4 bcr
695 PSXHW_LOG("DMA4 CHCR 32bit write %x\n", value);
697 DmaExec(4); // DMA4 chcr (SPU DMA)
701 case 0x1f8010d0: break; //DMA5write_madr();
702 case 0x1f8010d4: break; //DMA5write_bcr();
703 case 0x1f8010d8: break; //DMA5write_chcr(); // Not needed
708 PSXHW_LOG("DMA6 MADR 32bit write %x\n", value);
709 HW_DMA6_MADR = SWAPu32(value); return; // DMA6 bcr
711 PSXHW_LOG("DMA6 BCR 32bit write %x\n", value);
712 HW_DMA6_BCR = SWAPu32(value); return; // DMA6 bcr
716 PSXHW_LOG("DMA6 CHCR 32bit write %x\n", value);
718 DmaExec(6); // DMA6 chcr (OT clear)
723 PSXHW_LOG("DMA PCR 32bit write %x\n", value);
724 HW_DMA_PCR = SWAPu32(value);
730 PSXHW_LOG("DMA ICR 32bit write %x\n", value);
733 u32 tmp = value & 0x00ff803f;
734 tmp |= (SWAPu32(HW_DMA_ICR) & ~value) & 0x7f000000;
735 if ((tmp & HW_DMA_ICR_GLOBAL_ENABLE && tmp & 0x7f000000)
736 || tmp & HW_DMA_ICR_BUS_ERROR) {
737 if (!(SWAPu32(HW_DMA_ICR) & HW_DMA_ICR_IRQ_SENT))
738 psxHu32ref(0x1070) |= SWAP32(8);
739 tmp |= HW_DMA_ICR_IRQ_SENT;
741 HW_DMA_ICR = SWAPu32(tmp);
747 PSXHW_LOG("GPU DATA 32bit write %x\n", value);
749 GPU_writeData(value); return;
752 PSXHW_LOG("GPU STATUS 32bit write %x\n", value);
754 GPU_writeStatus(value);
759 mdecWrite0(value); break;
761 mdecWrite1(value); break;
765 PSXHW_LOG("COUNTER 0 COUNT 32bit write %x\n", value);
767 psxRcntWcount(0, value & 0xffff); return;
770 PSXHW_LOG("COUNTER 0 MODE 32bit write %x\n", value);
772 psxRcntWmode(0, value); return;
775 PSXHW_LOG("COUNTER 0 TARGET 32bit write %x\n", value);
777 psxRcntWtarget(0, value & 0xffff); return; // HW_DMA_ICR&= SWAP32((~value)&0xff000000);
781 PSXHW_LOG("COUNTER 1 COUNT 32bit write %x\n", value);
783 psxRcntWcount(1, value & 0xffff); return;
786 PSXHW_LOG("COUNTER 1 MODE 32bit write %x\n", value);
788 psxRcntWmode(1, value); return;
791 PSXHW_LOG("COUNTER 1 TARGET 32bit write %x\n", value);
793 psxRcntWtarget(1, value & 0xffff); return;
797 PSXHW_LOG("COUNTER 2 COUNT 32bit write %x\n", value);
799 psxRcntWcount(2, value & 0xffff); return;
802 PSXHW_LOG("COUNTER 2 MODE 32bit write %x\n", value);
804 psxRcntWmode(2, value); return;
807 PSXHW_LOG("COUNTER 2 TARGET 32bit write %x\n", value);
809 psxRcntWtarget(2, value & 0xffff); return;
819 log_unhandled("unhandled w32 %08x @%08x\n", add, psxRegs.pc);
822 // Dukes of Hazard 2 - car engine noise
823 if (0x1f801c00 <= add && add < 0x1f802000) {
824 SPU_writeRegister(add, value&0xffff, psxRegs.cycle);
825 SPU_writeRegister(add + 2, value>>16, psxRegs.cycle);
829 psxHu32ref(add) = SWAPu32(value);
831 PSXHW_LOG("*Unknown 32bit write at address %x value %x\n", add, value);
835 psxHu32ref(add) = SWAPu32(value);
837 PSXHW_LOG("*Known 32bit write at address %x value %x\n", add, value);
841 int psxHwFreeze(void *f, int Mode) {