1 /***************************************************************************
2 * Copyright (C) 2007 Ryan Schultz, PCSX-df Team, PCSX team *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. *
18 ***************************************************************************/
21 * Functions for PSX hardware control.
30 //#define PSXHW_LOG printf
33 if (Config.Sio) psxHu32ref(0x1070) |= SWAP32(0x80);
34 if (Config.SpuIrq) psxHu32ref(0x1070) |= SWAP32(0x200);
36 memset(psxH, 0, 0x10000);
38 mdecInit(); // initialize mdec decoder
41 HW_GPU_STATUS = SWAP32(0x14802000);
44 u8 psxHwRead8(u32 add) {
47 switch (add & 0x1fffffff) {
48 case 0x1f801040: hard = sioRead8();break;
\r
50 case 0x1f801050: hard = SIO1_readData8(); break;
\r
52 case 0x1f801800: hard = cdrRead0(); break;
53 case 0x1f801801: hard = cdrRead1(); break;
54 case 0x1f801802: hard = cdrRead2(); break;
55 case 0x1f801803: hard = cdrRead3(); break;
59 PSXHW_LOG("*Unkwnown 8bit read at address %x\n", add);
65 PSXHW_LOG("*Known 8bit read at address %x value %x\n", add, hard);
70 u16 psxHwRead16(u32 add) {
73 switch (add & 0x1fffffff) {
75 case 0x1f801070: PSXHW_LOG("IREG 16bit read %x\n", psxHu16(0x1070));
76 return psxHu16(0x1070);
79 case 0x1f801074: PSXHW_LOG("IMASK 16bit read %x\n", psxHu16(0x1074));
80 return psxHu16(0x1074);
85 hard|= sioRead8() << 8;
87 PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
91 hard = sioReadStat16();
93 PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
97 hard = sioReadMode16();
99 PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
103 hard = sioReadCtrl16();
105 PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
109 hard = sioReadBaud16();
111 PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
114 #ifdef ENABLE_SIO1API
116 hard = SIO1_readData16();
119 hard = SIO1_readStat16();
122 hard = SIO1_readCtrl16();
125 hard = SIO1_readBaud16();
128 /* Fixes Armored Core misdetecting the Link cable being detected.
129 * We want to turn that thing off and force it to do local multiplayer instead.
130 * Thanks Sony for the fix, they fixed it in their PS Classic fork.
136 hard = psxRcntRcount(0);
138 PSXHW_LOG("T0 count read16: %x\n", hard);
142 hard = psxRcntRmode(0);
144 PSXHW_LOG("T0 mode read16: %x\n", hard);
148 hard = psxRcntRtarget(0);
150 PSXHW_LOG("T0 target read16: %x\n", hard);
154 hard = psxRcntRcount(1);
156 PSXHW_LOG("T1 count read16: %x\n", hard);
160 hard = psxRcntRmode(1);
162 PSXHW_LOG("T1 mode read16: %x\n", hard);
166 hard = psxRcntRtarget(1);
168 PSXHW_LOG("T1 target read16: %x\n", hard);
172 hard = psxRcntRcount(2);
174 PSXHW_LOG("T2 count read16: %x\n", hard);
178 hard = psxRcntRmode(2);
180 PSXHW_LOG("T2 mode read16: %x\n", hard);
184 hard = psxRcntRtarget(2);
186 PSXHW_LOG("T2 target read16: %x\n", hard);
190 //case 0x1f802030: hard = //int_2000????
191 //case 0x1f802040: hard =//dip switches...??
195 log_unhandled("cdrom r16 %x\n", add);
198 if (add >= 0x1f801c00 && add < 0x1f801e00) {
199 hard = SPU_readRegister(add);
203 PSXHW_LOG("*Unkwnown 16bit read at address %x\n", add);
210 PSXHW_LOG("*Known 16bit read at address %x value %x\n", add, hard);
215 u32 psxHwRead32(u32 add) {
218 switch (add & 0x1fffffff) {
221 hard |= sioRead8() << 8;
222 hard |= sioRead8() << 16;
223 hard |= sioRead8() << 24;
225 PAD_LOG("sio read32 ;ret = %x\n", hard);
228 #ifdef ENABLE_SIO1API
230 hard = SIO1_readData32();
235 PSXHW_LOG("RAM size read %x\n", psxHu32(0x1060));
236 return psxHu32(0x1060);
239 case 0x1f801070: PSXHW_LOG("IREG 32bit read %x\n", psxHu32(0x1070));
240 return psxHu32(0x1070);
243 case 0x1f801074: PSXHW_LOG("IMASK 32bit read %x\n", psxHu32(0x1074));
244 return psxHu32(0x1074);
248 hard = GPU_readData();
250 PSXHW_LOG("GPU DATA 32bit read %x\n", hard);
255 hard = SWAP32(HW_GPU_STATUS);
256 if (hSyncCount < 240 && (hard & PSXGPU_ILACE_BITS) != PSXGPU_ILACE_BITS)
257 hard |= PSXGPU_LCF & (psxRegs.cycle << 20);
259 PSXHW_LOG("GPU STATUS 32bit read %x\n", hard);
263 case 0x1f801820: hard = mdecRead0(); break;
264 case 0x1f801824: hard = mdecRead1(); break;
268 PSXHW_LOG("DMA2 MADR 32bit read %x\n", psxHu32(0x10a0));
269 return SWAPu32(HW_DMA2_MADR);
271 PSXHW_LOG("DMA2 BCR 32bit read %x\n", psxHu32(0x10a4));
272 return SWAPu32(HW_DMA2_BCR);
274 PSXHW_LOG("DMA2 CHCR 32bit read %x\n", psxHu32(0x10a8));
275 return SWAPu32(HW_DMA2_CHCR);
280 PSXHW_LOG("DMA3 MADR 32bit read %x\n", psxHu32(0x10b0));
281 return SWAPu32(HW_DMA3_MADR);
283 PSXHW_LOG("DMA3 BCR 32bit read %x\n", psxHu32(0x10b4));
284 return SWAPu32(HW_DMA3_BCR);
286 PSXHW_LOG("DMA3 CHCR 32bit read %x\n", psxHu32(0x10b8));
287 return SWAPu32(HW_DMA3_CHCR);
292 PSXHW_LOG("DMA PCR 32bit read %x\n", psxHu32(0x10f0));
293 return SWAPu32(HW_DMA_PCR); // dma rest channel
295 PSXHW_LOG("DMA ICR 32bit read %x\n", psxHu32(0x10f4));
296 return SWAPu32(HW_DMA_ICR); // interrupt enabler?*/
299 // time for rootcounters :)
301 hard = psxRcntRcount(0);
303 PSXHW_LOG("T0 count read32: %x\n", hard);
307 hard = psxRcntRmode(0);
309 PSXHW_LOG("T0 mode read32: %x\n", hard);
313 hard = psxRcntRtarget(0);
315 PSXHW_LOG("T0 target read32: %x\n", hard);
319 hard = psxRcntRcount(1);
321 PSXHW_LOG("T1 count read32: %x\n", hard);
325 hard = psxRcntRmode(1);
327 PSXHW_LOG("T1 mode read32: %x\n", hard);
331 hard = psxRcntRtarget(1);
333 PSXHW_LOG("T1 target read32: %x\n", hard);
337 hard = psxRcntRcount(2);
339 PSXHW_LOG("T2 count read32: %x\n", hard);
343 hard = psxRcntRmode(2);
345 PSXHW_LOG("T2 mode read32: %x\n", hard);
349 hard = psxRcntRtarget(2);
351 PSXHW_LOG("T2 target read32: %x\n", hard);
356 log_unhandled("cdrom r32 %x\n", add);
361 PSXHW_LOG("*Unkwnown 32bit read at address %x\n", add);
366 PSXHW_LOG("*Known 32bit read at address %x\n", add);
371 void psxHwWrite8(u32 add, u8 value) {
372 switch (add & 0x1fffffff) {
373 case 0x1f801040: sioWrite8(value); break;
\r
374 #ifdef ENABLE_SIO1API
375 case 0x1f801050: SIO1_writeData8(value); break;
\r
377 case 0x1f801800: cdrWrite0(value); break;
378 case 0x1f801801: cdrWrite1(value); break;
379 case 0x1f801802: cdrWrite2(value); break;
380 case 0x1f801803: cdrWrite3(value); break;
385 PSXHW_LOG("*Unknown 8bit write at address %x value %x\n", add, value);
391 PSXHW_LOG("*Known 8bit write at address %x value %x\n", add, value);
395 void psxHwWrite16(u32 add, u16 value) {
396 switch (add & 0x1fffffff) {
398 sioWrite8((unsigned char)value);
399 sioWrite8((unsigned char)(value>>8));
401 PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
405 sioWriteStat16(value);
407 PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
411 sioWriteMode16(value);
413 PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
416 case 0x1f80104a: // control register
417 sioWriteCtrl16(value);
419 PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
422 case 0x1f80104e: // baudrate register
423 sioWriteBaud16(value);
425 PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
428 #ifdef ENABLE_SIO1API
430 SIO1_writeData16(value);
433 SIO1_writeStat16(value);
436 SIO1_writeCtrl16(value);
439 SIO1_writeBaud16(value);
444 PSXHW_LOG("IREG 16bit write %x\n", value);
446 if (Config.Sio) psxHu16ref(0x1070) |= SWAPu16(0x80);
447 if (Config.SpuIrq) psxHu16ref(0x1070) |= SWAPu16(0x200);
448 psxHu16ref(0x1070) &= SWAPu16(value);
453 PSXHW_LOG("IMASK 16bit write %x\n", value);
455 psxHu16ref(0x1074) = SWAPu16(value);
456 if (psxHu16ref(0x1070) & SWAPu16(value))
457 new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
462 PSXHW_LOG("COUNTER 0 COUNT 16bit write %x\n", value);
464 psxRcntWcount(0, value); return;
467 PSXHW_LOG("COUNTER 0 MODE 16bit write %x\n", value);
469 psxRcntWmode(0, value); return;
472 PSXHW_LOG("COUNTER 0 TARGET 16bit write %x\n", value);
474 psxRcntWtarget(0, value); return;
478 PSXHW_LOG("COUNTER 1 COUNT 16bit write %x\n", value);
480 psxRcntWcount(1, value); return;
483 PSXHW_LOG("COUNTER 1 MODE 16bit write %x\n", value);
485 psxRcntWmode(1, value); return;
488 PSXHW_LOG("COUNTER 1 TARGET 16bit write %x\n", value);
490 psxRcntWtarget(1, value); return;
494 PSXHW_LOG("COUNTER 2 COUNT 16bit write %x\n", value);
496 psxRcntWcount(2, value); return;
499 PSXHW_LOG("COUNTER 2 MODE 16bit write %x\n", value);
501 psxRcntWmode(2, value); return;
504 PSXHW_LOG("COUNTER 2 TARGET 16bit write %x\n", value);
506 psxRcntWtarget(2, value); return;
509 if (add>=0x1f801c00 && add<0x1f801e00) {
510 SPU_writeRegister(add, value, psxRegs.cycle);
514 psxHu16ref(add) = SWAPu16(value);
516 PSXHW_LOG("*Unknown 16bit write at address %x value %x\n", add, value);
520 psxHu16ref(add) = SWAPu16(value);
522 PSXHW_LOG("*Known 16bit write at address %x value %x\n", add, value);
526 #define DmaExec(n) { \
527 HW_DMA##n##_CHCR = SWAPu32(value); \
529 if (SWAPu32(HW_DMA##n##_CHCR) & 0x01000000 && SWAPu32(HW_DMA_PCR) & (8 << (n * 4))) { \
530 psxDma##n(SWAPu32(HW_DMA##n##_MADR), SWAPu32(HW_DMA##n##_BCR), SWAPu32(HW_DMA##n##_CHCR)); \
534 void psxHwWrite32(u32 add, u32 value) {
535 switch (add & 0x1fffffff) {
537 sioWrite8((unsigned char)value);
538 sioWrite8((unsigned char)((value&0xff) >> 8));
539 sioWrite8((unsigned char)((value&0xff) >> 16));
540 sioWrite8((unsigned char)((value&0xff) >> 24));
542 PAD_LOG("sio write32 %x\n", value);
545 #ifdef ENABLE_SIO1API
547 SIO1_writeData32(value);
552 PSXHW_LOG("RAM size write %x\n", value);
553 psxHu32ref(add) = SWAPu32(value);
559 PSXHW_LOG("IREG 32bit write %x\n", value);
561 if (Config.Sio) psxHu32ref(0x1070) |= SWAPu32(0x80);
562 if (Config.SpuIrq) psxHu32ref(0x1070) |= SWAPu32(0x200);
563 psxHu32ref(0x1070) &= SWAPu32(value);
567 PSXHW_LOG("IMASK 32bit write %x\n", value);
569 psxHu32ref(0x1074) = SWAPu32(value);
570 if (psxHu32ref(0x1070) & SWAPu32(value))
571 new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
576 PSXHW_LOG("DMA0 MADR 32bit write %x\n", value);
577 HW_DMA0_MADR = SWAPu32(value); return; // DMA0 madr
579 PSXHW_LOG("DMA0 BCR 32bit write %x\n", value);
580 HW_DMA0_BCR = SWAPu32(value); return; // DMA0 bcr
584 PSXHW_LOG("DMA0 CHCR 32bit write %x\n", value);
586 DmaExec(0); // DMA0 chcr (MDEC in DMA)
591 PSXHW_LOG("DMA1 MADR 32bit write %x\n", value);
592 HW_DMA1_MADR = SWAPu32(value); return; // DMA1 madr
594 PSXHW_LOG("DMA1 BCR 32bit write %x\n", value);
595 HW_DMA1_BCR = SWAPu32(value); return; // DMA1 bcr
599 PSXHW_LOG("DMA1 CHCR 32bit write %x\n", value);
601 DmaExec(1); // DMA1 chcr (MDEC out DMA)
606 PSXHW_LOG("DMA2 MADR 32bit write %x\n", value);
607 HW_DMA2_MADR = SWAPu32(value); return; // DMA2 madr
609 PSXHW_LOG("DMA2 BCR 32bit write %x\n", value);
610 HW_DMA2_BCR = SWAPu32(value); return; // DMA2 bcr
614 PSXHW_LOG("DMA2 CHCR 32bit write %x\n", value);
616 DmaExec(2); // DMA2 chcr (GPU DMA)
621 PSXHW_LOG("DMA3 MADR 32bit write %x\n", value);
622 HW_DMA3_MADR = SWAPu32(value); return; // DMA3 madr
624 PSXHW_LOG("DMA3 BCR 32bit write %x\n", value);
625 HW_DMA3_BCR = SWAPu32(value); return; // DMA3 bcr
629 PSXHW_LOG("DMA3 CHCR 32bit write %x\n", value);
631 DmaExec(3); // DMA3 chcr (CDROM DMA)
637 PSXHW_LOG("DMA4 MADR 32bit write %x\n", value);
638 HW_DMA4_MADR = SWAPu32(value); return; // DMA4 madr
640 PSXHW_LOG("DMA4 BCR 32bit write %x\n", value);
641 HW_DMA4_BCR = SWAPu32(value); return; // DMA4 bcr
645 PSXHW_LOG("DMA4 CHCR 32bit write %x\n", value);
647 DmaExec(4); // DMA4 chcr (SPU DMA)
651 case 0x1f8010d0: break; //DMA5write_madr();
652 case 0x1f8010d4: break; //DMA5write_bcr();
653 case 0x1f8010d8: break; //DMA5write_chcr(); // Not needed
658 PSXHW_LOG("DMA6 MADR 32bit write %x\n", value);
659 HW_DMA6_MADR = SWAPu32(value); return; // DMA6 bcr
661 PSXHW_LOG("DMA6 BCR 32bit write %x\n", value);
662 HW_DMA6_BCR = SWAPu32(value); return; // DMA6 bcr
666 PSXHW_LOG("DMA6 CHCR 32bit write %x\n", value);
668 DmaExec(6); // DMA6 chcr (OT clear)
673 PSXHW_LOG("DMA PCR 32bit write %x\n", value);
674 HW_DMA_PCR = SWAPu32(value);
680 PSXHW_LOG("DMA ICR 32bit write %x\n", value);
683 u32 tmp = value & 0x00ff803f;
684 tmp |= (SWAPu32(HW_DMA_ICR) & ~value) & 0x7f000000;
685 if ((tmp & HW_DMA_ICR_GLOBAL_ENABLE && tmp & 0x7f000000)
686 || tmp & HW_DMA_ICR_BUS_ERROR) {
687 if (!(SWAPu32(HW_DMA_ICR) & HW_DMA_ICR_IRQ_SENT))
688 psxHu32ref(0x1070) |= SWAP32(8);
689 tmp |= HW_DMA_ICR_IRQ_SENT;
691 HW_DMA_ICR = SWAPu32(tmp);
697 PSXHW_LOG("GPU DATA 32bit write %x\n", value);
699 GPU_writeData(value); return;
702 PSXHW_LOG("GPU STATUS 32bit write %x\n", value);
704 GPU_writeStatus(value);
709 mdecWrite0(value); break;
711 mdecWrite1(value); break;
715 PSXHW_LOG("COUNTER 0 COUNT 32bit write %x\n", value);
717 psxRcntWcount(0, value & 0xffff); return;
720 PSXHW_LOG("COUNTER 0 MODE 32bit write %x\n", value);
722 psxRcntWmode(0, value); return;
725 PSXHW_LOG("COUNTER 0 TARGET 32bit write %x\n", value);
727 psxRcntWtarget(0, value & 0xffff); return; // HW_DMA_ICR&= SWAP32((~value)&0xff000000);
731 PSXHW_LOG("COUNTER 1 COUNT 32bit write %x\n", value);
733 psxRcntWcount(1, value & 0xffff); return;
736 PSXHW_LOG("COUNTER 1 MODE 32bit write %x\n", value);
738 psxRcntWmode(1, value); return;
741 PSXHW_LOG("COUNTER 1 TARGET 32bit write %x\n", value);
743 psxRcntWtarget(1, value & 0xffff); return;
747 PSXHW_LOG("COUNTER 2 COUNT 32bit write %x\n", value);
749 psxRcntWcount(2, value & 0xffff); return;
752 PSXHW_LOG("COUNTER 2 MODE 32bit write %x\n", value);
754 psxRcntWmode(2, value); return;
757 PSXHW_LOG("COUNTER 2 TARGET 32bit write %x\n", value);
759 psxRcntWtarget(2, value & 0xffff); return;
762 // Dukes of Hazard 2 - car engine noise
763 if (add>=0x1f801c00 && add<0x1f801e00) {
764 SPU_writeRegister(add, value&0xffff, psxRegs.cycle);
765 SPU_writeRegister(add + 2, value>>16, psxRegs.cycle);
769 psxHu32ref(add) = SWAPu32(value);
771 PSXHW_LOG("*Unknown 32bit write at address %x value %x\n", add, value);
775 psxHu32ref(add) = SWAPu32(value);
777 PSXHW_LOG("*Known 32bit write at address %x value %x\n", add, value);
781 int psxHwFreeze(void *f, int Mode) {