1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
3 * Copyright (C) 2009-2011 Ari64 *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
25 #include <stdint.h> //include for uint64_t
29 #include "../recomp.h"
30 #include "../recomph.h" //include for function prototypes
31 #include "../macros.h"
34 #include "../interupt.h"
35 #include "new_dynarec.h"
37 #include "../../memory/memory.h"
38 #include "../../main/rom.h"
42 #if NEW_DYNAREC == NEW_DYNAREC_X86
43 #include "assem_x86.h"
44 #elif NEW_DYNAREC == NEW_DYNAREC_ARM
45 #include "assem_arm.h"
47 #error Unsupported dynarec architecture
51 #define MAX_OUTPUT_BLOCK_SIZE 262144
52 #define CLOCK_DIVIDER count_per_op
58 signed char regmap_entry[HOST_REGS];
59 signed char regmap[HOST_REGS];
68 uint64_t constmap[HOST_REGS];
76 struct ll_entry *next;
81 static u_int pagelimit;
82 static char insn[MAXBLOCK][10];
83 static u_char itype[MAXBLOCK];
84 static u_char opcode[MAXBLOCK];
85 static u_char opcode2[MAXBLOCK];
86 static u_char bt[MAXBLOCK];
87 static u_char rs1[MAXBLOCK];
88 static u_char rs2[MAXBLOCK];
89 static u_char rt1[MAXBLOCK];
90 static u_char rt2[MAXBLOCK];
91 static u_char us1[MAXBLOCK];
92 static u_char us2[MAXBLOCK];
93 static u_char dep1[MAXBLOCK];
94 static u_char dep2[MAXBLOCK];
95 static u_char lt1[MAXBLOCK];
96 static int imm[MAXBLOCK];
97 static u_int ba[MAXBLOCK];
98 static char likely[MAXBLOCK];
99 static char is_ds[MAXBLOCK];
100 static char ooo[MAXBLOCK];
101 static uint64_t unneeded_reg[MAXBLOCK];
102 static uint64_t unneeded_reg_upper[MAXBLOCK];
103 static uint64_t branch_unneeded_reg[MAXBLOCK];
104 static uint64_t branch_unneeded_reg_upper[MAXBLOCK];
105 static uint64_t p32[MAXBLOCK];
106 static uint64_t pr32[MAXBLOCK];
107 static signed char regmap_pre[MAXBLOCK][HOST_REGS];
109 static signed char regmap[MAXBLOCK][HOST_REGS];
110 static signed char regmap_entry[MAXBLOCK][HOST_REGS];
112 static uint64_t constmap[MAXBLOCK][HOST_REGS];
113 static struct regstat regs[MAXBLOCK];
114 static struct regstat branch_regs[MAXBLOCK];
115 static signed char minimum_free_regs[MAXBLOCK];
116 static u_int needed_reg[MAXBLOCK];
117 static uint64_t requires_32bit[MAXBLOCK];
118 static u_int wont_dirty[MAXBLOCK];
119 static u_int will_dirty[MAXBLOCK];
120 static int ccadj[MAXBLOCK];
122 static u_int instr_addr[MAXBLOCK];
123 static u_int link_addr[MAXBLOCK][3];
124 static int linkcount;
125 static u_int stubs[MAXBLOCK*3][8];
126 static int stubcount;
127 static int literalcount;
128 static int is_delayslot;
129 static int cop1_usable;
131 struct ll_entry *jump_in[4096];
132 static struct ll_entry *jump_out[4096];
133 struct ll_entry *jump_dirty[4096];
134 u_int hash_table[65536][4] __attribute__((aligned(16)));
135 static char shadow[2097152] __attribute__((aligned(16)));
139 static u_int stop_after_jal;
140 extern u_char restore_candidate[512];
141 extern int cycle_count;
143 /* registers that may be allocated */
145 #define HIREG 32 // hi
146 #define LOREG 33 // lo
147 #define FSREG 34 // FPU status (FCSR)
148 #define CSREG 35 // Coprocessor status
149 #define CCREG 36 // Cycle count
150 #define INVCP 37 // Pointer to invalid_code
151 #define MMREG 38 // Pointer to memory_map
152 #define ROREG 39 // ram offset (if rdram!=0x80000000)
154 #define FTEMP 40 // FPU temporary register
155 #define PTEMP 41 // Prefetch temporary register
156 #define TLREG 42 // TLB mapping offset
157 #define RHASH 43 // Return address hash
158 #define RHTBL 44 // Return address hash table address
159 #define RTEMP 45 // JR/JALR address register
161 #define AGEN1 46 // Address generation temporary register
162 #define AGEN2 47 // Address generation temporary register
163 #define MGEN1 48 // Maptable address generation temporary register
164 #define MGEN2 49 // Maptable address generation temporary register
165 #define BTREG 50 // Branch target temporary register
167 /* instruction types */
168 #define NOP 0 // No operation
169 #define LOAD 1 // Load
170 #define STORE 2 // Store
171 #define LOADLR 3 // Unaligned load
172 #define STORELR 4 // Unaligned store
173 #define MOV 5 // Move
174 #define ALU 6 // Arithmetic/logic
175 #define MULTDIV 7 // Multiply/divide
176 #define SHIFT 8 // Shift by register
177 #define SHIFTIMM 9// Shift by immediate
178 #define IMM16 10 // 16-bit immediate
179 #define RJUMP 11 // Unconditional jump to register
180 #define UJUMP 12 // Unconditional jump
181 #define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
182 #define SJUMP 14 // Conditional branch (regimm format)
183 #define COP0 15 // Coprocessor 0
184 #define COP1 16 // Coprocessor 1
185 #define C1LS 17 // Coprocessor 1 load/store
186 #define FJUMP 18 // Conditional branch (floating point)
187 #define FLOAT 19 // Floating point unit
188 #define FCONV 20 // Convert integer to float
189 #define FCOMP 21 // Floating point compare (sets FSREG)
190 #define SYSCALL 22// SYSCALL
191 #define OTHER 23 // Other
192 #define SPAN 24 // Branch/delay slot spans 2 pages
193 #define NI 25 // Not implemented
202 #define LOADBU_STUB 7
203 #define LOADHU_STUB 8
204 #define STOREB_STUB 9
205 #define STOREH_STUB 10
206 #define STOREW_STUB 11
207 #define STORED_STUB 12
208 #define STORELR_STUB 13
209 #define INVCODE_STUB 14
216 /* bug-fix to implement __clear_cache (missing in Android; http://code.google.com/p/android/issues/detail?id=1803) */
217 void __clear_cache_bugfix(char* begin, char *end);
219 #define __clear_cache __clear_cache_bugfix
223 int new_recompile_block(int addr);
224 void *get_addr_ht(u_int vaddr);
225 static void remove_hash(int vaddr);
227 void dyna_linker_ds();
229 void verify_code_vm();
230 void verify_code_ds();
233 void fp_exception_ds();
236 #if NEW_DYNAREC == NEW_DYNAREC_ARM
237 static void invalidate_addr(u_int addr);
243 void read_nomem_new();
244 void read_nomemb_new();
245 void read_nomemh_new();
246 void read_nomemd_new();
247 void write_nomem_new();
248 void write_nomemb_new();
249 void write_nomemh_new();
250 void write_nomemd_new();
251 void write_rdram_new();
252 void write_rdramb_new();
253 void write_rdramh_new();
254 void write_rdramd_new();
255 extern u_int memory_map[1048576];
257 // Needed by assembler
258 static void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
259 static void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
260 static void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
261 static void load_all_regs(signed char i_regmap[]);
262 static void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
263 static void load_regs_entry(int t);
264 static void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
266 static void add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e);
267 static void add_to_linker(int addr,int target,int ext);
268 static int verify_dirty(void *addr);
270 //static int tracedebug=0;
272 //#define DEBUG_CYCLE_COUNT 1
274 // Uncomment these two lines to generate debug output:
275 //#define ASSEM_DEBUG 1
276 //#define INV_DEBUG 1
278 // Uncomment this line to output the number of NOTCOMPILED blocks as they occur:
279 //#define COUNT_NOTCOMPILEDS 1
281 #if defined (COUNT_NOTCOMPILEDS )
282 int notcompiledCount = 0;
284 static void nullf() {}
286 #if defined( ASSEM_DEBUG )
287 #define assem_debug(...) DebugMessage(M64MSG_VERBOSE, __VA_ARGS__)
289 #define assem_debug nullf
291 #if defined( INV_DEBUG )
292 #define inv_debug(...) DebugMessage(M64MSG_VERBOSE, __VA_ARGS__)
294 #define inv_debug nullf
297 #define log_message(...) DebugMessage(M64MSG_VERBOSE, __VA_ARGS__)
299 static void tlb_hacks()
302 if (strncmp((char *) ROM_HEADER.Name, "GOLDENEYE",9) == 0)
306 switch (ROM_HEADER.Country_code&0xFF)
318 // Unknown country code
322 u_int rom_addr=(u_int)rom;
324 // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
325 // in the lower 4G of memory to use this hack. Copy it if necessary.
326 if((void *)rom>(void *)0xffffffff) {
327 munmap(ROM_COPY, 67108864);
328 if(mmap(ROM_COPY, 12582912,
329 PROT_READ | PROT_WRITE,
330 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
331 -1, 0) <= 0) {DebugMessage(M64MSG_ERROR, "mmap() failed");}
332 memcpy(ROM_COPY,rom,12582912);
333 rom_addr=(u_int)ROM_COPY;
337 for(n=0x7F000;n<0x80000;n++) {
338 memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
344 // Get address from virtual address
345 // This is called from the recompiled JR/JALR instructions
346 void *get_addr(u_int vaddr)
348 u_int page=(vaddr^0x80000000)>>12;
350 if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
351 if(page>2048) page=2048+(page&2047);
352 if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
353 if(vpage>2048) vpage=2048+(vpage&2047);
354 struct ll_entry *head;
355 //DebugMessage(M64MSG_VERBOSE, "TRACE: count=%d next=%d (get_addr %x,page %d)",Count,next_interupt,vaddr,page);
358 if(head->vaddr==vaddr&&head->reg32==0) {
359 //DebugMessage(M64MSG_VERBOSE, "TRACE: count=%d next=%d (get_addr match %x: %x)",Count,next_interupt,vaddr,(int)head->addr);
360 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
363 ht_bin[1]=(int)head->addr;
369 head=jump_dirty[vpage];
371 if(head->vaddr==vaddr&&head->reg32==0) {
372 //DebugMessage(M64MSG_VERBOSE, "TRACE: count=%d next=%d (get_addr match dirty %x: %x)",Count,next_interupt,vaddr,(int)head->addr);
373 // Don't restore blocks which are about to expire from the cache
374 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
375 if(verify_dirty(head->addr)) {
376 //DebugMessage(M64MSG_VERBOSE, "restore candidate: %x (%d) d=%d",vaddr,page,invalid_code[vaddr>>12]);
377 invalid_code[vaddr>>12]=0;
378 memory_map[vaddr>>12]|=0x40000000;
380 if(tlb_LUT_r[vaddr>>12]) {
381 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
382 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
384 restore_candidate[vpage>>3]|=1<<(vpage&7);
386 else restore_candidate[page>>3]|=1<<(page&7);
387 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
388 if(ht_bin[0]==vaddr) {
389 ht_bin[1]=(int)head->addr; // Replace existing entry
395 ht_bin[1]=(int)head->addr;
403 //DebugMessage(M64MSG_VERBOSE, "TRACE: count=%d next=%d (get_addr no-match %x)",Count,next_interupt,vaddr);
404 int r=new_recompile_block(vaddr);
405 if(r==0) return get_addr(vaddr);
406 // Execute in unmapped page, generate pagefault execption
408 Cause=(vaddr<<31)|0x8;
409 EPC=(vaddr&1)?vaddr-5:vaddr;
411 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
412 EntryHi=BadVAddr&0xFFFFE000;
413 return get_addr_ht(0x80000000);
415 // Look up address in hash table first
416 void *get_addr_ht(u_int vaddr)
418 //DebugMessage(M64MSG_VERBOSE, "TRACE: count=%d next=%d (get_addr_ht %x)",Count,next_interupt,vaddr);
419 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
420 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
421 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
422 return get_addr(vaddr);
425 void *get_addr_32(u_int vaddr,u_int flags)
427 //DebugMessage(M64MSG_VERBOSE, "TRACE: count=%d next=%d (get_addr_32 %x,flags %x)",Count,next_interupt,vaddr,flags);
428 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
429 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
430 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
431 u_int page=(vaddr^0x80000000)>>12;
433 if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
434 if(page>2048) page=2048+(page&2047);
435 if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
436 if(vpage>2048) vpage=2048+(vpage&2047);
437 struct ll_entry *head;
440 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
441 //DebugMessage(M64MSG_VERBOSE, "TRACE: count=%d next=%d (get_addr_32 match %x: %x)",Count,next_interupt,vaddr,(int)head->addr);
443 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
445 ht_bin[1]=(int)head->addr;
447 }else if(ht_bin[2]==-1) {
448 ht_bin[3]=(int)head->addr;
451 //ht_bin[3]=ht_bin[1];
452 //ht_bin[2]=ht_bin[0];
453 //ht_bin[1]=(int)head->addr;
460 head=jump_dirty[vpage];
462 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
463 //DebugMessage(M64MSG_VERBOSE, "TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)",Count,next_interupt,vaddr,(int)head->addr);
464 // Don't restore blocks which are about to expire from the cache
465 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
466 if(verify_dirty(head->addr)) {
467 //DebugMessage(M64MSG_VERBOSE, "restore candidate: %x (%d) d=%d",vaddr,page,invalid_code[vaddr>>12]);
468 invalid_code[vaddr>>12]=0;
469 memory_map[vaddr>>12]|=0x40000000;
471 if(tlb_LUT_r[vaddr>>12]) {
472 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
473 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
475 restore_candidate[vpage>>3]|=1<<(vpage&7);
477 else restore_candidate[page>>3]|=1<<(page&7);
479 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
481 ht_bin[1]=(int)head->addr;
483 }else if(ht_bin[2]==-1) {
484 ht_bin[3]=(int)head->addr;
487 //ht_bin[3]=ht_bin[1];
488 //ht_bin[2]=ht_bin[0];
489 //ht_bin[1]=(int)head->addr;
497 //DebugMessage(M64MSG_VERBOSE, "TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)",Count,next_interupt,vaddr,flags);
498 int r=new_recompile_block(vaddr);
499 if(r==0) return get_addr(vaddr);
500 // Execute in unmapped page, generate pagefault execption
502 Cause=(vaddr<<31)|0x8;
503 EPC=(vaddr&1)?vaddr-5:vaddr;
505 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
506 EntryHi=BadVAddr&0xFFFFE000;
507 return get_addr_ht(0x80000000);
510 static void clear_all_regs(signed char regmap[])
513 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
516 static signed char get_reg(signed char regmap[],int r)
519 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map[hr]==r) return hr;
523 // Find a register that is available for two consecutive cycles
524 static signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
527 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map1[hr]==r&®map2[hr]==r) return hr;
531 static int count_free_regs(signed char regmap[])
535 for(hr=0;hr<HOST_REGS;hr++)
537 if(hr!=EXCLUDE_REG) {
538 if(regmap[hr]<0) count++;
544 static void dirty_reg(struct regstat *cur,signed char reg)
548 for (hr=0;hr<HOST_REGS;hr++) {
549 if((cur->regmap[hr]&63)==reg) {
555 // If we dirty the lower half of a 64 bit register which is now being
556 // sign-extended, we need to dump the upper half.
557 // Note: Do this only after completion of the instruction, because
558 // some instructions may need to read the full 64-bit value even if
559 // overwriting it (eg SLTI, DSRA32).
560 static void flush_dirty_uppers(struct regstat *cur)
563 for (hr=0;hr<HOST_REGS;hr++) {
564 if((cur->dirty>>hr)&1) {
567 if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
572 static void set_const(struct regstat *cur,signed char reg,uint64_t value)
576 for (hr=0;hr<HOST_REGS;hr++) {
577 if(cur->regmap[hr]==reg) {
579 cur->constmap[hr]=value;
581 else if((cur->regmap[hr]^64)==reg) {
583 cur->constmap[hr]=value>>32;
588 static void clear_const(struct regstat *cur,signed char reg)
592 for (hr=0;hr<HOST_REGS;hr++) {
593 if((cur->regmap[hr]&63)==reg) {
594 cur->isconst&=~(1<<hr);
599 static int is_const(struct regstat *cur,signed char reg)
604 for (hr=0;hr<HOST_REGS;hr++) {
605 if((cur->regmap[hr]&63)==reg) {
606 return (cur->isconst>>hr)&1;
611 static uint64_t get_const(struct regstat *cur,signed char reg)
615 for (hr=0;hr<HOST_REGS;hr++) {
616 if(cur->regmap[hr]==reg) {
617 return cur->constmap[hr];
620 DebugMessage(M64MSG_ERROR, "Unknown constant in r%d",reg);
624 // Least soon needed registers
625 // Look at the next ten instructions and see which registers
626 // will be used. Try not to reallocate these.
627 static void lsn(u_char hsn[], int i, int *preferred_reg)
637 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
639 // Don't go past an unconditonal jump
646 if(rs1[i+j]) hsn[rs1[i+j]]=j;
647 if(rs2[i+j]) hsn[rs2[i+j]]=j;
648 if(rt1[i+j]) hsn[rt1[i+j]]=j;
649 if(rt2[i+j]) hsn[rt2[i+j]]=j;
650 if(itype[i+j]==STORE || itype[i+j]==STORELR) {
651 // Stores can allocate zero
655 // On some architectures stores need invc_ptr
656 #if defined(HOST_IMM8)
657 if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39) {
661 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
669 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
671 // Follow first branch
672 int t=(ba[i+b]-start)>>2;
673 j=7-b;if(t+j>=slen) j=slen-t-1;
676 if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
677 if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
678 //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
679 //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
682 // TODO: preferred register based on backward branch
684 // Delay slot should preferably not overwrite branch conditions or cycle count
685 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
686 if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
687 if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
693 // Coprocessor load/store needs FTEMP, even if not declared
697 // Load L/R also uses FTEMP as a temporary register
698 if(itype[i]==LOADLR) {
701 // Also 64-bit SDL/SDR
702 if(opcode[i]==0x2c||opcode[i]==0x2d) {
705 // Don't remove the TLB registers either
706 if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS ) {
709 // Don't remove the miniht registers
710 if(itype[i]==UJUMP||itype[i]==RJUMP)
717 // We only want to allocate registers if we're going to use them again soon
718 static int needed_again(int r, int i)
724 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
726 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
727 return 0; // Don't need any registers if exiting the block
735 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
737 // Don't go past an unconditonal jump
741 if(itype[i+j]==SYSCALL||((source[i+j]&0xfc00003f)==0x0d))
748 if(rs1[i+j]==r) rn=j;
749 if(rs2[i+j]==r) rn=j;
750 if((unneeded_reg[i+j]>>r)&1) rn=10;
751 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
759 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
761 // Follow first branch
763 int t=(ba[i+b]-start)>>2;
764 j=7-b;if(t+j>=slen) j=slen-t-1;
767 if(!((unneeded_reg[t+j]>>r)&1)) {
768 if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
769 if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
779 // Try to match register allocations at the end of a loop with those
781 static int loop_reg(int i, int r, int hr)
790 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
792 // Don't go past an unconditonal jump
799 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
804 if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
805 if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
806 if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
808 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
810 int t=(ba[i+k]-start)>>2;
811 int reg=get_reg(regs[t].regmap_entry,r);
812 if(reg>=0) return reg;
813 //reg=get_reg(regs[t+1].regmap_entry,r);
814 //if(reg>=0) return reg;
822 // Allocate every register, preserving source/target regs
823 static void alloc_all(struct regstat *cur,int i)
827 for(hr=0;hr<HOST_REGS;hr++) {
828 if(hr!=EXCLUDE_REG) {
829 if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
830 ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
833 cur->dirty&=~(1<<hr);
836 if((cur->regmap[hr]&63)==0)
839 cur->dirty&=~(1<<hr);
846 static void div64(int64_t dividend,int64_t divisor)
848 if ((dividend) && (divisor)) {
855 //DebugMessage(M64MSG_VERBOSE, "TRACE: ddiv %8x%8x %8x%8x" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
856 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
858 static void divu64(uint64_t dividend,uint64_t divisor)
860 if ((dividend) && (divisor)) {
867 //DebugMessage(M64MSG_VERBOSE, "TRACE: ddivu %8x%8x %8x%8x",(int)reg[HIREG],(int)(reg[HIREG]>>32)
868 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
870 static void div32(int32_t dividend,int32_t divisor)
872 if ((dividend) && (divisor)) {
879 //DebugMessage(M64MSG_VERBOSE, "TRACE: ddiv %8x%8x %8x%8x" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
880 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
882 static void divu32(uint32_t dividend,uint32_t divisor)
884 if ((dividend) && (divisor)) {
891 //DebugMessage(M64MSG_VERBOSE, "TRACE: ddivu %8x%8x %8x%8x",(int)reg[HIREG],(int)(reg[HIREG]>>32)
892 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
895 static void mult64(int64_t m1,int64_t m2)
897 uint64_t op1, op2, op3, op4;
898 uint64_t result1, result2, result3, result4;
899 uint64_t temp1, temp2, temp3, temp4;
915 op1 = op2 & 0xFFFFFFFF;
916 op2 = (op2 >> 32) & 0xFFFFFFFF;
917 op3 = op4 & 0xFFFFFFFF;
918 op4 = (op4 >> 32) & 0xFFFFFFFF;
921 temp2 = (temp1 >> 32) + op1 * op4;
923 temp4 = (temp3 >> 32) + op2 * op4;
925 result1 = temp1 & 0xFFFFFFFF;
926 result2 = temp2 + (temp3 & 0xFFFFFFFF);
927 result3 = (result2 >> 32) + temp4;
928 result4 = (result3 >> 32);
930 lo = result1 | (result2 << 32);
931 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
940 #if NEW_DYNAREC == NEW_DYNAREC_ARM
941 static void multu64(uint64_t m1,uint64_t m2)
943 uint64_t op1, op2, op3, op4;
944 uint64_t result1, result2, result3, result4;
945 uint64_t temp1, temp2, temp3, temp4;
947 op1 = m1 & 0xFFFFFFFF;
948 op2 = (m1 >> 32) & 0xFFFFFFFF;
949 op3 = m2 & 0xFFFFFFFF;
950 op4 = (m2 >> 32) & 0xFFFFFFFF;
953 temp2 = (temp1 >> 32) + op1 * op4;
955 temp4 = (temp3 >> 32) + op2 * op4;
957 result1 = temp1 & 0xFFFFFFFF;
958 result2 = temp2 + (temp3 & 0xFFFFFFFF);
959 result3 = (result2 >> 32) + temp4;
960 result4 = (result3 >> 32);
962 lo = result1 | (result2 << 32);
963 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
965 //DebugMessage(M64MSG_VERBOSE, "TRACE: dmultu %8x%8x %8x%8x",(int)reg[HIREG],(int)(reg[HIREG]>>32)
966 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
970 static uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
978 else original=loaded;
981 static uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
984 original>>=64-(bits^56);
985 original<<=64-(bits^56);
989 else original=loaded;
993 #if NEW_DYNAREC == NEW_DYNAREC_X86
994 #include "assem_x86.c"
995 #elif NEW_DYNAREC == NEW_DYNAREC_ARM
996 #include "assem_arm.c"
998 #error Unsupported dynarec architecture
1001 // Add virtual address mapping to linked list
1002 static void ll_add(struct ll_entry **head,int vaddr,void *addr)
1004 struct ll_entry *new_entry;
1005 new_entry=malloc(sizeof(struct ll_entry));
1006 assert(new_entry!=NULL);
1007 new_entry->vaddr=vaddr;
1009 new_entry->addr=addr;
1010 new_entry->next=*head;
1014 // Add virtual address mapping for 32-bit compiled block
1015 static void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
1017 struct ll_entry *new_entry;
1018 new_entry=malloc(sizeof(struct ll_entry));
1019 assert(new_entry!=NULL);
1020 new_entry->vaddr=vaddr;
1021 new_entry->reg32=reg32;
1022 new_entry->addr=addr;
1023 new_entry->next=*head;
1027 // Check if an address is already compiled
1028 // but don't return addresses which are about to expire from the cache
1029 static void *check_addr(u_int vaddr)
1031 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
1032 if(ht_bin[0]==vaddr) {
1033 if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1034 if(isclean(ht_bin[1])) return (void *)ht_bin[1];
1036 if(ht_bin[2]==vaddr) {
1037 if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1038 if(isclean(ht_bin[3])) return (void *)ht_bin[3];
1040 u_int page=(vaddr^0x80000000)>>12;
1041 if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
1042 if(page>2048) page=2048+(page&2047);
1043 struct ll_entry *head;
1046 if(head->vaddr==vaddr&&head->reg32==0) {
1047 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1048 // Update existing entry with current address
1049 if(ht_bin[0]==vaddr) {
1050 ht_bin[1]=(int)head->addr;
1053 if(ht_bin[2]==vaddr) {
1054 ht_bin[3]=(int)head->addr;
1057 // Insert into hash table with low priority.
1058 // Don't evict existing entries, as they are probably
1059 // addresses that are being accessed frequently.
1061 ht_bin[1]=(int)head->addr;
1063 }else if(ht_bin[2]==-1) {
1064 ht_bin[3]=(int)head->addr;
1075 static void remove_hash(int vaddr)
1077 //DebugMessage(M64MSG_VERBOSE, "remove hash: %x",vaddr);
1078 u_int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1079 if(ht_bin[2]==vaddr) {
1080 ht_bin[2]=ht_bin[3]=-1;
1082 if(ht_bin[0]==vaddr) {
1083 ht_bin[0]=ht_bin[2];
1084 ht_bin[1]=ht_bin[3];
1085 ht_bin[2]=ht_bin[3]=-1;
1089 static void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1091 struct ll_entry *next;
1093 if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1094 ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1096 inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1097 remove_hash((*head)->vaddr);
1104 head=&((*head)->next);
1109 // Remove all entries from linked list
1110 static void ll_clear(struct ll_entry **head)
1112 struct ll_entry *cur;
1113 struct ll_entry *next;
1124 // Dereference the pointers and remove if it matches
1125 static void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1128 int ptr=get_pointer(head->addr);
1129 inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1130 if(((ptr>>shift)==(addr>>shift)) ||
1131 (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1133 inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1134 u_int host_addr=(int)kill_pointer(head->addr);
1135 #if NEW_DYNAREC == NEW_DYNAREC_ARM
1136 needs_clear_cache[(host_addr-(u_int)base_addr)>>17]|=1<<(((host_addr-(u_int)base_addr)>>12)&31);
1143 // This is called when we write to a compiled block (see do_invstub)
1144 static void invalidate_page(u_int page)
1146 struct ll_entry *head;
1147 struct ll_entry *next;
1151 inv_debug("INVALIDATE: %x\n",head->vaddr);
1152 remove_hash(head->vaddr);
1157 head=jump_out[page];
1160 inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
1161 u_int host_addr=(int)kill_pointer(head->addr);
1162 #if NEW_DYNAREC == NEW_DYNAREC_ARM
1163 needs_clear_cache[(host_addr-(u_int)base_addr)>>17]|=1<<(((host_addr-(u_int)base_addr)>>12)&31);
1170 void invalidate_block(u_int block)
1173 page=vpage=block^0x80000;
1174 if(page>262143&&tlb_LUT_r[block]) page=(tlb_LUT_r[block]^0x80000000)>>12;
1175 if(page>2048) page=2048+(page&2047);
1176 if(vpage>262143&&tlb_LUT_r[block]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
1177 if(vpage>2048) vpage=2048+(vpage&2047);
1178 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1179 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1182 struct ll_entry *head;
1183 head=jump_dirty[vpage];
1184 //DebugMessage(M64MSG_VERBOSE, "page=%d vpage=%d",page,vpage);
1187 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1188 get_bounds((int)head->addr,&start,&end);
1189 //DebugMessage(M64MSG_VERBOSE, "start: %x end: %x",start,end);
1190 if(page<2048&&start>=0x80000000&&end<0x80800000) {
1191 if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1192 if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1193 if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1196 if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1197 if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1198 if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1199 if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1205 //DebugMessage(M64MSG_VERBOSE, "first=%d last=%d",first,last);
1206 invalidate_page(page);
1207 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1208 assert(last<page+5);
1209 // Invalidate the adjacent pages if a block crosses a 4K boundary
1211 invalidate_page(first);
1214 for(first=page+1;first<last;first++) {
1215 invalidate_page(first);
1217 #if NEW_DYNAREC == NEW_DYNAREC_ARM
1221 // Don't trap writes
1222 invalid_code[block]=1;
1223 // If there is a valid TLB entry for this page, remove write protect
1224 if(tlb_LUT_w[block]) {
1225 assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1226 // CHECK: Is this right?
1227 memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1228 u_int real_block=tlb_LUT_w[block]>>12;
1229 invalid_code[real_block]=1;
1230 if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1232 else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
1234 memset(mini_ht,-1,sizeof(mini_ht));
1238 #if NEW_DYNAREC == NEW_DYNAREC_ARM
1239 static void invalidate_addr(u_int addr)
1241 invalidate_block(addr>>12);
1245 // This is called when loading a save state.
1246 // Anything could have changed, so invalidate everything.
1247 void invalidate_all_pages()
1250 for(page=0;page<4096;page++)
1251 invalidate_page(page);
1252 for(page=0;page<1048576;page++)
1253 if(!invalid_code[page]) {
1254 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1255 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1257 #if NEW_DYNAREC == NEW_DYNAREC_ARM
1258 __clear_cache((void *)base_addr,(void *)base_addr+(1<<TARGET_SIZE_2));
1259 //cacheflush((void *)base_addr,(void *)base_addr+(1<<TARGET_SIZE_2),0);
1262 memset(mini_ht,-1,sizeof(mini_ht));
1265 for(page=0;page<0x100000;page++) {
1266 if(tlb_LUT_r[page]) {
1267 memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1268 if(!tlb_LUT_w[page]||!invalid_code[page])
1269 memory_map[page]|=0x40000000; // Write protect
1271 else memory_map[page]=-1;
1272 if(page==0x80000) page=0xC0000;
1277 // Add an entry to jump_out after making a link
1278 void add_link(u_int vaddr,void *src)
1280 u_int page=(vaddr^0x80000000)>>12;
1281 if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
1282 if(page>4095) page=2048+(page&2047);
1283 inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1284 ll_add(jump_out+page,vaddr,src);
1285 //int ptr=get_pointer(src);
1286 //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1289 // If a code block was found to be unmodified (bit was set in
1290 // restore_candidate) and it remains unmodified (bit is clear
1291 // in invalid_code) then move the entries for that 4K page from
1292 // the dirty list to the clean list.
1293 void clean_blocks(u_int page)
1295 struct ll_entry *head;
1296 inv_debug("INV: clean_blocks page=%d\n",page);
1297 head=jump_dirty[page];
1299 if(!invalid_code[head->vaddr>>12]) {
1300 // Don't restore blocks which are about to expire from the cache
1301 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1303 if(verify_dirty(head->addr)) {
1304 //DebugMessage(M64MSG_VERBOSE, "Possibly Restore %x (%x)",head->vaddr, (int)head->addr);
1307 get_bounds((int)head->addr,&start,&end);
1308 if(start-(u_int)rdram<0x800000) {
1309 for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1310 inv|=invalid_code[i];
1313 if((signed int)head->vaddr>=(signed int)0xC0000000) {
1314 u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1315 //DebugMessage(M64MSG_VERBOSE, "addr=%x start=%x end=%x",addr,start,end);
1316 if(addr<start||addr>=end) inv=1;
1318 else if((signed int)head->vaddr>=(signed int)0x80800000) {
1322 void * clean_addr=(void *)get_clean_addr((int)head->addr);
1323 if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1325 if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
1326 inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1327 //DebugMessage(M64MSG_VERBOSE, "page=%x, addr=%x",page,head->vaddr);
1328 //assert(head->vaddr>>12==(page|0x80000));
1329 ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1330 u_int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1332 if(ht_bin[0]==head->vaddr) {
1333 ht_bin[1]=(int)clean_addr; // Replace existing entry
1335 if(ht_bin[2]==head->vaddr) {
1336 ht_bin[3]=(int)clean_addr; // Replace existing entry
1349 static void mov_alloc(struct regstat *current,int i)
1351 // Note: Don't need to actually alloc the source registers
1352 if((~current->is32>>rs1[i])&1) {
1353 //alloc_reg64(current,i,rs1[i]);
1354 alloc_reg64(current,i,rt1[i]);
1355 current->is32&=~(1LL<<rt1[i]);
1357 //alloc_reg(current,i,rs1[i]);
1358 alloc_reg(current,i,rt1[i]);
1359 current->is32|=(1LL<<rt1[i]);
1361 clear_const(current,rs1[i]);
1362 clear_const(current,rt1[i]);
1363 dirty_reg(current,rt1[i]);
1366 static void shiftimm_alloc(struct regstat *current,int i)
1368 clear_const(current,rs1[i]);
1369 clear_const(current,rt1[i]);
1370 if(opcode2[i]<=0x3) // SLL/SRL/SRA
1373 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1375 alloc_reg(current,i,rt1[i]);
1376 current->is32|=1LL<<rt1[i];
1377 dirty_reg(current,rt1[i]);
1380 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1383 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1384 alloc_reg64(current,i,rt1[i]);
1385 current->is32&=~(1LL<<rt1[i]);
1386 dirty_reg(current,rt1[i]);
1389 if(opcode2[i]==0x3c) // DSLL32
1392 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1393 alloc_reg64(current,i,rt1[i]);
1394 current->is32&=~(1LL<<rt1[i]);
1395 dirty_reg(current,rt1[i]);
1398 if(opcode2[i]==0x3e) // DSRL32
1401 alloc_reg64(current,i,rs1[i]);
1403 alloc_reg64(current,i,rt1[i]);
1404 current->is32&=~(1LL<<rt1[i]);
1406 alloc_reg(current,i,rt1[i]);
1407 current->is32|=1LL<<rt1[i];
1409 dirty_reg(current,rt1[i]);
1412 if(opcode2[i]==0x3f) // DSRA32
1415 alloc_reg64(current,i,rs1[i]);
1416 alloc_reg(current,i,rt1[i]);
1417 current->is32|=1LL<<rt1[i];
1418 dirty_reg(current,rt1[i]);
1423 static void shift_alloc(struct regstat *current,int i)
1426 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1428 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1429 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1430 alloc_reg(current,i,rt1[i]);
1431 if(rt1[i]==rs2[i]) {
1432 alloc_reg_temp(current,i,-1);
1433 minimum_free_regs[i]=1;
1435 current->is32|=1LL<<rt1[i];
1436 } else { // DSLLV/DSRLV/DSRAV
1437 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1438 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1439 alloc_reg64(current,i,rt1[i]);
1440 current->is32&=~(1LL<<rt1[i]);
1441 if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1443 alloc_reg_temp(current,i,-1);
1444 minimum_free_regs[i]=1;
1447 clear_const(current,rs1[i]);
1448 clear_const(current,rs2[i]);
1449 clear_const(current,rt1[i]);
1450 dirty_reg(current,rt1[i]);
1454 static void alu_alloc(struct regstat *current,int i)
1456 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1458 if(rs1[i]&&rs2[i]) {
1459 alloc_reg(current,i,rs1[i]);
1460 alloc_reg(current,i,rs2[i]);
1463 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1464 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1466 alloc_reg(current,i,rt1[i]);
1468 current->is32|=1LL<<rt1[i];
1470 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1472 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1474 alloc_reg64(current,i,rs1[i]);
1475 alloc_reg64(current,i,rs2[i]);
1476 alloc_reg(current,i,rt1[i]);
1478 alloc_reg(current,i,rs1[i]);
1479 alloc_reg(current,i,rs2[i]);
1480 alloc_reg(current,i,rt1[i]);
1483 current->is32|=1LL<<rt1[i];
1485 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1487 if(rs1[i]&&rs2[i]) {
1488 alloc_reg(current,i,rs1[i]);
1489 alloc_reg(current,i,rs2[i]);
1493 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1494 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1496 alloc_reg(current,i,rt1[i]);
1497 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1499 if(!((current->uu>>rt1[i])&1)) {
1500 alloc_reg64(current,i,rt1[i]);
1502 if(get_reg(current->regmap,rt1[i]|64)>=0) {
1503 if(rs1[i]&&rs2[i]) {
1504 alloc_reg64(current,i,rs1[i]);
1505 alloc_reg64(current,i,rs2[i]);
1509 // Is is really worth it to keep 64-bit values in registers?
1511 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1512 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1516 current->is32&=~(1LL<<rt1[i]);
1518 current->is32|=1LL<<rt1[i];
1522 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1524 if(rs1[i]&&rs2[i]) {
1525 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1526 alloc_reg64(current,i,rs1[i]);
1527 alloc_reg64(current,i,rs2[i]);
1528 alloc_reg64(current,i,rt1[i]);
1530 alloc_reg(current,i,rs1[i]);
1531 alloc_reg(current,i,rs2[i]);
1532 alloc_reg(current,i,rt1[i]);
1536 alloc_reg(current,i,rt1[i]);
1537 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1538 // DADD used as move, or zeroing
1539 // If we have a 64-bit source, then make the target 64 bits too
1540 if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1541 if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1542 alloc_reg64(current,i,rt1[i]);
1543 } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1544 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1545 alloc_reg64(current,i,rt1[i]);
1547 if(opcode2[i]>=0x2e&&rs2[i]) {
1548 // DSUB used as negation - 64-bit result
1549 // If we have a 32-bit register, extend it to 64 bits
1550 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1551 alloc_reg64(current,i,rt1[i]);
1555 if(rs1[i]&&rs2[i]) {
1556 current->is32&=~(1LL<<rt1[i]);
1558 current->is32&=~(1LL<<rt1[i]);
1559 if((current->is32>>rs1[i])&1)
1560 current->is32|=1LL<<rt1[i];
1562 current->is32&=~(1LL<<rt1[i]);
1563 if((current->is32>>rs2[i])&1)
1564 current->is32|=1LL<<rt1[i];
1566 current->is32|=1LL<<rt1[i];
1570 clear_const(current,rs1[i]);
1571 clear_const(current,rs2[i]);
1572 clear_const(current,rt1[i]);
1573 dirty_reg(current,rt1[i]);
1576 static void imm16_alloc(struct regstat *current,int i)
1578 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1580 if(rt1[i]) alloc_reg(current,i,rt1[i]);
1581 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1582 current->is32&=~(1LL<<rt1[i]);
1583 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1584 // TODO: Could preserve the 32-bit flag if the immediate is zero
1585 alloc_reg64(current,i,rt1[i]);
1586 alloc_reg64(current,i,rs1[i]);
1588 clear_const(current,rs1[i]);
1589 clear_const(current,rt1[i]);
1591 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1592 if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1593 current->is32|=1LL<<rt1[i];
1594 clear_const(current,rs1[i]);
1595 clear_const(current,rt1[i]);
1597 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1598 if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1599 if(rs1[i]!=rt1[i]) {
1600 if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1601 alloc_reg64(current,i,rt1[i]);
1602 current->is32&=~(1LL<<rt1[i]);
1605 else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1606 if(is_const(current,rs1[i])) {
1607 int v=get_const(current,rs1[i]);
1608 if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1609 if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1610 if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1612 else clear_const(current,rt1[i]);
1614 else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1615 if(is_const(current,rs1[i])) {
1616 int v=get_const(current,rs1[i]);
1617 set_const(current,rt1[i],v+imm[i]);
1619 else clear_const(current,rt1[i]);
1620 current->is32|=1LL<<rt1[i];
1623 set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1624 current->is32|=1LL<<rt1[i];
1626 dirty_reg(current,rt1[i]);
1629 static void load_alloc(struct regstat *current,int i)
1631 clear_const(current,rt1[i]);
1632 //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1633 if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1634 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1635 if(rt1[i]&&!((current->u>>rt1[i])&1)) {
1636 alloc_reg(current,i,rt1[i]);
1637 assert(get_reg(current->regmap,rt1[i])>=0);
1638 if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1640 current->is32&=~(1LL<<rt1[i]);
1641 alloc_reg64(current,i,rt1[i]);
1643 else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1645 current->is32&=~(1LL<<rt1[i]);
1646 alloc_reg64(current,i,rt1[i]);
1647 alloc_all(current,i);
1648 alloc_reg64(current,i,FTEMP);
1649 minimum_free_regs[i]=HOST_REGS;
1651 else current->is32|=1LL<<rt1[i];
1652 dirty_reg(current,rt1[i]);
1653 // If using TLB, need a register for pointer to the mapping table
1654 if(using_tlb) alloc_reg(current,i,TLREG);
1655 // LWL/LWR need a temporary register for the old value
1656 if(opcode[i]==0x22||opcode[i]==0x26)
1658 alloc_reg(current,i,FTEMP);
1659 alloc_reg_temp(current,i,-1);
1660 minimum_free_regs[i]=1;
1665 // Load to r0 or unneeded register (dummy load)
1666 // but we still need a register to calculate the address
1667 if(opcode[i]==0x22||opcode[i]==0x26)
1669 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1671 // If using TLB, need a register for pointer to the mapping table
1672 if(using_tlb) alloc_reg(current,i,TLREG);
1673 alloc_reg_temp(current,i,-1);
1674 minimum_free_regs[i]=1;
1675 if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1677 alloc_all(current,i);
1678 alloc_reg64(current,i,FTEMP);
1679 minimum_free_regs[i]=HOST_REGS;
1684 static void store_alloc(struct regstat *current,int i)
1686 clear_const(current,rs2[i]);
1687 if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1688 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1689 alloc_reg(current,i,rs2[i]);
1690 if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1691 alloc_reg64(current,i,rs2[i]);
1692 if(rs2[i]) alloc_reg(current,i,FTEMP);
1694 // If using TLB, need a register for pointer to the mapping table
1695 if(using_tlb) alloc_reg(current,i,TLREG);
1696 #if defined(HOST_IMM8)
1697 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1698 else alloc_reg(current,i,INVCP);
1700 if(opcode[i]==0x2c||opcode[i]==0x2d) { // 64-bit SDL/SDR
1701 alloc_reg(current,i,FTEMP);
1703 // We need a temporary register for address generation
1704 alloc_reg_temp(current,i,-1);
1705 minimum_free_regs[i]=1;
1708 static void c1ls_alloc(struct regstat *current,int i)
1710 //clear_const(current,rs1[i]); // FIXME
1711 clear_const(current,rt1[i]);
1712 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1713 alloc_reg(current,i,CSREG); // Status
1714 alloc_reg(current,i,FTEMP);
1715 if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1716 alloc_reg64(current,i,FTEMP);
1718 // If using TLB, need a register for pointer to the mapping table
1719 if(using_tlb) alloc_reg(current,i,TLREG);
1720 #if defined(HOST_IMM8)
1721 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1722 else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1723 alloc_reg(current,i,INVCP);
1725 // We need a temporary register for address generation
1726 alloc_reg_temp(current,i,-1);
1727 minimum_free_regs[i]=1;
1730 #ifndef multdiv_alloc
1731 void multdiv_alloc(struct regstat *current,int i)
1738 // case 0x1D: DMULTU
1741 clear_const(current,rs1[i]);
1742 clear_const(current,rs2[i]);
1745 if((opcode2[i]&4)==0) // 32-bit
1747 current->u&=~(1LL<<HIREG);
1748 current->u&=~(1LL<<LOREG);
1749 alloc_reg(current,i,HIREG);
1750 alloc_reg(current,i,LOREG);
1751 alloc_reg(current,i,rs1[i]);
1752 alloc_reg(current,i,rs2[i]);
1753 current->is32|=1LL<<HIREG;
1754 current->is32|=1LL<<LOREG;
1755 dirty_reg(current,HIREG);
1756 dirty_reg(current,LOREG);
1760 current->u&=~(1LL<<HIREG);
1761 current->u&=~(1LL<<LOREG);
1762 current->uu&=~(1LL<<HIREG);
1763 current->uu&=~(1LL<<LOREG);
1764 alloc_reg64(current,i,HIREG);
1765 //if(HOST_REGS>10) alloc_reg64(current,i,LOREG); //*SEB* Why commenting this line? uncommenting make SM64 freeze after title (before mario head and spinning stars)
1766 alloc_reg64(current,i,rs1[i]);
1767 alloc_reg64(current,i,rs2[i]);
1768 alloc_all(current,i);
1769 current->is32&=~(1LL<<HIREG);
1770 current->is32&=~(1LL<<LOREG);
1771 dirty_reg(current,HIREG);
1772 dirty_reg(current,LOREG);
1773 minimum_free_regs[i]=HOST_REGS;
1778 // Multiply by zero is zero.
1779 // MIPS does not have a divide by zero exception.
1780 // The result is undefined, we return zero.
1781 alloc_reg(current,i,HIREG);
1782 alloc_reg(current,i,LOREG);
1783 current->is32|=1LL<<HIREG;
1784 current->is32|=1LL<<LOREG;
1785 dirty_reg(current,HIREG);
1786 dirty_reg(current,LOREG);
1791 static void cop0_alloc(struct regstat *current,int i)
1793 if(opcode2[i]==0) // MFC0
1796 clear_const(current,rt1[i]);
1797 alloc_all(current,i);
1798 alloc_reg(current,i,rt1[i]);
1799 current->is32|=1LL<<rt1[i];
1800 dirty_reg(current,rt1[i]);
1803 else if(opcode2[i]==4) // MTC0
1806 clear_const(current,rs1[i]);
1807 alloc_reg(current,i,rs1[i]);
1808 alloc_all(current,i);
1811 alloc_all(current,i); // FIXME: Keep r0
1813 alloc_reg(current,i,0);
1818 // TLBR/TLBWI/TLBWR/TLBP/ERET
1819 assert(opcode2[i]==0x10);
1820 alloc_all(current,i);
1822 minimum_free_regs[i]=HOST_REGS;
1825 static void cop1_alloc(struct regstat *current,int i)
1827 alloc_reg(current,i,CSREG); // Load status
1828 if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1831 clear_const(current,rt1[i]);
1833 alloc_reg64(current,i,rt1[i]); // DMFC1
1834 current->is32&=~(1LL<<rt1[i]);
1836 alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1837 current->is32|=1LL<<rt1[i];
1839 dirty_reg(current,rt1[i]);
1840 alloc_reg_temp(current,i,-1);
1842 else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1845 clear_const(current,rs1[i]);
1847 alloc_reg64(current,i,rs1[i]); // DMTC1
1849 alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1850 alloc_reg_temp(current,i,-1);
1854 alloc_reg(current,i,0);
1855 alloc_reg_temp(current,i,-1);
1858 minimum_free_regs[i]=1;
1860 static void fconv_alloc(struct regstat *current,int i)
1862 alloc_reg(current,i,CSREG); // Load status
1863 alloc_reg_temp(current,i,-1);
1864 minimum_free_regs[i]=1;
1866 static void float_alloc(struct regstat *current,int i)
1868 alloc_reg(current,i,CSREG); // Load status
1869 alloc_reg_temp(current,i,-1);
1870 minimum_free_regs[i]=1;
1872 static void fcomp_alloc(struct regstat *current,int i)
1874 alloc_reg(current,i,CSREG); // Load status
1875 alloc_reg(current,i,FSREG); // Load flags
1876 dirty_reg(current,FSREG); // Flag will be modified
1877 alloc_reg_temp(current,i,-1);
1878 minimum_free_regs[i]=1;
1881 static void syscall_alloc(struct regstat *current,int i)
1883 alloc_cc(current,i);
1884 dirty_reg(current,CCREG);
1885 alloc_all(current,i);
1886 minimum_free_regs[i]=HOST_REGS;
1890 static void delayslot_alloc(struct regstat *current,int i)
1900 assem_debug("jump in the delay slot. this shouldn't happen.");//exit(1);
1901 DebugMessage(M64MSG_VERBOSE, "Disabled speculative precompilation");
1905 imm16_alloc(current,i);
1909 load_alloc(current,i);
1913 store_alloc(current,i);
1916 alu_alloc(current,i);
1919 shift_alloc(current,i);
1922 multdiv_alloc(current,i);
1925 shiftimm_alloc(current,i);
1928 mov_alloc(current,i);
1931 cop0_alloc(current,i);
1934 cop1_alloc(current,i);
1937 c1ls_alloc(current,i);
1940 fconv_alloc(current,i);
1943 float_alloc(current,i);
1946 fcomp_alloc(current,i);
1951 // Special case where a branch and delay slot span two pages in virtual memory
1952 static void pagespan_alloc(struct regstat *current,int i)
1955 current->wasconst=0;
1957 minimum_free_regs[i]=HOST_REGS;
1958 alloc_all(current,i);
1959 alloc_cc(current,i);
1960 dirty_reg(current,CCREG);
1961 if(opcode[i]==3) // JAL
1963 alloc_reg(current,i,31);
1964 dirty_reg(current,31);
1966 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
1968 alloc_reg(current,i,rs1[i]);
1970 alloc_reg(current,i,rt1[i]);
1971 dirty_reg(current,rt1[i]);
1974 if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
1976 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1977 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1978 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1980 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1981 if(rs2[i]) alloc_reg64(current,i,rs2[i]);
1985 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
1987 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1988 if(!((current->is32>>rs1[i])&1))
1990 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1994 if(opcode[i]==0x11) // BC1
1996 alloc_reg(current,i,FSREG);
1997 alloc_reg(current,i,CSREG);
2002 static void add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
2004 stubs[stubcount][0]=type;
2005 stubs[stubcount][1]=addr;
2006 stubs[stubcount][2]=retaddr;
2007 stubs[stubcount][3]=a;
2008 stubs[stubcount][4]=b;
2009 stubs[stubcount][5]=c;
2010 stubs[stubcount][6]=d;
2011 stubs[stubcount][7]=e;
2015 // Write out a single register
2016 static void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
2019 for(hr=0;hr<HOST_REGS;hr++) {
2020 if(hr!=EXCLUDE_REG) {
2021 if((regmap[hr]&63)==r) {
2024 emit_storereg(r,hr);
2025 if((is32>>regmap[hr])&1) {
2026 emit_sarimm(hr,31,hr);
2027 emit_storereg(r|64,hr);
2030 emit_storereg(r|64,hr);
2038 static int mchecksum()
2040 //if(!tracedebug) return 0;
2043 for(i=0;i<2097152;i++) {
2044 unsigned int temp=sum;
2047 sum^=((u_int *)rdram)[i];
2052 static int rchecksum()
2057 sum^=((u_int *)reg)[i];
2064 DebugMessage(M64MSG_VERBOSE, "TRACE: ");
2066 DebugMessage(M64MSG_VERBOSE, "r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2067 DebugMessage(M64MSG_VERBOSE, "TRACE: ");
2069 DebugMessage(M64MSG_VERBOSE, "f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2072 static void enabletrace()
2078 static void memdebug(int i)
2080 //DebugMessage(M64MSG_VERBOSE, "TRACE: count=%d next=%d (checksum %x) lo=%8x%8x",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2081 //DebugMessage(M64MSG_VERBOSE, "TRACE: count=%d next=%d (rchecksum %x)",Count,next_interupt,rchecksum());
2084 //if(Count>=-2084597794) {
2085 if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2087 DebugMessage(M64MSG_VERBOSE, "TRACE: count=%d next=%d (checksum %x)",Count,next_interupt,mchecksum());
2088 //DebugMessage(M64MSG_VERBOSE, "TRACE: count=%d next=%d (checksum %x) Status=%x",Count,next_interupt,mchecksum(),Status);
2089 //DebugMessage(M64MSG_VERBOSE, "TRACE: count=%d next=%d (checksum %x) hi=%8x%8x",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2091 #if NEW_DYNAREC == NEW_DYNAREC_X86
2092 DebugMessage(M64MSG_VERBOSE, "TRACE: %x",(&i)[-1]);
2094 #if NEW_DYNAREC == NEW_DYNAREC_ARM
2096 DebugMessage(M64MSG_VERBOSE, "TRACE: %x ",(&j)[10]);
2097 DebugMessage(M64MSG_VERBOSE, "TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2101 //DebugMessage(M64MSG_VERBOSE, "TRACE: %x",(&i)[-1]);
2106 static void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2108 DebugMessage(M64MSG_VERBOSE, "TLB Exception: instruction=%x addr=%x cause=%x",iaddr, addr, cause);
2112 static void alu_assemble(int i,struct regstat *i_regs)
2114 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2116 signed char s1,s2,t;
2117 t=get_reg(i_regs->regmap,rt1[i]);
2119 s1=get_reg(i_regs->regmap,rs1[i]);
2120 s2=get_reg(i_regs->regmap,rs2[i]);
2121 if(rs1[i]&&rs2[i]) {
2124 if(opcode2[i]&2) emit_sub(s1,s2,t);
2125 else emit_add(s1,s2,t);
2128 if(s1>=0) emit_mov(s1,t);
2129 else emit_loadreg(rs1[i],t);
2133 if(opcode2[i]&2) emit_neg(s2,t);
2134 else emit_mov(s2,t);
2137 emit_loadreg(rs2[i],t);
2138 if(opcode2[i]&2) emit_neg(t,t);
2141 else emit_zeroreg(t);
2145 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2147 signed char s1l,s2l,s1h,s2h,tl,th;
2148 tl=get_reg(i_regs->regmap,rt1[i]);
2149 th=get_reg(i_regs->regmap,rt1[i]|64);
2151 s1l=get_reg(i_regs->regmap,rs1[i]);
2152 s2l=get_reg(i_regs->regmap,rs2[i]);
2153 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2154 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2155 if(rs1[i]&&rs2[i]) {
2158 if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2159 else emit_adds(s1l,s2l,tl);
2161 #ifdef INVERTED_CARRY
2162 if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2164 if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2166 else emit_add(s1h,s2h,th);
2170 if(s1l>=0) emit_mov(s1l,tl);
2171 else emit_loadreg(rs1[i],tl);
2173 if(s1h>=0) emit_mov(s1h,th);
2174 else emit_loadreg(rs1[i]|64,th);
2179 if(opcode2[i]&2) emit_negs(s2l,tl);
2180 else emit_mov(s2l,tl);
2183 emit_loadreg(rs2[i],tl);
2184 if(opcode2[i]&2) emit_negs(tl,tl);
2187 #ifdef INVERTED_CARRY
2188 if(s2h>=0) emit_mov(s2h,th);
2189 else emit_loadreg(rs2[i]|64,th);
2191 emit_adcimm(-1,th); // x86 has inverted carry flag
2196 if(s2h>=0) emit_rscimm(s2h,0,th);
2198 emit_loadreg(rs2[i]|64,th);
2199 emit_rscimm(th,0,th);
2202 if(s2h>=0) emit_mov(s2h,th);
2203 else emit_loadreg(rs2[i]|64,th);
2210 if(th>=0) emit_zeroreg(th);
2215 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2217 signed char s1l,s1h,s2l,s2h,t;
2218 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2220 t=get_reg(i_regs->regmap,rt1[i]);
2223 s1l=get_reg(i_regs->regmap,rs1[i]);
2224 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2225 s2l=get_reg(i_regs->regmap,rs2[i]);
2226 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2227 if(rs2[i]==0) // rx<r0
2230 if(opcode2[i]==0x2a) // SLT
2231 emit_shrimm(s1h,31,t);
2232 else // SLTU (unsigned can not be less than zero)
2235 else if(rs1[i]==0) // r0<rx
2238 if(opcode2[i]==0x2a) // SLT
2239 emit_set_gz64_32(s2h,s2l,t);
2240 else // SLTU (set if not zero)
2241 emit_set_nz64_32(s2h,s2l,t);
2244 assert(s1l>=0);assert(s1h>=0);
2245 assert(s2l>=0);assert(s2h>=0);
2246 if(opcode2[i]==0x2a) // SLT
2247 emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2249 emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2253 t=get_reg(i_regs->regmap,rt1[i]);
2256 s1l=get_reg(i_regs->regmap,rs1[i]);
2257 s2l=get_reg(i_regs->regmap,rs2[i]);
2258 if(rs2[i]==0) // rx<r0
2261 if(opcode2[i]==0x2a) // SLT
2262 emit_shrimm(s1l,31,t);
2263 else // SLTU (unsigned can not be less than zero)
2266 else if(rs1[i]==0) // r0<rx
2269 if(opcode2[i]==0x2a) // SLT
2270 emit_set_gz32(s2l,t);
2271 else // SLTU (set if not zero)
2272 emit_set_nz32(s2l,t);
2275 assert(s1l>=0);assert(s2l>=0);
2276 if(opcode2[i]==0x2a) // SLT
2277 emit_set_if_less32(s1l,s2l,t);
2279 emit_set_if_carry32(s1l,s2l,t);
2285 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2287 signed char s1l,s1h,s2l,s2h,th,tl;
2288 tl=get_reg(i_regs->regmap,rt1[i]);
2289 th=get_reg(i_regs->regmap,rt1[i]|64);
2290 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2294 s1l=get_reg(i_regs->regmap,rs1[i]);
2295 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2296 s2l=get_reg(i_regs->regmap,rs2[i]);
2297 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2298 if(rs1[i]&&rs2[i]) {
2299 assert(s1l>=0);assert(s1h>=0);
2300 assert(s2l>=0);assert(s2h>=0);
2301 if(opcode2[i]==0x24) { // AND
2302 emit_and(s1l,s2l,tl);
2303 emit_and(s1h,s2h,th);
2305 if(opcode2[i]==0x25) { // OR
2306 emit_or(s1l,s2l,tl);
2307 emit_or(s1h,s2h,th);
2309 if(opcode2[i]==0x26) { // XOR
2310 emit_xor(s1l,s2l,tl);
2311 emit_xor(s1h,s2h,th);
2313 if(opcode2[i]==0x27) { // NOR
2314 emit_or(s1l,s2l,tl);
2315 emit_or(s1h,s2h,th);
2322 if(opcode2[i]==0x24) { // AND
2326 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2328 if(s1l>=0) emit_mov(s1l,tl);
2329 else emit_loadreg(rs1[i],tl);
2330 if(s1h>=0) emit_mov(s1h,th);
2331 else emit_loadreg(rs1[i]|64,th);
2335 if(s2l>=0) emit_mov(s2l,tl);
2336 else emit_loadreg(rs2[i],tl);
2337 if(s2h>=0) emit_mov(s2h,th);
2338 else emit_loadreg(rs2[i]|64,th);
2345 if(opcode2[i]==0x27) { // NOR
2347 if(s1l>=0) emit_not(s1l,tl);
2349 emit_loadreg(rs1[i],tl);
2352 if(s1h>=0) emit_not(s1h,th);
2354 emit_loadreg(rs1[i]|64,th);
2360 if(s2l>=0) emit_not(s2l,tl);
2362 emit_loadreg(rs2[i],tl);
2365 if(s2h>=0) emit_not(s2h,th);
2367 emit_loadreg(rs2[i]|64,th);
2383 s1l=get_reg(i_regs->regmap,rs1[i]);
2384 s2l=get_reg(i_regs->regmap,rs2[i]);
2385 if(rs1[i]&&rs2[i]) {
2388 if(opcode2[i]==0x24) { // AND
2389 emit_and(s1l,s2l,tl);
2391 if(opcode2[i]==0x25) { // OR
2392 emit_or(s1l,s2l,tl);
2394 if(opcode2[i]==0x26) { // XOR
2395 emit_xor(s1l,s2l,tl);
2397 if(opcode2[i]==0x27) { // NOR
2398 emit_or(s1l,s2l,tl);
2404 if(opcode2[i]==0x24) { // AND
2407 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2409 if(s1l>=0) emit_mov(s1l,tl);
2410 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2414 if(s2l>=0) emit_mov(s2l,tl);
2415 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2417 else emit_zeroreg(tl);
2419 if(opcode2[i]==0x27) { // NOR
2421 if(s1l>=0) emit_not(s1l,tl);
2423 emit_loadreg(rs1[i],tl);
2429 if(s2l>=0) emit_not(s2l,tl);
2431 emit_loadreg(rs2[i],tl);
2435 else emit_movimm(-1,tl);
2444 static void imm16_assemble(int i,struct regstat *i_regs)
2446 if (opcode[i]==0x0f) { // LUI
2449 t=get_reg(i_regs->regmap,rt1[i]);
2452 if(!((i_regs->isconst>>t)&1))
2453 emit_movimm(imm[i]<<16,t);
2457 if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2460 t=get_reg(i_regs->regmap,rt1[i]);
2461 s=get_reg(i_regs->regmap,rs1[i]);
2466 if(!((i_regs->isconst>>t)&1)) {
2468 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2469 emit_addimm(t,imm[i],t);
2471 if(!((i_regs->wasconst>>s)&1))
2472 emit_addimm(s,imm[i],t);
2474 emit_movimm(constmap[i][s]+imm[i],t);
2480 if(!((i_regs->isconst>>t)&1))
2481 emit_movimm(imm[i],t);
2486 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2488 signed char sh,sl,th,tl;
2489 th=get_reg(i_regs->regmap,rt1[i]|64);
2490 tl=get_reg(i_regs->regmap,rt1[i]);
2491 sh=get_reg(i_regs->regmap,rs1[i]|64);
2492 sl=get_reg(i_regs->regmap,rs1[i]);
2498 emit_addimm64_32(sh,sl,imm[i],th,tl);
2501 emit_addimm(sl,imm[i],tl);
2504 emit_movimm(imm[i],tl);
2505 if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2510 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2512 //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2513 signed char sh,sl,t;
2514 t=get_reg(i_regs->regmap,rt1[i]);
2515 sh=get_reg(i_regs->regmap,rs1[i]|64);
2516 sl=get_reg(i_regs->regmap,rs1[i]);
2520 if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2521 if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2522 if(opcode[i]==0x0a) { // SLTI
2524 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2525 emit_slti32(t,imm[i],t);
2527 emit_slti32(sl,imm[i],t);
2532 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2533 emit_sltiu32(t,imm[i],t);
2535 emit_sltiu32(sl,imm[i],t);
2540 if(opcode[i]==0x0a) // SLTI
2541 emit_slti64_32(sh,sl,imm[i],t);
2543 emit_sltiu64_32(sh,sl,imm[i],t);
2546 // SLTI(U) with r0 is just stupid,
2547 // nonetheless examples can be found
2548 if(opcode[i]==0x0a) // SLTI
2549 if(0<imm[i]) emit_movimm(1,t);
2550 else emit_zeroreg(t);
2553 if(imm[i]) emit_movimm(1,t);
2554 else emit_zeroreg(t);
2560 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2562 signed char sh,sl,th,tl;
2563 th=get_reg(i_regs->regmap,rt1[i]|64);
2564 tl=get_reg(i_regs->regmap,rt1[i]);
2565 sh=get_reg(i_regs->regmap,rs1[i]|64);
2566 sl=get_reg(i_regs->regmap,rs1[i]);
2567 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2568 if(opcode[i]==0x0c) //ANDI
2572 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2573 emit_andimm(tl,imm[i],tl);
2575 if(!((i_regs->wasconst>>sl)&1))
2576 emit_andimm(sl,imm[i],tl);
2578 emit_movimm(constmap[i][sl]&imm[i],tl);
2583 if(th>=0) emit_zeroreg(th);
2589 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2593 emit_loadreg(rs1[i]|64,th);
2598 if(opcode[i]==0x0d) { //ORI
2600 emit_orimm(tl,imm[i],tl);
2602 if(!((i_regs->wasconst>>sl)&1))
2603 emit_orimm(sl,imm[i],tl);
2605 emit_movimm(constmap[i][sl]|imm[i],tl);
2608 if(opcode[i]==0x0e) { //XORI
2610 emit_xorimm(tl,imm[i],tl);
2612 if(!((i_regs->wasconst>>sl)&1))
2613 emit_xorimm(sl,imm[i],tl);
2615 emit_movimm(constmap[i][sl]^imm[i],tl);
2620 emit_movimm(imm[i],tl);
2621 if(th>=0) emit_zeroreg(th);
2629 static void shiftimm_assemble(int i,struct regstat *i_regs)
2631 if(opcode2[i]<=0x3) // SLL/SRL/SRA
2635 t=get_reg(i_regs->regmap,rt1[i]);
2636 s=get_reg(i_regs->regmap,rs1[i]);
2645 if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2647 if(opcode2[i]==0) // SLL
2649 emit_shlimm(s<0?t:s,imm[i],t);
2651 if(opcode2[i]==2) // SRL
2653 emit_shrimm(s<0?t:s,imm[i],t);
2655 if(opcode2[i]==3) // SRA
2657 emit_sarimm(s<0?t:s,imm[i],t);
2661 if(s>=0 && s!=t) emit_mov(s,t);
2665 //emit_storereg(rt1[i],t); //DEBUG
2668 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2671 signed char sh,sl,th,tl;
2672 th=get_reg(i_regs->regmap,rt1[i]|64);
2673 tl=get_reg(i_regs->regmap,rt1[i]);
2674 sh=get_reg(i_regs->regmap,rs1[i]|64);
2675 sl=get_reg(i_regs->regmap,rs1[i]);
2680 if(th>=0) emit_zeroreg(th);
2687 if(opcode2[i]==0x38) // DSLL
2689 if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2690 emit_shlimm(sl,imm[i],tl);
2692 if(opcode2[i]==0x3a) // DSRL
2694 emit_shrdimm(sl,sh,imm[i],tl);
2695 if(th>=0) emit_shrimm(sh,imm[i],th);
2697 if(opcode2[i]==0x3b) // DSRA
2699 emit_shrdimm(sl,sh,imm[i],tl);
2700 if(th>=0) emit_sarimm(sh,imm[i],th);
2704 if(sl!=tl) emit_mov(sl,tl);
2705 if(th>=0&&sh!=th) emit_mov(sh,th);
2711 if(opcode2[i]==0x3c) // DSLL32
2714 signed char sl,tl,th;
2715 tl=get_reg(i_regs->regmap,rt1[i]);
2716 th=get_reg(i_regs->regmap,rt1[i]|64);
2717 sl=get_reg(i_regs->regmap,rs1[i]);
2726 emit_shlimm(th,imm[i]&31,th);
2731 if(opcode2[i]==0x3e) // DSRL32
2734 signed char sh,tl,th;
2735 tl=get_reg(i_regs->regmap,rt1[i]);
2736 th=get_reg(i_regs->regmap,rt1[i]|64);
2737 sh=get_reg(i_regs->regmap,rs1[i]|64);
2741 if(th>=0) emit_zeroreg(th);
2744 emit_shrimm(tl,imm[i]&31,tl);
2749 if(opcode2[i]==0x3f) // DSRA32
2753 tl=get_reg(i_regs->regmap,rt1[i]);
2754 sh=get_reg(i_regs->regmap,rs1[i]|64);
2760 emit_sarimm(tl,imm[i]&31,tl);
2767 #ifndef shift_assemble
2768 void shift_assemble(int i,struct regstat *i_regs)
2770 DebugMessage(M64MSG_ERROR, "Need shift_assemble for this architecture.");
2775 static void load_assemble(int i,struct regstat *i_regs)
2777 int s,th,tl,addr,map=-1,cache=-1;
2782 th=get_reg(i_regs->regmap,rt1[i]|64);
2783 tl=get_reg(i_regs->regmap,rt1[i]);
2784 s=get_reg(i_regs->regmap,rs1[i]);
2786 for(hr=0;hr<HOST_REGS;hr++) {
2787 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2789 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2791 c=(i_regs->wasconst>>s)&1;
2792 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80800000;
2793 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2795 if(tl<0) tl=get_reg(i_regs->regmap,-1);
2796 if(offset||s<0||c) addr=tl;
2798 //DebugMessage(M64MSG_VERBOSE, "load_assemble: c=%d",c);
2799 //if(c) DebugMessage(M64MSG_VERBOSE, "load_assemble: const=%x",(int)constmap[i][s]+offset);
2800 assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2802 if(th>=0) reglist&=~(1<<th);
2806 map=get_reg(i_regs->regmap,ROREG);
2807 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2809 //#define R29_HACK 1
2811 // Strmnnrmn's speed hack
2812 if(rs1[i]!=29||start<0x80001000||start>=0x80800000)
2815 emit_cmpimm(addr,0x800000);
2817 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2818 // Hint to branch predictor that the branch is unlikely to be taken
2820 emit_jno_unlikely(0);
2828 if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2829 if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2830 map=get_reg(i_regs->regmap,TLREG);
2831 cache=get_reg(i_regs->regmap,MMREG);
2834 map=do_tlb_r(addr,tl,map,cache,x,-1,-1,c,constmap[i][s]+offset);
2835 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2837 int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2838 if (opcode[i]==0x20) { // LB
2841 #ifdef HOST_IMM_ADDR32
2843 emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2847 //emit_xorimm(addr,3,tl);
2848 //gen_tlb_addr_r(tl,map);
2849 //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2851 if(!c) emit_xorimm(addr,3,tl);
2852 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2853 emit_movsbl_indexed_tlb(x,tl,map,tl);
2857 add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2860 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2862 if (opcode[i]==0x21) { // LH
2865 #ifdef HOST_IMM_ADDR32
2867 emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2872 if(!c) emit_xorimm(addr,2,tl);
2873 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2875 //emit_movswl_indexed_tlb(x,tl,map,tl);
2878 gen_tlb_addr_r(tl,map);
2879 emit_movswl_indexed(x,tl,tl);
2882 emit_movswl_indexed(x,tl,tl);
2884 emit_movswl_indexed((int)rdram-0x80000000+x,tl,tl);
2890 add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2893 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2895 if (opcode[i]==0x23) { // LW
2898 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2899 #ifdef HOST_IMM_ADDR32
2901 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2904 emit_readword_indexed_tlb(0,addr,map,tl);
2907 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2910 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2912 if (opcode[i]==0x24) { // LBU
2915 #ifdef HOST_IMM_ADDR32
2917 emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
2921 //emit_xorimm(addr,3,tl);
2922 //gen_tlb_addr_r(tl,map);
2923 //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
2925 if(!c) emit_xorimm(addr,3,tl);
2926 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2927 emit_movzbl_indexed_tlb(x,tl,map,tl);
2931 add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2934 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2936 if (opcode[i]==0x25) { // LHU
2939 #ifdef HOST_IMM_ADDR32
2941 emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
2946 if(!c) emit_xorimm(addr,2,tl);
2947 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2949 //emit_movzwl_indexed_tlb(x,tl,map,tl);
2952 gen_tlb_addr_r(tl,map);
2953 emit_movzwl_indexed(x,tl,tl);
2956 emit_movzwl_indexed(x,tl,tl);
2958 emit_movzwl_indexed((int)rdram-0x80000000+x,tl,tl);
2964 add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2967 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2969 if (opcode[i]==0x27) { // LWU
2973 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2974 #ifdef HOST_IMM_ADDR32
2976 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2979 emit_readword_indexed_tlb(0,addr,map,tl);
2982 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2985 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2989 if (opcode[i]==0x37) { // LD
2992 //gen_tlb_addr_r(tl,map);
2993 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
2994 //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
2995 #ifdef HOST_IMM_ADDR32
2997 emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3000 emit_readdword_indexed_tlb(0,addr,map,th,tl);
3003 add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3006 inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3008 //emit_storereg(rt1[i],tl); // DEBUG
3009 //if(opcode[i]==0x23)
3010 //if(opcode[i]==0x24)
3011 //if(opcode[i]==0x23||opcode[i]==0x24)
3012 /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
3016 emit_readword((int)&last_count,ECX);
3017 #if NEW_DYNAREC == NEW_DYNAREC_X86
3018 if(get_reg(i_regs->regmap,CCREG)<0)
3019 emit_loadreg(CCREG,HOST_CCREG);
3020 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3021 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3022 emit_writeword(HOST_CCREG,(int)&Count);
3024 #if NEW_DYNAREC == NEW_DYNAREC_ARM
3025 if(get_reg(i_regs->regmap,CCREG)<0)
3026 emit_loadreg(CCREG,0);
3028 emit_mov(HOST_CCREG,0);
3030 emit_addimm(0,2*ccadj[i],0);
3031 emit_writeword(0,(int)&Count);
3033 emit_call((int)memdebug);
3035 restore_regs(0x100f);
3039 #ifndef loadlr_assemble
3040 static void loadlr_assemble(int i,struct regstat *i_regs)
3042 DebugMessage(M64MSG_ERROR, "Need loadlr_assemble for this architecture.");
3047 static void store_assemble(int i,struct regstat *i_regs)
3049 int s,th,tl,map=-1,cache=-1;
3052 int jaddr=0,jaddr2,type;
3054 int agr=AGEN1+(i&1);
3056 th=get_reg(i_regs->regmap,rs2[i]|64);
3057 tl=get_reg(i_regs->regmap,rs2[i]);
3058 s=get_reg(i_regs->regmap,rs1[i]);
3059 temp=get_reg(i_regs->regmap,agr);
3060 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3063 c=(i_regs->wasconst>>s)&1;
3064 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80800000;
3065 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3069 for(hr=0;hr<HOST_REGS;hr++) {
3070 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3072 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3073 if(offset||s<0||c) addr=temp;
3077 map=get_reg(i_regs->regmap,ROREG);
3078 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3082 // Strmnnrmn's speed hack
3084 if(rs1[i]!=29||start<0x80001000||start>=0x80800000)
3086 emit_cmpimm(addr,0x800000);
3087 #ifdef DESTRUCTIVE_SHIFT
3088 if(s==addr) emit_mov(s,temp);
3091 if(rs1[i]!=29||start<0x80001000||start>=0x80800000)
3095 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3096 // Hint to branch predictor that the branch is unlikely to be taken
3098 emit_jno_unlikely(0);
3106 if (opcode[i]==0x28) x=3; // SB
3107 if (opcode[i]==0x29) x=2; // SH
3108 map=get_reg(i_regs->regmap,TLREG);
3109 cache=get_reg(i_regs->regmap,MMREG);
3112 map=do_tlb_w(addr,temp,map,cache,x,c,constmap[i][s]+offset);
3113 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3116 if (opcode[i]==0x28) { // SB
3119 if(!c) emit_xorimm(addr,3,temp);
3120 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3121 //gen_tlb_addr_w(temp,map);
3122 //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3123 emit_writebyte_indexed_tlb(tl,x,temp,map,temp);
3127 if (opcode[i]==0x29) { // SH
3130 if(!c) emit_xorimm(addr,2,temp);
3131 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3133 //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3136 gen_tlb_addr_w(temp,map);
3137 emit_writehword_indexed(tl,x,temp);
3139 emit_writehword_indexed(tl,(int)rdram-0x80000000+x,temp);
3143 if (opcode[i]==0x2B) { // SW
3145 //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3146 emit_writeword_indexed_tlb(tl,0,addr,map,temp);
3149 if (opcode[i]==0x3F) { // SD
3153 //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3154 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3155 emit_writedword_indexed_tlb(th,tl,0,addr,map,temp);
3158 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3159 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3160 emit_writedword_indexed_tlb(tl,tl,0,addr,map,temp);
3167 #ifdef DESTRUCTIVE_SHIFT
3168 // The x86 shift operation is 'destructive'; it overwrites the
3169 // source register, so we need to make a copy first and use that.
3172 #if defined(HOST_IMM8)
3173 int ir=get_reg(i_regs->regmap,INVCP);
3175 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3177 emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3179 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3180 emit_callne(invalidate_addr_reg[addr]);
3184 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3189 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3190 } else if(c&&!memtarget) {
3191 inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3193 //if(opcode[i]==0x2B || opcode[i]==0x3F)
3194 //if(opcode[i]==0x2B || opcode[i]==0x28)
3195 //if(opcode[i]==0x2B || opcode[i]==0x29)
3196 //if(opcode[i]==0x2B)
3198 // Uncomment for extra debug output:
3200 if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3202 #if NEW_DYNAREC == NEW_DYNAREC_X86
3205 #if NEW_DYNAREC == NEW_DYNAREC_ARM
3208 emit_readword((int)&last_count,ECX);
3209 #if NEW_DYNAREC == NEW_DYNAREC_X86
3210 if(get_reg(i_regs->regmap,CCREG)<0)
3211 emit_loadreg(CCREG,HOST_CCREG);
3212 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3213 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3214 emit_writeword(HOST_CCREG,(int)&Count);
3216 #if NEW_DYNAREC == NEW_DYNAREC_ARM
3217 if(get_reg(i_regs->regmap,CCREG)<0)
3218 emit_loadreg(CCREG,0);
3220 emit_mov(HOST_CCREG,0);
3222 emit_addimm(0,2*ccadj[i],0);
3223 emit_writeword(0,(int)&Count);
3225 emit_call((int)memdebug);
3226 #if NEW_DYNAREC == NEW_DYNAREC_X86
3229 #if NEW_DYNAREC == NEW_DYNAREC_ARM
3230 restore_regs(0x100f);
3236 static void storelr_assemble(int i,struct regstat *i_regs)
3243 int case1,case2,case3;
3244 int done0,done1,done2;
3246 int agr=AGEN1+(i&1);
3248 th=get_reg(i_regs->regmap,rs2[i]|64);
3249 tl=get_reg(i_regs->regmap,rs2[i]);
3250 s=get_reg(i_regs->regmap,rs1[i]);
3251 temp=get_reg(i_regs->regmap,agr);
3252 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3255 c=(i_regs->isconst>>s)&1;
3256 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80800000;
3257 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3260 for(hr=0;hr<HOST_REGS;hr++) {
3261 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3266 emit_cmpimm(s<0||offset?temp:s,0x800000);
3267 if(!offset&&s!=temp) emit_mov(s,temp);
3273 if(!memtarget||!rs1[i]) {
3279 int map=get_reg(i_regs->regmap,ROREG);
3280 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3281 gen_tlb_addr_w(temp,map);
3283 if((u_int)rdram!=0x80000000)
3284 emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3287 int map=get_reg(i_regs->regmap,TLREG);
3288 int cache=get_reg(i_regs->regmap,MMREG);
3291 map=do_tlb_w(c||s<0||offset?temp:s,temp,map,cache,0,c,constmap[i][s]+offset);
3292 if(!c&&!offset&&s>=0) emit_mov(s,temp);
3293 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3294 if(!jaddr&&!memtarget) {
3298 gen_tlb_addr_w(temp,map);
3301 if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3302 temp2=get_reg(i_regs->regmap,FTEMP);
3303 if(!rs2[i]) temp2=th=tl;
3306 emit_testimm(temp,2);
3309 emit_testimm(temp,1);
3313 if (opcode[i]==0x2A) { // SWL
3314 emit_writeword_indexed(tl,0,temp);
3316 if (opcode[i]==0x2E) { // SWR
3317 emit_writebyte_indexed(tl,3,temp);
3319 if (opcode[i]==0x2C) { // SDL
3320 emit_writeword_indexed(th,0,temp);
3321 if(rs2[i]) emit_mov(tl,temp2);
3323 if (opcode[i]==0x2D) { // SDR
3324 emit_writebyte_indexed(tl,3,temp);
3325 if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3330 set_jump_target(case1,(int)out);
3331 if (opcode[i]==0x2A) { // SWL
3332 // Write 3 msb into three least significant bytes
3333 if(rs2[i]) emit_rorimm(tl,8,tl);
3334 emit_writehword_indexed(tl,-1,temp);
3335 if(rs2[i]) emit_rorimm(tl,16,tl);
3336 emit_writebyte_indexed(tl,1,temp);
3337 if(rs2[i]) emit_rorimm(tl,8,tl);
3339 if (opcode[i]==0x2E) { // SWR
3340 // Write two lsb into two most significant bytes
3341 emit_writehword_indexed(tl,1,temp);
3343 if (opcode[i]==0x2C) { // SDL
3344 if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3345 // Write 3 msb into three least significant bytes
3346 if(rs2[i]) emit_rorimm(th,8,th);
3347 emit_writehword_indexed(th,-1,temp);
3348 if(rs2[i]) emit_rorimm(th,16,th);
3349 emit_writebyte_indexed(th,1,temp);
3350 if(rs2[i]) emit_rorimm(th,8,th);
3352 if (opcode[i]==0x2D) { // SDR
3353 if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3354 // Write two lsb into two most significant bytes
3355 emit_writehword_indexed(tl,1,temp);
3360 set_jump_target(case2,(int)out);
3361 emit_testimm(temp,1);
3364 if (opcode[i]==0x2A) { // SWL
3365 // Write two msb into two least significant bytes
3366 if(rs2[i]) emit_rorimm(tl,16,tl);
3367 emit_writehword_indexed(tl,-2,temp);
3368 if(rs2[i]) emit_rorimm(tl,16,tl);
3370 if (opcode[i]==0x2E) { // SWR
3371 // Write 3 lsb into three most significant bytes
3372 emit_writebyte_indexed(tl,-1,temp);
3373 if(rs2[i]) emit_rorimm(tl,8,tl);
3374 emit_writehword_indexed(tl,0,temp);
3375 if(rs2[i]) emit_rorimm(tl,24,tl);
3377 if (opcode[i]==0x2C) { // SDL
3378 if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3379 // Write two msb into two least significant bytes
3380 if(rs2[i]) emit_rorimm(th,16,th);
3381 emit_writehword_indexed(th,-2,temp);
3382 if(rs2[i]) emit_rorimm(th,16,th);
3384 if (opcode[i]==0x2D) { // SDR
3385 if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3386 // Write 3 lsb into three most significant bytes
3387 emit_writebyte_indexed(tl,-1,temp);
3388 if(rs2[i]) emit_rorimm(tl,8,tl);
3389 emit_writehword_indexed(tl,0,temp);
3390 if(rs2[i]) emit_rorimm(tl,24,tl);
3395 set_jump_target(case3,(int)out);
3396 if (opcode[i]==0x2A) { // SWL
3397 // Write msb into least significant byte
3398 if(rs2[i]) emit_rorimm(tl,24,tl);
3399 emit_writebyte_indexed(tl,-3,temp);
3400 if(rs2[i]) emit_rorimm(tl,8,tl);
3402 if (opcode[i]==0x2E) { // SWR
3403 // Write entire word
3404 emit_writeword_indexed(tl,-3,temp);
3406 if (opcode[i]==0x2C) { // SDL
3407 if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3408 // Write msb into least significant byte
3409 if(rs2[i]) emit_rorimm(th,24,th);
3410 emit_writebyte_indexed(th,-3,temp);
3411 if(rs2[i]) emit_rorimm(th,8,th);
3413 if (opcode[i]==0x2D) { // SDR
3414 if(rs2[i]) emit_mov(th,temp2);
3415 // Write entire word
3416 emit_writeword_indexed(tl,-3,temp);
3418 set_jump_target(done0,(int)out);
3419 set_jump_target(done1,(int)out);
3420 set_jump_target(done2,(int)out);
3421 if (opcode[i]==0x2C) { // SDL
3422 emit_testimm(temp,4);
3425 emit_andimm(temp,~3,temp);
3426 emit_writeword_indexed(temp2,4,temp);
3427 set_jump_target(done0,(int)out);
3429 if (opcode[i]==0x2D) { // SDR
3430 emit_testimm(temp,4);
3433 emit_andimm(temp,~3,temp);
3434 emit_writeword_indexed(temp2,-4,temp);
3435 set_jump_target(done0,(int)out);
3438 add_stub(STORELR_STUB,jaddr,(int)out,0,(int)i_regs,rs2[i],ccadj[i],reglist);
3441 int map=get_reg(i_regs->regmap,ROREG);
3442 if(map<0) map=HOST_TEMPREG;
3443 gen_orig_addr_w(temp,map);
3445 emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
3447 #if defined(HOST_IMM8)
3448 int ir=get_reg(i_regs->regmap,INVCP);
3450 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3452 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3454 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3455 emit_callne(invalidate_addr_reg[temp]);
3459 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3464 //save_regs(0x100f);
3465 emit_readword((int)&last_count,ECX);
3466 if(get_reg(i_regs->regmap,CCREG)<0)
3467 emit_loadreg(CCREG,HOST_CCREG);
3468 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3469 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3470 emit_writeword(HOST_CCREG,(int)&Count);
3471 emit_call((int)memdebug);
3473 //restore_regs(0x100f);
3477 static void c1ls_assemble(int i,struct regstat *i_regs)
3484 int jaddr,jaddr2=0,jaddr3,type;
3485 int agr=AGEN1+(i&1);
3487 th=get_reg(i_regs->regmap,FTEMP|64);
3488 tl=get_reg(i_regs->regmap,FTEMP);
3489 s=get_reg(i_regs->regmap,rs1[i]);
3490 temp=get_reg(i_regs->regmap,agr);
3491 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3496 for(hr=0;hr<HOST_REGS;hr++) {
3497 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3499 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3500 if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3502 // Loads use a temporary register which we need to save
3505 if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3509 //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3510 //else c=(i_regs->wasconst>>s)&1;
3511 if(s>=0) c=(i_regs->wasconst>>s)&1;
3512 // Check cop1 unusable
3514 signed char rs=get_reg(i_regs->regmap,CSREG);
3516 emit_testimm(rs,0x20000000);
3519 add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3522 if (opcode[i]==0x39) { // SWC1 (get float address)
3523 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],tl);
3525 if (opcode[i]==0x3D) { // SDC1 (get double address)
3526 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],tl);
3528 // Generate address + offset
3531 if (!c||opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3533 map=get_reg(i_regs->regmap,ROREG);
3534 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3538 emit_cmpimm(offset||c||s<0?ar:s,0x800000);
3542 map=get_reg(i_regs->regmap,TLREG);
3543 int cache=get_reg(i_regs->regmap,MMREG);
3546 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3547 map=do_tlb_r(offset||c||s<0?ar:s,ar,map,cache,0,-1,-1,c,constmap[i][s]+offset);
3549 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3550 map=do_tlb_w(offset||c||s<0?ar:s,ar,map,cache,0,c,constmap[i][s]+offset);
3553 if (opcode[i]==0x39) { // SWC1 (read float)
3554 emit_readword_indexed(0,tl,tl);
3556 if (opcode[i]==0x3D) { // SDC1 (read double)
3557 emit_readword_indexed(4,tl,th);
3558 emit_readword_indexed(0,tl,tl);
3560 if (opcode[i]==0x31) { // LWC1 (get target address)
3561 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],temp);
3563 if (opcode[i]==0x35) { // LDC1 (get target address)
3564 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],temp);
3571 else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80800000) {
3573 emit_jmp(0); // inline_readstub/inline_writestub? Very rare case
3575 #ifdef DESTRUCTIVE_SHIFT
3576 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3577 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3581 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3582 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3584 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3585 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3588 if (opcode[i]==0x31) { // LWC1
3589 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3590 //gen_tlb_addr_r(ar,map);
3591 //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3592 #ifdef HOST_IMM_ADDR32
3593 if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3596 emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3599 if (opcode[i]==0x35) { // LDC1
3601 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3602 //gen_tlb_addr_r(ar,map);
3603 //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3604 //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3605 #ifdef HOST_IMM_ADDR32
3606 if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3609 emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3612 if (opcode[i]==0x39) { // SWC1
3613 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3614 emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3617 if (opcode[i]==0x3D) { // SDC1
3619 //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3620 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3621 emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3625 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3626 #ifndef DESTRUCTIVE_SHIFT
3627 temp=offset||c||s<0?ar:s;
3629 #if defined(HOST_IMM8)
3630 int ir=get_reg(i_regs->regmap,INVCP);
3632 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3634 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3636 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3637 emit_callne(invalidate_addr_reg[temp]);
3641 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3645 if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3646 if (opcode[i]==0x31) { // LWC1 (write float)
3647 emit_writeword_indexed(tl,0,temp);
3649 if (opcode[i]==0x35) { // LDC1 (write double)
3650 emit_writeword_indexed(th,4,temp);
3651 emit_writeword_indexed(tl,0,temp);
3653 //if(opcode[i]==0x39)
3654 /*if(opcode[i]==0x39||opcode[i]==0x31)
3657 emit_readword((int)&last_count,ECX);
3658 if(get_reg(i_regs->regmap,CCREG)<0)
3659 emit_loadreg(CCREG,HOST_CCREG);
3660 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3661 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3662 emit_writeword(HOST_CCREG,(int)&Count);
3663 emit_call((int)memdebug);
3668 #ifndef multdiv_assemble
3669 void multdiv_assemble(int i,struct regstat *i_regs)
3671 DebugMessage(M64MSG_ERROR, "Need multdiv_assemble for this architecture.");
3676 static void mov_assemble(int i,struct regstat *i_regs)
3678 //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3679 //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
3681 signed char sh,sl,th,tl;
3682 th=get_reg(i_regs->regmap,rt1[i]|64);
3683 tl=get_reg(i_regs->regmap,rt1[i]);
3686 sh=get_reg(i_regs->regmap,rs1[i]|64);
3687 sl=get_reg(i_regs->regmap,rs1[i]);
3688 if(sl>=0) emit_mov(sl,tl);
3689 else emit_loadreg(rs1[i],tl);
3691 if(sh>=0) emit_mov(sh,th);
3692 else emit_loadreg(rs1[i]|64,th);
3698 #ifndef fconv_assemble
3699 void fconv_assemble(int i,struct regstat *i_regs)
3701 DebugMessage(M64MSG_ERROR, "Need fconv_assemble for this architecture.");
3707 static void float_assemble(int i,struct regstat *i_regs)
3709 DebugMessage(M64MSG_ERROR, "Need float_assemble for this architecture.");
3714 static void syscall_assemble(int i,struct regstat *i_regs)
3716 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3717 assert(ccreg==HOST_CCREG);
3718 assert(!is_delayslot);
3719 emit_movimm(start+i*4,EAX); // Get PC
3720 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
3721 emit_jmp((int)jump_syscall);
3724 static void ds_assemble(int i,struct regstat *i_regs)
3729 alu_assemble(i,i_regs);break;
3731 imm16_assemble(i,i_regs);break;
3733 shift_assemble(i,i_regs);break;
3735 shiftimm_assemble(i,i_regs);break;
3737 load_assemble(i,i_regs);break;
3739 loadlr_assemble(i,i_regs);break;
3741 store_assemble(i,i_regs);break;
3743 storelr_assemble(i,i_regs);break;
3745 cop0_assemble(i,i_regs);break;
3747 cop1_assemble(i,i_regs);break;
3749 c1ls_assemble(i,i_regs);break;
3751 fconv_assemble(i,i_regs);break;
3753 float_assemble(i,i_regs);break;
3755 fcomp_assemble(i,i_regs);break;
3757 multdiv_assemble(i,i_regs);break;
3759 mov_assemble(i,i_regs);break;
3767 DebugMessage(M64MSG_VERBOSE, "Jump in the delay slot. This is probably a bug.");
3772 // Is the branch target a valid internal jump?
3773 static int internal_branch(uint64_t i_is32,int addr)
3775 if(addr&1) return 0; // Indirect (register) jump
3776 if(addr>=start && addr<start+slen*4-4)
3778 int t=(addr-start)>>2;
3779 // Delay slots are not valid branch targets
3780 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
3781 // 64 -> 32 bit transition requires a recompile
3782 /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
3784 if(requires_32bit[t]&~i_is32) DebugMessage(M64MSG_VERBOSE, "optimizable: no");
3785 else DebugMessage(M64MSG_VERBOSE, "optimizable: yes");
3787 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
3788 if(requires_32bit[t]&~i_is32) return 0;
3794 #ifndef wb_invalidate
3795 static void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
3796 uint64_t u,uint64_t uu)
3799 for(hr=0;hr<HOST_REGS;hr++) {
3800 if(hr!=EXCLUDE_REG) {
3801 if(pre[hr]!=entry[hr]) {
3804 if(get_reg(entry,pre[hr])<0) {
3806 if(!((u>>pre[hr])&1)) {
3807 emit_storereg(pre[hr],hr);
3808 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
3809 emit_sarimm(hr,31,hr);
3810 emit_storereg(pre[hr]|64,hr);
3814 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
3815 emit_storereg(pre[hr],hr);
3824 // Move from one register to another (no writeback)
3825 for(hr=0;hr<HOST_REGS;hr++) {
3826 if(hr!=EXCLUDE_REG) {
3827 if(pre[hr]!=entry[hr]) {
3828 if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
3830 if((nr=get_reg(entry,pre[hr]))>=0) {
3840 // Load the specified registers
3841 // This only loads the registers given as arguments because
3842 // we don't want to load things that will be overwritten
3843 static void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
3847 for(hr=0;hr<HOST_REGS;hr++) {
3848 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
3849 if(entry[hr]!=regmap[hr]) {
3850 if(regmap[hr]==rs1||regmap[hr]==rs2)
3857 emit_loadreg(regmap[hr],hr);
3864 for(hr=0;hr<HOST_REGS;hr++) {
3865 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
3866 if(entry[hr]!=regmap[hr]) {
3867 if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
3869 assert(regmap[hr]!=64);
3870 if((is32>>(regmap[hr]&63))&1) {
3871 int lr=get_reg(regmap,regmap[hr]-64);
3873 emit_sarimm(lr,31,hr);
3875 emit_loadreg(regmap[hr],hr);
3879 emit_loadreg(regmap[hr],hr);
3887 // Load registers prior to the start of a loop
3888 // so that they are not loaded within the loop
3889 static void loop_preload(signed char pre[],signed char entry[])
3892 for(hr=0;hr<HOST_REGS;hr++) {
3893 if(hr!=EXCLUDE_REG) {
3894 if(pre[hr]!=entry[hr]) {
3896 if(get_reg(pre,entry[hr])<0) {
3897 assem_debug("loop preload:");
3898 //DebugMessage(M64MSG_VERBOSE, "loop preload: %d",hr);
3902 else if(entry[hr]<TEMPREG)
3904 emit_loadreg(entry[hr],hr);
3906 else if(entry[hr]-64<TEMPREG)
3908 emit_loadreg(entry[hr],hr);
3917 // Generate address for load/store instruction
3918 static void address_generation(int i,struct regstat *i_regs,signed char entry[])
3920 if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS) {
3922 int agr=AGEN1+(i&1);
3923 int mgr=MGEN1+(i&1);
3924 if(itype[i]==LOAD) {
3925 ra=get_reg(i_regs->regmap,rt1[i]);
3926 if(ra<0) ra=get_reg(i_regs->regmap,-1);
3929 if(itype[i]==LOADLR) {
3930 ra=get_reg(i_regs->regmap,FTEMP);
3932 if(itype[i]==STORE||itype[i]==STORELR) {
3933 ra=get_reg(i_regs->regmap,agr);
3934 if(ra<0) ra=get_reg(i_regs->regmap,-1);
3936 if(itype[i]==C1LS) {
3937 if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3938 ra=get_reg(i_regs->regmap,FTEMP);
3940 ra=get_reg(i_regs->regmap,agr);
3941 if(ra<0) ra=get_reg(i_regs->regmap,-1);
3944 int rs=get_reg(i_regs->regmap,rs1[i]);
3945 int rm=get_reg(i_regs->regmap,TLREG);
3948 int c=(i_regs->wasconst>>rs)&1;
3950 // Using r0 as a base address
3952 if(!entry||entry[rm]!=mgr) {
3953 generate_map_const(offset,rm);
3954 } // else did it in the previous cycle
3956 if(!entry||entry[ra]!=agr) {
3957 if (opcode[i]==0x22||opcode[i]==0x26) {
3958 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
3959 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
3960 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
3962 emit_movimm(offset,ra);
3964 } // else did it in the previous cycle
3967 if(!entry||entry[ra]!=rs1[i])
3968 emit_loadreg(rs1[i],ra);
3969 //if(!entry||entry[ra]!=rs1[i])
3970 // DebugMessage(M64MSG_VERBOSE, "poor load scheduling!");
3974 if(!entry||entry[rm]!=mgr) {
3975 if(itype[i]==STORE||itype[i]==STORELR||opcode[i]==0x39||opcode[i]==0x3D) {
3976 // Stores to memory go thru the mapper to detect self-modifying
3977 // code, loads don't.
3978 if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
3979 (unsigned int)(constmap[i][rs]+offset)<0x80800000 )
3980 generate_map_const(constmap[i][rs]+offset,rm);
3982 if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
3983 generate_map_const(constmap[i][rs]+offset,rm);
3987 if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
3988 if(!entry||entry[ra]!=agr) {
3989 if (opcode[i]==0x22||opcode[i]==0x26) { // LWL/LWR
3991 if((signed int)constmap[i][rs]+offset<(signed int)0x80800000)
3992 emit_movimm(((constmap[i][rs]+offset)&0xFFFFFFFC)+(int)rdram-0x80000000,ra);
3995 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra);
3996 }else if (opcode[i]==0x1a||opcode[i]==0x1b) { // LDL/LDR
3998 if((signed int)constmap[i][rs]+offset<(signed int)0x80800000)
3999 emit_movimm(((constmap[i][rs]+offset)&0xFFFFFFF8)+(int)rdram-0x80000000,ra);
4002 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra);
4004 #ifdef HOST_IMM_ADDR32
4005 if((itype[i]!=LOAD&&opcode[i]!=0x31&&opcode[i]!=0x35) ||
4006 (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
4009 if((itype[i]==LOAD||opcode[i]==0x31||opcode[i]==0x35)&&(signed int)constmap[i][rs]+offset<(signed int)0x80800000)
4010 emit_movimm(constmap[i][rs]+offset+(int)rdram-0x80000000,ra);
4013 emit_movimm(constmap[i][rs]+offset,ra);
4015 } // else did it in the previous cycle
4016 } // else load_consts already did it
4018 if(offset&&!c&&rs1[i]) {
4020 emit_addimm(rs,offset,ra);
4022 emit_addimm(ra,offset,ra);
4027 // Preload constants for next instruction
4028 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS) {
4030 #ifndef HOST_IMM_ADDR32
4032 agr=MGEN1+((i+1)&1);
4033 ra=get_reg(i_regs->regmap,agr);
4035 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4036 int offset=imm[i+1];
4037 int c=(regs[i+1].wasconst>>rs)&1;
4039 if(itype[i+1]==STORE||itype[i+1]==STORELR||opcode[i+1]==0x39||opcode[i+1]==0x3D) {
4040 // Stores to memory go thru the mapper to detect self-modifying
4041 // code, loads don't.
4042 if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
4043 (unsigned int)(constmap[i+1][rs]+offset)<0x80800000 )
4044 generate_map_const(constmap[i+1][rs]+offset,ra);
4046 if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
4047 generate_map_const(constmap[i+1][rs]+offset,ra);
4050 /*else if(rs1[i]==0) {
4051 generate_map_const(offset,ra);
4056 agr=AGEN1+((i+1)&1);
4057 ra=get_reg(i_regs->regmap,agr);
4059 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4060 int offset=imm[i+1];
4061 int c=(regs[i+1].wasconst>>rs)&1;
4062 if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
4063 if (opcode[i+1]==0x22||opcode[i+1]==0x26) { // LWL/LWR
4065 if((signed int)constmap[i+1][rs]+offset<(signed int)0x80800000)
4066 emit_movimm(((constmap[i+1][rs]+offset)&0xFFFFFFFC)+(int)rdram-0x80000000,ra);
4069 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra);
4070 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) { // LDL/LDR
4072 if((signed int)constmap[i+1][rs]+offset<(signed int)0x80800000)
4073 emit_movimm(((constmap[i+1][rs]+offset)&0xFFFFFFF8)+(int)rdram-0x80000000,ra);
4076 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra);
4078 #ifdef HOST_IMM_ADDR32
4079 if((itype[i+1]!=LOAD&&opcode[i+1]!=0x31&&opcode[i+1]!=0x35) ||
4080 (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000))
4083 if((itype[i+1]==LOAD||opcode[i+1]==0x31||opcode[i+1]==0x35)&&(signed int)constmap[i+1][rs]+offset<(signed int)0x80800000)
4084 emit_movimm(constmap[i+1][rs]+offset+(int)rdram-0x80000000,ra);
4087 emit_movimm(constmap[i+1][rs]+offset,ra);
4090 else if(rs1[i+1]==0) {
4091 // Using r0 as a base address
4092 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4093 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4094 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4095 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4097 emit_movimm(offset,ra);
4104 static int get_final_value(int hr, int i, int *value)
4106 int reg=regs[i].regmap[hr];
4108 if(regs[i+1].regmap[hr]!=reg) break;
4109 if(!((regs[i+1].isconst>>hr)&1)) break;
4114 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
4115 *value=constmap[i][hr];
4119 if(itype[i+1]==UJUMP||itype[i+1]==RJUMP||itype[i+1]==CJUMP||itype[i+1]==SJUMP) {
4120 // Load in delay slot, out-of-order execution
4121 if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
4123 #ifdef HOST_IMM_ADDR32
4124 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+2])<(signed int)0xC0000000) return 0;
4127 if((signed int)constmap[i][hr]+imm[i+2]<(signed int)0x80800000)
4128 *value=constmap[i][hr]+imm[i+2]+(int)rdram-0x80000000;
4131 // Precompute load address
4132 *value=constmap[i][hr]+imm[i+2];
4136 if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)
4138 #ifdef HOST_IMM_ADDR32
4139 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+1])<(signed int)0xC0000000) return 0;
4142 if((signed int)constmap[i][hr]+imm[i+1]<(signed int)0x80800000)
4143 *value=constmap[i][hr]+imm[i+1]+(int)rdram-0x80000000;
4146 // Precompute load address
4147 *value=constmap[i][hr]+imm[i+1];
4148 //DebugMessage(M64MSG_VERBOSE, "c=%x imm=%x",(int)constmap[i][hr],imm[i+1]);
4153 *value=constmap[i][hr];
4154 //DebugMessage(M64MSG_VERBOSE, "c=%x",(int)constmap[i][hr]);
4155 if(i==slen-1) return 1;
4157 return !((unneeded_reg[i+1]>>reg)&1);
4159 return !((unneeded_reg_upper[i+1]>>reg)&1);
4163 // Load registers with known constants
4164 static void load_consts(signed char pre[],signed char regmap[],int is32,int i)
4168 for(hr=0;hr<HOST_REGS;hr++) {
4169 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4170 //if(entry[hr]!=regmap[hr]) {
4171 if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4172 if(((regs[i].isconst>>hr)&1)&®map[hr]<64&®map[hr]>0) {
4174 if(get_final_value(hr,i,&value)) {
4179 emit_movimm(value,hr);
4187 for(hr=0;hr<HOST_REGS;hr++) {
4188 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4189 //if(entry[hr]!=regmap[hr]) {
4190 if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4191 if(((regs[i].isconst>>hr)&1)&®map[hr]>64) {
4192 if((is32>>(regmap[hr]&63))&1) {
4193 int lr=get_reg(regmap,regmap[hr]-64);
4195 emit_sarimm(lr,31,hr);
4200 if(get_final_value(hr,i,&value)) {
4205 emit_movimm(value,hr);
4214 static void load_all_consts(signed char regmap[],int is32,u_int dirty,int i)
4218 for(hr=0;hr<HOST_REGS;hr++) {
4219 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) {
4220 if(((regs[i].isconst>>hr)&1)&®map[hr]<64&®map[hr]>0) {
4221 int value=constmap[i][hr];
4226 emit_movimm(value,hr);
4232 for(hr=0;hr<HOST_REGS;hr++) {
4233 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) {
4234 if(((regs[i].isconst>>hr)&1)&®map[hr]>64) {
4235 if((is32>>(regmap[hr]&63))&1) {
4236 int lr=get_reg(regmap,regmap[hr]-64);
4238 emit_sarimm(lr,31,hr);
4242 int value=constmap[i][hr];
4247 emit_movimm(value,hr);
4255 // Write out all dirty registers (except cycle count)
4256 static void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty)
4259 for(hr=0;hr<HOST_REGS;hr++) {
4260 if(hr!=EXCLUDE_REG) {
4261 if(i_regmap[hr]>0) {
4262 if(i_regmap[hr]!=CCREG) {
4263 if((i_dirty>>hr)&1) {
4264 if(i_regmap[hr]<64) {
4265 emit_storereg(i_regmap[hr],hr);
4266 if( ((i_is32>>i_regmap[hr])&1) ) {
4267 #ifdef DESTRUCTIVE_WRITEBACK
4268 emit_sarimm(hr,31,hr);
4269 emit_storereg(i_regmap[hr]|64,hr);
4271 emit_sarimm(hr,31,HOST_TEMPREG);
4272 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4276 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4277 emit_storereg(i_regmap[hr],hr);
4286 // Write out dirty registers that we need to reload (pair with load_needed_regs)
4287 // This writes the registers not written by store_regs_bt
4288 static void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4291 int t=(addr-start)>>2;
4292 for(hr=0;hr<HOST_REGS;hr++) {
4293 if(hr!=EXCLUDE_REG) {
4294 if(i_regmap[hr]>0) {
4295 if(i_regmap[hr]!=CCREG) {
4296 if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1) && !(((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4297 if((i_dirty>>hr)&1) {
4298 if(i_regmap[hr]<64) {
4299 emit_storereg(i_regmap[hr],hr);
4300 if( ((i_is32>>i_regmap[hr])&1) ) {
4301 #ifdef DESTRUCTIVE_WRITEBACK
4302 emit_sarimm(hr,31,hr);
4303 emit_storereg(i_regmap[hr]|64,hr);
4305 emit_sarimm(hr,31,HOST_TEMPREG);
4306 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4310 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4311 emit_storereg(i_regmap[hr],hr);
4322 // Load all registers (except cycle count)
4323 static void load_all_regs(signed char i_regmap[])
4326 for(hr=0;hr<HOST_REGS;hr++) {
4327 if(hr!=EXCLUDE_REG) {
4328 if(i_regmap[hr]==0) {
4332 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4334 emit_loadreg(i_regmap[hr],hr);
4340 // Load all current registers also needed by next instruction
4341 static void load_needed_regs(signed char i_regmap[],signed char next_regmap[])
4344 for(hr=0;hr<HOST_REGS;hr++) {
4345 if(hr!=EXCLUDE_REG) {
4346 if(get_reg(next_regmap,i_regmap[hr])>=0) {
4347 if(i_regmap[hr]==0) {
4351 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4353 emit_loadreg(i_regmap[hr],hr);
4360 // Load all regs, storing cycle count if necessary
4361 static void load_regs_entry(int t)
4364 if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER,HOST_CCREG);
4365 else if(ccadj[t]) emit_addimm(HOST_CCREG,-ccadj[t]*CLOCK_DIVIDER,HOST_CCREG);
4366 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4367 emit_storereg(CCREG,HOST_CCREG);
4370 for(hr=0;hr<HOST_REGS;hr++) {
4371 if(regs[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) {
4372 if(regs[t].regmap_entry[hr]==0) {
4375 else if(regs[t].regmap_entry[hr]!=CCREG)
4377 emit_loadreg(regs[t].regmap_entry[hr],hr);
4382 for(hr=0;hr<HOST_REGS;hr++) {
4383 if(regs[t].regmap_entry[hr]>=64&®s[t].regmap_entry[hr]<TEMPREG+64) {
4384 assert(regs[t].regmap_entry[hr]!=64);
4385 if((regs[t].was32>>(regs[t].regmap_entry[hr]&63))&1) {
4386 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4388 emit_loadreg(regs[t].regmap_entry[hr],hr);
4392 emit_sarimm(lr,31,hr);
4397 emit_loadreg(regs[t].regmap_entry[hr],hr);
4403 // Store dirty registers prior to branch
4404 static void store_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4406 if(internal_branch(i_is32,addr))
4408 int t=(addr-start)>>2;
4410 for(hr=0;hr<HOST_REGS;hr++) {
4411 if(hr!=EXCLUDE_REG) {
4412 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4413 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4414 if((i_dirty>>hr)&1) {
4415 if(i_regmap[hr]<64) {
4416 if(!((unneeded_reg[t]>>i_regmap[hr])&1)) {
4417 emit_storereg(i_regmap[hr],hr);
4418 if( ((i_is32>>i_regmap[hr])&1) && !((unneeded_reg_upper[t]>>i_regmap[hr])&1) ) {
4419 #ifdef DESTRUCTIVE_WRITEBACK
4420 emit_sarimm(hr,31,hr);
4421 emit_storereg(i_regmap[hr]|64,hr);
4423 emit_sarimm(hr,31,HOST_TEMPREG);
4424 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4429 if( !((i_is32>>(i_regmap[hr]&63))&1) && !((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1) ) {
4430 emit_storereg(i_regmap[hr],hr);
4441 // Branch out of this block, write out all dirty regs
4442 wb_dirtys(i_regmap,i_is32,i_dirty);
4446 // Load all needed registers for branch target
4447 static void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4449 //if(addr>=start && addr<(start+slen*4))
4450 if(internal_branch(i_is32,addr))
4452 int t=(addr-start)>>2;
4454 // Store the cycle count before loading something else
4455 if(i_regmap[HOST_CCREG]!=CCREG) {
4456 assert(i_regmap[HOST_CCREG]==-1);
4458 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4459 emit_storereg(CCREG,HOST_CCREG);
4462 for(hr=0;hr<HOST_REGS;hr++) {
4463 if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) {
4464 #ifdef DESTRUCTIVE_WRITEBACK
4465 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || ( !((regs[t].dirty>>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4467 if(i_regmap[hr]!=regs[t].regmap_entry[hr] ) {
4469 if(regs[t].regmap_entry[hr]==0) {
4472 else if(regs[t].regmap_entry[hr]!=CCREG)
4474 emit_loadreg(regs[t].regmap_entry[hr],hr);
4480 for(hr=0;hr<HOST_REGS;hr++) {
4481 if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=64&®s[t].regmap_entry[hr]<TEMPREG+64) {
4482 if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4483 assert(regs[t].regmap_entry[hr]!=64);
4484 if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4485 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4487 emit_loadreg(regs[t].regmap_entry[hr],hr);
4491 emit_sarimm(lr,31,hr);
4496 emit_loadreg(regs[t].regmap_entry[hr],hr);
4499 else if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4500 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4502 emit_sarimm(lr,31,hr);
4509 static int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4511 if(addr>=start && addr<start+slen*4-4)
4513 int t=(addr-start)>>2;
4515 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4516 for(hr=0;hr<HOST_REGS;hr++)
4520 if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4522 if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
4529 if(i_regmap[hr]<TEMPREG)
4531 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4534 else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
4536 if(!((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1))
4541 else // Same register but is it 32-bit or dirty?
4544 if(!((regs[t].dirty>>hr)&1))
4548 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4550 //DebugMessage(M64MSG_VERBOSE, "%x: dirty no match",addr);
4555 if((((regs[t].was32^i_is32)&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)
4557 //DebugMessage(M64MSG_VERBOSE, "%x: is32 no match",addr);
4563 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4564 if(requires_32bit[t]&~i_is32) return 0;
4565 // Delay slots are not valid branch targets
4566 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4567 // Delay slots require additional processing, so do not match
4568 if(is_ds[t]) return 0;
4573 for(hr=0;hr<HOST_REGS;hr++)
4579 if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4593 // Used when a branch jumps into the delay slot of another branch
4594 static void ds_assemble_entry(int i)
4596 int t=(ba[i]-start)>>2;
4597 if(!instr_addr[t]) instr_addr[t]=(u_int)out;
4598 assem_debug("Assemble delay slot at %x",ba[i]);
4600 if(regs[t].regmap_entry[HOST_CCREG]==CCREG&®s[t].regmap[HOST_CCREG]!=CCREG)
4601 wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty,regs[t].was32);
4602 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,rs1[t],rs2[t]);
4603 address_generation(t,®s[t],regs[t].regmap_entry);
4604 if(itype[t]==LOAD||itype[t]==LOADLR||itype[t]==STORE||itype[t]==STORELR||itype[t]==C1LS)
4605 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,MMREG,ROREG);
4606 if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39)
4607 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,INVCP,INVCP);
4612 alu_assemble(t,®s[t]);break;
4614 imm16_assemble(t,®s[t]);break;
4616 shift_assemble(t,®s[t]);break;
4618 shiftimm_assemble(t,®s[t]);break;
4620 load_assemble(t,®s[t]);break;
4622 loadlr_assemble(t,®s[t]);break;
4624 store_assemble(t,®s[t]);break;
4626 storelr_assemble(t,®s[t]);break;
4628 cop0_assemble(t,®s[t]);break;
4630 cop1_assemble(t,®s[t]);break;
4632 c1ls_assemble(t,®s[t]);break;
4634 fconv_assemble(t,®s[t]);break;
4636 float_assemble(t,®s[t]);break;
4638 fcomp_assemble(t,®s[t]);break;
4640 multdiv_assemble(t,®s[t]);break;
4642 mov_assemble(t,®s[t]);break;
4650 DebugMessage(M64MSG_VERBOSE, "Jump in the delay slot. This is probably a bug.");
4652 store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4653 load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4654 if(internal_branch(regs[t].is32,ba[i]+4))
4655 assem_debug("branch: internal");
4657 assem_debug("branch: external");
4658 assert(internal_branch(regs[t].is32,ba[i]+4));
4659 add_to_linker((int)out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4));
4663 static void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
4672 //if(ba[i]>=start && ba[i]<(start+slen*4))
4673 if(internal_branch(branch_regs[i].is32,ba[i]))
4675 int t=(ba[i]-start)>>2;
4676 if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
4684 if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4686 if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
4688 //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4689 emit_andimm(HOST_CCREG,3,HOST_CCREG);
4693 else if(*adj==0||invert) {
4694 emit_addimm_and_set_flags(CLOCK_DIVIDER*(count+2),HOST_CCREG);
4700 emit_cmpimm(HOST_CCREG,-CLOCK_DIVIDER*(count+2));
4704 add_stub(CC_STUB,jaddr,idle?idle:(int)out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
4707 static void do_ccstub(int n)
4710 assem_debug("do_ccstub %x",start+stubs[n][4]*4);
4711 set_jump_target(stubs[n][1],(int)out);
4713 if(stubs[n][6]==NULLDS) {
4714 // Delay slot instruction is nullified ("likely" branch)
4715 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
4717 else if(stubs[n][6]!=TAKEN) {
4718 wb_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty);
4721 if(internal_branch(branch_regs[i].is32,ba[i]))
4722 wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4726 // Save PC as return address
4727 emit_movimm(stubs[n][5],EAX);
4728 emit_writeword(EAX,(int)&pcaddr);
4732 // Return address depends on which way the branch goes
4733 if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
4735 int s1l=get_reg(branch_regs[i].regmap,rs1[i]);
4736 int s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
4737 int s2l=get_reg(branch_regs[i].regmap,rs2[i]);
4738 int s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
4748 if((branch_regs[i].is32>>rs1[i])&(branch_regs[i].is32>>rs2[i])&1) {
4752 #ifdef DESTRUCTIVE_WRITEBACK
4754 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1)
4755 emit_loadreg(rs1[i],s1l);
4758 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1)
4759 emit_loadreg(rs2[i],s1l);
4762 if((branch_regs[i].dirty>>s2l)&(branch_regs[i].is32>>rs2[i])&1)
4763 emit_loadreg(rs2[i],s2l);
4766 int addr,alt,ntaddr;
4769 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4770 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4771 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4779 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4780 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4781 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4787 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
4791 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4792 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4793 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4799 assert(hr<HOST_REGS);
4801 if((opcode[i]&0x2f)==4) // BEQ
4803 #ifdef HAVE_CMOV_IMM
4805 if(s2l>=0) emit_cmp(s1l,s2l);
4806 else emit_test(s1l,s1l);
4807 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
4812 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4814 if(s2h>=0) emit_cmp(s1h,s2h);
4815 else emit_test(s1h,s1h);
4816 emit_cmovne_reg(alt,addr);
4818 if(s2l>=0) emit_cmp(s1l,s2l);
4819 else emit_test(s1l,s1l);
4820 emit_cmovne_reg(alt,addr);
4823 if((opcode[i]&0x2f)==5) // BNE
4825 #ifdef HAVE_CMOV_IMM
4827 if(s2l>=0) emit_cmp(s1l,s2l);
4828 else emit_test(s1l,s1l);
4829 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
4834 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
4836 if(s2h>=0) emit_cmp(s1h,s2h);
4837 else emit_test(s1h,s1h);
4838 emit_cmovne_reg(alt,addr);
4840 if(s2l>=0) emit_cmp(s1l,s2l);
4841 else emit_test(s1l,s1l);
4842 emit_cmovne_reg(alt,addr);
4845 if((opcode[i]&0x2f)==6) // BLEZ
4847 //emit_movimm(ba[i],alt);
4848 //emit_movimm(start+i*4+8,addr);
4849 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4851 if(s1h>=0) emit_mov(addr,ntaddr);
4852 emit_cmovl_reg(alt,addr);
4855 emit_cmovne_reg(ntaddr,addr);
4856 emit_cmovs_reg(alt,addr);
4859 if((opcode[i]&0x2f)==7) // BGTZ
4861 //emit_movimm(ba[i],addr);
4862 //emit_movimm(start+i*4+8,ntaddr);
4863 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
4865 if(s1h>=0) emit_mov(addr,alt);
4866 emit_cmovl_reg(ntaddr,addr);
4869 emit_cmovne_reg(alt,addr);
4870 emit_cmovs_reg(ntaddr,addr);
4873 if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ
4875 //emit_movimm(ba[i],alt);
4876 //emit_movimm(start+i*4+8,addr);
4877 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4878 if(s1h>=0) emit_test(s1h,s1h);
4879 else emit_test(s1l,s1l);
4880 emit_cmovs_reg(alt,addr);
4882 if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ
4884 //emit_movimm(ba[i],addr);
4885 //emit_movimm(start+i*4+8,alt);
4886 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4887 if(s1h>=0) emit_test(s1h,s1h);
4888 else emit_test(s1l,s1l);
4889 emit_cmovs_reg(alt,addr);
4891 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
4892 if(source[i]&0x10000) // BC1T
4894 //emit_movimm(ba[i],alt);
4895 //emit_movimm(start+i*4+8,addr);
4896 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4897 emit_testimm(s1l,0x800000);
4898 emit_cmovne_reg(alt,addr);
4902 //emit_movimm(ba[i],addr);
4903 //emit_movimm(start+i*4+8,alt);
4904 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4905 emit_testimm(s1l,0x800000);
4906 emit_cmovne_reg(alt,addr);
4909 emit_writeword(addr,(int)&pcaddr);
4914 int r=get_reg(branch_regs[i].regmap,rs1[i]);
4915 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
4916 r=get_reg(branch_regs[i].regmap,RTEMP);
4918 emit_writeword(r,(int)&pcaddr);
4920 else {DebugMessage(M64MSG_ERROR, "Unknown branch type in do_ccstub");exit(1);}
4922 // Update cycle count
4923 assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
4924 if(stubs[n][3]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
4925 emit_call((int)cc_interrupt);
4926 if(stubs[n][3]) emit_addimm(HOST_CCREG,-CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
4927 if(stubs[n][6]==TAKEN) {
4928 if(internal_branch(branch_regs[i].is32,ba[i]))
4929 load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
4930 else if(itype[i]==RJUMP) {
4931 if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
4932 emit_readword((int)&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
4934 emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i]));
4936 }else if(stubs[n][6]==NOTTAKEN) {
4937 if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
4938 else load_all_regs(branch_regs[i].regmap);
4939 }else if(stubs[n][6]==NULLDS) {
4940 // Delay slot instruction is nullified ("likely" branch)
4941 if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
4942 else load_all_regs(regs[i].regmap);
4944 load_all_regs(branch_regs[i].regmap);
4946 emit_jmp(stubs[n][2]); // return address
4948 /* This works but uses a lot of memory...
4949 emit_readword((int)&last_count,ECX);
4950 emit_add(HOST_CCREG,ECX,EAX);
4951 emit_writeword(EAX,(int)&Count);
4952 emit_call((int)gen_interupt);
4953 emit_readword((int)&Count,HOST_CCREG);
4954 emit_readword((int)&next_interupt,EAX);
4955 emit_readword((int)&pending_exception,EBX);
4956 emit_writeword(EAX,(int)&last_count);
4957 emit_sub(HOST_CCREG,EAX,HOST_CCREG);
4959 int jne_instr=(int)out;
4961 if(stubs[n][3]) emit_addimm(HOST_CCREG,-2*stubs[n][3],HOST_CCREG);
4962 load_all_regs(branch_regs[i].regmap);
4963 emit_jmp(stubs[n][2]); // return address
4964 set_jump_target(jne_instr,(int)out);
4965 emit_readword((int)&pcaddr,EAX);
4966 // Call get_addr_ht instead of doing the hash table here.
4967 // This code is executed infrequently and takes up a lot of space
4968 // so smaller is better.
4969 emit_storereg(CCREG,HOST_CCREG);
4971 emit_call((int)get_addr_ht);
4972 emit_loadreg(CCREG,HOST_CCREG);
4973 emit_addimm(ESP,4,ESP);
4977 static void add_to_linker(int addr,int target,int ext)
4979 link_addr[linkcount][0]=addr;
4980 link_addr[linkcount][1]=target;
4981 link_addr[linkcount][2]=ext;
4985 static void ujump_assemble(int i,struct regstat *i_regs)
4988 signed char *i_regmap=i_regs->regmap;
4990 if(i==(ba[i]-start)>>2) assem_debug("idle loop");
4991 address_generation(i+1,i_regs,regs[i].regmap_entry);
4993 int temp=get_reg(branch_regs[i].regmap,PTEMP);
4994 if(rt1[i]==31&&temp>=0)
4996 int return_address=start+i*4+8;
4997 if(get_reg(branch_regs[i].regmap,31)>0)
4998 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5001 ds_assemble(i+1,i_regs);
5002 uint64_t bc_unneeded=branch_regs[i].u;
5003 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5004 bc_unneeded|=1|(1LL<<rt1[i]);
5005 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5006 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5007 bc_unneeded,bc_unneeded_upper);
5008 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5011 unsigned int return_address;
5012 assert(rt1[i+1]!=31);
5013 assert(rt2[i+1]!=31);
5014 rt=get_reg(branch_regs[i].regmap,31);
5015 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5017 return_address=start+i*4+8;
5020 if(internal_branch(branch_regs[i].is32,return_address)) {
5022 if(temp==EXCLUDE_REG||temp>=HOST_REGS||
5023 branch_regs[i].regmap[temp]>=0)
5025 temp=get_reg(branch_regs[i].regmap,-1);
5028 if(temp<0) temp=HOST_TEMPREG;
5030 if(temp>=0) do_miniht_insert(return_address,rt,temp);
5031 else emit_movimm(return_address,rt);
5039 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5042 emit_movimm(return_address,rt); // PC into link register
5044 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5050 cc=get_reg(branch_regs[i].regmap,CCREG);
5051 assert(cc==HOST_CCREG);
5052 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5054 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5056 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5057 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5058 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5059 if(internal_branch(branch_regs[i].is32,ba[i]))
5060 assem_debug("branch: internal");
5062 assem_debug("branch: external");
5063 if(internal_branch(branch_regs[i].is32,ba[i])&&is_ds[(ba[i]-start)>>2]) {
5064 ds_assemble_entry(i);
5067 add_to_linker((int)out,ba[i],internal_branch(branch_regs[i].is32,ba[i]));
5072 static void rjump_assemble(int i,struct regstat *i_regs)
5075 signed char *i_regmap=i_regs->regmap;
5079 rs=get_reg(branch_regs[i].regmap,rs1[i]);
5081 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5082 // Delay slot abuse, make a copy of the branch address register
5083 temp=get_reg(branch_regs[i].regmap,RTEMP);
5085 assert(regs[i].regmap[temp]==RTEMP);
5089 address_generation(i+1,i_regs,regs[i].regmap_entry);
5093 if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5094 int return_address=start+i*4+8;
5095 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5101 int rh=get_reg(regs[i].regmap,RHASH);
5102 if(rh>=0) do_preload_rhash(rh);
5105 ds_assemble(i+1,i_regs);
5106 uint64_t bc_unneeded=branch_regs[i].u;
5107 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5108 bc_unneeded|=1|(1LL<<rt1[i]);
5109 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5110 bc_unneeded&=~(1LL<<rs1[i]);
5111 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5112 bc_unneeded,bc_unneeded_upper);
5113 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
5115 int rt,return_address;
5116 assert(rt1[i+1]!=rt1[i]);
5117 assert(rt2[i+1]!=rt1[i]);
5118 rt=get_reg(branch_regs[i].regmap,rt1[i]);
5119 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5121 return_address=start+i*4+8;
5125 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5128 emit_movimm(return_address,rt); // PC into link register
5130 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5133 cc=get_reg(branch_regs[i].regmap,CCREG);
5134 assert(cc==HOST_CCREG);
5136 int rh=get_reg(branch_regs[i].regmap,RHASH);
5137 int ht=get_reg(branch_regs[i].regmap,RHTBL);
5139 if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5140 do_preload_rhtbl(ht);
5144 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5145 #ifdef DESTRUCTIVE_WRITEBACK
5146 if((branch_regs[i].dirty>>rs)&(branch_regs[i].is32>>rs1[i])&1) {
5147 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
5148 emit_loadreg(rs1[i],rs);
5153 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5157 do_miniht_load(ht,rh);
5160 //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5161 //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5163 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5164 add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
5166 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5169 do_miniht_jump(rs,rh,ht);
5174 //if(rs!=EAX) emit_mov(rs,EAX);
5175 //emit_jmp((int)jump_vaddr_eax);
5176 emit_jmp(jump_vaddr_reg[rs]);
5181 emit_shrimm(rs,16,rs);
5182 emit_xor(temp,rs,rs);
5183 emit_movzwl_reg(rs,rs);
5184 emit_shlimm(rs,4,rs);
5185 emit_cmpmem_indexed((int)hash_table,rs,temp);
5186 emit_jne((int)out+14);
5187 emit_readword_indexed((int)hash_table+4,rs,rs);
5189 emit_cmpmem_indexed((int)hash_table+8,rs,temp);
5190 emit_addimm_no_flags(8,rs);
5191 emit_jeq((int)out-17);
5192 // No hit on hash table, call compiler
5195 #ifdef DEBUG_CYCLE_COUNT
5196 emit_readword((int)&last_count,ECX);
5197 emit_add(HOST_CCREG,ECX,HOST_CCREG);
5198 emit_readword((int)&next_interupt,ECX);
5199 emit_writeword(HOST_CCREG,(int)&Count);
5200 emit_sub(HOST_CCREG,ECX,HOST_CCREG);
5201 emit_writeword(ECX,(int)&last_count);
5204 emit_storereg(CCREG,HOST_CCREG);
5205 emit_call((int)get_addr);
5206 emit_loadreg(CCREG,HOST_CCREG);
5207 emit_addimm(ESP,4,ESP);
5209 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5210 if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5214 static void cjump_assemble(int i,struct regstat *i_regs)
5216 signed char *i_regmap=i_regs->regmap;
5219 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5220 assem_debug("match=%d",match);
5221 int s1h,s1l,s2h,s2l;
5222 int prev_cop1_usable=cop1_usable;
5223 int unconditional=0,nop=0;
5226 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5227 if(i==(ba[i]-start)>>2) assem_debug("idle loop");
5228 if(!match) invert=1;
5229 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5230 if(i>(ba[i]-start)>>2) invert=1;
5234 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5235 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5236 s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5237 s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5240 s1l=get_reg(i_regmap,rs1[i]);
5241 s1h=get_reg(i_regmap,rs1[i]|64);
5242 s2l=get_reg(i_regmap,rs2[i]);
5243 s2h=get_reg(i_regmap,rs2[i]|64);
5245 if(rs1[i]==0&&rs2[i]==0)
5247 if(opcode[i]&1) nop=1;
5248 else unconditional=1;
5249 //assert(opcode[i]!=5);
5250 //assert(opcode[i]!=7);
5251 //assert(opcode[i]!=0x15);
5252 //assert(opcode[i]!=0x17);
5258 only32=(regs[i].was32>>rs2[i])&1;
5263 only32=(regs[i].was32>>rs1[i])&1;
5266 only32=(regs[i].was32>>rs1[i])&(regs[i].was32>>rs2[i])&1;
5270 // Out of order execution (delay slot first)
5271 //DebugMessage(M64MSG_VERBOSE, "OOOE");
5272 address_generation(i+1,i_regs,regs[i].regmap_entry);
5273 ds_assemble(i+1,i_regs);
5275 uint64_t bc_unneeded=branch_regs[i].u;
5276 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5277 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5278 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5280 bc_unneeded_upper|=1;
5281 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5282 bc_unneeded,bc_unneeded_upper);
5283 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
5284 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5285 cc=get_reg(branch_regs[i].regmap,CCREG);
5286 assert(cc==HOST_CCREG);
5288 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5289 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5290 //assem_debug("cycle count (adj)");
5292 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5293 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5294 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5295 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5297 assem_debug("branch: internal");
5299 assem_debug("branch: external");
5300 if(internal&&is_ds[(ba[i]-start)>>2]) {
5301 ds_assemble_entry(i);
5304 add_to_linker((int)out,ba[i],internal);
5307 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5308 if(((u_int)out)&7) emit_addnop(0);
5313 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5316 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5319 int taken=0,nottaken=0,nottaken1=0;
5320 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5321 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5325 if(opcode[i]==4) // BEQ
5327 if(s2h>=0) emit_cmp(s1h,s2h);
5328 else emit_test(s1h,s1h);
5332 if(opcode[i]==5) // BNE
5334 if(s2h>=0) emit_cmp(s1h,s2h);
5335 else emit_test(s1h,s1h);
5336 if(invert) taken=(int)out;
5337 else add_to_linker((int)out,ba[i],internal);
5340 if(opcode[i]==6) // BLEZ
5343 // emit_testimm(s1h,0);
5344 if(invert) taken=(int)out;
5345 else add_to_linker((int)out,ba[i],internal);
5350 if(opcode[i]==7) // BGTZ
5353 // emit_testimm(s1h,0);
5356 if(invert) taken=(int)out;
5357 else add_to_linker((int)out,ba[i],internal);
5362 //DebugMessage(M64MSG_VERBOSE, "branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5364 if(opcode[i]==4) // BEQ
5366 if(s2l>=0) emit_cmp(s1l,s2l);
5367 else emit_test(s1l,s1l);
5372 add_to_linker((int)out,ba[i],internal);
5376 if(opcode[i]==5) // BNE
5378 if(s2l>=0) emit_cmp(s1l,s2l);
5379 else emit_test(s1l,s1l);
5384 add_to_linker((int)out,ba[i],internal);
5388 if(opcode[i]==6) // BLEZ
5395 add_to_linker((int)out,ba[i],internal);
5399 if(opcode[i]==7) // BGTZ
5406 add_to_linker((int)out,ba[i],internal);
5411 if(taken) set_jump_target(taken,(int)out);
5412 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5413 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5415 emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5416 add_to_linker((int)out,ba[i],internal);
5419 add_to_linker((int)out,ba[i],internal*2);
5425 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5426 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5427 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5429 assem_debug("branch: internal");
5431 assem_debug("branch: external");
5432 if(internal&&is_ds[(ba[i]-start)>>2]) {
5433 ds_assemble_entry(i);
5436 add_to_linker((int)out,ba[i],internal);
5440 set_jump_target(nottaken,(int)out);
5443 if(nottaken1) set_jump_target(nottaken1,(int)out);
5445 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5447 } // (!unconditional)
5451 // In-order execution (branch first)
5452 //if(likely[i]) DebugMessage(M64MSG_VERBOSE, "IOL");
5454 //DebugMessage(M64MSG_VERBOSE, "IOE");
5455 int taken=0,nottaken=0,nottaken1=0;
5456 if(!unconditional&&!nop) {
5460 if((opcode[i]&0x2f)==4) // BEQ
5462 if(s2h>=0) emit_cmp(s1h,s2h);
5463 else emit_test(s1h,s1h);
5467 if((opcode[i]&0x2f)==5) // BNE
5469 if(s2h>=0) emit_cmp(s1h,s2h);
5470 else emit_test(s1h,s1h);
5474 if((opcode[i]&0x2f)==6) // BLEZ
5482 if((opcode[i]&0x2f)==7) // BGTZ
5492 //DebugMessage(M64MSG_VERBOSE, "branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5494 if((opcode[i]&0x2f)==4) // BEQ
5496 if(s2l>=0) emit_cmp(s1l,s2l);
5497 else emit_test(s1l,s1l);
5501 if((opcode[i]&0x2f)==5) // BNE
5503 if(s2l>=0) emit_cmp(s1l,s2l);
5504 else emit_test(s1l,s1l);
5508 if((opcode[i]&0x2f)==6) // BLEZ
5514 if((opcode[i]&0x2f)==7) // BGTZ
5520 } // if(!unconditional)
5522 uint64_t ds_unneeded=branch_regs[i].u;
5523 uint64_t ds_unneeded_upper=branch_regs[i].uu;
5524 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5525 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5526 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5528 ds_unneeded_upper|=1;
5531 if(taken) set_jump_target(taken,(int)out);
5533 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5534 ds_unneeded,ds_unneeded_upper);
5536 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5537 address_generation(i+1,&branch_regs[i],0);
5538 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5539 ds_assemble(i+1,&branch_regs[i]);
5540 cc=get_reg(branch_regs[i].regmap,CCREG);
5542 emit_loadreg(CCREG,cc=HOST_CCREG);
5543 // CHECK: Is the following instruction (fall thru) allocated ok?
5545 assert(cc==HOST_CCREG);
5546 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5547 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5548 assem_debug("cycle count (adj)");
5549 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5550 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5552 assem_debug("branch: internal");
5554 assem_debug("branch: external");
5555 if(internal&&is_ds[(ba[i]-start)>>2]) {
5556 ds_assemble_entry(i);
5559 add_to_linker((int)out,ba[i],internal);
5564 cop1_usable=prev_cop1_usable;
5565 if(!unconditional) {
5566 if(nottaken1) set_jump_target(nottaken1,(int)out);
5567 set_jump_target(nottaken,(int)out);
5570 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5571 ds_unneeded,ds_unneeded_upper);
5572 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5573 address_generation(i+1,&branch_regs[i],0);
5574 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5575 ds_assemble(i+1,&branch_regs[i]);
5577 cc=get_reg(branch_regs[i].regmap,CCREG);
5578 if(cc==-1&&!likely[i]) {
5579 // Cycle count isn't in a register, temporarily load it then write it out
5580 emit_loadreg(CCREG,HOST_CCREG);
5581 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5584 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5585 emit_storereg(CCREG,HOST_CCREG);
5588 cc=get_reg(i_regmap,CCREG);
5589 assert(cc==HOST_CCREG);
5590 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5593 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5599 static void sjump_assemble(int i,struct regstat *i_regs)
5601 signed char *i_regmap=i_regs->regmap;
5604 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5605 assem_debug("smatch=%d",match);
5607 int prev_cop1_usable=cop1_usable;
5608 int unconditional=0,nevertaken=0;
5611 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5612 if(i==(ba[i]-start)>>2) assem_debug("idle loop");
5613 if(!match) invert=1;
5614 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5615 if(i>(ba[i]-start)>>2) invert=1;
5618 //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
5619 assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
5622 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5623 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5626 s1l=get_reg(i_regmap,rs1[i]);
5627 s1h=get_reg(i_regmap,rs1[i]|64);
5631 if(opcode2[i]&1) unconditional=1;
5633 // These are never taken (r0 is never less than zero)
5634 //assert(opcode2[i]!=0);
5635 //assert(opcode2[i]!=2);
5636 //assert(opcode2[i]!=0x10);
5637 //assert(opcode2[i]!=0x12);
5640 only32=(regs[i].was32>>rs1[i])&1;
5644 // Out of order execution (delay slot first)
5645 //DebugMessage(M64MSG_VERBOSE, "OOOE");
5646 address_generation(i+1,i_regs,regs[i].regmap_entry);
5647 ds_assemble(i+1,i_regs);
5649 uint64_t bc_unneeded=branch_regs[i].u;
5650 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5651 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5652 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5654 bc_unneeded_upper|=1;
5655 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5656 bc_unneeded,bc_unneeded_upper);
5657 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5658 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5660 int rt,return_address;
5661 assert(rt1[i+1]!=31);
5662 assert(rt2[i+1]!=31);
5663 rt=get_reg(branch_regs[i].regmap,31);
5664 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5666 // Save the PC even if the branch is not taken
5667 return_address=start+i*4+8;
5668 emit_movimm(return_address,rt); // PC into link register
5670 if(!nevertaken) emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5674 cc=get_reg(branch_regs[i].regmap,CCREG);
5675 assert(cc==HOST_CCREG);
5677 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5678 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5679 assem_debug("cycle count (adj)");
5681 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5682 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5683 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5684 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5686 assem_debug("branch: internal");
5688 assem_debug("branch: external");
5689 if(internal&&is_ds[(ba[i]-start)>>2]) {
5690 ds_assemble_entry(i);
5693 add_to_linker((int)out,ba[i],internal);
5696 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5697 if(((u_int)out)&7) emit_addnop(0);
5701 else if(nevertaken) {
5702 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5705 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5709 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5710 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5714 if(opcode2[i]==0) // BLTZ
5721 add_to_linker((int)out,ba[i],internal);
5725 if(opcode2[i]==1) // BGEZ
5732 add_to_linker((int)out,ba[i],internal);
5740 if(opcode2[i]==0) // BLTZ
5747 add_to_linker((int)out,ba[i],internal);
5751 if(opcode2[i]==1) // BGEZ
5758 add_to_linker((int)out,ba[i],internal);
5765 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5766 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5768 emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5769 add_to_linker((int)out,ba[i],internal);
5772 add_to_linker((int)out,ba[i],internal*2);
5778 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5779 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5780 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5782 assem_debug("branch: internal");
5784 assem_debug("branch: external");
5785 if(internal&&is_ds[(ba[i]-start)>>2]) {
5786 ds_assemble_entry(i);
5789 add_to_linker((int)out,ba[i],internal);
5793 set_jump_target(nottaken,(int)out);
5797 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5799 } // (!unconditional)
5803 // In-order execution (branch first)
5804 //DebugMessage(M64MSG_VERBOSE, "IOE");
5806 if(!unconditional) {
5807 //DebugMessage(M64MSG_VERBOSE, "branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5811 if((opcode2[i]&0x1d)==0) // BLTZ/BLTZL
5817 if((opcode2[i]&0x1d)==1) // BGEZ/BGEZL
5827 if((opcode2[i]&0x1d)==0) // BLTZ/BLTZL
5833 if((opcode2[i]&0x1d)==1) // BGEZ/BGEZL
5840 } // if(!unconditional)
5842 uint64_t ds_unneeded=branch_regs[i].u;
5843 uint64_t ds_unneeded_upper=branch_regs[i].uu;
5844 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5845 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5846 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5848 ds_unneeded_upper|=1;
5851 //assem_debug("1:");
5852 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5853 ds_unneeded,ds_unneeded_upper);
5855 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5856 address_generation(i+1,&branch_regs[i],0);
5857 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5858 ds_assemble(i+1,&branch_regs[i]);
5859 cc=get_reg(branch_regs[i].regmap,CCREG);
5861 emit_loadreg(CCREG,cc=HOST_CCREG);
5862 // CHECK: Is the following instruction (fall thru) allocated ok?
5864 assert(cc==HOST_CCREG);
5865 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5866 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5867 assem_debug("cycle count (adj)");
5868 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5869 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5871 assem_debug("branch: internal");
5873 assem_debug("branch: external");
5874 if(internal&&is_ds[(ba[i]-start)>>2]) {
5875 ds_assemble_entry(i);
5878 add_to_linker((int)out,ba[i],internal);
5883 cop1_usable=prev_cop1_usable;
5884 if(!unconditional) {
5885 set_jump_target(nottaken,(int)out);
5888 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5889 ds_unneeded,ds_unneeded_upper);
5890 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5891 address_generation(i+1,&branch_regs[i],0);
5892 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5893 ds_assemble(i+1,&branch_regs[i]);
5895 cc=get_reg(branch_regs[i].regmap,CCREG);
5896 if(cc==-1&&!likely[i]) {
5897 // Cycle count isn't in a register, temporarily load it then write it out
5898 emit_loadreg(CCREG,HOST_CCREG);
5899 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5902 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5903 emit_storereg(CCREG,HOST_CCREG);
5906 cc=get_reg(i_regmap,CCREG);
5907 assert(cc==HOST_CCREG);
5908 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5911 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5917 static void fjump_assemble(int i,struct regstat *i_regs)
5919 signed char *i_regmap=i_regs->regmap;
5922 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5923 assem_debug("fmatch=%d",match);
5927 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5928 if(i==(ba[i]-start)>>2) assem_debug("idle loop");
5929 if(!match) invert=1;
5930 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5931 if(i>(ba[i]-start)>>2) invert=1;
5935 fs=get_reg(branch_regs[i].regmap,FSREG);
5936 address_generation(i+1,i_regs,regs[i].regmap_entry); // Is this okay?
5939 fs=get_reg(i_regmap,FSREG);
5942 // Check cop1 unusable
5944 cs=get_reg(i_regmap,CSREG);
5946 emit_testimm(cs,0x20000000);
5949 add_stub(FP_STUB,eaddr,(int)out,i,cs,(int)i_regs,0,0);
5954 // Out of order execution (delay slot first)
5955 //DebugMessage(M64MSG_VERBOSE, "OOOE");
5956 ds_assemble(i+1,i_regs);
5958 uint64_t bc_unneeded=branch_regs[i].u;
5959 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5960 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5961 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5963 bc_unneeded_upper|=1;
5964 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5965 bc_unneeded,bc_unneeded_upper);
5966 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5967 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5968 cc=get_reg(branch_regs[i].regmap,CCREG);
5969 assert(cc==HOST_CCREG);
5970 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5971 assem_debug("cycle count (adj)");
5974 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5977 emit_testimm(fs,0x800000);
5978 if(source[i]&0x10000) // BC1T
5984 add_to_linker((int)out,ba[i],internal);
5993 add_to_linker((int)out,ba[i],internal);
6001 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
6002 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6003 else if(match) emit_addnop(13);
6005 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6006 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6008 assem_debug("branch: internal");
6010 assem_debug("branch: external");
6011 if(internal&&is_ds[(ba[i]-start)>>2]) {
6012 ds_assemble_entry(i);
6015 add_to_linker((int)out,ba[i],internal);
6018 set_jump_target(nottaken,(int)out);
6022 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
6024 } // (!unconditional)
6028 // In-order execution (branch first)
6029 //DebugMessage(M64MSG_VERBOSE, "IOE");
6032 //DebugMessage(M64MSG_VERBOSE, "branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6035 emit_testimm(fs,0x800000);
6036 if(source[i]&0x10000) // BC1T
6047 } // if(!unconditional)
6049 uint64_t ds_unneeded=branch_regs[i].u;
6050 uint64_t ds_unneeded_upper=branch_regs[i].uu;
6051 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6052 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6053 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6055 ds_unneeded_upper|=1;
6057 //assem_debug("1:");
6058 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6059 ds_unneeded,ds_unneeded_upper);
6061 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6062 address_generation(i+1,&branch_regs[i],0);
6063 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6064 ds_assemble(i+1,&branch_regs[i]);
6065 cc=get_reg(branch_regs[i].regmap,CCREG);
6067 emit_loadreg(CCREG,cc=HOST_CCREG);
6068 // CHECK: Is the following instruction (fall thru) allocated ok?
6070 assert(cc==HOST_CCREG);
6071 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6072 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6073 assem_debug("cycle count (adj)");
6074 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6075 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6077 assem_debug("branch: internal");
6079 assem_debug("branch: external");
6080 if(internal&&is_ds[(ba[i]-start)>>2]) {
6081 ds_assemble_entry(i);
6084 add_to_linker((int)out,ba[i],internal);
6089 if(1) { // <- FIXME (don't need this)
6090 set_jump_target(nottaken,(int)out);
6093 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6094 ds_unneeded,ds_unneeded_upper);
6095 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6096 address_generation(i+1,&branch_regs[i],0);
6097 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6098 ds_assemble(i+1,&branch_regs[i]);
6100 cc=get_reg(branch_regs[i].regmap,CCREG);
6101 if(cc==-1&&!likely[i]) {
6102 // Cycle count isn't in a register, temporarily load it then write it out
6103 emit_loadreg(CCREG,HOST_CCREG);
6104 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6107 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6108 emit_storereg(CCREG,HOST_CCREG);
6111 cc=get_reg(i_regmap,CCREG);
6112 assert(cc==HOST_CCREG);
6113 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
6116 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6122 static void pagespan_assemble(int i,struct regstat *i_regs)
6124 int s1l=get_reg(i_regs->regmap,rs1[i]);
6125 int s1h=get_reg(i_regs->regmap,rs1[i]|64);
6126 int s2l=get_reg(i_regs->regmap,rs2[i]);
6127 int s2h=get_reg(i_regs->regmap,rs2[i]|64);
6130 int unconditional=0;
6140 if((i_regs->is32>>rs1[i])&(i_regs->is32>>rs2[i])&1) {
6144 int addr,alt,ntaddr;
6145 if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
6149 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
6150 (i_regs->regmap[hr]&63)!=rs1[i] &&
6151 (i_regs->regmap[hr]&63)!=rs2[i] )
6160 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6161 (i_regs->regmap[hr]&63)!=rs1[i] &&
6162 (i_regs->regmap[hr]&63)!=rs2[i] )
6168 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
6172 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6173 (i_regs->regmap[hr]&63)!=rs1[i] &&
6174 (i_regs->regmap[hr]&63)!=rs2[i] )
6181 assert(hr<HOST_REGS);
6182 if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
6183 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
6185 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6186 if(opcode[i]==2) // J
6190 if(opcode[i]==3) // JAL
6193 int rt=get_reg(i_regs->regmap,31);
6194 emit_movimm(start+i*4+8,rt);
6197 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
6200 if(opcode2[i]==9) // JALR
6202 int rt=get_reg(i_regs->regmap,rt1[i]);
6203 emit_movimm(start+i*4+8,rt);
6206 if((opcode[i]&0x3f)==4) // BEQ
6213 #ifdef HAVE_CMOV_IMM
6215 if(s2l>=0) emit_cmp(s1l,s2l);
6216 else emit_test(s1l,s1l);
6217 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
6223 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6225 if(s2h>=0) emit_cmp(s1h,s2h);
6226 else emit_test(s1h,s1h);
6227 emit_cmovne_reg(alt,addr);
6229 if(s2l>=0) emit_cmp(s1l,s2l);
6230 else emit_test(s1l,s1l);
6231 emit_cmovne_reg(alt,addr);
6234 if((opcode[i]&0x3f)==5) // BNE
6236 #ifdef HAVE_CMOV_IMM
6238 if(s2l>=0) emit_cmp(s1l,s2l);
6239 else emit_test(s1l,s1l);
6240 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
6246 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
6248 if(s2h>=0) emit_cmp(s1h,s2h);
6249 else emit_test(s1h,s1h);
6250 emit_cmovne_reg(alt,addr);
6252 if(s2l>=0) emit_cmp(s1l,s2l);
6253 else emit_test(s1l,s1l);
6254 emit_cmovne_reg(alt,addr);
6257 if((opcode[i]&0x3f)==0x14) // BEQL
6260 if(s2h>=0) emit_cmp(s1h,s2h);
6261 else emit_test(s1h,s1h);
6265 if(s2l>=0) emit_cmp(s1l,s2l);
6266 else emit_test(s1l,s1l);
6267 if(nottaken) set_jump_target(nottaken,(int)out);
6271 if((opcode[i]&0x3f)==0x15) // BNEL
6274 if(s2h>=0) emit_cmp(s1h,s2h);
6275 else emit_test(s1h,s1h);
6279 if(s2l>=0) emit_cmp(s1l,s2l);
6280 else emit_test(s1l,s1l);
6283 if(taken) set_jump_target(taken,(int)out);
6285 if((opcode[i]&0x3f)==6) // BLEZ
6287 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6289 if(s1h>=0) emit_mov(addr,ntaddr);
6290 emit_cmovl_reg(alt,addr);
6293 emit_cmovne_reg(ntaddr,addr);
6294 emit_cmovs_reg(alt,addr);
6297 if((opcode[i]&0x3f)==7) // BGTZ
6299 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
6301 if(s1h>=0) emit_mov(addr,alt);
6302 emit_cmovl_reg(ntaddr,addr);
6305 emit_cmovne_reg(alt,addr);
6306 emit_cmovs_reg(ntaddr,addr);
6309 if((opcode[i]&0x3f)==0x16) // BLEZL
6311 assert((opcode[i]&0x3f)!=0x16);
6313 if((opcode[i]&0x3f)==0x17) // BGTZL
6315 assert((opcode[i]&0x3f)!=0x17);
6317 assert(opcode[i]!=1); // BLTZ/BGEZ
6319 //FIXME: Check CSREG
6320 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
6321 if((source[i]&0x30000)==0) // BC1F
6323 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6324 emit_testimm(s1l,0x800000);
6325 emit_cmovne_reg(alt,addr);
6327 if((source[i]&0x30000)==0x10000) // BC1T
6329 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6330 emit_testimm(s1l,0x800000);
6331 emit_cmovne_reg(alt,addr);
6333 if((source[i]&0x30000)==0x20000) // BC1FL
6335 emit_testimm(s1l,0x800000);
6339 if((source[i]&0x30000)==0x30000) // BC1TL
6341 emit_testimm(s1l,0x800000);
6347 assert(i_regs->regmap[HOST_CCREG]==CCREG);
6348 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6349 if(likely[i]||unconditional)
6351 emit_movimm(ba[i],HOST_BTREG);
6353 else if(addr!=HOST_BTREG)
6355 emit_mov(addr,HOST_BTREG);
6357 void *branch_addr=out;
6359 int target_addr=start+i*4+5;
6361 void *compiled_target_addr=check_addr(target_addr);
6362 emit_extjump_ds((int)branch_addr,target_addr);
6363 if(compiled_target_addr) {
6364 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6365 add_link(target_addr,stub);
6367 else set_jump_target((int)branch_addr,(int)stub);
6370 set_jump_target((int)nottaken,(int)out);
6371 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6372 void *branch_addr=out;
6374 int target_addr=start+i*4+8;
6376 void *compiled_target_addr=check_addr(target_addr);
6377 emit_extjump_ds((int)branch_addr,target_addr);
6378 if(compiled_target_addr) {
6379 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6380 add_link(target_addr,stub);
6382 else set_jump_target((int)branch_addr,(int)stub);
6386 // Assemble the delay slot for the above
6387 static void pagespan_ds()
6389 assem_debug("initial delay slot:");
6390 u_int vaddr=start+1;
6391 u_int page=(0x80000000^vaddr)>>12;
6393 if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[page^0x80000]^0x80000000)>>12;
6394 if(page>2048) page=2048+(page&2047);
6395 if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
6396 if(vpage>2048) vpage=2048+(vpage&2047);
6397 ll_add(jump_dirty+vpage,vaddr,(void *)out);
6399 ll_add(jump_in+page,vaddr,(void *)out);
6400 assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6401 if(regs[0].regmap[HOST_CCREG]!=CCREG)
6402 wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty,regs[0].was32);
6403 if(regs[0].regmap[HOST_BTREG]!=BTREG)
6404 emit_writeword(HOST_BTREG,(int)&branch_target);
6405 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,rs1[0],rs2[0]);
6406 address_generation(0,®s[0],regs[0].regmap_entry);
6407 if(itype[0]==LOAD||itype[0]==LOADLR||itype[0]==STORE||itype[0]==STORELR||itype[0]==C1LS)
6408 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,MMREG,ROREG);
6409 if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39)
6410 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,INVCP,INVCP);
6415 alu_assemble(0,®s[0]);break;
6417 imm16_assemble(0,®s[0]);break;
6419 shift_assemble(0,®s[0]);break;
6421 shiftimm_assemble(0,®s[0]);break;
6423 load_assemble(0,®s[0]);break;
6425 loadlr_assemble(0,®s[0]);break;
6427 store_assemble(0,®s[0]);break;
6429 storelr_assemble(0,®s[0]);break;
6431 cop0_assemble(0,®s[0]);break;
6433 cop1_assemble(0,®s[0]);break;
6435 c1ls_assemble(0,®s[0]);break;
6437 fconv_assemble(0,®s[0]);break;
6439 float_assemble(0,®s[0]);break;
6441 fcomp_assemble(0,®s[0]);break;
6443 multdiv_assemble(0,®s[0]);break;
6445 mov_assemble(0,®s[0]);break;
6453 DebugMessage(M64MSG_VERBOSE, "Jump in the delay slot. This is probably a bug.");
6455 int btaddr=get_reg(regs[0].regmap,BTREG);
6457 btaddr=get_reg(regs[0].regmap,-1);
6458 emit_readword((int)&branch_target,btaddr);
6460 assert(btaddr!=HOST_CCREG);
6461 if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6463 emit_movimm(start+4,HOST_TEMPREG);
6464 emit_cmp(btaddr,HOST_TEMPREG);
6466 emit_cmpimm(btaddr,start+4);
6468 int branch=(int)out;
6470 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,-1);
6471 emit_jmp(jump_vaddr_reg[btaddr]);
6472 set_jump_target(branch,(int)out);
6473 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6474 load_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6477 // Basic liveness analysis for MIPS registers
6478 static void unneeded_registers(int istart,int iend,int r)
6482 uint64_t temp_u,temp_uu;
6487 u=unneeded_reg[iend+1];
6488 uu=unneeded_reg_upper[iend+1];
6491 for (i=iend;i>=istart;i--)
6493 //DebugMessage(M64MSG_VERBOSE, "unneeded registers i=%d (%d,%d) r=%d",i,istart,iend,r);
6494 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6496 // If subroutine call, flag return address as a possible branch target
6497 if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
6499 if(ba[i]<start || ba[i]>=(start+slen*4))
6501 // Branch out of this block, flush all regs
6505 if(itype[i]==UJUMP&&rt1[i]==31)
6507 uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
6509 if(itype[i]==RJUMP&&rs1[i]==31)
6511 uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9
6513 if(start>0x80000400&&start<0x80800000) {
6514 if(itype[i]==UJUMP&&rt1[i]==31)
6516 //uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi
6517 uu=u=0x300FF0F; // Discard at, v0-v1, t0-t9
6519 if(itype[i]==RJUMP&&rs1[i]==31)
6521 //uu=u=0x30300FFF3LL; // Discard at, a0-a3, t0-t9, lo, hi
6522 uu=u=0x300FFF3; // Discard at, a0-a3, t0-t9
6525 branch_unneeded_reg[i]=u;
6526 branch_unneeded_reg_upper[i]=uu;
6527 // Merge in delay slot
6528 tdep=(~uu>>rt1[i+1])&1;
6529 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6530 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6531 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6532 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6533 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6535 // If branch is "likely" (and conditional)
6536 // then we skip the delay slot on the fall-thru path
6539 u&=unneeded_reg[i+2];
6540 uu&=unneeded_reg_upper[i+2];
6551 // Internal branch, flag target
6552 bt[(ba[i]-start)>>2]=1;
6553 if(ba[i]<=start+i*4) {
6555 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6557 // Unconditional branch
6560 // Conditional branch (not taken case)
6561 temp_u=unneeded_reg[i+2];
6562 temp_uu=unneeded_reg_upper[i+2];
6564 // Merge in delay slot
6565 tdep=(~temp_uu>>rt1[i+1])&1;
6566 temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6567 temp_uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6568 temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6569 temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6570 temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6571 temp_u|=1;temp_uu|=1;
6572 // If branch is "likely" (and conditional)
6573 // then we skip the delay slot on the fall-thru path
6576 temp_u&=unneeded_reg[i+2];
6577 temp_uu&=unneeded_reg_upper[i+2];
6585 tdep=(~temp_uu>>rt1[i])&1;
6586 temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6587 temp_uu|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6588 temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6589 temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
6590 temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i]));
6591 temp_u|=1;temp_uu|=1;
6592 unneeded_reg[i]=temp_u;
6593 unneeded_reg_upper[i]=temp_uu;
6594 // Only go three levels deep. This recursion can take an
6595 // excessive amount of time if there are a lot of nested loops.
6597 unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6599 unneeded_reg[(ba[i]-start)>>2]=1;
6600 unneeded_reg_upper[(ba[i]-start)>>2]=1;
6603 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6605 // Unconditional branch
6606 u=unneeded_reg[(ba[i]-start)>>2];
6607 uu=unneeded_reg_upper[(ba[i]-start)>>2];
6608 branch_unneeded_reg[i]=u;
6609 branch_unneeded_reg_upper[i]=uu;
6612 //branch_unneeded_reg[i]=u;
6613 //branch_unneeded_reg_upper[i]=uu;
6614 // Merge in delay slot
6615 tdep=(~uu>>rt1[i+1])&1;
6616 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6617 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6618 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6619 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6620 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6623 // Conditional branch
6624 b=unneeded_reg[(ba[i]-start)>>2];
6625 bu=unneeded_reg_upper[(ba[i]-start)>>2];
6626 branch_unneeded_reg[i]=b;
6627 branch_unneeded_reg_upper[i]=bu;
6630 //branch_unneeded_reg[i]=b;
6631 //branch_unneeded_reg_upper[i]=bu;
6632 // Branch delay slot
6633 tdep=(~uu>>rt1[i+1])&1;
6634 b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6635 bu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6636 b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6637 bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6638 bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6640 // If branch is "likely" then we skip the
6641 // delay slot on the fall-thru path
6646 u&=unneeded_reg[i+2];
6647 uu&=unneeded_reg_upper[i+2];
6658 branch_unneeded_reg[i]&=unneeded_reg[i+2];
6659 branch_unneeded_reg_upper[i]&=unneeded_reg_upper[i+2];
6660 //branch_unneeded_reg[i]=1;
6661 //branch_unneeded_reg_upper[i]=1;
6663 branch_unneeded_reg[i]=1;
6664 branch_unneeded_reg_upper[i]=1;
6670 else if(itype[i]==SYSCALL)
6672 // SYSCALL instruction (software interrupt)
6676 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
6678 // ERET instruction (return from interrupt)
6683 tdep=(~uu>>rt1[i])&1;
6684 // Written registers are unneeded
6689 // Accessed registers are needed
6694 // Source-target dependencies
6695 uu&=~(tdep<<dep1[i]);
6696 uu&=~(tdep<<dep2[i]);
6697 // R0 is always unneeded
6701 unneeded_reg_upper[i]=uu;
6703 DebugMessage(M64MSG_VERBOSE, "ur (%d,%d) %x: ",istart,iend,start+i*4);
6704 DebugMessage(M64MSG_VERBOSE, "U:");
6706 for(r=1;r<=CCREG;r++) {
6707 if((unneeded_reg[i]>>r)&1) {
6708 if(r==HIREG) DebugMessage(M64MSG_VERBOSE, " HI");
6709 else if(r==LOREG) DebugMessage(M64MSG_VERBOSE, " LO");
6710 else DebugMessage(M64MSG_VERBOSE, " r%d",r);
6713 DebugMessage(M64MSG_VERBOSE, " UU:");
6714 for(r=1;r<=CCREG;r++) {
6715 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
6716 if(r==HIREG) DebugMessage(M64MSG_VERBOSE, " HI");
6717 else if(r==LOREG) DebugMessage(M64MSG_VERBOSE, " LO");
6718 else DebugMessage(M64MSG_VERBOSE, " r%d",r);
6724 // Identify registers which are likely to contain 32-bit values
6725 // This is used to predict whether any branches will jump to a
6726 // location with 64-bit values in registers.
6727 static void provisional_32bit()
6731 uint64_t lastbranch=1;
6736 if(itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) {
6737 if(i>1) is32=lastbranch;
6743 if(itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP) {
6745 if(i>2) is32=lastbranch;
6749 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
6751 if(rs1[i-2]==0||rs2[i-2]==0)
6754 is32|=1LL<<rs1[i-2];
6757 is32|=1LL<<rs2[i-2];
6762 // If something jumps here with 64-bit values
6763 // then promote those registers to 64 bits
6766 uint64_t temp_is32=is32;
6769 if(ba[j]==start+i*4)
6770 //temp_is32&=branch_regs[j].is32;
6775 if(ba[j]==start+i*4)
6786 if(type==UJUMP||type==RJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
6787 // Branches don't write registers, consider the delay slot instead.
6798 if(opcode[i]==0x27||opcode[i]==0x37|| // LWU/LD
6799 opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
6808 if(op==0x1a||op==0x1b) is32&=~(1LL<<rt); // LDR/LDL
6809 if(op==0x22) is32|=1LL<<rt; // LWL
6812 if (op==0x08||op==0x09|| // ADDI/ADDIU
6813 op==0x0a||op==0x0b|| // SLTI/SLTIU
6819 if(op==0x18||op==0x19) { // DADDI/DADDIU
6822 // is32|=((is32>>s1)&1LL)<<rt;
6824 if(op==0x0d||op==0x0e) { // ORI/XORI
6825 uint64_t sr=((is32>>s1)&1LL);
6841 if(op2>=0x20&&op2<=0x23) { // ADD/ADDU/SUB/SUBU
6844 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
6847 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
6848 uint64_t sr=((is32>>s1)&(is32>>s2)&1LL);
6852 else if(op2>=0x2c&&op2<=0x2d) { // DADD/DADDU
6857 uint64_t sr=((is32>>s1)&1LL);
6862 uint64_t sr=((is32>>s2)&1LL);
6870 else if(op2>=0x2e&&op2<=0x2f) { // DSUB/DSUBU
6875 uint64_t sr=((is32>>s1)&1LL);
6885 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
6886 is32&=~((1LL<<HIREG)|(1LL<<LOREG));
6889 is32|=(1LL<<HIREG)|(1LL<<LOREG);
6894 uint64_t sr=((is32>>s1)&1LL);
6900 if(op2>=0x14&&op2<=0x17) is32&=~(1LL<<rt); // DSLLV/DSRLV/DSRAV
6901 else is32|=1LL<<rt; // SLLV/SRLV/SRAV
6905 // DSLL/DSRL/DSRA/DSLL32/DSRL32 but not DSRA32 have 64-bit result
6906 if(op2>=0x38&&op2<0x3f) is32&=~(1LL<<rt);
6909 if(op2==0) is32|=1LL<<rt; // MFC0
6912 if(op2==0) is32|=1LL<<rt; // MFC1
6913 if(op2==1) is32&=~(1LL<<rt); // DMFC1
6914 if(op2==2) is32|=1LL<<rt; // CFC1
6933 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
6935 if(rt1[i-1]==31) // JAL/JALR
6937 // Subroutine call will return here, don't alloc any registers
6942 // Internal branch will jump here, match registers to caller
6950 // Identify registers which may be assumed to contain 32-bit values
6951 // and where optimizations will rely on this.
6952 // This is used to determine whether backward branches can safely
6953 // jump to a location with 64-bit values in registers.
6954 static void provisional_r32()
6959 for (i=slen-1;i>=0;i--)
6962 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6964 if(ba[i]<start || ba[i]>=(start+slen*4))
6966 // Branch out of this block, don't need anything
6972 // Need whatever matches the target
6973 // (and doesn't get overwritten by the delay slot instruction)
6975 int t=(ba[i]-start)>>2;
6976 if(ba[i]>start+i*4) {
6978 //if(!(requires_32bit[t]&~regs[i].was32))
6979 // r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
6980 if(!(pr32[t]&~regs[i].was32))
6981 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
6984 if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
6985 r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
6988 // Conditional branch may need registers for following instructions
6989 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
6992 //r32|=requires_32bit[i+2];
6995 // Mark this address as a branch target since it may be called
6996 // upon return from interrupt
7000 // Merge in delay slot
7002 // These are overwritten unless the branch is "likely"
7003 // and the delay slot is nullified if not taken
7004 r32&=~(1LL<<rt1[i+1]);
7005 r32&=~(1LL<<rt2[i+1]);
7007 // Assume these are needed (delay slot)
7010 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
7014 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
7016 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
7018 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
7020 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
7022 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
7025 else if(itype[i]==SYSCALL)
7027 // SYSCALL instruction (software interrupt)
7030 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7032 // ERET instruction (return from interrupt)
7036 r32&=~(1LL<<rt1[i]);
7037 r32&=~(1LL<<rt2[i]);
7040 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
7044 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
7046 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
7048 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
7050 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
7052 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
7054 //requires_32bit[i]=r32;
7057 // Dirty registers which are 32-bit, require 32-bit input
7058 // as they will be written as 32-bit values
7059 for(hr=0;hr<HOST_REGS;hr++)
7061 if(regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64) {
7062 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
7063 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
7064 pr32[i]|=1LL<<regs[i].regmap_entry[hr];
7065 //requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
7072 // Write back dirty registers as soon as we will no longer modify them,
7073 // so that we don't end up with lots of writes at the branches.
7074 static void clean_registers(int istart,int iend,int wr)
7078 u_int will_dirty_i,will_dirty_next,temp_will_dirty;
7079 u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
7081 will_dirty_i=will_dirty_next=0;
7082 wont_dirty_i=wont_dirty_next=0;
7084 will_dirty_i=will_dirty_next=will_dirty[iend+1];
7085 wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
7087 for (i=iend;i>=istart;i--)
7089 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7091 if(ba[i]<start || ba[i]>=(start+slen*4))
7093 // Branch out of this block, flush all regs
7094 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7096 // Unconditional branch
7099 // Merge in delay slot (will dirty)
7100 for(r=0;r<HOST_REGS;r++) {
7101 if(r!=EXCLUDE_REG) {
7102 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7103 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7104 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7105 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7106 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7107 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7108 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7109 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7110 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7111 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7112 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7113 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7114 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7115 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7121 // Conditional branch
7123 wont_dirty_i=wont_dirty_next;
7124 // Merge in delay slot (will dirty)
7125 for(r=0;r<HOST_REGS;r++) {
7126 if(r!=EXCLUDE_REG) {
7128 // Might not dirty if likely branch is not taken
7129 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7130 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7131 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7132 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7133 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7134 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
7135 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7136 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7137 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7138 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7139 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7140 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7141 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7142 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7147 // Merge in delay slot (wont dirty)
7148 for(r=0;r<HOST_REGS;r++) {
7149 if(r!=EXCLUDE_REG) {
7150 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7151 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7152 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7153 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7154 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7155 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7156 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7157 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7158 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7159 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7163 #ifndef DESTRUCTIVE_WRITEBACK
7164 branch_regs[i].dirty&=wont_dirty_i;
7166 branch_regs[i].dirty|=will_dirty_i;
7172 if(ba[i]<=start+i*4) {
7174 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7176 // Unconditional branch
7179 // Merge in delay slot (will dirty)
7180 for(r=0;r<HOST_REGS;r++) {
7181 if(r!=EXCLUDE_REG) {
7182 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7183 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7184 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7185 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7186 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7187 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7188 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7189 if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7190 if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7191 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7192 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7193 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7194 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7195 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7199 // Conditional branch (not taken case)
7200 temp_will_dirty=will_dirty_next;
7201 temp_wont_dirty=wont_dirty_next;
7202 // Merge in delay slot (will dirty)
7203 for(r=0;r<HOST_REGS;r++) {
7204 if(r!=EXCLUDE_REG) {
7206 // Will not dirty if likely branch is not taken
7207 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7208 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7209 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7210 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7211 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7212 if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
7213 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7214 //if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7215 //if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7216 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7217 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7218 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7219 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7220 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7225 // Merge in delay slot (wont dirty)
7226 for(r=0;r<HOST_REGS;r++) {
7227 if(r!=EXCLUDE_REG) {
7228 if((regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7229 if((regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7230 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7231 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7232 if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7233 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7234 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7235 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7236 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7237 if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7240 // Deal with changed mappings
7242 for(r=0;r<HOST_REGS;r++) {
7243 if(r!=EXCLUDE_REG) {
7244 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
7245 temp_will_dirty&=~(1<<r);
7246 temp_wont_dirty&=~(1<<r);
7247 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7248 temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7249 temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7251 temp_will_dirty|=1<<r;
7252 temp_wont_dirty|=1<<r;
7259 will_dirty[i]=temp_will_dirty;
7260 wont_dirty[i]=temp_wont_dirty;
7261 clean_registers((ba[i]-start)>>2,i-1,0);
7263 // Limit recursion. It can take an excessive amount
7264 // of time if there are a lot of nested loops.
7265 will_dirty[(ba[i]-start)>>2]=0;
7266 wont_dirty[(ba[i]-start)>>2]=-1;
7271 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7273 // Unconditional branch
7276 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7277 for(r=0;r<HOST_REGS;r++) {
7278 if(r!=EXCLUDE_REG) {
7279 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7280 will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
7281 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7283 if(branch_regs[i].regmap[r]>=0) {
7284 will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7285 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7290 // Merge in delay slot
7291 for(r=0;r<HOST_REGS;r++) {
7292 if(r!=EXCLUDE_REG) {
7293 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7294 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7295 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7296 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7297 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7298 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7299 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7300 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7301 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7302 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7303 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7304 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7305 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7306 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7310 // Conditional branch
7311 will_dirty_i=will_dirty_next;
7312 wont_dirty_i=wont_dirty_next;
7313 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7314 for(r=0;r<HOST_REGS;r++) {
7315 if(r!=EXCLUDE_REG) {
7316 signed char target_reg=branch_regs[i].regmap[r];
7317 if(target_reg==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7318 will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7319 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7321 else if(target_reg>=0) {
7322 will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
7323 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
7325 // Treat delay slot as part of branch too
7326 /*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7327 will_dirty[i+1]&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7328 wont_dirty[i+1]|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7332 will_dirty[i+1]&=~(1<<r);
7337 // Merge in delay slot
7338 for(r=0;r<HOST_REGS;r++) {
7339 if(r!=EXCLUDE_REG) {
7341 // Might not dirty if likely branch is not taken
7342 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7343 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7344 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7345 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7346 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7347 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7348 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7349 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7350 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7351 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7352 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7353 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7354 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7355 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7360 // Merge in delay slot (won't dirty)
7361 for(r=0;r<HOST_REGS;r++) {
7362 if(r!=EXCLUDE_REG) {
7363 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7364 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7365 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7366 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7367 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7368 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7369 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7370 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7371 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7372 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7376 #ifndef DESTRUCTIVE_WRITEBACK
7377 branch_regs[i].dirty&=wont_dirty_i;
7379 branch_regs[i].dirty|=will_dirty_i;
7384 else if(itype[i]==SYSCALL)
7386 // SYSCALL instruction (software interrupt)
7390 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7392 // ERET instruction (return from interrupt)
7396 will_dirty_next=will_dirty_i;
7397 wont_dirty_next=wont_dirty_i;
7398 for(r=0;r<HOST_REGS;r++) {
7399 if(r!=EXCLUDE_REG) {
7400 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7401 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7402 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7403 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7404 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7405 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7406 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7407 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7409 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
7411 // Don't store a register immediately after writing it,
7412 // may prevent dual-issue.
7413 if((regs[i].regmap[r]&63)==rt1[i-1]) wont_dirty_i|=1<<r;
7414 if((regs[i].regmap[r]&63)==rt2[i-1]) wont_dirty_i|=1<<r;
7420 will_dirty[i]=will_dirty_i;
7421 wont_dirty[i]=wont_dirty_i;
7422 // Mark registers that won't be dirtied as not dirty
7424 /*DebugMessage(M64MSG_VERBOSE, "wr (%d,%d) %x will:",istart,iend,start+i*4);
7425 for(r=0;r<HOST_REGS;r++) {
7426 if((will_dirty_i>>r)&1) {
7427 DebugMessage(M64MSG_VERBOSE, " r%d",r);
7431 //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=FJUMP)) {
7432 regs[i].dirty|=will_dirty_i;
7433 #ifndef DESTRUCTIVE_WRITEBACK
7434 regs[i].dirty&=wont_dirty_i;
7435 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7437 if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
7438 for(r=0;r<HOST_REGS;r++) {
7439 if(r!=EXCLUDE_REG) {
7440 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
7441 regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
7442 }else {/*DebugMessage(M64MSG_VERBOSE, "i: %x (%d) mismatch(+2): %d",start+i*4,i,r); / *assert(!((wont_dirty_i>>r)&1));*/}
7450 for(r=0;r<HOST_REGS;r++) {
7451 if(r!=EXCLUDE_REG) {
7452 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
7453 regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
7454 }else {/*DebugMessage(M64MSG_VERBOSE, "i: %x (%d) mismatch(+1): %d",start+i*4,i,r);/ *assert(!((wont_dirty_i>>r)&1));*/}
7462 // Deal with changed mappings
7463 temp_will_dirty=will_dirty_i;
7464 temp_wont_dirty=wont_dirty_i;
7465 for(r=0;r<HOST_REGS;r++) {
7466 if(r!=EXCLUDE_REG) {
7468 if(regs[i].regmap[r]==regmap_pre[i][r]) {
7470 #ifndef DESTRUCTIVE_WRITEBACK
7471 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7473 regs[i].wasdirty|=will_dirty_i&(1<<r);
7476 else if((nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
7477 // Register moved to a different register
7478 will_dirty_i&=~(1<<r);
7479 wont_dirty_i&=~(1<<r);
7480 will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
7481 wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
7483 #ifndef DESTRUCTIVE_WRITEBACK
7484 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7486 regs[i].wasdirty|=will_dirty_i&(1<<r);
7490 will_dirty_i&=~(1<<r);
7491 wont_dirty_i&=~(1<<r);
7492 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7493 will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7494 wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7497 /*DebugMessage(M64MSG_VERBOSE, "i: %x (%d) mismatch: %d",start+i*4,i,r);/ *assert(!((will_dirty>>r)&1));*/
7507 static void disassemble_inst(int i)
7509 if (bt[i]) DebugMessage(M64MSG_VERBOSE, "*"); else DebugMessage(M64MSG_VERBOSE, " ");
7512 printf (" %x: %s %8x",start+i*4,insn[i],ba[i]);break;
7514 printf (" %x: %s r%d,r%d,%8x",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
7516 printf (" %x: %s r%d,%8x",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
7518 printf (" %x: %s %8x",start+i*4,insn[i],ba[i]);break;
7520 if ((opcode2[i]&1)&&rt1[i]!=31)
7521 printf (" %x: %s r%d,r%d",start+i*4,insn[i],rt1[i],rs1[i]);
7523 printf (" %x: %s r%d",start+i*4,insn[i],rs1[i]);
7526 printf (" %x: %s (pagespan) r%d,r%d,%8x",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break;
7528 if(opcode[i]==0xf) //LUI
7529 printf (" %x: %s r%d,%4x0000",start+i*4,insn[i],rt1[i],imm[i]&0xffff);
7531 printf (" %x: %s r%d,r%d,%d",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7535 printf (" %x: %s r%d,r%d+%x",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7539 printf (" %x: %s r%d,r%d+%x",start+i*4,insn[i],rs2[i],rs1[i],imm[i]);
7543 printf (" %x: %s r%d,r%d,r%d",start+i*4,insn[i],rt1[i],rs1[i],rs2[i]);
7546 printf (" %x: %s r%d,r%d",start+i*4,insn[i],rs1[i],rs2[i]);
7549 printf (" %x: %s r%d,r%d,%d",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7552 if((opcode2[i]&0x1d)==0x10)
7553 printf (" %x: %s r%d",start+i*4,insn[i],rt1[i]);
7554 else if((opcode2[i]&0x1d)==0x11)
7555 printf (" %x: %s r%d",start+i*4,insn[i],rs1[i]);
7557 printf (" %x: %s",start+i*4,insn[i]);
7561 printf (" %x: %s r%d,cpr0[%d]",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC0
7562 else if(opcode2[i]==4)
7563 printf (" %x: %s r%d,cpr0[%d]",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC0
7564 else printf (" %x: %s",start+i*4,insn[i]);
7568 printf (" %x: %s r%d,cpr1[%d]",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC1
7569 else if(opcode2[i]>3)
7570 printf (" %x: %s r%d,cpr1[%d]",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC1
7571 else printf (" %x: %s",start+i*4,insn[i]);
7574 printf (" %x: %s cpr1[%d],r%d+%x",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7577 //printf (" %s %8x",insn[i],source[i]);
7578 printf (" %x: %s",start+i*4,insn[i]);
7583 void new_dynarec_init()
7585 DebugMessage(M64MSG_INFO, "Init new dynarec");
7587 #if NEW_DYNAREC == NEW_DYNAREC_ARM
7588 if ((base_addr = mmap ((u_char *)BASE_ADDR, 1<<TARGET_SIZE_2,
7589 PROT_READ | PROT_WRITE | PROT_EXEC,
7590 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
7591 -1, 0)) <= 0) {DebugMessage(M64MSG_ERROR, "mmap() failed");}
7593 if ((base_addr = mmap (NULL, 1<<TARGET_SIZE_2,
7594 PROT_READ | PROT_WRITE | PROT_EXEC,
7595 MAP_PRIVATE | MAP_ANONYMOUS,
7596 -1, 0)) <= 0) {DebugMessage(M64MSG_ERROR, "mmap() failed");}
7598 out=(u_char *)base_addr;
7600 rdword=&readmem_dword;
7601 fake_pc.f.r.rs=(long long int *)&readmem_dword;
7602 fake_pc.f.r.rt=(long long int *)&readmem_dword;
7603 fake_pc.f.r.rd=(long long int *)&readmem_dword;
7605 for(n=0x80000;n<0x80800;n++)
7607 for(n=0;n<65536;n++)
7608 hash_table[n][0]=hash_table[n][2]=-1;
7609 memset(mini_ht,-1,sizeof(mini_ht));
7610 memset(restore_candidate,0,sizeof(restore_candidate));
7612 expirep=16384; // Expiry pointer, +2 blocks
7613 pending_exception=0;
7616 // Copy this into local area so we don't have to put it in every literal pool
7617 invc_ptr=invalid_code;
7622 for(n=0;n<524288;n++) // 0 .. 0x7FFFFFFF
7624 for(n=524288;n<526336;n++) // 0x80000000 .. 0x807FFFFF
7625 memory_map[n]=((u_int)rdram-0x80000000)>>2;
7626 for(n=526336;n<1048576;n++) // 0x80800000 .. 0xFFFFFFFF
7628 for(n=0;n<0x8000;n++) { // 0 .. 0x7FFFFFFF
7629 writemem[n] = write_nomem_new;
7630 writememb[n] = write_nomemb_new;
7631 writememh[n] = write_nomemh_new;
7632 writememd[n] = write_nomemd_new;
7633 readmem[n] = read_nomem_new;
7634 readmemb[n] = read_nomemb_new;
7635 readmemh[n] = read_nomemh_new;
7636 readmemd[n] = read_nomemd_new;
7638 for(n=0x8000;n<0x8080;n++) { // 0x80000000 .. 0x807FFFFF
7639 writemem[n] = write_rdram_new;
7640 writememb[n] = write_rdramb_new;
7641 writememh[n] = write_rdramh_new;
7642 writememd[n] = write_rdramd_new;
7644 for(n=0xC000;n<0x10000;n++) { // 0xC0000000 .. 0xFFFFFFFF
7645 writemem[n] = write_nomem_new;
7646 writememb[n] = write_nomemb_new;
7647 writememh[n] = write_nomemh_new;
7648 writememd[n] = write_nomemd_new;
7649 readmem[n] = read_nomem_new;
7650 readmemb[n] = read_nomemb_new;
7651 readmemh[n] = read_nomemh_new;
7652 readmemd[n] = read_nomemd_new;
7658 void new_dynarec_cleanup()
7661 if (munmap (base_addr, 1<<TARGET_SIZE_2) < 0) {DebugMessage(M64MSG_ERROR, "munmap() failed");}
7662 for(n=0;n<4096;n++) ll_clear(jump_in+n);
7663 for(n=0;n<4096;n++) ll_clear(jump_out+n);
7664 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7666 if (munmap (ROM_COPY, 67108864) < 0) {DebugMessage(M64MSG_ERROR, "munmap() failed");}
7670 int new_recompile_block(int addr)
7673 if(addr==0x800cd050) {
7675 for(block=0x80000;block<0x80800;block++) invalidate_block(block);
7677 for(n=0;n<=2048;n++) ll_clear(jump_dirty+n);
7680 //if(Count==365117028) tracedebug=1;
7681 assem_debug("NOTCOMPILED: addr = %x -> %x", (int)addr, (int)out);
7682 #if defined (COUNT_NOTCOMPILEDS )
7684 log_message( "notcompiledCount=%i", notcompiledCount );
7686 //DebugMessage(M64MSG_VERBOSE, "NOTCOMPILED: addr = %x -> %x", (int)addr, (int)out);
7687 //DebugMessage(M64MSG_VERBOSE, "TRACE: count=%d next=%d (compile %x)",Count,next_interupt,addr);
7689 //DebugMessage(M64MSG_VERBOSE, "TRACE: count=%d next=%d (checksum %x)",Count,next_interupt,mchecksum());
7690 //DebugMessage(M64MSG_VERBOSE, "fpu mapping=%x enabled=%x",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
7691 /*if(Count>=312978186) {
7695 start = (u_int)addr&~3;
7696 //assert(((u_int)addr&1)==0);
7697 if ((int)addr >= 0xa4000000 && (int)addr < 0xa4001000) {
7698 source = (u_int *)((u_int)SP_DMEM+start-0xa4000000);
7699 pagelimit = 0xa4001000;
7701 else if ((int)addr >= 0x80000000 && (int)addr < 0x80800000) {
7702 source = (u_int *)((u_int)rdram+start-0x80000000);
7703 pagelimit = 0x80800000;
7705 else if ((signed int)addr >= (signed int)0xC0000000) {
7706 //DebugMessage(M64MSG_VERBOSE, "addr=%x mm=%x",(u_int)addr,(memory_map[start>>12]<<2));
7707 //if(tlb_LUT_r[start>>12])
7708 //source = (u_int *)(((int)rdram)+(tlb_LUT_r[start>>12]&0xFFFFF000)+(((int)addr)&0xFFF)-0x80000000);
7709 if((signed int)memory_map[start>>12]>=0) {
7710 source = (u_int *)((u_int)(start+(memory_map[start>>12]<<2)));
7711 pagelimit=(start+4096)&0xFFFFF000;
7712 int map=memory_map[start>>12];
7715 //DebugMessage(M64MSG_VERBOSE, "start: %x next: %x",map,memory_map[pagelimit>>12]);
7716 if((map&0xBFFFFFFF)==(memory_map[pagelimit>>12]&0xBFFFFFFF)) pagelimit+=4096;
7718 assem_debug("pagelimit=%x",pagelimit);
7719 assem_debug("mapping=%x (%x)",memory_map[start>>12],(memory_map[start>>12]<<2)+start);
7722 assem_debug("Compile at unmapped memory address: %x ", (int)addr);
7723 //assem_debug("start: %x next: %x",memory_map[start>>12],memory_map[(start+4096)>>12]);
7724 return 1; // Caller will invoke exception handler
7726 //DebugMessage(M64MSG_VERBOSE, "source= %x",(int)source);
7729 //DebugMessage(M64MSG_VERBOSE, "Compile at bogus memory address: %x ", (int)addr);
7730 log_message("Compile at bogus memory address: %x", (int)addr);
7734 /* Pass 1: disassemble */
7735 /* Pass 2: register dependencies, branch targets */
7736 /* Pass 3: register allocation */
7737 /* Pass 4: branch dependencies */
7738 /* Pass 5: pre-alloc */
7739 /* Pass 6: optimize clean/dirty state */
7740 /* Pass 7: flag 32-bit registers */
7741 /* Pass 8: assembly */
7742 /* Pass 9: linker */
7743 /* Pass 10: garbage collection / free memory */
7747 unsigned int type,op,op2;
7749 //DebugMessage(M64MSG_VERBOSE, "addr = %x source = %x %x", addr,source,source[0]);
7751 /* Pass 1 disassembly */
7753 for(i=0;!done;i++) {
7754 bt[i]=0;likely[i]=0;ooo[i]=0;op2=0;
7755 minimum_free_regs[i]=0;
7756 opcode[i]=op=source[i]>>26;
7759 case 0x00: strcpy(insn[i],"special"); type=NI;
7763 case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
7764 case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
7765 case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
7766 case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
7767 case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
7768 case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
7769 case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
7770 case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
7771 case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
7772 case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
7773 case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
7774 case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
7775 case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
7776 case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
7777 case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
7778 case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
7779 case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
7780 case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
7781 case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
7782 case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
7783 case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
7784 case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
7785 case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
7786 case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
7787 case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
7788 case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
7789 case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
7790 case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
7791 case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
7792 case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
7793 case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
7794 case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
7795 case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
7796 case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
7797 case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
7798 case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
7799 case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
7800 case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
7801 case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
7802 case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
7803 case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
7804 case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
7805 case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
7806 case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
7807 case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
7808 case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
7809 case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
7810 case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
7811 case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
7812 case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
7813 case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
7814 case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
7817 case 0x01: strcpy(insn[i],"regimm"); type=NI;
7818 op2=(source[i]>>16)&0x1f;
7821 case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
7822 case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
7823 case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
7824 case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
7825 case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
7826 case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
7827 case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
7828 case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
7829 case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
7830 case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
7831 case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
7832 case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
7833 case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
7834 case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
7837 case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
7838 case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
7839 case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
7840 case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
7841 case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
7842 case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
7843 case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
7844 case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
7845 case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
7846 case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
7847 case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
7848 case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
7849 case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
7850 case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
7851 case 0x10: strcpy(insn[i],"cop0"); type=NI;
7852 op2=(source[i]>>21)&0x1f;
7855 case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
7856 case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
7857 case 0x10: strcpy(insn[i],"tlb"); type=NI;
7858 switch(source[i]&0x3f)
7860 case 0x01: strcpy(insn[i],"TLBR"); type=COP0; break;
7861 case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break;
7862 case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break;
7863 case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break;
7864 case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
7868 case 0x11: strcpy(insn[i],"cop1"); type=NI;
7869 op2=(source[i]>>21)&0x1f;
7872 case 0x00: strcpy(insn[i],"MFC1"); type=COP1; break;
7873 case 0x01: strcpy(insn[i],"DMFC1"); type=COP1; break;
7874 case 0x02: strcpy(insn[i],"CFC1"); type=COP1; break;
7875 case 0x04: strcpy(insn[i],"MTC1"); type=COP1; break;
7876 case 0x05: strcpy(insn[i],"DMTC1"); type=COP1; break;
7877 case 0x06: strcpy(insn[i],"CTC1"); type=COP1; break;
7878 case 0x08: strcpy(insn[i],"BC1"); type=FJUMP;
7879 switch((source[i]>>16)&0x3)
7881 case 0x00: strcpy(insn[i],"BC1F"); break;
7882 case 0x01: strcpy(insn[i],"BC1T"); break;
7883 case 0x02: strcpy(insn[i],"BC1FL"); break;
7884 case 0x03: strcpy(insn[i],"BC1TL"); break;
7887 case 0x10: strcpy(insn[i],"C1.S"); type=NI;
7888 switch(source[i]&0x3f)
7890 case 0x00: strcpy(insn[i],"ADD.S"); type=FLOAT; break;
7891 case 0x01: strcpy(insn[i],"SUB.S"); type=FLOAT; break;
7892 case 0x02: strcpy(insn[i],"MUL.S"); type=FLOAT; break;
7893 case 0x03: strcpy(insn[i],"DIV.S"); type=FLOAT; break;
7894 case 0x04: strcpy(insn[i],"SQRT.S"); type=FLOAT; break;
7895 case 0x05: strcpy(insn[i],"ABS.S"); type=FLOAT; break;
7896 case 0x06: strcpy(insn[i],"MOV.S"); type=FLOAT; break;
7897 case 0x07: strcpy(insn[i],"NEG.S"); type=FLOAT; break;
7898 case 0x08: strcpy(insn[i],"ROUND.L.S"); type=FCONV; break;
7899 case 0x09: strcpy(insn[i],"TRUNC.L.S"); type=FCONV; break;
7900 case 0x0A: strcpy(insn[i],"CEIL.L.S"); type=FCONV; break;
7901 case 0x0B: strcpy(insn[i],"FLOOR.L.S"); type=FCONV; break;
7902 case 0x0C: strcpy(insn[i],"ROUND.W.S"); type=FCONV; break;
7903 case 0x0D: strcpy(insn[i],"TRUNC.W.S"); type=FCONV; break;
7904 case 0x0E: strcpy(insn[i],"CEIL.W.S"); type=FCONV; break;
7905 case 0x0F: strcpy(insn[i],"FLOOR.W.S"); type=FCONV; break;
7906 case 0x21: strcpy(insn[i],"CVT.D.S"); type=FCONV; break;
7907 case 0x24: strcpy(insn[i],"CVT.W.S"); type=FCONV; break;
7908 case 0x25: strcpy(insn[i],"CVT.L.S"); type=FCONV; break;
7909 case 0x30: strcpy(insn[i],"C.F.S"); type=FCOMP; break;
7910 case 0x31: strcpy(insn[i],"C.UN.S"); type=FCOMP; break;
7911 case 0x32: strcpy(insn[i],"C.EQ.S"); type=FCOMP; break;
7912 case 0x33: strcpy(insn[i],"C.UEQ.S"); type=FCOMP; break;
7913 case 0x34: strcpy(insn[i],"C.OLT.S"); type=FCOMP; break;
7914 case 0x35: strcpy(insn[i],"C.ULT.S"); type=FCOMP; break;
7915 case 0x36: strcpy(insn[i],"C.OLE.S"); type=FCOMP; break;
7916 case 0x37: strcpy(insn[i],"C.ULE.S"); type=FCOMP; break;
7917 case 0x38: strcpy(insn[i],"C.SF.S"); type=FCOMP; break;
7918 case 0x39: strcpy(insn[i],"C.NGLE.S"); type=FCOMP; break;
7919 case 0x3A: strcpy(insn[i],"C.SEQ.S"); type=FCOMP; break;
7920 case 0x3B: strcpy(insn[i],"C.NGL.S"); type=FCOMP; break;
7921 case 0x3C: strcpy(insn[i],"C.LT.S"); type=FCOMP; break;
7922 case 0x3D: strcpy(insn[i],"C.NGE.S"); type=FCOMP; break;
7923 case 0x3E: strcpy(insn[i],"C.LE.S"); type=FCOMP; break;
7924 case 0x3F: strcpy(insn[i],"C.NGT.S"); type=FCOMP; break;
7927 case 0x11: strcpy(insn[i],"C1.D"); type=NI;
7928 switch(source[i]&0x3f)
7930 case 0x00: strcpy(insn[i],"ADD.D"); type=FLOAT; break;
7931 case 0x01: strcpy(insn[i],"SUB.D"); type=FLOAT; break;
7932 case 0x02: strcpy(insn[i],"MUL.D"); type=FLOAT; break;
7933 case 0x03: strcpy(insn[i],"DIV.D"); type=FLOAT; break;
7934 case 0x04: strcpy(insn[i],"SQRT.D"); type=FLOAT; break;
7935 case 0x05: strcpy(insn[i],"ABS.D"); type=FLOAT; break;
7936 case 0x06: strcpy(insn[i],"MOV.D"); type=FLOAT; break;
7937 case 0x07: strcpy(insn[i],"NEG.D"); type=FLOAT; break;
7938 case 0x08: strcpy(insn[i],"ROUND.L.D"); type=FCONV; break;
7939 case 0x09: strcpy(insn[i],"TRUNC.L.D"); type=FCONV; break;
7940 case 0x0A: strcpy(insn[i],"CEIL.L.D"); type=FCONV; break;
7941 case 0x0B: strcpy(insn[i],"FLOOR.L.D"); type=FCONV; break;
7942 case 0x0C: strcpy(insn[i],"ROUND.W.D"); type=FCONV; break;
7943 case 0x0D: strcpy(insn[i],"TRUNC.W.D"); type=FCONV; break;
7944 case 0x0E: strcpy(insn[i],"CEIL.W.D"); type=FCONV; break;
7945 case 0x0F: strcpy(insn[i],"FLOOR.W.D"); type=FCONV; break;
7946 case 0x20: strcpy(insn[i],"CVT.S.D"); type=FCONV; break;
7947 case 0x24: strcpy(insn[i],"CVT.W.D"); type=FCONV; break;
7948 case 0x25: strcpy(insn[i],"CVT.L.D"); type=FCONV; break;
7949 case 0x30: strcpy(insn[i],"C.F.D"); type=FCOMP; break;
7950 case 0x31: strcpy(insn[i],"C.UN.D"); type=FCOMP; break;
7951 case 0x32: strcpy(insn[i],"C.EQ.D"); type=FCOMP; break;
7952 case 0x33: strcpy(insn[i],"C.UEQ.D"); type=FCOMP; break;
7953 case 0x34: strcpy(insn[i],"C.OLT.D"); type=FCOMP; break;
7954 case 0x35: strcpy(insn[i],"C.ULT.D"); type=FCOMP; break;
7955 case 0x36: strcpy(insn[i],"C.OLE.D"); type=FCOMP; break;
7956 case 0x37: strcpy(insn[i],"C.ULE.D"); type=FCOMP; break;
7957 case 0x38: strcpy(insn[i],"C.SF.D"); type=FCOMP; break;
7958 case 0x39: strcpy(insn[i],"C.NGLE.D"); type=FCOMP; break;
7959 case 0x3A: strcpy(insn[i],"C.SEQ.D"); type=FCOMP; break;
7960 case 0x3B: strcpy(insn[i],"C.NGL.D"); type=FCOMP; break;
7961 case 0x3C: strcpy(insn[i],"C.LT.D"); type=FCOMP; break;
7962 case 0x3D: strcpy(insn[i],"C.NGE.D"); type=FCOMP; break;
7963 case 0x3E: strcpy(insn[i],"C.LE.D"); type=FCOMP; break;
7964 case 0x3F: strcpy(insn[i],"C.NGT.D"); type=FCOMP; break;
7967 case 0x14: strcpy(insn[i],"C1.W"); type=NI;
7968 switch(source[i]&0x3f)
7970 case 0x20: strcpy(insn[i],"CVT.S.W"); type=FCONV; break;
7971 case 0x21: strcpy(insn[i],"CVT.D.W"); type=FCONV; break;
7974 case 0x15: strcpy(insn[i],"C1.L"); type=NI;
7975 switch(source[i]&0x3f)
7977 case 0x20: strcpy(insn[i],"CVT.S.L"); type=FCONV; break;
7978 case 0x21: strcpy(insn[i],"CVT.D.L"); type=FCONV; break;
7983 case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
7984 case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
7985 case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
7986 case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
7987 case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
7988 case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
7989 case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
7990 case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
7991 case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
7992 case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
7993 case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
7994 case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
7995 case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
7996 case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
7997 case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
7998 case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
7999 case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
8000 case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
8001 case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
8002 case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
8003 case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
8004 case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
8005 case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
8006 case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
8007 case 0x30: strcpy(insn[i],"LL"); type=NI; break;
8008 case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
8009 case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
8010 case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
8011 case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
8012 case 0x38: strcpy(insn[i],"SC"); type=NI; break;
8013 case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
8014 case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
8015 case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
8016 case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
8017 default: strcpy(insn[i],"???"); type=NI; break;
8021 /* Get registers/immediates */
8029 rs1[i]=(source[i]>>21)&0x1f;
8031 rt1[i]=(source[i]>>16)&0x1f;
8033 imm[i]=(short)source[i];
8037 rs1[i]=(source[i]>>21)&0x1f;
8038 rs2[i]=(source[i]>>16)&0x1f;
8041 imm[i]=(short)source[i];
8042 if(op==0x2c||op==0x2d||op==0x3f) us1[i]=rs2[i]; // 64-bit SDL/SDR/SD
8045 // LWL/LWR only load part of the register,
8046 // therefore the target register must be treated as a source too
8047 rs1[i]=(source[i]>>21)&0x1f;
8048 rs2[i]=(source[i]>>16)&0x1f;
8049 rt1[i]=(source[i]>>16)&0x1f;
8051 imm[i]=(short)source[i];
8052 if(op==0x1a||op==0x1b) us1[i]=rs2[i]; // LDR/LDL
8053 if(op==0x26) dep1[i]=rt1[i]; // LWR
8056 if (op==0x0f) rs1[i]=0; // LUI instruction has no source register
8057 else rs1[i]=(source[i]>>21)&0x1f;
8059 rt1[i]=(source[i]>>16)&0x1f;
8061 if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
8062 imm[i]=(unsigned short)source[i];
8064 imm[i]=(short)source[i];
8066 if(op==0x18||op==0x19) us1[i]=rs1[i]; // DADDI/DADDIU
8067 if(op==0x0a||op==0x0b) us1[i]=rs1[i]; // SLTI/SLTIU
8068 if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI
8075 // The JAL instruction writes to r31.
8082 rs1[i]=(source[i]>>21)&0x1f;
8086 // The JALR instruction writes to rd.
8088 rt1[i]=(source[i]>>11)&0x1f;
8093 rs1[i]=(source[i]>>21)&0x1f;
8094 rs2[i]=(source[i]>>16)&0x1f;
8097 if(op&2) { // BGTZ/BLEZ
8105 rs1[i]=(source[i]>>21)&0x1f;
8110 if(op2&0x10) { // BxxAL
8112 // NOTE: If the branch is not taken, r31 is still overwritten
8114 likely[i]=(op2&2)>>1;
8121 likely[i]=((source[i])>>17)&1;
8124 rs1[i]=(source[i]>>21)&0x1f; // source
8125 rs2[i]=(source[i]>>16)&0x1f; // subtract amount
8126 rt1[i]=(source[i]>>11)&0x1f; // destination
8128 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
8129 us1[i]=rs1[i];us2[i]=rs2[i];
8131 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
8132 dep1[i]=rs1[i];dep2[i]=rs2[i];
8134 else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB
8135 dep1[i]=rs1[i];dep2[i]=rs2[i];
8139 rs1[i]=(source[i]>>21)&0x1f; // source
8140 rs2[i]=(source[i]>>16)&0x1f; // divisor
8143 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
8144 us1[i]=rs1[i];us2[i]=rs2[i];
8152 if(op2==0x10) rs1[i]=HIREG; // MFHI
8153 if(op2==0x11) rt1[i]=HIREG; // MTHI
8154 if(op2==0x12) rs1[i]=LOREG; // MFLO
8155 if(op2==0x13) rt1[i]=LOREG; // MTLO
8156 if((op2&0x1d)==0x10) rt1[i]=(source[i]>>11)&0x1f; // MFxx
8157 if((op2&0x1d)==0x11) rs1[i]=(source[i]>>21)&0x1f; // MTxx
8161 rs1[i]=(source[i]>>16)&0x1f; // target of shift
8162 rs2[i]=(source[i]>>21)&0x1f; // shift amount
8163 rt1[i]=(source[i]>>11)&0x1f; // destination
8165 // DSLLV/DSRLV/DSRAV are 64-bit
8166 if(op2>=0x14&&op2<=0x17) us1[i]=rs1[i];
8169 rs1[i]=(source[i]>>16)&0x1f;
8171 rt1[i]=(source[i]>>11)&0x1f;
8173 imm[i]=(source[i]>>6)&0x1f;
8174 // DSxx32 instructions
8175 if(op2>=0x3c) imm[i]|=0x20;
8176 // DSLL/DSRL/DSRA/DSRA32/DSRL32 but not DSLL32 require 64-bit source
8177 if(op2>=0x38&&op2!=0x3c) us1[i]=rs1[i];
8184 if(op2==0) rt1[i]=(source[i]>>16)&0x1F; // MFC0
8185 if(op2==4) rs1[i]=(source[i]>>16)&0x1F; // MTC0
8186 if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status
8187 if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET
8194 if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
8195 if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
8196 if(op2==5) us1[i]=rs1[i]; // DMTC1
8200 rs1[i]=(source[i]>>21)&0x1F;
8204 imm[i]=(short)source[i];
8231 /* Calculate branch target addresses */
8233 ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
8234 else if(type==CJUMP&&rs1[i]==rs2[i]&&(op&1))
8235 ba[i]=start+i*4+8; // Ignore never taken branch
8236 else if(type==SJUMP&&rs1[i]==0&&!(op2&1))
8237 ba[i]=start+i*4+8; // Ignore never taken branch
8238 else if(type==CJUMP||type==SJUMP||type==FJUMP)
8239 ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
8241 /* Is this the end of the block? */
8242 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
8243 if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
8245 // Does the block continue due to a branch?
8248 if(ba[j]==start+i*4) done=j=0; // Branch into delay slot
8249 if(ba[j]==start+i*4+4) done=j=0;
8250 if(ba[j]==start+i*4+8) done=j=0;
8254 if(stop_after_jal) done=1;
8256 if((source[i+1]&0xfc00003f)==0x0d) done=1;
8258 // Don't recompile stuff that's already compiled
8259 if(check_addr(start+i*4+4)) done=1;
8260 // Don't get too close to the limit
8261 if(i>MAXBLOCK/2) done=1;
8263 if(i>0&&itype[i-1]==SYSCALL&&stop_after_jal) done=1;
8264 assert(i<MAXBLOCK-1);
8265 if(start+i*4==pagelimit-4) done=1;
8266 assert(start+i*4<pagelimit);
8267 if (i==MAXBLOCK-1) done=1;
8268 // Stop if we're compiling junk
8269 if(itype[i]==NI&&opcode[i]==0x11) {
8270 done=stop_after_jal=1;
8271 DebugMessage(M64MSG_VERBOSE, "Disabled speculative precompilation");
8275 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP||itype[i-1]==FJUMP) {
8276 if(start+i*4==pagelimit) {
8282 /* Pass 2 - Register dependencies and branch targets */
8284 unneeded_registers(0,slen-1,0);
8286 /* Pass 3 - Register allocation */
8288 struct regstat current; // Current register allocations/status
8291 current.u=unneeded_reg[0];
8292 current.uu=unneeded_reg_upper[0];
8293 clear_all_regs(current.regmap);
8294 alloc_reg(¤t,0,CCREG);
8295 dirty_reg(¤t,CCREG);
8302 provisional_32bit();
8305 // First instruction is delay slot
8310 unneeded_reg_upper[0]=1;
8311 current.regmap[HOST_BTREG]=BTREG;
8319 for(hr=0;hr<HOST_REGS;hr++)
8321 // Is this really necessary?
8322 if(current.regmap[hr]==0) current.regmap[hr]=-1;
8328 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
8330 if(rs1[i-2]==0||rs2[i-2]==0)
8333 current.is32|=1LL<<rs1[i-2];
8334 int hr=get_reg(current.regmap,rs1[i-2]|64);
8335 if(hr>=0) current.regmap[hr]=-1;
8338 current.is32|=1LL<<rs2[i-2];
8339 int hr=get_reg(current.regmap,rs2[i-2]|64);
8340 if(hr>=0) current.regmap[hr]=-1;
8345 // If something jumps here with 64-bit values
8346 // then promote those registers to 64 bits
8349 uint64_t temp_is32=current.is32;
8352 if(ba[j]==start+i*4)
8353 temp_is32&=branch_regs[j].is32;
8357 if(ba[j]==start+i*4)
8361 if(temp_is32!=current.is32) {
8362 //DebugMessage(M64MSG_VERBOSE, "dumping 32-bit regs (%x)",start+i*4);
8363 #ifndef DESTRUCTIVE_WRITEBACK
8366 for(hr=0;hr<HOST_REGS;hr++)
8368 int r=current.regmap[hr];
8371 if((current.dirty>>hr)&((current.is32&~temp_is32)>>r)&1) {
8373 //DebugMessage(M64MSG_VERBOSE, "restore %d",r);
8377 current.is32=temp_is32;
8380 memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
8381 regs[i].wasconst=current.isconst;
8382 regs[i].was32=current.is32;
8383 regs[i].wasdirty=current.dirty;
8384 #ifdef DESTRUCTIVE_WRITEBACK
8385 // To change a dirty register from 32 to 64 bits, we must write
8386 // it out during the previous cycle (for branches, 2 cycles)
8387 if(i<slen-1&&bt[i+1]&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP)
8389 uint64_t temp_is32=current.is32;
8392 if(ba[j]==start+i*4+4)
8393 temp_is32&=branch_regs[j].is32;
8397 if(ba[j]==start+i*4+4)
8401 if(temp_is32!=current.is32) {
8402 //DebugMessage(M64MSG_VERBOSE, "pre-dumping 32-bit regs (%x)",start+i*4);
8403 for(hr=0;hr<HOST_REGS;hr++)
8405 int r=current.regmap[hr];
8408 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8409 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP)
8411 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63))
8413 //DebugMessage(M64MSG_VERBOSE, "dump %d/r%d",hr,r);
8414 current.regmap[hr]=-1;
8415 if(get_reg(current.regmap,r|64)>=0)
8416 current.regmap[get_reg(current.regmap,r|64)]=-1;
8424 else if(i<slen-2&&bt[i+2]&&(source[i-1]>>16)!=0x1000&&(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP))
8426 uint64_t temp_is32=current.is32;
8429 if(ba[j]==start+i*4+8)
8430 temp_is32&=branch_regs[j].is32;
8434 if(ba[j]==start+i*4+8)
8438 if(temp_is32!=current.is32) {
8439 //DebugMessage(M64MSG_VERBOSE, "pre-dumping 32-bit regs (%x)",start+i*4);
8440 for(hr=0;hr<HOST_REGS;hr++)
8442 int r=current.regmap[hr];
8445 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8446 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63)&&rs1[i+1]!=(r&63)&&rs2[i+1]!=(r&63))
8448 //DebugMessage(M64MSG_VERBOSE, "dump %d/r%d",hr,r);
8449 current.regmap[hr]=-1;
8450 if(get_reg(current.regmap,r|64)>=0)
8451 current.regmap[get_reg(current.regmap,r|64)]=-1;
8459 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
8461 current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
8462 current.uu=unneeded_reg_upper[i+1]&~((1LL<<us1[i])|(1LL<<us2[i]));
8463 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8472 current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
8473 current.uu=branch_unneeded_reg_upper[i]&~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
8474 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
8475 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8476 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8479 } else { DebugMessage(M64MSG_ERROR, "oops, branch at end of block with no delay slot");exit(1); }
8483 ds=0; // Skip delay slot, already allocated as part of branch
8484 // ...but we need to alloc it in case something jumps here
8486 current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
8487 current.uu=branch_unneeded_reg_upper[i-1]&unneeded_reg_upper[i+1];
8489 current.u=branch_unneeded_reg[i-1];
8490 current.uu=branch_unneeded_reg_upper[i-1];
8492 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8493 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8494 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8497 struct regstat temp;
8498 memcpy(&temp,¤t,sizeof(current));
8499 temp.wasdirty=temp.dirty;
8500 temp.was32=temp.is32;
8501 // TODO: Take into account unconditional branches, as below
8502 delayslot_alloc(&temp,i);
8503 memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
8504 regs[i].wasdirty=temp.wasdirty;
8505 regs[i].was32=temp.was32;
8506 regs[i].dirty=temp.dirty;
8507 regs[i].is32=temp.is32;
8511 // Create entry (branch target) regmap
8512 for(hr=0;hr<HOST_REGS;hr++)
8514 int r=temp.regmap[hr];
8516 if(r!=regmap_pre[i][hr]) {
8517 regs[i].regmap_entry[hr]=-1;
8522 if((current.u>>r)&1) {
8523 regs[i].regmap_entry[hr]=-1;
8524 regs[i].regmap[hr]=-1;
8525 //Don't clear regs in the delay slot as the branch might need them
8526 //current.regmap[hr]=-1;
8528 regs[i].regmap_entry[hr]=r;
8531 if((current.uu>>(r&63))&1) {
8532 regs[i].regmap_entry[hr]=-1;
8533 regs[i].regmap[hr]=-1;
8534 //Don't clear regs in the delay slot as the branch might need them
8535 //current.regmap[hr]=-1;
8537 regs[i].regmap_entry[hr]=r;
8541 // First instruction expects CCREG to be allocated
8542 if(i==0&&hr==HOST_CCREG)
8543 regs[i].regmap_entry[hr]=CCREG;
8545 regs[i].regmap_entry[hr]=-1;
8549 else { // Not delay slot
8552 //current.isconst=0; // DEBUG
8553 //current.wasconst=0; // DEBUG
8554 //regs[i].wasconst=0; // DEBUG
8555 clear_const(¤t,rt1[i]);
8556 alloc_cc(¤t,i);
8557 dirty_reg(¤t,CCREG);
8559 alloc_reg(¤t,i,31);
8560 dirty_reg(¤t,31);
8561 assert(rs1[i+1]!=31&&rs2[i+1]!=31);
8563 alloc_reg(¤t,i,PTEMP);
8565 //current.is32|=1LL<<rt1[i];
8568 delayslot_alloc(¤t,i+1);
8569 //current.isconst=0; // DEBUG
8571 //DebugMessage(M64MSG_VERBOSE, "i=%d, isconst=%x",i,current.isconst);
8574 //current.isconst=0;
8575 //current.wasconst=0;
8576 //regs[i].wasconst=0;
8577 clear_const(¤t,rs1[i]);
8578 clear_const(¤t,rt1[i]);
8579 alloc_cc(¤t,i);
8580 dirty_reg(¤t,CCREG);
8581 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
8582 alloc_reg(¤t,i,rs1[i]);
8584 alloc_reg(¤t,i,rt1[i]);
8585 dirty_reg(¤t,rt1[i]);
8586 assert(rs1[i+1]!=31&&rs2[i+1]!=31);
8588 alloc_reg(¤t,i,PTEMP);
8592 if(rs1[i]==31) { // JALR
8593 alloc_reg(¤t,i,RHASH);
8594 #ifndef HOST_IMM_ADDR32
8595 alloc_reg(¤t,i,RHTBL);
8599 delayslot_alloc(¤t,i+1);
8601 // The delay slot overwrites our source register,
8602 // allocate a temporary register to hold the old value.
8606 delayslot_alloc(¤t,i+1);
8608 alloc_reg(¤t,i,RTEMP);
8610 //current.isconst=0; // DEBUG
8615 //current.isconst=0;
8616 //current.wasconst=0;
8617 //regs[i].wasconst=0;
8618 clear_const(¤t,rs1[i]);
8619 clear_const(¤t,rs2[i]);
8620 if((opcode[i]&0x3E)==4) // BEQ/BNE
8622 alloc_cc(¤t,i);
8623 dirty_reg(¤t,CCREG);
8624 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
8625 if(rs2[i]) alloc_reg(¤t,i,rs2[i]);
8626 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8628 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
8629 if(rs2[i]) alloc_reg64(¤t,i,rs2[i]);
8631 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
8632 (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) {
8633 // The delay slot overwrites one of our conditions.
8634 // Allocate the branch condition registers instead.
8638 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
8639 if(rs2[i]) alloc_reg(¤t,i,rs2[i]);
8640 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8642 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
8643 if(rs2[i]) alloc_reg64(¤t,i,rs2[i]);
8649 delayslot_alloc(¤t,i+1);
8653 if((opcode[i]&0x3E)==6) // BLEZ/BGTZ
8655 alloc_cc(¤t,i);
8656 dirty_reg(¤t,CCREG);
8657 alloc_reg(¤t,i,rs1[i]);
8658 if(!(current.is32>>rs1[i]&1))
8660 alloc_reg64(¤t,i,rs1[i]);
8662 if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
8663 // The delay slot overwrites one of our conditions.
8664 // Allocate the branch condition registers instead.
8668 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
8669 if(!((current.is32>>rs1[i])&1))
8671 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
8677 delayslot_alloc(¤t,i+1);
8681 // Don't alloc the delay slot yet because we might not execute it
8682 if((opcode[i]&0x3E)==0x14) // BEQL/BNEL
8687 alloc_cc(¤t,i);
8688 dirty_reg(¤t,CCREG);
8689 alloc_reg(¤t,i,rs1[i]);
8690 alloc_reg(¤t,i,rs2[i]);
8691 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8693 alloc_reg64(¤t,i,rs1[i]);
8694 alloc_reg64(¤t,i,rs2[i]);
8698 if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL
8703 alloc_cc(¤t,i);
8704 dirty_reg(¤t,CCREG);
8705 alloc_reg(¤t,i,rs1[i]);
8706 if(!(current.is32>>rs1[i]&1))
8708 alloc_reg64(¤t,i,rs1[i]);
8712 //current.isconst=0;
8715 //current.isconst=0;
8716 //current.wasconst=0;
8717 //regs[i].wasconst=0;
8718 clear_const(¤t,rs1[i]);
8719 clear_const(¤t,rt1[i]);
8720 //if((opcode2[i]&0x1E)==0x0) // BLTZ/BGEZ
8721 if((opcode2[i]&0x0E)==0x0) // BLTZ/BGEZ
8723 alloc_cc(¤t,i);
8724 dirty_reg(¤t,CCREG);
8725 alloc_reg(¤t,i,rs1[i]);
8726 if(!(current.is32>>rs1[i]&1))
8728 alloc_reg64(¤t,i,rs1[i]);
8730 if (rt1[i]==31) { // BLTZAL/BGEZAL
8731 alloc_reg(¤t,i,31);
8732 dirty_reg(¤t,31);
8733 assert(rs1[i+1]!=31&&rs2[i+1]!=31);
8734 //#ifdef REG_PREFETCH
8735 //alloc_reg(¤t,i,PTEMP);
8737 //current.is32|=1LL<<rt1[i];
8739 if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
8740 // The delay slot overwrites the branch condition.
8741 // Allocate the branch condition registers instead.
8745 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
8746 if(!((current.is32>>rs1[i])&1))
8748 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
8754 delayslot_alloc(¤t,i+1);
8758 // Don't alloc the delay slot yet because we might not execute it
8759 if((opcode2[i]&0x1E)==0x2) // BLTZL/BGEZL
8764 alloc_cc(¤t,i);
8765 dirty_reg(¤t,CCREG);
8766 alloc_reg(¤t,i,rs1[i]);
8767 if(!(current.is32>>rs1[i]&1))
8769 alloc_reg64(¤t,i,rs1[i]);
8773 //current.isconst=0;
8779 if(likely[i]==0) // BC1F/BC1T
8781 // TODO: Theoretically we can run out of registers here on x86.
8782 // The delay slot can allocate up to six, and we need to check
8783 // CSREG before executing the delay slot. Possibly we can drop
8784 // the cycle count and then reload it after checking that the
8785 // FPU is in a usable state, or don't do out-of-order execution.
8786 alloc_cc(¤t,i);
8787 dirty_reg(¤t,CCREG);
8788 alloc_reg(¤t,i,FSREG);
8789 alloc_reg(¤t,i,CSREG);
8790 if(itype[i+1]==FCOMP) {
8791 // The delay slot overwrites the branch condition.
8792 // Allocate the branch condition registers instead.
8793 alloc_cc(¤t,i);
8794 dirty_reg(¤t,CCREG);
8795 alloc_reg(¤t,i,CSREG);
8796 alloc_reg(¤t,i,FSREG);
8800 delayslot_alloc(¤t,i+1);
8801 alloc_reg(¤t,i+1,CSREG);
8805 // Don't alloc the delay slot yet because we might not execute it
8806 if(likely[i]) // BC1FL/BC1TL
8808 alloc_cc(¤t,i);
8809 dirty_reg(¤t,CCREG);
8810 alloc_reg(¤t,i,CSREG);
8811 alloc_reg(¤t,i,FSREG);
8817 imm16_alloc(¤t,i);
8821 load_alloc(¤t,i);
8825 store_alloc(¤t,i);
8828 alu_alloc(¤t,i);
8831 shift_alloc(¤t,i);
8834 multdiv_alloc(¤t,i);
8837 shiftimm_alloc(¤t,i);
8840 mov_alloc(¤t,i);
8843 cop0_alloc(¤t,i);
8846 cop1_alloc(¤t,i);
8849 c1ls_alloc(¤t,i);
8852 fconv_alloc(¤t,i);
8855 float_alloc(¤t,i);
8858 fcomp_alloc(¤t,i);
8861 syscall_alloc(¤t,i);
8864 pagespan_alloc(¤t,i);
8868 // Drop the upper half of registers that have become 32-bit
8869 current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i]));
8870 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
8871 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8872 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8875 current.uu|=current.is32&((1LL<<rt1[i+1])|(1LL<<rt2[i+1]));
8876 current.uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
8877 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
8878 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8882 // Create entry (branch target) regmap
8883 for(hr=0;hr<HOST_REGS;hr++)
8886 r=current.regmap[hr];
8888 if(r!=regmap_pre[i][hr]) {
8889 // TODO: delay slot (?)
8890 or=get_reg(regmap_pre[i],r); // Get old mapping for this register
8891 if(or<0||(r&63)>=TEMPREG){
8892 regs[i].regmap_entry[hr]=-1;
8896 // Just move it to a different register
8897 regs[i].regmap_entry[hr]=r;
8898 // If it was dirty before, it's still dirty
8899 if((regs[i].wasdirty>>or)&1) dirty_reg(¤t,r&63);
8906 regs[i].regmap_entry[hr]=0;
8910 if((current.u>>r)&1) {
8911 regs[i].regmap_entry[hr]=-1;
8912 //regs[i].regmap[hr]=-1;
8913 current.regmap[hr]=-1;
8915 regs[i].regmap_entry[hr]=r;
8918 if((current.uu>>(r&63))&1) {
8919 regs[i].regmap_entry[hr]=-1;
8920 //regs[i].regmap[hr]=-1;
8921 current.regmap[hr]=-1;
8923 regs[i].regmap_entry[hr]=r;
8927 // Branches expect CCREG to be allocated at the target
8928 if(regmap_pre[i][hr]==CCREG)
8929 regs[i].regmap_entry[hr]=CCREG;
8931 regs[i].regmap_entry[hr]=-1;
8934 memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
8936 /* Branch post-alloc */
8939 current.was32=current.is32;
8940 current.wasdirty=current.dirty;
8941 switch(itype[i-1]) {
8943 memcpy(&branch_regs[i-1],¤t,sizeof(current));
8944 branch_regs[i-1].isconst=0;
8945 branch_regs[i-1].wasconst=0;
8946 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
8947 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
8948 alloc_cc(&branch_regs[i-1],i-1);
8949 dirty_reg(&branch_regs[i-1],CCREG);
8950 if(rt1[i-1]==31) { // JAL
8951 alloc_reg(&branch_regs[i-1],i-1,31);
8952 dirty_reg(&branch_regs[i-1],31);
8953 branch_regs[i-1].is32|=1LL<<31;
8955 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8956 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
8959 memcpy(&branch_regs[i-1],¤t,sizeof(current));
8960 branch_regs[i-1].isconst=0;
8961 branch_regs[i-1].wasconst=0;
8962 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
8963 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
8964 alloc_cc(&branch_regs[i-1],i-1);
8965 dirty_reg(&branch_regs[i-1],CCREG);
8966 alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]);
8967 if(rt1[i-1]!=0) { // JALR
8968 alloc_reg(&branch_regs[i-1],i-1,rt1[i-1]);
8969 dirty_reg(&branch_regs[i-1],rt1[i-1]);
8970 branch_regs[i-1].is32|=1LL<<rt1[i-1];
8973 if(rs1[i-1]==31) { // JALR
8974 alloc_reg(&branch_regs[i-1],i-1,RHASH);
8975 #ifndef HOST_IMM_ADDR32
8976 alloc_reg(&branch_regs[i-1],i-1,RHTBL);
8980 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8981 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
8984 if((opcode[i-1]&0x3E)==4) // BEQ/BNE
8986 alloc_cc(¤t,i-1);
8987 dirty_reg(¤t,CCREG);
8988 if((rs1[i-1]&&(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]))||
8989 (rs2[i-1]&&(rs2[i-1]==rt1[i]||rs2[i-1]==rt2[i]))) {
8990 // The delay slot overwrote one of our conditions
8991 // Delay slot goes after the test (in order)
8992 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
8993 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
8994 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8997 delayslot_alloc(¤t,i);
9002 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9003 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9004 // Alloc the branch condition registers
9005 if(rs1[i-1]) alloc_reg(¤t,i-1,rs1[i-1]);
9006 if(rs2[i-1]) alloc_reg(¤t,i-1,rs2[i-1]);
9007 if(!((current.is32>>rs1[i-1])&(current.is32>>rs2[i-1])&1))
9009 if(rs1[i-1]) alloc_reg64(¤t,i-1,rs1[i-1]);
9010 if(rs2[i-1]) alloc_reg64(¤t,i-1,rs2[i-1]);
9013 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9014 branch_regs[i-1].isconst=0;
9015 branch_regs[i-1].wasconst=0;
9016 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9017 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9020 if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ
9022 alloc_cc(¤t,i-1);
9023 dirty_reg(¤t,CCREG);
9024 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9025 // The delay slot overwrote the branch condition
9026 // Delay slot goes after the test (in order)
9027 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9028 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9029 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9032 delayslot_alloc(¤t,i);
9037 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9038 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9039 // Alloc the branch condition register
9040 alloc_reg(¤t,i-1,rs1[i-1]);
9041 if(!(current.is32>>rs1[i-1]&1))
9043 alloc_reg64(¤t,i-1,rs1[i-1]);
9046 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9047 branch_regs[i-1].isconst=0;
9048 branch_regs[i-1].wasconst=0;
9049 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9050 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9053 // Alloc the delay slot in case the branch is taken
9054 if((opcode[i-1]&0x3E)==0x14) // BEQL/BNEL
9056 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9057 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9058 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9059 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9060 alloc_cc(&branch_regs[i-1],i);
9061 dirty_reg(&branch_regs[i-1],CCREG);
9062 delayslot_alloc(&branch_regs[i-1],i);
9063 branch_regs[i-1].isconst=0;
9064 alloc_reg(¤t,i,CCREG); // Not taken path
9065 dirty_reg(¤t,CCREG);
9066 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9069 if((opcode[i-1]&0x3E)==0x16) // BLEZL/BGTZL
9071 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9072 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9073 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9074 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9075 alloc_cc(&branch_regs[i-1],i);
9076 dirty_reg(&branch_regs[i-1],CCREG);
9077 delayslot_alloc(&branch_regs[i-1],i);
9078 branch_regs[i-1].isconst=0;
9079 alloc_reg(¤t,i,CCREG); // Not taken path
9080 dirty_reg(¤t,CCREG);
9081 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9085 //if((opcode2[i-1]&0x1E)==0) // BLTZ/BGEZ
9086 if((opcode2[i-1]&0x0E)==0) // BLTZ/BGEZ
9088 alloc_cc(¤t,i-1);
9089 dirty_reg(¤t,CCREG);
9090 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9091 // The delay slot overwrote the branch condition
9092 // Delay slot goes after the test (in order)
9093 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9094 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9095 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9098 delayslot_alloc(¤t,i);
9103 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9104 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9105 // Alloc the branch condition register
9106 alloc_reg(¤t,i-1,rs1[i-1]);
9107 if(!(current.is32>>rs1[i-1]&1))
9109 alloc_reg64(¤t,i-1,rs1[i-1]);
9112 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9113 branch_regs[i-1].isconst=0;
9114 branch_regs[i-1].wasconst=0;
9115 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9116 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9119 // Alloc the delay slot in case the branch is taken
9120 if((opcode2[i-1]&0x1E)==2) // BLTZL/BGEZL
9122 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9123 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9124 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9125 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9126 alloc_cc(&branch_regs[i-1],i);
9127 dirty_reg(&branch_regs[i-1],CCREG);
9128 delayslot_alloc(&branch_regs[i-1],i);
9129 branch_regs[i-1].isconst=0;
9130 alloc_reg(¤t,i,CCREG); // Not taken path
9131 dirty_reg(¤t,CCREG);
9132 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9134 // FIXME: BLTZAL/BGEZAL
9135 if(opcode2[i-1]&0x10) { // BxxZAL
9136 alloc_reg(&branch_regs[i-1],i-1,31);
9137 dirty_reg(&branch_regs[i-1],31);
9138 branch_regs[i-1].is32|=1LL<<31;
9142 if(likely[i-1]==0) // BC1F/BC1T
9144 alloc_cc(¤t,i-1);
9145 dirty_reg(¤t,CCREG);
9146 if(itype[i]==FCOMP) {
9147 // The delay slot overwrote the branch condition
9148 // Delay slot goes after the test (in order)
9149 delayslot_alloc(¤t,i);
9154 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9155 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9156 // Alloc the branch condition register
9157 alloc_reg(¤t,i-1,FSREG);
9159 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9160 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9164 // Alloc the delay slot in case the branch is taken
9165 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9166 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9167 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9168 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9169 alloc_cc(&branch_regs[i-1],i);
9170 dirty_reg(&branch_regs[i-1],CCREG);
9171 delayslot_alloc(&branch_regs[i-1],i);
9172 branch_regs[i-1].isconst=0;
9173 alloc_reg(¤t,i,CCREG); // Not taken path
9174 dirty_reg(¤t,CCREG);
9175 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9180 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
9182 if(rt1[i-1]==31) // JAL/JALR
9184 // Subroutine call will return here, don't alloc any registers
9187 clear_all_regs(current.regmap);
9188 alloc_reg(¤t,i,CCREG);
9189 dirty_reg(¤t,CCREG);
9193 // Internal branch will jump here, match registers to caller
9194 current.is32=0x3FFFFFFFFLL;
9196 clear_all_regs(current.regmap);
9197 alloc_reg(¤t,i,CCREG);
9198 dirty_reg(¤t,CCREG);
9201 if(ba[j]==start+i*4+4) {
9202 memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
9203 current.is32=branch_regs[j].is32;
9204 current.dirty=branch_regs[j].dirty;
9209 if(ba[j]==start+i*4+4) {
9210 for(hr=0;hr<HOST_REGS;hr++) {
9211 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
9212 current.regmap[hr]=-1;
9214 current.is32&=branch_regs[j].is32;
9215 current.dirty&=branch_regs[j].dirty;
9224 // Count cycles in between branches
9226 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP||itype[i]==SYSCALL))
9235 flush_dirty_uppers(¤t);
9237 regs[i].is32=current.is32;
9238 regs[i].dirty=current.dirty;
9239 regs[i].isconst=current.isconst;
9240 memcpy(constmap[i],current.constmap,sizeof(current.constmap));
9242 for(hr=0;hr<HOST_REGS;hr++) {
9243 if(hr!=EXCLUDE_REG&®s[i].regmap[hr]>=0) {
9244 if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
9245 regs[i].wasconst&=~(1<<hr);
9249 if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
9252 /* Pass 4 - Cull unused host registers */
9256 for (i=slen-1;i>=0;i--)
9259 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9261 if(ba[i]<start || ba[i]>=(start+slen*4))
9263 // Branch out of this block, don't need anything
9269 // Need whatever matches the target
9271 int t=(ba[i]-start)>>2;
9272 for(hr=0;hr<HOST_REGS;hr++)
9274 if(regs[i].regmap_entry[hr]>=0) {
9275 if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
9279 // Conditional branch may need registers for following instructions
9280 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9283 nr|=needed_reg[i+2];
9284 for(hr=0;hr<HOST_REGS;hr++)
9286 if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
9287 //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) DebugMessage(M64MSG_VERBOSE, "%x-bogus(%d=%d)",start+i*4,hr,regmap_entry[i+2][hr]);
9291 // Don't need stuff which is overwritten
9292 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9293 if(regs[i].regmap[hr]<0) nr&=~(1<<hr); //moved...
9294 // Merge in delay slot
9295 for(hr=0;hr<HOST_REGS;hr++)
9297 // Don't need stuff which is overwritten
9298 /* if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr); //*SEB* Moved here
9299 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);*/
9302 // These are overwritten unless the branch is "likely"
9303 // and the delay slot is nullified if not taken
9304 if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9305 if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9307 if(us1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9308 if(us2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9309 if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9310 if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9311 if(us1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9312 if(us2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9313 if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9314 if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9315 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1)) {
9316 if(dep1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9317 if(dep2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9319 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1)) {
9320 if(dep1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9321 if(dep2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9323 if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39) {
9324 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9325 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9329 else if(itype[i]==SYSCALL)
9331 // SYSCALL instruction (software interrupt)
9334 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
9336 // ERET instruction (return from interrupt)
9342 for(hr=0;hr<HOST_REGS;hr++) {
9343 if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
9344 if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
9345 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9346 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9350 for(hr=0;hr<HOST_REGS;hr++)
9352 // Overwritten registers are not needed
9353 if(rt1[i]&&rt1[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9354 if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9355 if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9356 // Source registers are needed
9357 if(us1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9358 if(us2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9359 if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr;
9360 if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr;
9361 if(us1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9362 if(us2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9363 if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9364 if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9365 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1)) {
9366 if(dep1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9367 if(dep1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9369 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1)) {
9370 if(dep2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9371 if(dep2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9373 if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39) {
9374 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9375 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9377 // Don't store a register immediately after writing it,
9378 // may prevent dual-issue.
9379 // But do so if this is a branch target, otherwise we
9380 // might have to load the register before the branch.
9381 if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) {
9382 if((regmap_pre[i][hr]>0&®map_pre[i][hr]<64&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1)) ||
9383 (regmap_pre[i][hr]>64&&!((unneeded_reg_upper[i]>>(regmap_pre[i][hr]&63))&1)) ) {
9384 if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9385 if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9387 if((regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1)) ||
9388 (regs[i].regmap_entry[hr]>64&&!((unneeded_reg_upper[i]>>(regs[i].regmap_entry[hr]&63))&1)) ) {
9389 if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9390 if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9394 // Cycle count is needed at branches. Assume it is needed at the target too.
9395 if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==FJUMP||itype[i]==SPAN) {
9396 if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9397 if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9402 // Deallocate unneeded registers
9403 for(hr=0;hr<HOST_REGS;hr++)
9406 if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
9407 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9408 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9409 (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG)
9411 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9414 regs[i].regmap[hr]=-1;
9415 regs[i].isconst&=~(1<<hr);
9417 regmap_pre[i+2][hr]=-1;
9418 regs[i+2].wasconst&=~(1<<hr);
9423 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9425 int d1=0,d2=0,map=0,temp=0;
9426 if(get_reg(regs[i].regmap,rt1[i+1]|64)>=0||get_reg(branch_regs[i].regmap,rt1[i+1]|64)>=0)
9432 if(itype[i+1]==LOAD || itype[i+1]==LOADLR ||
9433 itype[i+1]==STORE || itype[i+1]==STORELR ||
9437 if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39) {
9440 if(itype[i+1]==LOADLR || itype[i+1]==STORELR ||
9443 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9444 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9445 (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] &&
9446 (regs[i].regmap[hr]^64)!=us1[i+1] && (regs[i].regmap[hr]^64)!=us2[i+1] &&
9447 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9448 regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] &&
9449 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
9450 regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
9451 regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
9452 regs[i].regmap[hr]!=map )
9454 regs[i].regmap[hr]=-1;
9455 regs[i].isconst&=~(1<<hr);
9456 if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] &&
9457 (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] &&
9458 (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] &&
9459 (branch_regs[i].regmap[hr]^64)!=us1[i+1] && (branch_regs[i].regmap[hr]^64)!=us2[i+1] &&
9460 (branch_regs[i].regmap[hr]^64)!=d1 && (branch_regs[i].regmap[hr]^64)!=d2 &&
9461 branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] &&
9462 (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
9463 branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
9464 branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
9465 branch_regs[i].regmap[hr]!=map)
9467 branch_regs[i].regmap[hr]=-1;
9468 branch_regs[i].regmap_entry[hr]=-1;
9469 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9471 if(!likely[i]&&i<slen-2) {
9472 regmap_pre[i+2][hr]=-1;
9473 regs[i+2].wasconst&=~(1<<hr);
9484 int d1=0,d2=0,map=-1,temp=-1;
9485 if(get_reg(regs[i].regmap,rt1[i]|64)>=0)
9491 if(itype[i]==LOAD || itype[i]==LOADLR ||
9492 itype[i]==STORE || itype[i]==STORELR ||
9495 } else if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39) {
9498 if(itype[i]==LOADLR || itype[i]==STORELR ||
9501 if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9502 (regs[i].regmap[hr]^64)!=us1[i] && (regs[i].regmap[hr]^64)!=us2[i] &&
9503 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9504 regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] &&
9505 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map &&
9506 (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG))
9508 if(i<slen-1&&!is_ds[i]) {
9509 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]!=-1)
9510 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
9511 if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
9513 DebugMessage(M64MSG_VERBOSE, "fail: %x (%d %d!=%d)",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
9514 assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
9516 regmap_pre[i+1][hr]=-1;
9517 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
9518 regs[i+1].wasconst&=~(1<<hr);
9520 regs[i].regmap[hr]=-1;
9521 regs[i].isconst&=~(1<<hr);
9529 /* Pass 5 - Pre-allocate registers */
9531 // If a register is allocated during a loop, try to allocate it for the
9532 // entire loop, if possible. This avoids loading/storing registers
9533 // inside of the loop.
9535 signed char f_regmap[HOST_REGS];
9536 clear_all_regs(f_regmap);
9537 for(i=0;i<slen-1;i++)
9539 if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9541 if(ba[i]>=start && ba[i]<(start+i*4))
9542 if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
9543 ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
9544 ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
9545 ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
9546 ||itype[i+1]==FCOMP||itype[i+1]==FCONV)
9548 int t=(ba[i]-start)>>2;
9549 if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots
9550 if(t<2||(itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||rt1[t-2]!=31) // call/ret assumes no registers allocated
9551 for(hr=0;hr<HOST_REGS;hr++)
9553 if(regs[i].regmap[hr]>64) {
9554 if(!((regs[i].dirty>>hr)&1))
9555 f_regmap[hr]=regs[i].regmap[hr];
9556 else f_regmap[hr]=-1;
9558 else if(regs[i].regmap[hr]>=0) {
9559 if(f_regmap[hr]!=regs[i].regmap[hr]) {
9560 // dealloc old register
9562 for(n=0;n<HOST_REGS;n++)
9564 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
9566 // and alloc new one
9567 f_regmap[hr]=regs[i].regmap[hr];
9570 if(branch_regs[i].regmap[hr]>64) {
9571 if(!((branch_regs[i].dirty>>hr)&1))
9572 f_regmap[hr]=branch_regs[i].regmap[hr];
9573 else f_regmap[hr]=-1;
9575 else if(branch_regs[i].regmap[hr]>=0) {
9576 if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
9577 // dealloc old register
9579 for(n=0;n<HOST_REGS;n++)
9581 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
9583 // and alloc new one
9584 f_regmap[hr]=branch_regs[i].regmap[hr];
9588 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
9589 f_regmap[hr]=branch_regs[i].regmap[hr];
9591 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
9592 f_regmap[hr]=branch_regs[i].regmap[hr];
9594 // Avoid dirty->clean transition
9595 #ifdef DESTRUCTIVE_WRITEBACK
9596 if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
9598 // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
9599 // case above, however it's always a good idea. We can't hoist the
9600 // load if the register was already allocated, so there's no point
9601 // wasting time analyzing most of these cases. It only "succeeds"
9602 // when the mapping was different and the load can be replaced with
9603 // a mov, which is of negligible benefit. So such cases are
9605 if(f_regmap[hr]>0) {
9606 if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
9610 //DebugMessage(M64MSG_VERBOSE, "Test %x -> %x, %x %d/%d",start+i*4,ba[i],start+j*4,hr,r);
9611 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
9612 if(r>63&&((unneeded_reg_upper[j]>>(r&63))&1)) break;
9614 // NB This can exclude the case where the upper-half
9615 // register is lower numbered than the lower-half
9616 // register. Not sure if it's worth fixing...
9617 if(get_reg(regs[j].regmap,r&63)<0) break;
9618 if(get_reg(regs[j].regmap_entry,r&63)<0) break;
9619 if(regs[j].is32&(1LL<<(r&63))) break;
9621 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
9622 //DebugMessage(M64MSG_VERBOSE, "Hit %x -> %x, %x %d/%d",start+i*4,ba[i],start+j*4,hr,r);
9624 if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
9625 if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
9627 if(get_reg(regs[i].regmap,r&63)<0) break;
9628 if(get_reg(branch_regs[i].regmap,r&63)<0) break;
9631 while(k>1&®s[k-1].regmap[hr]==-1) {
9632 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
9633 //DebugMessage(M64MSG_VERBOSE, "no free regs for store %x",start+(k-1)*4);
9636 if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
9637 //DebugMessage(M64MSG_VERBOSE, "no-match due to different register");
9640 if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP||itype[k-2]==FJUMP) {
9641 //DebugMessage(M64MSG_VERBOSE, "no-match due to branch");
9644 // call/ret fast path assumes no registers allocated
9645 if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)&&rt1[k-3]==31) {
9649 // NB This can exclude the case where the upper-half
9650 // register is lower numbered than the lower-half
9651 // register. Not sure if it's worth fixing...
9652 if(get_reg(regs[k-1].regmap,r&63)<0) break;
9653 if(regs[k-1].is32&(1LL<<(r&63))) break;
9658 if((regs[k].is32&(1LL<<f_regmap[hr]))!=
9659 (regs[i+2].was32&(1LL<<f_regmap[hr]))) {
9660 //DebugMessage(M64MSG_VERBOSE, "bad match after branch");
9664 if(regs[k-1].regmap[hr]==f_regmap[hr]&®map_pre[k][hr]==f_regmap[hr]) {
9665 //DebugMessage(M64MSG_VERBOSE, "Extend r%d, %x ->",hr,start+k*4);
9667 regs[k].regmap_entry[hr]=f_regmap[hr];
9668 regs[k].regmap[hr]=f_regmap[hr];
9669 regmap_pre[k+1][hr]=f_regmap[hr];
9670 regs[k].wasdirty&=~(1<<hr);
9671 regs[k].dirty&=~(1<<hr);
9672 regs[k].wasdirty|=(1<<hr)®s[k-1].dirty;
9673 regs[k].dirty|=(1<<hr)®s[k].wasdirty;
9674 regs[k].wasconst&=~(1<<hr);
9675 regs[k].isconst&=~(1<<hr);
9680 //DebugMessage(M64MSG_VERBOSE, "Fail Extend r%d, %x ->",hr,start+k*4);
9683 assert(regs[i-1].regmap[hr]==f_regmap[hr]);
9684 if(regs[i-1].regmap[hr]==f_regmap[hr]&®map_pre[i][hr]==f_regmap[hr]) {
9685 //DebugMessage(M64MSG_VERBOSE, "OK fill %x (r%d)",start+i*4,hr);
9686 regs[i].regmap_entry[hr]=f_regmap[hr];
9687 regs[i].regmap[hr]=f_regmap[hr];
9688 regs[i].wasdirty&=~(1<<hr);
9689 regs[i].dirty&=~(1<<hr);
9690 regs[i].wasdirty|=(1<<hr)®s[i-1].dirty;
9691 regs[i].dirty|=(1<<hr)®s[i-1].dirty;
9692 regs[i].wasconst&=~(1<<hr);
9693 regs[i].isconst&=~(1<<hr);
9694 branch_regs[i].regmap_entry[hr]=f_regmap[hr];
9695 branch_regs[i].wasdirty&=~(1<<hr);
9696 branch_regs[i].wasdirty|=(1<<hr)®s[i].dirty;
9697 branch_regs[i].regmap[hr]=f_regmap[hr];
9698 branch_regs[i].dirty&=~(1<<hr);
9699 branch_regs[i].dirty|=(1<<hr)®s[i].dirty;
9700 branch_regs[i].wasconst&=~(1<<hr);
9701 branch_regs[i].isconst&=~(1<<hr);
9702 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
9703 regmap_pre[i+2][hr]=f_regmap[hr];
9704 regs[i+2].wasdirty&=~(1<<hr);
9705 regs[i+2].wasdirty|=(1<<hr)®s[i].dirty;
9706 assert((branch_regs[i].is32&(1LL<<f_regmap[hr]))==
9707 (regs[i+2].was32&(1LL<<f_regmap[hr])));
9712 // Alloc register clean at beginning of loop,
9713 // but may dirty it in pass 6
9714 regs[k].regmap_entry[hr]=f_regmap[hr];
9715 regs[k].regmap[hr]=f_regmap[hr];
9716 regs[k].dirty&=~(1<<hr);
9717 regs[k].wasconst&=~(1<<hr);
9718 regs[k].isconst&=~(1<<hr);
9719 if(itype[k]==UJUMP||itype[k]==RJUMP||itype[k]==CJUMP||itype[k]==SJUMP||itype[k]==FJUMP) {
9720 branch_regs[k].regmap_entry[hr]=f_regmap[hr];
9721 branch_regs[k].regmap[hr]=f_regmap[hr];
9722 branch_regs[k].dirty&=~(1<<hr);
9723 branch_regs[k].wasconst&=~(1<<hr);
9724 branch_regs[k].isconst&=~(1<<hr);
9725 if(itype[k]!=RJUMP&&itype[k]!=UJUMP&&(source[k]>>16)!=0x1000) {
9726 regmap_pre[k+2][hr]=f_regmap[hr];
9727 regs[k+2].wasdirty&=~(1<<hr);
9728 assert((branch_regs[k].is32&(1LL<<f_regmap[hr]))==
9729 (regs[k+2].was32&(1LL<<f_regmap[hr])));
9734 regmap_pre[k+1][hr]=f_regmap[hr];
9735 regs[k+1].wasdirty&=~(1<<hr);
9738 if(regs[j].regmap[hr]==f_regmap[hr])
9739 regs[j].regmap_entry[hr]=f_regmap[hr];
9743 if(regs[j].regmap[hr]>=0)
9745 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
9746 //DebugMessage(M64MSG_VERBOSE, "no-match due to different register");
9749 if((regs[j+1].is32&(1LL<<f_regmap[hr]))!=(regs[j].is32&(1LL<<f_regmap[hr]))) {
9750 //DebugMessage(M64MSG_VERBOSE, "32/64 mismatch %x %d",start+j*4,hr);
9753 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
9755 // Stop on unconditional branch
9758 if(itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP)
9761 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
9764 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
9767 if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
9768 //DebugMessage(M64MSG_VERBOSE, "no-match due to different register (branch)");
9772 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
9773 //DebugMessage(M64MSG_VERBOSE, "No free regs for store %x",start+j*4);
9776 if(f_regmap[hr]>=64) {
9777 if(regs[j].is32&(1LL<<(f_regmap[hr]&63))) {
9782 if(get_reg(regs[j].regmap,f_regmap[hr]&63)<0) {
9793 // Non branch or undetermined branch target
9794 for(hr=0;hr<HOST_REGS;hr++)
9796 if(hr!=EXCLUDE_REG) {
9797 if(regs[i].regmap[hr]>64) {
9798 if(!((regs[i].dirty>>hr)&1))
9799 f_regmap[hr]=regs[i].regmap[hr];
9801 else if(regs[i].regmap[hr]>=0) {
9802 if(f_regmap[hr]!=regs[i].regmap[hr]) {
9803 // dealloc old register
9805 for(n=0;n<HOST_REGS;n++)
9807 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
9809 // and alloc new one
9810 f_regmap[hr]=regs[i].regmap[hr];
9815 // Try to restore cycle count at branch targets
9817 for(j=i;j<slen-1;j++) {
9818 if(regs[j].regmap[HOST_CCREG]!=-1) break;
9819 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
9820 //DebugMessage(M64MSG_VERBOSE, "no free regs for store %x",start+j*4);
9824 if(regs[j].regmap[HOST_CCREG]==CCREG) {
9826 //DebugMessage(M64MSG_VERBOSE, "Extend CC, %x -> %x",start+k*4,start+j*4);
9828 regs[k].regmap_entry[HOST_CCREG]=CCREG;
9829 regs[k].regmap[HOST_CCREG]=CCREG;
9830 regmap_pre[k+1][HOST_CCREG]=CCREG;
9831 regs[k+1].wasdirty|=1<<HOST_CCREG;
9832 regs[k].dirty|=1<<HOST_CCREG;
9833 regs[k].wasconst&=~(1<<HOST_CCREG);
9834 regs[k].isconst&=~(1<<HOST_CCREG);
9837 regs[j].regmap_entry[HOST_CCREG]=CCREG;
9839 // Work backwards from the branch target
9840 if(j>i&&f_regmap[HOST_CCREG]==CCREG)
9842 //DebugMessage(M64MSG_VERBOSE, "Extend backwards");
9845 while(regs[k-1].regmap[HOST_CCREG]==-1) {
9846 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
9847 //DebugMessage(M64MSG_VERBOSE, "no free regs for store %x",start+(k-1)*4);
9852 if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
9853 //DebugMessage(M64MSG_VERBOSE, "Extend CC, %x ->",start+k*4);
9855 regs[k].regmap_entry[HOST_CCREG]=CCREG;
9856 regs[k].regmap[HOST_CCREG]=CCREG;
9857 regmap_pre[k+1][HOST_CCREG]=CCREG;
9858 regs[k+1].wasdirty|=1<<HOST_CCREG;
9859 regs[k].dirty|=1<<HOST_CCREG;
9860 regs[k].wasconst&=~(1<<HOST_CCREG);
9861 regs[k].isconst&=~(1<<HOST_CCREG);
9866 //DebugMessage(M64MSG_VERBOSE, "Fail Extend CC, %x ->",start+k*4);
9870 if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&&
9871 itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&&
9872 itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1&&itype[i]!=FLOAT&&
9873 itype[i]!=FCONV&&itype[i]!=FCOMP)
9875 memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
9880 // Cache memory offset or tlb map pointer if a register is available
9881 #ifndef HOST_IMM_ADDR32
9886 int earliest_available[HOST_REGS];
9887 int loop_start[HOST_REGS];
9888 int score[HOST_REGS];
9890 int reg=using_tlb?MMREG:ROREG;
9893 for(hr=0;hr<HOST_REGS;hr++) {
9894 score[hr]=0;earliest_available[hr]=0;
9895 loop_start[hr]=MAXBLOCK;
9897 for(i=0;i<slen-1;i++)
9899 // Can't do anything if no registers are available
9900 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i]) {
9901 for(hr=0;hr<HOST_REGS;hr++) {
9902 score[hr]=0;earliest_available[hr]=i+1;
9903 loop_start[hr]=MAXBLOCK;
9906 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
9908 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1]) {
9909 for(hr=0;hr<HOST_REGS;hr++) {
9910 score[hr]=0;earliest_available[hr]=i+1;
9911 loop_start[hr]=MAXBLOCK;
9915 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1]) {
9916 for(hr=0;hr<HOST_REGS;hr++) {
9917 score[hr]=0;earliest_available[hr]=i+1;
9918 loop_start[hr]=MAXBLOCK;
9923 // Mark unavailable registers
9924 for(hr=0;hr<HOST_REGS;hr++) {
9925 if(regs[i].regmap[hr]>=0) {
9926 score[hr]=0;earliest_available[hr]=i+1;
9927 loop_start[hr]=MAXBLOCK;
9929 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
9930 if(branch_regs[i].regmap[hr]>=0) {
9931 score[hr]=0;earliest_available[hr]=i+2;
9932 loop_start[hr]=MAXBLOCK;
9936 // No register allocations after unconditional jumps
9937 if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
9939 for(hr=0;hr<HOST_REGS;hr++) {
9940 score[hr]=0;earliest_available[hr]=i+2;
9941 loop_start[hr]=MAXBLOCK;
9943 i++; // Skip delay slot too
9944 //DebugMessage(M64MSG_VERBOSE, "skip delay slot: %x",start+i*4);
9948 if(itype[i]==LOAD||itype[i]==LOADLR||
9949 itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS) {
9950 for(hr=0;hr<HOST_REGS;hr++) {
9951 if(hr!=EXCLUDE_REG) {
9953 for(j=i;j<slen-1;j++) {
9954 if(regs[j].regmap[hr]>=0) break;
9955 if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
9956 if(branch_regs[j].regmap[hr]>=0) break;
9958 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1]) break;
9960 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1]) break;
9963 else if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) break;
9964 if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
9965 int t=(ba[j]-start)>>2;
9966 if(t<j&&t>=earliest_available[hr]) {
9967 if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) { // call/ret assumes no registers allocated
9968 // Score a point for hoisting loop invariant
9969 if(t<loop_start[hr]) loop_start[hr]=t;
9970 //DebugMessage(M64MSG_VERBOSE, "set loop_start: i=%x j=%x (%x)",start+i*4,start+j*4,start+t*4);
9976 if(regs[t].regmap[hr]==reg) {
9977 // Score a point if the branch target matches this register
9982 if(itype[j+1]==LOAD||itype[j+1]==LOADLR||
9983 itype[j+1]==STORE||itype[j+1]==STORELR||itype[j+1]==C1LS) {
9988 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
9990 // Stop on unconditional branch
9994 if(itype[j]==LOAD||itype[j]==LOADLR||
9995 itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS) {
10002 // Find highest score and allocate that register
10004 for(hr=0;hr<HOST_REGS;hr++) {
10005 if(hr!=EXCLUDE_REG) {
10006 if(score[hr]>score[maxscore]) {
10008 //DebugMessage(M64MSG_VERBOSE, "highest score: %d %d (%x->%x)",score[hr],hr,start+i*4,start+end[hr]*4);
10012 if(score[maxscore]>1)
10014 if(i<loop_start[maxscore]) loop_start[maxscore]=i;
10015 for(j=loop_start[maxscore];j<slen&&j<=end[maxscore];j++) {
10016 //if(regs[j].regmap[maxscore]>=0) {DebugMessage(M64MSG_ERROR, "oops: %x %x was %d=%d",loop_start[maxscore]*4+start,j*4+start,maxscore,regs[j].regmap[maxscore]);}
10017 assert(regs[j].regmap[maxscore]<0);
10018 if(j>loop_start[maxscore]) regs[j].regmap_entry[maxscore]=reg;
10019 regs[j].regmap[maxscore]=reg;
10020 regs[j].dirty&=~(1<<maxscore);
10021 regs[j].wasconst&=~(1<<maxscore);
10022 regs[j].isconst&=~(1<<maxscore);
10023 if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10024 branch_regs[j].regmap[maxscore]=reg;
10025 branch_regs[j].wasdirty&=~(1<<maxscore);
10026 branch_regs[j].dirty&=~(1<<maxscore);
10027 branch_regs[j].wasconst&=~(1<<maxscore);
10028 branch_regs[j].isconst&=~(1<<maxscore);
10029 if(itype[j]!=RJUMP&&itype[j]!=UJUMP&&(source[j]>>16)!=0x1000) {
10030 regmap_pre[j+2][maxscore]=reg;
10031 regs[j+2].wasdirty&=~(1<<maxscore);
10033 // loop optimization (loop_preload)
10034 int t=(ba[j]-start)>>2;
10035 if(t==loop_start[maxscore]) {
10036 if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) // call/ret assumes no registers allocated
10037 regs[t].regmap_entry[maxscore]=reg;
10042 if(j<1||(itype[j-1]!=RJUMP&&itype[j-1]!=UJUMP&&itype[j-1]!=CJUMP&&itype[j-1]!=SJUMP&&itype[j-1]!=FJUMP)) {
10043 regmap_pre[j+1][maxscore]=reg;
10044 regs[j+1].wasdirty&=~(1<<maxscore);
10049 if(itype[j-1]==RJUMP||itype[j-1]==UJUMP||itype[j-1]==CJUMP||itype[j-1]==SJUMP||itype[j-1]==FJUMP) i++; // skip delay slot
10050 for(hr=0;hr<HOST_REGS;hr++) {
10051 score[hr]=0;earliest_available[hr]=i+i;
10052 loop_start[hr]=MAXBLOCK;
10060 // This allocates registers (if possible) one instruction prior
10061 // to use, which can avoid a load-use penalty on certain CPUs.
10062 for(i=0;i<slen-1;i++)
10064 if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP))
10068 if(itype[i]==ALU||itype[i]==MOV||itype[i]==LOAD||itype[i]==SHIFTIMM||itype[i]==IMM16||(itype[i]==COP1&&opcode2[i]<3))
10071 if((hr=get_reg(regs[i+1].regmap,rs1[i+1]))>=0)
10073 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10075 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10076 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10077 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10078 regs[i].isconst&=~(1<<hr);
10079 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10080 constmap[i][hr]=constmap[i+1][hr];
10081 regs[i+1].wasdirty&=~(1<<hr);
10082 regs[i].dirty&=~(1<<hr);
10087 if((hr=get_reg(regs[i+1].regmap,rs2[i+1]))>=0)
10089 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10091 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10092 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10093 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10094 regs[i].isconst&=~(1<<hr);
10095 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10096 constmap[i][hr]=constmap[i+1][hr];
10097 regs[i+1].wasdirty&=~(1<<hr);
10098 regs[i].dirty&=~(1<<hr);
10102 // Preload target address for load instruction (non-constant)
10103 if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10104 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10106 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10108 regs[i].regmap[hr]=rs1[i+1];
10109 regmap_pre[i+1][hr]=rs1[i+1];
10110 regs[i+1].regmap_entry[hr]=rs1[i+1];
10111 regs[i].isconst&=~(1<<hr);
10112 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10113 constmap[i][hr]=constmap[i+1][hr];
10114 regs[i+1].wasdirty&=~(1<<hr);
10115 regs[i].dirty&=~(1<<hr);
10119 // Load source into target register
10120 if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10121 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10123 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10125 regs[i].regmap[hr]=rs1[i+1];
10126 regmap_pre[i+1][hr]=rs1[i+1];
10127 regs[i+1].regmap_entry[hr]=rs1[i+1];
10128 regs[i].isconst&=~(1<<hr);
10129 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10130 constmap[i][hr]=constmap[i+1][hr];
10131 regs[i+1].wasdirty&=~(1<<hr);
10132 regs[i].dirty&=~(1<<hr);
10136 // Preload map address
10137 #ifndef HOST_IMM_ADDR32
10138 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS) {
10139 hr=get_reg(regs[i+1].regmap,TLREG);
10141 int sr=get_reg(regs[i+1].regmap,rs1[i+1]);
10142 if(sr>=0&&((regs[i+1].wasconst>>sr)&1)) {
10144 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10146 regs[i].regmap[hr]=MGEN1+((i+1)&1);
10147 regmap_pre[i+1][hr]=MGEN1+((i+1)&1);
10148 regs[i+1].regmap_entry[hr]=MGEN1+((i+1)&1);
10149 regs[i].isconst&=~(1<<hr);
10150 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10151 constmap[i][hr]=constmap[i+1][hr];
10152 regs[i+1].wasdirty&=~(1<<hr);
10153 regs[i].dirty&=~(1<<hr);
10155 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10157 // move it to another register
10158 regs[i+1].regmap[hr]=-1;
10159 regmap_pre[i+2][hr]=-1;
10160 regs[i+1].regmap[nr]=TLREG;
10161 regmap_pre[i+2][nr]=TLREG;
10162 regs[i].regmap[nr]=MGEN1+((i+1)&1);
10163 regmap_pre[i+1][nr]=MGEN1+((i+1)&1);
10164 regs[i+1].regmap_entry[nr]=MGEN1+((i+1)&1);
10165 regs[i].isconst&=~(1<<nr);
10166 regs[i+1].isconst&=~(1<<nr);
10167 regs[i].dirty&=~(1<<nr);
10168 regs[i+1].wasdirty&=~(1<<nr);
10169 regs[i+1].dirty&=~(1<<nr);
10170 regs[i+2].wasdirty&=~(1<<nr);
10176 // Address for store instruction (non-constant)
10177 if(itype[i+1]==STORE||itype[i+1]==STORELR||opcode[i+1]==0x39||opcode[i+1]==0x3D) { // SB/SH/SW/SD/SWC1/SDC1
10178 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10179 hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
10180 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10181 else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
10183 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10185 regs[i].regmap[hr]=rs1[i+1];
10186 regmap_pre[i+1][hr]=rs1[i+1];
10187 regs[i+1].regmap_entry[hr]=rs1[i+1];
10188 regs[i].isconst&=~(1<<hr);
10189 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10190 constmap[i][hr]=constmap[i+1][hr];
10191 regs[i+1].wasdirty&=~(1<<hr);
10192 regs[i].dirty&=~(1<<hr);
10196 if(itype[i+1]==LOADLR||opcode[i+1]==0x31||opcode[i+1]==0x35) { // LWC1/LDC1
10197 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10199 hr=get_reg(regs[i+1].regmap,FTEMP);
10201 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10203 regs[i].regmap[hr]=rs1[i+1];
10204 regmap_pre[i+1][hr]=rs1[i+1];
10205 regs[i+1].regmap_entry[hr]=rs1[i+1];
10206 regs[i].isconst&=~(1<<hr);
10207 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10208 constmap[i][hr]=constmap[i+1][hr];
10209 regs[i+1].wasdirty&=~(1<<hr);
10210 regs[i].dirty&=~(1<<hr);
10212 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10214 // move it to another register
10215 regs[i+1].regmap[hr]=-1;
10216 regmap_pre[i+2][hr]=-1;
10217 regs[i+1].regmap[nr]=FTEMP;
10218 regmap_pre[i+2][nr]=FTEMP;
10219 regs[i].regmap[nr]=rs1[i+1];
10220 regmap_pre[i+1][nr]=rs1[i+1];
10221 regs[i+1].regmap_entry[nr]=rs1[i+1];
10222 regs[i].isconst&=~(1<<nr);
10223 regs[i+1].isconst&=~(1<<nr);
10224 regs[i].dirty&=~(1<<nr);
10225 regs[i+1].wasdirty&=~(1<<nr);
10226 regs[i+1].dirty&=~(1<<nr);
10227 regs[i+2].wasdirty&=~(1<<nr);
10231 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS*/) {
10232 if(itype[i+1]==LOAD)
10233 hr=get_reg(regs[i+1].regmap,rt1[i+1]);
10234 if(itype[i+1]==LOADLR||opcode[i+1]==0x31||opcode[i+1]==0x35) // LWC1/LDC1
10235 hr=get_reg(regs[i+1].regmap,FTEMP);
10236 if(itype[i+1]==STORE||itype[i+1]==STORELR||opcode[i+1]==0x39||opcode[i+1]==0x3D) { // SWC1/SDC1
10237 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
10238 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10240 if(hr>=0&®s[i].regmap[hr]<0) {
10241 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
10242 if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
10243 regs[i].regmap[hr]=AGEN1+((i+1)&1);
10244 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
10245 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
10246 regs[i].isconst&=~(1<<hr);
10247 regs[i+1].wasdirty&=~(1<<hr);
10248 regs[i].dirty&=~(1<<hr);
10257 /* Pass 6 - Optimize clean/dirty state */
10258 clean_registers(0,slen-1,1);
10260 /* Pass 7 - Identify 32-bit registers */
10266 for (i=slen-1;i>=0;i--)
10269 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10271 if(ba[i]<start || ba[i]>=(start+slen*4))
10273 // Branch out of this block, don't need anything
10279 // Need whatever matches the target
10280 // (and doesn't get overwritten by the delay slot instruction)
10282 int t=(ba[i]-start)>>2;
10283 if(ba[i]>start+i*4) {
10285 if(!(requires_32bit[t]&~regs[i].was32))
10286 r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10289 //if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
10290 // r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10291 if(!(pr32[t]&~regs[i].was32))
10292 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10295 // Conditional branch may need registers for following instructions
10296 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10299 r32|=requires_32bit[i+2];
10300 r32&=regs[i].was32;
10301 // Mark this address as a branch target since it may be called
10302 // upon return from interrupt
10306 // Merge in delay slot
10308 // These are overwritten unless the branch is "likely"
10309 // and the delay slot is nullified if not taken
10310 r32&=~(1LL<<rt1[i+1]);
10311 r32&=~(1LL<<rt2[i+1]);
10313 // Assume these are needed (delay slot)
10316 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
10320 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
10322 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
10324 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
10326 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
10328 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
10331 else if(itype[i]==SYSCALL)
10333 // SYSCALL instruction (software interrupt)
10336 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
10338 // ERET instruction (return from interrupt)
10342 r32&=~(1LL<<rt1[i]);
10343 r32&=~(1LL<<rt2[i]);
10346 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
10350 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
10352 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
10354 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
10356 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
10358 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
10360 requires_32bit[i]=r32;
10362 // Dirty registers which are 32-bit, require 32-bit input
10363 // as they will be written as 32-bit values
10364 for(hr=0;hr<HOST_REGS;hr++)
10366 if(regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64) {
10367 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
10368 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
10369 requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
10373 //requires_32bit[i]=is32[i]&~unneeded_reg_upper[i]; // DEBUG
10376 if(itype[slen-1]==SPAN) {
10377 bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
10380 /* Debug/disassembly */
10381 // if((void*)assem_debug==(void*)printf)
10382 #if defined( ASSEM_DEBUG )
10383 for(i=0;i<slen;i++)
10385 DebugMessage(M64MSG_VERBOSE, "U:");
10387 for(r=1;r<=CCREG;r++) {
10388 if((unneeded_reg[i]>>r)&1) {
10389 if(r==HIREG) DebugMessage(M64MSG_VERBOSE, " HI");
10390 else if(r==LOREG) DebugMessage(M64MSG_VERBOSE, " LO");
10391 else DebugMessage(M64MSG_VERBOSE, " r%d",r);
10394 DebugMessage(M64MSG_VERBOSE, " UU:");
10395 for(r=1;r<=CCREG;r++) {
10396 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
10397 if(r==HIREG) DebugMessage(M64MSG_VERBOSE, " HI");
10398 else if(r==LOREG) DebugMessage(M64MSG_VERBOSE, " LO");
10399 else DebugMessage(M64MSG_VERBOSE, " r%d",r);
10402 DebugMessage(M64MSG_VERBOSE, " 32:");
10403 for(r=0;r<=CCREG;r++) {
10404 //if(((is32[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10405 if((regs[i].was32>>r)&1) {
10406 if(r==CCREG) DebugMessage(M64MSG_VERBOSE, " CC");
10407 else if(r==HIREG) DebugMessage(M64MSG_VERBOSE, " HI");
10408 else if(r==LOREG) DebugMessage(M64MSG_VERBOSE, " LO");
10409 else DebugMessage(M64MSG_VERBOSE, " r%d",r);
10412 #if NEW_DYNAREC == NEW_DYNAREC_X86
10413 DebugMessage(M64MSG_VERBOSE, "pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
10415 #if NEW_DYNAREC == NEW_DYNAREC_ARM
10416 DebugMessage(M64MSG_VERBOSE, "pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
10418 DebugMessage(M64MSG_VERBOSE, "needs: ");
10419 if(needed_reg[i]&1) DebugMessage(M64MSG_VERBOSE, "eax ");
10420 if((needed_reg[i]>>1)&1) DebugMessage(M64MSG_VERBOSE, "ecx ");
10421 if((needed_reg[i]>>2)&1) DebugMessage(M64MSG_VERBOSE, "edx ");
10422 if((needed_reg[i]>>3)&1) DebugMessage(M64MSG_VERBOSE, "ebx ");
10423 if((needed_reg[i]>>5)&1) DebugMessage(M64MSG_VERBOSE, "ebp ");
10424 if((needed_reg[i]>>6)&1) DebugMessage(M64MSG_VERBOSE, "esi ");
10425 if((needed_reg[i]>>7)&1) DebugMessage(M64MSG_VERBOSE, "edi ");
10426 DebugMessage(M64MSG_VERBOSE, "r:");
10427 for(r=0;r<=CCREG;r++) {
10428 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10429 if((requires_32bit[i]>>r)&1) {
10430 if(r==CCREG) DebugMessage(M64MSG_VERBOSE, " CC");
10431 else if(r==HIREG) DebugMessage(M64MSG_VERBOSE, " HI");
10432 else if(r==LOREG) DebugMessage(M64MSG_VERBOSE, " LO");
10433 else DebugMessage(M64MSG_VERBOSE, " r%d",r);
10436 /*DebugMessage(M64MSG_VERBOSE, "pr:");
10437 for(r=0;r<=CCREG;r++) {
10438 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10439 if((pr32[i]>>r)&1) {
10440 if(r==CCREG) DebugMessage(M64MSG_VERBOSE, " CC");
10441 else if(r==HIREG) DebugMessage(M64MSG_VERBOSE, " HI");
10442 else if(r==LOREG) DebugMessage(M64MSG_VERBOSE, " LO");
10443 else DebugMessage(M64MSG_VERBOSE, " r%d",r);
10446 if(pr32[i]!=requires_32bit[i]) DebugMessage(M64MSG_ERROR, " OOPS");*/
10447 #if NEW_DYNAREC == NEW_DYNAREC_X86
10448 DebugMessage(M64MSG_VERBOSE, "entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
10449 DebugMessage(M64MSG_VERBOSE, "dirty: ");
10450 if(regs[i].wasdirty&1) DebugMessage(M64MSG_VERBOSE, "eax ");
10451 if((regs[i].wasdirty>>1)&1) DebugMessage(M64MSG_VERBOSE, "ecx ");
10452 if((regs[i].wasdirty>>2)&1) DebugMessage(M64MSG_VERBOSE, "edx ");
10453 if((regs[i].wasdirty>>3)&1) DebugMessage(M64MSG_VERBOSE, "ebx ");
10454 if((regs[i].wasdirty>>5)&1) DebugMessage(M64MSG_VERBOSE, "ebp ");
10455 if((regs[i].wasdirty>>6)&1) DebugMessage(M64MSG_VERBOSE, "esi ");
10456 if((regs[i].wasdirty>>7)&1) DebugMessage(M64MSG_VERBOSE, "edi ");
10458 #if NEW_DYNAREC == NEW_DYNAREC_ARM
10459 DebugMessage(M64MSG_VERBOSE, "entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
10460 DebugMessage(M64MSG_VERBOSE, "dirty: ");
10461 if(regs[i].wasdirty&1) DebugMessage(M64MSG_VERBOSE, "r0 ");
10462 if((regs[i].wasdirty>>1)&1) DebugMessage(M64MSG_VERBOSE, "r1 ");
10463 if((regs[i].wasdirty>>2)&1) DebugMessage(M64MSG_VERBOSE, "r2 ");
10464 if((regs[i].wasdirty>>3)&1) DebugMessage(M64MSG_VERBOSE, "r3 ");
10465 if((regs[i].wasdirty>>4)&1) DebugMessage(M64MSG_VERBOSE, "r4 ");
10466 if((regs[i].wasdirty>>5)&1) DebugMessage(M64MSG_VERBOSE, "r5 ");
10467 if((regs[i].wasdirty>>6)&1) DebugMessage(M64MSG_VERBOSE, "r6 ");
10468 if((regs[i].wasdirty>>7)&1) DebugMessage(M64MSG_VERBOSE, "r7 ");
10469 if((regs[i].wasdirty>>8)&1) DebugMessage(M64MSG_VERBOSE, "r8 ");
10470 if((regs[i].wasdirty>>9)&1) DebugMessage(M64MSG_VERBOSE, "r9 ");
10471 if((regs[i].wasdirty>>10)&1) DebugMessage(M64MSG_VERBOSE, "r10 ");
10472 if((regs[i].wasdirty>>12)&1) DebugMessage(M64MSG_VERBOSE, "r12 ");
10474 disassemble_inst(i);
10475 //printf ("ccadj[%d] = %d",i,ccadj[i]);
10476 #if NEW_DYNAREC == NEW_DYNAREC_X86
10477 DebugMessage(M64MSG_VERBOSE, "eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
10478 if(regs[i].dirty&1) DebugMessage(M64MSG_VERBOSE, "eax ");
10479 if((regs[i].dirty>>1)&1) DebugMessage(M64MSG_VERBOSE, "ecx ");
10480 if((regs[i].dirty>>2)&1) DebugMessage(M64MSG_VERBOSE, "edx ");
10481 if((regs[i].dirty>>3)&1) DebugMessage(M64MSG_VERBOSE, "ebx ");
10482 if((regs[i].dirty>>5)&1) DebugMessage(M64MSG_VERBOSE, "ebp ");
10483 if((regs[i].dirty>>6)&1) DebugMessage(M64MSG_VERBOSE, "esi ");
10484 if((regs[i].dirty>>7)&1) DebugMessage(M64MSG_VERBOSE, "edi ");
10486 #if NEW_DYNAREC == NEW_DYNAREC_ARM
10487 DebugMessage(M64MSG_VERBOSE, "r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
10488 if(regs[i].dirty&1) DebugMessage(M64MSG_VERBOSE, "r0 ");
10489 if((regs[i].dirty>>1)&1) DebugMessage(M64MSG_VERBOSE, "r1 ");
10490 if((regs[i].dirty>>2)&1) DebugMessage(M64MSG_VERBOSE, "r2 ");
10491 if((regs[i].dirty>>3)&1) DebugMessage(M64MSG_VERBOSE, "r3 ");
10492 if((regs[i].dirty>>4)&1) DebugMessage(M64MSG_VERBOSE, "r4 ");
10493 if((regs[i].dirty>>5)&1) DebugMessage(M64MSG_VERBOSE, "r5 ");
10494 if((regs[i].dirty>>6)&1) DebugMessage(M64MSG_VERBOSE, "r6 ");
10495 if((regs[i].dirty>>7)&1) DebugMessage(M64MSG_VERBOSE, "r7 ");
10496 if((regs[i].dirty>>8)&1) DebugMessage(M64MSG_VERBOSE, "r8 ");
10497 if((regs[i].dirty>>9)&1) DebugMessage(M64MSG_VERBOSE, "r9 ");
10498 if((regs[i].dirty>>10)&1) DebugMessage(M64MSG_VERBOSE, "r10 ");
10499 if((regs[i].dirty>>12)&1) DebugMessage(M64MSG_VERBOSE, "r12 ");
10501 if(regs[i].isconst) {
10502 DebugMessage(M64MSG_VERBOSE, "constants: ");
10503 #if NEW_DYNAREC == NEW_DYNAREC_X86
10504 if(regs[i].isconst&1) DebugMessage(M64MSG_VERBOSE, "eax=%x ",(int)constmap[i][0]);
10505 if((regs[i].isconst>>1)&1) DebugMessage(M64MSG_VERBOSE, "ecx=%x ",(int)constmap[i][1]);
10506 if((regs[i].isconst>>2)&1) DebugMessage(M64MSG_VERBOSE, "edx=%x ",(int)constmap[i][2]);
10507 if((regs[i].isconst>>3)&1) DebugMessage(M64MSG_VERBOSE, "ebx=%x ",(int)constmap[i][3]);
10508 if((regs[i].isconst>>5)&1) DebugMessage(M64MSG_VERBOSE, "ebp=%x ",(int)constmap[i][5]);
10509 if((regs[i].isconst>>6)&1) DebugMessage(M64MSG_VERBOSE, "esi=%x ",(int)constmap[i][6]);
10510 if((regs[i].isconst>>7)&1) DebugMessage(M64MSG_VERBOSE, "edi=%x ",(int)constmap[i][7]);
10512 #if NEW_DYNAREC == NEW_DYNAREC_ARM
10513 if(regs[i].isconst&1) DebugMessage(M64MSG_VERBOSE, "r0=%x ",(int)constmap[i][0]);
10514 if((regs[i].isconst>>1)&1) DebugMessage(M64MSG_VERBOSE, "r1=%x ",(int)constmap[i][1]);
10515 if((regs[i].isconst>>2)&1) DebugMessage(M64MSG_VERBOSE, "r2=%x ",(int)constmap[i][2]);
10516 if((regs[i].isconst>>3)&1) DebugMessage(M64MSG_VERBOSE, "r3=%x ",(int)constmap[i][3]);
10517 if((regs[i].isconst>>4)&1) DebugMessage(M64MSG_VERBOSE, "r4=%x ",(int)constmap[i][4]);
10518 if((regs[i].isconst>>5)&1) DebugMessage(M64MSG_VERBOSE, "r5=%x ",(int)constmap[i][5]);
10519 if((regs[i].isconst>>6)&1) DebugMessage(M64MSG_VERBOSE, "r6=%x ",(int)constmap[i][6]);
10520 if((regs[i].isconst>>7)&1) DebugMessage(M64MSG_VERBOSE, "r7=%x ",(int)constmap[i][7]);
10521 if((regs[i].isconst>>8)&1) DebugMessage(M64MSG_VERBOSE, "r8=%x ",(int)constmap[i][8]);
10522 if((regs[i].isconst>>9)&1) DebugMessage(M64MSG_VERBOSE, "r9=%x ",(int)constmap[i][9]);
10523 if((regs[i].isconst>>10)&1) DebugMessage(M64MSG_VERBOSE, "r10=%x ",(int)constmap[i][10]);
10524 if((regs[i].isconst>>12)&1) DebugMessage(M64MSG_VERBOSE, "r12=%x ",(int)constmap[i][12]);
10527 DebugMessage(M64MSG_VERBOSE, " 32:");
10528 for(r=0;r<=CCREG;r++) {
10529 if((regs[i].is32>>r)&1) {
10530 if(r==CCREG) DebugMessage(M64MSG_VERBOSE, " CC");
10531 else if(r==HIREG) DebugMessage(M64MSG_VERBOSE, " HI");
10532 else if(r==LOREG) DebugMessage(M64MSG_VERBOSE, " LO");
10533 else DebugMessage(M64MSG_VERBOSE, " r%d",r);
10536 /*DebugMessage(M64MSG_VERBOSE, " p32:");
10537 for(r=0;r<=CCREG;r++) {
10538 if((p32[i]>>r)&1) {
10539 if(r==CCREG) DebugMessage(M64MSG_VERBOSE, " CC");
10540 else if(r==HIREG) DebugMessage(M64MSG_VERBOSE, " HI");
10541 else if(r==LOREG) DebugMessage(M64MSG_VERBOSE, " LO");
10542 else DebugMessage(M64MSG_VERBOSE, " r%d",r);
10545 if(p32[i]!=regs[i].is32) DebugMessage(M64MSG_VERBOSE, " NO MATCH");*/
10546 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10547 #if NEW_DYNAREC == NEW_DYNAREC_X86
10548 DebugMessage(M64MSG_VERBOSE, "branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
10549 if(branch_regs[i].dirty&1) DebugMessage(M64MSG_VERBOSE, "eax ");
10550 if((branch_regs[i].dirty>>1)&1) DebugMessage(M64MSG_VERBOSE, "ecx ");
10551 if((branch_regs[i].dirty>>2)&1) DebugMessage(M64MSG_VERBOSE, "edx ");
10552 if((branch_regs[i].dirty>>3)&1) DebugMessage(M64MSG_VERBOSE, "ebx ");
10553 if((branch_regs[i].dirty>>5)&1) DebugMessage(M64MSG_VERBOSE, "ebp ");
10554 if((branch_regs[i].dirty>>6)&1) DebugMessage(M64MSG_VERBOSE, "esi ");
10555 if((branch_regs[i].dirty>>7)&1) DebugMessage(M64MSG_VERBOSE, "edi ");
10557 #if NEW_DYNAREC == NEW_DYNAREC_ARM
10558 DebugMessage(M64MSG_VERBOSE, "branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
10559 if(branch_regs[i].dirty&1) DebugMessage(M64MSG_VERBOSE, "r0 ");
10560 if((branch_regs[i].dirty>>1)&1) DebugMessage(M64MSG_VERBOSE, "r1 ");
10561 if((branch_regs[i].dirty>>2)&1) DebugMessage(M64MSG_VERBOSE, "r2 ");
10562 if((branch_regs[i].dirty>>3)&1) DebugMessage(M64MSG_VERBOSE, "r3 ");
10563 if((branch_regs[i].dirty>>4)&1) DebugMessage(M64MSG_VERBOSE, "r4 ");
10564 if((branch_regs[i].dirty>>5)&1) DebugMessage(M64MSG_VERBOSE, "r5 ");
10565 if((branch_regs[i].dirty>>6)&1) DebugMessage(M64MSG_VERBOSE, "r6 ");
10566 if((branch_regs[i].dirty>>7)&1) DebugMessage(M64MSG_VERBOSE, "r7 ");
10567 if((branch_regs[i].dirty>>8)&1) DebugMessage(M64MSG_VERBOSE, "r8 ");
10568 if((branch_regs[i].dirty>>9)&1) DebugMessage(M64MSG_VERBOSE, "r9 ");
10569 if((branch_regs[i].dirty>>10)&1) DebugMessage(M64MSG_VERBOSE, "r10 ");
10570 if((branch_regs[i].dirty>>12)&1) DebugMessage(M64MSG_VERBOSE, "r12 ");
10572 DebugMessage(M64MSG_VERBOSE, " 32:");
10573 for(r=0;r<=CCREG;r++) {
10574 if((branch_regs[i].is32>>r)&1) {
10575 if(r==CCREG) DebugMessage(M64MSG_VERBOSE, " CC");
10576 else if(r==HIREG) DebugMessage(M64MSG_VERBOSE, " HI");
10577 else if(r==LOREG) DebugMessage(M64MSG_VERBOSE, " LO");
10578 else DebugMessage(M64MSG_VERBOSE, " r%d",r);
10585 /* Pass 8 - Assembly */
10586 linkcount=0;stubcount=0;
10587 ds=0;is_delayslot=0;
10589 #ifndef DESTRUCTIVE_WRITEBACK
10590 uint64_t is32_pre=0;
10593 u_int beginning=(u_int)out;
10594 if((u_int)addr&1) {
10598 for(i=0;i<slen;i++)
10600 //if(ds) DebugMessage(M64MSG_VERBOSE, "ds: ");
10601 // if((void*)assem_debug==(void*)printf) disassemble_inst(i);
10602 #if defined( ASSEM_DEBUG )
10603 disassemble_inst(i);
10606 ds=0; // Skip delay slot
10607 if(bt[i]) assem_debug("OOPS - branch into delay slot");
10610 #ifndef DESTRUCTIVE_WRITEBACK
10611 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
10613 wb_sx(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,is32_pre,regs[i].was32,
10614 unneeded_reg[i],unneeded_reg_upper[i]);
10615 wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre,
10616 unneeded_reg[i],unneeded_reg_upper[i]);
10618 is32_pre=regs[i].is32;
10619 dirty_pre=regs[i].dirty;
10622 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
10624 wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32,
10625 unneeded_reg[i],unneeded_reg_upper[i]);
10626 loop_preload(regmap_pre[i],regs[i].regmap_entry);
10628 // branch target entry point
10629 instr_addr[i]=(u_int)out;
10630 assem_debug("<->");
10632 if(regs[i].regmap_entry[HOST_CCREG]==CCREG&®s[i].regmap[HOST_CCREG]!=CCREG)
10633 wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32);
10634 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
10635 address_generation(i,®s[i],regs[i].regmap_entry);
10636 load_consts(regmap_pre[i],regs[i].regmap,regs[i].was32,i);
10637 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10639 // Load the delay slot registers if necessary
10640 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
10641 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
10642 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
10643 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
10644 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39)
10645 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
10649 // Preload registers for following instruction
10650 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
10651 if(rs1[i+1]!=rt1[i]&&rs1[i+1]!=rt2[i])
10652 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
10653 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
10654 if(rs2[i+1]!=rt1[i]&&rs2[i+1]!=rt2[i])
10655 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
10657 // TODO: if(is_ooo(i)) address_generation(i+1);
10658 if(itype[i]==CJUMP||itype[i]==FJUMP)
10659 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
10660 if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS)
10661 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,MMREG,ROREG);
10662 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39)
10663 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
10664 if(bt[i]) cop1_usable=0;
10668 alu_assemble(i,®s[i]);break;
10670 imm16_assemble(i,®s[i]);break;
10672 shift_assemble(i,®s[i]);break;
10674 shiftimm_assemble(i,®s[i]);break;
10676 load_assemble(i,®s[i]);break;
10678 loadlr_assemble(i,®s[i]);break;
10680 store_assemble(i,®s[i]);break;
10682 storelr_assemble(i,®s[i]);break;
10684 cop0_assemble(i,®s[i]);break;
10686 cop1_assemble(i,®s[i]);break;
10688 c1ls_assemble(i,®s[i]);break;
10690 fconv_assemble(i,®s[i]);break;
10692 float_assemble(i,®s[i]);break;
10694 fcomp_assemble(i,®s[i]);break;
10696 multdiv_assemble(i,®s[i]);break;
10698 mov_assemble(i,®s[i]);break;
10700 syscall_assemble(i,®s[i]);break;
10702 ujump_assemble(i,®s[i]);ds=1;break;
10704 rjump_assemble(i,®s[i]);ds=1;break;
10706 cjump_assemble(i,®s[i]);ds=1;break;
10708 sjump_assemble(i,®s[i]);ds=1;break;
10710 fjump_assemble(i,®s[i]);ds=1;break;
10712 pagespan_assemble(i,®s[i]);break;
10714 if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
10715 literal_pool(1024);
10717 literal_pool_jumpover(256);
10720 //assert(itype[i-2]==UJUMP||itype[i-2]==RJUMP||(source[i-2]>>16)==0x1000);
10721 // If the block did not end with an unconditional branch,
10722 // add a jump to the next instruction.
10724 if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) {
10725 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
10727 if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP&&itype[i-2]!=FJUMP) {
10728 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
10729 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
10730 emit_loadreg(CCREG,HOST_CCREG);
10731 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
10733 else if(!likely[i-2])
10735 store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].is32,branch_regs[i-2].dirty,start+i*4);
10736 assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
10740 store_regs_bt(regs[i-2].regmap,regs[i-2].is32,regs[i-2].dirty,start+i*4);
10741 assert(regs[i-2].regmap[HOST_CCREG]==CCREG);
10743 add_to_linker((int)out,start+i*4,0);
10750 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
10751 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
10752 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
10753 emit_loadreg(CCREG,HOST_CCREG);
10754 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
10755 add_to_linker((int)out,start+i*4,0);
10759 // TODO: delay slot stubs?
10761 for(i=0;i<stubcount;i++)
10763 switch(stubs[i][0])
10771 do_readstub(i);break;
10776 do_writestub(i);break;
10778 do_ccstub(i);break;
10780 do_invstub(i);break;
10782 do_cop1stub(i);break;
10784 do_unalignedwritestub(i);break;
10788 /* Pass 9 - Linker */
10789 for(i=0;i<linkcount;i++)
10791 assem_debug("%8x -> %8x",link_addr[i][0],link_addr[i][1]);
10793 if(!link_addr[i][2])
10796 void *addr=check_addr(link_addr[i][1]);
10797 emit_extjump(link_addr[i][0],link_addr[i][1]);
10799 set_jump_target(link_addr[i][0],(int)addr);
10800 add_link(link_addr[i][1],stub);
10802 else set_jump_target(link_addr[i][0],(int)stub);
10807 int target=(link_addr[i][1]-start)>>2;
10808 assert(target>=0&&target<slen);
10809 assert(instr_addr[target]);
10810 //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
10811 //set_jump_target_fillslot(link_addr[i][0],instr_addr[target],link_addr[i][2]>>1);
10813 set_jump_target(link_addr[i][0],instr_addr[target]);
10817 // External Branch Targets (jump_in)
10818 if(copy+slen*4>(void *)shadow+sizeof(shadow)) copy=shadow;
10819 for(i=0;i<slen;i++)
10823 if(instr_addr[i]) // TODO - delay slots (=null)
10825 u_int vaddr=start+i*4;
10826 u_int page=(0x80000000^vaddr)>>12;
10828 if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[page^0x80000]^0x80000000)>>12;
10829 if(page>2048) page=2048+(page&2047);
10830 if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
10831 if(vpage>2048) vpage=2048+(vpage&2047);
10833 //if(!(is32[i]&(~unneeded_reg_upper[i])&~(1LL<<CCREG)))
10834 if(!requires_32bit[i])
10836 assem_debug("%8x (%d) <- %8x",instr_addr[i],i,start+i*4);
10837 assem_debug("jump_in: %x",start+i*4);
10838 ll_add(jump_dirty+vpage,vaddr,(void *)out);
10839 int entry_point=do_dirty_stub(i);
10840 ll_add(jump_in+page,vaddr,(void *)entry_point);
10841 // If there was an existing entry in the hash table,
10842 // replace it with the new address.
10843 // Don't add new entries. We'll insert the
10844 // ones that actually get used in check_addr().
10845 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
10846 if(ht_bin[0]==vaddr) {
10847 ht_bin[1]=entry_point;
10849 if(ht_bin[2]==vaddr) {
10850 ht_bin[3]=entry_point;
10855 u_int r=requires_32bit[i]|!!(requires_32bit[i]>>32);
10856 assem_debug("%8x (%d) <- %8x",instr_addr[i],i,start+i*4);
10857 assem_debug("jump_in: %x (restricted - %x)",start+i*4,r);
10858 //int entry_point=(int)out;
10859 ////assem_debug("entry_point: %x",entry_point);
10860 //load_regs_entry(i);
10861 //if(entry_point==(int)out)
10862 // entry_point=instr_addr[i];
10864 // emit_jmp(instr_addr[i]);
10865 //ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
10866 ll_add_32(jump_dirty+vpage,vaddr,r,(void *)out);
10867 int entry_point=do_dirty_stub(i);
10868 ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
10873 // Write out the literal pool if necessary
10875 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
10877 if(((u_int)out)&7) emit_addnop(13);
10879 assert((u_int)out-beginning<MAX_OUTPUT_BLOCK_SIZE);
10880 //DebugMessage(M64MSG_VERBOSE, "shadow buffer: %x-%x",(int)copy,(int)copy+slen*4);
10881 memcpy(copy,source,slen*4);
10884 #if NEW_DYNAREC == NEW_DYNAREC_ARM
10885 __clear_cache((void *)beginning,out);
10886 //cacheflush((void *)beginning,out,0);
10889 // If we're within 256K of the end of the buffer,
10890 // start over from the beginning. (Is 256K enough?)
10891 if(out > (u_char *)(base_addr+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE-JUMP_TABLE_SIZE))
10892 out=(u_char *)base_addr;
10894 // Trap writes to any of the pages we compiled
10895 for(i=start>>12;i<=(start+slen*4)>>12;i++) {
10897 memory_map[i]|=0x40000000;
10898 if((signed int)start>=(signed int)0xC0000000) {
10900 j=(((u_int)i<<12)+(memory_map[i]<<2)-(u_int)rdram+(u_int)0x80000000)>>12;
10902 memory_map[j]|=0x40000000;
10903 //DebugMessage(M64MSG_VERBOSE, "write protect physical page: %x (virtual %x)",j<<12,start);
10907 /* Pass 10 - Free memory by expiring oldest blocks */
10909 int end=((((intptr_t)out-(intptr_t)base_addr)>>(TARGET_SIZE_2-16))+16384)&65535;
10910 while(expirep!=end)
10912 int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
10913 int base=(int)base_addr+((expirep>>13)<<shift); // Base address of this block
10914 inv_debug("EXP: Phase %d\n",expirep);
10915 switch((expirep>>11)&3)
10918 // Clear jump_in and jump_dirty
10919 ll_remove_matching_addrs(jump_in+(expirep&2047),base,shift);
10920 ll_remove_matching_addrs(jump_dirty+(expirep&2047),base,shift);
10921 ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base,shift);
10922 ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base,shift);
10926 ll_kill_pointers(jump_out[expirep&2047],base,shift);
10927 ll_kill_pointers(jump_out[(expirep&2047)+2048],base,shift);
10930 // Clear hash table
10931 for(i=0;i<32;i++) {
10932 u_int *ht_bin=hash_table[((expirep&2047)<<5)+i];
10933 if((ht_bin[3]>>shift)==(base>>shift) ||
10934 ((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
10935 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[2],ht_bin[3]);
10936 ht_bin[2]=ht_bin[3]=-1;
10938 if((ht_bin[1]>>shift)==(base>>shift) ||
10939 ((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
10940 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[0],ht_bin[1]);
10941 ht_bin[0]=ht_bin[2];
10942 ht_bin[1]=ht_bin[3];
10943 ht_bin[2]=ht_bin[3]=-1;
10949 #if NEW_DYNAREC == NEW_DYNAREC_ARM
10950 if((expirep&2047)==0)
10953 ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);
10954 ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base,shift);
10957 expirep=(expirep+1)&65535;
10962 void TLBWI_new(void)
10965 /* Remove old entries */
10966 unsigned int old_start_even=tlb_e[Index&0x3F].start_even;
10967 unsigned int old_end_even=tlb_e[Index&0x3F].end_even;
10968 unsigned int old_start_odd=tlb_e[Index&0x3F].start_odd;
10969 unsigned int old_end_odd=tlb_e[Index&0x3F].end_odd;
10970 for (i=old_start_even>>12; i<=old_end_even>>12; i++)
10972 if(i<0x80000||i>0xBFFFF)
10974 invalidate_block(i);
10978 for (i=old_start_odd>>12; i<=old_end_odd>>12; i++)
10980 if(i<0x80000||i>0xBFFFF)
10982 invalidate_block(i);
10986 cached_interpreter_table.TLBWI();
10987 //DebugMessage(M64MSG_VERBOSE, "TLBWI: index=%d",Index);
10988 //DebugMessage(M64MSG_VERBOSE, "TLBWI: start_even=%x end_even=%x phys_even=%x v=%d d=%d",tlb_e[Index&0x3F].start_even,tlb_e[Index&0x3F].end_even,tlb_e[Index&0x3F].phys_even,tlb_e[Index&0x3F].v_even,tlb_e[Index&0x3F].d_even);
10989 //DebugMessage(M64MSG_VERBOSE, "TLBWI: start_odd=%x end_odd=%x phys_odd=%x v=%d d=%d",tlb_e[Index&0x3F].start_odd,tlb_e[Index&0x3F].end_odd,tlb_e[Index&0x3F].phys_odd,tlb_e[Index&0x3F].v_odd,tlb_e[Index&0x3F].d_odd);
10990 /* Combine tlb_LUT_r, tlb_LUT_w, and invalid_code into a single table
10991 for fast look up. */
10992 for (i=tlb_e[Index&0x3F].start_even>>12; i<=tlb_e[Index&0x3F].end_even>>12; i++)
10994 //DebugMessage(M64MSG_VERBOSE, "%x: r:%8x w:%8x",i,tlb_LUT_r[i],tlb_LUT_w[i]);
10995 if(i<0x80000||i>0xBFFFF)
10998 memory_map[i]=((tlb_LUT_r[i]&0xFFFFF000)-(i<<12)+(unsigned int)rdram-0x80000000)>>2;
10999 // FIXME: should make sure the physical page is invalid too
11000 if(!tlb_LUT_w[i]||!invalid_code[i]) {
11001 memory_map[i]|=0x40000000; // Write protect
11003 assert(tlb_LUT_r[i]==tlb_LUT_w[i]);
11005 if(!using_tlb) DebugMessage(M64MSG_VERBOSE, "Enabled TLB");
11006 // Tell the dynamic recompiler to generate tlb lookup code
11009 else memory_map[i]=-1;
11011 //DebugMessage(M64MSG_VERBOSE, "memory_map[%x]: %8x (+%8x)",i,memory_map[i],memory_map[i]<<2);
11013 for (i=tlb_e[Index&0x3F].start_odd>>12; i<=tlb_e[Index&0x3F].end_odd>>12; i++)
11015 //DebugMessage(M64MSG_VERBOSE, "%x: r:%8x w:%8x",i,tlb_LUT_r[i],tlb_LUT_w[i]);
11016 if(i<0x80000||i>0xBFFFF)
11019 memory_map[i]=((tlb_LUT_r[i]&0xFFFFF000)-(i<<12)+(unsigned int)rdram-0x80000000)>>2;
11020 // FIXME: should make sure the physical page is invalid too
11021 if(!tlb_LUT_w[i]||!invalid_code[i]) {
11022 memory_map[i]|=0x40000000; // Write protect
11024 assert(tlb_LUT_r[i]==tlb_LUT_w[i]);
11026 if(!using_tlb) DebugMessage(M64MSG_VERBOSE, "Enabled TLB");
11027 // Tell the dynamic recompiler to generate tlb lookup code
11030 else memory_map[i]=-1;
11032 //DebugMessage(M64MSG_VERBOSE, "memory_map[%x]: %8x (+%8x)",i,memory_map[i],memory_map[i]<<2);
11036 void TLBWR_new(void)
11039 Random = (Count/2 % (32 - Wired)) + Wired;
11040 /* Remove old entries */
11041 unsigned int old_start_even=tlb_e[Random&0x3F].start_even;
11042 unsigned int old_end_even=tlb_e[Random&0x3F].end_even;
11043 unsigned int old_start_odd=tlb_e[Random&0x3F].start_odd;
11044 unsigned int old_end_odd=tlb_e[Random&0x3F].end_odd;
11045 for (i=old_start_even>>12; i<=old_end_even>>12; i++)
11047 if(i<0x80000||i>0xBFFFF)
11049 invalidate_block(i);
11053 for (i=old_start_odd>>12; i<=old_end_odd>>12; i++)
11055 if(i<0x80000||i>0xBFFFF)
11057 invalidate_block(i);
11061 cached_interpreter_table.TLBWR();
11062 /* Combine tlb_LUT_r, tlb_LUT_w, and invalid_code into a single table
11063 for fast look up. */
11064 for (i=tlb_e[Random&0x3F].start_even>>12; i<=tlb_e[Random&0x3F].end_even>>12; i++)
11066 //DebugMessage(M64MSG_VERBOSE, "%x: r:%8x w:%8x",i,tlb_LUT_r[i],tlb_LUT_w[i]);
11067 if(i<0x80000||i>0xBFFFF)
11070 memory_map[i]=((tlb_LUT_r[i]&0xFFFFF000)-(i<<12)+(unsigned int)rdram-0x80000000)>>2;
11071 // FIXME: should make sure the physical page is invalid too
11072 if(!tlb_LUT_w[i]||!invalid_code[i]) {
11073 memory_map[i]|=0x40000000; // Write protect
11075 assert(tlb_LUT_r[i]==tlb_LUT_w[i]);
11077 if(!using_tlb) DebugMessage(M64MSG_VERBOSE, "Enabled TLB");
11078 // Tell the dynamic recompiler to generate tlb lookup code
11081 else memory_map[i]=-1;
11083 //DebugMessage(M64MSG_VERBOSE, "memory_map[%x]: %8x (+%8x)",i,memory_map[i],memory_map[i]<<2);
11085 for (i=tlb_e[Random&0x3F].start_odd>>12; i<=tlb_e[Random&0x3F].end_odd>>12; i++)
11087 //DebugMessage(M64MSG_VERBOSE, "%x: r:%8x w:%8x",i,tlb_LUT_r[i],tlb_LUT_w[i]);
11088 if(i<0x80000||i>0xBFFFF)
11091 memory_map[i]=((tlb_LUT_r[i]&0xFFFFF000)-(i<<12)+(unsigned int)rdram-0x80000000)>>2;
11092 // FIXME: should make sure the physical page is invalid too
11093 if(!tlb_LUT_w[i]||!invalid_code[i]) {
11094 memory_map[i]|=0x40000000; // Write protect
11096 assert(tlb_LUT_r[i]==tlb_LUT_w[i]);
11098 if(!using_tlb) DebugMessage(M64MSG_VERBOSE, "Enabled TLB");
11099 // Tell the dynamic recompiler to generate tlb lookup code
11102 else memory_map[i]=-1;
11104 //DebugMessage(M64MSG_VERBOSE, "memory_map[%x]: %8x (+%8x)",i,memory_map[i],memory_map[i]<<2);