1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - gr4300.c *
3 * Mupen64Plus homepage: http://code.google.com/p/mupen64plus/ *
4 * Copyright (C) 2002 Hacktarux *
6 * This program is free software; you can redistribute it and/or modify *
7 * it under the terms of the GNU General Public License as published by *
8 * the Free Software Foundation; either version 2 of the License, or *
9 * (at your option) any later version. *
11 * This program is distributed in the hope that it will be useful, *
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
14 * GNU General Public License for more details. *
16 * You should have received a copy of the GNU General Public License *
17 * along with this program; if not, write to the *
18 * Free Software Foundation, Inc., *
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
20 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
23 #include "interpret.h"
26 #include "api/debugger.h"
28 #include "r4300/r4300.h"
29 #include "r4300/macros.h"
30 #include "r4300/interupt.h"
31 #include "r4300/ops.h"
32 #include "r4300/recomph.h"
33 #include "r4300/exception.h"
35 #include "memory/memory.h"
37 extern unsigned int op;
39 static precomp_instr fake_instr;
41 static int eax, ebx, ecx, edx, esp, ebp, esi, edi;
46 /* static functions */
48 static void genupdate_count(unsigned int addr)
50 #if !defined(COMPARE_CORE) && !defined(DBG)
51 mov_reg32_imm32(EAX, addr);
52 sub_reg32_m32(EAX, (unsigned int*)(&last_addr));
53 shr_reg32_imm8(EAX, 2);
54 mov_reg32_m32(EDX, &count_per_op);
56 add_m32_reg32((unsigned int*)(&Count), EAX);
58 mov_m32_imm32((unsigned int*)(&PC), (unsigned int)(dst+1));
59 mov_reg32_imm32(EAX, (unsigned int)update_count);
64 static void gencheck_interupt(unsigned int instr_structure)
66 mov_eax_memoffs32(&next_interupt);
67 cmp_reg32_m32(EAX, &Count);
69 mov_m32_imm32((unsigned int*)(&PC), instr_structure); // 10
70 mov_reg32_imm32(EAX, (unsigned int)gen_interupt); // 5
74 static void gencheck_interupt_out(unsigned int addr)
76 mov_eax_memoffs32(&next_interupt);
77 cmp_reg32_m32(EAX, &Count);
79 mov_m32_imm32((unsigned int*)(&fake_instr.addr), addr);
80 mov_m32_imm32((unsigned int*)(&PC), (unsigned int)(&fake_instr));
81 mov_reg32_imm32(EAX, (unsigned int)gen_interupt);
85 static void genbeq_test(void)
87 int rs_64bit = is64((unsigned int *)dst->f.i.rs);
88 int rt_64bit = is64((unsigned int *)dst->f.i.rt);
90 if (!rs_64bit && !rt_64bit)
92 int rs = allocate_register((unsigned int *)dst->f.i.rs);
93 int rt = allocate_register((unsigned int *)dst->f.i.rt);
95 cmp_reg32_reg32(rs, rt);
97 mov_m32_imm32((unsigned int *)(&branch_taken), 1); // 10
98 jmp_imm_short(10); // 2
99 mov_m32_imm32((unsigned int *)(&branch_taken), 0); // 10
101 else if (rs_64bit == -1)
103 int rt1 = allocate_64_register1((unsigned int *)dst->f.i.rt);
104 int rt2 = allocate_64_register2((unsigned int *)dst->f.i.rt);
106 cmp_reg32_m32(rt1, (unsigned int *)dst->f.i.rs);
108 cmp_reg32_m32(rt2, ((unsigned int *)dst->f.i.rs)+1); // 6
110 mov_m32_imm32((unsigned int *)(&branch_taken), 1); // 10
111 jmp_imm_short(10); // 2
112 mov_m32_imm32((unsigned int *)(&branch_taken), 0); // 10
114 else if (rt_64bit == -1)
116 int rs1 = allocate_64_register1((unsigned int *)dst->f.i.rs);
117 int rs2 = allocate_64_register2((unsigned int *)dst->f.i.rs);
119 cmp_reg32_m32(rs1, (unsigned int *)dst->f.i.rt);
121 cmp_reg32_m32(rs2, ((unsigned int *)dst->f.i.rt)+1); // 6
123 mov_m32_imm32((unsigned int *)(&branch_taken), 1); // 10
124 jmp_imm_short(10); // 2
125 mov_m32_imm32((unsigned int *)(&branch_taken), 0); // 10
129 int rs1, rs2, rt1, rt2;
132 rt1 = allocate_64_register1((unsigned int *)dst->f.i.rt);
133 rt2 = allocate_64_register2((unsigned int *)dst->f.i.rt);
134 rs1 = allocate_64_register1((unsigned int *)dst->f.i.rs);
135 rs2 = allocate_64_register2((unsigned int *)dst->f.i.rs);
139 rs1 = allocate_64_register1((unsigned int *)dst->f.i.rs);
140 rs2 = allocate_64_register2((unsigned int *)dst->f.i.rs);
141 rt1 = allocate_64_register1((unsigned int *)dst->f.i.rt);
142 rt2 = allocate_64_register2((unsigned int *)dst->f.i.rt);
144 cmp_reg32_reg32(rs1, rt1);
146 cmp_reg32_reg32(rs2, rt2); // 2
148 mov_m32_imm32((unsigned int *)(&branch_taken), 1); // 10
149 jmp_imm_short(10); // 2
150 mov_m32_imm32((unsigned int *)(&branch_taken), 0); // 10
154 static void genbne_test(void)
156 int rs_64bit = is64((unsigned int *)dst->f.i.rs);
157 int rt_64bit = is64((unsigned int *)dst->f.i.rt);
159 if (!rs_64bit && !rt_64bit)
161 int rs = allocate_register((unsigned int *)dst->f.i.rs);
162 int rt = allocate_register((unsigned int *)dst->f.i.rt);
164 cmp_reg32_reg32(rs, rt);
166 mov_m32_imm32((unsigned int *)(&branch_taken), 1); // 10
167 jmp_imm_short(10); // 2
168 mov_m32_imm32((unsigned int *)(&branch_taken), 0); // 10
170 else if (rs_64bit == -1)
172 int rt1 = allocate_64_register1((unsigned int *)dst->f.i.rt);
173 int rt2 = allocate_64_register2((unsigned int *)dst->f.i.rt);
175 cmp_reg32_m32(rt1, (unsigned int *)dst->f.i.rs);
177 cmp_reg32_m32(rt2, ((unsigned int *)dst->f.i.rs)+1); // 6
179 mov_m32_imm32((unsigned int *)(&branch_taken), 0); // 10
180 jmp_imm_short(10); // 2
181 mov_m32_imm32((unsigned int *)(&branch_taken), 1); // 10
183 else if (rt_64bit == -1)
185 int rs1 = allocate_64_register1((unsigned int *)dst->f.i.rs);
186 int rs2 = allocate_64_register2((unsigned int *)dst->f.i.rs);
188 cmp_reg32_m32(rs1, (unsigned int *)dst->f.i.rt);
190 cmp_reg32_m32(rs2, ((unsigned int *)dst->f.i.rt)+1); // 6
192 mov_m32_imm32((unsigned int *)(&branch_taken), 0); // 10
193 jmp_imm_short(10); // 2
194 mov_m32_imm32((unsigned int *)(&branch_taken), 1); // 10
198 int rs1, rs2, rt1, rt2;
201 rt1 = allocate_64_register1((unsigned int *)dst->f.i.rt);
202 rt2 = allocate_64_register2((unsigned int *)dst->f.i.rt);
203 rs1 = allocate_64_register1((unsigned int *)dst->f.i.rs);
204 rs2 = allocate_64_register2((unsigned int *)dst->f.i.rs);
208 rs1 = allocate_64_register1((unsigned int *)dst->f.i.rs);
209 rs2 = allocate_64_register2((unsigned int *)dst->f.i.rs);
210 rt1 = allocate_64_register1((unsigned int *)dst->f.i.rt);
211 rt2 = allocate_64_register2((unsigned int *)dst->f.i.rt);
213 cmp_reg32_reg32(rs1, rt1);
215 cmp_reg32_reg32(rs2, rt2); // 2
217 mov_m32_imm32((unsigned int *)(&branch_taken), 0); // 10
218 jmp_imm_short(10); // 2
219 mov_m32_imm32((unsigned int *)(&branch_taken), 1); // 10
223 static void genblez_test(void)
225 int rs_64bit = is64((unsigned int *)dst->f.i.rs);
229 int rs = allocate_register((unsigned int *)dst->f.i.rs);
231 cmp_reg32_imm32(rs, 0);
233 mov_m32_imm32((unsigned int *)(&branch_taken), 1); // 10
234 jmp_imm_short(10); // 2
235 mov_m32_imm32((unsigned int *)(&branch_taken), 0); // 10
237 else if (rs_64bit == -1)
239 cmp_m32_imm32(((unsigned int *)dst->f.i.rs)+1, 0);
242 cmp_m32_imm32((unsigned int *)dst->f.i.rs, 0); // 10
244 mov_m32_imm32((unsigned int *)(&branch_taken), 0); // 10
245 jmp_imm_short(10); // 2
246 mov_m32_imm32((unsigned int *)(&branch_taken), 1); // 10
250 int rs1 = allocate_64_register1((unsigned int *)dst->f.i.rs);
251 int rs2 = allocate_64_register2((unsigned int *)dst->f.i.rs);
253 cmp_reg32_imm32(rs2, 0);
256 cmp_reg32_imm32(rs1, 0); // 6
258 mov_m32_imm32((unsigned int *)(&branch_taken), 0); // 10
259 jmp_imm_short(10); // 2
260 mov_m32_imm32((unsigned int *)(&branch_taken), 1); // 10
264 static void genbgtz_test(void)
266 int rs_64bit = is64((unsigned int *)dst->f.i.rs);
270 int rs = allocate_register((unsigned int *)dst->f.i.rs);
272 cmp_reg32_imm32(rs, 0);
274 mov_m32_imm32((unsigned int *)(&branch_taken), 1); // 10
275 jmp_imm_short(10); // 2
276 mov_m32_imm32((unsigned int *)(&branch_taken), 0); // 10
278 else if (rs_64bit == -1)
280 cmp_m32_imm32(((unsigned int *)dst->f.i.rs)+1, 0);
283 cmp_m32_imm32((unsigned int *)dst->f.i.rs, 0); // 10
285 mov_m32_imm32((unsigned int *)(&branch_taken), 0); // 10
286 jmp_imm_short(10); // 2
287 mov_m32_imm32((unsigned int *)(&branch_taken), 1); // 10
291 int rs1 = allocate_64_register1((unsigned int *)dst->f.i.rs);
292 int rs2 = allocate_64_register2((unsigned int *)dst->f.i.rs);
294 cmp_reg32_imm32(rs2, 0);
297 cmp_reg32_imm32(rs1, 0); // 6
299 mov_m32_imm32((unsigned int *)(&branch_taken), 0); // 10
300 jmp_imm_short(10); // 2
301 mov_m32_imm32((unsigned int *)(&branch_taken), 1); // 10
306 /* global functions */
308 void gennotcompiled(void)
310 free_all_registers();
313 mov_m32_imm32((unsigned int*)(&PC), (unsigned int)(dst));
314 mov_reg32_imm32(EAX, (unsigned int)cached_interpreter_table.NOTCOMPILED);
318 void genlink_subblock(void)
320 free_all_registers();
327 free_all_registers();
328 mov_m32_reg32((unsigned int*)&eax, EAX);
329 mov_m32_reg32((unsigned int*)&ebx, EBX);
330 mov_m32_reg32((unsigned int*)&ecx, ECX);
331 mov_m32_reg32((unsigned int*)&edx, EDX);
332 mov_m32_reg32((unsigned int*)&esp, ESP);
333 mov_m32_reg32((unsigned int*)&ebp, EBP);
334 mov_m32_reg32((unsigned int*)&esi, ESI);
335 mov_m32_reg32((unsigned int*)&edi, EDI);
337 mov_m32_imm32((unsigned int*)(&PC), (unsigned int)(dst));
338 mov_m32_imm32((unsigned int*)(&op), (unsigned int)(src));
339 mov_reg32_imm32(EAX, (unsigned int) CoreCompareCallback);
342 mov_reg32_m32(EAX, (unsigned int*)&eax);
343 mov_reg32_m32(EBX, (unsigned int*)&ebx);
344 mov_reg32_m32(ECX, (unsigned int*)&ecx);
345 mov_reg32_m32(EDX, (unsigned int*)&edx);
346 mov_reg32_m32(ESP, (unsigned int*)&esp);
347 mov_reg32_m32(EBP, (unsigned int*)&ebp);
348 mov_reg32_m32(ESI, (unsigned int*)&esi);
349 mov_reg32_m32(EDI, (unsigned int*)&edi);
353 void gencallinterp(unsigned long addr, int jump)
355 free_all_registers();
358 mov_m32_imm32((unsigned int*)(&dyna_interp), 1);
359 mov_m32_imm32((unsigned int*)(&PC), (unsigned int)(dst));
360 mov_reg32_imm32(EAX, addr);
364 mov_m32_imm32((unsigned int*)(&dyna_interp), 0);
365 mov_reg32_imm32(EAX, (unsigned int)dyna_jump);
370 void gendelayslot(void)
372 mov_m32_imm32(&delay_slot, 1);
375 free_all_registers();
376 genupdate_count(dst->addr+4);
378 mov_m32_imm32(&delay_slot, 0);
383 gencallinterp((unsigned int)cached_interpreter_table.NI, 0);
386 void genreserved(void)
388 gencallinterp((unsigned int)cached_interpreter_table.RESERVED, 0);
391 void genfin_block(void)
393 gencallinterp((unsigned int)cached_interpreter_table.FIN_BLOCK, 0);
396 void gencheck_interupt_reg(void) // addr is in EAX
398 mov_reg32_m32(EBX, &next_interupt);
399 cmp_reg32_m32(EBX, &Count);
401 mov_memoffs32_eax((unsigned int*)(&fake_instr.addr)); // 5
402 mov_m32_imm32((unsigned int*)(&PC), (unsigned int)(&fake_instr)); // 10
403 mov_reg32_imm32(EAX, (unsigned int)gen_interupt); // 5
404 call_reg32(EAX); // 2
414 gencallinterp((unsigned int)cached_interpreter_table.J, 1);
418 if (((dst->addr & 0xFFF) == 0xFFC &&
419 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
421 gencallinterp((unsigned int)cached_interpreter_table.J, 1);
426 naddr = ((dst-1)->f.j.inst_index<<2) | (dst->addr & 0xF0000000);
428 mov_m32_imm32(&last_addr, naddr);
429 gencheck_interupt((unsigned int)&actual->block[(naddr-actual->start)/4]);
436 #ifdef INTERPRET_J_OUT
437 gencallinterp((unsigned int)cached_interpreter_table.J_OUT, 1);
441 if (((dst->addr & 0xFFF) == 0xFFC &&
442 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
444 gencallinterp((unsigned int)cached_interpreter_table.J_OUT, 1);
449 naddr = ((dst-1)->f.j.inst_index<<2) | (dst->addr & 0xF0000000);
451 mov_m32_imm32(&last_addr, naddr);
452 gencheck_interupt_out(naddr);
453 mov_m32_imm32(&jump_to_address, naddr);
454 mov_m32_imm32((unsigned int*)(&PC), (unsigned int)(dst+1));
455 mov_reg32_imm32(EAX, (unsigned int)jump_to_func);
462 #ifdef INTERPRET_J_IDLE
463 gencallinterp((unsigned int)cached_interpreter_table.J_IDLE, 1);
465 if (((dst->addr & 0xFFF) == 0xFFC &&
466 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
468 gencallinterp((unsigned int)cached_interpreter_table.J_IDLE, 1);
472 mov_eax_memoffs32((unsigned int *)(&next_interupt));
473 sub_reg32_m32(EAX, (unsigned int *)(&Count));
474 cmp_reg32_imm8(EAX, 3);
477 and_eax_imm32(0xFFFFFFFC); // 5
478 add_m32_reg32((unsigned int *)(&Count), EAX); // 6
487 gencallinterp((unsigned int)cached_interpreter_table.JAL, 1);
491 if (((dst->addr & 0xFFF) == 0xFFC &&
492 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
494 gencallinterp((unsigned int)cached_interpreter_table.JAL, 1);
500 mov_m32_imm32((unsigned int *)(reg + 31), dst->addr + 4);
501 if (((dst->addr + 4) & 0x80000000))
502 mov_m32_imm32((unsigned int *)(®[31])+1, 0xFFFFFFFF);
504 mov_m32_imm32((unsigned int *)(®[31])+1, 0);
506 naddr = ((dst-1)->f.j.inst_index<<2) | (dst->addr & 0xF0000000);
508 mov_m32_imm32(&last_addr, naddr);
509 gencheck_interupt((unsigned int)&actual->block[(naddr-actual->start)/4]);
514 void genjal_out(void)
516 #ifdef INTERPRET_JAL_OUT
517 gencallinterp((unsigned int)cached_interpreter_table.JAL_OUT, 1);
521 if (((dst->addr & 0xFFF) == 0xFFC &&
522 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
524 gencallinterp((unsigned int)cached_interpreter_table.JAL_OUT, 1);
530 mov_m32_imm32((unsigned int *)(reg + 31), dst->addr + 4);
531 if (((dst->addr + 4) & 0x80000000))
532 mov_m32_imm32((unsigned int *)(®[31])+1, 0xFFFFFFFF);
534 mov_m32_imm32((unsigned int *)(®[31])+1, 0);
536 naddr = ((dst-1)->f.j.inst_index<<2) | (dst->addr & 0xF0000000);
538 mov_m32_imm32(&last_addr, naddr);
539 gencheck_interupt_out(naddr);
540 mov_m32_imm32(&jump_to_address, naddr);
541 mov_m32_imm32((unsigned int*)(&PC), (unsigned int)(dst+1));
542 mov_reg32_imm32(EAX, (unsigned int)jump_to_func);
547 void genjal_idle(void)
549 #ifdef INTERPRET_JAL_IDLE
550 gencallinterp((unsigned int)cached_interpreter_table.JAL_IDLE, 1);
552 if (((dst->addr & 0xFFF) == 0xFFC &&
553 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
555 gencallinterp((unsigned int)cached_interpreter_table.JAL_IDLE, 1);
559 mov_eax_memoffs32((unsigned int *)(&next_interupt));
560 sub_reg32_m32(EAX, (unsigned int *)(&Count));
561 cmp_reg32_imm8(EAX, 3);
564 and_eax_imm32(0xFFFFFFFC);
565 add_m32_reg32((unsigned int *)(&Count), EAX);
573 cmp_m32_imm32((unsigned int *)(&branch_taken), 0);
578 mov_m32_imm32(&last_addr, dst->addr + (dst-1)->f.i.immediate*4);
579 gencheck_interupt((unsigned int)(dst + (dst-1)->f.i.immediate));
580 jmp(dst->addr + (dst-1)->f.i.immediate*4);
584 mov_m32_imm32(&last_addr, dst->addr + 4);
585 gencheck_interupt((unsigned int)(dst + 1));
592 gencallinterp((unsigned int)cached_interpreter_table.BEQ, 1);
594 if (((dst->addr & 0xFFF) == 0xFFC &&
595 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
597 gencallinterp((unsigned int)cached_interpreter_table.BEQ, 1);
607 void gentest_out(void)
609 cmp_m32_imm32((unsigned int *)(&branch_taken), 0);
614 mov_m32_imm32(&last_addr, dst->addr + (dst-1)->f.i.immediate*4);
615 gencheck_interupt_out(dst->addr + (dst-1)->f.i.immediate*4);
616 mov_m32_imm32(&jump_to_address, dst->addr + (dst-1)->f.i.immediate*4);
617 mov_m32_imm32((unsigned int*)(&PC), (unsigned int)(dst+1));
618 mov_reg32_imm32(EAX, (unsigned int)jump_to_func);
623 mov_m32_imm32(&last_addr, dst->addr + 4);
624 gencheck_interupt((unsigned int)(dst + 1));
628 void genbeq_out(void)
630 #ifdef INTERPRET_BEQ_OUT
631 gencallinterp((unsigned int)cached_interpreter_table.BEQ_OUT, 1);
633 if (((dst->addr & 0xFFF) == 0xFFC &&
634 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
636 gencallinterp((unsigned int)cached_interpreter_table.BEQ_OUT, 1);
646 void gentest_idle(void)
650 reg = lru_register();
653 cmp_m32_imm32((unsigned int *)(&branch_taken), 0);
658 mov_reg32_m32(reg, (unsigned int *)(&next_interupt));
659 sub_reg32_m32(reg, (unsigned int *)(&Count));
660 cmp_reg32_imm8(reg, 5);
663 sub_reg32_imm32(reg, 2); // 6
664 and_reg32_imm32(reg, 0xFFFFFFFC); // 6
665 add_m32_reg32((unsigned int *)(&Count), reg); // 6
670 void genbeq_idle(void)
672 #ifdef INTERPRET_BEQ_IDLE
673 gencallinterp((unsigned int)cached_interpreter_table.BEQ_IDLE, 1);
675 if (((dst->addr & 0xFFF) == 0xFFC &&
676 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
678 gencallinterp((unsigned int)cached_interpreter_table.BEQ_IDLE, 1);
691 gencallinterp((unsigned int)cached_interpreter_table.BNE, 1);
693 if (((dst->addr & 0xFFF) == 0xFFC &&
694 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
696 gencallinterp((unsigned int)cached_interpreter_table.BNE, 1);
706 void genbne_out(void)
708 #ifdef INTERPRET_BNE_OUT
709 gencallinterp((unsigned int)cached_interpreter_table.BNE_OUT, 1);
711 if (((dst->addr & 0xFFF) == 0xFFC &&
712 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
714 gencallinterp((unsigned int)cached_interpreter_table.BNE_OUT, 1);
724 void genbne_idle(void)
726 #ifdef INTERPRET_BNE_IDLE
727 gencallinterp((unsigned int)cached_interpreter_table.BNE_IDLE, 1);
729 if (((dst->addr & 0xFFF) == 0xFFC &&
730 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
732 gencallinterp((unsigned int)cached_interpreter_table.BNE_IDLE, 1);
744 #ifdef INTERPRET_BLEZ
745 gencallinterp((unsigned int)cached_interpreter_table.BLEZ, 1);
747 if (((dst->addr & 0xFFF) == 0xFFC &&
748 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
750 gencallinterp((unsigned int)cached_interpreter_table.BLEZ, 1);
760 void genblez_out(void)
762 #ifdef INTERPRET_BLEZ_OUT
763 gencallinterp((unsigned int)cached_interpreter_table.BLEZ_OUT, 1);
765 if (((dst->addr & 0xFFF) == 0xFFC &&
766 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
768 gencallinterp((unsigned int)cached_interpreter_table.BLEZ_OUT, 1);
778 void genblez_idle(void)
780 #ifdef INTERPRET_BLEZ_IDLE
781 gencallinterp((unsigned int)cached_interpreter_table.BLEZ_IDLE, 1);
783 if (((dst->addr & 0xFFF) == 0xFFC &&
784 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
786 gencallinterp((unsigned int)cached_interpreter_table.BLEZ_IDLE, 1);
798 #ifdef INTERPRET_BGTZ
799 gencallinterp((unsigned int)cached_interpreter_table.BGTZ, 1);
801 if (((dst->addr & 0xFFF) == 0xFFC &&
802 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
804 gencallinterp((unsigned int)cached_interpreter_table.BGTZ, 1);
814 void genbgtz_out(void)
816 #ifdef INTERPRET_BGTZ_OUT
817 gencallinterp((unsigned int)cached_interpreter_table.BGTZ_OUT, 1);
819 if (((dst->addr & 0xFFF) == 0xFFC &&
820 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
822 gencallinterp((unsigned int)cached_interpreter_table.BGTZ_OUT, 1);
832 void genbgtz_idle(void)
834 #ifdef INTERPRET_BGTZ_IDLE
835 gencallinterp((unsigned int)cached_interpreter_table.BGTZ_IDLE, 1);
837 if (((dst->addr & 0xFFF) == 0xFFC &&
838 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
840 gencallinterp((unsigned int)cached_interpreter_table.BGTZ_IDLE, 1);
852 #ifdef INTERPRET_ADDI
853 gencallinterp((unsigned int)cached_interpreter_table.ADDI, 0);
855 int rs = allocate_register((unsigned int *)dst->f.i.rs);
856 int rt = allocate_register_w((unsigned int *)dst->f.i.rt);
858 mov_reg32_reg32(rt, rs);
859 add_reg32_imm32(rt,(int)dst->f.i.immediate);
865 #ifdef INTERPRET_ADDIU
866 gencallinterp((unsigned int)cached_interpreter_table.ADDIU, 0);
868 int rs = allocate_register((unsigned int *)dst->f.i.rs);
869 int rt = allocate_register_w((unsigned int *)dst->f.i.rt);
871 mov_reg32_reg32(rt, rs);
872 add_reg32_imm32(rt,(int)dst->f.i.immediate);
878 #ifdef INTERPRET_SLTI
879 gencallinterp((unsigned int)cached_interpreter_table.SLTI, 0);
881 int rs1 = allocate_64_register1((unsigned int *)dst->f.i.rs);
882 int rs2 = allocate_64_register2((unsigned int *)dst->f.i.rs);
883 int rt = allocate_register_w((unsigned int *)dst->f.i.rt);
884 long long imm = (long long)dst->f.i.immediate;
886 cmp_reg32_imm32(rs2, (unsigned int)(imm >> 32));
889 cmp_reg32_imm32(rs1, (unsigned int)imm); // 6
891 mov_reg32_imm32(rt, 0); // 5
892 jmp_imm_short(5); // 2
893 mov_reg32_imm32(rt, 1); // 5
899 #ifdef INTERPRET_SLTIU
900 gencallinterp((unsigned int)cached_interpreter_table.SLTIU, 0);
902 int rs1 = allocate_64_register1((unsigned int *)dst->f.i.rs);
903 int rs2 = allocate_64_register2((unsigned int *)dst->f.i.rs);
904 int rt = allocate_register_w((unsigned int *)dst->f.i.rt);
905 long long imm = (long long)dst->f.i.immediate;
907 cmp_reg32_imm32(rs2, (unsigned int)(imm >> 32));
910 cmp_reg32_imm32(rs1, (unsigned int)imm); // 6
912 mov_reg32_imm32(rt, 0); // 5
913 jmp_imm_short(5); // 2
914 mov_reg32_imm32(rt, 1); // 5
920 #ifdef INTERPRET_ANDI
921 gencallinterp((unsigned int)cached_interpreter_table.ANDI, 0);
923 int rs = allocate_register((unsigned int *)dst->f.i.rs);
924 int rt = allocate_register_w((unsigned int *)dst->f.i.rt);
926 mov_reg32_reg32(rt, rs);
927 and_reg32_imm32(rt, (unsigned short)dst->f.i.immediate);
934 gencallinterp((unsigned int)cached_interpreter_table.ORI, 0);
936 int rs1 = allocate_64_register1((unsigned int *)dst->f.i.rs);
937 int rs2 = allocate_64_register2((unsigned int *)dst->f.i.rs);
938 int rt1 = allocate_64_register1_w((unsigned int *)dst->f.i.rt);
939 int rt2 = allocate_64_register2_w((unsigned int *)dst->f.i.rt);
941 mov_reg32_reg32(rt1, rs1);
942 mov_reg32_reg32(rt2, rs2);
943 or_reg32_imm32(rt1, (unsigned short)dst->f.i.immediate);
949 #ifdef INTERPRET_XORI
950 gencallinterp((unsigned int)cached_interpreter_table.XORI, 0);
952 int rs1 = allocate_64_register1((unsigned int *)dst->f.i.rs);
953 int rs2 = allocate_64_register2((unsigned int *)dst->f.i.rs);
954 int rt1 = allocate_64_register1_w((unsigned int *)dst->f.i.rt);
955 int rt2 = allocate_64_register2_w((unsigned int *)dst->f.i.rt);
957 mov_reg32_reg32(rt1, rs1);
958 mov_reg32_reg32(rt2, rs2);
959 xor_reg32_imm32(rt1, (unsigned short)dst->f.i.immediate);
966 gencallinterp((unsigned int)cached_interpreter_table.LUI, 0);
968 int rt = allocate_register_w((unsigned int *)dst->f.i.rt);
970 mov_reg32_imm32(rt, (unsigned int)dst->f.i.immediate << 16);
976 cmp_m32_imm32((unsigned int *)(&branch_taken), 0);
982 mov_m32_imm32(&last_addr, dst->addr + (dst-1)->f.i.immediate*4);
983 gencheck_interupt((unsigned int)(dst + (dst-1)->f.i.immediate));
984 jmp(dst->addr + (dst-1)->f.i.immediate*4);
988 genupdate_count(dst->addr+4);
989 mov_m32_imm32(&last_addr, dst->addr + 4);
990 gencheck_interupt((unsigned int)(dst + 1));
996 #ifdef INTERPRET_BEQL
997 gencallinterp((unsigned int)cached_interpreter_table.BEQL, 1);
999 if (((dst->addr & 0xFFF) == 0xFFC &&
1000 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
1002 gencallinterp((unsigned int)cached_interpreter_table.BEQL, 1);
1007 free_all_registers();
1012 void gentestl_out(void)
1014 cmp_m32_imm32((unsigned int *)(&branch_taken), 0);
1020 mov_m32_imm32(&last_addr, dst->addr + (dst-1)->f.i.immediate*4);
1021 gencheck_interupt_out(dst->addr + (dst-1)->f.i.immediate*4);
1022 mov_m32_imm32(&jump_to_address, dst->addr + (dst-1)->f.i.immediate*4);
1023 mov_m32_imm32((unsigned int*)(&PC), (unsigned int)(dst+1));
1024 mov_reg32_imm32(EAX, (unsigned int)jump_to_func);
1029 genupdate_count(dst->addr+4);
1030 mov_m32_imm32(&last_addr, dst->addr + 4);
1031 gencheck_interupt((unsigned int)(dst + 1));
1035 void genbeql_out(void)
1037 #ifdef INTERPRET_BEQL_OUT
1038 gencallinterp((unsigned int)cached_interpreter_table.BEQL_OUT, 1);
1040 if (((dst->addr & 0xFFF) == 0xFFC &&
1041 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
1043 gencallinterp((unsigned int)cached_interpreter_table.BEQL_OUT, 1);
1048 free_all_registers();
1053 void genbeql_idle(void)
1055 #ifdef INTERPRET_BEQL_IDLE
1056 gencallinterp((unsigned int)cached_interpreter_table.BEQL_IDLE, 1);
1058 if (((dst->addr & 0xFFF) == 0xFFC &&
1059 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
1061 gencallinterp((unsigned int)cached_interpreter_table.BEQL_IDLE, 1);
1073 #ifdef INTERPRET_BNEL
1074 gencallinterp((unsigned int)cached_interpreter_table.BNEL, 1);
1076 if (((dst->addr & 0xFFF) == 0xFFC &&
1077 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
1079 gencallinterp((unsigned int)cached_interpreter_table.BNEL, 1);
1084 free_all_registers();
1089 void genbnel_out(void)
1091 #ifdef INTERPRET_BNEL_OUT
1092 gencallinterp((unsigned int)cached_interpreter_table.BNEL_OUT, 1);
1094 if (((dst->addr & 0xFFF) == 0xFFC &&
1095 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
1097 gencallinterp((unsigned int)cached_interpreter_table.BNEL_OUT, 1);
1102 free_all_registers();
1107 void genbnel_idle(void)
1109 #ifdef INTERPRET_BNEL_IDLE
1110 gencallinterp((unsigned int)cached_interpreter_table.BNEL_IDLE, 1);
1112 if (((dst->addr & 0xFFF) == 0xFFC &&
1113 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
1115 gencallinterp((unsigned int)cached_interpreter_table.BNEL_IDLE, 1);
1127 #ifdef INTERPRET_BLEZL
1128 gencallinterp((unsigned int)cached_interpreter_table.BLEZL, 1);
1130 if (((dst->addr & 0xFFF) == 0xFFC &&
1131 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
1133 gencallinterp((unsigned int)cached_interpreter_table.BLEZL, 1);
1138 free_all_registers();
1143 void genblezl_out(void)
1145 #ifdef INTERPRET_BLEZL_OUT
1146 gencallinterp((unsigned int)cached_interpreter_table.BLEZL_OUT, 1);
1148 if (((dst->addr & 0xFFF) == 0xFFC &&
1149 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
1151 gencallinterp((unsigned int)cached_interpreter_table.BLEZL_OUT, 1);
1156 free_all_registers();
1161 void genblezl_idle(void)
1163 #ifdef INTERPRET_BLEZL_IDLE
1164 gencallinterp((unsigned int)cached_interpreter_table.BLEZL_IDLE, 1);
1166 if (((dst->addr & 0xFFF) == 0xFFC &&
1167 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
1169 gencallinterp((unsigned int)cached_interpreter_table.BLEZL_IDLE, 1);
1181 #ifdef INTERPRET_BGTZL
1182 gencallinterp((unsigned int)cached_interpreter_table.BGTZL, 1);
1184 if (((dst->addr & 0xFFF) == 0xFFC &&
1185 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
1187 gencallinterp((unsigned int)cached_interpreter_table.BGTZL, 1);
1192 free_all_registers();
1197 void genbgtzl_out(void)
1199 #ifdef INTERPRET_BGTZL_OUT
1200 gencallinterp((unsigned int)cached_interpreter_table.BGTZL_OUT, 1);
1202 if (((dst->addr & 0xFFF) == 0xFFC &&
1203 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
1205 gencallinterp((unsigned int)cached_interpreter_table.BGTZL_OUT, 1);
1210 free_all_registers();
1215 void genbgtzl_idle(void)
1217 #ifdef INTERPRET_BGTZL_IDLE
1218 gencallinterp((unsigned int)cached_interpreter_table.BGTZL_IDLE, 1);
1220 if (((dst->addr & 0xFFF) == 0xFFC &&
1221 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
1223 gencallinterp((unsigned int)cached_interpreter_table.BGTZL_IDLE, 1);
1235 #ifdef INTERPRET_DADDI
1236 gencallinterp((unsigned int)cached_interpreter_table.DADDI, 0);
1238 int rs1 = allocate_64_register1((unsigned int *)dst->f.i.rs);
1239 int rs2 = allocate_64_register2((unsigned int *)dst->f.i.rs);
1240 int rt1 = allocate_64_register1_w((unsigned int *)dst->f.i.rt);
1241 int rt2 = allocate_64_register2_w((unsigned int *)dst->f.i.rt);
1243 mov_reg32_reg32(rt1, rs1);
1244 mov_reg32_reg32(rt2, rs2);
1245 add_reg32_imm32(rt1, dst->f.i.immediate);
1246 adc_reg32_imm32(rt2, (int)dst->f.i.immediate>>31);
1250 void gendaddiu(void)
1252 #ifdef INTERPRET_DADDIU
1253 gencallinterp((unsigned int)cached_interpreter_table.DADDIU, 0);
1255 int rs1 = allocate_64_register1((unsigned int *)dst->f.i.rs);
1256 int rs2 = allocate_64_register2((unsigned int *)dst->f.i.rs);
1257 int rt1 = allocate_64_register1_w((unsigned int *)dst->f.i.rt);
1258 int rt2 = allocate_64_register2_w((unsigned int *)dst->f.i.rt);
1260 mov_reg32_reg32(rt1, rs1);
1261 mov_reg32_reg32(rt2, rs2);
1262 add_reg32_imm32(rt1, dst->f.i.immediate);
1263 adc_reg32_imm32(rt2, (int)dst->f.i.immediate>>31);
1269 gencallinterp((unsigned int)cached_interpreter_table.LDL, 0);
1274 gencallinterp((unsigned int)cached_interpreter_table.LDR, 0);
1280 gencallinterp((unsigned int)cached_interpreter_table.LB, 0);
1282 free_all_registers();
1284 mov_eax_memoffs32((unsigned int *)dst->f.i.rs);
1285 add_eax_imm32((int)dst->f.i.immediate);
1286 mov_reg32_reg32(EBX, EAX);
1289 and_eax_imm32(0xDF800000);
1290 cmp_eax_imm32(0x80000000);
1294 shr_reg32_imm8(EAX, 16);
1295 mov_reg32_preg32x4pimm32(EAX, EAX, (unsigned int)readmemb);
1296 cmp_reg32_imm32(EAX, (unsigned int)read_rdramb);
1300 mov_m32_imm32((unsigned int *)&PC, (unsigned int)(dst+1)); // 10
1301 mov_m32_reg32((unsigned int *)(&address), EBX); // 6
1302 mov_m32_imm32((unsigned int *)(&rdword), (unsigned int)dst->f.i.rt); // 10
1303 shr_reg32_imm8(EBX, 16); // 3
1304 mov_reg32_preg32x4pimm32(EBX, EBX, (unsigned int)readmemb); // 7
1305 call_reg32(EBX); // 2
1306 movsx_reg32_m8(EAX, (unsigned char *)dst->f.i.rt); // 7
1307 jmp_imm_short(16); // 2
1309 and_reg32_imm32(EBX, 0x7FFFFF); // 6
1310 xor_reg8_imm8(BL, 3); // 3
1311 movsx_reg32_8preg32pimm32(EAX, EBX, (unsigned int)rdram); // 7
1313 set_register_state(EAX, (unsigned int*)dst->f.i.rt, 1);
1320 gencallinterp((unsigned int)cached_interpreter_table.LH, 0);
1322 free_all_registers();
1324 mov_eax_memoffs32((unsigned int *)dst->f.i.rs);
1325 add_eax_imm32((int)dst->f.i.immediate);
1326 mov_reg32_reg32(EBX, EAX);
1329 and_eax_imm32(0xDF800000);
1330 cmp_eax_imm32(0x80000000);
1334 shr_reg32_imm8(EAX, 16);
1335 mov_reg32_preg32x4pimm32(EAX, EAX, (unsigned int)readmemh);
1336 cmp_reg32_imm32(EAX, (unsigned int)read_rdramh);
1340 mov_m32_imm32((unsigned int *)&PC, (unsigned int)(dst+1)); // 10
1341 mov_m32_reg32((unsigned int *)(&address), EBX); // 6
1342 mov_m32_imm32((unsigned int *)(&rdword), (unsigned int)dst->f.i.rt); // 10
1343 shr_reg32_imm8(EBX, 16); // 3
1344 mov_reg32_preg32x4pimm32(EBX, EBX, (unsigned int)readmemh); // 7
1345 call_reg32(EBX); // 2
1346 movsx_reg32_m16(EAX, (unsigned short *)dst->f.i.rt); // 7
1347 jmp_imm_short(16); // 2
1349 and_reg32_imm32(EBX, 0x7FFFFF); // 6
1350 xor_reg8_imm8(BL, 2); // 3
1351 movsx_reg32_16preg32pimm32(EAX, EBX, (unsigned int)rdram); // 7
1353 set_register_state(EAX, (unsigned int*)dst->f.i.rt, 1);
1359 gencallinterp((unsigned int)cached_interpreter_table.LWL, 0);
1365 gencallinterp((unsigned int)cached_interpreter_table.LW, 0);
1367 free_all_registers();
1369 mov_eax_memoffs32((unsigned int *)dst->f.i.rs);
1370 add_eax_imm32((int)dst->f.i.immediate);
1371 mov_reg32_reg32(EBX, EAX);
1374 and_eax_imm32(0xDF800000);
1375 cmp_eax_imm32(0x80000000);
1379 shr_reg32_imm8(EAX, 16);
1380 mov_reg32_preg32x4pimm32(EAX, EAX, (unsigned int)readmem);
1381 cmp_reg32_imm32(EAX, (unsigned int)read_rdram);
1385 mov_m32_imm32((unsigned int *)&PC, (unsigned int)(dst+1)); // 10
1386 mov_m32_reg32((unsigned int *)(&address), EBX); // 6
1387 mov_m32_imm32((unsigned int *)(&rdword), (unsigned int)dst->f.i.rt); // 10
1388 shr_reg32_imm8(EBX, 16); // 3
1389 mov_reg32_preg32x4pimm32(EBX, EBX, (unsigned int)readmem); // 7
1390 call_reg32(EBX); // 2
1391 mov_eax_memoffs32((unsigned int *)(dst->f.i.rt)); // 5
1392 jmp_imm_short(12); // 2
1394 and_reg32_imm32(EBX, 0x7FFFFF); // 6
1395 mov_reg32_preg32pimm32(EAX, EBX, (unsigned int)rdram); // 6
1397 set_register_state(EAX, (unsigned int*)dst->f.i.rt, 1);
1403 #ifdef INTERPRET_LBU
1404 gencallinterp((unsigned int)cached_interpreter_table.LBU, 0);
1406 free_all_registers();
1408 mov_eax_memoffs32((unsigned int *)dst->f.i.rs);
1409 add_eax_imm32((int)dst->f.i.immediate);
1410 mov_reg32_reg32(EBX, EAX);
1413 and_eax_imm32(0xDF800000);
1414 cmp_eax_imm32(0x80000000);
1418 shr_reg32_imm8(EAX, 16);
1419 mov_reg32_preg32x4pimm32(EAX, EAX, (unsigned int)readmemb);
1420 cmp_reg32_imm32(EAX, (unsigned int)read_rdramb);
1424 mov_m32_imm32((unsigned int *)&PC, (unsigned int)(dst+1)); // 10
1425 mov_m32_reg32((unsigned int *)(&address), EBX); // 6
1426 mov_m32_imm32((unsigned int *)(&rdword), (unsigned int)dst->f.i.rt); // 10
1427 shr_reg32_imm8(EBX, 16); // 3
1428 mov_reg32_preg32x4pimm32(EBX, EBX, (unsigned int)readmemb); // 7
1429 call_reg32(EBX); // 2
1430 mov_reg32_m32(EAX, (unsigned int *)dst->f.i.rt); // 6
1431 jmp_imm_short(15); // 2
1433 and_reg32_imm32(EBX, 0x7FFFFF); // 6
1434 xor_reg8_imm8(BL, 3); // 3
1435 mov_reg32_preg32pimm32(EAX, EBX, (unsigned int)rdram); // 6
1437 and_eax_imm32(0xFF);
1439 set_register_state(EAX, (unsigned int*)dst->f.i.rt, 1);
1445 #ifdef INTERPRET_LHU
1446 gencallinterp((unsigned int)cached_interpreter_table.LHU, 0);
1448 free_all_registers();
1450 mov_eax_memoffs32((unsigned int *)dst->f.i.rs);
1451 add_eax_imm32((int)dst->f.i.immediate);
1452 mov_reg32_reg32(EBX, EAX);
1455 and_eax_imm32(0xDF800000);
1456 cmp_eax_imm32(0x80000000);
1460 shr_reg32_imm8(EAX, 16);
1461 mov_reg32_preg32x4pimm32(EAX, EAX, (unsigned int)readmemh);
1462 cmp_reg32_imm32(EAX, (unsigned int)read_rdramh);
1466 mov_m32_imm32((unsigned int *)&PC, (unsigned int)(dst+1)); // 10
1467 mov_m32_reg32((unsigned int *)(&address), EBX); // 6
1468 mov_m32_imm32((unsigned int *)(&rdword), (unsigned int)dst->f.i.rt); // 10
1469 shr_reg32_imm8(EBX, 16); // 3
1470 mov_reg32_preg32x4pimm32(EBX, EBX, (unsigned int)readmemh); // 7
1471 call_reg32(EBX); // 2
1472 mov_reg32_m32(EAX, (unsigned int *)dst->f.i.rt); // 6
1473 jmp_imm_short(15); // 2
1475 and_reg32_imm32(EBX, 0x7FFFFF); // 6
1476 xor_reg8_imm8(BL, 2); // 3
1477 mov_reg32_preg32pimm32(EAX, EBX, (unsigned int)rdram); // 6
1479 and_eax_imm32(0xFFFF);
1481 set_register_state(EAX, (unsigned int*)dst->f.i.rt, 1);
1487 gencallinterp((unsigned int)cached_interpreter_table.LWR, 0);
1492 #ifdef INTERPRET_LWU
1493 gencallinterp((unsigned int)cached_interpreter_table.LWU, 0);
1495 free_all_registers();
1497 mov_eax_memoffs32((unsigned int *)dst->f.i.rs);
1498 add_eax_imm32((int)dst->f.i.immediate);
1499 mov_reg32_reg32(EBX, EAX);
1502 and_eax_imm32(0xDF800000);
1503 cmp_eax_imm32(0x80000000);
1507 shr_reg32_imm8(EAX, 16);
1508 mov_reg32_preg32x4pimm32(EAX, EAX, (unsigned int)readmem);
1509 cmp_reg32_imm32(EAX, (unsigned int)read_rdram);
1513 mov_m32_imm32((unsigned int *)(&PC), (unsigned int)(dst+1)); // 10
1514 mov_m32_reg32((unsigned int *)(&address), EBX); // 6
1515 mov_m32_imm32((unsigned int *)(&rdword), (unsigned int)dst->f.i.rt); // 10
1516 shr_reg32_imm8(EBX, 16); // 3
1517 mov_reg32_preg32x4pimm32(EBX, EBX, (unsigned int)readmem); // 7
1518 call_reg32(EBX); // 2
1519 mov_eax_memoffs32((unsigned int *)(dst->f.i.rt)); // 5
1520 jmp_imm_short(12); // 2
1522 and_reg32_imm32(EBX, 0x7FFFFF); // 6
1523 mov_reg32_preg32pimm32(EAX, EBX, (unsigned int)rdram); // 6
1525 xor_reg32_reg32(EBX, EBX);
1527 set_64_register_state(EAX, EBX, (unsigned int*)dst->f.i.rt, 1);
1534 gencallinterp((unsigned int)cached_interpreter_table.SB, 0);
1536 free_all_registers();
1538 mov_reg8_m8(CL, (unsigned char *)dst->f.i.rt);
1539 mov_eax_memoffs32((unsigned int *)dst->f.i.rs);
1540 add_eax_imm32((int)dst->f.i.immediate);
1541 mov_reg32_reg32(EBX, EAX);
1544 and_eax_imm32(0xDF800000);
1545 cmp_eax_imm32(0x80000000);
1549 shr_reg32_imm8(EAX, 16);
1550 mov_reg32_preg32x4pimm32(EAX, EAX, (unsigned int)writememb);
1551 cmp_reg32_imm32(EAX, (unsigned int)write_rdramb);
1555 mov_m32_imm32((unsigned int *)(&PC), (unsigned int)(dst+1)); // 10
1556 mov_m32_reg32((unsigned int *)(&address), EBX); // 6
1557 mov_m8_reg8((unsigned char *)(&cpu_byte), CL); // 6
1558 shr_reg32_imm8(EBX, 16); // 3
1559 mov_reg32_preg32x4pimm32(EBX, EBX, (unsigned int)writememb); // 7
1560 call_reg32(EBX); // 2
1561 mov_eax_memoffs32((unsigned int *)(&address)); // 5
1562 jmp_imm_short(17); // 2
1564 mov_reg32_reg32(EAX, EBX); // 2
1565 and_reg32_imm32(EBX, 0x7FFFFF); // 6
1566 xor_reg8_imm8(BL, 3); // 3
1567 mov_preg32pimm32_reg8(EBX, (unsigned int)rdram, CL); // 6
1569 mov_reg32_reg32(EBX, EAX);
1570 shr_reg32_imm8(EBX, 12);
1571 cmp_preg32pimm32_imm8(EBX, (unsigned int)invalid_code, 0);
1573 mov_reg32_reg32(ECX, EBX); // 2
1574 shl_reg32_imm8(EBX, 2); // 3
1575 mov_reg32_preg32pimm32(EBX, EBX, (unsigned int)blocks); // 6
1576 mov_reg32_preg32pimm32(EBX, EBX, (int)&actual->block - (int)actual); // 6
1577 and_eax_imm32(0xFFF); // 5
1578 shr_reg32_imm8(EAX, 2); // 3
1579 mov_reg32_imm32(EDX, sizeof(precomp_instr)); // 5
1580 mul_reg32(EDX); // 2
1581 mov_reg32_preg32preg32pimm32(EAX, EAX, EBX, (int)&dst->ops - (int)dst); // 7
1582 cmp_reg32_imm32(EAX, (unsigned int)cached_interpreter_table.NOTCOMPILED); // 6
1584 mov_preg32pimm32_imm8(ECX, (unsigned int)invalid_code, 1); // 7
1591 gencallinterp((unsigned int)cached_interpreter_table.SH, 0);
1593 free_all_registers();
1595 mov_reg16_m16(CX, (unsigned short *)dst->f.i.rt);
1596 mov_eax_memoffs32((unsigned int *)dst->f.i.rs);
1597 add_eax_imm32((int)dst->f.i.immediate);
1598 mov_reg32_reg32(EBX, EAX);
1601 and_eax_imm32(0xDF800000);
1602 cmp_eax_imm32(0x80000000);
1606 shr_reg32_imm8(EAX, 16);
1607 mov_reg32_preg32x4pimm32(EAX, EAX, (unsigned int)writememh);
1608 cmp_reg32_imm32(EAX, (unsigned int)write_rdramh);
1612 mov_m32_imm32((unsigned int *)(&PC), (unsigned int)(dst+1)); // 10
1613 mov_m32_reg32((unsigned int *)(&address), EBX); // 6
1614 mov_m16_reg16((unsigned short *)(&hword), CX); // 7
1615 shr_reg32_imm8(EBX, 16); // 3
1616 mov_reg32_preg32x4pimm32(EBX, EBX, (unsigned int)writememh); // 7
1617 call_reg32(EBX); // 2
1618 mov_eax_memoffs32((unsigned int *)(&address)); // 5
1619 jmp_imm_short(18); // 2
1621 mov_reg32_reg32(EAX, EBX); // 2
1622 and_reg32_imm32(EBX, 0x7FFFFF); // 6
1623 xor_reg8_imm8(BL, 2); // 3
1624 mov_preg32pimm32_reg16(EBX, (unsigned int)rdram, CX); // 7
1626 mov_reg32_reg32(EBX, EAX);
1627 shr_reg32_imm8(EBX, 12);
1628 cmp_preg32pimm32_imm8(EBX, (unsigned int)invalid_code, 0);
1630 mov_reg32_reg32(ECX, EBX); // 2
1631 shl_reg32_imm8(EBX, 2); // 3
1632 mov_reg32_preg32pimm32(EBX, EBX, (unsigned int)blocks); // 6
1633 mov_reg32_preg32pimm32(EBX, EBX, (int)&actual->block - (int)actual); // 6
1634 and_eax_imm32(0xFFF); // 5
1635 shr_reg32_imm8(EAX, 2); // 3
1636 mov_reg32_imm32(EDX, sizeof(precomp_instr)); // 5
1637 mul_reg32(EDX); // 2
1638 mov_reg32_preg32preg32pimm32(EAX, EAX, EBX, (int)&dst->ops - (int)dst); // 7
1639 cmp_reg32_imm32(EAX, (unsigned int)cached_interpreter_table.NOTCOMPILED); // 6
1641 mov_preg32pimm32_imm8(ECX, (unsigned int)invalid_code, 1); // 7
1647 gencallinterp((unsigned int)cached_interpreter_table.SWL, 0);
1653 gencallinterp((unsigned int)cached_interpreter_table.SW, 0);
1655 free_all_registers();
1657 mov_reg32_m32(ECX, (unsigned int *)dst->f.i.rt);
1658 mov_eax_memoffs32((unsigned int *)dst->f.i.rs);
1659 add_eax_imm32((int)dst->f.i.immediate);
1660 mov_reg32_reg32(EBX, EAX);
1663 and_eax_imm32(0xDF800000);
1664 cmp_eax_imm32(0x80000000);
1668 shr_reg32_imm8(EAX, 16);
1669 mov_reg32_preg32x4pimm32(EAX, EAX, (unsigned int)writemem);
1670 cmp_reg32_imm32(EAX, (unsigned int)write_rdram);
1674 mov_m32_imm32((unsigned int *)(&PC), (unsigned int)(dst+1)); // 10
1675 mov_m32_reg32((unsigned int *)(&address), EBX); // 6
1676 mov_m32_reg32((unsigned int *)(&word), ECX); // 6
1677 shr_reg32_imm8(EBX, 16); // 3
1678 mov_reg32_preg32x4pimm32(EBX, EBX, (unsigned int)writemem); // 7
1679 call_reg32(EBX); // 2
1680 mov_eax_memoffs32((unsigned int *)(&address)); // 5
1681 jmp_imm_short(14); // 2
1683 mov_reg32_reg32(EAX, EBX); // 2
1684 and_reg32_imm32(EBX, 0x7FFFFF); // 6
1685 mov_preg32pimm32_reg32(EBX, (unsigned int)rdram, ECX); // 6
1687 mov_reg32_reg32(EBX, EAX);
1688 shr_reg32_imm8(EBX, 12);
1689 cmp_preg32pimm32_imm8(EBX, (unsigned int)invalid_code, 0);
1691 mov_reg32_reg32(ECX, EBX); // 2
1692 shl_reg32_imm8(EBX, 2); // 3
1693 mov_reg32_preg32pimm32(EBX, EBX, (unsigned int)blocks); // 6
1694 mov_reg32_preg32pimm32(EBX, EBX, (int)&actual->block - (int)actual); // 6
1695 and_eax_imm32(0xFFF); // 5
1696 shr_reg32_imm8(EAX, 2); // 3
1697 mov_reg32_imm32(EDX, sizeof(precomp_instr)); // 5
1698 mul_reg32(EDX); // 2
1699 mov_reg32_preg32preg32pimm32(EAX, EAX, EBX, (int)&dst->ops - (int)dst); // 7
1700 cmp_reg32_imm32(EAX, (unsigned int)cached_interpreter_table.NOTCOMPILED); // 6
1702 mov_preg32pimm32_imm8(ECX, (unsigned int)invalid_code, 1); // 7
1708 gencallinterp((unsigned int)cached_interpreter_table.SDL, 0);
1713 gencallinterp((unsigned int)cached_interpreter_table.SDR, 0);
1718 gencallinterp((unsigned int)cached_interpreter_table.SWR, 0);
1721 void gencheck_cop1_unusable(void)
1723 free_all_registers();
1725 test_m32_imm32((unsigned int*)&Status, 0x20000000);
1730 gencallinterp((unsigned int)check_cop1_unusable, 0);
1737 #ifdef INTERPRET_LWC1
1738 gencallinterp((unsigned int)cached_interpreter_table.LWC1, 0);
1740 gencheck_cop1_unusable();
1742 mov_eax_memoffs32((unsigned int *)(®[dst->f.lf.base]));
1743 add_eax_imm32((int)dst->f.lf.offset);
1744 mov_reg32_reg32(EBX, EAX);
1747 and_eax_imm32(0xDF800000);
1748 cmp_eax_imm32(0x80000000);
1752 shr_reg32_imm8(EAX, 16);
1753 mov_reg32_preg32x4pimm32(EAX, EAX, (unsigned int)readmem);
1754 cmp_reg32_imm32(EAX, (unsigned int)read_rdram);
1758 mov_m32_imm32((unsigned int *)(&PC), (unsigned int)(dst+1)); // 10
1759 mov_m32_reg32((unsigned int *)(&address), EBX); // 6
1760 mov_reg32_m32(EDX, (unsigned int*)(®_cop1_simple[dst->f.lf.ft])); // 6
1761 mov_m32_reg32((unsigned int *)(&rdword), EDX); // 6
1762 shr_reg32_imm8(EBX, 16); // 3
1763 mov_reg32_preg32x4pimm32(EBX, EBX, (unsigned int)readmem); // 7
1764 call_reg32(EBX); // 2
1765 jmp_imm_short(20); // 2
1767 and_reg32_imm32(EBX, 0x7FFFFF); // 6
1768 mov_reg32_preg32pimm32(EAX, EBX, (unsigned int)rdram); // 6
1769 mov_reg32_m32(EBX, (unsigned int*)(®_cop1_simple[dst->f.lf.ft])); // 6
1770 mov_preg32_reg32(EBX, EAX); // 2
1776 #ifdef INTERPRET_LDC1
1777 gencallinterp((unsigned int)cached_interpreter_table.LDC1, 0);
1779 gencheck_cop1_unusable();
1781 mov_eax_memoffs32((unsigned int *)(®[dst->f.lf.base]));
1782 add_eax_imm32((int)dst->f.lf.offset);
1783 mov_reg32_reg32(EBX, EAX);
1786 and_eax_imm32(0xDF800000);
1787 cmp_eax_imm32(0x80000000);
1791 shr_reg32_imm8(EAX, 16);
1792 mov_reg32_preg32x4pimm32(EAX, EAX, (unsigned int)readmemd);
1793 cmp_reg32_imm32(EAX, (unsigned int)read_rdramd);
1797 mov_m32_imm32((unsigned int *)(&PC), (unsigned int)(dst+1)); // 10
1798 mov_m32_reg32((unsigned int *)(&address), EBX); // 6
1799 mov_reg32_m32(EDX, (unsigned int*)(®_cop1_double[dst->f.lf.ft])); // 6
1800 mov_m32_reg32((unsigned int *)(&rdword), EDX); // 6
1801 shr_reg32_imm8(EBX, 16); // 3
1802 mov_reg32_preg32x4pimm32(EBX, EBX, (unsigned int)readmemd); // 7
1803 call_reg32(EBX); // 2
1804 jmp_imm_short(32); // 2
1806 and_reg32_imm32(EBX, 0x7FFFFF); // 6
1807 mov_reg32_preg32pimm32(EAX, EBX, ((unsigned int)rdram)+4); // 6
1808 mov_reg32_preg32pimm32(ECX, EBX, ((unsigned int)rdram)); // 6
1809 mov_reg32_m32(EBX, (unsigned int*)(®_cop1_double[dst->f.lf.ft])); // 6
1810 mov_preg32_reg32(EBX, EAX); // 2
1811 mov_preg32pimm32_reg32(EBX, 4, ECX); // 6
1822 gencallinterp((unsigned int)cached_interpreter_table.LD, 0);
1824 free_all_registers();
1826 mov_eax_memoffs32((unsigned int *)dst->f.i.rs);
1827 add_eax_imm32((int)dst->f.i.immediate);
1828 mov_reg32_reg32(EBX, EAX);
1831 and_eax_imm32(0xDF800000);
1832 cmp_eax_imm32(0x80000000);
1836 shr_reg32_imm8(EAX, 16);
1837 mov_reg32_preg32x4pimm32(EAX, EAX, (unsigned int)readmemd);
1838 cmp_reg32_imm32(EAX, (unsigned int)read_rdramd);
1842 mov_m32_imm32((unsigned int *)(&PC), (unsigned int)(dst+1)); // 10
1843 mov_m32_reg32((unsigned int *)(&address), EBX); // 6
1844 mov_m32_imm32((unsigned int *)(&rdword), (unsigned int)dst->f.i.rt); // 10
1845 shr_reg32_imm8(EBX, 16); // 3
1846 mov_reg32_preg32x4pimm32(EBX, EBX, (unsigned int)readmemd); // 7
1847 call_reg32(EBX); // 2
1848 mov_eax_memoffs32((unsigned int *)(dst->f.i.rt)); // 5
1849 mov_reg32_m32(ECX, (unsigned int *)(dst->f.i.rt)+1); // 6
1850 jmp_imm_short(18); // 2
1852 and_reg32_imm32(EBX, 0x7FFFFF); // 6
1853 mov_reg32_preg32pimm32(EAX, EBX, ((unsigned int)rdram)+4); // 6
1854 mov_reg32_preg32pimm32(ECX, EBX, ((unsigned int)rdram)); // 6
1856 set_64_register_state(EAX, ECX, (unsigned int*)dst->f.i.rt, 1);
1862 #ifdef INTERPRET_SWC1
1863 gencallinterp((unsigned int)cached_interpreter_table.SWC1, 0);
1865 gencheck_cop1_unusable();
1867 mov_reg32_m32(EDX, (unsigned int*)(®_cop1_simple[dst->f.lf.ft]));
1868 mov_reg32_preg32(ECX, EDX);
1869 mov_eax_memoffs32((unsigned int *)(®[dst->f.lf.base]));
1870 add_eax_imm32((int)dst->f.lf.offset);
1871 mov_reg32_reg32(EBX, EAX);
1874 and_eax_imm32(0xDF800000);
1875 cmp_eax_imm32(0x80000000);
1879 shr_reg32_imm8(EAX, 16);
1880 mov_reg32_preg32x4pimm32(EAX, EAX, (unsigned int)writemem);
1881 cmp_reg32_imm32(EAX, (unsigned int)write_rdram);
1885 mov_m32_imm32((unsigned int *)(&PC), (unsigned int)(dst+1)); // 10
1886 mov_m32_reg32((unsigned int *)(&address), EBX); // 6
1887 mov_m32_reg32((unsigned int *)(&word), ECX); // 6
1888 shr_reg32_imm8(EBX, 16); // 3
1889 mov_reg32_preg32x4pimm32(EBX, EBX, (unsigned int)writemem); // 7
1890 call_reg32(EBX); // 2
1891 mov_eax_memoffs32((unsigned int *)(&address)); // 5
1892 jmp_imm_short(14); // 2
1894 mov_reg32_reg32(EAX, EBX); // 2
1895 and_reg32_imm32(EBX, 0x7FFFFF); // 6
1896 mov_preg32pimm32_reg32(EBX, (unsigned int)rdram, ECX); // 6
1898 mov_reg32_reg32(EBX, EAX);
1899 shr_reg32_imm8(EBX, 12);
1900 cmp_preg32pimm32_imm8(EBX, (unsigned int)invalid_code, 0);
1902 mov_reg32_reg32(ECX, EBX); // 2
1903 shl_reg32_imm8(EBX, 2); // 3
1904 mov_reg32_preg32pimm32(EBX, EBX, (unsigned int)blocks); // 6
1905 mov_reg32_preg32pimm32(EBX, EBX, (int)&actual->block - (int)actual); // 6
1906 and_eax_imm32(0xFFF); // 5
1907 shr_reg32_imm8(EAX, 2); // 3
1908 mov_reg32_imm32(EDX, sizeof(precomp_instr)); // 5
1909 mul_reg32(EDX); // 2
1910 mov_reg32_preg32preg32pimm32(EAX, EAX, EBX, (int)&dst->ops - (int)dst); // 7
1911 cmp_reg32_imm32(EAX, (unsigned int)cached_interpreter_table.NOTCOMPILED); // 6
1913 mov_preg32pimm32_imm8(ECX, (unsigned int)invalid_code, 1); // 7
1919 #ifdef INTERPRET_SDC1
1920 gencallinterp((unsigned int)cached_interpreter_table.SDC1, 0);
1922 gencheck_cop1_unusable();
1924 mov_reg32_m32(ESI, (unsigned int*)(®_cop1_double[dst->f.lf.ft]));
1925 mov_reg32_preg32(ECX, ESI);
1926 mov_reg32_preg32pimm32(EDX, ESI, 4);
1927 mov_eax_memoffs32((unsigned int *)(®[dst->f.lf.base]));
1928 add_eax_imm32((int)dst->f.lf.offset);
1929 mov_reg32_reg32(EBX, EAX);
1932 and_eax_imm32(0xDF800000);
1933 cmp_eax_imm32(0x80000000);
1937 shr_reg32_imm8(EAX, 16);
1938 mov_reg32_preg32x4pimm32(EAX, EAX, (unsigned int)writememd);
1939 cmp_reg32_imm32(EAX, (unsigned int)write_rdramd);
1943 mov_m32_imm32((unsigned int *)(&PC), (unsigned int)(dst+1)); // 10
1944 mov_m32_reg32((unsigned int *)(&address), EBX); // 6
1945 mov_m32_reg32((unsigned int *)(&dword), ECX); // 6
1946 mov_m32_reg32((unsigned int *)(&dword)+1, EDX); // 6
1947 shr_reg32_imm8(EBX, 16); // 3
1948 mov_reg32_preg32x4pimm32(EBX, EBX, (unsigned int)writememd); // 7
1949 call_reg32(EBX); // 2
1950 mov_eax_memoffs32((unsigned int *)(&address)); // 5
1951 jmp_imm_short(20); // 2
1953 mov_reg32_reg32(EAX, EBX); // 2
1954 and_reg32_imm32(EBX, 0x7FFFFF); // 6
1955 mov_preg32pimm32_reg32(EBX, ((unsigned int)rdram)+4, ECX); // 6
1956 mov_preg32pimm32_reg32(EBX, ((unsigned int)rdram)+0, EDX); // 6
1958 mov_reg32_reg32(EBX, EAX);
1959 shr_reg32_imm8(EBX, 12);
1960 cmp_preg32pimm32_imm8(EBX, (unsigned int)invalid_code, 0);
1962 mov_reg32_reg32(ECX, EBX); // 2
1963 shl_reg32_imm8(EBX, 2); // 3
1964 mov_reg32_preg32pimm32(EBX, EBX, (unsigned int)blocks); // 6
1965 mov_reg32_preg32pimm32(EBX, EBX, (int)&actual->block - (int)actual); // 6
1966 and_eax_imm32(0xFFF); // 5
1967 shr_reg32_imm8(EAX, 2); // 3
1968 mov_reg32_imm32(EDX, sizeof(precomp_instr)); // 5
1969 mul_reg32(EDX); // 2
1970 mov_reg32_preg32preg32pimm32(EAX, EAX, EBX, (int)&dst->ops - (int)dst); // 7
1971 cmp_reg32_imm32(EAX, (unsigned int)cached_interpreter_table.NOTCOMPILED); // 6
1973 mov_preg32pimm32_imm8(ECX, (unsigned int)invalid_code, 1); // 7
1980 gencallinterp((unsigned int)cached_interpreter_table.SD, 0);
1982 free_all_registers();
1985 mov_reg32_m32(ECX, (unsigned int *)dst->f.i.rt);
1986 mov_reg32_m32(EDX, ((unsigned int *)dst->f.i.rt)+1);
1987 mov_eax_memoffs32((unsigned int *)dst->f.i.rs);
1988 add_eax_imm32((int)dst->f.i.immediate);
1989 mov_reg32_reg32(EBX, EAX);
1992 and_eax_imm32(0xDF800000);
1993 cmp_eax_imm32(0x80000000);
1997 shr_reg32_imm8(EAX, 16);
1998 mov_reg32_preg32x4pimm32(EAX, EAX, (unsigned int)writememd);
1999 cmp_reg32_imm32(EAX, (unsigned int)write_rdramd);
2003 mov_m32_imm32((unsigned int *)(&PC), (unsigned int)(dst+1)); // 10
2004 mov_m32_reg32((unsigned int *)(&address), EBX); // 6
2005 mov_m32_reg32((unsigned int *)(&dword), ECX); // 6
2006 mov_m32_reg32((unsigned int *)(&dword)+1, EDX); // 6
2007 shr_reg32_imm8(EBX, 16); // 3
2008 mov_reg32_preg32x4pimm32(EBX, EBX, (unsigned int)writememd); // 7
2009 call_reg32(EBX); // 2
2010 mov_eax_memoffs32((unsigned int *)(&address)); // 5
2011 jmp_imm_short(20); // 2
2013 mov_reg32_reg32(EAX, EBX); // 2
2014 and_reg32_imm32(EBX, 0x7FFFFF); // 6
2015 mov_preg32pimm32_reg32(EBX, ((unsigned int)rdram)+4, ECX); // 6
2016 mov_preg32pimm32_reg32(EBX, ((unsigned int)rdram)+0, EDX); // 6
2018 mov_reg32_reg32(EBX, EAX);
2019 shr_reg32_imm8(EBX, 12);
2020 cmp_preg32pimm32_imm8(EBX, (unsigned int)invalid_code, 0);
2022 mov_reg32_reg32(ECX, EBX); // 2
2023 shl_reg32_imm8(EBX, 2); // 3
2024 mov_reg32_preg32pimm32(EBX, EBX, (unsigned int)blocks); // 6
2025 mov_reg32_preg32pimm32(EBX, EBX, (int)&actual->block - (int)actual); // 6
2026 and_eax_imm32(0xFFF); // 5
2027 shr_reg32_imm8(EAX, 2); // 3
2028 mov_reg32_imm32(EDX, sizeof(precomp_instr)); // 5
2029 mul_reg32(EDX); // 2
2030 mov_reg32_preg32preg32pimm32(EAX, EAX, EBX, (int)&dst->ops - (int)dst); // 7
2031 cmp_reg32_imm32(EAX, (unsigned int)cached_interpreter_table.NOTCOMPILED); // 6
2033 mov_preg32pimm32_imm8(ECX, (unsigned int)invalid_code, 1); // 7
2039 gencallinterp((unsigned int)cached_interpreter_table.LL, 0);
2044 gencallinterp((unsigned int)cached_interpreter_table.SC, 0);