1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - gr4300.c *
3 * Mupen64Plus homepage: http://code.google.com/p/mupen64plus/ *
4 * Copyright (C) 2007 Richard Goedeken (Richard42) *
5 * Copyright (C) 2002 Hacktarux *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
21 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
25 #include "interpret.h"
27 #include "api/debugger.h"
29 #include "r4300/r4300.h"
30 #include "r4300/macros.h"
31 #include "r4300/interupt.h"
32 #include "r4300/ops.h"
33 #include "r4300/recomph.h"
34 #include "r4300/exception.h"
36 #include "memory/memory.h"
38 #if !defined(offsetof)
39 # define offsetof(TYPE,MEMBER) ((unsigned int) &((TYPE*)0)->MEMBER)
42 #if defined(COUNT_INSTR)
43 unsigned int instr_count[132];
44 char instr_name[][10] =
46 "reserved", "NI", "J", "JAL", "BEQ", "BNE", "BLEZ", "BGTZ",
47 "ADDI", "ADDIU", "SLTI", "SLTIU", "ANDI", "ORI", "XORI", "LUI",
48 "BEQL", "BNEL", "BLEZL", "BGTZL", "DADDI", "DADDIU", "LDL", "LDR",
49 "LB", "LH", "LW", "LWL", "LBU", "LHU", "LWU", "LWR",
50 "SB", "SH", "SW", "SWL", "SWR", "SDL", "SDR", "LWC1",
51 "LDC1", "LD", "LL", "SWC1", "SDC1", "SD", "SC", "BLTZ",
52 "BGEZ", "BLTZL", "BGEZL", "BLTZAL", "BGEZAL", "BLTZALL", "BGEZALL", "SLL",
53 "SRL", "SRA", "SLLV", "SRLV", "SRAV", "JR", "JALR", "SYSCALL",
54 "MFHI", "MTHI", "MFLO", "MTLO", "DSLLV", "DSRLV", "DSRAV", "MULT",
55 "MULTU", "DIV", "DIVU", "DMULT", "DMULTU", "DDIV", "DDIVU", "ADD",
56 "ADDU", "SUB", "SUBU", "AND", "OR", "XOR", "NOR", "SLT",
57 "SLTU", "DADD", "DADDU", "DSUB", "DSUBU", "DSLL", "DSRL", "DSRA",
58 "TEQ", "DSLL32", "DSRL32", "DSRA32", "BC1F", "BC1T", "BC1FL", "BC1TL",
59 "TLBWI", "TLBP", "TLBR", "TLBWR", "ERET", "MFC0", "MTC0", "MFC1",
60 "DMFC1", "CFC1", "MTC1", "DMTC1", "CTC1", "f.CVT", "f.CMP", "f.ADD",
61 "f.SUB", "f.MUL", "f.DIV", "f.SQRT", "f.ABS", "f.MOV", "f.NEG", "f.ROUND",
62 "f.TRUNC", "f.CEIL", "f.FLOOR"
64 unsigned int instr_type[131] = { 9, 10, 6, 6, 7, 7, 7, 7, 3, 3, 4, 4, 3, 4, 4, 0,
65 7, 7, 7, 7, 4, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
66 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 7,
67 7, 7, 7, 7, 7, 7, 7, 3, 3, 3, 3, 3, 3, 6, 6, 10,
68 2, 2, 2, 2, 4, 4, 4, 3, 3, 3, 3, 4, 4, 4, 4, 3,
69 3, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
70 8, 4, 4, 4, 7, 7, 7, 7, 10, 10, 10, 10, 8, 2, 2, 2,
71 2, 2, 2, 2, 2, 2, 5, 5, 5, 5, 5, 5, 5, 2, 5, 5,
73 char instr_typename[][20] = { "Load", "Store", "Data move/convert", "32-bit math", "64-bit math", "Float Math",
74 "Jump", "Branch", "Exceptions", "Reserved", "Other" };
77 extern unsigned int op;
79 static precomp_instr fake_instr;
81 static long long debug_reg_storage[8];
86 /* static functions */
88 static void genupdate_count(unsigned int addr)
90 #if !defined(COMPARE_CORE) && !defined(DBG)
91 mov_reg32_imm32(EAX, addr);
92 sub_xreg32_m32rel(EAX, (unsigned int*)(&last_addr));
93 shr_reg32_imm8(EAX, 2);
94 mov_xreg32_m32rel(EDX, (void*)&count_per_op);
96 add_m32rel_xreg32((unsigned int*)(&Count), EAX);
98 mov_reg64_imm64(RAX, (unsigned long long) (dst+1));
99 mov_m64rel_xreg64((unsigned long long *)(&PC), RAX);
100 mov_reg64_imm64(RAX, (unsigned long long)update_count);
105 static void gencheck_interupt(unsigned long long instr_structure)
107 mov_xreg32_m32rel(EAX, (void*)(&next_interupt));
108 cmp_xreg32_m32rel(EAX, (void*)&Count);
112 mov_reg64_imm64(RAX, (unsigned long long) instr_structure);
113 mov_m64rel_xreg64((unsigned long long *)(&PC), RAX);
114 mov_reg64_imm64(RAX, (unsigned long long) gen_interupt);
120 static void gencheck_interupt_out(unsigned int addr)
122 mov_xreg32_m32rel(EAX, (void*)(&next_interupt));
123 cmp_xreg32_m32rel(EAX, (void*)&Count);
127 mov_m32rel_imm32((unsigned int*)(&fake_instr.addr), addr);
128 mov_reg64_imm64(RAX, (unsigned long long) (&fake_instr));
129 mov_m64rel_xreg64((unsigned long long *)(&PC), RAX);
130 mov_reg64_imm64(RAX, (unsigned long long) gen_interupt);
136 static void genbeq_test(void)
138 int rs_64bit = is64((unsigned int *)dst->f.i.rs);
139 int rt_64bit = is64((unsigned int *)dst->f.i.rt);
141 if (rs_64bit == 0 && rt_64bit == 0)
143 int rs = allocate_register_32((unsigned int *)dst->f.i.rs);
144 int rt = allocate_register_32((unsigned int *)dst->f.i.rt);
146 cmp_reg32_reg32(rs, rt);
147 sete_m8rel((unsigned char *) &branch_taken);
149 else if (rs_64bit == -1)
151 int rt = allocate_register_64((unsigned long long *)dst->f.i.rt);
153 cmp_xreg64_m64rel(rt, (unsigned long long *) dst->f.i.rs);
154 sete_m8rel((unsigned char *) &branch_taken);
156 else if (rt_64bit == -1)
158 int rs = allocate_register_64((unsigned long long *)dst->f.i.rs);
160 cmp_xreg64_m64rel(rs, (unsigned long long *)dst->f.i.rt);
161 sete_m8rel((unsigned char *) &branch_taken);
165 int rs = allocate_register_64((unsigned long long *)dst->f.i.rs);
166 int rt = allocate_register_64((unsigned long long *)dst->f.i.rt);
167 cmp_reg64_reg64(rs, rt);
168 sete_m8rel((unsigned char *) &branch_taken);
172 static void genbne_test(void)
174 int rs_64bit = is64((unsigned int *)dst->f.i.rs);
175 int rt_64bit = is64((unsigned int *)dst->f.i.rt);
177 if (rs_64bit == 0 && rt_64bit == 0)
179 int rs = allocate_register_32((unsigned int *)dst->f.i.rs);
180 int rt = allocate_register_32((unsigned int *)dst->f.i.rt);
182 cmp_reg32_reg32(rs, rt);
183 setne_m8rel((unsigned char *) &branch_taken);
185 else if (rs_64bit == -1)
187 int rt = allocate_register_64((unsigned long long *) dst->f.i.rt);
189 cmp_xreg64_m64rel(rt, (unsigned long long *)dst->f.i.rs);
190 setne_m8rel((unsigned char *) &branch_taken);
192 else if (rt_64bit == -1)
194 int rs = allocate_register_64((unsigned long long *) dst->f.i.rs);
196 cmp_xreg64_m64rel(rs, (unsigned long long *)dst->f.i.rt);
197 setne_m8rel((unsigned char *) &branch_taken);
201 int rs = allocate_register_64((unsigned long long *)dst->f.i.rs);
202 int rt = allocate_register_64((unsigned long long *)dst->f.i.rt);
204 cmp_reg64_reg64(rs, rt);
205 setne_m8rel((unsigned char *) &branch_taken);
209 static void genblez_test(void)
211 int rs_64bit = is64((unsigned int *)dst->f.i.rs);
215 int rs = allocate_register_32((unsigned int *)dst->f.i.rs);
217 cmp_reg32_imm32(rs, 0);
218 setle_m8rel((unsigned char *) &branch_taken);
222 int rs = allocate_register_64((unsigned long long *)dst->f.i.rs);
224 cmp_reg64_imm8(rs, 0);
225 setle_m8rel((unsigned char *) &branch_taken);
229 static void genbgtz_test(void)
231 int rs_64bit = is64((unsigned int *)dst->f.i.rs);
235 int rs = allocate_register_32((unsigned int *)dst->f.i.rs);
237 cmp_reg32_imm32(rs, 0);
238 setg_m8rel((unsigned char *) &branch_taken);
242 int rs = allocate_register_64((unsigned long long *)dst->f.i.rs);
244 cmp_reg64_imm8(rs, 0);
245 setg_m8rel((unsigned char *) &branch_taken);
249 static void ld_register_alloc(int *pGpr1, int *pGpr2, int *pBase1, int *pBase2)
251 int gpr1, gpr2, base1, base2 = 0;
254 free_registers_move_start(); // to maintain parity with 32-bit core
257 if (dst->f.i.rs == dst->f.i.rt)
259 allocate_register_32((unsigned int*)dst->f.r.rs); // tell regcache we need to read RS register here
260 gpr1 = allocate_register_32_w((unsigned int*)dst->f.r.rt); // tell regcache we will modify RT register during this instruction
261 gpr2 = lock_register(lru_register()); // free and lock least recently used register for usage here
262 add_reg32_imm32(gpr1, (int)dst->f.i.immediate);
263 mov_reg32_reg32(gpr2, gpr1);
267 gpr2 = allocate_register_32((unsigned int*)dst->f.r.rs); // tell regcache we need to read RS register here
268 gpr1 = allocate_register_32_w((unsigned int*)dst->f.r.rt); // tell regcache we will modify RT register during this instruction
269 free_register(gpr2); // write out gpr2 if dirty because I'm going to trash it right now
270 add_reg32_imm32(gpr2, (int)dst->f.i.immediate);
271 mov_reg32_reg32(gpr1, gpr2);
272 lock_register(gpr2); // lock the freed gpr2 it so it doesn't get returned in the lru query
274 base1 = lock_register(lru_base_register()); // get another lru register
277 base2 = lock_register(lru_base_register()); // and another one if necessary
278 unlock_register(base2);
280 unlock_register(base1); // unlock the locked registers (they are
281 unlock_register(gpr2);
282 set_register_state(gpr1, NULL, 0, 0); // clear gpr1 state because it hasn't been written yet -
283 // we don't want it to be pushed/popped around read_rdramX call
291 /* global functions */
293 void gennotcompiled(void)
295 free_registers_move_start();
297 mov_reg64_imm64(RAX, (unsigned long long) dst);
298 mov_memoffs64_rax((unsigned long long *) &PC); /* RIP-relative will not work here */
299 mov_reg64_imm64(RAX, (unsigned long long) cached_interpreter_table.NOTCOMPILED);
303 void genlink_subblock(void)
305 free_all_registers();
312 free_all_registers();
314 mov_memoffs64_rax((unsigned long long *) &debug_reg_storage);
315 mov_reg64_imm64(RAX, (unsigned long long) &debug_reg_storage);
316 mov_preg64pimm8_reg64(RAX, 8, RBX);
317 mov_preg64pimm8_reg64(RAX, 16, RCX);
318 mov_preg64pimm8_reg64(RAX, 24, RDX);
319 mov_preg64pimm8_reg64(RAX, 32, RSP);
320 mov_preg64pimm8_reg64(RAX, 40, RBP);
321 mov_preg64pimm8_reg64(RAX, 48, RSI);
322 mov_preg64pimm8_reg64(RAX, 56, RDI);
324 mov_reg64_imm64(RAX, (unsigned long long) dst);
325 mov_memoffs64_rax((unsigned long long *) &PC);
326 mov_reg32_imm32(EAX, (unsigned int) src);
327 mov_memoffs32_eax((unsigned int *) &op);
328 mov_reg64_imm64(RAX, (unsigned long long) CoreCompareCallback);
331 mov_reg64_imm64(RAX, (unsigned long long) &debug_reg_storage);
332 mov_reg64_preg64pimm8(RDI, RAX, 56);
333 mov_reg64_preg64pimm8(RSI, RAX, 48);
334 mov_reg64_preg64pimm8(RBP, RAX, 40);
335 mov_reg64_preg64pimm8(RSP, RAX, 32);
336 mov_reg64_preg64pimm8(RDX, RAX, 24);
337 mov_reg64_preg64pimm8(RCX, RAX, 16);
338 mov_reg64_preg64pimm8(RBX, RAX, 8);
339 mov_reg64_preg64(RAX, RAX);
343 void gencallinterp(unsigned long addr, int jump)
345 free_registers_move_start();
348 mov_m32rel_imm32((unsigned int*)(&dyna_interp), 1);
350 mov_reg64_imm64(RAX, (unsigned long long) dst);
351 mov_m64rel_xreg64((unsigned long long *)(&PC), RAX);
352 mov_reg64_imm64(RAX, addr);
357 mov_m32rel_imm32((unsigned int*)(&dyna_interp), 0);
358 mov_reg64_imm64(RAX, (unsigned long long)dyna_jump);
363 void gendelayslot(void)
365 mov_m32rel_imm32((void*)(&delay_slot), 1);
368 free_all_registers();
369 genupdate_count(dst->addr+4);
371 mov_m32rel_imm32((void*)(&delay_slot), 0);
376 #if defined(COUNT_INSTR)
377 inc_m32rel(&instr_count[1]);
379 gencallinterp((unsigned long long)cached_interpreter_table.NI, 0);
382 void genreserved(void)
384 #if defined(COUNT_INSTR)
385 inc_m32rel(&instr_count[0]);
387 gencallinterp((unsigned long long)cached_interpreter_table.RESERVED, 0);
390 void genfin_block(void)
392 gencallinterp((unsigned long long)cached_interpreter_table.FIN_BLOCK, 0);
395 void gencheck_interupt_reg(void) // addr is in EAX
397 mov_xreg32_m32rel(EBX, (void*)&next_interupt);
398 cmp_xreg32_m32rel(EBX, (void*)&Count);
402 mov_m32rel_xreg32((unsigned int*)(&fake_instr.addr), EAX);
403 mov_reg64_imm64(RAX, (unsigned long long) (&fake_instr));
404 mov_m64rel_xreg64((unsigned long long *)(&PC), RAX);
405 mov_reg64_imm64(RAX, (unsigned long long) gen_interupt);
417 #if defined(COUNT_INSTR)
418 inc_m32rel(&instr_count[2]);
421 gencallinterp((unsigned long long)cached_interpreter_table.J, 1);
425 if (((dst->addr & 0xFFF) == 0xFFC &&
426 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
428 gencallinterp((unsigned long long)cached_interpreter_table.J, 1);
433 naddr = ((dst-1)->f.j.inst_index<<2) | (dst->addr & 0xF0000000);
435 mov_m32rel_imm32((void*)(&last_addr), naddr);
436 gencheck_interupt((unsigned long long) &actual->block[(naddr-actual->start)/4]);
443 #if defined(COUNT_INSTR)
444 inc_m32rel(&instr_count[2]);
446 #ifdef INTERPRET_J_OUT
447 gencallinterp((unsigned long long)cached_interpreter_table.J_OUT, 1);
451 if (((dst->addr & 0xFFF) == 0xFFC &&
452 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
454 gencallinterp((unsigned long long)cached_interpreter_table.J_OUT, 1);
459 naddr = ((dst-1)->f.j.inst_index<<2) | (dst->addr & 0xF0000000);
461 mov_m32rel_imm32((void*)(&last_addr), naddr);
462 gencheck_interupt_out(naddr);
463 mov_m32rel_imm32(&jump_to_address, naddr);
464 mov_reg64_imm64(RAX, (unsigned long long) (dst+1));
465 mov_m64rel_xreg64((unsigned long long *)(&PC), RAX);
466 mov_reg64_imm64(RAX, (unsigned long long)jump_to_func);
473 #if defined(COUNT_INSTR)
474 inc_m32rel(&instr_count[2]);
476 #ifdef INTERPRET_J_IDLE
477 gencallinterp((unsigned long long)cached_interpreter_table.J_IDLE, 1);
479 if (((dst->addr & 0xFFF) == 0xFFC &&
480 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
482 gencallinterp((unsigned long long)cached_interpreter_table.J_IDLE, 1);
486 mov_xreg32_m32rel(EAX, (unsigned int *)(&next_interupt));
487 sub_xreg32_m32rel(EAX, (unsigned int *)(&Count));
488 cmp_reg32_imm8(EAX, 3);
491 and_eax_imm32(0xFFFFFFFC); // 5
492 add_m32rel_xreg32((unsigned int *)(&Count), EAX); // 7
500 #if defined(COUNT_INSTR)
501 inc_m32rel(&instr_count[3]);
504 gencallinterp((unsigned long long)cached_interpreter_table.JAL, 1);
508 if (((dst->addr & 0xFFF) == 0xFFC &&
509 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
511 gencallinterp((unsigned long long)cached_interpreter_table.JAL, 1);
517 mov_m32rel_imm32((unsigned int *)(reg + 31), dst->addr + 4);
518 if (((dst->addr + 4) & 0x80000000))
519 mov_m32rel_imm32((unsigned int *)(®[31])+1, 0xFFFFFFFF);
521 mov_m32rel_imm32((unsigned int *)(®[31])+1, 0);
523 naddr = ((dst-1)->f.j.inst_index<<2) | (dst->addr & 0xF0000000);
525 mov_m32rel_imm32((void*)(&last_addr), naddr);
526 gencheck_interupt((unsigned long long) &actual->block[(naddr-actual->start)/4]);
531 void genjal_out(void)
533 #if defined(COUNT_INSTR)
534 inc_m32rel(&instr_count[3]);
536 #ifdef INTERPRET_JAL_OUT
537 gencallinterp((unsigned long long)cached_interpreter_table.JAL_OUT, 1);
541 if (((dst->addr & 0xFFF) == 0xFFC &&
542 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
544 gencallinterp((unsigned long long)cached_interpreter_table.JAL_OUT, 1);
550 mov_m32rel_imm32((unsigned int *)(reg + 31), dst->addr + 4);
551 if (((dst->addr + 4) & 0x80000000))
552 mov_m32rel_imm32((unsigned int *)(®[31])+1, 0xFFFFFFFF);
554 mov_m32rel_imm32((unsigned int *)(®[31])+1, 0);
556 naddr = ((dst-1)->f.j.inst_index<<2) | (dst->addr & 0xF0000000);
558 mov_m32rel_imm32((void*)(&last_addr), naddr);
559 gencheck_interupt_out(naddr);
560 mov_m32rel_imm32(&jump_to_address, naddr);
561 mov_reg64_imm64(RAX, (unsigned long long) (dst+1));
562 mov_m64rel_xreg64((unsigned long long *)(&PC), RAX);
563 mov_reg64_imm64(RAX, (unsigned long long) jump_to_func);
568 void genjal_idle(void)
570 #if defined(COUNT_INSTR)
571 inc_m32rel(&instr_count[3]);
573 #ifdef INTERPRET_JAL_IDLE
574 gencallinterp((unsigned long long)cached_interpreter_table.JAL_IDLE, 1);
576 if (((dst->addr & 0xFFF) == 0xFFC &&
577 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
579 gencallinterp((unsigned long long)cached_interpreter_table.JAL_IDLE, 1);
583 mov_xreg32_m32rel(EAX, (unsigned int *)(&next_interupt));
584 sub_xreg32_m32rel(EAX, (unsigned int *)(&Count));
585 cmp_reg32_imm8(EAX, 3);
588 and_eax_imm32(0xFFFFFFFC); // 5
589 add_m32rel_xreg32((unsigned int *)(&Count), EAX); // 7
597 cmp_m32rel_imm32((unsigned int *)(&branch_taken), 0);
601 mov_m32rel_imm32((void*)(&last_addr), dst->addr + (dst-1)->f.i.immediate*4);
602 gencheck_interupt((unsigned long long) (dst + (dst-1)->f.i.immediate));
603 jmp(dst->addr + (dst-1)->f.i.immediate*4);
607 mov_m32rel_imm32((void*)(&last_addr), dst->addr + 4);
608 gencheck_interupt((unsigned long long)(dst + 1));
614 #if defined(COUNT_INSTR)
615 inc_m32rel(&instr_count[4]);
618 gencallinterp((unsigned long long)cached_interpreter_table.BEQ, 1);
620 if (((dst->addr & 0xFFF) == 0xFFC &&
621 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
623 gencallinterp((unsigned long long)cached_interpreter_table.BEQ, 1);
633 void gentest_out(void)
635 cmp_m32rel_imm32((unsigned int *)(&branch_taken), 0);
639 mov_m32rel_imm32((void*)(&last_addr), dst->addr + (dst-1)->f.i.immediate*4);
640 gencheck_interupt_out(dst->addr + (dst-1)->f.i.immediate*4);
641 mov_m32rel_imm32(&jump_to_address, dst->addr + (dst-1)->f.i.immediate*4);
642 mov_reg64_imm64(RAX, (unsigned long long) (dst+1));
643 mov_m64rel_xreg64((unsigned long long *)(&PC), RAX);
644 mov_reg64_imm64(RAX, (unsigned long long) jump_to_func);
648 mov_m32rel_imm32((void*)(&last_addr), dst->addr + 4);
649 gencheck_interupt((unsigned long long) (dst + 1));
653 void genbeq_out(void)
655 #if defined(COUNT_INSTR)
656 inc_m32rel(&instr_count[4]);
658 #ifdef INTERPRET_BEQ_OUT
659 gencallinterp((unsigned long long)cached_interpreter_table.BEQ_OUT, 1);
661 if (((dst->addr & 0xFFF) == 0xFFC &&
662 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
664 gencallinterp((unsigned long long)cached_interpreter_table.BEQ_OUT, 1);
674 void gentest_idle(void)
678 reg = lru_register();
681 cmp_m32rel_imm32((unsigned int *)(&branch_taken), 0);
685 mov_xreg32_m32rel(reg, (unsigned int *)(&next_interupt));
686 sub_xreg32_m32rel(reg, (unsigned int *)(&Count));
687 cmp_reg32_imm8(reg, 3);
691 and_reg32_imm32(reg, 0xFFFFFFFC);
692 add_m32rel_xreg32((unsigned int *)(&Count), reg);
698 void genbeq_idle(void)
700 #ifdef INTERPRET_BEQ_IDLE
701 gencallinterp((unsigned long long)cached_interpreter_table.BEQ_IDLE, 1);
703 if (((dst->addr & 0xFFF) == 0xFFC &&
704 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
706 gencallinterp((unsigned long long)cached_interpreter_table.BEQ_IDLE, 1);
718 #if defined(COUNT_INSTR)
719 inc_m32rel(&instr_count[5]);
722 gencallinterp((unsigned long long)cached_interpreter_table.BNE, 1);
724 if (((dst->addr & 0xFFF) == 0xFFC &&
725 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
727 gencallinterp((unsigned long long)cached_interpreter_table.BNE, 1);
737 void genbne_out(void)
739 #if defined(COUNT_INSTR)
740 inc_m32rel(&instr_count[5]);
742 #ifdef INTERPRET_BNE_OUT
743 gencallinterp((unsigned long long)cached_interpreter_table.BNE_OUT, 1);
745 if (((dst->addr & 0xFFF) == 0xFFC &&
746 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
748 gencallinterp((unsigned long long)cached_interpreter_table.BNE_OUT, 1);
758 void genbne_idle(void)
760 #ifdef INTERPRET_BNE_IDLE
761 gencallinterp((unsigned long long)cached_interpreter_table.BNE_IDLE, 1);
763 if (((dst->addr & 0xFFF) == 0xFFC &&
764 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
766 gencallinterp((unsigned long long)cached_interpreter_table.BNE_IDLE, 1);
778 #if defined(COUNT_INSTR)
779 inc_m32rel(&instr_count[6]);
781 #ifdef INTERPRET_BLEZ
782 gencallinterp((unsigned long long)cached_interpreter_table.BLEZ, 1);
784 if (((dst->addr & 0xFFF) == 0xFFC &&
785 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
787 gencallinterp((unsigned long long)cached_interpreter_table.BLEZ, 1);
797 void genblez_out(void)
799 #if defined(COUNT_INSTR)
800 inc_m32rel(&instr_count[6]);
802 #ifdef INTERPRET_BLEZ_OUT
803 gencallinterp((unsigned long long)cached_interpreter_table.BLEZ_OUT, 1);
805 if (((dst->addr & 0xFFF) == 0xFFC &&
806 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
808 gencallinterp((unsigned long long)cached_interpreter_table.BLEZ_OUT, 1);
818 void genblez_idle(void)
820 #ifdef INTERPRET_BLEZ_IDLE
821 gencallinterp((unsigned long long)cached_interpreter_table.BLEZ_IDLE, 1);
823 if (((dst->addr & 0xFFF) == 0xFFC &&
824 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
826 gencallinterp((unsigned long long)cached_interpreter_table.BLEZ_IDLE, 1);
838 #if defined(COUNT_INSTR)
839 inc_m32rel(&instr_count[7]);
841 #ifdef INTERPRET_BGTZ
842 gencallinterp((unsigned long long)cached_interpreter_table.BGTZ, 1);
844 if (((dst->addr & 0xFFF) == 0xFFC &&
845 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
847 gencallinterp((unsigned long long)cached_interpreter_table.BGTZ, 1);
857 void genbgtz_out(void)
859 #if defined(COUNT_INSTR)
860 inc_m32rel(&instr_count[7]);
862 #ifdef INTERPRET_BGTZ_OUT
863 gencallinterp((unsigned long long)cached_interpreter_table.BGTZ_OUT, 1);
865 if (((dst->addr & 0xFFF) == 0xFFC &&
866 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
868 gencallinterp((unsigned long long)cached_interpreter_table.BGTZ_OUT, 1);
878 void genbgtz_idle(void)
880 #ifdef INTERPRET_BGTZ_IDLE
881 gencallinterp((unsigned long long)cached_interpreter_table.BGTZ_IDLE, 1);
883 if (((dst->addr & 0xFFF) == 0xFFC &&
884 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
886 gencallinterp((unsigned long long)cached_interpreter_table.BGTZ_IDLE, 1);
898 #if defined(COUNT_INSTR)
899 inc_m32rel(&instr_count[8]);
901 #ifdef INTERPRET_ADDI
902 gencallinterp((unsigned long long)cached_interpreter_table.ADDI, 0);
904 int rs = allocate_register_32((unsigned int *)dst->f.i.rs);
905 int rt = allocate_register_32_w((unsigned int *)dst->f.i.rt);
907 mov_reg32_reg32(rt, rs);
908 add_reg32_imm32(rt,(int)dst->f.i.immediate);
914 #if defined(COUNT_INSTR)
915 inc_m32rel(&instr_count[9]);
917 #ifdef INTERPRET_ADDIU
918 gencallinterp((unsigned long long)cached_interpreter_table.ADDIU, 0);
920 int rs = allocate_register_32((unsigned int *)dst->f.i.rs);
921 int rt = allocate_register_32_w((unsigned int *)dst->f.i.rt);
923 mov_reg32_reg32(rt, rs);
924 add_reg32_imm32(rt,(int)dst->f.i.immediate);
930 #if defined(COUNT_INSTR)
931 inc_m32rel(&instr_count[10]);
933 #ifdef INTERPRET_SLTI
934 gencallinterp((unsigned long long)cached_interpreter_table.SLTI, 0);
936 int rs = allocate_register_64((unsigned long long *) dst->f.i.rs);
937 int rt = allocate_register_64_w((unsigned long long *) dst->f.i.rt);
938 int imm = (int) dst->f.i.immediate;
940 cmp_reg64_imm32(rs, imm);
942 and_reg64_imm8(rt, 1);
948 #if defined(COUNT_INSTR)
949 inc_m32rel(&instr_count[11]);
951 #ifdef INTERPRET_SLTIU
952 gencallinterp((unsigned long long)cached_interpreter_table.SLTIU, 0);
954 int rs = allocate_register_64((unsigned long long *)dst->f.i.rs);
955 int rt = allocate_register_64_w((unsigned long long *)dst->f.i.rt);
956 int imm = (int) dst->f.i.immediate;
958 cmp_reg64_imm32(rs, imm);
960 and_reg64_imm8(rt, 1);
966 #if defined(COUNT_INSTR)
967 inc_m32rel(&instr_count[12]);
969 #ifdef INTERPRET_ANDI
970 gencallinterp((unsigned long long)cached_interpreter_table.ANDI, 0);
972 int rs = allocate_register_64((unsigned long long *)dst->f.i.rs);
973 int rt = allocate_register_64_w((unsigned long long *)dst->f.i.rt);
975 mov_reg64_reg64(rt, rs);
976 and_reg64_imm32(rt, (unsigned short)dst->f.i.immediate);
982 #if defined(COUNT_INSTR)
983 inc_m32rel(&instr_count[13]);
986 gencallinterp((unsigned long long)cached_interpreter_table.ORI, 0);
988 int rs = allocate_register_64((unsigned long long *) dst->f.i.rs);
989 int rt = allocate_register_64_w((unsigned long long *) dst->f.i.rt);
991 mov_reg64_reg64(rt, rs);
992 or_reg64_imm32(rt, (unsigned short)dst->f.i.immediate);
998 #if defined(COUNT_INSTR)
999 inc_m32rel(&instr_count[14]);
1001 #ifdef INTERPRET_XORI
1002 gencallinterp((unsigned long long)cached_interpreter_table.XORI, 0);
1004 int rs = allocate_register_64((unsigned long long *)dst->f.i.rs);
1005 int rt = allocate_register_64_w((unsigned long long *)dst->f.i.rt);
1007 mov_reg64_reg64(rt, rs);
1008 xor_reg64_imm32(rt, (unsigned short)dst->f.i.immediate);
1014 #if defined(COUNT_INSTR)
1015 inc_m32rel(&instr_count[15]);
1017 #ifdef INTERPRET_LUI
1018 gencallinterp((unsigned long long)cached_interpreter_table.LUI, 0);
1020 int rt = allocate_register_32_w((unsigned int *)dst->f.i.rt);
1022 mov_reg32_imm32(rt, (unsigned int)dst->f.i.immediate << 16);
1028 cmp_m32rel_imm32((unsigned int *)(&branch_taken), 0);
1033 mov_m32rel_imm32((void*)(&last_addr), dst->addr + (dst-1)->f.i.immediate*4);
1034 gencheck_interupt((unsigned long long) (dst + (dst-1)->f.i.immediate));
1035 jmp(dst->addr + (dst-1)->f.i.immediate*4);
1039 genupdate_count(dst->addr-4);
1040 mov_m32rel_imm32((void*)(&last_addr), dst->addr + 4);
1041 gencheck_interupt((unsigned long long) (dst + 1));
1047 #if defined(COUNT_INSTR)
1048 inc_m32rel(&instr_count[16]);
1050 #ifdef INTERPRET_BEQL
1051 gencallinterp((unsigned long long)cached_interpreter_table.BEQL, 1);
1053 if (((dst->addr & 0xFFF) == 0xFFC &&
1054 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
1056 gencallinterp((unsigned long long)cached_interpreter_table.BEQL, 1);
1061 free_all_registers();
1066 void gentestl_out(void)
1068 cmp_m32rel_imm32((unsigned int *)(&branch_taken), 0);
1073 mov_m32rel_imm32((void*)(&last_addr), dst->addr + (dst-1)->f.i.immediate*4);
1074 gencheck_interupt_out(dst->addr + (dst-1)->f.i.immediate*4);
1075 mov_m32rel_imm32(&jump_to_address, dst->addr + (dst-1)->f.i.immediate*4);
1077 mov_reg64_imm64(RAX, (unsigned long long) (dst+1));
1078 mov_m64rel_xreg64((unsigned long long *)(&PC), RAX);
1079 mov_reg64_imm64(RAX, (unsigned long long) jump_to_func);
1084 genupdate_count(dst->addr-4);
1085 mov_m32rel_imm32((void*)(&last_addr), dst->addr + 4);
1086 gencheck_interupt((unsigned long long) (dst + 1));
1090 void genbeql_out(void)
1092 #if defined(COUNT_INSTR)
1093 inc_m32rel(&instr_count[16]);
1095 #ifdef INTERPRET_BEQL_OUT
1096 gencallinterp((unsigned long long)cached_interpreter_table.BEQL_OUT, 1);
1098 if (((dst->addr & 0xFFF) == 0xFFC &&
1099 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
1101 gencallinterp((unsigned long long)cached_interpreter_table.BEQL_OUT, 1);
1106 free_all_registers();
1111 void genbeql_idle(void)
1113 #ifdef INTERPRET_BEQL_IDLE
1114 gencallinterp((unsigned long long)cached_interpreter_table.BEQL_IDLE, 1);
1116 if (((dst->addr & 0xFFF) == 0xFFC &&
1117 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
1119 gencallinterp((unsigned long long)cached_interpreter_table.BEQL_IDLE, 1);
1131 #if defined(COUNT_INSTR)
1132 inc_m32rel(&instr_count[17]);
1134 #ifdef INTERPRET_BNEL
1135 gencallinterp((unsigned long long)cached_interpreter_table.BNEL, 1);
1137 if (((dst->addr & 0xFFF) == 0xFFC &&
1138 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
1140 gencallinterp((unsigned long long)cached_interpreter_table.BNEL, 1);
1145 free_all_registers();
1150 void genbnel_out(void)
1152 #if defined(COUNT_INSTR)
1153 inc_m32rel(&instr_count[17]);
1155 #ifdef INTERPRET_BNEL_OUT
1156 gencallinterp((unsigned long long)cached_interpreter_table.BNEL_OUT, 1);
1158 if (((dst->addr & 0xFFF) == 0xFFC &&
1159 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
1161 gencallinterp((unsigned long long)cached_interpreter_table.BNEL_OUT, 1);
1166 free_all_registers();
1171 void genbnel_idle(void)
1173 #ifdef INTERPRET_BNEL_IDLE
1174 gencallinterp((unsigned long long)cached_interpreter_table.BNEL_IDLE, 1);
1176 if (((dst->addr & 0xFFF) == 0xFFC &&
1177 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
1179 gencallinterp((unsigned long long)cached_interpreter_table.BNEL_IDLE, 1);
1191 #if defined(COUNT_INSTR)
1192 inc_m32rel(&instr_count[18]);
1194 #ifdef INTERPRET_BLEZL
1195 gencallinterp((unsigned long long)cached_interpreter_table.BLEZL, 1);
1197 if (((dst->addr & 0xFFF) == 0xFFC &&
1198 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
1200 gencallinterp((unsigned long long)cached_interpreter_table.BLEZL, 1);
1205 free_all_registers();
1210 void genblezl_out(void)
1212 #if defined(COUNT_INSTR)
1213 inc_m32rel(&instr_count[18]);
1215 #ifdef INTERPRET_BLEZL_OUT
1216 gencallinterp((unsigned long long)cached_interpreter_table.BLEZL_OUT, 1);
1218 if (((dst->addr & 0xFFF) == 0xFFC &&
1219 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
1221 gencallinterp((unsigned long long)cached_interpreter_table.BLEZL_OUT, 1);
1226 free_all_registers();
1231 void genblezl_idle(void)
1233 #ifdef INTERPRET_BLEZL_IDLE
1234 gencallinterp((unsigned long long)cached_interpreter_table.BLEZL_IDLE, 1);
1236 if (((dst->addr & 0xFFF) == 0xFFC &&
1237 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
1239 gencallinterp((unsigned long long)cached_interpreter_table.BLEZL_IDLE, 1);
1251 #if defined(COUNT_INSTR)
1252 inc_m32rel(&instr_count[19]);
1254 #ifdef INTERPRET_BGTZL
1255 gencallinterp((unsigned long long)cached_interpreter_table.BGTZL, 1);
1257 if (((dst->addr & 0xFFF) == 0xFFC &&
1258 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
1260 gencallinterp((unsigned long long)cached_interpreter_table.BGTZL, 1);
1265 free_all_registers();
1270 void genbgtzl_out(void)
1272 #if defined(COUNT_INSTR)
1273 inc_m32rel(&instr_count[19]);
1275 #ifdef INTERPRET_BGTZL_OUT
1276 gencallinterp((unsigned long long)cached_interpreter_table.BGTZL_OUT, 1);
1278 if (((dst->addr & 0xFFF) == 0xFFC &&
1279 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
1281 gencallinterp((unsigned long long)cached_interpreter_table.BGTZL_OUT, 1);
1286 free_all_registers();
1291 void genbgtzl_idle(void)
1293 #ifdef INTERPRET_BGTZL_IDLE
1294 gencallinterp((unsigned long long)cached_interpreter_table.BGTZL_IDLE, 1);
1296 if (((dst->addr & 0xFFF) == 0xFFC &&
1297 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
1299 gencallinterp((unsigned long long)cached_interpreter_table.BGTZL_IDLE, 1);
1311 #if defined(COUNT_INSTR)
1312 inc_m32rel(&instr_count[20]);
1314 #ifdef INTERPRET_DADDI
1315 gencallinterp((unsigned long long)cached_interpreter_table.DADDI, 0);
1317 int rs = allocate_register_64((unsigned long long *)dst->f.i.rs);
1318 int rt = allocate_register_64_w((unsigned long long *)dst->f.i.rt);
1320 mov_reg64_reg64(rt, rs);
1321 add_reg64_imm32(rt, (int) dst->f.i.immediate);
1325 void gendaddiu(void)
1327 #ifdef INTERPRET_DADDIU
1328 gencallinterp((unsigned long long)cached_interpreter_table.DADDIU, 0);
1330 int rs = allocate_register_64((unsigned long long *)dst->f.i.rs);
1331 int rt = allocate_register_64_w((unsigned long long *)dst->f.i.rt);
1333 mov_reg64_reg64(rt, rs);
1334 add_reg64_imm32(rt, (int) dst->f.i.immediate);
1340 #if defined(COUNT_INSTR)
1341 inc_m32rel(&instr_count[22]);
1343 gencallinterp((unsigned long long)cached_interpreter_table.LDL, 0);
1348 #if defined(COUNT_INSTR)
1349 inc_m32rel(&instr_count[23]);
1351 gencallinterp((unsigned long long)cached_interpreter_table.LDR, 0);
1356 int gpr1, gpr2, base1, base2 = 0;
1357 #if defined(COUNT_INSTR)
1358 inc_m32rel(&instr_count[24]);
1361 gencallinterp((unsigned long long)cached_interpreter_table.LB, 0);
1363 free_registers_move_start();
1365 ld_register_alloc(&gpr1, &gpr2, &base1, &base2);
1367 mov_reg64_imm64(base1, (unsigned long long) readmemb);
1370 and_reg32_imm32(gpr1, 0xDF800000);
1371 cmp_reg32_imm32(gpr1, 0x80000000);
1375 mov_reg64_imm64(base2, (unsigned long long) read_rdramb);
1376 shr_reg32_imm8(gpr1, 16);
1377 mov_reg64_preg64x8preg64(gpr1, gpr1, base1);
1378 cmp_reg64_reg64(gpr1, base2);
1383 mov_reg64_imm64(gpr1, (unsigned long long) (dst+1));
1384 mov_m64rel_xreg64((unsigned long long *)(&PC), gpr1);
1385 mov_m32rel_xreg32((unsigned int *)(&address), gpr2);
1386 mov_reg64_imm64(gpr1, (unsigned long long) dst->f.i.rt);
1387 mov_m64rel_xreg64((unsigned long long *)(&rdword), gpr1);
1388 shr_reg32_imm8(gpr2, 16);
1389 mov_reg64_preg64x8preg64(gpr2, gpr2, base1);
1391 movsx_xreg32_m8rel(gpr1, (unsigned char *)dst->f.i.rt);
1395 mov_reg64_imm64(base1, (unsigned long long) rdram); // 10
1396 and_reg32_imm32(gpr2, 0x7FFFFF); // 6
1397 xor_reg8_imm8(gpr2, 3); // 4
1398 movsx_reg32_8preg64preg64(gpr1, gpr2, base1); // 4
1400 set_register_state(gpr1, (unsigned int*)dst->f.i.rt, 1, 0);
1406 int gpr1, gpr2, base1, base2 = 0;
1407 #if defined(COUNT_INSTR)
1408 inc_m32rel(&instr_count[25]);
1411 gencallinterp((unsigned long long)cached_interpreter_table.LH, 0);
1413 free_registers_move_start();
1415 ld_register_alloc(&gpr1, &gpr2, &base1, &base2);
1417 mov_reg64_imm64(base1, (unsigned long long) readmemh);
1420 and_reg32_imm32(gpr1, 0xDF800000);
1421 cmp_reg32_imm32(gpr1, 0x80000000);
1425 mov_reg64_imm64(base2, (unsigned long long) read_rdramh);
1426 shr_reg32_imm8(gpr1, 16);
1427 mov_reg64_preg64x8preg64(gpr1, gpr1, base1);
1428 cmp_reg64_reg64(gpr1, base2);
1433 mov_reg64_imm64(gpr1, (unsigned long long) (dst+1));
1434 mov_m64rel_xreg64((unsigned long long *)(&PC), gpr1);
1435 mov_m32rel_xreg32((unsigned int *)(&address), gpr2);
1436 mov_reg64_imm64(gpr1, (unsigned long long) dst->f.i.rt);
1437 mov_m64rel_xreg64((unsigned long long *)(&rdword), gpr1);
1438 shr_reg32_imm8(gpr2, 16);
1439 mov_reg64_preg64x8preg64(gpr2, gpr2, base1);
1441 movsx_xreg32_m16rel(gpr1, (unsigned short *)dst->f.i.rt);
1445 mov_reg64_imm64(base1, (unsigned long long) rdram); // 10
1446 and_reg32_imm32(gpr2, 0x7FFFFF); // 6
1447 xor_reg8_imm8(gpr2, 2); // 4
1448 movsx_reg32_16preg64preg64(gpr1, gpr2, base1); // 4
1450 set_register_state(gpr1, (unsigned int*)dst->f.i.rt, 1, 0);
1456 #if defined(COUNT_INSTR)
1457 inc_m32rel(&instr_count[27]);
1459 gencallinterp((unsigned long long)cached_interpreter_table.LWL, 0);
1464 int gpr1, gpr2, base1, base2 = 0;
1465 #if defined(COUNT_INSTR)
1466 inc_m32rel(&instr_count[26]);
1469 gencallinterp((unsigned long long)cached_interpreter_table.LW, 0);
1471 free_registers_move_start();
1473 ld_register_alloc(&gpr1, &gpr2, &base1, &base2);
1475 mov_reg64_imm64(base1, (unsigned long long) readmem);
1478 and_reg32_imm32(gpr1, 0xDF800000);
1479 cmp_reg32_imm32(gpr1, 0x80000000);
1483 mov_reg64_imm64(base2, (unsigned long long) read_rdram);
1484 shr_reg32_imm8(gpr1, 16);
1485 mov_reg64_preg64x8preg64(gpr1, gpr1, base1);
1486 cmp_reg64_reg64(gpr1, base2);
1490 mov_reg64_imm64(base1, (unsigned long long) rdram); // 10
1491 and_reg32_imm32(gpr2, 0x7FFFFF); // 6
1492 mov_reg32_preg64preg64(gpr1, gpr2, base1); // 3
1493 jmp_imm_short(0); // 2
1496 mov_reg64_imm64(gpr1, (unsigned long long) (dst+1));
1497 mov_m64rel_xreg64((unsigned long long *)(&PC), gpr1);
1498 mov_m32rel_xreg32((unsigned int *)(&address), gpr2);
1499 mov_reg64_imm64(gpr1, (unsigned long long) dst->f.i.rt);
1500 mov_m64rel_xreg64((unsigned long long *)(&rdword), gpr1);
1501 shr_reg32_imm8(gpr2, 16);
1502 mov_reg64_preg64x8preg64(gpr1, gpr2, base1);
1504 mov_xreg32_m32rel(gpr1, (unsigned int *)(dst->f.i.rt));
1508 set_register_state(gpr1, (unsigned int*)dst->f.i.rt, 1, 0); // set gpr1 state as dirty, and bound to r4300 reg RT
1514 int gpr1, gpr2, base1, base2 = 0;
1515 #if defined(COUNT_INSTR)
1516 inc_m32rel(&instr_count[28]);
1518 #ifdef INTERPRET_LBU
1519 gencallinterp((unsigned long long)cached_interpreter_table.LBU, 0);
1521 free_registers_move_start();
1523 ld_register_alloc(&gpr1, &gpr2, &base1, &base2);
1525 mov_reg64_imm64(base1, (unsigned long long) readmemb);
1528 and_reg32_imm32(gpr1, 0xDF800000);
1529 cmp_reg32_imm32(gpr1, 0x80000000);
1533 mov_reg64_imm64(base2, (unsigned long long) read_rdramb);
1534 shr_reg32_imm8(gpr1, 16);
1535 mov_reg64_preg64x8preg64(gpr1, gpr1, base1);
1536 cmp_reg64_reg64(gpr1, base2);
1541 mov_reg64_imm64(gpr1, (unsigned long long) (dst+1));
1542 mov_m64rel_xreg64((unsigned long long *)(&PC), gpr1);
1543 mov_m32rel_xreg32((unsigned int *)(&address), gpr2);
1544 mov_reg64_imm64(gpr1, (unsigned long long) dst->f.i.rt);
1545 mov_m64rel_xreg64((unsigned long long *)(&rdword), gpr1);
1546 shr_reg32_imm8(gpr2, 16);
1547 mov_reg64_preg64x8preg64(gpr2, gpr2, base1);
1549 mov_xreg32_m32rel(gpr1, (unsigned int *)dst->f.i.rt);
1553 mov_reg64_imm64(base1, (unsigned long long) rdram); // 10
1554 and_reg32_imm32(gpr2, 0x7FFFFF); // 6
1555 xor_reg8_imm8(gpr2, 3); // 4
1556 mov_reg32_preg64preg64(gpr1, gpr2, base1); // 3
1558 and_reg32_imm32(gpr1, 0xFF);
1559 set_register_state(gpr1, (unsigned int*)dst->f.i.rt, 1, 0);
1565 int gpr1, gpr2, base1, base2 = 0;
1566 #if defined(COUNT_INSTR)
1567 inc_m32rel(&instr_count[29]);
1569 #ifdef INTERPRET_LHU
1570 gencallinterp((unsigned long long)cached_interpreter_table.LHU, 0);
1572 free_registers_move_start();
1574 ld_register_alloc(&gpr1, &gpr2, &base1, &base2);
1576 mov_reg64_imm64(base1, (unsigned long long) readmemh);
1579 and_reg32_imm32(gpr1, 0xDF800000);
1580 cmp_reg32_imm32(gpr1, 0x80000000);
1584 mov_reg64_imm64(base2, (unsigned long long) read_rdramh);
1585 shr_reg32_imm8(gpr1, 16);
1586 mov_reg64_preg64x8preg64(gpr1, gpr1, base1);
1587 cmp_reg64_reg64(gpr1, base2);
1592 mov_reg64_imm64(gpr1, (unsigned long long) (dst+1));
1593 mov_m64rel_xreg64((unsigned long long *)(&PC), gpr1);
1594 mov_m32rel_xreg32((unsigned int *)(&address), gpr2);
1595 mov_reg64_imm64(gpr1, (unsigned long long) dst->f.i.rt);
1596 mov_m64rel_xreg64((unsigned long long *)(&rdword), gpr1);
1597 shr_reg32_imm8(gpr2, 16);
1598 mov_reg64_preg64x8preg64(gpr2, gpr2, base1);
1600 mov_xreg32_m32rel(gpr1, (unsigned int *)dst->f.i.rt);
1604 mov_reg64_imm64(base1, (unsigned long long) rdram); // 10
1605 and_reg32_imm32(gpr2, 0x7FFFFF); // 6
1606 xor_reg8_imm8(gpr2, 2); // 4
1607 mov_reg32_preg64preg64(gpr1, gpr2, base1); // 3
1609 and_reg32_imm32(gpr1, 0xFFFF);
1610 set_register_state(gpr1, (unsigned int*)dst->f.i.rt, 1, 0);
1616 #if defined(COUNT_INSTR)
1617 inc_m32rel(&instr_count[31]);
1619 gencallinterp((unsigned long long)cached_interpreter_table.LWR, 0);
1624 int gpr1, gpr2, base1, base2 = 0;
1625 #if defined(COUNT_INSTR)
1626 inc_m32rel(&instr_count[30]);
1628 #ifdef INTERPRET_LWU
1629 gencallinterp((unsigned long long)cached_interpreter_table.LWU, 0);
1631 free_registers_move_start();
1633 ld_register_alloc(&gpr1, &gpr2, &base1, &base2);
1635 mov_reg64_imm64(base1, (unsigned long long) readmem);
1638 and_reg32_imm32(gpr1, 0xDF800000);
1639 cmp_reg32_imm32(gpr1, 0x80000000);
1643 mov_reg64_imm64(base2, (unsigned long long) read_rdram);
1644 shr_reg32_imm8(gpr1, 16);
1645 mov_reg64_preg64x8preg64(gpr1, gpr1, base1);
1646 cmp_reg64_reg64(gpr1, base2);
1651 mov_reg64_imm64(gpr1, (unsigned long long) (dst+1));
1652 mov_m64rel_xreg64((unsigned long long *)(&PC), gpr1);
1653 mov_m32rel_xreg32((unsigned int *)(&address), gpr2);
1654 mov_reg64_imm64(gpr1, (unsigned long long) dst->f.i.rt);
1655 mov_m64rel_xreg64((unsigned long long *)(&rdword), gpr1);
1656 shr_reg32_imm8(gpr2, 16);
1657 mov_reg64_preg64x8preg64(gpr2, gpr2, base1);
1659 mov_xreg32_m32rel(gpr1, (unsigned int *)dst->f.i.rt);
1663 mov_reg64_imm64(base1, (unsigned long long) rdram); // 10
1664 and_reg32_imm32(gpr2, 0x7FFFFF); // 6
1665 mov_reg32_preg64preg64(gpr1, gpr2, base1); // 3
1667 set_register_state(gpr1, (unsigned int*)dst->f.i.rt, 1, 1);
1673 #if defined(COUNT_INSTR)
1674 inc_m32rel(&instr_count[32]);
1677 gencallinterp((unsigned long long)cached_interpreter_table.SB, 0);
1679 free_registers_move_start();
1681 mov_xreg8_m8rel(CL, (unsigned char *)dst->f.i.rt);
1682 mov_xreg32_m32rel(EAX, (unsigned int *)dst->f.i.rs);
1683 add_eax_imm32((int)dst->f.i.immediate);
1684 mov_reg32_reg32(EBX, EAX);
1685 mov_reg64_imm64(RSI, (unsigned long long) writememb);
1688 and_eax_imm32(0xDF800000);
1689 cmp_eax_imm32(0x80000000);
1693 mov_reg64_imm64(RDI, (unsigned long long) write_rdramb);
1694 shr_reg32_imm8(EAX, 16);
1695 mov_reg64_preg64x8preg64(RAX, RAX, RSI);
1696 cmp_reg64_reg64(RAX, RDI);
1700 mov_reg64_imm64(RAX, (unsigned long long) (dst+1)); // 10
1701 mov_m64rel_xreg64((unsigned long long *)(&PC), RAX); // 7
1702 mov_m32rel_xreg32((unsigned int *)(&address), EBX); // 7
1703 mov_m8rel_xreg8((unsigned char *)(&cpu_byte), CL); // 7
1704 shr_reg32_imm8(EBX, 16); // 3
1705 mov_reg64_preg64x8preg64(RBX, RBX, RSI); // 4
1706 call_reg64(RBX); // 2
1707 mov_xreg32_m32rel(EAX, (unsigned int *)(&address)); // 7
1708 jmp_imm_short(25); // 2
1710 mov_reg64_imm64(RSI, (unsigned long long) rdram); // 10
1711 mov_reg32_reg32(EAX, EBX); // 2
1712 and_reg32_imm32(EBX, 0x7FFFFF); // 6
1713 xor_reg8_imm8(BL, 3); // 4
1714 mov_preg64preg64_reg8(RBX, RSI, CL); // 3
1716 mov_reg64_imm64(RSI, (unsigned long long) invalid_code);
1717 mov_reg32_reg32(EBX, EAX);
1718 shr_reg32_imm8(EBX, 12);
1719 cmp_preg64preg64_imm8(RBX, RSI, 0);
1722 mov_reg64_imm64(RDI, (unsigned long long) blocks); // 10
1723 mov_reg32_reg32(ECX, EBX); // 2
1724 mov_reg64_preg64x8preg64(RBX, RBX, RDI); // 4
1725 mov_reg64_preg64pimm32(RBX, RBX, (int) offsetof(precomp_block, block)); // 7
1726 mov_reg64_imm64(RDI, (unsigned long long) cached_interpreter_table.NOTCOMPILED); // 10
1727 and_eax_imm32(0xFFF); // 5
1728 shr_reg32_imm8(EAX, 2); // 3
1729 mov_reg32_imm32(EDX, sizeof(precomp_instr)); // 5
1730 mul_reg32(EDX); // 2
1731 mov_reg64_preg64preg64pimm32(RAX, RAX, RBX, (int) offsetof(precomp_instr, ops)); // 8
1732 cmp_reg64_reg64(RAX, RDI); // 3
1734 mov_preg64preg64_imm8(RCX, RSI, 1); // 4
1740 #if defined(COUNT_INSTR)
1741 inc_m32rel(&instr_count[33]);
1744 gencallinterp((unsigned long long)cached_interpreter_table.SH, 0);
1746 free_registers_move_start();
1748 mov_xreg16_m16rel(CX, (unsigned short *)dst->f.i.rt);
1749 mov_xreg32_m32rel(EAX, (unsigned int *)dst->f.i.rs);
1750 add_eax_imm32((int)dst->f.i.immediate);
1751 mov_reg32_reg32(EBX, EAX);
1752 mov_reg64_imm64(RSI, (unsigned long long) writememh);
1755 and_eax_imm32(0xDF800000);
1756 cmp_eax_imm32(0x80000000);
1760 mov_reg64_imm64(RDI, (unsigned long long) write_rdramh);
1761 shr_reg32_imm8(EAX, 16);
1762 mov_reg64_preg64x8preg64(RAX, RAX, RSI);
1763 cmp_reg64_reg64(RAX, RDI);
1767 mov_reg64_imm64(RAX, (unsigned long long) (dst+1)); // 10
1768 mov_m64rel_xreg64((unsigned long long *)(&PC), RAX); // 7
1769 mov_m32rel_xreg32((unsigned int *)(&address), EBX); // 7
1770 mov_m16rel_xreg16((unsigned short *)(&hword), CX); // 8
1771 shr_reg32_imm8(EBX, 16); // 3
1772 mov_reg64_preg64x8preg64(RBX, RBX, RSI); // 4
1773 call_reg64(RBX); // 2
1774 mov_xreg32_m32rel(EAX, (unsigned int *)(&address)); // 7
1775 jmp_imm_short(26); // 2
1777 mov_reg64_imm64(RSI, (unsigned long long) rdram); // 10
1778 mov_reg32_reg32(EAX, EBX); // 2
1779 and_reg32_imm32(EBX, 0x7FFFFF); // 6
1780 xor_reg8_imm8(BL, 2); // 4
1781 mov_preg64preg64_reg16(RBX, RSI, CX); // 4
1783 mov_reg64_imm64(RSI, (unsigned long long) invalid_code);
1784 mov_reg32_reg32(EBX, EAX);
1785 shr_reg32_imm8(EBX, 12);
1786 cmp_preg64preg64_imm8(RBX, RSI, 0);
1789 mov_reg64_imm64(RDI, (unsigned long long) blocks); // 10
1790 mov_reg32_reg32(ECX, EBX); // 2
1791 mov_reg64_preg64x8preg64(RBX, RBX, RDI); // 4
1792 mov_reg64_preg64pimm32(RBX, RBX, (int) offsetof(precomp_block, block)); // 7
1793 mov_reg64_imm64(RDI, (unsigned long long) cached_interpreter_table.NOTCOMPILED); // 10
1794 and_eax_imm32(0xFFF); // 5
1795 shr_reg32_imm8(EAX, 2); // 3
1796 mov_reg32_imm32(EDX, sizeof(precomp_instr)); // 5
1797 mul_reg32(EDX); // 2
1798 mov_reg64_preg64preg64pimm32(RAX, RAX, RBX, (int) offsetof(precomp_instr, ops)); // 8
1799 cmp_reg64_reg64(RAX, RDI); // 3
1801 mov_preg64preg64_imm8(RCX, RSI, 1); // 4
1807 #if defined(COUNT_INSTR)
1808 inc_m32rel(&instr_count[35]);
1810 gencallinterp((unsigned long long)cached_interpreter_table.SWL, 0);
1815 #if defined(COUNT_INSTR)
1816 inc_m32rel(&instr_count[34]);
1819 gencallinterp((unsigned long long)cached_interpreter_table.SW, 0);
1821 free_registers_move_start();
1823 mov_xreg32_m32rel(ECX, (unsigned int *)dst->f.i.rt);
1824 mov_xreg32_m32rel(EAX, (unsigned int *)dst->f.i.rs);
1825 add_eax_imm32((int)dst->f.i.immediate);
1826 mov_reg32_reg32(EBX, EAX);
1827 mov_reg64_imm64(RSI, (unsigned long long) writemem);
1830 and_eax_imm32(0xDF800000);
1831 cmp_eax_imm32(0x80000000);
1835 mov_reg64_imm64(RDI, (unsigned long long) write_rdram);
1836 shr_reg32_imm8(EAX, 16);
1837 mov_reg64_preg64x8preg64(RAX, RAX, RSI);
1838 cmp_reg64_reg64(RAX, RDI);
1842 mov_reg64_imm64(RAX, (unsigned long long) (dst+1)); // 10
1843 mov_m64rel_xreg64((unsigned long long *)(&PC), RAX); // 7
1844 mov_m32rel_xreg32((unsigned int *)(&address), EBX); // 7
1845 mov_m32rel_xreg32((unsigned int *)(&word), ECX); // 7
1846 shr_reg32_imm8(EBX, 16); // 3
1847 mov_reg64_preg64x8preg64(RBX, RBX, RSI); // 4
1848 call_reg64(RBX); // 2
1849 mov_xreg32_m32rel(EAX, (unsigned int *)(&address)); // 7
1850 jmp_imm_short(21); // 2
1852 mov_reg64_imm64(RSI, (unsigned long long) rdram); // 10
1853 mov_reg32_reg32(EAX, EBX); // 2
1854 and_reg32_imm32(EBX, 0x7FFFFF); // 6
1855 mov_preg64preg64_reg32(RBX, RSI, ECX); // 3
1857 mov_reg64_imm64(RSI, (unsigned long long) invalid_code);
1858 mov_reg32_reg32(EBX, EAX);
1859 shr_reg32_imm8(EBX, 12);
1860 cmp_preg64preg64_imm8(RBX, RSI, 0);
1863 mov_reg64_imm64(RDI, (unsigned long long) blocks); // 10
1864 mov_reg32_reg32(ECX, EBX); // 2
1865 mov_reg64_preg64x8preg64(RBX, RBX, RDI); // 4
1866 mov_reg64_preg64pimm32(RBX, RBX, (int) offsetof(precomp_block, block)); // 7
1867 mov_reg64_imm64(RDI, (unsigned long long) cached_interpreter_table.NOTCOMPILED); // 10
1868 and_eax_imm32(0xFFF); // 5
1869 shr_reg32_imm8(EAX, 2); // 3
1870 mov_reg32_imm32(EDX, sizeof(precomp_instr)); // 5
1871 mul_reg32(EDX); // 2
1872 mov_reg64_preg64preg64pimm32(RAX, RAX, RBX, (int) offsetof(precomp_instr, ops)); // 8
1873 cmp_reg64_reg64(RAX, RDI); // 3
1875 mov_preg64preg64_imm8(RCX, RSI, 1); // 4
1881 #if defined(COUNT_INSTR)
1882 inc_m32rel(&instr_count[37]);
1884 gencallinterp((unsigned long long)cached_interpreter_table.SDL, 0);
1889 #if defined(COUNT_INSTR)
1890 inc_m32rel(&instr_count[38]);
1892 gencallinterp((unsigned long long)cached_interpreter_table.SDR, 0);
1897 #if defined(COUNT_INSTR)
1898 inc_m32rel(&instr_count[36]);
1900 gencallinterp((unsigned long long)cached_interpreter_table.SWR, 0);
1903 void gencheck_cop1_unusable(void)
1905 free_registers_move_start();
1907 test_m32rel_imm32((unsigned int*)&Status, 0x20000000);
1911 gencallinterp((unsigned long long)check_cop1_unusable, 0);
1918 #if defined(COUNT_INSTR)
1919 inc_m32rel(&instr_count[39]);
1921 #ifdef INTERPRET_LWC1
1922 gencallinterp((unsigned long long)cached_interpreter_table.LWC1, 0);
1924 gencheck_cop1_unusable();
1926 mov_xreg32_m32rel(EAX, (unsigned int *)(®[dst->f.lf.base]));
1927 add_eax_imm32((int)dst->f.lf.offset);
1928 mov_reg32_reg32(EBX, EAX);
1929 mov_reg64_imm64(RSI, (unsigned long long) readmem);
1932 and_eax_imm32(0xDF800000);
1933 cmp_eax_imm32(0x80000000);
1937 mov_reg64_imm64(RDI, (unsigned long long) read_rdram);
1938 shr_reg32_imm8(EAX, 16);
1939 mov_reg64_preg64x8preg64(RAX, RAX, RSI);
1940 cmp_reg64_reg64(RAX, RDI);
1944 mov_reg64_imm64(RAX, (unsigned long long) (dst+1)); // 10
1945 mov_m64rel_xreg64((unsigned long long *)(&PC), RAX); // 7
1946 mov_m32rel_xreg32((unsigned int *)(&address), EBX); // 7
1947 mov_xreg64_m64rel(RDX, (unsigned long long *)(®_cop1_simple[dst->f.lf.ft])); // 7
1948 mov_m64rel_xreg64((unsigned long long *)(&rdword), RDX); // 7
1949 shr_reg32_imm8(EBX, 16); // 3
1950 mov_reg64_preg64x8preg64(RBX, RBX, RSI); // 4
1951 call_reg64(RBX); // 2
1952 jmp_imm_short(28); // 2
1954 mov_reg64_imm64(RSI, (unsigned long long) rdram); // 10
1955 and_reg32_imm32(EBX, 0x7FFFFF); // 6
1956 mov_reg32_preg64preg64(EAX, RBX, RSI); // 3
1957 mov_xreg64_m64rel(RBX, (unsigned long long *)(®_cop1_simple[dst->f.lf.ft])); // 7
1958 mov_preg64_reg32(RBX, EAX); // 2
1964 #if defined(COUNT_INSTR)
1965 inc_m32rel(&instr_count[40]);
1967 #ifdef INTERPRET_LDC1
1968 gencallinterp((unsigned long long)cached_interpreter_table.LDC1, 0);
1970 gencheck_cop1_unusable();
1972 mov_xreg32_m32rel(EAX, (unsigned int *)(®[dst->f.lf.base]));
1973 add_eax_imm32((int)dst->f.lf.offset);
1974 mov_reg32_reg32(EBX, EAX);
1975 mov_reg64_imm64(RSI, (unsigned long long) readmemd);
1978 and_eax_imm32(0xDF800000);
1979 cmp_eax_imm32(0x80000000);
1983 mov_reg64_imm64(RDI, (unsigned long long) read_rdramd);
1984 shr_reg32_imm8(EAX, 16);
1985 mov_reg64_preg64x8preg64(RAX, RAX, RSI);
1986 cmp_reg64_reg64(RAX, RDI);
1990 mov_reg64_imm64(RAX, (unsigned long long) (dst+1)); // 10
1991 mov_m64rel_xreg64((unsigned long long *)(&PC), RAX); // 7
1992 mov_m32rel_xreg32((unsigned int *)(&address), EBX); // 7
1993 mov_xreg64_m64rel(RDX, (unsigned long long *)(®_cop1_double[dst->f.lf.ft])); // 7
1994 mov_m64rel_xreg64((unsigned long long *)(&rdword), RDX); // 7
1995 shr_reg32_imm8(EBX, 16); // 3
1996 mov_reg64_preg64x8preg64(RBX, RBX, RSI); // 4
1997 call_reg64(RBX); // 2
1998 jmp_imm_short(39); // 2
2000 mov_reg64_imm64(RSI, (unsigned long long) rdram); // 10
2001 and_reg32_imm32(EBX, 0x7FFFFF); // 6
2002 mov_reg64_preg64preg64(RAX, RBX, RSI); // 4
2003 mov_xreg64_m64rel(RBX, (unsigned long long *)(®_cop1_double[dst->f.lf.ft])); // 7
2004 mov_preg64pimm32_reg32(RBX, 4, EAX); // 6
2005 shr_reg64_imm8(RAX, 32); // 4
2006 mov_preg64_reg32(RBX, EAX); // 2
2016 #if defined(COUNT_INSTR)
2017 inc_m32rel(&instr_count[41]);
2020 gencallinterp((unsigned long long)cached_interpreter_table.LD, 0);
2022 free_registers_move_start();
2024 mov_xreg32_m32rel(EAX, (unsigned int *)dst->f.i.rs);
2025 add_eax_imm32((int)dst->f.i.immediate);
2026 mov_reg32_reg32(EBX, EAX);
2027 mov_reg64_imm64(RSI, (unsigned long long) readmemd);
2030 and_eax_imm32(0xDF800000);
2031 cmp_eax_imm32(0x80000000);
2035 mov_reg64_imm64(RDI, (unsigned long long) read_rdramd);
2036 shr_reg32_imm8(EAX, 16);
2037 mov_reg64_preg64x8preg64(RAX, RAX, RSI);
2038 cmp_reg64_reg64(RAX, RDI);
2042 mov_reg64_imm64(RAX, (unsigned long long) (dst+1)); // 10
2043 mov_m64rel_xreg64((unsigned long long *)(&PC), RAX); // 7
2044 mov_m32rel_xreg32((unsigned int *)(&address), EBX); // 7
2045 mov_reg64_imm64(RAX, (unsigned long long) dst->f.i.rt); // 10
2046 mov_m64rel_xreg64((unsigned long long *)(&rdword), RAX); // 7
2047 shr_reg32_imm8(EBX, 16); // 3
2048 mov_reg64_preg64x8preg64(RBX, RBX, RSI); // 4
2049 call_reg64(RBX); // 2
2050 mov_xreg64_m64rel(RAX, (unsigned long long *)(dst->f.i.rt)); // 7
2051 jmp_imm_short(33); // 2
2053 mov_reg64_imm64(RSI, (unsigned long long) rdram); // 10
2054 and_reg32_imm32(EBX, 0x7FFFFF); // 6
2056 mov_reg32_preg64preg64(EAX, RBX, RSI); // 3
2057 mov_reg32_preg64preg64pimm32(EBX, RBX, RSI, 4); // 7
2058 shl_reg64_imm8(RAX, 32); // 4
2059 or_reg64_reg64(RAX, RBX); // 3
2061 set_register_state(RAX, (unsigned int*)dst->f.i.rt, 1, 1);
2067 #if defined(COUNT_INSTR)
2068 inc_m32rel(&instr_count[43]);
2070 #ifdef INTERPRET_SWC1
2071 gencallinterp((unsigned long long)cached_interpreter_table.SWC1, 0);
2073 gencheck_cop1_unusable();
2075 mov_xreg64_m64rel(RDX, (unsigned long long *)(®_cop1_simple[dst->f.lf.ft]));
2076 mov_reg32_preg64(ECX, RDX);
2077 mov_xreg32_m32rel(EAX, (unsigned int *)(®[dst->f.lf.base]));
2078 add_eax_imm32((int)dst->f.lf.offset);
2079 mov_reg32_reg32(EBX, EAX);
2080 mov_reg64_imm64(RSI, (unsigned long long) writemem);
2083 and_eax_imm32(0xDF800000);
2084 cmp_eax_imm32(0x80000000);
2088 mov_reg64_imm64(RDI, (unsigned long long) write_rdram);
2089 shr_reg32_imm8(EAX, 16);
2090 mov_reg64_preg64x8preg64(RAX, RAX, RSI);
2091 cmp_reg64_reg64(RAX, RDI);
2095 mov_reg64_imm64(RAX, (unsigned long long) (dst+1)); // 10
2096 mov_m64rel_xreg64((unsigned long long *)(&PC), RAX); // 7
2097 mov_m32rel_xreg32((unsigned int *)(&address), EBX); // 7
2098 mov_m32rel_xreg32((unsigned int *)(&word), ECX); // 7
2099 shr_reg32_imm8(EBX, 16); // 3
2100 mov_reg64_preg64x8preg64(RBX, RBX, RSI); // 4
2101 call_reg64(RBX); // 2
2102 mov_xreg32_m32rel(EAX, (unsigned int *)(&address)); // 7
2103 jmp_imm_short(21); // 2
2105 mov_reg64_imm64(RSI, (unsigned long long) rdram); // 10
2106 mov_reg32_reg32(EAX, EBX); // 2
2107 and_reg32_imm32(EBX, 0x7FFFFF); // 6
2108 mov_preg64preg64_reg32(RBX, RSI, ECX); // 3
2110 mov_reg64_imm64(RSI, (unsigned long long) invalid_code);
2111 mov_reg32_reg32(EBX, EAX);
2112 shr_reg32_imm8(EBX, 12);
2113 cmp_preg64preg64_imm8(RBX, RSI, 0);
2116 mov_reg64_imm64(RDI, (unsigned long long) blocks); // 10
2117 mov_reg32_reg32(ECX, EBX); // 2
2118 mov_reg64_preg64x8preg64(RBX, RBX, RDI); // 4
2119 mov_reg64_preg64pimm32(RBX, RBX, (int) offsetof(precomp_block, block)); // 7
2120 mov_reg64_imm64(RDI, (unsigned long long) cached_interpreter_table.NOTCOMPILED); // 10
2121 and_eax_imm32(0xFFF); // 5
2122 shr_reg32_imm8(EAX, 2); // 3
2123 mov_reg32_imm32(EDX, sizeof(precomp_instr)); // 5
2124 mul_reg32(EDX); // 2
2125 mov_reg64_preg64preg64pimm32(RAX, RAX, RBX, (int) offsetof(precomp_instr, ops)); // 8
2126 cmp_reg64_reg64(RAX, RDI); // 3
2128 mov_preg64preg64_imm8(RCX, RSI, 1); // 4
2134 #if defined(COUNT_INSTR)
2135 inc_m32rel(&instr_count[44]);
2137 #ifdef INTERPRET_SDC1
2138 gencallinterp((unsigned long long)cached_interpreter_table.SDC1, 0);
2140 gencheck_cop1_unusable();
2142 mov_xreg64_m64rel(RSI, (unsigned long long *)(®_cop1_double[dst->f.lf.ft]));
2143 mov_reg32_preg64(ECX, RSI);
2144 mov_reg32_preg64pimm32(EDX, RSI, 4);
2145 mov_xreg32_m32rel(EAX, (unsigned int *)(®[dst->f.lf.base]));
2146 add_eax_imm32((int)dst->f.lf.offset);
2147 mov_reg32_reg32(EBX, EAX);
2148 mov_reg64_imm64(RSI, (unsigned long long) writememd);
2151 and_eax_imm32(0xDF800000);
2152 cmp_eax_imm32(0x80000000);
2156 mov_reg64_imm64(RDI, (unsigned long long) write_rdramd);
2157 shr_reg32_imm8(EAX, 16);
2158 mov_reg64_preg64x8preg64(RAX, RAX, RSI);
2159 cmp_reg64_reg64(RAX, RDI);
2163 mov_reg64_imm64(RAX, (unsigned long long) (dst+1)); // 10
2164 mov_m64rel_xreg64((unsigned long long *)(&PC), RAX); // 7
2165 mov_m32rel_xreg32((unsigned int *)(&address), EBX); // 7
2166 mov_m32rel_xreg32((unsigned int *)(&dword), ECX); // 7
2167 mov_m32rel_xreg32((unsigned int *)(&dword)+1, EDX); // 7
2168 shr_reg32_imm8(EBX, 16); // 3
2169 mov_reg64_preg64x8preg64(RBX, RBX, RSI); // 4
2170 call_reg64(RBX); // 2
2171 mov_xreg32_m32rel(EAX, (unsigned int *)(&address)); // 7
2172 jmp_imm_short(28); // 2
2174 mov_reg64_imm64(RSI, (unsigned long long) rdram); // 10
2175 mov_reg32_reg32(EAX, EBX); // 2
2176 and_reg32_imm32(EBX, 0x7FFFFF); // 6
2177 mov_preg64preg64pimm32_reg32(RBX, RSI, 4, ECX); // 7
2178 mov_preg64preg64_reg32(RBX, RSI, EDX); // 3
2180 mov_reg64_imm64(RSI, (unsigned long long) invalid_code);
2181 mov_reg32_reg32(EBX, EAX);
2182 shr_reg32_imm8(EBX, 12);
2183 cmp_preg64preg64_imm8(RBX, RSI, 0);
2186 mov_reg64_imm64(RDI, (unsigned long long) blocks); // 10
2187 mov_reg32_reg32(ECX, EBX); // 2
2188 mov_reg64_preg64x8preg64(RBX, RBX, RDI); // 4
2189 mov_reg64_preg64pimm32(RBX, RBX, (int) offsetof(precomp_block, block)); // 7
2190 mov_reg64_imm64(RDI, (unsigned long long) cached_interpreter_table.NOTCOMPILED); // 10
2191 and_eax_imm32(0xFFF); // 5
2192 shr_reg32_imm8(EAX, 2); // 3
2193 mov_reg32_imm32(EDX, sizeof(precomp_instr)); // 5
2194 mul_reg32(EDX); // 2
2195 mov_reg64_preg64preg64pimm32(RAX, RAX, RBX, (int) offsetof(precomp_instr, ops)); // 8
2196 cmp_reg64_reg64(RAX, RDI); // 3
2198 mov_preg64preg64_imm8(RCX, RSI, 1); // 4
2204 #if defined(COUNT_INSTR)
2205 inc_m32rel(&instr_count[45]);
2208 gencallinterp((unsigned long long)cached_interpreter_table.SD, 0);
2210 free_registers_move_start();
2212 mov_xreg32_m32rel(ECX, (unsigned int *)dst->f.i.rt);
2213 mov_xreg32_m32rel(EDX, ((unsigned int *)dst->f.i.rt)+1);
2214 mov_xreg32_m32rel(EAX, (unsigned int *)dst->f.i.rs);
2215 add_eax_imm32((int)dst->f.i.immediate);
2216 mov_reg32_reg32(EBX, EAX);
2217 mov_reg64_imm64(RSI, (unsigned long long) writememd);
2220 and_eax_imm32(0xDF800000);
2221 cmp_eax_imm32(0x80000000);
2225 mov_reg64_imm64(RDI, (unsigned long long) write_rdramd);
2226 shr_reg32_imm8(EAX, 16);
2227 mov_reg64_preg64x8preg64(RAX, RAX, RSI);
2228 cmp_reg64_reg64(RAX, RDI);
2232 mov_reg64_imm64(RAX, (unsigned long long) (dst+1)); // 10
2233 mov_m64rel_xreg64((unsigned long long *)(&PC), RAX); // 7
2234 mov_m32rel_xreg32((unsigned int *)(&address), EBX); // 7
2235 mov_m32rel_xreg32((unsigned int *)(&dword), ECX); // 7
2236 mov_m32rel_xreg32((unsigned int *)(&dword)+1, EDX); // 7
2237 shr_reg32_imm8(EBX, 16); // 3
2238 mov_reg64_preg64x8preg64(RBX, RBX, RSI); // 4
2239 call_reg64(RBX); // 2
2240 mov_xreg32_m32rel(EAX, (unsigned int *)(&address)); // 7
2241 jmp_imm_short(28); // 2
2243 mov_reg64_imm64(RSI, (unsigned long long) rdram); // 10
2244 mov_reg32_reg32(EAX, EBX); // 2
2245 and_reg32_imm32(EBX, 0x7FFFFF); // 6
2246 mov_preg64preg64pimm32_reg32(RBX, RSI, 4, ECX); // 7
2247 mov_preg64preg64_reg32(RBX, RSI, EDX); // 3
2249 mov_reg64_imm64(RSI, (unsigned long long) invalid_code);
2250 mov_reg32_reg32(EBX, EAX);
2251 shr_reg32_imm8(EBX, 12);
2252 cmp_preg64preg64_imm8(RBX, RSI, 0);
2255 mov_reg64_imm64(RDI, (unsigned long long) blocks); // 10
2256 mov_reg32_reg32(ECX, EBX); // 2
2257 mov_reg64_preg64x8preg64(RBX, RBX, RDI); // 4
2258 mov_reg64_preg64pimm32(RBX, RBX, (int) offsetof(precomp_block, block)); // 7
2259 mov_reg64_imm64(RDI, (unsigned long long) cached_interpreter_table.NOTCOMPILED); // 10
2260 and_eax_imm32(0xFFF); // 5
2261 shr_reg32_imm8(EAX, 2); // 3
2262 mov_reg32_imm32(EDX, sizeof(precomp_instr)); // 5
2263 mul_reg32(EDX); // 2
2264 mov_reg64_preg64preg64pimm32(RAX, RAX, RBX, (int) offsetof(precomp_instr, ops)); // 8
2265 cmp_reg64_reg64(RAX, RDI); // 3
2267 mov_preg64preg64_imm8(RCX, RSI, 1); // 4
2273 #if defined(COUNT_INSTR)
2274 inc_m32rel(&instr_count[42]);
2276 gencallinterp((unsigned long long)cached_interpreter_table.LL, 0);
2281 #if defined(COUNT_INSTR)
2282 inc_m32rel(&instr_count[46]);
2284 gencallinterp((unsigned long long)cached_interpreter_table.SC, 0);