static INLINE uint8 RdMem(unsigned int A)
{
- // notaz: try to avoid lookup of every address at least for ROM and RAM areas
- // I've verified that if ARead[0xfff0] points to CartBR, it is always normal ROM read.
-#if 0
- if ((A&0x8000)/* && ARead[0xfff0] == CartBR*/) {
- return (_DB=Page[A>>11][A]);
- }
-#endif
-#if 0 // enabling this causes 4fps slowdown. Why?
- if ((A&0xe000) == 0) { // RAM area (always 0-0x1fff)
- return (_DB=RAM[A&0x7FF]);
- }
-#endif
- _DB=ARead[A](A);
+ int _DB1=ARead[A](A);
#ifdef DEBUG_ASM_6502
+ //_DB=_DB1;
//printf("a == %x, pc == %x\n", A, _PC);
- if (A >= 0x2000 && A != _PC && A != _PC - 1 && A != _PC + 1) {
- dreads[dread_count_c++] = _DB;
+ if (A >= 0x2000) {
+ if (A == _PC || A == _PC - 1 || A == _PC + 1) {
+ //printf("fr: %02x\n", _DB1);
+ }
+ _DB=_DB1;
+ }
+ if (A >= 0x2000 && A != _PC - 1) {
+ dreads[dread_count_c++] = _DB1;
if (dread_count_c > 4) { printf("dread_count out of range\n"); exit(1); }
}
+#else
+ _DB=_DB1;
#endif
- return _DB;
+ return _DB1;
}
static INLINE void WrMem(unsigned int A, uint8 V)
static INLINE uint8 RdRAM(unsigned int A)
{
- return((_DB=RAM[A]));
+ //return((_DB=RAM[A]));
+ int _DB1=RAM[A];
+#ifndef DEBUG_ASM_6502
+ _DB=_DB1;
+#endif
+ return _DB1;
}
static INLINE void WrRAM(unsigned int A, uint8 V)
static uint8 CycTable[256] =
{
+/* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
/*0x00*/ 7,6,2,8,3,3,5,5,3,2,2,2,4,4,6,6,
/*0x10*/ 2,5,2,8,4,4,6,6,2,4,2,7,4,4,7,7,
/*0x20*/ 6,6,2,8,3,3,5,5,4,2,2,2,4,4,6,6,
void FASTAPASS(1) X6502_IRQBegin_c(int w)
{
+ dprintf("IRQB %02x",w);
_IRQlow|=w;
}
void FASTAPASS(1) X6502_IRQEnd_c(int w)
{
+ dprintf("IRQE %02x",w);
_IRQlow&=~w;
}
_IRQlow|=FCEU_IQTEMP;
}
-void TriggerNMINSF_c(void)
-{
- ADDCYC(7);
- PUSH(_PC>>8);
- PUSH(_PC);
- PUSH((_P&~B_FLAG)|(U_FLAG));
- _PC=0x3800;
-}
-
void TriggerNMI_c(void)
{
_IRQlow|=FCEU_IQNMI;
{
_PC=RdMem(0xFFFC);
_PC|=RdMem(0xFFFD)<<8;
- if(FCEUGameInfo.type==GIT_NSF) _PC=0x3830;
_jammed=0;
_PI=_P=I_FLAG;
}
}
}
_PI=_P;
+#ifdef DEBUG_ASM_6502
+ b1=RdMem(_PC++); _PC--;
+#else
b1=RdMem(_PC);
+#endif
ADDCYC(CycTable[b1]);
temp=_tcount;
{
extern uint8 SIRQStat;
SIRQStat|=0x80;
- X6502_IRQBegin_c(FCEU_IQDPCM);
+ X6502_IRQBegin(FCEU_IQDPCM);
}
}
}